RTEMS 6.1-rc1
MIMXRT1052.h
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1/*
2** ###################################################################
3** Processors: MIMXRT1052CVJ5B
4** MIMXRT1052CVL5B
5** MIMXRT1052DVJ6B
6** MIMXRT1052DVL6B
7**
8** Compilers: Freescale C/C++ for Embedded ARM
9** GNU C Compiler
10** IAR ANSI C/C++ Compiler for ARM
11** Keil ARM C/C++ Compiler
12** MCUXpresso Compiler
13**
14** Reference manual: IMXRT1050RM Rev.5, 07/2021 | IMXRT1050SRM Rev.2
15** Version: rev. 1.4, 2021-08-10
16** Build: b221010
17**
18** Abstract:
19** CMSIS Peripheral Access Layer for MIMXRT1052
20**
21** Copyright 1997-2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2022 NXP
23** All rights reserved.
24**
25** SPDX-License-Identifier: BSD-3-Clause
26**
27** http: www.nxp.com
28** mail: support@nxp.com
29**
30** Revisions:
31** - rev. 0.1 (2017-01-10)
32** Initial version.
33** - rev. 1.0 (2018-09-21)
34** Update interrupt vector table and dma request source.
35** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
36** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
37** - rev. 1.1 (2018-11-16)
38** Update header files to align with IMXRT1050RM Rev.1.
39** - rev. 1.2 (2018-11-27)
40** Update header files to align with IMXRT1050RM Rev.2.1.
41** - rev. 1.3 (2019-04-29)
42** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
43** - rev. 1.4 (2021-08-10)
44** Update header files to align with IMXRT1050RM Rev.5.
45**
46** ###################################################################
47*/
48
58#ifndef _MIMXRT1052_H_
59#define _MIMXRT1052_H_
63#define MCU_MEM_MAP_VERSION 0x0100U
65#define MCU_MEM_MAP_VERSION_MINOR 0x0004U
66
67
68/* ----------------------------------------------------------------------------
69 -- Interrupt vector numbers
70 ---------------------------------------------------------------------------- */
71
78#define NUMBER_OF_INT_VECTORS 168
80typedef enum IRQn {
81 /* Auxiliary constants */
82 NotAvail_IRQn = -128,
84 /* Core interrupts */
85 NonMaskableInt_IRQn = -14,
86 HardFault_IRQn = -13,
87 MemoryManagement_IRQn = -12,
88 BusFault_IRQn = -11,
89 UsageFault_IRQn = -10,
90 SVCall_IRQn = -5,
91 DebugMonitor_IRQn = -4,
92 PendSV_IRQn = -2,
93 SysTick_IRQn = -1,
95 /* Device specific interrupts */
96 DMA0_DMA16_IRQn = 0,
97 DMA1_DMA17_IRQn = 1,
98 DMA2_DMA18_IRQn = 2,
99 DMA3_DMA19_IRQn = 3,
100 DMA4_DMA20_IRQn = 4,
101 DMA5_DMA21_IRQn = 5,
102 DMA6_DMA22_IRQn = 6,
103 DMA7_DMA23_IRQn = 7,
104 DMA8_DMA24_IRQn = 8,
105 DMA9_DMA25_IRQn = 9,
106 DMA10_DMA26_IRQn = 10,
107 DMA11_DMA27_IRQn = 11,
108 DMA12_DMA28_IRQn = 12,
109 DMA13_DMA29_IRQn = 13,
110 DMA14_DMA30_IRQn = 14,
111 DMA15_DMA31_IRQn = 15,
112 DMA_ERROR_IRQn = 16,
113 CTI0_ERROR_IRQn = 17,
114 CTI1_ERROR_IRQn = 18,
115 CORE_IRQn = 19,
116 LPUART1_IRQn = 20,
117 LPUART2_IRQn = 21,
118 LPUART3_IRQn = 22,
119 LPUART4_IRQn = 23,
120 LPUART5_IRQn = 24,
121 LPUART6_IRQn = 25,
122 LPUART7_IRQn = 26,
123 LPUART8_IRQn = 27,
124 LPI2C1_IRQn = 28,
125 LPI2C2_IRQn = 29,
126 LPI2C3_IRQn = 30,
127 LPI2C4_IRQn = 31,
128 LPSPI1_IRQn = 32,
129 LPSPI2_IRQn = 33,
130 LPSPI3_IRQn = 34,
131 LPSPI4_IRQn = 35,
132 CAN1_IRQn = 36,
133 CAN2_IRQn = 37,
134 FLEXRAM_IRQn = 38,
135 KPP_IRQn = 39,
136 TSC_DIG_IRQn = 40,
137 GPR_IRQ_IRQn = 41,
138 LCDIF_IRQn = 42,
139 CSI_IRQn = 43,
140 PXP_IRQn = 44,
141 WDOG2_IRQn = 45,
142 SNVS_HP_WRAPPER_IRQn = 46,
143 SNVS_HP_WRAPPER_TZ_IRQn = 47,
144 SNVS_LP_WRAPPER_IRQn = 48,
145 CSU_IRQn = 49,
146 DCP_IRQn = 50,
147 DCP_VMI_IRQn = 51,
148 Reserved68_IRQn = 52,
149 TRNG_IRQn = 53,
150 SJC_IRQn = 54,
151 BEE_IRQn = 55,
152 SAI1_IRQn = 56,
153 SAI2_IRQn = 57,
154 SAI3_RX_IRQn = 58,
155 SAI3_TX_IRQn = 59,
156 SPDIF_IRQn = 60,
157 PMU_EVENT_IRQn = 61,
158 Reserved78_IRQn = 62,
159 TEMP_LOW_HIGH_IRQn = 63,
160 TEMP_PANIC_IRQn = 64,
161 USB_PHY1_IRQn = 65,
162 USB_PHY2_IRQn = 66,
163 ADC1_IRQn = 67,
164 ADC2_IRQn = 68,
165 DCDC_IRQn = 69,
166 Reserved86_IRQn = 70,
167 Reserved87_IRQn = 71,
168 GPIO1_INT0_IRQn = 72,
169 GPIO1_INT1_IRQn = 73,
170 GPIO1_INT2_IRQn = 74,
171 GPIO1_INT3_IRQn = 75,
172 GPIO1_INT4_IRQn = 76,
173 GPIO1_INT5_IRQn = 77,
174 GPIO1_INT6_IRQn = 78,
175 GPIO1_INT7_IRQn = 79,
176 GPIO1_Combined_0_15_IRQn = 80,
177 GPIO1_Combined_16_31_IRQn = 81,
178 GPIO2_Combined_0_15_IRQn = 82,
179 GPIO2_Combined_16_31_IRQn = 83,
180 GPIO3_Combined_0_15_IRQn = 84,
181 GPIO3_Combined_16_31_IRQn = 85,
182 GPIO4_Combined_0_15_IRQn = 86,
183 GPIO4_Combined_16_31_IRQn = 87,
184 GPIO5_Combined_0_15_IRQn = 88,
185 GPIO5_Combined_16_31_IRQn = 89,
186 FLEXIO1_IRQn = 90,
187 FLEXIO2_IRQn = 91,
188 WDOG1_IRQn = 92,
189 RTWDOG_IRQn = 93,
190 EWM_IRQn = 94,
191 CCM_1_IRQn = 95,
192 CCM_2_IRQn = 96,
193 GPC_IRQn = 97,
194 SRC_IRQn = 98,
195 Reserved115_IRQn = 99,
196 GPT1_IRQn = 100,
197 GPT2_IRQn = 101,
198 PWM1_0_IRQn = 102,
199 PWM1_1_IRQn = 103,
200 PWM1_2_IRQn = 104,
201 PWM1_3_IRQn = 105,
202 PWM1_FAULT_IRQn = 106,
203 Reserved123_IRQn = 107,
204 FLEXSPI_IRQn = 108,
205 SEMC_IRQn = 109,
206 USDHC1_IRQn = 110,
207 USDHC2_IRQn = 111,
208 USB_OTG2_IRQn = 112,
209 USB_OTG1_IRQn = 113,
210 ENET_IRQn = 114,
211 ENET_1588_Timer_IRQn = 115,
212 XBAR1_IRQ_0_1_IRQn = 116,
213 XBAR1_IRQ_2_3_IRQn = 117,
214 ADC_ETC_IRQ0_IRQn = 118,
215 ADC_ETC_IRQ1_IRQn = 119,
216 ADC_ETC_IRQ2_IRQn = 120,
217 ADC_ETC_ERROR_IRQ_IRQn = 121,
218 PIT_IRQn = 122,
219 ACMP1_IRQn = 123,
220 ACMP2_IRQn = 124,
221 ACMP3_IRQn = 125,
222 ACMP4_IRQn = 126,
223 Reserved143_IRQn = 127,
224 Reserved144_IRQn = 128,
225 ENC1_IRQn = 129,
226 ENC2_IRQn = 130,
227 ENC3_IRQn = 131,
228 ENC4_IRQn = 132,
229 TMR1_IRQn = 133,
230 TMR2_IRQn = 134,
231 TMR3_IRQn = 135,
232 TMR4_IRQn = 136,
233 PWM2_0_IRQn = 137,
234 PWM2_1_IRQn = 138,
235 PWM2_2_IRQn = 139,
236 PWM2_3_IRQn = 140,
237 PWM2_FAULT_IRQn = 141,
238 PWM3_0_IRQn = 142,
239 PWM3_1_IRQn = 143,
240 PWM3_2_IRQn = 144,
241 PWM3_3_IRQn = 145,
242 PWM3_FAULT_IRQn = 146,
243 PWM4_0_IRQn = 147,
244 PWM4_1_IRQn = 148,
245 PWM4_2_IRQn = 149,
246 PWM4_3_IRQn = 150,
247 PWM4_FAULT_IRQn = 151
248} IRQn_Type;
249 /* end of group Interrupt_vector_numbers */
253
254
255/* ----------------------------------------------------------------------------
256 -- Cortex M7 Core Configuration
257 ---------------------------------------------------------------------------- */
258
264#define __MPU_PRESENT 1
265#define __ICACHE_PRESENT 1
266#define __DCACHE_PRESENT 1
267#define __DTCM_PRESENT 1
268#define __NVIC_PRIO_BITS 4
269#define __Vendor_SysTickConfig 0
270#define __FPU_PRESENT 1
272#include "core_cm7.h" /* Core Peripheral Access Layer */
273#include "system_MIMXRT1052.h" /* Device specific configuration file */
274 /* end of group Cortex_Core_Configuration */
278
279
280/* ----------------------------------------------------------------------------
281 -- Mapping Information
282 ---------------------------------------------------------------------------- */
283
294/*******************************************************************************
295 * Definitions
296*******************************************************************************/
297
303typedef enum _iomuxc_sw_mux_ctl_pad
304{
305 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U,
306 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U,
307 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U,
308 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U,
309 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U,
310 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U,
311 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U,
312 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U,
313 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U,
314 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U,
315 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U,
316 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U,
317 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U,
318 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U,
319 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U,
320 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U,
321 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U,
322 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U,
323 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U,
324 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U,
325 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U,
326 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U,
327 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U,
328 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U,
329 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U,
330 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U,
331 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U,
332 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U,
333 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U,
334 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U,
335 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U,
336 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U,
337 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U,
338 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U,
339 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U,
340 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U,
341 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U,
342 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U,
343 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U,
344 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U,
345 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U,
346 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U,
347 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U,
348 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U,
349 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U,
350 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U,
351 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U,
352 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U,
353 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U,
354 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U,
355 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U,
356 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U,
357 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U,
358 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U,
359 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U,
360 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U,
361 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U,
362 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U,
363 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U,
364 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U,
365 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U,
366 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U,
367 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U,
368 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U,
369 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U,
370 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U,
371 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U,
372 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U,
373 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U,
374 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U,
375 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U,
376 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U,
377 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U,
378 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U,
379 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U,
380 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U,
381 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U,
382 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U,
383 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U,
384 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U,
385 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U,
386 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U,
387 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U,
388 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U,
389 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U,
390 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U,
391 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U,
392 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U,
393 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U,
394 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U,
395 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U,
396 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U,
397 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U,
398 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U,
399 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U,
400 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U,
401 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U,
402 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U,
403 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U,
404 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U,
405 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U,
406 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U,
407 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U,
408 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U,
409 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U,
410 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U,
411 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U,
412 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U,
413 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U,
414 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U,
415 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U,
416 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U,
417 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U,
418 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U,
419 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U,
420 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U,
421 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U,
422 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U,
423 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U,
424 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U,
425 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U,
426 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U,
427 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U,
428 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U,
429} iomuxc_sw_mux_ctl_pad_t;
430
431/* @} */
432
437/*******************************************************************************
438 * Definitions
439*******************************************************************************/
440
446typedef enum _iomuxc_sw_pad_ctl_pad
447{
448 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U,
449 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U,
450 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U,
451 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U,
452 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U,
453 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U,
454 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U,
455 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U,
456 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U,
457 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U,
458 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U,
459 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U,
460 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U,
461 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U,
462 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U,
463 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U,
464 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U,
465 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U,
466 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U,
467 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U,
468 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U,
469 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U,
470 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U,
471 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U,
472 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U,
473 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U,
474 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U,
475 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U,
476 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U,
477 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U,
478 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U,
479 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U,
480 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U,
481 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U,
482 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U,
483 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U,
484 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U,
485 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U,
486 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U,
487 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U,
488 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U,
489 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U,
490 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U,
491 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U,
492 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U,
493 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U,
494 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U,
495 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U,
496 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U,
497 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U,
498 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U,
499 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U,
500 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U,
501 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U,
502 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U,
503 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U,
504 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U,
505 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U,
506 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U,
507 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U,
508 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U,
509 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U,
510 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U,
511 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U,
512 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U,
513 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U,
514 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U,
515 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U,
516 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U,
517 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U,
518 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U,
519 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U,
520 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U,
521 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U,
522 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U,
523 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U,
524 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U,
525 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U,
526 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U,
527 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U,
528 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U,
529 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U,
530 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U,
531 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U,
532 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U,
533 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U,
534 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U,
535 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U,
536 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U,
537 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U,
538 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U,
539 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U,
540 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U,
541 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U,
542 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U,
543 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U,
544 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U,
545 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U,
546 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U,
547 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U,
548 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U,
549 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U,
550 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U,
551 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U,
552 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U,
553 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U,
554 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U,
555 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U,
556 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U,
557 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U,
558 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U,
559 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U,
560 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U,
561 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U,
562 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U,
563 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U,
564 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U,
565 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U,
566 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U,
567 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U,
568 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U,
569 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U,
570 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U,
571 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U,
572} iomuxc_sw_pad_ctl_pad_t;
573
574/* @} */
575
581typedef enum _iomuxc_select_input
582{
583 kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U,
584 kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U,
585 kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U,
586 kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U,
587 kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U,
588 kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U,
589 kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U,
590 kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U,
591 kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U,
592 kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U,
593 kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U,
594 kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U,
595 kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U,
596 kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U,
597 kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U,
598 kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U,
599 kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U,
600 kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U,
601 kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U,
602 kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U,
603 kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U,
604 kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U,
605 kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U,
606 kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U,
607 kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U,
608 kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U,
609 kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U,
610 kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U,
611 kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U,
612 kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U,
613 kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U,
614 kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U,
615 kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U,
616 kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U,
617 kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U,
618 kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U,
619 kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U,
620 kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U,
621 kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U,
622 kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U,
623 kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U,
624 kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U,
625 kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U,
626 kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U,
627 kIOMUXC_FLEXSPI_A_DQS_SELECT_INPUT = 44U,
628 kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT = 45U,
629 kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT = 46U,
630 kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT = 47U,
631 kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT = 48U,
632 kIOMUXC_FLEXSPI_B_DATA0_SELECT_INPUT = 49U,
633 kIOMUXC_FLEXSPI_B_DATA1_SELECT_INPUT = 50U,
634 kIOMUXC_FLEXSPI_B_DATA2_SELECT_INPUT = 51U,
635 kIOMUXC_FLEXSPI_B_DATA3_SELECT_INPUT = 52U,
636 kIOMUXC_FLEXSPI_A_SCK_SELECT_INPUT = 53U,
637 kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U,
638 kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U,
639 kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U,
640 kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U,
641 kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U,
642 kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U,
643 kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U,
644 kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U,
645 kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U,
646 kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U,
647 kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U,
648 kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U,
649 kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U,
650 kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U,
651 kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U,
652 kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U,
653 kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U,
654 kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U,
655 kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U,
656 kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U,
657 kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U,
658 kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U,
659 kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U,
660 kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U,
661 kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U,
662 kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U,
663 kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U,
664 kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U,
665 kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U,
666 kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U,
667 kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U,
668 kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U,
669 kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U,
670 kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U,
671 kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U,
672 kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U,
673 kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U,
674 kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U,
675 kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U,
676 kIOMUXC_NMI_SELECT_INPUT = 93U,
677 kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U,
678 kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U,
679 kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U,
680 kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U,
681 kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U,
682 kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U,
683 kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U,
684 kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U,
685 kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U,
686 kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U,
687 kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U,
688 kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U,
689 kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U,
690 kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U,
691 kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U,
692 kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U,
693 kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U,
694 kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U,
695 kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U,
696 kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U,
697 kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U,
698 kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U,
699 kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U,
700 kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U,
701 kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U,
702 kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U,
703 kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U,
704 kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U,
705 kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U,
706 kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U,
707 kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U,
708 kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U,
709 kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U,
710 kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U,
711 kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U,
712 kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U,
713 kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U,
714 kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U,
715 kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U,
716 kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U,
717 kIOMUXC_XBAR_INOUT02_SELECT_INPUT = 134U,
718 kIOMUXC_XBAR_INOUT03_SELECT_INPUT = 135U,
719 kIOMUXC_XBAR_INOUT04_SELECT_INPUT = 136U,
720 kIOMUXC_XBAR_INOUT05_SELECT_INPUT = 137U,
721 kIOMUXC_XBAR_INOUT06_SELECT_INPUT = 138U,
722 kIOMUXC_XBAR_INOUT07_SELECT_INPUT = 139U,
723 kIOMUXC_XBAR_INOUT08_SELECT_INPUT = 140U,
724 kIOMUXC_XBAR_INOUT09_SELECT_INPUT = 141U,
725 kIOMUXC_XBAR_INOUT17_SELECT_INPUT = 142U,
726 kIOMUXC_XBAR_INOUT18_SELECT_INPUT = 143U,
727 kIOMUXC_XBAR_INOUT20_SELECT_INPUT = 144U,
728 kIOMUXC_XBAR_INOUT22_SELECT_INPUT = 145U,
729 kIOMUXC_XBAR_INOUT23_SELECT_INPUT = 146U,
730 kIOMUXC_XBAR_INOUT24_SELECT_INPUT = 147U,
731 kIOMUXC_XBAR_INOUT14_SELECT_INPUT = 148U,
732 kIOMUXC_XBAR_INOUT15_SELECT_INPUT = 149U,
733 kIOMUXC_XBAR_INOUT16_SELECT_INPUT = 150U,
734 kIOMUXC_XBAR_INOUT25_SELECT_INPUT = 151U,
735 kIOMUXC_XBAR_INOUT19_SELECT_INPUT = 152U,
736 kIOMUXC_XBAR_INOUT21_SELECT_INPUT = 153U,
737} iomuxc_select_input_t;
738
739typedef enum _xbar_input_signal
740{
741 kXBARA1_InputLogicLow = 0|0x100U,
742 kXBARA1_InputLogicHigh = 1|0x100U,
743 kXBARA1_InputIomuxXbarIn02 = 2|0x100U,
744 kXBARA1_InputIomuxXbarIn03 = 3|0x100U,
745 kXBARA1_InputIomuxXbarInout04 = 4|0x100U,
746 kXBARA1_InputIomuxXbarInout05 = 5|0x100U,
747 kXBARA1_InputIomuxXbarInout06 = 6|0x100U,
748 kXBARA1_InputIomuxXbarInout07 = 7|0x100U,
749 kXBARA1_InputIomuxXbarInout08 = 8|0x100U,
750 kXBARA1_InputIomuxXbarInout09 = 9|0x100U,
751 kXBARA1_InputIomuxXbarInout10 = 10|0x100U,
752 kXBARA1_InputIomuxXbarInout11 = 11|0x100U,
753 kXBARA1_InputIomuxXbarInout12 = 12|0x100U,
754 kXBARA1_InputIomuxXbarInout13 = 13|0x100U,
755 kXBARA1_InputIomuxXbarInout14 = 14|0x100U,
756 kXBARA1_InputIomuxXbarInout15 = 15|0x100U,
757 kXBARA1_InputIomuxXbarInout16 = 16|0x100U,
758 kXBARA1_InputIomuxXbarInout17 = 17|0x100U,
759 kXBARA1_InputIomuxXbarInout18 = 18|0x100U,
760 kXBARA1_InputIomuxXbarInout19 = 19|0x100U,
761 kXBARA1_InputIomuxXbarIn20 = 20|0x100U,
762 kXBARA1_InputIomuxXbarIn21 = 21|0x100U,
763 kXBARA1_InputIomuxXbarIn22 = 22|0x100U,
764 kXBARA1_InputIomuxXbarIn23 = 23|0x100U,
765 kXBARA1_InputIomuxXbarIn24 = 24|0x100U,
766 kXBARA1_InputIomuxXbarIn25 = 25|0x100U,
767 kXBARA1_InputAcmp1Out = 26|0x100U,
768 kXBARA1_InputAcmp2Out = 27|0x100U,
769 kXBARA1_InputAcmp3Out = 28|0x100U,
770 kXBARA1_InputAcmp4Out = 29|0x100U,
771 kXBARA1_InputRESERVED30 = 30|0x100U,
772 kXBARA1_InputRESERVED31 = 31|0x100U,
773 kXBARA1_InputQtimer3Tmr0Output = 32|0x100U,
774 kXBARA1_InputQtimer3Tmr1Output = 33|0x100U,
775 kXBARA1_InputQtimer3Tmr2Output = 34|0x100U,
776 kXBARA1_InputQtimer3Tmr3Output = 35|0x100U,
777 kXBARA1_InputQtimer4Tmr0Output = 36|0x100U,
778 kXBARA1_InputQtimer4Tmr1Output = 37|0x100U,
779 kXBARA1_InputQtimer4Tmr2Output = 38|0x100U,
780 kXBARA1_InputQtimer4Tmr3Output = 39|0x100U,
781 kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U,
782 kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U,
783 kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U,
784 kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U,
785 kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U,
786 kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U,
787 kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U,
788 kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U,
789 kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U,
790 kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U,
791 kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U,
792 kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U,
793 kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U,
794 kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U,
795 kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U,
796 kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U,
797 kXBARA1_InputPitTrigger0 = 56|0x100U,
798 kXBARA1_InputPitTrigger1 = 57|0x100U,
799 kXBARA1_InputPitTrigger2 = 58|0x100U,
800 kXBARA1_InputPitTrigger3 = 59|0x100U,
801 kXBARA1_InputEnc1PosMatch = 60|0x100U,
802 kXBARA1_InputEnc2PosMatch = 61|0x100U,
803 kXBARA1_InputEnc3PosMatch = 62|0x100U,
804 kXBARA1_InputEnc4PosMatch = 63|0x100U,
805 kXBARA1_InputDmaDone0 = 64|0x100U,
806 kXBARA1_InputDmaDone1 = 65|0x100U,
807 kXBARA1_InputDmaDone2 = 66|0x100U,
808 kXBARA1_InputDmaDone3 = 67|0x100U,
809 kXBARA1_InputDmaDone4 = 68|0x100U,
810 kXBARA1_InputDmaDone5 = 69|0x100U,
811 kXBARA1_InputDmaDone6 = 70|0x100U,
812 kXBARA1_InputDmaDone7 = 71|0x100U,
813 kXBARA1_InputAoi1Out0 = 72|0x100U,
814 kXBARA1_InputAoi1Out1 = 73|0x100U,
815 kXBARA1_InputAoi1Out2 = 74|0x100U,
816 kXBARA1_InputAoi1Out3 = 75|0x100U,
817 kXBARA1_InputAoi2Out0 = 76|0x100U,
818 kXBARA1_InputAoi2Out1 = 77|0x100U,
819 kXBARA1_InputAoi2Out2 = 78|0x100U,
820 kXBARA1_InputAoi2Out3 = 79|0x100U,
821 kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U,
822 kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U,
823 kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U,
824 kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U,
825 kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U,
826 kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U,
827 kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U,
828 kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U,
829 kXBARB2_InputLogicLow = 0|0x200U,
830 kXBARB2_InputLogicHigh = 1|0x200U,
831 kXBARB2_InputRESERVED2 = 2|0x200U,
832 kXBARB2_InputRESERVED3 = 3|0x200U,
833 kXBARB2_InputRESERVED4 = 4|0x200U,
834 kXBARB2_InputRESERVED5 = 5|0x200U,
835 kXBARB2_InputAcmp1Out = 6|0x200U,
836 kXBARB2_InputAcmp2Out = 7|0x200U,
837 kXBARB2_InputAcmp3Out = 8|0x200U,
838 kXBARB2_InputAcmp4Out = 9|0x200U,
839 kXBARB2_InputRESERVED10 = 10|0x200U,
840 kXBARB2_InputRESERVED11 = 11|0x200U,
841 kXBARB2_InputQtimer3Tmr0Output = 12|0x200U,
842 kXBARB2_InputQtimer3Tmr1Output = 13|0x200U,
843 kXBARB2_InputQtimer3Tmr2Output = 14|0x200U,
844 kXBARB2_InputQtimer3Tmr3Output = 15|0x200U,
845 kXBARB2_InputQtimer4Tmr0Output = 16|0x200U,
846 kXBARB2_InputQtimer4Tmr1Output = 17|0x200U,
847 kXBARB2_InputQtimer4Tmr2Output = 18|0x200U,
848 kXBARB2_InputQtimer4Tmr3Output = 19|0x200U,
849 kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U,
850 kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U,
851 kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U,
852 kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U,
853 kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U,
854 kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U,
855 kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U,
856 kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U,
857 kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U,
858 kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U,
859 kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U,
860 kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U,
861 kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U,
862 kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U,
863 kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U,
864 kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U,
865 kXBARB2_InputPitTrigger0 = 36|0x200U,
866 kXBARB2_InputPitTrigger1 = 37|0x200U,
867 kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U,
868 kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U,
869 kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U,
870 kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U,
871 kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U,
872 kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U,
873 kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U,
874 kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U,
875 kXBARB2_InputEnc1PosMatch = 46|0x200U,
876 kXBARB2_InputEnc2PosMatch = 47|0x200U,
877 kXBARB2_InputEnc3PosMatch = 48|0x200U,
878 kXBARB2_InputEnc4PosMatch = 49|0x200U,
879 kXBARB2_InputDmaDone0 = 50|0x200U,
880 kXBARB2_InputDmaDone1 = 51|0x200U,
881 kXBARB2_InputDmaDone2 = 52|0x200U,
882 kXBARB2_InputDmaDone3 = 53|0x200U,
883 kXBARB2_InputDmaDone4 = 54|0x200U,
884 kXBARB2_InputDmaDone5 = 55|0x200U,
885 kXBARB2_InputDmaDone6 = 56|0x200U,
886 kXBARB2_InputDmaDone7 = 57|0x200U,
887 kXBARB3_InputLogicLow = 0|0x300U,
888 kXBARB3_InputLogicHigh = 1|0x300U,
889 kXBARB3_InputRESERVED2 = 2|0x300U,
890 kXBARB3_InputRESERVED3 = 3|0x300U,
891 kXBARB3_InputRESERVED4 = 4|0x300U,
892 kXBARB3_InputRESERVED5 = 5|0x300U,
893 kXBARB3_InputAcmp1Out = 6|0x300U,
894 kXBARB3_InputAcmp2Out = 7|0x300U,
895 kXBARB3_InputAcmp3Out = 8|0x300U,
896 kXBARB3_InputAcmp4Out = 9|0x300U,
897 kXBARB3_InputRESERVED10 = 10|0x300U,
898 kXBARB3_InputRESERVED11 = 11|0x300U,
899 kXBARB3_InputQtimer3Tmr0Output = 12|0x300U,
900 kXBARB3_InputQtimer3Tmr1Output = 13|0x300U,
901 kXBARB3_InputQtimer3Tmr2Output = 14|0x300U,
902 kXBARB3_InputQtimer3Tmr3Output = 15|0x300U,
903 kXBARB3_InputQtimer4Tmr0Output = 16|0x300U,
904 kXBARB3_InputQtimer4Tmr1Output = 17|0x300U,
905 kXBARB3_InputQtimer4Tmr2Output = 18|0x300U,
906 kXBARB3_InputQtimer4Tmr3Output = 19|0x300U,
907 kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U,
908 kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U,
909 kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U,
910 kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U,
911 kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U,
912 kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U,
913 kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U,
914 kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U,
915 kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U,
916 kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U,
917 kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U,
918 kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U,
919 kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U,
920 kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U,
921 kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U,
922 kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U,
923 kXBARB3_InputPitTrigger0 = 36|0x300U,
924 kXBARB3_InputPitTrigger1 = 37|0x300U,
925 kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U,
926 kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U,
927 kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U,
928 kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U,
929 kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U,
930 kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U,
931 kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U,
932 kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U,
933 kXBARB3_InputEnc1PosMatch = 46|0x300U,
934 kXBARB3_InputEnc2PosMatch = 47|0x300U,
935 kXBARB3_InputEnc3PosMatch = 48|0x300U,
936 kXBARB3_InputEnc4PosMatch = 49|0x300U,
937 kXBARB3_InputDmaDone0 = 50|0x300U,
938 kXBARB3_InputDmaDone1 = 51|0x300U,
939 kXBARB3_InputDmaDone2 = 52|0x300U,
940 kXBARB3_InputDmaDone3 = 53|0x300U,
941 kXBARB3_InputDmaDone4 = 54|0x300U,
942 kXBARB3_InputDmaDone5 = 55|0x300U,
943 kXBARB3_InputDmaDone6 = 56|0x300U,
944 kXBARB3_InputDmaDone7 = 57|0x300U,
945} xbar_input_signal_t;
946
947typedef enum _xbar_output_signal
948{
949 kXBARA1_OutputDmaChMuxReq30 = 0|0x100U,
950 kXBARA1_OutputDmaChMuxReq31 = 1|0x100U,
951 kXBARA1_OutputDmaChMuxReq94 = 2|0x100U,
952 kXBARA1_OutputDmaChMuxReq95 = 3|0x100U,
953 kXBARA1_OutputIomuxXbarInout04 = 4|0x100U,
954 kXBARA1_OutputIomuxXbarInout05 = 5|0x100U,
955 kXBARA1_OutputIomuxXbarInout06 = 6|0x100U,
956 kXBARA1_OutputIomuxXbarInout07 = 7|0x100U,
957 kXBARA1_OutputIomuxXbarInout08 = 8|0x100U,
958 kXBARA1_OutputIomuxXbarInout09 = 9|0x100U,
959 kXBARA1_OutputIomuxXbarInout10 = 10|0x100U,
960 kXBARA1_OutputIomuxXbarInout11 = 11|0x100U,
961 kXBARA1_OutputIomuxXbarInout12 = 12|0x100U,
962 kXBARA1_OutputIomuxXbarInout13 = 13|0x100U,
963 kXBARA1_OutputIomuxXbarInout14 = 14|0x100U,
964 kXBARA1_OutputIomuxXbarInout15 = 15|0x100U,
965 kXBARA1_OutputIomuxXbarInout16 = 16|0x100U,
966 kXBARA1_OutputIomuxXbarInout17 = 17|0x100U,
967 kXBARA1_OutputIomuxXbarInout18 = 18|0x100U,
968 kXBARA1_OutputIomuxXbarInout19 = 19|0x100U,
969 kXBARA1_OutputAcmp1Sample = 20|0x100U,
970 kXBARA1_OutputAcmp2Sample = 21|0x100U,
971 kXBARA1_OutputAcmp3Sample = 22|0x100U,
972 kXBARA1_OutputAcmp4Sample = 23|0x100U,
973 kXBARA1_OutputRESERVED24 = 24|0x100U,
974 kXBARA1_OutputRESERVED25 = 25|0x100U,
975 kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U,
976 kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U,
977 kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U,
978 kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U,
979 kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U,
980 kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U,
981 kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U,
982 kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U,
983 kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U,
984 kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U,
985 kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U,
986 kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U,
987 kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U,
988 kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U,
989 kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U,
990 kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U,
991 kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U,
992 kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U,
993 kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U,
994 kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U,
995 kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U,
996 kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U,
997 kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U,
998 kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U,
999 kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U,
1000 kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U,
1001 kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U,
1002 kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U,
1003 kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U,
1004 kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U,
1005 kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U,
1006 kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U,
1007 kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U,
1008 kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U,
1009 kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U,
1010 kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U,
1011 kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U,
1012 kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U,
1013 kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U,
1014 kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U,
1015 kXBARA1_OutputEnc1PhaseAInput = 66|0x100U,
1016 kXBARA1_OutputEnc1PhaseBInput = 67|0x100U,
1017 kXBARA1_OutputEnc1Index = 68|0x100U,
1018 kXBARA1_OutputEnc1Home = 69|0x100U,
1019 kXBARA1_OutputEnc1Trigger = 70|0x100U,
1020 kXBARA1_OutputEnc2PhaseAInput = 71|0x100U,
1021 kXBARA1_OutputEnc2PhaseBInput = 72|0x100U,
1022 kXBARA1_OutputEnc2Index = 73|0x100U,
1023 kXBARA1_OutputEnc2Home = 74|0x100U,
1024 kXBARA1_OutputEnc2Trigger = 75|0x100U,
1025 kXBARA1_OutputEnc3PhaseAInput = 76|0x100U,
1026 kXBARA1_OutputEnc3PhaseBInput = 77|0x100U,
1027 kXBARA1_OutputEnc3Index = 78|0x100U,
1028 kXBARA1_OutputEnc3Home = 79|0x100U,
1029 kXBARA1_OutputEnc3Trigger = 80|0x100U,
1030 kXBARA1_OutputEnc4PhaseAInput = 81|0x100U,
1031 kXBARA1_OutputEnc4PhaseBInput = 82|0x100U,
1032 kXBARA1_OutputEnc4Index = 83|0x100U,
1033 kXBARA1_OutputEnc4Home = 84|0x100U,
1034 kXBARA1_OutputEnc4Trigger = 85|0x100U,
1035 kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U,
1036 kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U,
1037 kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U,
1038 kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U,
1039 kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U,
1040 kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U,
1041 kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U,
1042 kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U,
1043 kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U,
1044 kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U,
1045 kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U,
1046 kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U,
1047 kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U,
1048 kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U,
1049 kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U,
1050 kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U,
1051 kXBARA1_OutputEwmEwmIn = 102|0x100U,
1052 kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U,
1053 kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U,
1054 kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U,
1055 kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U,
1056 kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U,
1057 kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U,
1058 kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U,
1059 kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U,
1060 kXBARA1_OutputLpi2c1TrgInput = 111|0x100U,
1061 kXBARA1_OutputLpi2c2TrgInput = 112|0x100U,
1062 kXBARA1_OutputLpi2c3TrgInput = 113|0x100U,
1063 kXBARA1_OutputLpi2c4TrgInput = 114|0x100U,
1064 kXBARA1_OutputLpspi1TrgInput = 115|0x100U,
1065 kXBARA1_OutputLpspi2TrgInput = 116|0x100U,
1066 kXBARA1_OutputLpspi3TrgInput = 117|0x100U,
1067 kXBARA1_OutputLpspi4TrgInput = 118|0x100U,
1068 kXBARA1_OutputLpuart1TrgInput = 119|0x100U,
1069 kXBARA1_OutputLpuart2TrgInput = 120|0x100U,
1070 kXBARA1_OutputLpuart3TrgInput = 121|0x100U,
1071 kXBARA1_OutputLpuart4TrgInput = 122|0x100U,
1072 kXBARA1_OutputLpuart5TrgInput = 123|0x100U,
1073 kXBARA1_OutputLpuart6TrgInput = 124|0x100U,
1074 kXBARA1_OutputLpuart7TrgInput = 125|0x100U,
1075 kXBARA1_OutputLpuart8TrgInput = 126|0x100U,
1076 kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U,
1077 kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U,
1078 kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U,
1079 kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U,
1080 kXBARB2_OutputAoi1In00 = 0|0x200U,
1081 kXBARB2_OutputAoi1In01 = 1|0x200U,
1082 kXBARB2_OutputAoi1In02 = 2|0x200U,
1083 kXBARB2_OutputAoi1In03 = 3|0x200U,
1084 kXBARB2_OutputAoi1In04 = 4|0x200U,
1085 kXBARB2_OutputAoi1In05 = 5|0x200U,
1086 kXBARB2_OutputAoi1In06 = 6|0x200U,
1087 kXBARB2_OutputAoi1In07 = 7|0x200U,
1088 kXBARB2_OutputAoi1In08 = 8|0x200U,
1089 kXBARB2_OutputAoi1In09 = 9|0x200U,
1090 kXBARB2_OutputAoi1In10 = 10|0x200U,
1091 kXBARB2_OutputAoi1In11 = 11|0x200U,
1092 kXBARB2_OutputAoi1In12 = 12|0x200U,
1093 kXBARB2_OutputAoi1In13 = 13|0x200U,
1094 kXBARB2_OutputAoi1In14 = 14|0x200U,
1095 kXBARB2_OutputAoi1In15 = 15|0x200U,
1096 kXBARB3_OutputAoi2In00 = 0|0x300U,
1097 kXBARB3_OutputAoi2In01 = 1|0x300U,
1098 kXBARB3_OutputAoi2In02 = 2|0x300U,
1099 kXBARB3_OutputAoi2In03 = 3|0x300U,
1100 kXBARB3_OutputAoi2In04 = 4|0x300U,
1101 kXBARB3_OutputAoi2In05 = 5|0x300U,
1102 kXBARB3_OutputAoi2In06 = 6|0x300U,
1103 kXBARB3_OutputAoi2In07 = 7|0x300U,
1104 kXBARB3_OutputAoi2In08 = 8|0x300U,
1105 kXBARB3_OutputAoi2In09 = 9|0x300U,
1106 kXBARB3_OutputAoi2In10 = 10|0x300U,
1107 kXBARB3_OutputAoi2In11 = 11|0x300U,
1108 kXBARB3_OutputAoi2In12 = 12|0x300U,
1109 kXBARB3_OutputAoi2In13 = 13|0x300U,
1110 kXBARB3_OutputAoi2In14 = 14|0x300U,
1111 kXBARB3_OutputAoi2In15 = 15|0x300U,
1112} xbar_output_signal_t;
1113
1119/*******************************************************************************
1120 * Definitions
1121 ******************************************************************************/
1122
1130typedef enum _dma_request_source
1131{
1132 kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U,
1133 kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U,
1134 kDmaRequestMuxLPUART1Tx = 2|0x100U,
1135 kDmaRequestMuxLPUART1Rx = 3|0x100U,
1136 kDmaRequestMuxLPUART3Tx = 4|0x100U,
1137 kDmaRequestMuxLPUART3Rx = 5|0x100U,
1138 kDmaRequestMuxLPUART5Tx = 6|0x100U,
1139 kDmaRequestMuxLPUART5Rx = 7|0x100U,
1140 kDmaRequestMuxLPUART7Tx = 8|0x100U,
1141 kDmaRequestMuxLPUART7Rx = 9|0x100U,
1142 kDmaRequestMuxCSI = 12|0x100U,
1143 kDmaRequestMuxLPSPI1Rx = 13|0x100U,
1144 kDmaRequestMuxLPSPI1Tx = 14|0x100U,
1145 kDmaRequestMuxLPSPI3Rx = 15|0x100U,
1146 kDmaRequestMuxLPSPI3Tx = 16|0x100U,
1147 kDmaRequestMuxLPI2C1 = 17|0x100U,
1148 kDmaRequestMuxLPI2C3 = 18|0x100U,
1149 kDmaRequestMuxSai1Rx = 19|0x100U,
1150 kDmaRequestMuxSai1Tx = 20|0x100U,
1151 kDmaRequestMuxSai2Rx = 21|0x100U,
1152 kDmaRequestMuxSai2Tx = 22|0x100U,
1153 kDmaRequestMuxADC_ETC = 23|0x100U,
1154 kDmaRequestMuxADC1 = 24|0x100U,
1155 kDmaRequestMuxACMP1 = 25|0x100U,
1156 kDmaRequestMuxACMP3 = 26|0x100U,
1157 kDmaRequestMuxFlexSPIRx = 28|0x100U,
1158 kDmaRequestMuxFlexSPITx = 29|0x100U,
1159 kDmaRequestMuxXBAR1Request0 = 30|0x100U,
1160 kDmaRequestMuxXBAR1Request1 = 31|0x100U,
1161 kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U,
1162 kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U,
1163 kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U,
1164 kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U,
1165 kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U,
1166 kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U,
1167 kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U,
1168 kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U,
1169 kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U,
1170 kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U,
1171 kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U,
1172 kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U,
1173 kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U,
1174 kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U,
1175 kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U,
1176 kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U,
1177 kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U,
1178 kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U,
1179 kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U,
1180 kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U,
1181 kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U,
1182 kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U,
1183 kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U,
1184 kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U,
1185 kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U,
1186 kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U,
1187 kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U,
1188 kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U,
1189 kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U,
1190 kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U,
1191 kDmaRequestMuxLPUART2Tx = 66|0x100U,
1192 kDmaRequestMuxLPUART2Rx = 67|0x100U,
1193 kDmaRequestMuxLPUART4Tx = 68|0x100U,
1194 kDmaRequestMuxLPUART4Rx = 69|0x100U,
1195 kDmaRequestMuxLPUART6Tx = 70|0x100U,
1196 kDmaRequestMuxLPUART6Rx = 71|0x100U,
1197 kDmaRequestMuxLPUART8Tx = 72|0x100U,
1198 kDmaRequestMuxLPUART8Rx = 73|0x100U,
1199 kDmaRequestMuxPxp = 75|0x100U,
1200 kDmaRequestMuxLCDIF = 76|0x100U,
1201 kDmaRequestMuxLPSPI2Rx = 77|0x100U,
1202 kDmaRequestMuxLPSPI2Tx = 78|0x100U,
1203 kDmaRequestMuxLPSPI4Rx = 79|0x100U,
1204 kDmaRequestMuxLPSPI4Tx = 80|0x100U,
1205 kDmaRequestMuxLPI2C2 = 81|0x100U,
1206 kDmaRequestMuxLPI2C4 = 82|0x100U,
1207 kDmaRequestMuxSai3Rx = 83|0x100U,
1208 kDmaRequestMuxSai3Tx = 84|0x100U,
1209 kDmaRequestMuxSpdifRx = 85|0x100U,
1210 kDmaRequestMuxSpdifTx = 86|0x100U,
1211 kDmaRequestMuxADC2 = 88|0x100U,
1212 kDmaRequestMuxACMP2 = 89|0x100U,
1213 kDmaRequestMuxACMP4 = 90|0x100U,
1214 kDmaRequestMuxEnetTimer0 = 92|0x100U,
1215 kDmaRequestMuxEnetTimer1 = 93|0x100U,
1216 kDmaRequestMuxXBAR1Request2 = 94|0x100U,
1217 kDmaRequestMuxXBAR1Request3 = 95|0x100U,
1218 kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U,
1219 kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U,
1220 kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U,
1221 kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U,
1222 kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U,
1223 kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U,
1224 kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U,
1225 kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U,
1226 kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U,
1227 kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U,
1228 kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U,
1229 kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U,
1230 kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U,
1231 kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U,
1232 kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U,
1233 kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U,
1234 kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U,
1235 kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U,
1236 kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U,
1237 kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U,
1238 kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U,
1239 kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U,
1240 kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U,
1241 kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U,
1242 kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U,
1243 kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U,
1244 kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U,
1245 kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U,
1246} dma_request_source_t;
1247
1248/* @} */
1249
1250 /* end of group Mapping_Information */
1254
1255
1256/* ----------------------------------------------------------------------------
1257 -- Device Peripheral Access Layer
1258 ---------------------------------------------------------------------------- */
1259
1266/*
1267** Start of section using anonymous unions
1268*/
1269
1270#if defined(__ARMCC_VERSION)
1271 #if (__ARMCC_VERSION >= 6010050)
1272 #pragma clang diagnostic push
1273 #else
1274 #pragma push
1275 #pragma anon_unions
1276 #endif
1277#elif defined(__CWCC__)
1278 #pragma push
1279 #pragma cpp_extensions on
1280#elif defined(__GNUC__)
1281 /* anonymous unions are enabled by default */
1282#elif defined(__IAR_SYSTEMS_ICC__)
1283 #pragma language=extended
1284#else
1285 #error Not supported compiler type
1286#endif
1287
1288/* ----------------------------------------------------------------------------
1289 -- ADC Peripheral Access Layer
1290 ---------------------------------------------------------------------------- */
1291
1298typedef struct {
1299 __IO uint32_t HC[8];
1300 __I uint32_t HS;
1301 __I uint32_t R[8];
1302 __IO uint32_t CFG;
1303 __IO uint32_t GC;
1304 __IO uint32_t GS;
1305 __IO uint32_t CV;
1306 __IO uint32_t OFS;
1307 __IO uint32_t CAL;
1308} ADC_Type;
1309
1310/* ----------------------------------------------------------------------------
1311 -- ADC Register Masks
1312 ---------------------------------------------------------------------------- */
1313
1322#define ADC_HC_ADCH_MASK (0x1FU)
1323#define ADC_HC_ADCH_SHIFT (0U)
1335#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
1336
1337#define ADC_HC_AIEN_MASK (0x80U)
1338#define ADC_HC_AIEN_SHIFT (7U)
1343#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
1346/* The count of ADC_HC */
1347#define ADC_HC_COUNT (8U)
1348
1352#define ADC_HS_COCO0_MASK (0x1U)
1353#define ADC_HS_COCO0_SHIFT (0U)
1356#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
1357
1358#define ADC_HS_COCO1_MASK (0x2U)
1359#define ADC_HS_COCO1_SHIFT (1U)
1362#define ADC_HS_COCO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO1_SHIFT)) & ADC_HS_COCO1_MASK)
1363
1364#define ADC_HS_COCO2_MASK (0x4U)
1365#define ADC_HS_COCO2_SHIFT (2U)
1366#define ADC_HS_COCO2(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO2_SHIFT)) & ADC_HS_COCO2_MASK)
1367
1368#define ADC_HS_COCO3_MASK (0x8U)
1369#define ADC_HS_COCO3_SHIFT (3U)
1370#define ADC_HS_COCO3(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO3_SHIFT)) & ADC_HS_COCO3_MASK)
1371
1372#define ADC_HS_COCO4_MASK (0x10U)
1373#define ADC_HS_COCO4_SHIFT (4U)
1374#define ADC_HS_COCO4(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO4_SHIFT)) & ADC_HS_COCO4_MASK)
1375
1376#define ADC_HS_COCO5_MASK (0x20U)
1377#define ADC_HS_COCO5_SHIFT (5U)
1378#define ADC_HS_COCO5(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO5_SHIFT)) & ADC_HS_COCO5_MASK)
1379
1380#define ADC_HS_COCO6_MASK (0x40U)
1381#define ADC_HS_COCO6_SHIFT (6U)
1382#define ADC_HS_COCO6(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO6_SHIFT)) & ADC_HS_COCO6_MASK)
1383
1384#define ADC_HS_COCO7_MASK (0x80U)
1385#define ADC_HS_COCO7_SHIFT (7U)
1386#define ADC_HS_COCO7(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO7_SHIFT)) & ADC_HS_COCO7_MASK)
1392#define ADC_R_CDATA_MASK (0xFFFU)
1393#define ADC_R_CDATA_SHIFT (0U)
1396#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
1399/* The count of ADC_R */
1400#define ADC_R_COUNT (8U)
1401
1405#define ADC_CFG_ADICLK_MASK (0x3U)
1406#define ADC_CFG_ADICLK_SHIFT (0U)
1413#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
1414
1415#define ADC_CFG_MODE_MASK (0xCU)
1416#define ADC_CFG_MODE_SHIFT (2U)
1423#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
1424
1425#define ADC_CFG_ADLSMP_MASK (0x10U)
1426#define ADC_CFG_ADLSMP_SHIFT (4U)
1431#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
1432
1433#define ADC_CFG_ADIV_MASK (0x60U)
1434#define ADC_CFG_ADIV_SHIFT (5U)
1441#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
1442
1443#define ADC_CFG_ADLPC_MASK (0x80U)
1444#define ADC_CFG_ADLPC_SHIFT (7U)
1449#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
1450
1451#define ADC_CFG_ADSTS_MASK (0x300U)
1452#define ADC_CFG_ADSTS_SHIFT (8U)
1459#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
1460
1461#define ADC_CFG_ADHSC_MASK (0x400U)
1462#define ADC_CFG_ADHSC_SHIFT (10U)
1467#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
1468
1469#define ADC_CFG_REFSEL_MASK (0x1800U)
1470#define ADC_CFG_REFSEL_SHIFT (11U)
1477#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1478
1479#define ADC_CFG_ADTRG_MASK (0x2000U)
1480#define ADC_CFG_ADTRG_SHIFT (13U)
1485#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
1486
1487#define ADC_CFG_AVGS_MASK (0xC000U)
1488#define ADC_CFG_AVGS_SHIFT (14U)
1495#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
1496
1497#define ADC_CFG_OVWREN_MASK (0x10000U)
1498#define ADC_CFG_OVWREN_SHIFT (16U)
1503#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
1509#define ADC_GC_ADACKEN_MASK (0x1U)
1510#define ADC_GC_ADACKEN_SHIFT (0U)
1515#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
1516
1517#define ADC_GC_DMAEN_MASK (0x2U)
1518#define ADC_GC_DMAEN_SHIFT (1U)
1523#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
1524
1525#define ADC_GC_ACREN_MASK (0x4U)
1526#define ADC_GC_ACREN_SHIFT (2U)
1531#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
1532
1533#define ADC_GC_ACFGT_MASK (0x8U)
1534#define ADC_GC_ACFGT_SHIFT (3U)
1541#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
1542
1543#define ADC_GC_ACFE_MASK (0x10U)
1544#define ADC_GC_ACFE_SHIFT (4U)
1549#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
1550
1551#define ADC_GC_AVGE_MASK (0x20U)
1552#define ADC_GC_AVGE_SHIFT (5U)
1557#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
1558
1559#define ADC_GC_ADCO_MASK (0x40U)
1560#define ADC_GC_ADCO_SHIFT (6U)
1565#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
1566
1567#define ADC_GC_CAL_MASK (0x80U)
1568#define ADC_GC_CAL_SHIFT (7U)
1571#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
1577#define ADC_GS_ADACT_MASK (0x1U)
1578#define ADC_GS_ADACT_SHIFT (0U)
1583#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
1584
1585#define ADC_GS_CALF_MASK (0x2U)
1586#define ADC_GS_CALF_SHIFT (1U)
1591#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
1592
1593#define ADC_GS_AWKST_MASK (0x4U)
1594#define ADC_GS_AWKST_SHIFT (2U)
1599#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
1605#define ADC_CV_CV1_MASK (0xFFFU)
1606#define ADC_CV_CV1_SHIFT (0U)
1609#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
1610
1611#define ADC_CV_CV2_MASK (0xFFF0000U)
1612#define ADC_CV_CV2_SHIFT (16U)
1615#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
1621#define ADC_OFS_OFS_MASK (0xFFFU)
1622#define ADC_OFS_OFS_SHIFT (0U)
1625#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
1626
1627#define ADC_OFS_SIGN_MASK (0x1000U)
1628#define ADC_OFS_SIGN_SHIFT (12U)
1633#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
1639#define ADC_CAL_CAL_CODE_MASK (0xFU)
1640#define ADC_CAL_CAL_CODE_SHIFT (0U)
1643#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) /* end of group ADC_Register_Masks */
1650
1651
1652/* ADC - Peripheral instance base addresses */
1654#define ADC1_BASE (0x400C4000u)
1656#define ADC1 ((ADC_Type *)ADC1_BASE)
1658#define ADC2_BASE (0x400C8000u)
1660#define ADC2 ((ADC_Type *)ADC2_BASE)
1662#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
1664#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
1666#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
1667 /* end of group ADC_Peripheral_Access_Layer */
1671
1672
1673/* ----------------------------------------------------------------------------
1674 -- ADC_ETC Peripheral Access Layer
1675 ---------------------------------------------------------------------------- */
1676
1683typedef struct {
1684 __IO uint32_t CTRL;
1685 __IO uint32_t DONE0_1_IRQ;
1686 __IO uint32_t DONE2_3_ERR_IRQ;
1687 __IO uint32_t DMA_CTRL;
1688 struct { /* offset: 0x10, array step: 0x28 */
1689 __IO uint32_t TRIGn_CTRL;
1690 __IO uint32_t TRIGn_COUNTER;
1691 __IO uint32_t TRIGn_CHAIN_1_0;
1692 __IO uint32_t TRIGn_CHAIN_3_2;
1693 __IO uint32_t TRIGn_CHAIN_5_4;
1694 __IO uint32_t TRIGn_CHAIN_7_6;
1695 __I uint32_t TRIGn_RESULT_1_0;
1696 __I uint32_t TRIGn_RESULT_3_2;
1697 __I uint32_t TRIGn_RESULT_5_4;
1698 __I uint32_t TRIGn_RESULT_7_6;
1699 } TRIG[8];
1700} ADC_ETC_Type;
1701
1702/* ----------------------------------------------------------------------------
1703 -- ADC_ETC Register Masks
1704 ---------------------------------------------------------------------------- */
1705
1714#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
1715#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
1723#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
1724
1725#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
1726#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
1731#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
1732
1733#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
1734#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
1735#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
1736
1737#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
1738#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
1743#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
1744
1745#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
1746#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
1747#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
1748
1749#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
1750#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
1751#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
1752
1753#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
1754#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
1759#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
1760
1761#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
1762#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
1767#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
1768
1769#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
1770#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
1775#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
1781#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
1782#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
1787#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
1788
1789#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
1790#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
1795#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
1796
1797#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
1798#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
1803#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
1804
1805#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
1806#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
1811#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
1812
1813#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
1814#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
1819#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
1820
1821#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
1822#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
1827#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
1828
1829#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
1830#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
1835#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
1836
1837#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
1838#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
1843#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
1844
1845#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
1846#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
1851#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
1852
1853#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
1854#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
1859#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
1860
1861#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
1862#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
1867#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
1868
1869#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
1870#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
1875#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
1876
1877#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
1878#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
1883#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
1884
1885#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
1886#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
1891#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
1892
1893#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
1894#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
1899#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
1900
1901#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
1902#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
1907#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
1913#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
1914#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
1919#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK)
1920
1921#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
1922#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
1927#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK)
1928
1929#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
1930#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
1935#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK)
1936
1937#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
1938#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
1943#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK)
1944
1945#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
1946#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
1951#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK)
1952
1953#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
1954#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
1959#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK)
1960
1961#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
1962#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
1967#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK)
1968
1969#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
1970#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
1975#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK)
1976
1977#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
1978#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
1983#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK)
1984
1985#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
1986#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
1991#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK)
1992
1993#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
1994#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
1999#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK)
2000
2001#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
2002#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
2007#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK)
2008
2009#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
2010#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
2015#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK)
2016
2017#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
2018#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
2023#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK)
2024
2025#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
2026#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
2031#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK)
2032
2033#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
2034#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
2039#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK)
2045#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
2046#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
2051#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
2052
2053#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
2054#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
2059#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
2060
2061#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
2062#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
2067#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
2068
2069#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
2070#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
2075#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
2076
2077#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
2078#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
2083#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
2084
2085#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
2086#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
2091#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
2092
2093#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
2094#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
2099#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
2100
2101#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
2102#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
2107#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
2108
2109#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
2110#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
2115#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
2116
2117#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
2118#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
2123#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
2124
2125#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
2126#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
2131#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
2132
2133#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
2134#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
2139#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
2140
2141#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
2142#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
2147#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
2148
2149#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
2150#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
2155#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
2156
2157#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
2158#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
2163#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
2164
2165#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
2166#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
2171#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
2177#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
2178#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
2183#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
2184
2185#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
2186#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
2191#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
2192
2193#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
2194#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
2205#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
2206
2207#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
2208#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
2209#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
2210
2211#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
2212#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
2217#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
2220/* The count of ADC_ETC_TRIGn_CTRL */
2221#define ADC_ETC_TRIGn_CTRL_COUNT (8U)
2222
2226#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
2227#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
2228#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
2229
2230#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
2231#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
2232#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
2235/* The count of ADC_ETC_TRIGn_COUNTER */
2236#define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
2237
2241#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
2242#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
2261#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
2262
2263#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
2264#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
2276#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
2277
2278#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
2279#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
2284#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
2285
2286#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
2287#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
2294#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
2295
2296#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
2297#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
2316#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
2317
2318#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
2319#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
2331#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
2332
2333#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
2334#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
2339#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
2340
2341#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
2342#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
2349#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
2352/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
2353#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
2354
2358#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
2359#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
2378#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
2379
2380#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
2381#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
2393#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
2394
2395#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
2396#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
2401#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
2402
2403#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
2404#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
2411#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
2412
2413#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
2414#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
2433#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
2434
2435#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
2436#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
2448#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
2449
2450#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
2451#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
2456#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
2457
2458#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
2459#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
2466#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
2469/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
2470#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
2471
2475#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
2476#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
2495#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
2496
2497#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
2498#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
2510#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
2511
2512#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
2513#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
2518#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
2519
2520#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
2521#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
2528#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
2529
2530#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
2531#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
2550#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
2551
2552#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
2553#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
2565#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
2566
2567#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
2568#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
2573#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
2574
2575#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
2576#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
2583#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
2586/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
2587#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
2588
2592#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
2593#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
2612#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
2613
2614#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
2615#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
2627#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
2628
2629#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
2630#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
2635#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
2636
2637#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
2638#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
2645#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
2646
2647#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
2648#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
2667#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
2668
2669#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
2670#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
2682#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
2683
2684#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
2685#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
2690#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
2691
2692#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
2693#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
2700#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
2703/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
2704#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
2705
2709#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
2710#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
2711#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
2712
2713#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
2714#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
2715#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
2718/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
2719#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
2720
2724#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
2725#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
2726#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
2727
2728#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
2729#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
2730#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
2733/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
2734#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
2735
2739#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
2740#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
2741#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
2742
2743#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
2744#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
2745#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
2748/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
2749#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
2750
2754#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
2755#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
2756#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
2757
2758#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
2759#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
2760#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
2763/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
2764#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
2765
2766 /* end of group ADC_ETC_Register_Masks */
2770
2771
2772/* ADC_ETC - Peripheral instance base addresses */
2774#define ADC_ETC_BASE (0x403B0000u)
2776#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
2778#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
2780#define ADC_ETC_BASE_PTRS { ADC_ETC }
2782#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
2783#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
2784 /* end of group ADC_ETC_Peripheral_Access_Layer */
2788
2789
2790/* ----------------------------------------------------------------------------
2791 -- AIPSTZ Peripheral Access Layer
2792 ---------------------------------------------------------------------------- */
2793
2800typedef struct {
2801 __IO uint32_t MPR;
2802 uint8_t RESERVED_0[60];
2803 __IO uint32_t OPACR;
2804 __IO uint32_t OPACR1;
2805 __IO uint32_t OPACR2;
2806 __IO uint32_t OPACR3;
2807 __IO uint32_t OPACR4;
2808} AIPSTZ_Type;
2809
2810/* ----------------------------------------------------------------------------
2811 -- AIPSTZ Register Masks
2812 ---------------------------------------------------------------------------- */
2813
2822#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
2823#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
2833#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
2834
2835#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
2836#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
2846#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
2847
2848#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
2849#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
2859#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
2860
2861#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
2862#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
2872#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
2878#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
2879#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
2894#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
2895
2896#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
2897#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
2912#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
2913
2914#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
2915#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
2930#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
2931
2932#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
2933#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
2948#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
2949
2950#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
2951#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
2966#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
2967
2968#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
2969#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
2984#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
2985
2986#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
2987#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
3002#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
3003
3004#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
3005#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
3020#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
3026#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
3027#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
3042#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
3043
3044#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
3045#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
3060#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
3061
3062#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
3063#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
3078#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
3079
3080#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
3081#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
3096#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
3097
3098#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
3099#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
3114#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
3115
3116#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
3117#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
3132#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
3133
3134#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
3135#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
3150#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
3151
3152#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
3153#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
3168#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
3174#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
3175#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
3190#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
3191
3192#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
3193#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
3208#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
3209
3210#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
3211#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
3226#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
3227
3228#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
3229#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
3244#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
3245
3246#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
3247#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
3262#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
3263
3264#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
3265#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
3280#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
3281
3282#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
3283#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
3298#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
3299
3300#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
3301#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
3316#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
3322#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
3323#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
3338#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
3339
3340#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
3341#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
3356#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
3357
3358#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
3359#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
3374#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
3375
3376#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
3377#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
3392#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
3393
3394#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
3395#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
3410#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
3411
3412#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
3413#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
3428#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
3429
3430#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
3431#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
3446#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
3447
3448#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
3449#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
3464#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
3470#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
3471#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
3486#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
3487
3488#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
3489#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
3504#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) /* end of group AIPSTZ_Register_Masks */
3511
3512
3513/* AIPSTZ - Peripheral instance base addresses */
3515#define AIPSTZ1_BASE (0x4007C000u)
3517#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
3519#define AIPSTZ2_BASE (0x4017C000u)
3521#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
3523#define AIPSTZ3_BASE (0x4027C000u)
3525#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
3527#define AIPSTZ4_BASE (0x4037C000u)
3529#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
3531#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
3533#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
3534 /* end of group AIPSTZ_Peripheral_Access_Layer */
3538
3539
3540/* ----------------------------------------------------------------------------
3541 -- AOI Peripheral Access Layer
3542 ---------------------------------------------------------------------------- */
3543
3550typedef struct {
3551 struct { /* offset: 0x0, array step: 0x4 */
3552 __IO uint16_t BFCRT01;
3553 __IO uint16_t BFCRT23;
3554 } BFCRT[4];
3555} AOI_Type;
3556
3557/* ----------------------------------------------------------------------------
3558 -- AOI Register Masks
3559 ---------------------------------------------------------------------------- */
3560
3569#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
3570#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
3577#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
3578
3579#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
3580#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
3587#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
3588
3589#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
3590#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
3597#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
3598
3599#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
3600#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
3607#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
3608
3609#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
3610#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
3617#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
3618
3619#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
3620#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
3627#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
3628
3629#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
3630#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
3637#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
3638
3639#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
3640#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
3647#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
3650/* The count of AOI_BFCRT01 */
3651#define AOI_BFCRT01_COUNT (4U)
3652
3656#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
3657#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
3664#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
3665
3666#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
3667#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
3674#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
3675
3676#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
3677#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
3684#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
3685
3686#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
3687#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
3694#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
3695
3696#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
3697#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
3704#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
3705
3706#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
3707#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
3714#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
3715
3716#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
3717#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
3724#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
3725
3726#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
3727#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
3734#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
3737/* The count of AOI_BFCRT23 */
3738#define AOI_BFCRT23_COUNT (4U)
3739
3740 /* end of group AOI_Register_Masks */
3744
3745
3746/* AOI - Peripheral instance base addresses */
3748#define AOI1_BASE (0x403B4000u)
3750#define AOI1 ((AOI_Type *)AOI1_BASE)
3752#define AOI2_BASE (0x403B8000u)
3754#define AOI2 ((AOI_Type *)AOI2_BASE)
3756#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
3758#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
3759 /* end of group AOI_Peripheral_Access_Layer */
3763
3764
3765/* ----------------------------------------------------------------------------
3766 -- BEE Peripheral Access Layer
3767 ---------------------------------------------------------------------------- */
3768
3775typedef struct {
3776 __IO uint32_t CTRL;
3777 __IO uint32_t ADDR_OFFSET0;
3778 __IO uint32_t ADDR_OFFSET1;
3779 __IO uint32_t AES_KEY0_W0;
3780 __IO uint32_t AES_KEY0_W1;
3781 __IO uint32_t AES_KEY0_W2;
3782 __IO uint32_t AES_KEY0_W3;
3783 __IO uint32_t STATUS;
3784 __O uint32_t CTR_NONCE0_W0;
3785 __O uint32_t CTR_NONCE0_W1;
3786 __O uint32_t CTR_NONCE0_W2;
3787 __O uint32_t CTR_NONCE0_W3;
3788 __O uint32_t CTR_NONCE1_W0;
3789 __O uint32_t CTR_NONCE1_W1;
3790 __O uint32_t CTR_NONCE1_W2;
3791 __O uint32_t CTR_NONCE1_W3;
3792 __IO uint32_t REGION1_TOP;
3793 __IO uint32_t REGION1_BOT;
3794} BEE_Type;
3795
3796/* ----------------------------------------------------------------------------
3797 -- BEE Register Masks
3798 ---------------------------------------------------------------------------- */
3799
3808#define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
3809#define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
3814#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
3815
3816#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
3817#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
3818#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
3819
3820#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
3821#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
3822#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
3823
3824#define BEE_CTRL_KEY_VALID_MASK (0x10U)
3825#define BEE_CTRL_KEY_VALID_SHIFT (4U)
3826#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
3827
3828#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
3829#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
3834#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
3835
3836#define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
3837#define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
3838#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
3839
3840#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
3841#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
3848#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
3849
3850#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
3851#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
3852#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
3853
3854#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
3855#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
3860#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
3861
3862#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
3863#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
3864#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
3865
3866#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
3867#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
3872#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
3873
3874#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
3875#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
3876#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
3877
3878#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
3879#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
3880#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
3881
3882#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
3883#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
3884#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
3885
3886#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
3887#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
3888#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
3889
3890#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
3891#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
3892#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
3893
3894#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
3895#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
3896#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
3897
3898#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
3899#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
3900#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
3901
3902#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
3903#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
3904#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
3905
3906#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
3907#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
3908#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
3909
3910#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
3911#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
3912#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
3913
3914#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
3915#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
3916#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
3917
3918#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
3919#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
3920#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
3921
3922#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
3923#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
3924#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
3925
3926#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
3927#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
3928#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
3934#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
3935#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
3936#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
3937
3938#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
3939#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
3940#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
3946#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
3947#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
3948#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
3949
3950#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
3951#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
3952#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
3958#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
3959#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
3962#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
3968#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
3969#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
3972#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
3978#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
3979#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
3982#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
3988#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
3989#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
3992#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
3998#define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
3999#define BEE_STATUS_IRQ_VEC_SHIFT (0U)
4000#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
4001
4002#define BEE_STATUS_BEE_IDLE_MASK (0x100U)
4003#define BEE_STATUS_BEE_IDLE_SHIFT (8U)
4004#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
4010#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
4011#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
4012#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
4018#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
4019#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
4020#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
4026#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
4027#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
4028#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
4034#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
4035#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
4036#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
4042#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
4043#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
4044#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
4050#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
4051#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
4052#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
4058#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
4059#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
4060#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
4066#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
4067#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
4068#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
4074#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
4075#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
4078#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
4084#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
4085#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
4088#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) /* end of group BEE_Register_Masks */
4095
4096
4097/* BEE - Peripheral instance base addresses */
4099#define BEE_BASE (0x403EC000u)
4101#define BEE ((BEE_Type *)BEE_BASE)
4103#define BEE_BASE_ADDRS { BEE_BASE }
4105#define BEE_BASE_PTRS { BEE }
4106 /* end of group BEE_Peripheral_Access_Layer */
4110
4111
4112/* ----------------------------------------------------------------------------
4113 -- CAN Peripheral Access Layer
4114 ---------------------------------------------------------------------------- */
4115
4122typedef struct {
4123 __IO uint32_t MCR;
4124 __IO uint32_t CTRL1;
4125 __IO uint32_t TIMER;
4126 uint8_t RESERVED_0[4];
4127 __IO uint32_t RXMGMASK;
4128 __IO uint32_t RX14MASK;
4129 __IO uint32_t RX15MASK;
4130 __IO uint32_t ECR;
4131 __IO uint32_t ESR1;
4132 __IO uint32_t IMASK2;
4133 __IO uint32_t IMASK1;
4134 __IO uint32_t IFLAG2;
4135 __IO uint32_t IFLAG1;
4136 __IO uint32_t CTRL2;
4137 __I uint32_t ESR2;
4138 uint8_t RESERVED_1[8];
4139 __I uint32_t CRCR;
4140 __IO uint32_t RXFGMASK;
4141 __I uint32_t RXFIR;
4142 uint8_t RESERVED_2[8];
4143 __I uint32_t DBG1;
4144 __I uint32_t DBG2;
4145 uint8_t RESERVED_3[32];
4146 struct { /* offset: 0x80, array step: 0x10 */
4147 __IO uint32_t CS;
4148 __IO uint32_t ID;
4149 __IO uint32_t WORD0;
4150 __IO uint32_t WORD1;
4151 } MB[64];
4152 uint8_t RESERVED_4[1024];
4153 __IO uint32_t RXIMR[64];
4154 uint8_t RESERVED_5[96];
4155 __IO uint32_t GFWR;
4156} CAN_Type;
4157
4158/* ----------------------------------------------------------------------------
4159 -- CAN Register Masks
4160 ---------------------------------------------------------------------------- */
4161
4170#define CAN_MCR_MAXMB_MASK (0x7FU)
4171#define CAN_MCR_MAXMB_SHIFT (0U)
4172#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4173
4174#define CAN_MCR_IDAM_MASK (0x300U)
4175#define CAN_MCR_IDAM_SHIFT (8U)
4182#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4183
4184#define CAN_MCR_AEN_MASK (0x1000U)
4185#define CAN_MCR_AEN_SHIFT (12U)
4190#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4191
4192#define CAN_MCR_LPRIOEN_MASK (0x2000U)
4193#define CAN_MCR_LPRIOEN_SHIFT (13U)
4198#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4199
4200#define CAN_MCR_IRMQ_MASK (0x10000U)
4201#define CAN_MCR_IRMQ_SHIFT (16U)
4206#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4207
4208#define CAN_MCR_SRXDIS_MASK (0x20000U)
4209#define CAN_MCR_SRXDIS_SHIFT (17U)
4214#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4215
4216#define CAN_MCR_WAKSRC_MASK (0x80000U)
4217#define CAN_MCR_WAKSRC_SHIFT (19U)
4222#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4223
4224#define CAN_MCR_LPMACK_MASK (0x100000U)
4225#define CAN_MCR_LPMACK_SHIFT (20U)
4230#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4231
4232#define CAN_MCR_WRNEN_MASK (0x200000U)
4233#define CAN_MCR_WRNEN_SHIFT (21U)
4238#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4239
4240#define CAN_MCR_SLFWAK_MASK (0x400000U)
4241#define CAN_MCR_SLFWAK_SHIFT (22U)
4246#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4247
4248#define CAN_MCR_SUPV_MASK (0x800000U)
4249#define CAN_MCR_SUPV_SHIFT (23U)
4255#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
4256
4257#define CAN_MCR_FRZACK_MASK (0x1000000U)
4258#define CAN_MCR_FRZACK_SHIFT (24U)
4263#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4264
4265#define CAN_MCR_SOFTRST_MASK (0x2000000U)
4266#define CAN_MCR_SOFTRST_SHIFT (25U)
4271#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4272
4273#define CAN_MCR_WAKMSK_MASK (0x4000000U)
4274#define CAN_MCR_WAKMSK_SHIFT (26U)
4279#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4280
4281#define CAN_MCR_NOTRDY_MASK (0x8000000U)
4282#define CAN_MCR_NOTRDY_SHIFT (27U)
4287#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4288
4289#define CAN_MCR_HALT_MASK (0x10000000U)
4290#define CAN_MCR_HALT_SHIFT (28U)
4295#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4296
4297#define CAN_MCR_RFEN_MASK (0x20000000U)
4298#define CAN_MCR_RFEN_SHIFT (29U)
4303#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4304
4305#define CAN_MCR_FRZ_MASK (0x40000000U)
4306#define CAN_MCR_FRZ_SHIFT (30U)
4311#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4312
4313#define CAN_MCR_MDIS_MASK (0x80000000U)
4314#define CAN_MCR_MDIS_SHIFT (31U)
4319#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4325#define CAN_CTRL1_PROPSEG_MASK (0x7U)
4326#define CAN_CTRL1_PROPSEG_SHIFT (0U)
4327#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4328
4329#define CAN_CTRL1_LOM_MASK (0x8U)
4330#define CAN_CTRL1_LOM_SHIFT (3U)
4335#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4336
4337#define CAN_CTRL1_LBUF_MASK (0x10U)
4338#define CAN_CTRL1_LBUF_SHIFT (4U)
4343#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4344
4345#define CAN_CTRL1_TSYN_MASK (0x20U)
4346#define CAN_CTRL1_TSYN_SHIFT (5U)
4351#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4352
4353#define CAN_CTRL1_BOFFREC_MASK (0x40U)
4354#define CAN_CTRL1_BOFFREC_SHIFT (6U)
4359#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4360
4361#define CAN_CTRL1_SMP_MASK (0x80U)
4362#define CAN_CTRL1_SMP_SHIFT (7U)
4368#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4369
4370#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
4371#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
4376#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4377
4378#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
4379#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
4384#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4385
4386#define CAN_CTRL1_LPB_MASK (0x1000U)
4387#define CAN_CTRL1_LPB_SHIFT (12U)
4392#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4393
4394#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
4395#define CAN_CTRL1_ERRMSK_SHIFT (14U)
4400#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4401
4402#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
4403#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
4408#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4409
4410#define CAN_CTRL1_PSEG2_MASK (0x70000U)
4411#define CAN_CTRL1_PSEG2_SHIFT (16U)
4412#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4413
4414#define CAN_CTRL1_PSEG1_MASK (0x380000U)
4415#define CAN_CTRL1_PSEG1_SHIFT (19U)
4416#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4417
4418#define CAN_CTRL1_RJW_MASK (0xC00000U)
4419#define CAN_CTRL1_RJW_SHIFT (22U)
4420#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4421
4422#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
4423#define CAN_CTRL1_PRESDIV_SHIFT (24U)
4424#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4430#define CAN_TIMER_TIMER_MASK (0xFFFFU)
4431#define CAN_TIMER_TIMER_SHIFT (0U)
4432#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4438#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
4439#define CAN_RXMGMASK_MG_SHIFT (0U)
4444#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4450#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
4451#define CAN_RX14MASK_RX14M_SHIFT (0U)
4456#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4462#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
4463#define CAN_RX15MASK_RX15M_SHIFT (0U)
4468#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4474#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
4475#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
4476#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
4477
4478#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
4479#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
4480#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
4486#define CAN_ESR1_WAKINT_MASK (0x1U)
4487#define CAN_ESR1_WAKINT_SHIFT (0U)
4492#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4493
4494#define CAN_ESR1_ERRINT_MASK (0x2U)
4495#define CAN_ESR1_ERRINT_SHIFT (1U)
4500#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4501
4502#define CAN_ESR1_BOFFINT_MASK (0x4U)
4503#define CAN_ESR1_BOFFINT_SHIFT (2U)
4508#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4509
4510#define CAN_ESR1_RX_MASK (0x8U)
4511#define CAN_ESR1_RX_SHIFT (3U)
4516#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4517
4518#define CAN_ESR1_FLTCONF_MASK (0x30U)
4519#define CAN_ESR1_FLTCONF_SHIFT (4U)
4525#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4526
4527#define CAN_ESR1_TX_MASK (0x40U)
4528#define CAN_ESR1_TX_SHIFT (6U)
4533#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4534
4535#define CAN_ESR1_IDLE_MASK (0x80U)
4536#define CAN_ESR1_IDLE_SHIFT (7U)
4541#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4542
4543#define CAN_ESR1_RXWRN_MASK (0x100U)
4544#define CAN_ESR1_RXWRN_SHIFT (8U)
4549#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4550
4551#define CAN_ESR1_TXWRN_MASK (0x200U)
4552#define CAN_ESR1_TXWRN_SHIFT (9U)
4557#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4558
4559#define CAN_ESR1_STFERR_MASK (0x400U)
4560#define CAN_ESR1_STFERR_SHIFT (10U)
4565#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4566
4567#define CAN_ESR1_FRMERR_MASK (0x800U)
4568#define CAN_ESR1_FRMERR_SHIFT (11U)
4573#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4574
4575#define CAN_ESR1_CRCERR_MASK (0x1000U)
4576#define CAN_ESR1_CRCERR_SHIFT (12U)
4581#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4582
4583#define CAN_ESR1_ACKERR_MASK (0x2000U)
4584#define CAN_ESR1_ACKERR_SHIFT (13U)
4589#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4590
4591#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
4592#define CAN_ESR1_BIT0ERR_SHIFT (14U)
4597#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4598
4599#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
4600#define CAN_ESR1_BIT1ERR_SHIFT (15U)
4605#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4606
4607#define CAN_ESR1_RWRNINT_MASK (0x10000U)
4608#define CAN_ESR1_RWRNINT_SHIFT (16U)
4613#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4614
4615#define CAN_ESR1_TWRNINT_MASK (0x20000U)
4616#define CAN_ESR1_TWRNINT_SHIFT (17U)
4621#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4622
4623#define CAN_ESR1_SYNCH_MASK (0x40000U)
4624#define CAN_ESR1_SYNCH_SHIFT (18U)
4629#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4635#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)
4636#define CAN_IMASK2_BUFHM_SHIFT (0U)
4641#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
4647#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
4648#define CAN_IMASK1_BUFLM_SHIFT (0U)
4653#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
4659#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)
4660#define CAN_IFLAG2_BUFHI_SHIFT (0U)
4665#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
4671#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
4672#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
4677#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
4678
4679#define CAN_IFLAG1_BUF5I_MASK (0x20U)
4680#define CAN_IFLAG1_BUF5I_SHIFT (5U)
4685#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4686
4687#define CAN_IFLAG1_BUF6I_MASK (0x40U)
4688#define CAN_IFLAG1_BUF6I_SHIFT (6U)
4693#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4694
4695#define CAN_IFLAG1_BUF7I_MASK (0x80U)
4696#define CAN_IFLAG1_BUF7I_SHIFT (7U)
4701#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4702
4703#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4704#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
4709#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4715#define CAN_CTRL2_EACEN_MASK (0x10000U)
4716#define CAN_CTRL2_EACEN_SHIFT (16U)
4722#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4723
4724#define CAN_CTRL2_RRS_MASK (0x20000U)
4725#define CAN_CTRL2_RRS_SHIFT (17U)
4730#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4731
4732#define CAN_CTRL2_MRP_MASK (0x40000U)
4733#define CAN_CTRL2_MRP_SHIFT (18U)
4738#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
4739
4740#define CAN_CTRL2_TASD_MASK (0xF80000U)
4741#define CAN_CTRL2_TASD_SHIFT (19U)
4742#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
4743
4744#define CAN_CTRL2_RFFN_MASK (0xF000000U)
4745#define CAN_CTRL2_RFFN_SHIFT (24U)
4746#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
4747
4748#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
4749#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
4754#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
4760#define CAN_ESR2_IMB_MASK (0x2000U)
4761#define CAN_ESR2_IMB_SHIFT (13U)
4766#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
4767
4768#define CAN_ESR2_VPS_MASK (0x4000U)
4769#define CAN_ESR2_VPS_SHIFT (14U)
4774#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
4775
4776#define CAN_ESR2_LPTM_MASK (0x7F0000U)
4777#define CAN_ESR2_LPTM_SHIFT (16U)
4778#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
4784#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
4785#define CAN_CRCR_TXCRC_SHIFT (0U)
4786#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
4787
4788#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
4789#define CAN_CRCR_MBCRC_SHIFT (16U)
4790#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
4796#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
4797#define CAN_RXFGMASK_FGM_SHIFT (0U)
4802#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
4808#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
4809#define CAN_RXFIR_IDHIT_SHIFT (0U)
4810#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
4816#define CAN_DBG1_CFSM_MASK (0x3FU)
4817#define CAN_DBG1_CFSM_SHIFT (0U)
4820#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
4821
4822#define CAN_DBG1_CBN_MASK (0x1F000000U)
4823#define CAN_DBG1_CBN_SHIFT (24U)
4826#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
4832#define CAN_DBG2_RMP_MASK (0x7FU)
4833#define CAN_DBG2_RMP_SHIFT (0U)
4836#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
4837
4838#define CAN_DBG2_MPP_MASK (0x80U)
4839#define CAN_DBG2_MPP_SHIFT (7U)
4844#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
4845
4846#define CAN_DBG2_TAP_MASK (0x7F00U)
4847#define CAN_DBG2_TAP_SHIFT (8U)
4850#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
4851
4852#define CAN_DBG2_APP_MASK (0x8000U)
4853#define CAN_DBG2_APP_SHIFT (15U)
4858#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
4864#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
4865#define CAN_CS_TIME_STAMP_SHIFT (0U)
4870#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
4871
4872#define CAN_CS_DLC_MASK (0xF0000U)
4873#define CAN_CS_DLC_SHIFT (16U)
4876#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
4877
4878#define CAN_CS_RTR_MASK (0x100000U)
4879#define CAN_CS_RTR_SHIFT (20U)
4882#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
4883
4884#define CAN_CS_IDE_MASK (0x200000U)
4885#define CAN_CS_IDE_SHIFT (21U)
4888#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
4889
4890#define CAN_CS_SRR_MASK (0x400000U)
4891#define CAN_CS_SRR_SHIFT (22U)
4894#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
4895
4896#define CAN_CS_CODE_MASK (0xF000000U)
4897#define CAN_CS_CODE_SHIFT (24U)
4900#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
4903/* The count of CAN_CS */
4904#define CAN_CS_COUNT (64U)
4905
4909#define CAN_ID_EXT_MASK (0x3FFFFU)
4910#define CAN_ID_EXT_SHIFT (0U)
4913#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
4914
4915#define CAN_ID_STD_MASK (0x1FFC0000U)
4916#define CAN_ID_STD_SHIFT (18U)
4919#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
4920
4921#define CAN_ID_PRIO_MASK (0xE0000000U)
4922#define CAN_ID_PRIO_SHIFT (29U)
4927#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
4930/* The count of CAN_ID */
4931#define CAN_ID_COUNT (64U)
4932
4936#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
4937#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
4940#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
4941
4942#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
4943#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
4946#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
4947
4948#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
4949#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
4952#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
4953
4954#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
4955#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
4958#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
4961/* The count of CAN_WORD0 */
4962#define CAN_WORD0_COUNT (64U)
4963
4967#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
4968#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
4971#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
4972
4973#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
4974#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
4977#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
4978
4979#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
4980#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
4983#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
4984
4985#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
4986#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
4989#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
4992/* The count of CAN_WORD1 */
4993#define CAN_WORD1_COUNT (64U)
4994
4998#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
4999#define CAN_RXIMR_MI_SHIFT (0U)
5004#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
5007/* The count of CAN_RXIMR */
5008#define CAN_RXIMR_COUNT (64U)
5009
5013#define CAN_GFWR_GFWR_MASK (0xFFU)
5014#define CAN_GFWR_GFWR_SHIFT (0U)
5015#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) /* end of group CAN_Register_Masks */
5022
5023
5024/* CAN - Peripheral instance base addresses */
5026#define CAN1_BASE (0x401D0000u)
5028#define CAN1 ((CAN_Type *)CAN1_BASE)
5030#define CAN2_BASE (0x401D4000u)
5032#define CAN2 ((CAN_Type *)CAN2_BASE)
5034#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }
5036#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }
5038#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5039#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5040#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5041#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5042#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5043#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
5044/* Backward compatibility */
5045#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK
5046#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT
5047#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)
5048#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK
5049#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT
5050#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)
5051
5052 /* end of group CAN_Peripheral_Access_Layer */
5056
5057
5058/* ----------------------------------------------------------------------------
5059 -- CCM Peripheral Access Layer
5060 ---------------------------------------------------------------------------- */
5061
5068typedef struct {
5069 __IO uint32_t CCR;
5070 uint8_t RESERVED_0[4];
5071 __I uint32_t CSR;
5072 __IO uint32_t CCSR;
5073 __IO uint32_t CACRR;
5074 __IO uint32_t CBCDR;
5075 __IO uint32_t CBCMR;
5076 __IO uint32_t CSCMR1;
5077 __IO uint32_t CSCMR2;
5078 __IO uint32_t CSCDR1;
5079 __IO uint32_t CS1CDR;
5080 __IO uint32_t CS2CDR;
5081 __IO uint32_t CDCDR;
5082 uint8_t RESERVED_1[4];
5083 __IO uint32_t CSCDR2;
5084 __IO uint32_t CSCDR3;
5085 uint8_t RESERVED_2[8];
5086 __I uint32_t CDHIPR;
5087 uint8_t RESERVED_3[8];
5088 __IO uint32_t CLPCR;
5089 __IO uint32_t CISR;
5090 __IO uint32_t CIMR;
5091 __IO uint32_t CCOSR;
5092 __IO uint32_t CGPR;
5093 __IO uint32_t CCGR0;
5094 __IO uint32_t CCGR1;
5095 __IO uint32_t CCGR2;
5096 __IO uint32_t CCGR3;
5097 __IO uint32_t CCGR4;
5098 __IO uint32_t CCGR5;
5099 __IO uint32_t CCGR6;
5100 uint8_t RESERVED_4[4];
5101 __IO uint32_t CMEOR;
5102} CCM_Type;
5103
5104/* ----------------------------------------------------------------------------
5105 -- CCM Register Masks
5106 ---------------------------------------------------------------------------- */
5107
5116#define CCM_CCR_OSCNT_MASK (0xFFU)
5117#define CCM_CCR_OSCNT_SHIFT (0U)
5124#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
5125
5126#define CCM_CCR_COSC_EN_MASK (0x1000U)
5127#define CCM_CCR_COSC_EN_SHIFT (12U)
5132#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
5133
5134#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
5135#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
5141#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
5142
5143#define CCM_CCR_RBC_EN_MASK (0x8000000U)
5144#define CCM_CCR_RBC_EN_SHIFT (27U)
5149#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
5155#define CCM_CSR_REF_EN_B_MASK (0x1U)
5156#define CCM_CSR_REF_EN_B_SHIFT (0U)
5161#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
5162
5163#define CCM_CSR_CAMP2_READY_MASK (0x8U)
5164#define CCM_CSR_CAMP2_READY_SHIFT (3U)
5169#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
5170
5171#define CCM_CSR_COSC_READY_MASK (0x20U)
5172#define CCM_CSR_COSC_READY_SHIFT (5U)
5177#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
5183#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
5184#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
5189#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
5195#define CCM_CACRR_ARM_PODF_MASK (0x7U)
5196#define CCM_CACRR_ARM_PODF_SHIFT (0U)
5207#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
5213#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
5214#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
5219#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
5220
5221#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
5222#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
5227#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
5228
5229#define CCM_CBCDR_IPG_PODF_MASK (0x300U)
5230#define CCM_CBCDR_IPG_PODF_SHIFT (8U)
5237#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
5238
5239#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
5240#define CCM_CBCDR_AHB_PODF_SHIFT (10U)
5251#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
5252
5253#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
5254#define CCM_CBCDR_SEMC_PODF_SHIFT (16U)
5265#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
5266
5267#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
5268#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
5273#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
5274
5275#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
5276#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
5287#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
5293#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
5294#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
5301#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
5302
5303#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
5304#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
5311#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
5312
5313#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
5314#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
5321#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
5322
5323#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
5324#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
5331#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
5332
5333#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)
5334#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U)
5345#define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
5346
5347#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
5348#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
5359#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
5365#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
5366#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
5433#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
5434
5435#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
5436#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
5441#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
5442
5443#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
5444#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
5451#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
5452
5453#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
5454#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
5461#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
5462
5463#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
5464#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
5471#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
5472
5473#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
5474#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
5479#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
5480
5481#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
5482#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
5487#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
5488
5489#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
5490#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
5501#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
5502
5503#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
5504#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
5511#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
5517#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
5518#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
5585#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
5586
5587#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
5588#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
5595#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
5596
5597#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)
5598#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)
5605#define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)
5611#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
5612#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
5679#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
5680
5681#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
5682#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
5687#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
5688
5689#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
5690#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
5701#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
5702
5703#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
5704#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
5715#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
5716
5717#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
5718#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
5725#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
5731#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
5732#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
5800#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
5801
5802#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
5803#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
5814#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
5815
5816#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)
5817#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)
5828#define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
5829
5830#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
5831#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
5899#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
5900
5901#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
5902#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
5913#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
5914
5915#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)
5916#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)
5927#define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)
5933#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
5934#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
6002#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
6003
6004#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
6005#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
6016#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
6022#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)
6023#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)
6030#define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
6031
6032#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)
6033#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)
6044#define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
6045
6046#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)
6047#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)
6058#define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
6059
6060#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
6061#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
6068#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
6069
6070#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
6071#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
6082#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
6083
6084#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
6085#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
6096#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
6102#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)
6103#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)
6114#define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
6115
6116#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)
6117#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)
6127#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
6128
6129#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
6130#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
6135#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
6136
6137#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
6138#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
6207#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
6213#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)
6214#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)
6221#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
6222
6223#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U)
6224#define CCM_CSCDR3_CSI_PODF_SHIFT (11U)
6235#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)
6241#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
6242#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
6248#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
6249
6250#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
6251#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
6257#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
6258
6259#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
6260#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
6266#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
6267
6268#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
6269#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
6275#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
6276
6277#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
6278#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
6284#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
6290#define CCM_CLPCR_LPM_MASK (0x3U)
6291#define CCM_CLPCR_LPM_SHIFT (0U)
6298#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
6299
6300#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
6301#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
6306#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
6307
6308#define CCM_CLPCR_SBYOS_MASK (0x40U)
6309#define CCM_CLPCR_SBYOS_SHIFT (6U)
6318#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
6319
6320#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
6321#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
6326#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
6327
6328#define CCM_CLPCR_VSTBY_MASK (0x100U)
6329#define CCM_CLPCR_VSTBY_SHIFT (8U)
6334#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
6335
6336#define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
6337#define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
6344#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
6345
6346#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
6347#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
6352#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
6353
6354#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
6355#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
6356#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
6357
6358#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
6359#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
6360#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
6361
6362#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
6363#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
6368#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
6369
6370#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
6371#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
6376#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
6377
6378#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
6379#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
6384#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
6390#define CCM_CISR_LRF_PLL_MASK (0x1U)
6391#define CCM_CISR_LRF_PLL_SHIFT (0U)
6396#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
6397
6398#define CCM_CISR_COSC_READY_MASK (0x40U)
6399#define CCM_CISR_COSC_READY_SHIFT (6U)
6404#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
6405
6406#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
6407#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
6412#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
6413
6414#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
6415#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
6420#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
6421
6422#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
6423#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
6428#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
6429
6430#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
6431#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
6436#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
6437
6438#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
6439#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
6444#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
6450#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
6451#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
6456#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
6457
6458#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
6459#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
6464#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
6465
6466#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
6467#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
6472#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
6473
6474#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
6475#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
6480#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
6481
6482#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
6483#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
6488#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
6489
6490#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
6491#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
6496#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
6497
6498#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
6499#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
6504#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
6510#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
6511#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
6525#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
6526
6527#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
6528#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
6539#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
6540
6541#define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
6542#define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
6547#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
6548
6549#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
6550#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
6555#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
6556
6557#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
6558#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
6574#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
6575
6576#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
6577#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
6588#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
6589
6590#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
6591#define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
6596#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
6602#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
6603#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
6608#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
6609
6610#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
6611#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
6616#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
6617
6618#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
6619#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
6625#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
6626
6627#define CCM_CGPR_FPL_MASK (0x10000U)
6628#define CCM_CGPR_FPL_SHIFT (16U)
6633#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
6634
6635#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
6636#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
6642#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
6648#define CCM_CCGR0_CG0_MASK (0x3U)
6649#define CCM_CCGR0_CG0_SHIFT (0U)
6650#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
6651
6652#define CCM_CCGR0_CG1_MASK (0xCU)
6653#define CCM_CCGR0_CG1_SHIFT (2U)
6654#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
6655
6656#define CCM_CCGR0_CG2_MASK (0x30U)
6657#define CCM_CCGR0_CG2_SHIFT (4U)
6658#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
6659
6660#define CCM_CCGR0_CG3_MASK (0xC0U)
6661#define CCM_CCGR0_CG3_SHIFT (6U)
6662#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
6663
6664#define CCM_CCGR0_CG4_MASK (0x300U)
6665#define CCM_CCGR0_CG4_SHIFT (8U)
6666#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
6667
6668#define CCM_CCGR0_CG5_MASK (0xC00U)
6669#define CCM_CCGR0_CG5_SHIFT (10U)
6670#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
6671
6672#define CCM_CCGR0_CG6_MASK (0x3000U)
6673#define CCM_CCGR0_CG6_SHIFT (12U)
6674#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
6675
6676#define CCM_CCGR0_CG7_MASK (0xC000U)
6677#define CCM_CCGR0_CG7_SHIFT (14U)
6678#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
6679
6680#define CCM_CCGR0_CG8_MASK (0x30000U)
6681#define CCM_CCGR0_CG8_SHIFT (16U)
6682#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
6683
6684#define CCM_CCGR0_CG9_MASK (0xC0000U)
6685#define CCM_CCGR0_CG9_SHIFT (18U)
6686#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
6687
6688#define CCM_CCGR0_CG10_MASK (0x300000U)
6689#define CCM_CCGR0_CG10_SHIFT (20U)
6690#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
6691
6692#define CCM_CCGR0_CG11_MASK (0xC00000U)
6693#define CCM_CCGR0_CG11_SHIFT (22U)
6694#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
6695
6696#define CCM_CCGR0_CG12_MASK (0x3000000U)
6697#define CCM_CCGR0_CG12_SHIFT (24U)
6698#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
6699
6700#define CCM_CCGR0_CG13_MASK (0xC000000U)
6701#define CCM_CCGR0_CG13_SHIFT (26U)
6702#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
6703
6704#define CCM_CCGR0_CG14_MASK (0x30000000U)
6705#define CCM_CCGR0_CG14_SHIFT (28U)
6706#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
6707
6708#define CCM_CCGR0_CG15_MASK (0xC0000000U)
6709#define CCM_CCGR0_CG15_SHIFT (30U)
6710#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
6716#define CCM_CCGR1_CG0_MASK (0x3U)
6717#define CCM_CCGR1_CG0_SHIFT (0U)
6718#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
6719
6720#define CCM_CCGR1_CG1_MASK (0xCU)
6721#define CCM_CCGR1_CG1_SHIFT (2U)
6722#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
6723
6724#define CCM_CCGR1_CG2_MASK (0x30U)
6725#define CCM_CCGR1_CG2_SHIFT (4U)
6726#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
6727
6728#define CCM_CCGR1_CG3_MASK (0xC0U)
6729#define CCM_CCGR1_CG3_SHIFT (6U)
6730#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
6731
6732#define CCM_CCGR1_CG4_MASK (0x300U)
6733#define CCM_CCGR1_CG4_SHIFT (8U)
6734#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
6735
6736#define CCM_CCGR1_CG5_MASK (0xC00U)
6737#define CCM_CCGR1_CG5_SHIFT (10U)
6738#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
6739
6740#define CCM_CCGR1_CG6_MASK (0x3000U)
6741#define CCM_CCGR1_CG6_SHIFT (12U)
6742#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
6743
6744#define CCM_CCGR1_CG7_MASK (0xC000U)
6745#define CCM_CCGR1_CG7_SHIFT (14U)
6746#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
6747
6748#define CCM_CCGR1_CG8_MASK (0x30000U)
6749#define CCM_CCGR1_CG8_SHIFT (16U)
6750#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
6751
6752#define CCM_CCGR1_CG9_MASK (0xC0000U)
6753#define CCM_CCGR1_CG9_SHIFT (18U)
6754#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
6755
6756#define CCM_CCGR1_CG10_MASK (0x300000U)
6757#define CCM_CCGR1_CG10_SHIFT (20U)
6758#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
6759
6760#define CCM_CCGR1_CG11_MASK (0xC00000U)
6761#define CCM_CCGR1_CG11_SHIFT (22U)
6762#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
6763
6764#define CCM_CCGR1_CG12_MASK (0x3000000U)
6765#define CCM_CCGR1_CG12_SHIFT (24U)
6766#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
6767
6768#define CCM_CCGR1_CG13_MASK (0xC000000U)
6769#define CCM_CCGR1_CG13_SHIFT (26U)
6770#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
6771
6772#define CCM_CCGR1_CG14_MASK (0x30000000U)
6773#define CCM_CCGR1_CG14_SHIFT (28U)
6774#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
6775
6776#define CCM_CCGR1_CG15_MASK (0xC0000000U)
6777#define CCM_CCGR1_CG15_SHIFT (30U)
6778#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
6784#define CCM_CCGR2_CG0_MASK (0x3U)
6785#define CCM_CCGR2_CG0_SHIFT (0U)
6786#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
6787
6788#define CCM_CCGR2_CG1_MASK (0xCU)
6789#define CCM_CCGR2_CG1_SHIFT (2U)
6790#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
6791
6792#define CCM_CCGR2_CG2_MASK (0x30U)
6793#define CCM_CCGR2_CG2_SHIFT (4U)
6794#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
6795
6796#define CCM_CCGR2_CG3_MASK (0xC0U)
6797#define CCM_CCGR2_CG3_SHIFT (6U)
6798#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
6799
6800#define CCM_CCGR2_CG4_MASK (0x300U)
6801#define CCM_CCGR2_CG4_SHIFT (8U)
6802#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
6803
6804#define CCM_CCGR2_CG5_MASK (0xC00U)
6805#define CCM_CCGR2_CG5_SHIFT (10U)
6806#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
6807
6808#define CCM_CCGR2_CG6_MASK (0x3000U)
6809#define CCM_CCGR2_CG6_SHIFT (12U)
6810#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
6811
6812#define CCM_CCGR2_CG7_MASK (0xC000U)
6813#define CCM_CCGR2_CG7_SHIFT (14U)
6814#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
6815
6816#define CCM_CCGR2_CG8_MASK (0x30000U)
6817#define CCM_CCGR2_CG8_SHIFT (16U)
6818#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
6819
6820#define CCM_CCGR2_CG9_MASK (0xC0000U)
6821#define CCM_CCGR2_CG9_SHIFT (18U)
6822#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
6823
6824#define CCM_CCGR2_CG10_MASK (0x300000U)
6825#define CCM_CCGR2_CG10_SHIFT (20U)
6826#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
6827
6828#define CCM_CCGR2_CG11_MASK (0xC00000U)
6829#define CCM_CCGR2_CG11_SHIFT (22U)
6830#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
6831
6832#define CCM_CCGR2_CG12_MASK (0x3000000U)
6833#define CCM_CCGR2_CG12_SHIFT (24U)
6834#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
6835
6836#define CCM_CCGR2_CG13_MASK (0xC000000U)
6837#define CCM_CCGR2_CG13_SHIFT (26U)
6838#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
6839
6840#define CCM_CCGR2_CG14_MASK (0x30000000U)
6841#define CCM_CCGR2_CG14_SHIFT (28U)
6842#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
6843
6844#define CCM_CCGR2_CG15_MASK (0xC0000000U)
6845#define CCM_CCGR2_CG15_SHIFT (30U)
6846#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
6852#define CCM_CCGR3_CG0_MASK (0x3U)
6853#define CCM_CCGR3_CG0_SHIFT (0U)
6854#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
6855
6856#define CCM_CCGR3_CG1_MASK (0xCU)
6857#define CCM_CCGR3_CG1_SHIFT (2U)
6858#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
6859
6860#define CCM_CCGR3_CG2_MASK (0x30U)
6861#define CCM_CCGR3_CG2_SHIFT (4U)
6862#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
6863
6864#define CCM_CCGR3_CG3_MASK (0xC0U)
6865#define CCM_CCGR3_CG3_SHIFT (6U)
6866#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
6867
6868#define CCM_CCGR3_CG4_MASK (0x300U)
6869#define CCM_CCGR3_CG4_SHIFT (8U)
6870#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
6871
6872#define CCM_CCGR3_CG5_MASK (0xC00U)
6873#define CCM_CCGR3_CG5_SHIFT (10U)
6874#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
6875
6876#define CCM_CCGR3_CG6_MASK (0x3000U)
6877#define CCM_CCGR3_CG6_SHIFT (12U)
6878#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
6879
6880#define CCM_CCGR3_CG7_MASK (0xC000U)
6881#define CCM_CCGR3_CG7_SHIFT (14U)
6882#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
6883
6884#define CCM_CCGR3_CG8_MASK (0x30000U)
6885#define CCM_CCGR3_CG8_SHIFT (16U)
6886#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
6887
6888#define CCM_CCGR3_CG9_MASK (0xC0000U)
6889#define CCM_CCGR3_CG9_SHIFT (18U)
6890#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
6891
6892#define CCM_CCGR3_CG10_MASK (0x300000U)
6893#define CCM_CCGR3_CG10_SHIFT (20U)
6894#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
6895
6896#define CCM_CCGR3_CG11_MASK (0xC00000U)
6897#define CCM_CCGR3_CG11_SHIFT (22U)
6898#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
6899
6900#define CCM_CCGR3_CG12_MASK (0x3000000U)
6901#define CCM_CCGR3_CG12_SHIFT (24U)
6902#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
6903
6904#define CCM_CCGR3_CG13_MASK (0xC000000U)
6905#define CCM_CCGR3_CG13_SHIFT (26U)
6906#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
6907
6908#define CCM_CCGR3_CG14_MASK (0x30000000U)
6909#define CCM_CCGR3_CG14_SHIFT (28U)
6912#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
6913
6914#define CCM_CCGR3_CG15_MASK (0xC0000000U)
6915#define CCM_CCGR3_CG15_SHIFT (30U)
6916#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
6922#define CCM_CCGR4_CG0_MASK (0x3U)
6923#define CCM_CCGR4_CG0_SHIFT (0U)
6924#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
6925
6926#define CCM_CCGR4_CG1_MASK (0xCU)
6927#define CCM_CCGR4_CG1_SHIFT (2U)
6928#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
6929
6930#define CCM_CCGR4_CG2_MASK (0x30U)
6931#define CCM_CCGR4_CG2_SHIFT (4U)
6932#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
6933
6934#define CCM_CCGR4_CG3_MASK (0xC0U)
6935#define CCM_CCGR4_CG3_SHIFT (6U)
6936#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
6937
6938#define CCM_CCGR4_CG4_MASK (0x300U)
6939#define CCM_CCGR4_CG4_SHIFT (8U)
6940#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
6941
6942#define CCM_CCGR4_CG5_MASK (0xC00U)
6943#define CCM_CCGR4_CG5_SHIFT (10U)
6944#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
6945
6946#define CCM_CCGR4_CG6_MASK (0x3000U)
6947#define CCM_CCGR4_CG6_SHIFT (12U)
6948#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
6949
6950#define CCM_CCGR4_CG7_MASK (0xC000U)
6951#define CCM_CCGR4_CG7_SHIFT (14U)
6952#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
6953
6954#define CCM_CCGR4_CG8_MASK (0x30000U)
6955#define CCM_CCGR4_CG8_SHIFT (16U)
6956#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
6957
6958#define CCM_CCGR4_CG9_MASK (0xC0000U)
6959#define CCM_CCGR4_CG9_SHIFT (18U)
6960#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
6961
6962#define CCM_CCGR4_CG10_MASK (0x300000U)
6963#define CCM_CCGR4_CG10_SHIFT (20U)
6964#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
6965
6966#define CCM_CCGR4_CG11_MASK (0xC00000U)
6967#define CCM_CCGR4_CG11_SHIFT (22U)
6968#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
6969
6970#define CCM_CCGR4_CG12_MASK (0x3000000U)
6971#define CCM_CCGR4_CG12_SHIFT (24U)
6972#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
6973
6974#define CCM_CCGR4_CG13_MASK (0xC000000U)
6975#define CCM_CCGR4_CG13_SHIFT (26U)
6976#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
6977
6978#define CCM_CCGR4_CG14_MASK (0x30000000U)
6979#define CCM_CCGR4_CG14_SHIFT (28U)
6980#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
6981
6982#define CCM_CCGR4_CG15_MASK (0xC0000000U)
6983#define CCM_CCGR4_CG15_SHIFT (30U)
6984#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
6990#define CCM_CCGR5_CG0_MASK (0x3U)
6991#define CCM_CCGR5_CG0_SHIFT (0U)
6992#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
6993
6994#define CCM_CCGR5_CG1_MASK (0xCU)
6995#define CCM_CCGR5_CG1_SHIFT (2U)
6996#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
6997
6998#define CCM_CCGR5_CG2_MASK (0x30U)
6999#define CCM_CCGR5_CG2_SHIFT (4U)
7000#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
7001
7002#define CCM_CCGR5_CG3_MASK (0xC0U)
7003#define CCM_CCGR5_CG3_SHIFT (6U)
7004#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
7005
7006#define CCM_CCGR5_CG4_MASK (0x300U)
7007#define CCM_CCGR5_CG4_SHIFT (8U)
7008#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
7009
7010#define CCM_CCGR5_CG5_MASK (0xC00U)
7011#define CCM_CCGR5_CG5_SHIFT (10U)
7012#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
7013
7014#define CCM_CCGR5_CG6_MASK (0x3000U)
7015#define CCM_CCGR5_CG6_SHIFT (12U)
7016#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
7017
7018#define CCM_CCGR5_CG7_MASK (0xC000U)
7019#define CCM_CCGR5_CG7_SHIFT (14U)
7020#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
7021
7022#define CCM_CCGR5_CG8_MASK (0x30000U)
7023#define CCM_CCGR5_CG8_SHIFT (16U)
7024#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
7025
7026#define CCM_CCGR5_CG9_MASK (0xC0000U)
7027#define CCM_CCGR5_CG9_SHIFT (18U)
7028#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
7029
7030#define CCM_CCGR5_CG10_MASK (0x300000U)
7031#define CCM_CCGR5_CG10_SHIFT (20U)
7032#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
7033
7034#define CCM_CCGR5_CG11_MASK (0xC00000U)
7035#define CCM_CCGR5_CG11_SHIFT (22U)
7036#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
7037
7038#define CCM_CCGR5_CG12_MASK (0x3000000U)
7039#define CCM_CCGR5_CG12_SHIFT (24U)
7040#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
7041
7042#define CCM_CCGR5_CG13_MASK (0xC000000U)
7043#define CCM_CCGR5_CG13_SHIFT (26U)
7044#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
7045
7046#define CCM_CCGR5_CG14_MASK (0x30000000U)
7047#define CCM_CCGR5_CG14_SHIFT (28U)
7048#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
7049
7050#define CCM_CCGR5_CG15_MASK (0xC0000000U)
7051#define CCM_CCGR5_CG15_SHIFT (30U)
7052#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
7058#define CCM_CCGR6_CG0_MASK (0x3U)
7059#define CCM_CCGR6_CG0_SHIFT (0U)
7060#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
7061
7062#define CCM_CCGR6_CG1_MASK (0xCU)
7063#define CCM_CCGR6_CG1_SHIFT (2U)
7064#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
7065
7066#define CCM_CCGR6_CG2_MASK (0x30U)
7067#define CCM_CCGR6_CG2_SHIFT (4U)
7068#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
7069
7070#define CCM_CCGR6_CG3_MASK (0xC0U)
7071#define CCM_CCGR6_CG3_SHIFT (6U)
7072#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
7073
7074#define CCM_CCGR6_CG4_MASK (0x300U)
7075#define CCM_CCGR6_CG4_SHIFT (8U)
7076#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
7077
7078#define CCM_CCGR6_CG5_MASK (0xC00U)
7079#define CCM_CCGR6_CG5_SHIFT (10U)
7080#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
7081
7082#define CCM_CCGR6_CG6_MASK (0x3000U)
7083#define CCM_CCGR6_CG6_SHIFT (12U)
7084#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
7085
7086#define CCM_CCGR6_CG7_MASK (0xC000U)
7087#define CCM_CCGR6_CG7_SHIFT (14U)
7088#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
7089
7090#define CCM_CCGR6_CG8_MASK (0x30000U)
7091#define CCM_CCGR6_CG8_SHIFT (16U)
7092#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
7093
7094#define CCM_CCGR6_CG9_MASK (0xC0000U)
7095#define CCM_CCGR6_CG9_SHIFT (18U)
7096#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
7097
7098#define CCM_CCGR6_CG10_MASK (0x300000U)
7099#define CCM_CCGR6_CG10_SHIFT (20U)
7100#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
7101
7102#define CCM_CCGR6_CG11_MASK (0xC00000U)
7103#define CCM_CCGR6_CG11_SHIFT (22U)
7104#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
7105
7106#define CCM_CCGR6_CG12_MASK (0x3000000U)
7107#define CCM_CCGR6_CG12_SHIFT (24U)
7108#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
7109
7110#define CCM_CCGR6_CG13_MASK (0xC000000U)
7111#define CCM_CCGR6_CG13_SHIFT (26U)
7112#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
7113
7114#define CCM_CCGR6_CG14_MASK (0x30000000U)
7115#define CCM_CCGR6_CG14_SHIFT (28U)
7116#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
7117
7118#define CCM_CCGR6_CG15_MASK (0xC0000000U)
7119#define CCM_CCGR6_CG15_SHIFT (30U)
7120#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
7126#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
7127#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
7132#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
7133
7134#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
7135#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
7140#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
7141
7142#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
7143#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
7148#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
7149
7150#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
7151#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
7156#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
7157
7158#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
7159#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
7164#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
7165
7166#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
7167#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
7172#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) /* end of group CCM_Register_Masks */
7179
7180
7181/* CCM - Peripheral instance base addresses */
7183#define CCM_BASE (0x400FC000u)
7185#define CCM ((CCM_Type *)CCM_BASE)
7187#define CCM_BASE_ADDRS { CCM_BASE }
7189#define CCM_BASE_PTRS { CCM }
7191#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
7192 /* end of group CCM_Peripheral_Access_Layer */
7196
7197
7198/* ----------------------------------------------------------------------------
7199 -- CCM_ANALOG Peripheral Access Layer
7200 ---------------------------------------------------------------------------- */
7201
7208typedef struct {
7209 __IO uint32_t PLL_ARM;
7210 __IO uint32_t PLL_ARM_SET;
7211 __IO uint32_t PLL_ARM_CLR;
7212 __IO uint32_t PLL_ARM_TOG;
7213 __IO uint32_t PLL_USB1;
7214 __IO uint32_t PLL_USB1_SET;
7215 __IO uint32_t PLL_USB1_CLR;
7216 __IO uint32_t PLL_USB1_TOG;
7217 __IO uint32_t PLL_USB2;
7218 __IO uint32_t PLL_USB2_SET;
7219 __IO uint32_t PLL_USB2_CLR;
7220 __IO uint32_t PLL_USB2_TOG;
7221 __IO uint32_t PLL_SYS;
7222 __IO uint32_t PLL_SYS_SET;
7223 __IO uint32_t PLL_SYS_CLR;
7224 __IO uint32_t PLL_SYS_TOG;
7225 __IO uint32_t PLL_SYS_SS;
7226 uint8_t RESERVED_0[12];
7227 __IO uint32_t PLL_SYS_NUM;
7228 uint8_t RESERVED_1[12];
7229 __IO uint32_t PLL_SYS_DENOM;
7230 uint8_t RESERVED_2[12];
7231 __IO uint32_t PLL_AUDIO;
7232 __IO uint32_t PLL_AUDIO_SET;
7233 __IO uint32_t PLL_AUDIO_CLR;
7234 __IO uint32_t PLL_AUDIO_TOG;
7235 __IO uint32_t PLL_AUDIO_NUM;
7236 uint8_t RESERVED_3[12];
7237 __IO uint32_t PLL_AUDIO_DENOM;
7238 uint8_t RESERVED_4[12];
7239 __IO uint32_t PLL_VIDEO;
7240 __IO uint32_t PLL_VIDEO_SET;
7241 __IO uint32_t PLL_VIDEO_CLR;
7242 __IO uint32_t PLL_VIDEO_TOG;
7243 __IO uint32_t PLL_VIDEO_NUM;
7244 uint8_t RESERVED_5[12];
7245 __IO uint32_t PLL_VIDEO_DENOM;
7246 uint8_t RESERVED_6[28];
7247 __IO uint32_t PLL_ENET;
7248 __IO uint32_t PLL_ENET_SET;
7249 __IO uint32_t PLL_ENET_CLR;
7250 __IO uint32_t PLL_ENET_TOG;
7251 __IO uint32_t PFD_480;
7252 __IO uint32_t PFD_480_SET;
7253 __IO uint32_t PFD_480_CLR;
7254 __IO uint32_t PFD_480_TOG;
7255 __IO uint32_t PFD_528;
7256 __IO uint32_t PFD_528_SET;
7257 __IO uint32_t PFD_528_CLR;
7258 __IO uint32_t PFD_528_TOG;
7259 uint8_t RESERVED_7[64];
7260 __IO uint32_t MISC0;
7261 __IO uint32_t MISC0_SET;
7262 __IO uint32_t MISC0_CLR;
7263 __IO uint32_t MISC0_TOG;
7264 __IO uint32_t MISC1;
7265 __IO uint32_t MISC1_SET;
7266 __IO uint32_t MISC1_CLR;
7267 __IO uint32_t MISC1_TOG;
7268 __IO uint32_t MISC2;
7269 __IO uint32_t MISC2_SET;
7270 __IO uint32_t MISC2_CLR;
7271 __IO uint32_t MISC2_TOG;
7272} CCM_ANALOG_Type;
7273
7274/* ----------------------------------------------------------------------------
7275 -- CCM_ANALOG Register Masks
7276 ---------------------------------------------------------------------------- */
7277
7286#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)
7287#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)
7288#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
7289
7290#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)
7291#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)
7292#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
7293
7294#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)
7295#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)
7296#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)
7297
7298#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)
7299#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)
7306#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
7307
7308#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)
7309#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)
7310#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
7311
7312#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)
7313#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)
7314#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)
7315
7316#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)
7317#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)
7318#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)
7324#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)
7325#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)
7326#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
7327
7328#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)
7329#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)
7330#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)
7331
7332#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)
7333#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)
7334#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)
7335
7336#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7337#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)
7344#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
7345
7346#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)
7347#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)
7348#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)
7349
7350#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)
7351#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)
7352#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)
7353
7354#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)
7355#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)
7356#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)
7362#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)
7363#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)
7364#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
7365
7366#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)
7367#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)
7368#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)
7369
7370#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)
7371#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)
7372#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)
7373
7374#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7375#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7382#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
7383
7384#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)
7385#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)
7386#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)
7387
7388#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)
7389#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)
7390#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)
7391
7392#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)
7393#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)
7394#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)
7400#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)
7401#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)
7402#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
7403
7404#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)
7405#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)
7406#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)
7407
7408#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)
7409#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)
7410#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)
7411
7412#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7413#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7420#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
7421
7422#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)
7423#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)
7424#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)
7425
7426#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)
7427#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)
7428#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)
7429
7430#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)
7431#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)
7432#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)
7438#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
7439#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
7440#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
7441
7442#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
7443#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
7448#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
7449
7450#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
7451#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
7452#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
7453
7454#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
7455#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
7456#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
7457
7458#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
7459#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
7464#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
7465
7466#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
7467#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
7468#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
7469
7470#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
7471#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
7472#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
7478#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
7479#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
7480#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
7481
7482#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
7483#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
7488#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
7489
7490#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
7491#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
7492#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
7493
7494#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
7495#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
7496#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
7497
7498#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7499#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
7504#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
7505
7506#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
7507#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
7508#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
7509
7510#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
7511#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
7512#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
7518#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
7519#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
7520#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
7521
7522#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
7523#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
7528#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
7529
7530#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
7531#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
7532#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
7533
7534#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
7535#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
7536#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
7537
7538#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7539#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7544#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
7545
7546#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
7547#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
7548#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
7549
7550#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
7551#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
7552#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
7558#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
7559#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
7560#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
7561
7562#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
7563#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
7568#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
7569
7570#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
7571#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
7572#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
7573
7574#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
7575#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
7576#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
7577
7578#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7579#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7584#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
7585
7586#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
7587#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
7588#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
7589
7590#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
7591#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
7592#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
7598#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U)
7599#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U)
7600#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)
7601
7602#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)
7603#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)
7604#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)
7605
7606#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)
7607#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)
7608#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)
7609
7610#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)
7611#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)
7612#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)
7613
7614#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)
7615#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)
7622#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
7623
7624#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)
7625#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)
7626#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)
7627
7628#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)
7629#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)
7630#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)
7636#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U)
7637#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U)
7638#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)
7639
7640#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)
7641#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)
7642#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)
7643
7644#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)
7645#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)
7646#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)
7647
7648#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)
7649#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)
7650#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)
7651
7652#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7653#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)
7660#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
7661
7662#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)
7663#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)
7664#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)
7665
7666#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)
7667#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)
7668#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)
7674#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U)
7675#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U)
7676#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)
7677
7678#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)
7679#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)
7680#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)
7681
7682#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)
7683#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)
7684#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)
7685
7686#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)
7687#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)
7688#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)
7689
7690#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7691#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7698#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
7699
7700#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)
7701#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)
7702#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)
7703
7704#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)
7705#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)
7706#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)
7712#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U)
7713#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U)
7714#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)
7715
7716#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)
7717#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)
7718#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)
7719
7720#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)
7721#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)
7722#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)
7723
7724#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)
7725#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)
7726#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)
7727
7728#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7729#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7736#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
7737
7738#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)
7739#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)
7740#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)
7741
7742#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)
7743#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)
7744#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)
7750#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
7751#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
7752#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
7753
7754#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
7755#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
7756#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
7757
7758#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
7759#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
7760#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
7761
7762#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
7763#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
7768#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
7769
7770#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
7771#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
7772#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
7773
7774#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
7775#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
7776#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
7782#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
7783#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
7784#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
7785
7786#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
7787#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
7788#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
7789
7790#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
7791#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
7792#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
7793
7794#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7795#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
7800#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
7801
7802#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
7803#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
7804#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
7805
7806#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
7807#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
7808#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
7814#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
7815#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
7816#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
7817
7818#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
7819#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
7820#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
7821
7822#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
7823#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
7824#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
7825
7826#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7827#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7832#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
7833
7834#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
7835#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
7836#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
7837
7838#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
7839#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
7840#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
7846#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
7847#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
7848#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
7849
7850#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
7851#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
7852#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
7853
7854#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
7855#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
7856#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
7857
7858#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7859#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7864#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
7865
7866#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
7867#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
7868#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
7869
7870#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
7871#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
7872#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
7878#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
7879#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
7880#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
7881
7882#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
7883#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
7888#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
7889
7890#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
7891#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
7892#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
7898#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
7899#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
7900#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
7906#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
7907#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
7908#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
7914#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
7915#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
7916#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
7917
7918#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
7919#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
7920#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
7921
7922#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
7923#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
7924#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
7925
7926#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
7927#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
7934#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
7935
7936#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
7937#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
7938#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
7939
7940#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
7941#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
7948#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
7949
7950#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
7951#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
7952#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
7958#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
7959#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
7960#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
7961
7962#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
7963#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
7964#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
7965
7966#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
7967#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
7968#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
7969
7970#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7971#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
7978#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
7979
7980#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
7981#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
7982#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
7983
7984#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
7985#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
7992#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
7993
7994#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
7995#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
7996#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
8002#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
8003#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
8004#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
8005
8006#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
8007#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
8008#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
8009
8010#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
8011#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
8012#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
8013
8014#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
8015#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
8022#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
8023
8024#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
8025#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
8026#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
8027
8028#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
8029#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
8036#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
8037
8038#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
8039#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
8040#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
8046#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
8047#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
8048#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
8049
8050#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
8051#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
8052#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
8053
8054#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
8055#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
8056#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
8057
8058#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
8059#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
8066#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
8067
8068#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
8069#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
8070#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
8071
8072#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
8073#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
8080#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
8081
8082#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
8083#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
8084#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
8090#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
8091#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
8092#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
8098#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
8099#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
8100#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
8106#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)
8107#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)
8108#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
8109
8110#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)
8111#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)
8112#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)
8113
8114#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)
8115#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)
8116#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)
8117
8118#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)
8119#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)
8126#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
8127
8128#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)
8129#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)
8130#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)
8131
8132#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)
8133#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)
8140#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
8141
8142#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)
8143#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)
8144#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)
8150#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)
8151#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)
8152#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
8153
8154#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)
8155#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)
8156#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)
8157
8158#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)
8159#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)
8160#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)
8161
8162#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
8163#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)
8170#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
8171
8172#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)
8173#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)
8174#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)
8175
8176#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)
8177#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)
8184#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
8185
8186#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)
8187#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)
8188#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)
8194#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)
8195#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)
8196#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
8197
8198#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)
8199#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)
8200#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)
8201
8202#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)
8203#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)
8204#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)
8205
8206#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
8207#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
8214#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
8215
8216#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)
8217#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)
8218#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)
8219
8220#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)
8221#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)
8228#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
8229
8230#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)
8231#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)
8232#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)
8238#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)
8239#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)
8240#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
8241
8242#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)
8243#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)
8244#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)
8245
8246#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)
8247#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)
8248#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)
8249
8250#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
8251#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
8258#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
8259
8260#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)
8261#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)
8262#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)
8263
8264#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)
8265#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)
8272#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
8273
8274#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)
8275#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)
8276#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)
8282#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)
8283#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)
8284#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
8290#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)
8291#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)
8292#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
8298#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)
8299#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)
8300#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
8301
8302#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
8303#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
8304#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
8305
8306#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)
8307#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)
8308#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
8309
8310#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
8311#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
8318#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
8319
8320#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
8321#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
8322#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
8323
8324#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
8325#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
8326#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
8327
8328#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
8329#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
8330#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
8336#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)
8337#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
8338#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
8339
8340#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
8341#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
8342#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
8343
8344#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)
8345#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)
8346#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
8347
8348#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
8349#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
8356#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
8357
8358#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
8359#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
8360#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
8361
8362#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
8363#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
8364#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
8365
8366#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
8367#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
8368#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
8374#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)
8375#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
8376#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
8377
8378#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
8379#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
8380#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
8381
8382#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)
8383#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)
8384#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
8385
8386#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
8387#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
8394#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
8395
8396#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
8397#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
8398#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
8399
8400#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
8401#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
8402#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
8403
8404#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
8405#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
8406#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
8412#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)
8413#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
8414#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
8415
8416#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
8417#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
8418#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
8419
8420#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)
8421#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)
8422#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
8423
8424#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
8425#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
8432#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
8433
8434#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
8435#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
8436#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
8437
8438#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
8439#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
8440#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
8441
8442#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
8443#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
8444#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
8450#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
8451#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
8452#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
8453
8454#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
8455#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
8456#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
8457
8458#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
8459#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
8460#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
8461
8462#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
8463#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
8464#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
8465
8466#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
8467#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
8468#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
8469
8470#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
8471#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
8472#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
8473
8474#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
8475#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
8476#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
8477
8478#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
8479#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
8480#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
8481
8482#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
8483#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
8484#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
8485
8486#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
8487#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
8488#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
8489
8490#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
8491#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
8492#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
8493
8494#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
8495#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
8496#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
8502#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
8503#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
8504#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
8505
8506#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
8507#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
8508#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
8509
8510#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
8511#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
8512#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
8513
8514#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
8515#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
8516#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
8517
8518#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
8519#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
8520#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
8521
8522#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
8523#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
8524#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
8525
8526#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
8527#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
8528#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
8529
8530#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
8531#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
8532#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
8533
8534#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
8535#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
8536#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
8537
8538#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
8539#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
8540#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
8541
8542#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
8543#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
8544#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
8545
8546#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
8547#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
8548#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
8554#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
8555#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
8556#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
8557
8558#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
8559#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
8560#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
8561
8562#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
8563#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
8564#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
8565
8566#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
8567#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
8568#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
8569
8570#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
8571#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
8572#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
8573
8574#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
8575#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
8576#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
8577
8578#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
8579#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
8580#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
8581
8582#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
8583#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
8584#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
8585
8586#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
8587#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
8588#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
8589
8590#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
8591#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
8592#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
8593
8594#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
8595#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
8596#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
8597
8598#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
8599#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
8600#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
8606#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
8607#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
8608#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
8609
8610#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
8611#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
8612#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
8613
8614#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
8615#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
8616#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
8617
8618#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
8619#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
8620#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
8621
8622#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
8623#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
8624#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
8625
8626#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
8627#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
8628#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
8629
8630#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
8631#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
8632#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
8633
8634#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
8635#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
8636#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
8637
8638#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
8639#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
8640#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
8641
8642#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
8643#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
8644#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
8645
8646#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
8647#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
8648#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
8649
8650#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
8651#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
8652#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
8658#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
8659#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
8660#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
8661
8662#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
8663#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
8664#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
8665
8666#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
8667#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
8668#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
8669
8670#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
8671#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
8672#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
8673
8674#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
8675#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
8676#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
8677
8678#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
8679#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
8680#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
8681
8682#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
8683#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
8684#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
8685
8686#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
8687#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
8688#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
8689
8690#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
8691#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
8692#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
8693
8694#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
8695#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
8696#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
8697
8698#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
8699#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
8700#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
8701
8702#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
8703#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
8704#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
8710#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
8711#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
8712#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
8713
8714#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
8715#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
8716#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
8717
8718#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
8719#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
8720#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
8721
8722#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
8723#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
8724#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
8725
8726#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
8727#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
8728#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
8729
8730#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
8731#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
8732#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
8733
8734#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
8735#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
8736#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
8737
8738#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
8739#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
8740#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
8741
8742#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
8743#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
8744#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
8745
8746#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
8747#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
8748#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
8749
8750#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
8751#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
8752#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
8753
8754#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
8755#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
8756#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
8762#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
8763#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
8764#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
8765
8766#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
8767#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
8768#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
8769
8770#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
8771#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
8772#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
8773
8774#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
8775#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
8776#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
8777
8778#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
8779#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
8780#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
8781
8782#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
8783#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
8784#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
8785
8786#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
8787#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
8788#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
8789
8790#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
8791#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
8792#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
8793
8794#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
8795#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
8796#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
8797
8798#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
8799#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
8800#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
8801
8802#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
8803#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
8804#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
8805
8806#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
8807#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
8808#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
8814#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
8815#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
8816#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
8817
8818#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
8819#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
8820#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
8821
8822#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
8823#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
8824#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
8825
8826#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
8827#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
8828#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
8829
8830#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
8831#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
8832#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
8833
8834#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
8835#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
8836#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
8837
8838#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
8839#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
8840#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
8841
8842#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
8843#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
8844#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
8845
8846#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
8847#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
8848#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
8849
8850#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
8851#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
8852#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
8853
8854#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
8855#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
8856#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
8857
8858#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
8859#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
8860#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
8866#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
8867#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
8868#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
8869
8870#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
8871#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
8876#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
8877
8878#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
8879#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
8890#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
8891
8892#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
8893#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
8894#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
8895
8896#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
8897#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
8905#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
8906
8907#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
8908#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
8913#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
8914
8915#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
8916#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
8923#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
8924
8925#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
8926#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
8927#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
8928
8929#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
8930#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
8931#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
8932
8933#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
8934#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
8939#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
8940
8941#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
8942#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
8953#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
8954
8955#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
8956#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
8961#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
8962
8963#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
8964#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
8965#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
8971#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
8972#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
8973#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
8974
8975#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
8976#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
8981#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
8982
8983#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
8984#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
8995#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
8996
8997#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
8998#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
8999#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
9000
9001#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
9002#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
9010#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
9011
9012#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
9013#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
9018#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
9019
9020#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
9021#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
9028#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
9029
9030#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
9031#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
9032#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
9033
9034#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
9035#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
9036#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
9037
9038#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
9039#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
9044#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
9045
9046#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
9047#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
9058#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
9059
9060#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
9061#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
9066#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
9067
9068#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
9069#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
9070#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
9076#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
9077#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
9078#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
9079
9080#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
9081#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
9086#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
9087
9088#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
9089#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
9100#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
9101
9102#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
9103#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
9104#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
9105
9106#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
9107#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
9115#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
9116
9117#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
9118#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
9123#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
9124
9125#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
9126#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
9133#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
9134
9135#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
9136#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
9137#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
9138
9139#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
9140#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
9141#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
9142
9143#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
9144#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
9149#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
9150
9151#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
9152#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
9163#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
9164
9165#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
9166#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
9171#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
9172
9173#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
9174#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
9175#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
9181#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
9182#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
9183#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
9184
9185#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
9186#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
9191#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
9192
9193#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
9194#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
9205#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
9206
9207#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
9208#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
9209#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
9210
9211#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
9212#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
9220#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
9221
9222#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
9223#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
9228#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
9229
9230#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)
9231#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)
9238#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
9239
9240#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
9241#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
9242#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
9243
9244#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
9245#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
9246#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
9247
9248#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
9249#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
9254#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
9255
9256#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
9257#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
9268#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
9269
9270#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
9271#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
9276#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
9277
9278#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
9279#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
9280#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
9286#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
9287#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
9306#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
9307
9308#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
9309#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
9310#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)
9311
9312#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
9313#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
9314#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)
9315
9316#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9317#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
9318#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
9319
9320#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9321#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
9322#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
9323
9324#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
9325#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
9326#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
9327
9328#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
9329#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)
9330#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
9331
9332#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
9333#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
9334#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
9335
9336#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
9337#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)
9338#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
9339
9340#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
9341#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)
9342#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
9348#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
9349#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
9368#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
9369
9370#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
9371#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
9372#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)
9373
9374#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
9375#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
9376#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)
9377
9378#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9379#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
9380#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
9381
9382#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9383#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
9384#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
9385
9386#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
9387#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
9388#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
9389
9390#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
9391#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
9392#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
9393
9394#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
9395#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
9396#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
9397
9398#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
9399#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
9400#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
9401
9402#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
9403#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
9404#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
9410#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
9411#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
9430#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
9431
9432#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
9433#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
9434#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)
9435
9436#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
9437#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
9438#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)
9439
9440#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9441#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
9442#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
9443
9444#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9445#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
9446#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
9447
9448#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
9449#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
9450#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
9451
9452#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
9453#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
9454#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
9455
9456#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
9457#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
9458#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
9459
9460#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
9461#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
9462#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
9463
9464#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
9465#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
9466#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
9472#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
9473#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
9492#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
9493
9494#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
9495#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
9496#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)
9497
9498#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
9499#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
9500#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)
9501
9502#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9503#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
9504#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
9505
9506#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9507#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
9508#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
9509
9510#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
9511#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
9512#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
9513
9514#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
9515#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
9516#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
9517
9518#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
9519#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
9520#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
9521
9522#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
9523#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
9524#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
9525
9526#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
9527#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
9528#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
9534#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)
9535#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)
9540#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
9541
9542#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)
9543#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)
9547#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
9548
9549#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)
9550#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)
9551#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
9552
9553#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)
9554#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)
9555#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
9556
9557#define CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U)
9558#define CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U)
9563#define CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK)
9564
9565#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)
9566#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)
9571#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
9572
9573#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)
9574#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)
9578#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
9579
9580#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
9581#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)
9582#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
9583
9584#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)
9585#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)
9586#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
9587
9588#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
9589#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
9594#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
9595
9596#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
9597#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)
9602#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
9603
9604#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)
9605#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)
9606#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
9607
9608#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
9609#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)
9610#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
9611
9612#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)
9613#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)
9614#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
9615
9616#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
9617#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
9622#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
9623
9624#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
9625#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)
9632#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
9633
9634#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
9635#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)
9642#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
9643
9644#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
9645#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)
9652#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
9653
9654#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)
9655#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)
9662#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
9668#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
9669#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
9674#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
9675
9676#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
9677#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
9681#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
9682
9683#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
9684#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
9685#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
9686
9687#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)
9688#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)
9689#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
9690
9691#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U)
9692#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U)
9697#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK)
9698
9699#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
9700#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
9705#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
9706
9707#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
9708#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
9712#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
9713
9714#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
9715#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
9716#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
9717
9718#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)
9719#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)
9720#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
9721
9722#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
9723#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
9728#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
9729
9730#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
9731#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
9736#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
9737
9738#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
9739#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
9740#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
9741
9742#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
9743#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
9744#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
9745
9746#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)
9747#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)
9748#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
9749
9750#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
9751#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
9756#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
9757
9758#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
9759#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
9766#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
9767
9768#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
9769#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
9776#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
9777
9778#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
9779#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
9786#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
9787
9788#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
9789#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)
9796#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
9802#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
9803#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
9808#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
9809
9810#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
9811#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
9815#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
9816
9817#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
9818#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
9819#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
9820
9821#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)
9822#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)
9823#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
9824
9825#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U)
9826#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U)
9831#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK)
9832
9833#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
9834#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
9839#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
9840
9841#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
9842#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
9846#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
9847
9848#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
9849#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
9850#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
9851
9852#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)
9853#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)
9854#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
9855
9856#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
9857#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
9862#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
9863
9864#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
9865#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
9870#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
9871
9872#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
9873#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
9874#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
9875
9876#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
9877#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
9878#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
9879
9880#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)
9881#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)
9882#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
9883
9884#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
9885#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
9890#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
9891
9892#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
9893#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
9900#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
9901
9902#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
9903#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
9910#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
9911
9912#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
9913#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
9920#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
9921
9922#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
9923#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
9930#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
9936#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
9937#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
9942#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
9943
9944#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
9945#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
9949#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
9950
9951#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
9952#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
9953#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
9954
9955#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)
9956#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)
9957#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
9958
9959#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U)
9960#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U)
9965#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK)
9966
9967#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
9968#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
9973#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
9974
9975#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
9976#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
9980#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
9981
9982#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
9983#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
9984#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
9985
9986#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)
9987#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)
9988#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
9989
9990#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
9991#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
9996#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
9997
9998#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
9999#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
10004#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
10005
10006#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
10007#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
10008#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
10009
10010#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
10011#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
10012#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
10013
10014#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)
10015#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)
10016#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
10017
10018#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
10019#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
10024#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
10025
10026#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
10027#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
10034#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
10035
10036#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
10037#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
10044#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
10045
10046#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
10047#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
10054#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
10055
10056#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
10057#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
10064#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) /* end of group CCM_ANALOG_Register_Masks */
10071
10072
10073/* CCM_ANALOG - Peripheral instance base addresses */
10075#define CCM_ANALOG_BASE (0x400D8000u)
10077#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
10079#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
10081#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
10082 /* end of group CCM_ANALOG_Peripheral_Access_Layer */
10086
10087
10088/* ----------------------------------------------------------------------------
10089 -- CM7_MCM Peripheral Access Layer
10090 ---------------------------------------------------------------------------- */
10091
10098typedef struct {
10099 uint8_t RESERVED_0[16];
10100 __IO uint32_t ISCR;
10101} CM7_MCM_Type;
10102
10103/* ----------------------------------------------------------------------------
10104 -- CM7_MCM Register Masks
10105 ---------------------------------------------------------------------------- */
10106
10115#define CM7_MCM_ISCR_WABS_MASK (0x20U)
10116#define CM7_MCM_ISCR_WABS_SHIFT (5U)
10121#define CM7_MCM_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABS_SHIFT)) & CM7_MCM_ISCR_WABS_MASK)
10122
10123#define CM7_MCM_ISCR_WABSO_MASK (0x40U)
10124#define CM7_MCM_ISCR_WABSO_SHIFT (6U)
10129#define CM7_MCM_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABSO_SHIFT)) & CM7_MCM_ISCR_WABSO_MASK)
10130
10131#define CM7_MCM_ISCR_FIOC_MASK (0x100U)
10132#define CM7_MCM_ISCR_FIOC_SHIFT (8U)
10137#define CM7_MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOC_SHIFT)) & CM7_MCM_ISCR_FIOC_MASK)
10138
10139#define CM7_MCM_ISCR_FDZC_MASK (0x200U)
10140#define CM7_MCM_ISCR_FDZC_SHIFT (9U)
10145#define CM7_MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZC_SHIFT)) & CM7_MCM_ISCR_FDZC_MASK)
10146
10147#define CM7_MCM_ISCR_FOFC_MASK (0x400U)
10148#define CM7_MCM_ISCR_FOFC_SHIFT (10U)
10153#define CM7_MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFC_SHIFT)) & CM7_MCM_ISCR_FOFC_MASK)
10154
10155#define CM7_MCM_ISCR_FUFC_MASK (0x800U)
10156#define CM7_MCM_ISCR_FUFC_SHIFT (11U)
10161#define CM7_MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFC_SHIFT)) & CM7_MCM_ISCR_FUFC_MASK)
10162
10163#define CM7_MCM_ISCR_FIXC_MASK (0x1000U)
10164#define CM7_MCM_ISCR_FIXC_SHIFT (12U)
10169#define CM7_MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXC_SHIFT)) & CM7_MCM_ISCR_FIXC_MASK)
10170
10171#define CM7_MCM_ISCR_FIDC_MASK (0x8000U)
10172#define CM7_MCM_ISCR_FIDC_SHIFT (15U)
10177#define CM7_MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDC_SHIFT)) & CM7_MCM_ISCR_FIDC_MASK)
10178
10179#define CM7_MCM_ISCR_WABE_MASK (0x200000U)
10180#define CM7_MCM_ISCR_WABE_SHIFT (21U)
10185#define CM7_MCM_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABE_SHIFT)) & CM7_MCM_ISCR_WABE_MASK)
10186
10187#define CM7_MCM_ISCR_FIOCE_MASK (0x1000000U)
10188#define CM7_MCM_ISCR_FIOCE_SHIFT (24U)
10193#define CM7_MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOCE_SHIFT)) & CM7_MCM_ISCR_FIOCE_MASK)
10194
10195#define CM7_MCM_ISCR_FDZCE_MASK (0x2000000U)
10196#define CM7_MCM_ISCR_FDZCE_SHIFT (25U)
10201#define CM7_MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZCE_SHIFT)) & CM7_MCM_ISCR_FDZCE_MASK)
10202
10203#define CM7_MCM_ISCR_FOFCE_MASK (0x4000000U)
10204#define CM7_MCM_ISCR_FOFCE_SHIFT (26U)
10209#define CM7_MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFCE_SHIFT)) & CM7_MCM_ISCR_FOFCE_MASK)
10210
10211#define CM7_MCM_ISCR_FUFCE_MASK (0x8000000U)
10212#define CM7_MCM_ISCR_FUFCE_SHIFT (27U)
10217#define CM7_MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFCE_SHIFT)) & CM7_MCM_ISCR_FUFCE_MASK)
10218
10219#define CM7_MCM_ISCR_FIXCE_MASK (0x10000000U)
10220#define CM7_MCM_ISCR_FIXCE_SHIFT (28U)
10225#define CM7_MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXCE_SHIFT)) & CM7_MCM_ISCR_FIXCE_MASK)
10226
10227#define CM7_MCM_ISCR_FIDCE_MASK (0x80000000U)
10228#define CM7_MCM_ISCR_FIDCE_SHIFT (31U)
10233#define CM7_MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDCE_SHIFT)) & CM7_MCM_ISCR_FIDCE_MASK) /* end of group CM7_MCM_Register_Masks */
10240
10241
10242/* CM7_MCM - Peripheral instance base addresses */
10244#define CM7_MCM_BASE (0xE0080000u)
10246#define CM7_MCM ((CM7_MCM_Type *)CM7_MCM_BASE)
10248#define CM7_MCM_BASE_ADDRS { CM7_MCM_BASE }
10250#define CM7_MCM_BASE_PTRS { CM7_MCM }
10251 /* end of group CM7_MCM_Peripheral_Access_Layer */
10255
10256
10257/* ----------------------------------------------------------------------------
10258 -- CMP Peripheral Access Layer
10259 ---------------------------------------------------------------------------- */
10260
10267typedef struct {
10268 __IO uint8_t CR0;
10269 __IO uint8_t CR1;
10270 __IO uint8_t FPR;
10271 __IO uint8_t SCR;
10272 __IO uint8_t DACCR;
10273 __IO uint8_t MUXCR;
10274} CMP_Type;
10275
10276/* ----------------------------------------------------------------------------
10277 -- CMP Register Masks
10278 ---------------------------------------------------------------------------- */
10279
10288#define CMP_CR0_HYSTCTR_MASK (0x3U)
10289#define CMP_CR0_HYSTCTR_SHIFT (0U)
10296#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
10297
10298#define CMP_CR0_FILTER_CNT_MASK (0x70U)
10299#define CMP_CR0_FILTER_CNT_SHIFT (4U)
10310#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
10316#define CMP_CR1_EN_MASK (0x1U)
10317#define CMP_CR1_EN_SHIFT (0U)
10322#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
10323
10324#define CMP_CR1_OPE_MASK (0x2U)
10325#define CMP_CR1_OPE_SHIFT (1U)
10332#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
10333
10334#define CMP_CR1_COS_MASK (0x4U)
10335#define CMP_CR1_COS_SHIFT (2U)
10340#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
10341
10342#define CMP_CR1_INV_MASK (0x8U)
10343#define CMP_CR1_INV_SHIFT (3U)
10348#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
10349
10350#define CMP_CR1_PMODE_MASK (0x10U)
10351#define CMP_CR1_PMODE_SHIFT (4U)
10356#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
10357
10358#define CMP_CR1_WE_MASK (0x40U)
10359#define CMP_CR1_WE_SHIFT (6U)
10364#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
10365
10366#define CMP_CR1_SE_MASK (0x80U)
10367#define CMP_CR1_SE_SHIFT (7U)
10372#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
10378#define CMP_FPR_FILT_PER_MASK (0xFFU)
10379#define CMP_FPR_FILT_PER_SHIFT (0U)
10382#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
10388#define CMP_SCR_COUT_MASK (0x1U)
10389#define CMP_SCR_COUT_SHIFT (0U)
10392#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
10393
10394#define CMP_SCR_CFF_MASK (0x2U)
10395#define CMP_SCR_CFF_SHIFT (1U)
10400#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
10401
10402#define CMP_SCR_CFR_MASK (0x4U)
10403#define CMP_SCR_CFR_SHIFT (2U)
10408#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
10409
10410#define CMP_SCR_IEF_MASK (0x8U)
10411#define CMP_SCR_IEF_SHIFT (3U)
10416#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
10417
10418#define CMP_SCR_IER_MASK (0x10U)
10419#define CMP_SCR_IER_SHIFT (4U)
10424#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
10425
10426#define CMP_SCR_DMAEN_MASK (0x40U)
10427#define CMP_SCR_DMAEN_SHIFT (6U)
10432#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
10438#define CMP_DACCR_VOSEL_MASK (0x3FU)
10439#define CMP_DACCR_VOSEL_SHIFT (0U)
10442#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
10443
10444#define CMP_DACCR_VRSEL_MASK (0x40U)
10445#define CMP_DACCR_VRSEL_SHIFT (6U)
10450#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
10451
10452#define CMP_DACCR_DACEN_MASK (0x80U)
10453#define CMP_DACCR_DACEN_SHIFT (7U)
10458#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
10464#define CMP_MUXCR_MSEL_MASK (0x7U)
10465#define CMP_MUXCR_MSEL_SHIFT (0U)
10476#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
10477
10478#define CMP_MUXCR_PSEL_MASK (0x38U)
10479#define CMP_MUXCR_PSEL_SHIFT (3U)
10490#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) /* end of group CMP_Register_Masks */
10497
10498
10499/* CMP - Peripheral instance base addresses */
10501#define CMP1_BASE (0x40094000u)
10503#define CMP1 ((CMP_Type *)CMP1_BASE)
10505#define CMP2_BASE (0x40094008u)
10507#define CMP2 ((CMP_Type *)CMP2_BASE)
10509#define CMP3_BASE (0x40094010u)
10511#define CMP3 ((CMP_Type *)CMP3_BASE)
10513#define CMP4_BASE (0x40094018u)
10515#define CMP4 ((CMP_Type *)CMP4_BASE)
10517#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
10519#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
10521#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
10522 /* end of group CMP_Peripheral_Access_Layer */
10526
10527
10528/* ----------------------------------------------------------------------------
10529 -- CSI Peripheral Access Layer
10530 ---------------------------------------------------------------------------- */
10531
10538typedef struct {
10539 __IO uint32_t CR1;
10540 __IO uint32_t CR2;
10541 __IO uint32_t CR3;
10542 __I uint32_t STATFIFO;
10543 __I uint32_t RFIFO;
10544 __IO uint32_t RXCNT;
10545 __IO uint32_t SR;
10546 uint8_t RESERVED_0[4];
10547 __IO uint32_t DMASA_STATFIFO;
10548 __IO uint32_t DMATS_STATFIFO;
10549 __IO uint32_t DMASA_FB1;
10550 __IO uint32_t DMASA_FB2;
10551 __IO uint32_t FBUF_PARA;
10552 __IO uint32_t IMAG_PARA;
10553 uint8_t RESERVED_1[16];
10554 __IO uint32_t CR18;
10555 __IO uint32_t CR19;
10556} CSI_Type;
10557
10558/* ----------------------------------------------------------------------------
10559 -- CSI Register Masks
10560 ---------------------------------------------------------------------------- */
10561
10570#define CSI_CR1_PIXEL_BIT_MASK (0x1U)
10571#define CSI_CR1_PIXEL_BIT_SHIFT (0U)
10576#define CSI_CR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PIXEL_BIT_SHIFT)) & CSI_CR1_PIXEL_BIT_MASK)
10577
10578#define CSI_CR1_REDGE_MASK (0x2U)
10579#define CSI_CR1_REDGE_SHIFT (1U)
10584#define CSI_CR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_REDGE_SHIFT)) & CSI_CR1_REDGE_MASK)
10585
10586#define CSI_CR1_INV_PCLK_MASK (0x4U)
10587#define CSI_CR1_INV_PCLK_SHIFT (2U)
10592#define CSI_CR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_PCLK_SHIFT)) & CSI_CR1_INV_PCLK_MASK)
10593
10594#define CSI_CR1_INV_DATA_MASK (0x8U)
10595#define CSI_CR1_INV_DATA_SHIFT (3U)
10600#define CSI_CR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_DATA_SHIFT)) & CSI_CR1_INV_DATA_MASK)
10601
10602#define CSI_CR1_GCLK_MODE_MASK (0x10U)
10603#define CSI_CR1_GCLK_MODE_SHIFT (4U)
10608#define CSI_CR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_GCLK_MODE_SHIFT)) & CSI_CR1_GCLK_MODE_MASK)
10609
10610#define CSI_CR1_CLR_RXFIFO_MASK (0x20U)
10611#define CSI_CR1_CLR_RXFIFO_SHIFT (5U)
10612#define CSI_CR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_RXFIFO_SHIFT)) & CSI_CR1_CLR_RXFIFO_MASK)
10613
10614#define CSI_CR1_CLR_STATFIFO_MASK (0x40U)
10615#define CSI_CR1_CLR_STATFIFO_SHIFT (6U)
10616#define CSI_CR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_STATFIFO_SHIFT)) & CSI_CR1_CLR_STATFIFO_MASK)
10617
10618#define CSI_CR1_PACK_DIR_MASK (0x80U)
10619#define CSI_CR1_PACK_DIR_SHIFT (7U)
10626#define CSI_CR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PACK_DIR_SHIFT)) & CSI_CR1_PACK_DIR_MASK)
10627
10628#define CSI_CR1_FCC_MASK (0x100U)
10629#define CSI_CR1_FCC_SHIFT (8U)
10634#define CSI_CR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FCC_SHIFT)) & CSI_CR1_FCC_MASK)
10635
10636#define CSI_CR1_CCIR_EN_MASK (0x400U)
10637#define CSI_CR1_CCIR_EN_SHIFT (10U)
10642#define CSI_CR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CCIR_EN_SHIFT)) & CSI_CR1_CCIR_EN_MASK)
10643
10644#define CSI_CR1_HSYNC_POL_MASK (0x800U)
10645#define CSI_CR1_HSYNC_POL_SHIFT (11U)
10650#define CSI_CR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HSYNC_POL_SHIFT)) & CSI_CR1_HSYNC_POL_MASK)
10651
10652#define CSI_CR1_SOF_INTEN_MASK (0x10000U)
10653#define CSI_CR1_SOF_INTEN_SHIFT (16U)
10658#define CSI_CR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_INTEN_SHIFT)) & CSI_CR1_SOF_INTEN_MASK)
10659
10660#define CSI_CR1_SOF_POL_MASK (0x20000U)
10661#define CSI_CR1_SOF_POL_SHIFT (17U)
10666#define CSI_CR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_POL_SHIFT)) & CSI_CR1_SOF_POL_MASK)
10667
10668#define CSI_CR1_RXFF_INTEN_MASK (0x40000U)
10669#define CSI_CR1_RXFF_INTEN_SHIFT (18U)
10674#define CSI_CR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RXFF_INTEN_SHIFT)) & CSI_CR1_RXFF_INTEN_MASK)
10675
10676#define CSI_CR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
10677#define CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
10682#define CSI_CR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB1_DMA_DONE_INTEN_MASK)
10683
10684#define CSI_CR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
10685#define CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
10690#define CSI_CR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB2_DMA_DONE_INTEN_MASK)
10691
10692#define CSI_CR1_STATFF_INTEN_MASK (0x200000U)
10693#define CSI_CR1_STATFF_INTEN_SHIFT (21U)
10698#define CSI_CR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_STATFF_INTEN_SHIFT)) & CSI_CR1_STATFF_INTEN_MASK)
10699
10700#define CSI_CR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
10701#define CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
10706#define CSI_CR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_SFF_DMA_DONE_INTEN_MASK)
10707
10708#define CSI_CR1_RF_OR_INTEN_MASK (0x1000000U)
10709#define CSI_CR1_RF_OR_INTEN_SHIFT (24U)
10714#define CSI_CR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RF_OR_INTEN_SHIFT)) & CSI_CR1_RF_OR_INTEN_MASK)
10715
10716#define CSI_CR1_SF_OR_INTEN_MASK (0x2000000U)
10717#define CSI_CR1_SF_OR_INTEN_SHIFT (25U)
10722#define CSI_CR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SF_OR_INTEN_SHIFT)) & CSI_CR1_SF_OR_INTEN_MASK)
10723
10724#define CSI_CR1_COF_INT_EN_MASK (0x4000000U)
10725#define CSI_CR1_COF_INT_EN_SHIFT (26U)
10730#define CSI_CR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_COF_INT_EN_SHIFT)) & CSI_CR1_COF_INT_EN_MASK)
10731
10732#define CSI_CR1_CCIR_MODE_MASK (0x8000000U)
10733#define CSI_CR1_CCIR_MODE_SHIFT (27U)
10738#define CSI_CR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CCIR_MODE_SHIFT)) & CSI_CR1_CCIR_MODE_MASK)
10739
10740#define CSI_CR1_PrP_IF_EN_MASK (0x10000000U)
10741#define CSI_CR1_PrP_IF_EN_SHIFT (28U)
10746#define CSI_CR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PrP_IF_EN_SHIFT)) & CSI_CR1_PrP_IF_EN_MASK)
10747
10748#define CSI_CR1_EOF_INT_EN_MASK (0x20000000U)
10749#define CSI_CR1_EOF_INT_EN_SHIFT (29U)
10754#define CSI_CR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EOF_INT_EN_SHIFT)) & CSI_CR1_EOF_INT_EN_MASK)
10755
10756#define CSI_CR1_EXT_VSYNC_MASK (0x40000000U)
10757#define CSI_CR1_EXT_VSYNC_SHIFT (30U)
10762#define CSI_CR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EXT_VSYNC_SHIFT)) & CSI_CR1_EXT_VSYNC_MASK)
10763
10764#define CSI_CR1_SWAP16_EN_MASK (0x80000000U)
10765#define CSI_CR1_SWAP16_EN_SHIFT (31U)
10770#define CSI_CR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SWAP16_EN_SHIFT)) & CSI_CR1_SWAP16_EN_MASK)
10776#define CSI_CR2_HSC_MASK (0xFFU)
10777#define CSI_CR2_HSC_SHIFT (0U)
10781#define CSI_CR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_HSC_SHIFT)) & CSI_CR2_HSC_MASK)
10782
10783#define CSI_CR2_VSC_MASK (0xFF00U)
10784#define CSI_CR2_VSC_SHIFT (8U)
10788#define CSI_CR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_VSC_SHIFT)) & CSI_CR2_VSC_MASK)
10789
10790#define CSI_CR2_LVRM_MASK (0x70000U)
10791#define CSI_CR2_LVRM_SHIFT (16U)
10801#define CSI_CR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_LVRM_SHIFT)) & CSI_CR2_LVRM_MASK)
10802
10803#define CSI_CR2_BTS_MASK (0x180000U)
10804#define CSI_CR2_BTS_SHIFT (19U)
10811#define CSI_CR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_BTS_SHIFT)) & CSI_CR2_BTS_MASK)
10812
10813#define CSI_CR2_SCE_MASK (0x800000U)
10814#define CSI_CR2_SCE_SHIFT (23U)
10819#define CSI_CR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_SCE_SHIFT)) & CSI_CR2_SCE_MASK)
10820
10821#define CSI_CR2_AFS_MASK (0x3000000U)
10822#define CSI_CR2_AFS_SHIFT (24U)
10828#define CSI_CR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_AFS_SHIFT)) & CSI_CR2_AFS_MASK)
10829
10830#define CSI_CR2_DRM_MASK (0x4000000U)
10831#define CSI_CR2_DRM_SHIFT (26U)
10836#define CSI_CR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DRM_SHIFT)) & CSI_CR2_DRM_MASK)
10837
10838#define CSI_CR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
10839#define CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
10845#define CSI_CR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_SFF_MASK)
10846
10847#define CSI_CR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
10848#define CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
10854#define CSI_CR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_RFF_MASK)
10860#define CSI_CR3_ECC_AUTO_EN_MASK (0x1U)
10861#define CSI_CR3_ECC_AUTO_EN_SHIFT (0U)
10866#define CSI_CR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_AUTO_EN_SHIFT)) & CSI_CR3_ECC_AUTO_EN_MASK)
10867
10868#define CSI_CR3_ECC_INT_EN_MASK (0x2U)
10869#define CSI_CR3_ECC_INT_EN_SHIFT (1U)
10874#define CSI_CR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_INT_EN_SHIFT)) & CSI_CR3_ECC_INT_EN_MASK)
10875
10876#define CSI_CR3_ZERO_PACK_EN_MASK (0x4U)
10877#define CSI_CR3_ZERO_PACK_EN_SHIFT (2U)
10882#define CSI_CR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ZERO_PACK_EN_SHIFT)) & CSI_CR3_ZERO_PACK_EN_MASK)
10883
10884#define CSI_CR3_SENSOR_16BITS_MASK (0x8U)
10885#define CSI_CR3_SENSOR_16BITS_SHIFT (3U)
10890#define CSI_CR3_SENSOR_16BITS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_SENSOR_16BITS_SHIFT)) & CSI_CR3_SENSOR_16BITS_MASK)
10891
10892#define CSI_CR3_RxFF_LEVEL_MASK (0x70U)
10893#define CSI_CR3_RxFF_LEVEL_SHIFT (4U)
10904#define CSI_CR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_RxFF_LEVEL_SHIFT)) & CSI_CR3_RxFF_LEVEL_MASK)
10905
10906#define CSI_CR3_HRESP_ERR_EN_MASK (0x80U)
10907#define CSI_CR3_HRESP_ERR_EN_SHIFT (7U)
10912#define CSI_CR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_HRESP_ERR_EN_SHIFT)) & CSI_CR3_HRESP_ERR_EN_MASK)
10913
10914#define CSI_CR3_STATFF_LEVEL_MASK (0x700U)
10915#define CSI_CR3_STATFF_LEVEL_SHIFT (8U)
10926#define CSI_CR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_STATFF_LEVEL_SHIFT)) & CSI_CR3_STATFF_LEVEL_MASK)
10927
10928#define CSI_CR3_DMA_REQ_EN_SFF_MASK (0x800U)
10929#define CSI_CR3_DMA_REQ_EN_SFF_SHIFT (11U)
10934#define CSI_CR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_SFF_MASK)
10935
10936#define CSI_CR3_DMA_REQ_EN_RFF_MASK (0x1000U)
10937#define CSI_CR3_DMA_REQ_EN_RFF_SHIFT (12U)
10942#define CSI_CR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_RFF_MASK)
10943
10944#define CSI_CR3_DMA_REFLASH_SFF_MASK (0x2000U)
10945#define CSI_CR3_DMA_REFLASH_SFF_SHIFT (13U)
10950#define CSI_CR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CR3_DMA_REFLASH_SFF_MASK)
10951
10952#define CSI_CR3_DMA_REFLASH_RFF_MASK (0x4000U)
10953#define CSI_CR3_DMA_REFLASH_RFF_SHIFT (14U)
10958#define CSI_CR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CR3_DMA_REFLASH_RFF_MASK)
10959
10960#define CSI_CR3_FRMCNT_RST_MASK (0x8000U)
10961#define CSI_CR3_FRMCNT_RST_SHIFT (15U)
10966#define CSI_CR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_RST_SHIFT)) & CSI_CR3_FRMCNT_RST_MASK)
10967
10968#define CSI_CR3_FRMCNT_MASK (0xFFFF0000U)
10969#define CSI_CR3_FRMCNT_SHIFT (16U)
10970#define CSI_CR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_SHIFT)) & CSI_CR3_FRMCNT_MASK)
10976#define CSI_STATFIFO_STAT_MASK (0xFFFFFFFFU)
10977#define CSI_STATFIFO_STAT_SHIFT (0U)
10978#define CSI_STATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_STATFIFO_STAT_SHIFT)) & CSI_STATFIFO_STAT_MASK)
10984#define CSI_RFIFO_IMAGE_MASK (0xFFFFFFFFU)
10985#define CSI_RFIFO_IMAGE_SHIFT (0U)
10986#define CSI_RFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_RFIFO_IMAGE_SHIFT)) & CSI_RFIFO_IMAGE_MASK)
10992#define CSI_RXCNT_RXCNT_MASK (0x3FFFFFU)
10993#define CSI_RXCNT_RXCNT_SHIFT (0U)
10994#define CSI_RXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_RXCNT_RXCNT_SHIFT)) & CSI_RXCNT_RXCNT_MASK)
11000#define CSI_SR_DRDY_MASK (0x1U)
11001#define CSI_SR_DRDY_SHIFT (0U)
11006#define CSI_SR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DRDY_SHIFT)) & CSI_SR_DRDY_MASK)
11007
11008#define CSI_SR_ECC_INT_MASK (0x2U)
11009#define CSI_SR_ECC_INT_SHIFT (1U)
11014#define CSI_SR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_ECC_INT_SHIFT)) & CSI_SR_ECC_INT_MASK)
11015
11016#define CSI_SR_HRESP_ERR_INT_MASK (0x80U)
11017#define CSI_SR_HRESP_ERR_INT_SHIFT (7U)
11022#define CSI_SR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_HRESP_ERR_INT_SHIFT)) & CSI_SR_HRESP_ERR_INT_MASK)
11023
11024#define CSI_SR_COF_INT_MASK (0x2000U)
11025#define CSI_SR_COF_INT_SHIFT (13U)
11030#define CSI_SR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_COF_INT_SHIFT)) & CSI_SR_COF_INT_MASK)
11031
11032#define CSI_SR_F1_INT_MASK (0x4000U)
11033#define CSI_SR_F1_INT_SHIFT (14U)
11038#define CSI_SR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_F1_INT_SHIFT)) & CSI_SR_F1_INT_MASK)
11039
11040#define CSI_SR_F2_INT_MASK (0x8000U)
11041#define CSI_SR_F2_INT_SHIFT (15U)
11046#define CSI_SR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_F2_INT_SHIFT)) & CSI_SR_F2_INT_MASK)
11047
11048#define CSI_SR_SOF_INT_MASK (0x10000U)
11049#define CSI_SR_SOF_INT_SHIFT (16U)
11054#define CSI_SR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_SOF_INT_SHIFT)) & CSI_SR_SOF_INT_MASK)
11055
11056#define CSI_SR_EOF_INT_MASK (0x20000U)
11057#define CSI_SR_EOF_INT_SHIFT (17U)
11062#define CSI_SR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_EOF_INT_SHIFT)) & CSI_SR_EOF_INT_MASK)
11063
11064#define CSI_SR_RxFF_INT_MASK (0x40000U)
11065#define CSI_SR_RxFF_INT_SHIFT (18U)
11070#define CSI_SR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_RxFF_INT_SHIFT)) & CSI_SR_RxFF_INT_MASK)
11071
11072#define CSI_SR_DMA_TSF_DONE_FB1_MASK (0x80000U)
11073#define CSI_SR_DMA_TSF_DONE_FB1_SHIFT (19U)
11078#define CSI_SR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB1_MASK)
11079
11080#define CSI_SR_DMA_TSF_DONE_FB2_MASK (0x100000U)
11081#define CSI_SR_DMA_TSF_DONE_FB2_SHIFT (20U)
11086#define CSI_SR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB2_MASK)
11087
11088#define CSI_SR_STATFF_INT_MASK (0x200000U)
11089#define CSI_SR_STATFF_INT_SHIFT (21U)
11094#define CSI_SR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_STATFF_INT_SHIFT)) & CSI_SR_STATFF_INT_MASK)
11095
11096#define CSI_SR_DMA_TSF_DONE_SFF_MASK (0x400000U)
11097#define CSI_SR_DMA_TSF_DONE_SFF_SHIFT (22U)
11102#define CSI_SR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_SR_DMA_TSF_DONE_SFF_MASK)
11103
11104#define CSI_SR_RF_OR_INT_MASK (0x1000000U)
11105#define CSI_SR_RF_OR_INT_SHIFT (24U)
11110#define CSI_SR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_RF_OR_INT_SHIFT)) & CSI_SR_RF_OR_INT_MASK)
11111
11112#define CSI_SR_SF_OR_INT_MASK (0x2000000U)
11113#define CSI_SR_SF_OR_INT_SHIFT (25U)
11118#define CSI_SR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_SF_OR_INT_SHIFT)) & CSI_SR_SF_OR_INT_MASK)
11119
11120#define CSI_SR_DMA_FIELD1_DONE_MASK (0x4000000U)
11121#define CSI_SR_DMA_FIELD1_DONE_SHIFT (26U)
11122#define CSI_SR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD1_DONE_SHIFT)) & CSI_SR_DMA_FIELD1_DONE_MASK)
11123
11124#define CSI_SR_DMA_FIELD0_DONE_MASK (0x8000000U)
11125#define CSI_SR_DMA_FIELD0_DONE_SHIFT (27U)
11126#define CSI_SR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD0_DONE_SHIFT)) & CSI_SR_DMA_FIELD0_DONE_MASK)
11127
11128#define CSI_SR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
11129#define CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
11130#define CSI_SR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_SR_BASEADDR_CHHANGE_ERROR_MASK)
11136#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
11137#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
11138#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
11144#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
11145#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
11146#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
11152#define CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
11153#define CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
11154#define CSI_DMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK)
11160#define CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
11161#define CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
11162#define CSI_DMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK)
11168#define CSI_FBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
11169#define CSI_FBUF_PARA_FBUF_STRIDE_SHIFT (0U)
11170#define CSI_FBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_FBUF_PARA_FBUF_STRIDE_MASK)
11171
11172#define CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
11173#define CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
11174#define CSI_FBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK)
11180#define CSI_IMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
11181#define CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
11182#define CSI_IMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_IMAG_PARA_IMAGE_HEIGHT_MASK)
11183
11184#define CSI_IMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
11185#define CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
11186#define CSI_IMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_IMAG_PARA_IMAGE_WIDTH_MASK)
11192#define CSI_CR18_DEINTERLACE_EN_MASK (0x4U)
11193#define CSI_CR18_DEINTERLACE_EN_SHIFT (2U)
11198#define CSI_CR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DEINTERLACE_EN_SHIFT)) & CSI_CR18_DEINTERLACE_EN_MASK)
11199
11200#define CSI_CR18_PARALLEL24_EN_MASK (0x8U)
11201#define CSI_CR18_PARALLEL24_EN_SHIFT (3U)
11206#define CSI_CR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_PARALLEL24_EN_SHIFT)) & CSI_CR18_PARALLEL24_EN_MASK)
11207
11208#define CSI_CR18_BASEADDR_SWITCH_EN_MASK (0x10U)
11209#define CSI_CR18_BASEADDR_SWITCH_EN_SHIFT (4U)
11210#define CSI_CR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_EN_MASK)
11211
11212#define CSI_CR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
11213#define CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
11218#define CSI_CR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_SEL_MASK)
11219
11220#define CSI_CR18_FIELD0_DONE_IE_MASK (0x40U)
11221#define CSI_CR18_FIELD0_DONE_IE_SHIFT (6U)
11226#define CSI_CR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_FIELD0_DONE_IE_SHIFT)) & CSI_CR18_FIELD0_DONE_IE_MASK)
11227
11228#define CSI_CR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
11229#define CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
11234#define CSI_CR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CR18_DMA_FIELD1_DONE_IE_MASK)
11235
11236#define CSI_CR18_LAST_DMA_REQ_SEL_MASK (0x100U)
11237#define CSI_CR18_LAST_DMA_REQ_SEL_SHIFT (8U)
11242#define CSI_CR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CR18_LAST_DMA_REQ_SEL_MASK)
11243
11244#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
11245#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
11250#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK)
11251
11252#define CSI_CR18_RGB888A_FORMAT_SEL_MASK (0x400U)
11253#define CSI_CR18_RGB888A_FORMAT_SEL_SHIFT (10U)
11258#define CSI_CR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CR18_RGB888A_FORMAT_SEL_MASK)
11259
11260#define CSI_CR18_AHB_HPROT_MASK (0xF000U)
11261#define CSI_CR18_AHB_HPROT_SHIFT (12U)
11262#define CSI_CR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_AHB_HPROT_SHIFT)) & CSI_CR18_AHB_HPROT_MASK)
11263
11264#define CSI_CR18_MASK_OPTION_MASK (0xC0000U)
11265#define CSI_CR18_MASK_OPTION_SHIFT (18U)
11272#define CSI_CR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MASK_OPTION_SHIFT)) & CSI_CR18_MASK_OPTION_MASK)
11273
11274#define CSI_CR18_CSI_ENABLE_MASK (0x80000000U)
11275#define CSI_CR18_CSI_ENABLE_SHIFT (31U)
11276#define CSI_CR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_CSI_ENABLE_SHIFT)) & CSI_CR18_CSI_ENABLE_MASK)
11282#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
11283#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
11284#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) /* end of group CSI_Register_Masks */
11291
11292
11293/* CSI - Peripheral instance base addresses */
11295#define CSI_BASE (0x402BC000u)
11297#define CSI ((CSI_Type *)CSI_BASE)
11299#define CSI_BASE_ADDRS { CSI_BASE }
11301#define CSI_BASE_PTRS { CSI }
11303#define CSI_IRQS { CSI_IRQn }
11304 /* end of group CSI_Peripheral_Access_Layer */
11308
11309
11310/* ----------------------------------------------------------------------------
11311 -- CSU Peripheral Access Layer
11312 ---------------------------------------------------------------------------- */
11313
11320typedef struct {
11321 __IO uint32_t CSL[32];
11322 uint8_t RESERVED_0[384];
11323 __IO uint32_t HP0;
11324 uint8_t RESERVED_1[20];
11325 __IO uint32_t SA;
11326 uint8_t RESERVED_2[316];
11327 __IO uint32_t HPCONTROL0;
11328} CSU_Type;
11329
11330/* ----------------------------------------------------------------------------
11331 -- CSU Register Masks
11332 ---------------------------------------------------------------------------- */
11333
11342#define CSU_CSL_SUR_S2_MASK (0x1U)
11343#define CSU_CSL_SUR_S2_SHIFT (0U)
11348#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
11349
11350#define CSU_CSL_SSR_S2_MASK (0x2U)
11351#define CSU_CSL_SSR_S2_SHIFT (1U)
11356#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
11357
11358#define CSU_CSL_NUR_S2_MASK (0x4U)
11359#define CSU_CSL_NUR_S2_SHIFT (2U)
11364#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
11365
11366#define CSU_CSL_NSR_S2_MASK (0x8U)
11367#define CSU_CSL_NSR_S2_SHIFT (3U)
11372#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
11373
11374#define CSU_CSL_SUW_S2_MASK (0x10U)
11375#define CSU_CSL_SUW_S2_SHIFT (4U)
11380#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
11381
11382#define CSU_CSL_SSW_S2_MASK (0x20U)
11383#define CSU_CSL_SSW_S2_SHIFT (5U)
11388#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
11389
11390#define CSU_CSL_NUW_S2_MASK (0x40U)
11391#define CSU_CSL_NUW_S2_SHIFT (6U)
11396#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
11397
11398#define CSU_CSL_NSW_S2_MASK (0x80U)
11399#define CSU_CSL_NSW_S2_SHIFT (7U)
11404#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
11405
11406#define CSU_CSL_LOCK_S2_MASK (0x100U)
11407#define CSU_CSL_LOCK_S2_SHIFT (8U)
11412#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
11413
11414#define CSU_CSL_SUR_S1_MASK (0x10000U)
11415#define CSU_CSL_SUR_S1_SHIFT (16U)
11420#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
11421
11422#define CSU_CSL_SSR_S1_MASK (0x20000U)
11423#define CSU_CSL_SSR_S1_SHIFT (17U)
11428#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
11429
11430#define CSU_CSL_NUR_S1_MASK (0x40000U)
11431#define CSU_CSL_NUR_S1_SHIFT (18U)
11436#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
11437
11438#define CSU_CSL_NSR_S1_MASK (0x80000U)
11439#define CSU_CSL_NSR_S1_SHIFT (19U)
11444#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
11445
11446#define CSU_CSL_SUW_S1_MASK (0x100000U)
11447#define CSU_CSL_SUW_S1_SHIFT (20U)
11452#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
11453
11454#define CSU_CSL_SSW_S1_MASK (0x200000U)
11455#define CSU_CSL_SSW_S1_SHIFT (21U)
11460#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
11461
11462#define CSU_CSL_NUW_S1_MASK (0x400000U)
11463#define CSU_CSL_NUW_S1_SHIFT (22U)
11468#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
11469
11470#define CSU_CSL_NSW_S1_MASK (0x800000U)
11471#define CSU_CSL_NSW_S1_SHIFT (23U)
11476#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
11477
11478#define CSU_CSL_LOCK_S1_MASK (0x1000000U)
11479#define CSU_CSL_LOCK_S1_SHIFT (24U)
11484#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
11487/* The count of CSU_CSL */
11488#define CSU_CSL_COUNT (32U)
11489
11493#define CSU_HP0_HP_DMA_MASK (0x4U)
11494#define CSU_HP0_HP_DMA_SHIFT (2U)
11499#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
11500
11501#define CSU_HP0_L_DMA_MASK (0x8U)
11502#define CSU_HP0_L_DMA_SHIFT (3U)
11507#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
11508
11509#define CSU_HP0_HP_LCDIF_MASK (0x10U)
11510#define CSU_HP0_HP_LCDIF_SHIFT (4U)
11515#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
11516
11517#define CSU_HP0_L_LCDIF_MASK (0x20U)
11518#define CSU_HP0_L_LCDIF_SHIFT (5U)
11523#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
11524
11525#define CSU_HP0_HP_CSI_MASK (0x40U)
11526#define CSU_HP0_HP_CSI_SHIFT (6U)
11531#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
11532
11533#define CSU_HP0_L_CSI_MASK (0x80U)
11534#define CSU_HP0_L_CSI_SHIFT (7U)
11539#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
11540
11541#define CSU_HP0_HP_PXP_MASK (0x100U)
11542#define CSU_HP0_HP_PXP_SHIFT (8U)
11547#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
11548
11549#define CSU_HP0_L_PXP_MASK (0x200U)
11550#define CSU_HP0_L_PXP_SHIFT (9U)
11555#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
11556
11557#define CSU_HP0_HP_DCP_MASK (0x400U)
11558#define CSU_HP0_HP_DCP_SHIFT (10U)
11563#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
11564
11565#define CSU_HP0_L_DCP_MASK (0x800U)
11566#define CSU_HP0_L_DCP_SHIFT (11U)
11571#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
11572
11573#define CSU_HP0_HP_ENET_MASK (0x4000U)
11574#define CSU_HP0_HP_ENET_SHIFT (14U)
11579#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
11580
11581#define CSU_HP0_L_ENET_MASK (0x8000U)
11582#define CSU_HP0_L_ENET_SHIFT (15U)
11587#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
11588
11589#define CSU_HP0_HP_USDHC1_MASK (0x10000U)
11590#define CSU_HP0_HP_USDHC1_SHIFT (16U)
11595#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
11596
11597#define CSU_HP0_L_USDHC1_MASK (0x20000U)
11598#define CSU_HP0_L_USDHC1_SHIFT (17U)
11603#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
11604
11605#define CSU_HP0_HP_USDHC2_MASK (0x40000U)
11606#define CSU_HP0_HP_USDHC2_SHIFT (18U)
11611#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
11612
11613#define CSU_HP0_L_USDHC2_MASK (0x80000U)
11614#define CSU_HP0_L_USDHC2_SHIFT (19U)
11619#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
11620
11621#define CSU_HP0_HP_TPSMP_MASK (0x100000U)
11622#define CSU_HP0_HP_TPSMP_SHIFT (20U)
11627#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
11628
11629#define CSU_HP0_L_TPSMP_MASK (0x200000U)
11630#define CSU_HP0_L_TPSMP_SHIFT (21U)
11635#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
11636
11637#define CSU_HP0_HP_USB_MASK (0x400000U)
11638#define CSU_HP0_HP_USB_SHIFT (22U)
11643#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
11644
11645#define CSU_HP0_L_USB_MASK (0x800000U)
11646#define CSU_HP0_L_USB_SHIFT (23U)
11651#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
11657#define CSU_SA_NSA_DMA_MASK (0x4U)
11658#define CSU_SA_NSA_DMA_SHIFT (2U)
11663#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
11664
11665#define CSU_SA_L_DMA_MASK (0x8U)
11666#define CSU_SA_L_DMA_SHIFT (3U)
11671#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
11672
11673#define CSU_SA_NSA_LCDIF_MASK (0x10U)
11674#define CSU_SA_NSA_LCDIF_SHIFT (4U)
11679#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
11680
11681#define CSU_SA_L_LCDIF_MASK (0x20U)
11682#define CSU_SA_L_LCDIF_SHIFT (5U)
11687#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
11688
11689#define CSU_SA_NSA_CSI_MASK (0x40U)
11690#define CSU_SA_NSA_CSI_SHIFT (6U)
11695#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
11696
11697#define CSU_SA_L_CSI_MASK (0x80U)
11698#define CSU_SA_L_CSI_SHIFT (7U)
11703#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
11704
11705#define CSU_SA_NSA_PXP_MASK (0x100U)
11706#define CSU_SA_NSA_PXP_SHIFT (8U)
11711#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
11712
11713#define CSU_SA_L_PXP_MASK (0x200U)
11714#define CSU_SA_L_PXP_SHIFT (9U)
11719#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
11720
11721#define CSU_SA_NSA_DCP_MASK (0x400U)
11722#define CSU_SA_NSA_DCP_SHIFT (10U)
11727#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
11728
11729#define CSU_SA_L_DCP_MASK (0x800U)
11730#define CSU_SA_L_DCP_SHIFT (11U)
11735#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
11736
11737#define CSU_SA_NSA_ENET_MASK (0x4000U)
11738#define CSU_SA_NSA_ENET_SHIFT (14U)
11743#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
11744
11745#define CSU_SA_L_ENET_MASK (0x8000U)
11746#define CSU_SA_L_ENET_SHIFT (15U)
11751#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
11752
11753#define CSU_SA_NSA_USDHC1_MASK (0x10000U)
11754#define CSU_SA_NSA_USDHC1_SHIFT (16U)
11759#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
11760
11761#define CSU_SA_L_USDHC1_MASK (0x20000U)
11762#define CSU_SA_L_USDHC1_SHIFT (17U)
11767#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
11768
11769#define CSU_SA_NSA_USDHC2_MASK (0x40000U)
11770#define CSU_SA_NSA_USDHC2_SHIFT (18U)
11775#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
11776
11777#define CSU_SA_L_USDHC2_MASK (0x80000U)
11778#define CSU_SA_L_USDHC2_SHIFT (19U)
11783#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
11784
11785#define CSU_SA_NSA_TPSMP_MASK (0x100000U)
11786#define CSU_SA_NSA_TPSMP_SHIFT (20U)
11791#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
11792
11793#define CSU_SA_L_TPSMP_MASK (0x200000U)
11794#define CSU_SA_L_TPSMP_SHIFT (21U)
11799#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
11800
11801#define CSU_SA_NSA_USB_MASK (0x400000U)
11802#define CSU_SA_NSA_USB_SHIFT (22U)
11807#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
11808
11809#define CSU_SA_L_USB_MASK (0x800000U)
11810#define CSU_SA_L_USB_SHIFT (23U)
11815#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
11821#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)
11822#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)
11827#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
11828
11829#define CSU_HPCONTROL0_L_DMA_MASK (0x8U)
11830#define CSU_HPCONTROL0_L_DMA_SHIFT (3U)
11835#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
11836
11837#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)
11838#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)
11843#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
11844
11845#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)
11846#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)
11851#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
11852
11853#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)
11854#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)
11859#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
11860
11861#define CSU_HPCONTROL0_L_CSI_MASK (0x80U)
11862#define CSU_HPCONTROL0_L_CSI_SHIFT (7U)
11867#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
11868
11869#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)
11870#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)
11875#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
11876
11877#define CSU_HPCONTROL0_L_PXP_MASK (0x200U)
11878#define CSU_HPCONTROL0_L_PXP_SHIFT (9U)
11883#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
11884
11885#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)
11886#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)
11891#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
11892
11893#define CSU_HPCONTROL0_L_DCP_MASK (0x800U)
11894#define CSU_HPCONTROL0_L_DCP_SHIFT (11U)
11899#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
11900
11901#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)
11902#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)
11907#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
11908
11909#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U)
11910#define CSU_HPCONTROL0_L_ENET_SHIFT (15U)
11915#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
11916
11917#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)
11918#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)
11923#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
11924
11925#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)
11926#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)
11931#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
11932
11933#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)
11934#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)
11939#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
11940
11941#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)
11942#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)
11947#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
11948
11949#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)
11950#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)
11955#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
11956
11957#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)
11958#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)
11963#define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
11964
11965#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)
11966#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U)
11971#define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
11972
11973#define CSU_HPCONTROL0_L_USB_MASK (0x800000U)
11974#define CSU_HPCONTROL0_L_USB_SHIFT (23U)
11979#define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) /* end of group CSU_Register_Masks */
11986
11987
11988/* CSU - Peripheral instance base addresses */
11990#define CSU_BASE (0x400DC000u)
11992#define CSU ((CSU_Type *)CSU_BASE)
11994#define CSU_BASE_ADDRS { CSU_BASE }
11996#define CSU_BASE_PTRS { CSU }
11997 /* end of group CSU_Peripheral_Access_Layer */
12001
12002
12003/* ----------------------------------------------------------------------------
12004 -- DCDC Peripheral Access Layer
12005 ---------------------------------------------------------------------------- */
12006
12013typedef struct {
12014 __IO uint32_t REG0;
12015 __IO uint32_t REG1;
12016 __IO uint32_t REG2;
12017 __IO uint32_t REG3;
12018} DCDC_Type;
12019
12020/* ----------------------------------------------------------------------------
12021 -- DCDC Register Masks
12022 ---------------------------------------------------------------------------- */
12023
12032#define DCDC_REG0_PWD_ZCD_MASK (0x1U)
12033#define DCDC_REG0_PWD_ZCD_SHIFT (0U)
12038#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
12039
12040#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
12041#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
12046#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
12047
12048#define DCDC_REG0_SEL_CLK_MASK (0x4U)
12049#define DCDC_REG0_SEL_CLK_SHIFT (2U)
12054#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
12055
12056#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
12057#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
12062#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
12063
12064#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
12065#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
12070#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
12071
12072#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
12073#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
12082#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
12083
12084#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
12085#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
12090#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
12091
12092#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)
12093#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)
12100#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
12101
12102#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)
12103#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)
12108#define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
12109
12110#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)
12111#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)
12116#define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
12117
12118#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)
12119#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)
12124#define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
12125
12126#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)
12127#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)
12134#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
12135
12136#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)
12137#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)
12142#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
12143
12144#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
12145#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
12150#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
12151
12152#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
12153#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
12158#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
12159
12160#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
12161#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
12166#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
12167
12168#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)
12169#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)
12174#define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
12175
12176#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
12177#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
12182#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
12183
12184#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
12185#define DCDC_REG0_STS_DC_OK_SHIFT (31U)
12190#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
12196#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U)
12197#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U)
12204#define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
12205
12206#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)
12207#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)
12212#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
12213
12214#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)
12215#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)
12222#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
12223
12224#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)
12225#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)
12230#define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
12231
12232#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)
12233#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)
12238#define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
12239
12240#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)
12241#define DCDC_REG1_VBG_TRIM_SHIFT (24U)
12244#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
12250#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
12251#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
12252#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
12253
12254#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
12255#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
12258#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
12259
12260#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
12261#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
12266#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
12267
12268#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
12269#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
12274#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
12275
12276#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)
12277#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)
12282#define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
12283
12284#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
12285#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
12288#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
12294#define DCDC_REG3_TRG_MASK (0x1FU)
12295#define DCDC_REG3_TRG_SHIFT (0U)
12298#define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
12299
12300#define DCDC_REG3_TARGET_LP_MASK (0x700U)
12301#define DCDC_REG3_TARGET_LP_SHIFT (8U)
12309#define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
12310
12311#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
12312#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
12317#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
12318
12319#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)
12320#define DCDC_REG3_DISABLE_STEP_SHIFT (30U)
12325#define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) /* end of group DCDC_Register_Masks */
12332
12333
12334/* DCDC - Peripheral instance base addresses */
12336#define DCDC_BASE (0x40080000u)
12338#define DCDC ((DCDC_Type *)DCDC_BASE)
12340#define DCDC_BASE_ADDRS { DCDC_BASE }
12342#define DCDC_BASE_PTRS { DCDC }
12344#define DCDC_IRQS { DCDC_IRQn }
12345 /* end of group DCDC_Peripheral_Access_Layer */
12349
12350
12351/* ----------------------------------------------------------------------------
12352 -- DCP Peripheral Access Layer
12353 ---------------------------------------------------------------------------- */
12354
12361typedef struct {
12362 __IO uint32_t CTRL;
12363 __IO uint32_t CTRL_SET;
12364 __IO uint32_t CTRL_CLR;
12365 __IO uint32_t CTRL_TOG;
12366 __IO uint32_t STAT;
12367 __IO uint32_t STAT_SET;
12368 __IO uint32_t STAT_CLR;
12369 __IO uint32_t STAT_TOG;
12370 __IO uint32_t CHANNELCTRL;
12371 __IO uint32_t CHANNELCTRL_SET;
12372 __IO uint32_t CHANNELCTRL_CLR;
12373 __IO uint32_t CHANNELCTRL_TOG;
12374 __IO uint32_t CAPABILITY0;
12375 uint8_t RESERVED_0[12];
12376 __I uint32_t CAPABILITY1;
12377 uint8_t RESERVED_1[12];
12378 __IO uint32_t CONTEXT;
12379 uint8_t RESERVED_2[12];
12380 __IO uint32_t KEY;
12381 uint8_t RESERVED_3[12];
12382 __IO uint32_t KEYDATA;
12383 uint8_t RESERVED_4[12];
12384 __I uint32_t PACKET0;
12385 uint8_t RESERVED_5[12];
12386 __I uint32_t PACKET1;
12387 uint8_t RESERVED_6[12];
12388 __I uint32_t PACKET2;
12389 uint8_t RESERVED_7[12];
12390 __I uint32_t PACKET3;
12391 uint8_t RESERVED_8[12];
12392 __I uint32_t PACKET4;
12393 uint8_t RESERVED_9[12];
12394 __I uint32_t PACKET5;
12395 uint8_t RESERVED_10[12];
12396 __I uint32_t PACKET6;
12397 uint8_t RESERVED_11[28];
12398 __IO uint32_t CH0CMDPTR;
12399 uint8_t RESERVED_12[12];
12400 __IO uint32_t CH0SEMA;
12401 uint8_t RESERVED_13[12];
12402 __IO uint32_t CH0STAT;
12403 __IO uint32_t CH0STAT_SET;
12404 __IO uint32_t CH0STAT_CLR;
12405 __IO uint32_t CH0STAT_TOG;
12406 __IO uint32_t CH0OPTS;
12407 __IO uint32_t CH0OPTS_SET;
12408 __IO uint32_t CH0OPTS_CLR;
12409 __IO uint32_t CH0OPTS_TOG;
12410 __IO uint32_t CH1CMDPTR;
12411 uint8_t RESERVED_14[12];
12412 __IO uint32_t CH1SEMA;
12413 uint8_t RESERVED_15[12];
12414 __IO uint32_t CH1STAT;
12415 __IO uint32_t CH1STAT_SET;
12416 __IO uint32_t CH1STAT_CLR;
12417 __IO uint32_t CH1STAT_TOG;
12418 __IO uint32_t CH1OPTS;
12419 __IO uint32_t CH1OPTS_SET;
12420 __IO uint32_t CH1OPTS_CLR;
12421 __IO uint32_t CH1OPTS_TOG;
12422 __IO uint32_t CH2CMDPTR;
12423 uint8_t RESERVED_16[12];
12424 __IO uint32_t CH2SEMA;
12425 uint8_t RESERVED_17[12];
12426 __IO uint32_t CH2STAT;
12427 __IO uint32_t CH2STAT_SET;
12428 __IO uint32_t CH2STAT_CLR;
12429 __IO uint32_t CH2STAT_TOG;
12430 __IO uint32_t CH2OPTS;
12431 __IO uint32_t CH2OPTS_SET;
12432 __IO uint32_t CH2OPTS_CLR;
12433 __IO uint32_t CH2OPTS_TOG;
12434 __IO uint32_t CH3CMDPTR;
12435 uint8_t RESERVED_18[12];
12436 __IO uint32_t CH3SEMA;
12437 uint8_t RESERVED_19[12];
12438 __IO uint32_t CH3STAT;
12439 __IO uint32_t CH3STAT_SET;
12440 __IO uint32_t CH3STAT_CLR;
12441 __IO uint32_t CH3STAT_TOG;
12442 __IO uint32_t CH3OPTS;
12443 __IO uint32_t CH3OPTS_SET;
12444 __IO uint32_t CH3OPTS_CLR;
12445 __IO uint32_t CH3OPTS_TOG;
12446 uint8_t RESERVED_20[512];
12447 __IO uint32_t DBGSELECT;
12448 uint8_t RESERVED_21[12];
12449 __I uint32_t DBGDATA;
12450 uint8_t RESERVED_22[12];
12451 __IO uint32_t PAGETABLE;
12452 uint8_t RESERVED_23[12];
12453 __I uint32_t VERSION;
12454} DCP_Type;
12455
12456/* ----------------------------------------------------------------------------
12457 -- DCP Register Masks
12458 ---------------------------------------------------------------------------- */
12459
12468#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
12469#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
12476#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)
12477
12478#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
12479#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
12480#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)
12481
12482#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
12483#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
12484#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)
12485
12486#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
12487#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)
12488#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)
12489
12490#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
12491#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)
12492#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)
12493
12494#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)
12495#define DCP_CTRL_PRESENT_SHA_SHIFT (28U)
12500#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)
12501
12502#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)
12503#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)
12508#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)
12509
12510#define DCP_CTRL_CLKGATE_MASK (0x40000000U)
12511#define DCP_CTRL_CLKGATE_SHIFT (30U)
12512#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)
12513
12514#define DCP_CTRL_SFTRST_MASK (0x80000000U)
12515#define DCP_CTRL_SFTRST_SHIFT (31U)
12516#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)
12522#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
12523#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
12530#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK)
12531
12532#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
12533#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
12534#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK)
12535
12536#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
12537#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
12538#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK)
12539
12540#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
12541#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U)
12542#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK)
12543
12544#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
12545#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U)
12546#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK)
12547
12548#define DCP_CTRL_SET_PRESENT_SHA_MASK (0x10000000U)
12549#define DCP_CTRL_SET_PRESENT_SHA_SHIFT (28U)
12554#define DCP_CTRL_SET_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK)
12555
12556#define DCP_CTRL_SET_PRESENT_CRYPTO_MASK (0x20000000U)
12557#define DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT (29U)
12562#define DCP_CTRL_SET_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK)
12563
12564#define DCP_CTRL_SET_CLKGATE_MASK (0x40000000U)
12565#define DCP_CTRL_SET_CLKGATE_SHIFT (30U)
12566#define DCP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK)
12567
12568#define DCP_CTRL_SET_SFTRST_MASK (0x80000000U)
12569#define DCP_CTRL_SET_SFTRST_SHIFT (31U)
12570#define DCP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK)
12576#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
12577#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
12584#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK)
12585
12586#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
12587#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
12588#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK)
12589
12590#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
12591#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
12592#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK)
12593
12594#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
12595#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U)
12596#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK)
12597
12598#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
12599#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U)
12600#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK)
12601
12602#define DCP_CTRL_CLR_PRESENT_SHA_MASK (0x10000000U)
12603#define DCP_CTRL_CLR_PRESENT_SHA_SHIFT (28U)
12608#define DCP_CTRL_CLR_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK)
12609
12610#define DCP_CTRL_CLR_PRESENT_CRYPTO_MASK (0x20000000U)
12611#define DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT (29U)
12616#define DCP_CTRL_CLR_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK)
12617
12618#define DCP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
12619#define DCP_CTRL_CLR_CLKGATE_SHIFT (30U)
12620#define DCP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK)
12621
12622#define DCP_CTRL_CLR_SFTRST_MASK (0x80000000U)
12623#define DCP_CTRL_CLR_SFTRST_SHIFT (31U)
12624#define DCP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK)
12630#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
12631#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
12638#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK)
12639
12640#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
12641#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
12642#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK)
12643
12644#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
12645#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
12646#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK)
12647
12648#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
12649#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U)
12650#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK)
12651
12652#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
12653#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U)
12654#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK)
12655
12656#define DCP_CTRL_TOG_PRESENT_SHA_MASK (0x10000000U)
12657#define DCP_CTRL_TOG_PRESENT_SHA_SHIFT (28U)
12662#define DCP_CTRL_TOG_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK)
12663
12664#define DCP_CTRL_TOG_PRESENT_CRYPTO_MASK (0x20000000U)
12665#define DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT (29U)
12670#define DCP_CTRL_TOG_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK)
12671
12672#define DCP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
12673#define DCP_CTRL_TOG_CLKGATE_SHIFT (30U)
12674#define DCP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK)
12675
12676#define DCP_CTRL_TOG_SFTRST_MASK (0x80000000U)
12677#define DCP_CTRL_TOG_SFTRST_SHIFT (31U)
12678#define DCP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK)
12684#define DCP_STAT_IRQ_MASK (0xFU)
12685#define DCP_STAT_IRQ_SHIFT (0U)
12686#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)
12687
12688#define DCP_STAT_RSVD_IRQ_MASK (0x100U)
12689#define DCP_STAT_RSVD_IRQ_SHIFT (8U)
12690#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)
12691
12692#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U)
12693#define DCP_STAT_READY_CHANNELS_SHIFT (16U)
12700#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)
12701
12702#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U)
12703#define DCP_STAT_CUR_CHANNEL_SHIFT (24U)
12711#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)
12712
12713#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
12714#define DCP_STAT_OTP_KEY_READY_SHIFT (28U)
12715#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)
12721#define DCP_STAT_SET_IRQ_MASK (0xFU)
12722#define DCP_STAT_SET_IRQ_SHIFT (0U)
12723#define DCP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK)
12724
12725#define DCP_STAT_SET_RSVD_IRQ_MASK (0x100U)
12726#define DCP_STAT_SET_RSVD_IRQ_SHIFT (8U)
12727#define DCP_STAT_SET_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK)
12728
12729#define DCP_STAT_SET_READY_CHANNELS_MASK (0xFF0000U)
12730#define DCP_STAT_SET_READY_CHANNELS_SHIFT (16U)
12737#define DCP_STAT_SET_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK)
12738
12739#define DCP_STAT_SET_CUR_CHANNEL_MASK (0xF000000U)
12740#define DCP_STAT_SET_CUR_CHANNEL_SHIFT (24U)
12748#define DCP_STAT_SET_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK)
12749
12750#define DCP_STAT_SET_OTP_KEY_READY_MASK (0x10000000U)
12751#define DCP_STAT_SET_OTP_KEY_READY_SHIFT (28U)
12752#define DCP_STAT_SET_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK)
12758#define DCP_STAT_CLR_IRQ_MASK (0xFU)
12759#define DCP_STAT_CLR_IRQ_SHIFT (0U)
12760#define DCP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK)
12761
12762#define DCP_STAT_CLR_RSVD_IRQ_MASK (0x100U)
12763#define DCP_STAT_CLR_RSVD_IRQ_SHIFT (8U)
12764#define DCP_STAT_CLR_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK)
12765
12766#define DCP_STAT_CLR_READY_CHANNELS_MASK (0xFF0000U)
12767#define DCP_STAT_CLR_READY_CHANNELS_SHIFT (16U)
12774#define DCP_STAT_CLR_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK)
12775
12776#define DCP_STAT_CLR_CUR_CHANNEL_MASK (0xF000000U)
12777#define DCP_STAT_CLR_CUR_CHANNEL_SHIFT (24U)
12785#define DCP_STAT_CLR_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK)
12786
12787#define DCP_STAT_CLR_OTP_KEY_READY_MASK (0x10000000U)
12788#define DCP_STAT_CLR_OTP_KEY_READY_SHIFT (28U)
12789#define DCP_STAT_CLR_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK)
12795#define DCP_STAT_TOG_IRQ_MASK (0xFU)
12796#define DCP_STAT_TOG_IRQ_SHIFT (0U)
12797#define DCP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK)
12798
12799#define DCP_STAT_TOG_RSVD_IRQ_MASK (0x100U)
12800#define DCP_STAT_TOG_RSVD_IRQ_SHIFT (8U)
12801#define DCP_STAT_TOG_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK)
12802
12803#define DCP_STAT_TOG_READY_CHANNELS_MASK (0xFF0000U)
12804#define DCP_STAT_TOG_READY_CHANNELS_SHIFT (16U)
12811#define DCP_STAT_TOG_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK)
12812
12813#define DCP_STAT_TOG_CUR_CHANNEL_MASK (0xF000000U)
12814#define DCP_STAT_TOG_CUR_CHANNEL_SHIFT (24U)
12822#define DCP_STAT_TOG_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK)
12823
12824#define DCP_STAT_TOG_OTP_KEY_READY_MASK (0x10000000U)
12825#define DCP_STAT_TOG_OTP_KEY_READY_SHIFT (28U)
12826#define DCP_STAT_TOG_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK)
12832#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU)
12833#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U)
12840#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)
12841
12842#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
12843#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
12850#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)
12851
12852#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U)
12853#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U)
12854#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)
12855
12856#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U)
12857#define DCP_CHANNELCTRL_RSVD_SHIFT (17U)
12858#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)
12864#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK (0xFFU)
12865#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U)
12872#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK)
12873
12874#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
12875#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
12882#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK)
12883
12884#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK (0x10000U)
12885#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U)
12886#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK)
12887
12888#define DCP_CHANNELCTRL_SET_RSVD_MASK (0xFFFE0000U)
12889#define DCP_CHANNELCTRL_SET_RSVD_SHIFT (17U)
12890#define DCP_CHANNELCTRL_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK)
12896#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK (0xFFU)
12897#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U)
12904#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK)
12905
12906#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
12907#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
12914#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK)
12915
12916#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK (0x10000U)
12917#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U)
12918#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK)
12919
12920#define DCP_CHANNELCTRL_CLR_RSVD_MASK (0xFFFE0000U)
12921#define DCP_CHANNELCTRL_CLR_RSVD_SHIFT (17U)
12922#define DCP_CHANNELCTRL_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK)
12928#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK (0xFFU)
12929#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U)
12936#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK)
12937
12938#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
12939#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
12946#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK)
12947
12948#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK (0x10000U)
12949#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U)
12950#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK)
12951
12952#define DCP_CHANNELCTRL_TOG_RSVD_MASK (0xFFFE0000U)
12953#define DCP_CHANNELCTRL_TOG_RSVD_SHIFT (17U)
12954#define DCP_CHANNELCTRL_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK)
12960#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU)
12961#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U)
12962#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)
12963
12964#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U)
12965#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U)
12966#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)
12967
12968#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U)
12969#define DCP_CAPABILITY0_RSVD_SHIFT (12U)
12970#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)
12971
12972#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U)
12973#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)
12974#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)
12975
12976#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U)
12977#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U)
12978#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)
12984#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU)
12985#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U)
12989#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)
12990
12991#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U)
12992#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U)
12998#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)
13004#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU)
13005#define DCP_CONTEXT_ADDR_SHIFT (0U)
13006#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)
13012#define DCP_KEY_SUBWORD_MASK (0x3U)
13013#define DCP_KEY_SUBWORD_SHIFT (0U)
13014#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)
13015
13016#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU)
13017#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U)
13018#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)
13019
13020#define DCP_KEY_INDEX_MASK (0x30U)
13021#define DCP_KEY_INDEX_SHIFT (4U)
13022#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
13023
13024#define DCP_KEY_RSVD_INDEX_MASK (0xC0U)
13025#define DCP_KEY_RSVD_INDEX_SHIFT (6U)
13026#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)
13027
13028#define DCP_KEY_RSVD_MASK (0xFFFFFF00U)
13029#define DCP_KEY_RSVD_SHIFT (8U)
13030#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)
13036#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)
13037#define DCP_KEYDATA_DATA_SHIFT (0U)
13038#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)
13044#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)
13045#define DCP_PACKET0_ADDR_SHIFT (0U)
13046#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)
13052#define DCP_PACKET1_INTERRUPT_MASK (0x1U)
13053#define DCP_PACKET1_INTERRUPT_SHIFT (0U)
13054#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)
13055
13056#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)
13057#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)
13058#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)
13059
13060#define DCP_PACKET1_CHAIN_MASK (0x4U)
13061#define DCP_PACKET1_CHAIN_SHIFT (2U)
13062#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)
13063
13064#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)
13065#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)
13066#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)
13067
13068#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)
13069#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)
13070#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)
13071
13072#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)
13073#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)
13074#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)
13075
13076#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U)
13077#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U)
13078#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)
13079
13080#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)
13081#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)
13082#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)
13083
13084#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)
13085#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)
13090#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)
13091
13092#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U)
13093#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U)
13094#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)
13095
13096#define DCP_PACKET1_OTP_KEY_MASK (0x400U)
13097#define DCP_PACKET1_OTP_KEY_SHIFT (10U)
13098#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)
13099
13100#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)
13101#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)
13102#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)
13103
13104#define DCP_PACKET1_HASH_INIT_MASK (0x1000U)
13105#define DCP_PACKET1_HASH_INIT_SHIFT (12U)
13106#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)
13107
13108#define DCP_PACKET1_HASH_TERM_MASK (0x2000U)
13109#define DCP_PACKET1_HASH_TERM_SHIFT (13U)
13110#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)
13111
13112#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U)
13113#define DCP_PACKET1_CHECK_HASH_SHIFT (14U)
13114#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)
13115
13116#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)
13117#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)
13122#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)
13123
13124#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)
13125#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)
13126#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)
13127
13128#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)
13129#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)
13130#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)
13131
13132#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)
13133#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)
13134#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)
13135
13136#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)
13137#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)
13138#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)
13139
13140#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)
13141#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)
13142#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)
13143
13144#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)
13145#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)
13146#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)
13147
13148#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)
13149#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)
13150#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)
13151
13152#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)
13153#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)
13154#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)
13155
13156#define DCP_PACKET1_TAG_MASK (0xFF000000U)
13157#define DCP_PACKET1_TAG_SHIFT (24U)
13158#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)
13164#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)
13165#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)
13169#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)
13170
13171#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)
13172#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U)
13177#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)
13178
13179#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)
13180#define DCP_PACKET2_KEY_SELECT_SHIFT (8U)
13189#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)
13190
13191#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)
13192#define DCP_PACKET2_HASH_SELECT_SHIFT (16U)
13198#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)
13199
13200#define DCP_PACKET2_RSVD_MASK (0xF00000U)
13201#define DCP_PACKET2_RSVD_SHIFT (20U)
13202#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)
13203
13204#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)
13205#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U)
13206#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)
13212#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)
13213#define DCP_PACKET3_ADDR_SHIFT (0U)
13214#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)
13220#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)
13221#define DCP_PACKET4_ADDR_SHIFT (0U)
13222#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)
13228#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)
13229#define DCP_PACKET5_COUNT_SHIFT (0U)
13230#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)
13236#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)
13237#define DCP_PACKET6_ADDR_SHIFT (0U)
13238#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)
13244#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)
13245#define DCP_CH0CMDPTR_ADDR_SHIFT (0U)
13246#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)
13252#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU)
13253#define DCP_CH0SEMA_INCREMENT_SHIFT (0U)
13254#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)
13255
13256#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
13257#define DCP_CH0SEMA_VALUE_SHIFT (16U)
13258#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)
13264#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)
13265#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)
13266#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)
13267
13268#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)
13269#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)
13270#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)
13271
13272#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)
13273#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)
13274#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)
13275
13276#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)
13277#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)
13278#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)
13279
13280#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U)
13281#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U)
13282#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)
13283
13284#define DCP_CH0STAT_ERROR_DST_MASK (0x20U)
13285#define DCP_CH0STAT_ERROR_DST_SHIFT (5U)
13286#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)
13287
13288#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)
13289#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)
13290#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)
13291
13292#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
13293#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U)
13301#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)
13302
13303#define DCP_CH0STAT_TAG_MASK (0xFF000000U)
13304#define DCP_CH0STAT_TAG_SHIFT (24U)
13305#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)
13311#define DCP_CH0STAT_SET_RSVD_COMPLETE_MASK (0x1U)
13312#define DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT (0U)
13313#define DCP_CH0STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK)
13314
13315#define DCP_CH0STAT_SET_HASH_MISMATCH_MASK (0x2U)
13316#define DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT (1U)
13317#define DCP_CH0STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK)
13318
13319#define DCP_CH0STAT_SET_ERROR_SETUP_MASK (0x4U)
13320#define DCP_CH0STAT_SET_ERROR_SETUP_SHIFT (2U)
13321#define DCP_CH0STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK)
13322
13323#define DCP_CH0STAT_SET_ERROR_PACKET_MASK (0x8U)
13324#define DCP_CH0STAT_SET_ERROR_PACKET_SHIFT (3U)
13325#define DCP_CH0STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK)
13326
13327#define DCP_CH0STAT_SET_ERROR_SRC_MASK (0x10U)
13328#define DCP_CH0STAT_SET_ERROR_SRC_SHIFT (4U)
13329#define DCP_CH0STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK)
13330
13331#define DCP_CH0STAT_SET_ERROR_DST_MASK (0x20U)
13332#define DCP_CH0STAT_SET_ERROR_DST_SHIFT (5U)
13333#define DCP_CH0STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK)
13334
13335#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
13336#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
13337#define DCP_CH0STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK)
13338
13339#define DCP_CH0STAT_SET_ERROR_CODE_MASK (0xFF0000U)
13340#define DCP_CH0STAT_SET_ERROR_CODE_SHIFT (16U)
13348#define DCP_CH0STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK)
13349
13350#define DCP_CH0STAT_SET_TAG_MASK (0xFF000000U)
13351#define DCP_CH0STAT_SET_TAG_SHIFT (24U)
13352#define DCP_CH0STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK)
13358#define DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
13359#define DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
13360#define DCP_CH0STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK)
13361
13362#define DCP_CH0STAT_CLR_HASH_MISMATCH_MASK (0x2U)
13363#define DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT (1U)
13364#define DCP_CH0STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK)
13365
13366#define DCP_CH0STAT_CLR_ERROR_SETUP_MASK (0x4U)
13367#define DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT (2U)
13368#define DCP_CH0STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK)
13369
13370#define DCP_CH0STAT_CLR_ERROR_PACKET_MASK (0x8U)
13371#define DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT (3U)
13372#define DCP_CH0STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK)
13373
13374#define DCP_CH0STAT_CLR_ERROR_SRC_MASK (0x10U)
13375#define DCP_CH0STAT_CLR_ERROR_SRC_SHIFT (4U)
13376#define DCP_CH0STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK)
13377
13378#define DCP_CH0STAT_CLR_ERROR_DST_MASK (0x20U)
13379#define DCP_CH0STAT_CLR_ERROR_DST_SHIFT (5U)
13380#define DCP_CH0STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK)
13381
13382#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
13383#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
13384#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK)
13385
13386#define DCP_CH0STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
13387#define DCP_CH0STAT_CLR_ERROR_CODE_SHIFT (16U)
13395#define DCP_CH0STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK)
13396
13397#define DCP_CH0STAT_CLR_TAG_MASK (0xFF000000U)
13398#define DCP_CH0STAT_CLR_TAG_SHIFT (24U)
13399#define DCP_CH0STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK)
13405#define DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
13406#define DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
13407#define DCP_CH0STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK)
13408
13409#define DCP_CH0STAT_TOG_HASH_MISMATCH_MASK (0x2U)
13410#define DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT (1U)
13411#define DCP_CH0STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK)
13412
13413#define DCP_CH0STAT_TOG_ERROR_SETUP_MASK (0x4U)
13414#define DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT (2U)
13415#define DCP_CH0STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK)
13416
13417#define DCP_CH0STAT_TOG_ERROR_PACKET_MASK (0x8U)
13418#define DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT (3U)
13419#define DCP_CH0STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK)
13420
13421#define DCP_CH0STAT_TOG_ERROR_SRC_MASK (0x10U)
13422#define DCP_CH0STAT_TOG_ERROR_SRC_SHIFT (4U)
13423#define DCP_CH0STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK)
13424
13425#define DCP_CH0STAT_TOG_ERROR_DST_MASK (0x20U)
13426#define DCP_CH0STAT_TOG_ERROR_DST_SHIFT (5U)
13427#define DCP_CH0STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK)
13428
13429#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
13430#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
13431#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK)
13432
13433#define DCP_CH0STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
13434#define DCP_CH0STAT_TOG_ERROR_CODE_SHIFT (16U)
13442#define DCP_CH0STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK)
13443
13444#define DCP_CH0STAT_TOG_TAG_MASK (0xFF000000U)
13445#define DCP_CH0STAT_TOG_TAG_SHIFT (24U)
13446#define DCP_CH0STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK)
13452#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
13453#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)
13454#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)
13455
13456#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)
13457#define DCP_CH0OPTS_RSVD_SHIFT (16U)
13458#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)
13464#define DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
13465#define DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
13466#define DCP_CH0OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK)
13467
13468#define DCP_CH0OPTS_SET_RSVD_MASK (0xFFFF0000U)
13469#define DCP_CH0OPTS_SET_RSVD_SHIFT (16U)
13470#define DCP_CH0OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK)
13476#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
13477#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
13478#define DCP_CH0OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK)
13479
13480#define DCP_CH0OPTS_CLR_RSVD_MASK (0xFFFF0000U)
13481#define DCP_CH0OPTS_CLR_RSVD_SHIFT (16U)
13482#define DCP_CH0OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK)
13488#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
13489#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
13490#define DCP_CH0OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK)
13491
13492#define DCP_CH0OPTS_TOG_RSVD_MASK (0xFFFF0000U)
13493#define DCP_CH0OPTS_TOG_RSVD_SHIFT (16U)
13494#define DCP_CH0OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK)
13500#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)
13501#define DCP_CH1CMDPTR_ADDR_SHIFT (0U)
13502#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)
13508#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU)
13509#define DCP_CH1SEMA_INCREMENT_SHIFT (0U)
13510#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)
13511
13512#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U)
13513#define DCP_CH1SEMA_VALUE_SHIFT (16U)
13514#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)
13520#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)
13521#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)
13522#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)
13523
13524#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)
13525#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)
13526#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)
13527
13528#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)
13529#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)
13530#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)
13531
13532#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)
13533#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)
13534#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)
13535
13536#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U)
13537#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U)
13538#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)
13539
13540#define DCP_CH1STAT_ERROR_DST_MASK (0x20U)
13541#define DCP_CH1STAT_ERROR_DST_SHIFT (5U)
13542#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)
13543
13544#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)
13545#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)
13546#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)
13547
13548#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)
13549#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U)
13557#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)
13558
13559#define DCP_CH1STAT_TAG_MASK (0xFF000000U)
13560#define DCP_CH1STAT_TAG_SHIFT (24U)
13561#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)
13567#define DCP_CH1STAT_SET_RSVD_COMPLETE_MASK (0x1U)
13568#define DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT (0U)
13569#define DCP_CH1STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK)
13570
13571#define DCP_CH1STAT_SET_HASH_MISMATCH_MASK (0x2U)
13572#define DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT (1U)
13573#define DCP_CH1STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK)
13574
13575#define DCP_CH1STAT_SET_ERROR_SETUP_MASK (0x4U)
13576#define DCP_CH1STAT_SET_ERROR_SETUP_SHIFT (2U)
13577#define DCP_CH1STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK)
13578
13579#define DCP_CH1STAT_SET_ERROR_PACKET_MASK (0x8U)
13580#define DCP_CH1STAT_SET_ERROR_PACKET_SHIFT (3U)
13581#define DCP_CH1STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK)
13582
13583#define DCP_CH1STAT_SET_ERROR_SRC_MASK (0x10U)
13584#define DCP_CH1STAT_SET_ERROR_SRC_SHIFT (4U)
13585#define DCP_CH1STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK)
13586
13587#define DCP_CH1STAT_SET_ERROR_DST_MASK (0x20U)
13588#define DCP_CH1STAT_SET_ERROR_DST_SHIFT (5U)
13589#define DCP_CH1STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK)
13590
13591#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
13592#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
13593#define DCP_CH1STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK)
13594
13595#define DCP_CH1STAT_SET_ERROR_CODE_MASK (0xFF0000U)
13596#define DCP_CH1STAT_SET_ERROR_CODE_SHIFT (16U)
13604#define DCP_CH1STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK)
13605
13606#define DCP_CH1STAT_SET_TAG_MASK (0xFF000000U)
13607#define DCP_CH1STAT_SET_TAG_SHIFT (24U)
13608#define DCP_CH1STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK)
13614#define DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
13615#define DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
13616#define DCP_CH1STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK)
13617
13618#define DCP_CH1STAT_CLR_HASH_MISMATCH_MASK (0x2U)
13619#define DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT (1U)
13620#define DCP_CH1STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK)
13621
13622#define DCP_CH1STAT_CLR_ERROR_SETUP_MASK (0x4U)
13623#define DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT (2U)
13624#define DCP_CH1STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK)
13625
13626#define DCP_CH1STAT_CLR_ERROR_PACKET_MASK (0x8U)
13627#define DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT (3U)
13628#define DCP_CH1STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK)
13629
13630#define DCP_CH1STAT_CLR_ERROR_SRC_MASK (0x10U)
13631#define DCP_CH1STAT_CLR_ERROR_SRC_SHIFT (4U)
13632#define DCP_CH1STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK)
13633
13634#define DCP_CH1STAT_CLR_ERROR_DST_MASK (0x20U)
13635#define DCP_CH1STAT_CLR_ERROR_DST_SHIFT (5U)
13636#define DCP_CH1STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK)
13637
13638#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
13639#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
13640#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK)
13641
13642#define DCP_CH1STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
13643#define DCP_CH1STAT_CLR_ERROR_CODE_SHIFT (16U)
13651#define DCP_CH1STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK)
13652
13653#define DCP_CH1STAT_CLR_TAG_MASK (0xFF000000U)
13654#define DCP_CH1STAT_CLR_TAG_SHIFT (24U)
13655#define DCP_CH1STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK)
13661#define DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
13662#define DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
13663#define DCP_CH1STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK)
13664
13665#define DCP_CH1STAT_TOG_HASH_MISMATCH_MASK (0x2U)
13666#define DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT (1U)
13667#define DCP_CH1STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK)
13668
13669#define DCP_CH1STAT_TOG_ERROR_SETUP_MASK (0x4U)
13670#define DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT (2U)
13671#define DCP_CH1STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK)
13672
13673#define DCP_CH1STAT_TOG_ERROR_PACKET_MASK (0x8U)
13674#define DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT (3U)
13675#define DCP_CH1STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK)
13676
13677#define DCP_CH1STAT_TOG_ERROR_SRC_MASK (0x10U)
13678#define DCP_CH1STAT_TOG_ERROR_SRC_SHIFT (4U)
13679#define DCP_CH1STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK)
13680
13681#define DCP_CH1STAT_TOG_ERROR_DST_MASK (0x20U)
13682#define DCP_CH1STAT_TOG_ERROR_DST_SHIFT (5U)
13683#define DCP_CH1STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK)
13684
13685#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
13686#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
13687#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK)
13688
13689#define DCP_CH1STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
13690#define DCP_CH1STAT_TOG_ERROR_CODE_SHIFT (16U)
13698#define DCP_CH1STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK)
13699
13700#define DCP_CH1STAT_TOG_TAG_MASK (0xFF000000U)
13701#define DCP_CH1STAT_TOG_TAG_SHIFT (24U)
13702#define DCP_CH1STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK)
13708#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
13709#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)
13710#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)
13711
13712#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)
13713#define DCP_CH1OPTS_RSVD_SHIFT (16U)
13714#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)
13720#define DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
13721#define DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
13722#define DCP_CH1OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK)
13723
13724#define DCP_CH1OPTS_SET_RSVD_MASK (0xFFFF0000U)
13725#define DCP_CH1OPTS_SET_RSVD_SHIFT (16U)
13726#define DCP_CH1OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK)
13732#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
13733#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
13734#define DCP_CH1OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK)
13735
13736#define DCP_CH1OPTS_CLR_RSVD_MASK (0xFFFF0000U)
13737#define DCP_CH1OPTS_CLR_RSVD_SHIFT (16U)
13738#define DCP_CH1OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK)
13744#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
13745#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
13746#define DCP_CH1OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK)
13747
13748#define DCP_CH1OPTS_TOG_RSVD_MASK (0xFFFF0000U)
13749#define DCP_CH1OPTS_TOG_RSVD_SHIFT (16U)
13750#define DCP_CH1OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK)
13756#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)
13757#define DCP_CH2CMDPTR_ADDR_SHIFT (0U)
13758#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)
13764#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU)
13765#define DCP_CH2SEMA_INCREMENT_SHIFT (0U)
13766#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)
13767
13768#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U)
13769#define DCP_CH2SEMA_VALUE_SHIFT (16U)
13770#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)
13776#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)
13777#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)
13778#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)
13779
13780#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)
13781#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)
13782#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)
13783
13784#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U)
13785#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U)
13786#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)
13787
13788#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U)
13789#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U)
13790#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)
13791
13792#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U)
13793#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U)
13794#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)
13795
13796#define DCP_CH2STAT_ERROR_DST_MASK (0x20U)
13797#define DCP_CH2STAT_ERROR_DST_SHIFT (5U)
13798#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)
13799
13800#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)
13801#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)
13802#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)
13803
13804#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)
13805#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U)
13813#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)
13814
13815#define DCP_CH2STAT_TAG_MASK (0xFF000000U)
13816#define DCP_CH2STAT_TAG_SHIFT (24U)
13817#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)
13823#define DCP_CH2STAT_SET_RSVD_COMPLETE_MASK (0x1U)
13824#define DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT (0U)
13825#define DCP_CH2STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK)
13826
13827#define DCP_CH2STAT_SET_HASH_MISMATCH_MASK (0x2U)
13828#define DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT (1U)
13829#define DCP_CH2STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK)
13830
13831#define DCP_CH2STAT_SET_ERROR_SETUP_MASK (0x4U)
13832#define DCP_CH2STAT_SET_ERROR_SETUP_SHIFT (2U)
13833#define DCP_CH2STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK)
13834
13835#define DCP_CH2STAT_SET_ERROR_PACKET_MASK (0x8U)
13836#define DCP_CH2STAT_SET_ERROR_PACKET_SHIFT (3U)
13837#define DCP_CH2STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK)
13838
13839#define DCP_CH2STAT_SET_ERROR_SRC_MASK (0x10U)
13840#define DCP_CH2STAT_SET_ERROR_SRC_SHIFT (4U)
13841#define DCP_CH2STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK)
13842
13843#define DCP_CH2STAT_SET_ERROR_DST_MASK (0x20U)
13844#define DCP_CH2STAT_SET_ERROR_DST_SHIFT (5U)
13845#define DCP_CH2STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK)
13846
13847#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
13848#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
13849#define DCP_CH2STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK)
13850
13851#define DCP_CH2STAT_SET_ERROR_CODE_MASK (0xFF0000U)
13852#define DCP_CH2STAT_SET_ERROR_CODE_SHIFT (16U)
13860#define DCP_CH2STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK)
13861
13862#define DCP_CH2STAT_SET_TAG_MASK (0xFF000000U)
13863#define DCP_CH2STAT_SET_TAG_SHIFT (24U)
13864#define DCP_CH2STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK)
13870#define DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
13871#define DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
13872#define DCP_CH2STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK)
13873
13874#define DCP_CH2STAT_CLR_HASH_MISMATCH_MASK (0x2U)
13875#define DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT (1U)
13876#define DCP_CH2STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK)
13877
13878#define DCP_CH2STAT_CLR_ERROR_SETUP_MASK (0x4U)
13879#define DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT (2U)
13880#define DCP_CH2STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK)
13881
13882#define DCP_CH2STAT_CLR_ERROR_PACKET_MASK (0x8U)
13883#define DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT (3U)
13884#define DCP_CH2STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK)
13885
13886#define DCP_CH2STAT_CLR_ERROR_SRC_MASK (0x10U)
13887#define DCP_CH2STAT_CLR_ERROR_SRC_SHIFT (4U)
13888#define DCP_CH2STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK)
13889
13890#define DCP_CH2STAT_CLR_ERROR_DST_MASK (0x20U)
13891#define DCP_CH2STAT_CLR_ERROR_DST_SHIFT (5U)
13892#define DCP_CH2STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK)
13893
13894#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
13895#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
13896#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK)
13897
13898#define DCP_CH2STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
13899#define DCP_CH2STAT_CLR_ERROR_CODE_SHIFT (16U)
13907#define DCP_CH2STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK)
13908
13909#define DCP_CH2STAT_CLR_TAG_MASK (0xFF000000U)
13910#define DCP_CH2STAT_CLR_TAG_SHIFT (24U)
13911#define DCP_CH2STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK)
13917#define DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
13918#define DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
13919#define DCP_CH2STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK)
13920
13921#define DCP_CH2STAT_TOG_HASH_MISMATCH_MASK (0x2U)
13922#define DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT (1U)
13923#define DCP_CH2STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK)
13924
13925#define DCP_CH2STAT_TOG_ERROR_SETUP_MASK (0x4U)
13926#define DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT (2U)
13927#define DCP_CH2STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK)
13928
13929#define DCP_CH2STAT_TOG_ERROR_PACKET_MASK (0x8U)
13930#define DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT (3U)
13931#define DCP_CH2STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK)
13932
13933#define DCP_CH2STAT_TOG_ERROR_SRC_MASK (0x10U)
13934#define DCP_CH2STAT_TOG_ERROR_SRC_SHIFT (4U)
13935#define DCP_CH2STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK)
13936
13937#define DCP_CH2STAT_TOG_ERROR_DST_MASK (0x20U)
13938#define DCP_CH2STAT_TOG_ERROR_DST_SHIFT (5U)
13939#define DCP_CH2STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK)
13940
13941#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
13942#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
13943#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK)
13944
13945#define DCP_CH2STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
13946#define DCP_CH2STAT_TOG_ERROR_CODE_SHIFT (16U)
13954#define DCP_CH2STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK)
13955
13956#define DCP_CH2STAT_TOG_TAG_MASK (0xFF000000U)
13957#define DCP_CH2STAT_TOG_TAG_SHIFT (24U)
13958#define DCP_CH2STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK)
13964#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
13965#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)
13966#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)
13967
13968#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)
13969#define DCP_CH2OPTS_RSVD_SHIFT (16U)
13970#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)
13976#define DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
13977#define DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
13978#define DCP_CH2OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK)
13979
13980#define DCP_CH2OPTS_SET_RSVD_MASK (0xFFFF0000U)
13981#define DCP_CH2OPTS_SET_RSVD_SHIFT (16U)
13982#define DCP_CH2OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK)
13988#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
13989#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
13990#define DCP_CH2OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK)
13991
13992#define DCP_CH2OPTS_CLR_RSVD_MASK (0xFFFF0000U)
13993#define DCP_CH2OPTS_CLR_RSVD_SHIFT (16U)
13994#define DCP_CH2OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK)
14000#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
14001#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
14002#define DCP_CH2OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK)
14003
14004#define DCP_CH2OPTS_TOG_RSVD_MASK (0xFFFF0000U)
14005#define DCP_CH2OPTS_TOG_RSVD_SHIFT (16U)
14006#define DCP_CH2OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RSVD_SHIFT)) & DCP_CH2OPTS_TOG_RSVD_MASK)
14012#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU)
14013#define DCP_CH3CMDPTR_ADDR_SHIFT (0U)
14014#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)
14020#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU)
14021#define DCP_CH3SEMA_INCREMENT_SHIFT (0U)
14022#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)
14023
14024#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U)
14025#define DCP_CH3SEMA_VALUE_SHIFT (16U)
14026#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)
14032#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U)
14033#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U)
14034#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)
14035
14036#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U)
14037#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U)
14038#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)
14039
14040#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U)
14041#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U)
14042#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)
14043
14044#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U)
14045#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U)
14046#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)
14047
14048#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U)
14049#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U)
14050#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)
14051
14052#define DCP_CH3STAT_ERROR_DST_MASK (0x20U)
14053#define DCP_CH3STAT_ERROR_DST_SHIFT (5U)
14054#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)
14055
14056#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U)
14057#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U)
14058#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)
14059
14060#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U)
14061#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U)
14069#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)
14070
14071#define DCP_CH3STAT_TAG_MASK (0xFF000000U)
14072#define DCP_CH3STAT_TAG_SHIFT (24U)
14073#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)
14079#define DCP_CH3STAT_SET_RSVD_COMPLETE_MASK (0x1U)
14080#define DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT (0U)
14081#define DCP_CH3STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_SET_RSVD_COMPLETE_MASK)
14082
14083#define DCP_CH3STAT_SET_HASH_MISMATCH_MASK (0x2U)
14084#define DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT (1U)
14085#define DCP_CH3STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_SET_HASH_MISMATCH_MASK)
14086
14087#define DCP_CH3STAT_SET_ERROR_SETUP_MASK (0x4U)
14088#define DCP_CH3STAT_SET_ERROR_SETUP_SHIFT (2U)
14089#define DCP_CH3STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_SET_ERROR_SETUP_MASK)
14090
14091#define DCP_CH3STAT_SET_ERROR_PACKET_MASK (0x8U)
14092#define DCP_CH3STAT_SET_ERROR_PACKET_SHIFT (3U)
14093#define DCP_CH3STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_SET_ERROR_PACKET_MASK)
14094
14095#define DCP_CH3STAT_SET_ERROR_SRC_MASK (0x10U)
14096#define DCP_CH3STAT_SET_ERROR_SRC_SHIFT (4U)
14097#define DCP_CH3STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH3STAT_SET_ERROR_SRC_MASK)
14098
14099#define DCP_CH3STAT_SET_ERROR_DST_MASK (0x20U)
14100#define DCP_CH3STAT_SET_ERROR_DST_SHIFT (5U)
14101#define DCP_CH3STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_DST_SHIFT)) & DCP_CH3STAT_SET_ERROR_DST_MASK)
14102
14103#define DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
14104#define DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
14105#define DCP_CH3STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK)
14106
14107#define DCP_CH3STAT_SET_ERROR_CODE_MASK (0xFF0000U)
14108#define DCP_CH3STAT_SET_ERROR_CODE_SHIFT (16U)
14116#define DCP_CH3STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH3STAT_SET_ERROR_CODE_MASK)
14117
14118#define DCP_CH3STAT_SET_TAG_MASK (0xFF000000U)
14119#define DCP_CH3STAT_SET_TAG_SHIFT (24U)
14120#define DCP_CH3STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_TAG_SHIFT)) & DCP_CH3STAT_SET_TAG_MASK)
14126#define DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
14127#define DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
14128#define DCP_CH3STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK)
14129
14130#define DCP_CH3STAT_CLR_HASH_MISMATCH_MASK (0x2U)
14131#define DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT (1U)
14132#define DCP_CH3STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_CLR_HASH_MISMATCH_MASK)
14133
14134#define DCP_CH3STAT_CLR_ERROR_SETUP_MASK (0x4U)
14135#define DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT (2U)
14136#define DCP_CH3STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SETUP_MASK)
14137
14138#define DCP_CH3STAT_CLR_ERROR_PACKET_MASK (0x8U)
14139#define DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT (3U)
14140#define DCP_CH3STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PACKET_MASK)
14141
14142#define DCP_CH3STAT_CLR_ERROR_SRC_MASK (0x10U)
14143#define DCP_CH3STAT_CLR_ERROR_SRC_SHIFT (4U)
14144#define DCP_CH3STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SRC_MASK)
14145
14146#define DCP_CH3STAT_CLR_ERROR_DST_MASK (0x20U)
14147#define DCP_CH3STAT_CLR_ERROR_DST_SHIFT (5U)
14148#define DCP_CH3STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH3STAT_CLR_ERROR_DST_MASK)
14149
14150#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
14151#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
14152#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK)
14153
14154#define DCP_CH3STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
14155#define DCP_CH3STAT_CLR_ERROR_CODE_SHIFT (16U)
14163#define DCP_CH3STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH3STAT_CLR_ERROR_CODE_MASK)
14164
14165#define DCP_CH3STAT_CLR_TAG_MASK (0xFF000000U)
14166#define DCP_CH3STAT_CLR_TAG_SHIFT (24U)
14167#define DCP_CH3STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_TAG_SHIFT)) & DCP_CH3STAT_CLR_TAG_MASK)
14173#define DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
14174#define DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
14175#define DCP_CH3STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK)
14176
14177#define DCP_CH3STAT_TOG_HASH_MISMATCH_MASK (0x2U)
14178#define DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT (1U)
14179#define DCP_CH3STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_TOG_HASH_MISMATCH_MASK)
14180
14181#define DCP_CH3STAT_TOG_ERROR_SETUP_MASK (0x4U)
14182#define DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT (2U)
14183#define DCP_CH3STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SETUP_MASK)
14184
14185#define DCP_CH3STAT_TOG_ERROR_PACKET_MASK (0x8U)
14186#define DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT (3U)
14187#define DCP_CH3STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PACKET_MASK)
14188
14189#define DCP_CH3STAT_TOG_ERROR_SRC_MASK (0x10U)
14190#define DCP_CH3STAT_TOG_ERROR_SRC_SHIFT (4U)
14191#define DCP_CH3STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SRC_MASK)
14192
14193#define DCP_CH3STAT_TOG_ERROR_DST_MASK (0x20U)
14194#define DCP_CH3STAT_TOG_ERROR_DST_SHIFT (5U)
14195#define DCP_CH3STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH3STAT_TOG_ERROR_DST_MASK)
14196
14197#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
14198#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
14199#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK)
14200
14201#define DCP_CH3STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
14202#define DCP_CH3STAT_TOG_ERROR_CODE_SHIFT (16U)
14210#define DCP_CH3STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH3STAT_TOG_ERROR_CODE_MASK)
14211
14212#define DCP_CH3STAT_TOG_TAG_MASK (0xFF000000U)
14213#define DCP_CH3STAT_TOG_TAG_SHIFT (24U)
14214#define DCP_CH3STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_TAG_SHIFT)) & DCP_CH3STAT_TOG_TAG_MASK)
14220#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
14221#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)
14222#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)
14223
14224#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)
14225#define DCP_CH3OPTS_RSVD_SHIFT (16U)
14226#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)
14232#define DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
14233#define DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
14234#define DCP_CH3OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK)
14235
14236#define DCP_CH3OPTS_SET_RSVD_MASK (0xFFFF0000U)
14237#define DCP_CH3OPTS_SET_RSVD_SHIFT (16U)
14238#define DCP_CH3OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RSVD_SHIFT)) & DCP_CH3OPTS_SET_RSVD_MASK)
14244#define DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
14245#define DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
14246#define DCP_CH3OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK)
14247
14248#define DCP_CH3OPTS_CLR_RSVD_MASK (0xFFFF0000U)
14249#define DCP_CH3OPTS_CLR_RSVD_SHIFT (16U)
14250#define DCP_CH3OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RSVD_SHIFT)) & DCP_CH3OPTS_CLR_RSVD_MASK)
14256#define DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
14257#define DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
14258#define DCP_CH3OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK)
14259
14260#define DCP_CH3OPTS_TOG_RSVD_MASK (0xFFFF0000U)
14261#define DCP_CH3OPTS_TOG_RSVD_SHIFT (16U)
14262#define DCP_CH3OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RSVD_SHIFT)) & DCP_CH3OPTS_TOG_RSVD_MASK)
14268#define DCP_DBGSELECT_INDEX_MASK (0xFFU)
14269#define DCP_DBGSELECT_INDEX_SHIFT (0U)
14277#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)
14278
14279#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)
14280#define DCP_DBGSELECT_RSVD_SHIFT (8U)
14281#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)
14287#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)
14288#define DCP_DBGDATA_DATA_SHIFT (0U)
14289#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)
14295#define DCP_PAGETABLE_ENABLE_MASK (0x1U)
14296#define DCP_PAGETABLE_ENABLE_SHIFT (0U)
14297#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)
14298
14299#define DCP_PAGETABLE_FLUSH_MASK (0x2U)
14300#define DCP_PAGETABLE_FLUSH_SHIFT (1U)
14301#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)
14302
14303#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)
14304#define DCP_PAGETABLE_BASE_SHIFT (2U)
14305#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)
14311#define DCP_VERSION_STEP_MASK (0xFFFFU)
14312#define DCP_VERSION_STEP_SHIFT (0U)
14313#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)
14314
14315#define DCP_VERSION_MINOR_MASK (0xFF0000U)
14316#define DCP_VERSION_MINOR_SHIFT (16U)
14317#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)
14318
14319#define DCP_VERSION_MAJOR_MASK (0xFF000000U)
14320#define DCP_VERSION_MAJOR_SHIFT (24U)
14321#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) /* end of group DCP_Register_Masks */
14328
14329
14330/* DCP - Peripheral instance base addresses */
14332#define DCP_BASE (0x402FC000u)
14334#define DCP ((DCP_Type *)DCP_BASE)
14336#define DCP_BASE_ADDRS { DCP_BASE }
14338#define DCP_BASE_PTRS { DCP }
14340#define DCP_IRQS { DCP_IRQn }
14341#define DCP_VMI_IRQS { DCP_VMI_IRQn }
14342 /* end of group DCP_Peripheral_Access_Layer */
14346
14347
14348/* ----------------------------------------------------------------------------
14349 -- DMA Peripheral Access Layer
14350 ---------------------------------------------------------------------------- */
14351
14358typedef struct {
14359 __IO uint32_t CR;
14360 __I uint32_t ES;
14361 uint8_t RESERVED_0[4];
14362 __IO uint32_t ERQ;
14363 uint8_t RESERVED_1[4];
14364 __IO uint32_t EEI;
14365 __O uint8_t CEEI;
14366 __O uint8_t SEEI;
14367 __O uint8_t CERQ;
14368 __O uint8_t SERQ;
14369 __O uint8_t CDNE;
14370 __O uint8_t SSRT;
14371 __O uint8_t CERR;
14372 __O uint8_t CINT;
14373 uint8_t RESERVED_2[4];
14374 __IO uint32_t INT;
14375 uint8_t RESERVED_3[4];
14376 __IO uint32_t ERR;
14377 uint8_t RESERVED_4[4];
14378 __I uint32_t HRS;
14379 uint8_t RESERVED_5[12];
14380 __IO uint32_t EARS;
14381 uint8_t RESERVED_6[184];
14382 __IO uint8_t DCHPRI3;
14383 __IO uint8_t DCHPRI2;
14384 __IO uint8_t DCHPRI1;
14385 __IO uint8_t DCHPRI0;
14386 __IO uint8_t DCHPRI7;
14387 __IO uint8_t DCHPRI6;
14388 __IO uint8_t DCHPRI5;
14389 __IO uint8_t DCHPRI4;
14390 __IO uint8_t DCHPRI11;
14391 __IO uint8_t DCHPRI10;
14392 __IO uint8_t DCHPRI9;
14393 __IO uint8_t DCHPRI8;
14394 __IO uint8_t DCHPRI15;
14395 __IO uint8_t DCHPRI14;
14396 __IO uint8_t DCHPRI13;
14397 __IO uint8_t DCHPRI12;
14398 __IO uint8_t DCHPRI19;
14399 __IO uint8_t DCHPRI18;
14400 __IO uint8_t DCHPRI17;
14401 __IO uint8_t DCHPRI16;
14402 __IO uint8_t DCHPRI23;
14403 __IO uint8_t DCHPRI22;
14404 __IO uint8_t DCHPRI21;
14405 __IO uint8_t DCHPRI20;
14406 __IO uint8_t DCHPRI27;
14407 __IO uint8_t DCHPRI26;
14408 __IO uint8_t DCHPRI25;
14409 __IO uint8_t DCHPRI24;
14410 __IO uint8_t DCHPRI31;
14411 __IO uint8_t DCHPRI30;
14412 __IO uint8_t DCHPRI29;
14413 __IO uint8_t DCHPRI28;
14414 uint8_t RESERVED_7[3808];
14415 struct { /* offset: 0x1000, array step: 0x20 */
14416 __IO uint32_t SADDR;
14417 __IO uint16_t SOFF;
14418 __IO uint16_t ATTR;
14419 union { /* offset: 0x1008, array step: 0x20 */
14420 __IO uint32_t NBYTES_MLNO;
14421 __IO uint32_t NBYTES_MLOFFNO;
14422 __IO uint32_t NBYTES_MLOFFYES;
14423 };
14424 __IO int32_t SLAST;
14425 __IO uint32_t DADDR;
14426 __IO uint16_t DOFF;
14427 union { /* offset: 0x1016, array step: 0x20 */
14428 __IO uint16_t CITER_ELINKNO;
14429 __IO uint16_t CITER_ELINKYES;
14430 };
14431 __IO int32_t DLAST_SGA;
14432 __IO uint16_t CSR;
14433 union { /* offset: 0x101E, array step: 0x20 */
14434 __IO uint16_t BITER_ELINKNO;
14435 __IO uint16_t BITER_ELINKYES;
14436 };
14437 } TCD[32];
14438} DMA_Type;
14439
14440/* ----------------------------------------------------------------------------
14441 -- DMA Register Masks
14442 ---------------------------------------------------------------------------- */
14443
14452#define DMA_CR_EDBG_MASK (0x2U)
14453#define DMA_CR_EDBG_SHIFT (1U)
14458#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
14459
14460#define DMA_CR_ERCA_MASK (0x4U)
14461#define DMA_CR_ERCA_SHIFT (2U)
14466#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
14467
14468#define DMA_CR_ERGA_MASK (0x8U)
14469#define DMA_CR_ERGA_SHIFT (3U)
14474#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
14475
14476#define DMA_CR_HOE_MASK (0x10U)
14477#define DMA_CR_HOE_SHIFT (4U)
14482#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
14483
14484#define DMA_CR_HALT_MASK (0x20U)
14485#define DMA_CR_HALT_SHIFT (5U)
14490#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
14491
14492#define DMA_CR_CLM_MASK (0x40U)
14493#define DMA_CR_CLM_SHIFT (6U)
14498#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
14499
14500#define DMA_CR_EMLM_MASK (0x80U)
14501#define DMA_CR_EMLM_SHIFT (7U)
14506#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
14507
14508#define DMA_CR_GRP0PRI_MASK (0x100U)
14509#define DMA_CR_GRP0PRI_SHIFT (8U)
14512#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
14513
14514#define DMA_CR_GRP1PRI_MASK (0x400U)
14515#define DMA_CR_GRP1PRI_SHIFT (10U)
14518#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
14519
14520#define DMA_CR_ECX_MASK (0x10000U)
14521#define DMA_CR_ECX_SHIFT (16U)
14526#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
14527
14528#define DMA_CR_CX_MASK (0x20000U)
14529#define DMA_CR_CX_SHIFT (17U)
14534#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
14535
14536#define DMA_CR_VERSION_MASK (0x7F000000U)
14537#define DMA_CR_VERSION_SHIFT (24U)
14540#define DMA_CR_VERSION(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK)
14541
14542#define DMA_CR_ACTIVE_MASK (0x80000000U)
14543#define DMA_CR_ACTIVE_SHIFT (31U)
14548#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
14554#define DMA_ES_DBE_MASK (0x1U)
14555#define DMA_ES_DBE_SHIFT (0U)
14560#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
14561
14562#define DMA_ES_SBE_MASK (0x2U)
14563#define DMA_ES_SBE_SHIFT (1U)
14568#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
14569
14570#define DMA_ES_SGE_MASK (0x4U)
14571#define DMA_ES_SGE_SHIFT (2U)
14576#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
14577
14578#define DMA_ES_NCE_MASK (0x8U)
14579#define DMA_ES_NCE_SHIFT (3U)
14586#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
14587
14588#define DMA_ES_DOE_MASK (0x10U)
14589#define DMA_ES_DOE_SHIFT (4U)
14594#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
14595
14596#define DMA_ES_DAE_MASK (0x20U)
14597#define DMA_ES_DAE_SHIFT (5U)
14603#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
14604
14605#define DMA_ES_SOE_MASK (0x40U)
14606#define DMA_ES_SOE_SHIFT (6U)
14611#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
14612
14613#define DMA_ES_SAE_MASK (0x80U)
14614#define DMA_ES_SAE_SHIFT (7U)
14620#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
14621
14622#define DMA_ES_ERRCHN_MASK (0x1F00U)
14623#define DMA_ES_ERRCHN_SHIFT (8U)
14626#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
14627
14628#define DMA_ES_CPE_MASK (0x4000U)
14629#define DMA_ES_CPE_SHIFT (14U)
14635#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
14636
14637#define DMA_ES_GPE_MASK (0x8000U)
14638#define DMA_ES_GPE_SHIFT (15U)
14643#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
14644
14645#define DMA_ES_ECX_MASK (0x10000U)
14646#define DMA_ES_ECX_SHIFT (16U)
14651#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
14652
14653#define DMA_ES_VLD_MASK (0x80000000U)
14654#define DMA_ES_VLD_SHIFT (31U)
14659#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
14665#define DMA_ERQ_ERQ0_MASK (0x1U)
14666#define DMA_ERQ_ERQ0_SHIFT (0U)
14671#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
14672
14673#define DMA_ERQ_ERQ1_MASK (0x2U)
14674#define DMA_ERQ_ERQ1_SHIFT (1U)
14679#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
14680
14681#define DMA_ERQ_ERQ2_MASK (0x4U)
14682#define DMA_ERQ_ERQ2_SHIFT (2U)
14687#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
14688
14689#define DMA_ERQ_ERQ3_MASK (0x8U)
14690#define DMA_ERQ_ERQ3_SHIFT (3U)
14695#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
14696
14697#define DMA_ERQ_ERQ4_MASK (0x10U)
14698#define DMA_ERQ_ERQ4_SHIFT (4U)
14703#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
14704
14705#define DMA_ERQ_ERQ5_MASK (0x20U)
14706#define DMA_ERQ_ERQ5_SHIFT (5U)
14711#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
14712
14713#define DMA_ERQ_ERQ6_MASK (0x40U)
14714#define DMA_ERQ_ERQ6_SHIFT (6U)
14719#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
14720
14721#define DMA_ERQ_ERQ7_MASK (0x80U)
14722#define DMA_ERQ_ERQ7_SHIFT (7U)
14727#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
14728
14729#define DMA_ERQ_ERQ8_MASK (0x100U)
14730#define DMA_ERQ_ERQ8_SHIFT (8U)
14735#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
14736
14737#define DMA_ERQ_ERQ9_MASK (0x200U)
14738#define DMA_ERQ_ERQ9_SHIFT (9U)
14743#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
14744
14745#define DMA_ERQ_ERQ10_MASK (0x400U)
14746#define DMA_ERQ_ERQ10_SHIFT (10U)
14751#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
14752
14753#define DMA_ERQ_ERQ11_MASK (0x800U)
14754#define DMA_ERQ_ERQ11_SHIFT (11U)
14759#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
14760
14761#define DMA_ERQ_ERQ12_MASK (0x1000U)
14762#define DMA_ERQ_ERQ12_SHIFT (12U)
14767#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
14768
14769#define DMA_ERQ_ERQ13_MASK (0x2000U)
14770#define DMA_ERQ_ERQ13_SHIFT (13U)
14775#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
14776
14777#define DMA_ERQ_ERQ14_MASK (0x4000U)
14778#define DMA_ERQ_ERQ14_SHIFT (14U)
14783#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
14784
14785#define DMA_ERQ_ERQ15_MASK (0x8000U)
14786#define DMA_ERQ_ERQ15_SHIFT (15U)
14791#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
14792
14793#define DMA_ERQ_ERQ16_MASK (0x10000U)
14794#define DMA_ERQ_ERQ16_SHIFT (16U)
14799#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
14800
14801#define DMA_ERQ_ERQ17_MASK (0x20000U)
14802#define DMA_ERQ_ERQ17_SHIFT (17U)
14807#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
14808
14809#define DMA_ERQ_ERQ18_MASK (0x40000U)
14810#define DMA_ERQ_ERQ18_SHIFT (18U)
14815#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
14816
14817#define DMA_ERQ_ERQ19_MASK (0x80000U)
14818#define DMA_ERQ_ERQ19_SHIFT (19U)
14823#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
14824
14825#define DMA_ERQ_ERQ20_MASK (0x100000U)
14826#define DMA_ERQ_ERQ20_SHIFT (20U)
14831#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
14832
14833#define DMA_ERQ_ERQ21_MASK (0x200000U)
14834#define DMA_ERQ_ERQ21_SHIFT (21U)
14839#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
14840
14841#define DMA_ERQ_ERQ22_MASK (0x400000U)
14842#define DMA_ERQ_ERQ22_SHIFT (22U)
14847#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
14848
14849#define DMA_ERQ_ERQ23_MASK (0x800000U)
14850#define DMA_ERQ_ERQ23_SHIFT (23U)
14855#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
14856
14857#define DMA_ERQ_ERQ24_MASK (0x1000000U)
14858#define DMA_ERQ_ERQ24_SHIFT (24U)
14863#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
14864
14865#define DMA_ERQ_ERQ25_MASK (0x2000000U)
14866#define DMA_ERQ_ERQ25_SHIFT (25U)
14871#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
14872
14873#define DMA_ERQ_ERQ26_MASK (0x4000000U)
14874#define DMA_ERQ_ERQ26_SHIFT (26U)
14879#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
14880
14881#define DMA_ERQ_ERQ27_MASK (0x8000000U)
14882#define DMA_ERQ_ERQ27_SHIFT (27U)
14887#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
14888
14889#define DMA_ERQ_ERQ28_MASK (0x10000000U)
14890#define DMA_ERQ_ERQ28_SHIFT (28U)
14895#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
14896
14897#define DMA_ERQ_ERQ29_MASK (0x20000000U)
14898#define DMA_ERQ_ERQ29_SHIFT (29U)
14903#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
14904
14905#define DMA_ERQ_ERQ30_MASK (0x40000000U)
14906#define DMA_ERQ_ERQ30_SHIFT (30U)
14911#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
14912
14913#define DMA_ERQ_ERQ31_MASK (0x80000000U)
14914#define DMA_ERQ_ERQ31_SHIFT (31U)
14919#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
14925#define DMA_EEI_EEI0_MASK (0x1U)
14926#define DMA_EEI_EEI0_SHIFT (0U)
14931#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
14932
14933#define DMA_EEI_EEI1_MASK (0x2U)
14934#define DMA_EEI_EEI1_SHIFT (1U)
14939#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
14940
14941#define DMA_EEI_EEI2_MASK (0x4U)
14942#define DMA_EEI_EEI2_SHIFT (2U)
14947#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
14948
14949#define DMA_EEI_EEI3_MASK (0x8U)
14950#define DMA_EEI_EEI3_SHIFT (3U)
14955#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
14956
14957#define DMA_EEI_EEI4_MASK (0x10U)
14958#define DMA_EEI_EEI4_SHIFT (4U)
14963#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
14964
14965#define DMA_EEI_EEI5_MASK (0x20U)
14966#define DMA_EEI_EEI5_SHIFT (5U)
14971#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
14972
14973#define DMA_EEI_EEI6_MASK (0x40U)
14974#define DMA_EEI_EEI6_SHIFT (6U)
14979#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
14980
14981#define DMA_EEI_EEI7_MASK (0x80U)
14982#define DMA_EEI_EEI7_SHIFT (7U)
14987#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
14988
14989#define DMA_EEI_EEI8_MASK (0x100U)
14990#define DMA_EEI_EEI8_SHIFT (8U)
14995#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
14996
14997#define DMA_EEI_EEI9_MASK (0x200U)
14998#define DMA_EEI_EEI9_SHIFT (9U)
15003#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
15004
15005#define DMA_EEI_EEI10_MASK (0x400U)
15006#define DMA_EEI_EEI10_SHIFT (10U)
15011#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
15012
15013#define DMA_EEI_EEI11_MASK (0x800U)
15014#define DMA_EEI_EEI11_SHIFT (11U)
15019#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
15020
15021#define DMA_EEI_EEI12_MASK (0x1000U)
15022#define DMA_EEI_EEI12_SHIFT (12U)
15027#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
15028
15029#define DMA_EEI_EEI13_MASK (0x2000U)
15030#define DMA_EEI_EEI13_SHIFT (13U)
15035#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
15036
15037#define DMA_EEI_EEI14_MASK (0x4000U)
15038#define DMA_EEI_EEI14_SHIFT (14U)
15043#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
15044
15045#define DMA_EEI_EEI15_MASK (0x8000U)
15046#define DMA_EEI_EEI15_SHIFT (15U)
15051#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
15052
15053#define DMA_EEI_EEI16_MASK (0x10000U)
15054#define DMA_EEI_EEI16_SHIFT (16U)
15059#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
15060
15061#define DMA_EEI_EEI17_MASK (0x20000U)
15062#define DMA_EEI_EEI17_SHIFT (17U)
15067#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
15068
15069#define DMA_EEI_EEI18_MASK (0x40000U)
15070#define DMA_EEI_EEI18_SHIFT (18U)
15075#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
15076
15077#define DMA_EEI_EEI19_MASK (0x80000U)
15078#define DMA_EEI_EEI19_SHIFT (19U)
15083#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
15084
15085#define DMA_EEI_EEI20_MASK (0x100000U)
15086#define DMA_EEI_EEI20_SHIFT (20U)
15091#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
15092
15093#define DMA_EEI_EEI21_MASK (0x200000U)
15094#define DMA_EEI_EEI21_SHIFT (21U)
15099#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
15100
15101#define DMA_EEI_EEI22_MASK (0x400000U)
15102#define DMA_EEI_EEI22_SHIFT (22U)
15107#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
15108
15109#define DMA_EEI_EEI23_MASK (0x800000U)
15110#define DMA_EEI_EEI23_SHIFT (23U)
15115#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
15116
15117#define DMA_EEI_EEI24_MASK (0x1000000U)
15118#define DMA_EEI_EEI24_SHIFT (24U)
15123#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
15124
15125#define DMA_EEI_EEI25_MASK (0x2000000U)
15126#define DMA_EEI_EEI25_SHIFT (25U)
15131#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
15132
15133#define DMA_EEI_EEI26_MASK (0x4000000U)
15134#define DMA_EEI_EEI26_SHIFT (26U)
15139#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
15140
15141#define DMA_EEI_EEI27_MASK (0x8000000U)
15142#define DMA_EEI_EEI27_SHIFT (27U)
15147#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
15148
15149#define DMA_EEI_EEI28_MASK (0x10000000U)
15150#define DMA_EEI_EEI28_SHIFT (28U)
15155#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
15156
15157#define DMA_EEI_EEI29_MASK (0x20000000U)
15158#define DMA_EEI_EEI29_SHIFT (29U)
15163#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
15164
15165#define DMA_EEI_EEI30_MASK (0x40000000U)
15166#define DMA_EEI_EEI30_SHIFT (30U)
15171#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
15172
15173#define DMA_EEI_EEI31_MASK (0x80000000U)
15174#define DMA_EEI_EEI31_SHIFT (31U)
15179#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
15185#define DMA_CEEI_CEEI_MASK (0x1FU)
15186#define DMA_CEEI_CEEI_SHIFT (0U)
15189#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
15190
15191#define DMA_CEEI_CAEE_MASK (0x40U)
15192#define DMA_CEEI_CAEE_SHIFT (6U)
15197#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
15198
15199#define DMA_CEEI_NOP_MASK (0x80U)
15200#define DMA_CEEI_NOP_SHIFT (7U)
15205#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
15211#define DMA_SEEI_SEEI_MASK (0x1FU)
15212#define DMA_SEEI_SEEI_SHIFT (0U)
15215#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
15216
15217#define DMA_SEEI_SAEE_MASK (0x40U)
15218#define DMA_SEEI_SAEE_SHIFT (6U)
15223#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
15224
15225#define DMA_SEEI_NOP_MASK (0x80U)
15226#define DMA_SEEI_NOP_SHIFT (7U)
15231#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
15237#define DMA_CERQ_CERQ_MASK (0x1FU)
15238#define DMA_CERQ_CERQ_SHIFT (0U)
15241#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
15242
15243#define DMA_CERQ_CAER_MASK (0x40U)
15244#define DMA_CERQ_CAER_SHIFT (6U)
15249#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
15250
15251#define DMA_CERQ_NOP_MASK (0x80U)
15252#define DMA_CERQ_NOP_SHIFT (7U)
15257#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
15263#define DMA_SERQ_SERQ_MASK (0x1FU)
15264#define DMA_SERQ_SERQ_SHIFT (0U)
15267#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
15268
15269#define DMA_SERQ_SAER_MASK (0x40U)
15270#define DMA_SERQ_SAER_SHIFT (6U)
15275#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
15276
15277#define DMA_SERQ_NOP_MASK (0x80U)
15278#define DMA_SERQ_NOP_SHIFT (7U)
15283#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
15289#define DMA_CDNE_CDNE_MASK (0x1FU)
15290#define DMA_CDNE_CDNE_SHIFT (0U)
15293#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
15294
15295#define DMA_CDNE_CADN_MASK (0x40U)
15296#define DMA_CDNE_CADN_SHIFT (6U)
15301#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
15302
15303#define DMA_CDNE_NOP_MASK (0x80U)
15304#define DMA_CDNE_NOP_SHIFT (7U)
15309#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
15315#define DMA_SSRT_SSRT_MASK (0x1FU)
15316#define DMA_SSRT_SSRT_SHIFT (0U)
15319#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
15320
15321#define DMA_SSRT_SAST_MASK (0x40U)
15322#define DMA_SSRT_SAST_SHIFT (6U)
15327#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
15328
15329#define DMA_SSRT_NOP_MASK (0x80U)
15330#define DMA_SSRT_NOP_SHIFT (7U)
15335#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
15341#define DMA_CERR_CERR_MASK (0x1FU)
15342#define DMA_CERR_CERR_SHIFT (0U)
15345#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
15346
15347#define DMA_CERR_CAEI_MASK (0x40U)
15348#define DMA_CERR_CAEI_SHIFT (6U)
15353#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
15354
15355#define DMA_CERR_NOP_MASK (0x80U)
15356#define DMA_CERR_NOP_SHIFT (7U)
15361#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
15367#define DMA_CINT_CINT_MASK (0x1FU)
15368#define DMA_CINT_CINT_SHIFT (0U)
15371#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
15372
15373#define DMA_CINT_CAIR_MASK (0x40U)
15374#define DMA_CINT_CAIR_SHIFT (6U)
15379#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
15380
15381#define DMA_CINT_NOP_MASK (0x80U)
15382#define DMA_CINT_NOP_SHIFT (7U)
15387#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
15393#define DMA_INT_INT0_MASK (0x1U)
15394#define DMA_INT_INT0_SHIFT (0U)
15399#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
15400
15401#define DMA_INT_INT1_MASK (0x2U)
15402#define DMA_INT_INT1_SHIFT (1U)
15407#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
15408
15409#define DMA_INT_INT2_MASK (0x4U)
15410#define DMA_INT_INT2_SHIFT (2U)
15415#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
15416
15417#define DMA_INT_INT3_MASK (0x8U)
15418#define DMA_INT_INT3_SHIFT (3U)
15423#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
15424
15425#define DMA_INT_INT4_MASK (0x10U)
15426#define DMA_INT_INT4_SHIFT (4U)
15431#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
15432
15433#define DMA_INT_INT5_MASK (0x20U)
15434#define DMA_INT_INT5_SHIFT (5U)
15439#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
15440
15441#define DMA_INT_INT6_MASK (0x40U)
15442#define DMA_INT_INT6_SHIFT (6U)
15447#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
15448
15449#define DMA_INT_INT7_MASK (0x80U)
15450#define DMA_INT_INT7_SHIFT (7U)
15455#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
15456
15457#define DMA_INT_INT8_MASK (0x100U)
15458#define DMA_INT_INT8_SHIFT (8U)
15463#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
15464
15465#define DMA_INT_INT9_MASK (0x200U)
15466#define DMA_INT_INT9_SHIFT (9U)
15471#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
15472
15473#define DMA_INT_INT10_MASK (0x400U)
15474#define DMA_INT_INT10_SHIFT (10U)
15479#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
15480
15481#define DMA_INT_INT11_MASK (0x800U)
15482#define DMA_INT_INT11_SHIFT (11U)
15487#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
15488
15489#define DMA_INT_INT12_MASK (0x1000U)
15490#define DMA_INT_INT12_SHIFT (12U)
15495#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
15496
15497#define DMA_INT_INT13_MASK (0x2000U)
15498#define DMA_INT_INT13_SHIFT (13U)
15503#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
15504
15505#define DMA_INT_INT14_MASK (0x4000U)
15506#define DMA_INT_INT14_SHIFT (14U)
15511#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
15512
15513#define DMA_INT_INT15_MASK (0x8000U)
15514#define DMA_INT_INT15_SHIFT (15U)
15519#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
15520
15521#define DMA_INT_INT16_MASK (0x10000U)
15522#define DMA_INT_INT16_SHIFT (16U)
15527#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
15528
15529#define DMA_INT_INT17_MASK (0x20000U)
15530#define DMA_INT_INT17_SHIFT (17U)
15535#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
15536
15537#define DMA_INT_INT18_MASK (0x40000U)
15538#define DMA_INT_INT18_SHIFT (18U)
15543#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
15544
15545#define DMA_INT_INT19_MASK (0x80000U)
15546#define DMA_INT_INT19_SHIFT (19U)
15551#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
15552
15553#define DMA_INT_INT20_MASK (0x100000U)
15554#define DMA_INT_INT20_SHIFT (20U)
15559#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
15560
15561#define DMA_INT_INT21_MASK (0x200000U)
15562#define DMA_INT_INT21_SHIFT (21U)
15567#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
15568
15569#define DMA_INT_INT22_MASK (0x400000U)
15570#define DMA_INT_INT22_SHIFT (22U)
15575#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
15576
15577#define DMA_INT_INT23_MASK (0x800000U)
15578#define DMA_INT_INT23_SHIFT (23U)
15583#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
15584
15585#define DMA_INT_INT24_MASK (0x1000000U)
15586#define DMA_INT_INT24_SHIFT (24U)
15591#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
15592
15593#define DMA_INT_INT25_MASK (0x2000000U)
15594#define DMA_INT_INT25_SHIFT (25U)
15599#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
15600
15601#define DMA_INT_INT26_MASK (0x4000000U)
15602#define DMA_INT_INT26_SHIFT (26U)
15607#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
15608
15609#define DMA_INT_INT27_MASK (0x8000000U)
15610#define DMA_INT_INT27_SHIFT (27U)
15615#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
15616
15617#define DMA_INT_INT28_MASK (0x10000000U)
15618#define DMA_INT_INT28_SHIFT (28U)
15623#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
15624
15625#define DMA_INT_INT29_MASK (0x20000000U)
15626#define DMA_INT_INT29_SHIFT (29U)
15631#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
15632
15633#define DMA_INT_INT30_MASK (0x40000000U)
15634#define DMA_INT_INT30_SHIFT (30U)
15639#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
15640
15641#define DMA_INT_INT31_MASK (0x80000000U)
15642#define DMA_INT_INT31_SHIFT (31U)
15647#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
15653#define DMA_ERR_ERR0_MASK (0x1U)
15654#define DMA_ERR_ERR0_SHIFT (0U)
15659#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
15660
15661#define DMA_ERR_ERR1_MASK (0x2U)
15662#define DMA_ERR_ERR1_SHIFT (1U)
15667#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
15668
15669#define DMA_ERR_ERR2_MASK (0x4U)
15670#define DMA_ERR_ERR2_SHIFT (2U)
15675#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
15676
15677#define DMA_ERR_ERR3_MASK (0x8U)
15678#define DMA_ERR_ERR3_SHIFT (3U)
15683#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
15684
15685#define DMA_ERR_ERR4_MASK (0x10U)
15686#define DMA_ERR_ERR4_SHIFT (4U)
15691#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
15692
15693#define DMA_ERR_ERR5_MASK (0x20U)
15694#define DMA_ERR_ERR5_SHIFT (5U)
15699#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
15700
15701#define DMA_ERR_ERR6_MASK (0x40U)
15702#define DMA_ERR_ERR6_SHIFT (6U)
15707#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
15708
15709#define DMA_ERR_ERR7_MASK (0x80U)
15710#define DMA_ERR_ERR7_SHIFT (7U)
15715#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
15716
15717#define DMA_ERR_ERR8_MASK (0x100U)
15718#define DMA_ERR_ERR8_SHIFT (8U)
15723#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
15724
15725#define DMA_ERR_ERR9_MASK (0x200U)
15726#define DMA_ERR_ERR9_SHIFT (9U)
15731#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
15732
15733#define DMA_ERR_ERR10_MASK (0x400U)
15734#define DMA_ERR_ERR10_SHIFT (10U)
15739#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
15740
15741#define DMA_ERR_ERR11_MASK (0x800U)
15742#define DMA_ERR_ERR11_SHIFT (11U)
15747#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
15748
15749#define DMA_ERR_ERR12_MASK (0x1000U)
15750#define DMA_ERR_ERR12_SHIFT (12U)
15755#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
15756
15757#define DMA_ERR_ERR13_MASK (0x2000U)
15758#define DMA_ERR_ERR13_SHIFT (13U)
15763#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
15764
15765#define DMA_ERR_ERR14_MASK (0x4000U)
15766#define DMA_ERR_ERR14_SHIFT (14U)
15771#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
15772
15773#define DMA_ERR_ERR15_MASK (0x8000U)
15774#define DMA_ERR_ERR15_SHIFT (15U)
15779#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
15780
15781#define DMA_ERR_ERR16_MASK (0x10000U)
15782#define DMA_ERR_ERR16_SHIFT (16U)
15787#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
15788
15789#define DMA_ERR_ERR17_MASK (0x20000U)
15790#define DMA_ERR_ERR17_SHIFT (17U)
15795#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
15796
15797#define DMA_ERR_ERR18_MASK (0x40000U)
15798#define DMA_ERR_ERR18_SHIFT (18U)
15803#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
15804
15805#define DMA_ERR_ERR19_MASK (0x80000U)
15806#define DMA_ERR_ERR19_SHIFT (19U)
15811#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
15812
15813#define DMA_ERR_ERR20_MASK (0x100000U)
15814#define DMA_ERR_ERR20_SHIFT (20U)
15819#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
15820
15821#define DMA_ERR_ERR21_MASK (0x200000U)
15822#define DMA_ERR_ERR21_SHIFT (21U)
15827#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
15828
15829#define DMA_ERR_ERR22_MASK (0x400000U)
15830#define DMA_ERR_ERR22_SHIFT (22U)
15835#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
15836
15837#define DMA_ERR_ERR23_MASK (0x800000U)
15838#define DMA_ERR_ERR23_SHIFT (23U)
15843#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
15844
15845#define DMA_ERR_ERR24_MASK (0x1000000U)
15846#define DMA_ERR_ERR24_SHIFT (24U)
15851#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
15852
15853#define DMA_ERR_ERR25_MASK (0x2000000U)
15854#define DMA_ERR_ERR25_SHIFT (25U)
15859#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
15860
15861#define DMA_ERR_ERR26_MASK (0x4000000U)
15862#define DMA_ERR_ERR26_SHIFT (26U)
15867#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
15868
15869#define DMA_ERR_ERR27_MASK (0x8000000U)
15870#define DMA_ERR_ERR27_SHIFT (27U)
15875#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
15876
15877#define DMA_ERR_ERR28_MASK (0x10000000U)
15878#define DMA_ERR_ERR28_SHIFT (28U)
15883#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
15884
15885#define DMA_ERR_ERR29_MASK (0x20000000U)
15886#define DMA_ERR_ERR29_SHIFT (29U)
15891#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
15892
15893#define DMA_ERR_ERR30_MASK (0x40000000U)
15894#define DMA_ERR_ERR30_SHIFT (30U)
15899#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
15900
15901#define DMA_ERR_ERR31_MASK (0x80000000U)
15902#define DMA_ERR_ERR31_SHIFT (31U)
15907#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
15913#define DMA_HRS_HRS0_MASK (0x1U)
15914#define DMA_HRS_HRS0_SHIFT (0U)
15919#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
15920
15921#define DMA_HRS_HRS1_MASK (0x2U)
15922#define DMA_HRS_HRS1_SHIFT (1U)
15927#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
15928
15929#define DMA_HRS_HRS2_MASK (0x4U)
15930#define DMA_HRS_HRS2_SHIFT (2U)
15935#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
15936
15937#define DMA_HRS_HRS3_MASK (0x8U)
15938#define DMA_HRS_HRS3_SHIFT (3U)
15943#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
15944
15945#define DMA_HRS_HRS4_MASK (0x10U)
15946#define DMA_HRS_HRS4_SHIFT (4U)
15951#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
15952
15953#define DMA_HRS_HRS5_MASK (0x20U)
15954#define DMA_HRS_HRS5_SHIFT (5U)
15959#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
15960
15961#define DMA_HRS_HRS6_MASK (0x40U)
15962#define DMA_HRS_HRS6_SHIFT (6U)
15967#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
15968
15969#define DMA_HRS_HRS7_MASK (0x80U)
15970#define DMA_HRS_HRS7_SHIFT (7U)
15975#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
15976
15977#define DMA_HRS_HRS8_MASK (0x100U)
15978#define DMA_HRS_HRS8_SHIFT (8U)
15983#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
15984
15985#define DMA_HRS_HRS9_MASK (0x200U)
15986#define DMA_HRS_HRS9_SHIFT (9U)
15991#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
15992
15993#define DMA_HRS_HRS10_MASK (0x400U)
15994#define DMA_HRS_HRS10_SHIFT (10U)
15999#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
16000
16001#define DMA_HRS_HRS11_MASK (0x800U)
16002#define DMA_HRS_HRS11_SHIFT (11U)
16007#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
16008
16009#define DMA_HRS_HRS12_MASK (0x1000U)
16010#define DMA_HRS_HRS12_SHIFT (12U)
16015#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
16016
16017#define DMA_HRS_HRS13_MASK (0x2000U)
16018#define DMA_HRS_HRS13_SHIFT (13U)
16023#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
16024
16025#define DMA_HRS_HRS14_MASK (0x4000U)
16026#define DMA_HRS_HRS14_SHIFT (14U)
16031#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
16032
16033#define DMA_HRS_HRS15_MASK (0x8000U)
16034#define DMA_HRS_HRS15_SHIFT (15U)
16039#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
16040
16041#define DMA_HRS_HRS16_MASK (0x10000U)
16042#define DMA_HRS_HRS16_SHIFT (16U)
16047#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
16048
16049#define DMA_HRS_HRS17_MASK (0x20000U)
16050#define DMA_HRS_HRS17_SHIFT (17U)
16055#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
16056
16057#define DMA_HRS_HRS18_MASK (0x40000U)
16058#define DMA_HRS_HRS18_SHIFT (18U)
16063#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
16064
16065#define DMA_HRS_HRS19_MASK (0x80000U)
16066#define DMA_HRS_HRS19_SHIFT (19U)
16071#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
16072
16073#define DMA_HRS_HRS20_MASK (0x100000U)
16074#define DMA_HRS_HRS20_SHIFT (20U)
16079#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
16080
16081#define DMA_HRS_HRS21_MASK (0x200000U)
16082#define DMA_HRS_HRS21_SHIFT (21U)
16087#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
16088
16089#define DMA_HRS_HRS22_MASK (0x400000U)
16090#define DMA_HRS_HRS22_SHIFT (22U)
16095#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
16096
16097#define DMA_HRS_HRS23_MASK (0x800000U)
16098#define DMA_HRS_HRS23_SHIFT (23U)
16103#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
16104
16105#define DMA_HRS_HRS24_MASK (0x1000000U)
16106#define DMA_HRS_HRS24_SHIFT (24U)
16111#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
16112
16113#define DMA_HRS_HRS25_MASK (0x2000000U)
16114#define DMA_HRS_HRS25_SHIFT (25U)
16119#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
16120
16121#define DMA_HRS_HRS26_MASK (0x4000000U)
16122#define DMA_HRS_HRS26_SHIFT (26U)
16127#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
16128
16129#define DMA_HRS_HRS27_MASK (0x8000000U)
16130#define DMA_HRS_HRS27_SHIFT (27U)
16135#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
16136
16137#define DMA_HRS_HRS28_MASK (0x10000000U)
16138#define DMA_HRS_HRS28_SHIFT (28U)
16143#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
16144
16145#define DMA_HRS_HRS29_MASK (0x20000000U)
16146#define DMA_HRS_HRS29_SHIFT (29U)
16151#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
16152
16153#define DMA_HRS_HRS30_MASK (0x40000000U)
16154#define DMA_HRS_HRS30_SHIFT (30U)
16159#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
16160
16161#define DMA_HRS_HRS31_MASK (0x80000000U)
16162#define DMA_HRS_HRS31_SHIFT (31U)
16167#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
16173#define DMA_EARS_EDREQ_0_MASK (0x1U)
16174#define DMA_EARS_EDREQ_0_SHIFT (0U)
16179#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
16180
16181#define DMA_EARS_EDREQ_1_MASK (0x2U)
16182#define DMA_EARS_EDREQ_1_SHIFT (1U)
16187#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
16188
16189#define DMA_EARS_EDREQ_2_MASK (0x4U)
16190#define DMA_EARS_EDREQ_2_SHIFT (2U)
16195#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
16196
16197#define DMA_EARS_EDREQ_3_MASK (0x8U)
16198#define DMA_EARS_EDREQ_3_SHIFT (3U)
16203#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
16204
16205#define DMA_EARS_EDREQ_4_MASK (0x10U)
16206#define DMA_EARS_EDREQ_4_SHIFT (4U)
16211#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
16212
16213#define DMA_EARS_EDREQ_5_MASK (0x20U)
16214#define DMA_EARS_EDREQ_5_SHIFT (5U)
16219#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
16220
16221#define DMA_EARS_EDREQ_6_MASK (0x40U)
16222#define DMA_EARS_EDREQ_6_SHIFT (6U)
16227#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
16228
16229#define DMA_EARS_EDREQ_7_MASK (0x80U)
16230#define DMA_EARS_EDREQ_7_SHIFT (7U)
16235#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
16236
16237#define DMA_EARS_EDREQ_8_MASK (0x100U)
16238#define DMA_EARS_EDREQ_8_SHIFT (8U)
16243#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
16244
16245#define DMA_EARS_EDREQ_9_MASK (0x200U)
16246#define DMA_EARS_EDREQ_9_SHIFT (9U)
16251#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
16252
16253#define DMA_EARS_EDREQ_10_MASK (0x400U)
16254#define DMA_EARS_EDREQ_10_SHIFT (10U)
16259#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
16260
16261#define DMA_EARS_EDREQ_11_MASK (0x800U)
16262#define DMA_EARS_EDREQ_11_SHIFT (11U)
16267#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
16268
16269#define DMA_EARS_EDREQ_12_MASK (0x1000U)
16270#define DMA_EARS_EDREQ_12_SHIFT (12U)
16275#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
16276
16277#define DMA_EARS_EDREQ_13_MASK (0x2000U)
16278#define DMA_EARS_EDREQ_13_SHIFT (13U)
16283#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
16284
16285#define DMA_EARS_EDREQ_14_MASK (0x4000U)
16286#define DMA_EARS_EDREQ_14_SHIFT (14U)
16291#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
16292
16293#define DMA_EARS_EDREQ_15_MASK (0x8000U)
16294#define DMA_EARS_EDREQ_15_SHIFT (15U)
16299#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
16300
16301#define DMA_EARS_EDREQ_16_MASK (0x10000U)
16302#define DMA_EARS_EDREQ_16_SHIFT (16U)
16307#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
16308
16309#define DMA_EARS_EDREQ_17_MASK (0x20000U)
16310#define DMA_EARS_EDREQ_17_SHIFT (17U)
16315#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
16316
16317#define DMA_EARS_EDREQ_18_MASK (0x40000U)
16318#define DMA_EARS_EDREQ_18_SHIFT (18U)
16323#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
16324
16325#define DMA_EARS_EDREQ_19_MASK (0x80000U)
16326#define DMA_EARS_EDREQ_19_SHIFT (19U)
16331#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
16332
16333#define DMA_EARS_EDREQ_20_MASK (0x100000U)
16334#define DMA_EARS_EDREQ_20_SHIFT (20U)
16339#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
16340
16341#define DMA_EARS_EDREQ_21_MASK (0x200000U)
16342#define DMA_EARS_EDREQ_21_SHIFT (21U)
16347#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
16348
16349#define DMA_EARS_EDREQ_22_MASK (0x400000U)
16350#define DMA_EARS_EDREQ_22_SHIFT (22U)
16355#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
16356
16357#define DMA_EARS_EDREQ_23_MASK (0x800000U)
16358#define DMA_EARS_EDREQ_23_SHIFT (23U)
16363#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
16364
16365#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
16366#define DMA_EARS_EDREQ_24_SHIFT (24U)
16371#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
16372
16373#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
16374#define DMA_EARS_EDREQ_25_SHIFT (25U)
16379#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
16380
16381#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
16382#define DMA_EARS_EDREQ_26_SHIFT (26U)
16387#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
16388
16389#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
16390#define DMA_EARS_EDREQ_27_SHIFT (27U)
16395#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
16396
16397#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
16398#define DMA_EARS_EDREQ_28_SHIFT (28U)
16403#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
16404
16405#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
16406#define DMA_EARS_EDREQ_29_SHIFT (29U)
16411#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
16412
16413#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
16414#define DMA_EARS_EDREQ_30_SHIFT (30U)
16419#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
16420
16421#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
16422#define DMA_EARS_EDREQ_31_SHIFT (31U)
16427#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
16433#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
16434#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
16437#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
16438
16439#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
16440#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
16443#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
16444
16445#define DMA_DCHPRI3_DPA_MASK (0x40U)
16446#define DMA_DCHPRI3_DPA_SHIFT (6U)
16451#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
16452
16453#define DMA_DCHPRI3_ECP_MASK (0x80U)
16454#define DMA_DCHPRI3_ECP_SHIFT (7U)
16459#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
16465#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
16466#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
16469#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
16470
16471#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
16472#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
16475#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
16476
16477#define DMA_DCHPRI2_DPA_MASK (0x40U)
16478#define DMA_DCHPRI2_DPA_SHIFT (6U)
16483#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
16484
16485#define DMA_DCHPRI2_ECP_MASK (0x80U)
16486#define DMA_DCHPRI2_ECP_SHIFT (7U)
16491#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
16497#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
16498#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
16501#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
16502
16503#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
16504#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
16507#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
16508
16509#define DMA_DCHPRI1_DPA_MASK (0x40U)
16510#define DMA_DCHPRI1_DPA_SHIFT (6U)
16515#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
16516
16517#define DMA_DCHPRI1_ECP_MASK (0x80U)
16518#define DMA_DCHPRI1_ECP_SHIFT (7U)
16523#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
16529#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
16530#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
16533#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
16534
16535#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
16536#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
16539#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
16540
16541#define DMA_DCHPRI0_DPA_MASK (0x40U)
16542#define DMA_DCHPRI0_DPA_SHIFT (6U)
16547#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
16548
16549#define DMA_DCHPRI0_ECP_MASK (0x80U)
16550#define DMA_DCHPRI0_ECP_SHIFT (7U)
16555#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
16561#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
16562#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
16565#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
16566
16567#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
16568#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
16571#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
16572
16573#define DMA_DCHPRI7_DPA_MASK (0x40U)
16574#define DMA_DCHPRI7_DPA_SHIFT (6U)
16579#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
16580
16581#define DMA_DCHPRI7_ECP_MASK (0x80U)
16582#define DMA_DCHPRI7_ECP_SHIFT (7U)
16587#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
16593#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
16594#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
16597#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
16598
16599#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
16600#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
16603#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
16604
16605#define DMA_DCHPRI6_DPA_MASK (0x40U)
16606#define DMA_DCHPRI6_DPA_SHIFT (6U)
16611#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
16612
16613#define DMA_DCHPRI6_ECP_MASK (0x80U)
16614#define DMA_DCHPRI6_ECP_SHIFT (7U)
16619#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
16625#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
16626#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
16629#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
16630
16631#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
16632#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
16635#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
16636
16637#define DMA_DCHPRI5_DPA_MASK (0x40U)
16638#define DMA_DCHPRI5_DPA_SHIFT (6U)
16643#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
16644
16645#define DMA_DCHPRI5_ECP_MASK (0x80U)
16646#define DMA_DCHPRI5_ECP_SHIFT (7U)
16651#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
16657#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
16658#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
16661#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
16662
16663#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
16664#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
16667#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
16668
16669#define DMA_DCHPRI4_DPA_MASK (0x40U)
16670#define DMA_DCHPRI4_DPA_SHIFT (6U)
16675#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
16676
16677#define DMA_DCHPRI4_ECP_MASK (0x80U)
16678#define DMA_DCHPRI4_ECP_SHIFT (7U)
16683#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
16689#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
16690#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
16693#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
16694
16695#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
16696#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
16699#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
16700
16701#define DMA_DCHPRI11_DPA_MASK (0x40U)
16702#define DMA_DCHPRI11_DPA_SHIFT (6U)
16707#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
16708
16709#define DMA_DCHPRI11_ECP_MASK (0x80U)
16710#define DMA_DCHPRI11_ECP_SHIFT (7U)
16715#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
16721#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
16722#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
16725#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
16726
16727#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
16728#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
16731#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
16732
16733#define DMA_DCHPRI10_DPA_MASK (0x40U)
16734#define DMA_DCHPRI10_DPA_SHIFT (6U)
16739#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
16740
16741#define DMA_DCHPRI10_ECP_MASK (0x80U)
16742#define DMA_DCHPRI10_ECP_SHIFT (7U)
16747#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
16753#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
16754#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
16757#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
16758
16759#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
16760#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
16763#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
16764
16765#define DMA_DCHPRI9_DPA_MASK (0x40U)
16766#define DMA_DCHPRI9_DPA_SHIFT (6U)
16771#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
16772
16773#define DMA_DCHPRI9_ECP_MASK (0x80U)
16774#define DMA_DCHPRI9_ECP_SHIFT (7U)
16779#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
16785#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
16786#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
16789#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
16790
16791#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
16792#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
16795#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
16796
16797#define DMA_DCHPRI8_DPA_MASK (0x40U)
16798#define DMA_DCHPRI8_DPA_SHIFT (6U)
16803#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
16804
16805#define DMA_DCHPRI8_ECP_MASK (0x80U)
16806#define DMA_DCHPRI8_ECP_SHIFT (7U)
16811#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
16817#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
16818#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
16821#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
16822
16823#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
16824#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
16827#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
16828
16829#define DMA_DCHPRI15_DPA_MASK (0x40U)
16830#define DMA_DCHPRI15_DPA_SHIFT (6U)
16835#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
16836
16837#define DMA_DCHPRI15_ECP_MASK (0x80U)
16838#define DMA_DCHPRI15_ECP_SHIFT (7U)
16843#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
16849#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
16850#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
16853#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
16854
16855#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
16856#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
16859#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
16860
16861#define DMA_DCHPRI14_DPA_MASK (0x40U)
16862#define DMA_DCHPRI14_DPA_SHIFT (6U)
16867#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
16868
16869#define DMA_DCHPRI14_ECP_MASK (0x80U)
16870#define DMA_DCHPRI14_ECP_SHIFT (7U)
16875#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
16881#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
16882#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
16885#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
16886
16887#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
16888#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
16891#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
16892
16893#define DMA_DCHPRI13_DPA_MASK (0x40U)
16894#define DMA_DCHPRI13_DPA_SHIFT (6U)
16899#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
16900
16901#define DMA_DCHPRI13_ECP_MASK (0x80U)
16902#define DMA_DCHPRI13_ECP_SHIFT (7U)
16907#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
16913#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
16914#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
16917#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
16918
16919#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
16920#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
16923#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
16924
16925#define DMA_DCHPRI12_DPA_MASK (0x40U)
16926#define DMA_DCHPRI12_DPA_SHIFT (6U)
16931#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
16932
16933#define DMA_DCHPRI12_ECP_MASK (0x80U)
16934#define DMA_DCHPRI12_ECP_SHIFT (7U)
16939#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
16945#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
16946#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
16949#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
16950
16951#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
16952#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
16955#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
16956
16957#define DMA_DCHPRI19_DPA_MASK (0x40U)
16958#define DMA_DCHPRI19_DPA_SHIFT (6U)
16963#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
16964
16965#define DMA_DCHPRI19_ECP_MASK (0x80U)
16966#define DMA_DCHPRI19_ECP_SHIFT (7U)
16971#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
16977#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
16978#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
16981#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
16982
16983#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
16984#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
16987#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
16988
16989#define DMA_DCHPRI18_DPA_MASK (0x40U)
16990#define DMA_DCHPRI18_DPA_SHIFT (6U)
16995#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
16996
16997#define DMA_DCHPRI18_ECP_MASK (0x80U)
16998#define DMA_DCHPRI18_ECP_SHIFT (7U)
17003#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
17009#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
17010#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
17013#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
17014
17015#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
17016#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
17019#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
17020
17021#define DMA_DCHPRI17_DPA_MASK (0x40U)
17022#define DMA_DCHPRI17_DPA_SHIFT (6U)
17027#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
17028
17029#define DMA_DCHPRI17_ECP_MASK (0x80U)
17030#define DMA_DCHPRI17_ECP_SHIFT (7U)
17035#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
17041#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
17042#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
17045#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
17046
17047#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
17048#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
17051#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
17052
17053#define DMA_DCHPRI16_DPA_MASK (0x40U)
17054#define DMA_DCHPRI16_DPA_SHIFT (6U)
17059#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
17060
17061#define DMA_DCHPRI16_ECP_MASK (0x80U)
17062#define DMA_DCHPRI16_ECP_SHIFT (7U)
17067#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
17073#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
17074#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
17077#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
17078
17079#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
17080#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
17083#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
17084
17085#define DMA_DCHPRI23_DPA_MASK (0x40U)
17086#define DMA_DCHPRI23_DPA_SHIFT (6U)
17091#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
17092
17093#define DMA_DCHPRI23_ECP_MASK (0x80U)
17094#define DMA_DCHPRI23_ECP_SHIFT (7U)
17099#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
17105#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
17106#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
17109#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
17110
17111#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
17112#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
17115#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
17116
17117#define DMA_DCHPRI22_DPA_MASK (0x40U)
17118#define DMA_DCHPRI22_DPA_SHIFT (6U)
17123#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
17124
17125#define DMA_DCHPRI22_ECP_MASK (0x80U)
17126#define DMA_DCHPRI22_ECP_SHIFT (7U)
17131#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
17137#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
17138#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
17141#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
17142
17143#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
17144#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
17147#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
17148
17149#define DMA_DCHPRI21_DPA_MASK (0x40U)
17150#define DMA_DCHPRI21_DPA_SHIFT (6U)
17155#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
17156
17157#define DMA_DCHPRI21_ECP_MASK (0x80U)
17158#define DMA_DCHPRI21_ECP_SHIFT (7U)
17163#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
17169#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
17170#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
17173#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
17174
17175#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
17176#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
17179#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
17180
17181#define DMA_DCHPRI20_DPA_MASK (0x40U)
17182#define DMA_DCHPRI20_DPA_SHIFT (6U)
17187#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
17188
17189#define DMA_DCHPRI20_ECP_MASK (0x80U)
17190#define DMA_DCHPRI20_ECP_SHIFT (7U)
17195#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
17201#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
17202#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
17205#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
17206
17207#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
17208#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
17211#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
17212
17213#define DMA_DCHPRI27_DPA_MASK (0x40U)
17214#define DMA_DCHPRI27_DPA_SHIFT (6U)
17219#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
17220
17221#define DMA_DCHPRI27_ECP_MASK (0x80U)
17222#define DMA_DCHPRI27_ECP_SHIFT (7U)
17227#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
17233#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
17234#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
17237#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
17238
17239#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
17240#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
17243#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
17244
17245#define DMA_DCHPRI26_DPA_MASK (0x40U)
17246#define DMA_DCHPRI26_DPA_SHIFT (6U)
17251#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
17252
17253#define DMA_DCHPRI26_ECP_MASK (0x80U)
17254#define DMA_DCHPRI26_ECP_SHIFT (7U)
17259#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
17265#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
17266#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
17269#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
17270
17271#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
17272#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
17275#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
17276
17277#define DMA_DCHPRI25_DPA_MASK (0x40U)
17278#define DMA_DCHPRI25_DPA_SHIFT (6U)
17283#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
17284
17285#define DMA_DCHPRI25_ECP_MASK (0x80U)
17286#define DMA_DCHPRI25_ECP_SHIFT (7U)
17291#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
17297#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
17298#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
17301#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
17302
17303#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
17304#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
17307#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
17308
17309#define DMA_DCHPRI24_DPA_MASK (0x40U)
17310#define DMA_DCHPRI24_DPA_SHIFT (6U)
17315#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
17316
17317#define DMA_DCHPRI24_ECP_MASK (0x80U)
17318#define DMA_DCHPRI24_ECP_SHIFT (7U)
17323#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
17329#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
17330#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
17333#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
17334
17335#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
17336#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
17339#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
17340
17341#define DMA_DCHPRI31_DPA_MASK (0x40U)
17342#define DMA_DCHPRI31_DPA_SHIFT (6U)
17347#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
17348
17349#define DMA_DCHPRI31_ECP_MASK (0x80U)
17350#define DMA_DCHPRI31_ECP_SHIFT (7U)
17355#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
17361#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
17362#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
17365#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
17366
17367#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
17368#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
17371#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
17372
17373#define DMA_DCHPRI30_DPA_MASK (0x40U)
17374#define DMA_DCHPRI30_DPA_SHIFT (6U)
17379#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
17380
17381#define DMA_DCHPRI30_ECP_MASK (0x80U)
17382#define DMA_DCHPRI30_ECP_SHIFT (7U)
17387#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
17393#define DMA_DCHPRI29_CHPRI_MASK (0xFU)
17394#define DMA_DCHPRI29_CHPRI_SHIFT (0U)
17397#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
17398
17399#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
17400#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
17403#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
17404
17405#define DMA_DCHPRI29_DPA_MASK (0x40U)
17406#define DMA_DCHPRI29_DPA_SHIFT (6U)
17411#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
17412
17413#define DMA_DCHPRI29_ECP_MASK (0x80U)
17414#define DMA_DCHPRI29_ECP_SHIFT (7U)
17419#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
17425#define DMA_DCHPRI28_CHPRI_MASK (0xFU)
17426#define DMA_DCHPRI28_CHPRI_SHIFT (0U)
17429#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
17430
17431#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
17432#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
17435#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
17436
17437#define DMA_DCHPRI28_DPA_MASK (0x40U)
17438#define DMA_DCHPRI28_DPA_SHIFT (6U)
17443#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
17444
17445#define DMA_DCHPRI28_ECP_MASK (0x80U)
17446#define DMA_DCHPRI28_ECP_SHIFT (7U)
17451#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
17457#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
17458#define DMA_SADDR_SADDR_SHIFT (0U)
17461#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
17464/* The count of DMA_SADDR */
17465#define DMA_SADDR_COUNT (32U)
17466
17470#define DMA_SOFF_SOFF_MASK (0xFFFFU)
17471#define DMA_SOFF_SOFF_SHIFT (0U)
17474#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
17477/* The count of DMA_SOFF */
17478#define DMA_SOFF_COUNT (32U)
17479
17483#define DMA_ATTR_DSIZE_MASK (0x7U)
17484#define DMA_ATTR_DSIZE_SHIFT (0U)
17487#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
17488
17489#define DMA_ATTR_DMOD_MASK (0xF8U)
17490#define DMA_ATTR_DMOD_SHIFT (3U)
17493#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
17494
17495#define DMA_ATTR_SSIZE_MASK (0x700U)
17496#define DMA_ATTR_SSIZE_SHIFT (8U)
17507#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
17508
17509#define DMA_ATTR_SMOD_MASK (0xF800U)
17510#define DMA_ATTR_SMOD_SHIFT (11U)
17515#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
17518/* The count of DMA_ATTR */
17519#define DMA_ATTR_COUNT (32U)
17520
17524#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
17525#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
17528#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
17531/* The count of DMA_NBYTES_MLNO */
17532#define DMA_NBYTES_MLNO_COUNT (32U)
17533
17537#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
17538#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
17541#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
17542
17543#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
17544#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
17549#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
17550
17551#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
17552#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
17557#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
17560/* The count of DMA_NBYTES_MLOFFNO */
17561#define DMA_NBYTES_MLOFFNO_COUNT (32U)
17562
17566#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
17567#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
17570#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
17571
17572#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
17573#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
17577#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
17578
17579#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
17580#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
17585#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
17586
17587#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
17588#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
17593#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
17596/* The count of DMA_NBYTES_MLOFFYES */
17597#define DMA_NBYTES_MLOFFYES_COUNT (32U)
17598
17602#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
17603#define DMA_SLAST_SLAST_SHIFT (0U)
17606#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
17609/* The count of DMA_SLAST */
17610#define DMA_SLAST_COUNT (32U)
17611
17615#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
17616#define DMA_DADDR_DADDR_SHIFT (0U)
17619#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
17622/* The count of DMA_DADDR */
17623#define DMA_DADDR_COUNT (32U)
17624
17628#define DMA_DOFF_DOFF_MASK (0xFFFFU)
17629#define DMA_DOFF_DOFF_SHIFT (0U)
17632#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
17635/* The count of DMA_DOFF */
17636#define DMA_DOFF_COUNT (32U)
17637
17641#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
17642#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
17645#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
17646
17647#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
17648#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
17653#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
17656/* The count of DMA_CITER_ELINKNO */
17657#define DMA_CITER_ELINKNO_COUNT (32U)
17658
17662#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
17663#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
17666#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
17667
17668#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
17669#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
17672#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
17673
17674#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
17675#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
17680#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
17683/* The count of DMA_CITER_ELINKYES */
17684#define DMA_CITER_ELINKYES_COUNT (32U)
17685
17689#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
17690#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
17693#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
17696/* The count of DMA_DLAST_SGA */
17697#define DMA_DLAST_SGA_COUNT (32U)
17698
17702#define DMA_CSR_START_MASK (0x1U)
17703#define DMA_CSR_START_SHIFT (0U)
17708#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
17709
17710#define DMA_CSR_INTMAJOR_MASK (0x2U)
17711#define DMA_CSR_INTMAJOR_SHIFT (1U)
17716#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
17717
17718#define DMA_CSR_INTHALF_MASK (0x4U)
17719#define DMA_CSR_INTHALF_SHIFT (2U)
17724#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
17725
17726#define DMA_CSR_DREQ_MASK (0x8U)
17727#define DMA_CSR_DREQ_SHIFT (3U)
17732#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
17733
17734#define DMA_CSR_ESG_MASK (0x10U)
17735#define DMA_CSR_ESG_SHIFT (4U)
17740#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
17741
17742#define DMA_CSR_MAJORELINK_MASK (0x20U)
17743#define DMA_CSR_MAJORELINK_SHIFT (5U)
17748#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
17749
17750#define DMA_CSR_ACTIVE_MASK (0x40U)
17751#define DMA_CSR_ACTIVE_SHIFT (6U)
17754#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
17755
17756#define DMA_CSR_DONE_MASK (0x80U)
17757#define DMA_CSR_DONE_SHIFT (7U)
17760#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
17761
17762#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
17763#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
17766#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
17767
17768#define DMA_CSR_BWC_MASK (0xC000U)
17769#define DMA_CSR_BWC_SHIFT (14U)
17776#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
17779/* The count of DMA_CSR */
17780#define DMA_CSR_COUNT (32U)
17781
17785#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
17786#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
17789#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
17790
17791#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
17792#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
17797#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
17800/* The count of DMA_BITER_ELINKNO */
17801#define DMA_BITER_ELINKNO_COUNT (32U)
17802
17806#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
17807#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
17810#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
17811
17812#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
17813#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
17816#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
17817
17818#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
17819#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
17824#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
17827/* The count of DMA_BITER_ELINKYES */
17828#define DMA_BITER_ELINKYES_COUNT (32U)
17829
17830 /* end of group DMA_Register_Masks */
17834
17835
17836/* DMA - Peripheral instance base addresses */
17838#define DMA0_BASE (0x400E8000u)
17840#define DMA0 ((DMA_Type *)DMA0_BASE)
17842#define DMA_BASE_ADDRS { DMA0_BASE }
17844#define DMA_BASE_PTRS { DMA0 }
17846#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
17847#define DMA_ERROR_IRQS { DMA_ERROR_IRQn }
17848 /* end of group DMA_Peripheral_Access_Layer */
17852
17853
17854/* ----------------------------------------------------------------------------
17855 -- DMAMUX Peripheral Access Layer
17856 ---------------------------------------------------------------------------- */
17857
17864typedef struct {
17865 __IO uint32_t CHCFG[32];
17866} DMAMUX_Type;
17867
17868/* ----------------------------------------------------------------------------
17869 -- DMAMUX Register Masks
17870 ---------------------------------------------------------------------------- */
17871
17880#define DMAMUX_CHCFG_SOURCE_MASK (0x7FU)
17881#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
17884#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
17885
17886#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
17887#define DMAMUX_CHCFG_A_ON_SHIFT (29U)
17892#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
17893
17894#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
17895#define DMAMUX_CHCFG_TRIG_SHIFT (30U)
17901#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
17902
17903#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
17904#define DMAMUX_CHCFG_ENBL_SHIFT (31U)
17909#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
17912/* The count of DMAMUX_CHCFG */
17913#define DMAMUX_CHCFG_COUNT (32U)
17914
17915 /* end of group DMAMUX_Register_Masks */
17919
17920
17921/* DMAMUX - Peripheral instance base addresses */
17923#define DMAMUX_BASE (0x400EC000u)
17925#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
17927#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
17929#define DMAMUX_BASE_PTRS { DMAMUX }
17930 /* end of group DMAMUX_Peripheral_Access_Layer */
17934
17935
17936/* ----------------------------------------------------------------------------
17937 -- ENC Peripheral Access Layer
17938 ---------------------------------------------------------------------------- */
17939
17946typedef struct {
17947 __IO uint16_t CTRL;
17948 __IO uint16_t FILT;
17949 __IO uint16_t WTR;
17950 __IO uint16_t POSD;
17951 __I uint16_t POSDH;
17952 __IO uint16_t REV;
17953 __I uint16_t REVH;
17954 __IO uint16_t UPOS;
17955 __IO uint16_t LPOS;
17956 __I uint16_t UPOSH;
17957 __I uint16_t LPOSH;
17958 __IO uint16_t UINIT;
17959 __IO uint16_t LINIT;
17960 __I uint16_t IMR;
17961 __IO uint16_t TST;
17962 __IO uint16_t CTRL2;
17963 __IO uint16_t UMOD;
17964 __IO uint16_t LMOD;
17965 __IO uint16_t UCOMP;
17966 __IO uint16_t LCOMP;
17967} ENC_Type;
17968
17969/* ----------------------------------------------------------------------------
17970 -- ENC Register Masks
17971 ---------------------------------------------------------------------------- */
17972
17981#define ENC_CTRL_CMPIE_MASK (0x1U)
17982#define ENC_CTRL_CMPIE_SHIFT (0U)
17987#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
17988
17989#define ENC_CTRL_CMPIRQ_MASK (0x2U)
17990#define ENC_CTRL_CMPIRQ_SHIFT (1U)
17995#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
17996
17997#define ENC_CTRL_WDE_MASK (0x4U)
17998#define ENC_CTRL_WDE_SHIFT (2U)
18003#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
18004
18005#define ENC_CTRL_DIE_MASK (0x8U)
18006#define ENC_CTRL_DIE_SHIFT (3U)
18011#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
18012
18013#define ENC_CTRL_DIRQ_MASK (0x10U)
18014#define ENC_CTRL_DIRQ_SHIFT (4U)
18019#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
18020
18021#define ENC_CTRL_XNE_MASK (0x20U)
18022#define ENC_CTRL_XNE_SHIFT (5U)
18027#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
18028
18029#define ENC_CTRL_XIP_MASK (0x40U)
18030#define ENC_CTRL_XIP_SHIFT (6U)
18035#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
18036
18037#define ENC_CTRL_XIE_MASK (0x80U)
18038#define ENC_CTRL_XIE_SHIFT (7U)
18043#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
18044
18045#define ENC_CTRL_XIRQ_MASK (0x100U)
18046#define ENC_CTRL_XIRQ_SHIFT (8U)
18051#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
18052
18053#define ENC_CTRL_PH1_MASK (0x200U)
18054#define ENC_CTRL_PH1_SHIFT (9U)
18062#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
18063
18064#define ENC_CTRL_REV_MASK (0x400U)
18065#define ENC_CTRL_REV_SHIFT (10U)
18070#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
18071
18072#define ENC_CTRL_SWIP_MASK (0x800U)
18073#define ENC_CTRL_SWIP_SHIFT (11U)
18078#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
18079
18080#define ENC_CTRL_HNE_MASK (0x1000U)
18081#define ENC_CTRL_HNE_SHIFT (12U)
18086#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
18087
18088#define ENC_CTRL_HIP_MASK (0x2000U)
18089#define ENC_CTRL_HIP_SHIFT (13U)
18094#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
18095
18096#define ENC_CTRL_HIE_MASK (0x4000U)
18097#define ENC_CTRL_HIE_SHIFT (14U)
18102#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
18103
18104#define ENC_CTRL_HIRQ_MASK (0x8000U)
18105#define ENC_CTRL_HIRQ_SHIFT (15U)
18110#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
18116#define ENC_FILT_FILT_PER_MASK (0xFFU)
18117#define ENC_FILT_FILT_PER_SHIFT (0U)
18120#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
18121
18122#define ENC_FILT_FILT_CNT_MASK (0x700U)
18123#define ENC_FILT_FILT_CNT_SHIFT (8U)
18126#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
18132#define ENC_WTR_WDOG_MASK (0xFFFFU)
18133#define ENC_WTR_WDOG_SHIFT (0U)
18136#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
18142#define ENC_POSD_POSD_MASK (0xFFFFU)
18143#define ENC_POSD_POSD_SHIFT (0U)
18146#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
18152#define ENC_POSDH_POSDH_MASK (0xFFFFU)
18153#define ENC_POSDH_POSDH_SHIFT (0U)
18156#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
18162#define ENC_REV_REV_MASK (0xFFFFU)
18163#define ENC_REV_REV_SHIFT (0U)
18166#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
18172#define ENC_REVH_REVH_MASK (0xFFFFU)
18173#define ENC_REVH_REVH_SHIFT (0U)
18176#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
18182#define ENC_UPOS_POS_MASK (0xFFFFU)
18183#define ENC_UPOS_POS_SHIFT (0U)
18186#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
18192#define ENC_LPOS_POS_MASK (0xFFFFU)
18193#define ENC_LPOS_POS_SHIFT (0U)
18196#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
18202#define ENC_UPOSH_POSH_MASK (0xFFFFU)
18203#define ENC_UPOSH_POSH_SHIFT (0U)
18206#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
18212#define ENC_LPOSH_POSH_MASK (0xFFFFU)
18213#define ENC_LPOSH_POSH_SHIFT (0U)
18216#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
18222#define ENC_UINIT_INIT_MASK (0xFFFFU)
18223#define ENC_UINIT_INIT_SHIFT (0U)
18226#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
18232#define ENC_LINIT_INIT_MASK (0xFFFFU)
18233#define ENC_LINIT_INIT_SHIFT (0U)
18236#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
18242#define ENC_IMR_HOME_MASK (0x1U)
18243#define ENC_IMR_HOME_SHIFT (0U)
18246#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
18247
18248#define ENC_IMR_INDEX_MASK (0x2U)
18249#define ENC_IMR_INDEX_SHIFT (1U)
18252#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
18253
18254#define ENC_IMR_PHB_MASK (0x4U)
18255#define ENC_IMR_PHB_SHIFT (2U)
18258#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
18259
18260#define ENC_IMR_PHA_MASK (0x8U)
18261#define ENC_IMR_PHA_SHIFT (3U)
18264#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
18265
18266#define ENC_IMR_FHOM_MASK (0x10U)
18267#define ENC_IMR_FHOM_SHIFT (4U)
18270#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
18271
18272#define ENC_IMR_FIND_MASK (0x20U)
18273#define ENC_IMR_FIND_SHIFT (5U)
18276#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
18277
18278#define ENC_IMR_FPHB_MASK (0x40U)
18279#define ENC_IMR_FPHB_SHIFT (6U)
18282#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
18283
18284#define ENC_IMR_FPHA_MASK (0x80U)
18285#define ENC_IMR_FPHA_SHIFT (7U)
18288#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
18294#define ENC_TST_TEST_COUNT_MASK (0xFFU)
18295#define ENC_TST_TEST_COUNT_SHIFT (0U)
18298#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
18299
18300#define ENC_TST_TEST_PERIOD_MASK (0x1F00U)
18301#define ENC_TST_TEST_PERIOD_SHIFT (8U)
18304#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
18305
18306#define ENC_TST_QDN_MASK (0x2000U)
18307#define ENC_TST_QDN_SHIFT (13U)
18312#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
18313
18314#define ENC_TST_TCE_MASK (0x4000U)
18315#define ENC_TST_TCE_SHIFT (14U)
18320#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
18321
18322#define ENC_TST_TEN_MASK (0x8000U)
18323#define ENC_TST_TEN_SHIFT (15U)
18328#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
18334#define ENC_CTRL2_UPDHLD_MASK (0x1U)
18335#define ENC_CTRL2_UPDHLD_SHIFT (0U)
18340#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
18341
18342#define ENC_CTRL2_UPDPOS_MASK (0x2U)
18343#define ENC_CTRL2_UPDPOS_SHIFT (1U)
18348#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
18349
18350#define ENC_CTRL2_MOD_MASK (0x4U)
18351#define ENC_CTRL2_MOD_SHIFT (2U)
18356#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
18357
18358#define ENC_CTRL2_DIR_MASK (0x8U)
18359#define ENC_CTRL2_DIR_SHIFT (3U)
18364#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
18365
18366#define ENC_CTRL2_RUIE_MASK (0x10U)
18367#define ENC_CTRL2_RUIE_SHIFT (4U)
18372#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
18373
18374#define ENC_CTRL2_RUIRQ_MASK (0x20U)
18375#define ENC_CTRL2_RUIRQ_SHIFT (5U)
18380#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
18381
18382#define ENC_CTRL2_ROIE_MASK (0x40U)
18383#define ENC_CTRL2_ROIE_SHIFT (6U)
18388#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
18389
18390#define ENC_CTRL2_ROIRQ_MASK (0x80U)
18391#define ENC_CTRL2_ROIRQ_SHIFT (7U)
18396#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
18397
18398#define ENC_CTRL2_REVMOD_MASK (0x100U)
18399#define ENC_CTRL2_REVMOD_SHIFT (8U)
18404#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
18405
18406#define ENC_CTRL2_OUTCTL_MASK (0x200U)
18407#define ENC_CTRL2_OUTCTL_SHIFT (9U)
18412#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
18418#define ENC_UMOD_MOD_MASK (0xFFFFU)
18419#define ENC_UMOD_MOD_SHIFT (0U)
18422#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
18428#define ENC_LMOD_MOD_MASK (0xFFFFU)
18429#define ENC_LMOD_MOD_SHIFT (0U)
18432#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
18438#define ENC_UCOMP_COMP_MASK (0xFFFFU)
18439#define ENC_UCOMP_COMP_SHIFT (0U)
18442#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
18448#define ENC_LCOMP_COMP_MASK (0xFFFFU)
18449#define ENC_LCOMP_COMP_SHIFT (0U)
18452#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) /* end of group ENC_Register_Masks */
18459
18460
18461/* ENC - Peripheral instance base addresses */
18463#define ENC1_BASE (0x403C8000u)
18465#define ENC1 ((ENC_Type *)ENC1_BASE)
18467#define ENC2_BASE (0x403CC000u)
18469#define ENC2 ((ENC_Type *)ENC2_BASE)
18471#define ENC3_BASE (0x403D0000u)
18473#define ENC3 ((ENC_Type *)ENC3_BASE)
18475#define ENC4_BASE (0x403D4000u)
18477#define ENC4 ((ENC_Type *)ENC4_BASE)
18479#define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
18481#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
18483#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
18484#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
18485#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
18486#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
18487#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
18488 /* end of group ENC_Peripheral_Access_Layer */
18492
18493
18494/* ----------------------------------------------------------------------------
18495 -- ENET Peripheral Access Layer
18496 ---------------------------------------------------------------------------- */
18497
18504typedef struct {
18505 uint8_t RESERVED_0[4];
18506 __IO uint32_t EIR;
18507 __IO uint32_t EIMR;
18508 uint8_t RESERVED_1[4];
18509 __IO uint32_t RDAR;
18510 __IO uint32_t TDAR;
18511 uint8_t RESERVED_2[12];
18512 __IO uint32_t ECR;
18513 uint8_t RESERVED_3[24];
18514 __IO uint32_t MMFR;
18515 __IO uint32_t MSCR;
18516 uint8_t RESERVED_4[28];
18517 __IO uint32_t MIBC;
18518 uint8_t RESERVED_5[28];
18519 __IO uint32_t RCR;
18520 uint8_t RESERVED_6[60];
18521 __IO uint32_t TCR;
18522 uint8_t RESERVED_7[28];
18523 __IO uint32_t PALR;
18524 __IO uint32_t PAUR;
18525 __IO uint32_t OPD;
18526 __IO uint32_t TXIC[1];
18527 uint8_t RESERVED_8[12];
18528 __IO uint32_t RXIC[1];
18529 uint8_t RESERVED_9[20];
18530 __IO uint32_t IAUR;
18531 __IO uint32_t IALR;
18532 __IO uint32_t GAUR;
18533 __IO uint32_t GALR;
18534 uint8_t RESERVED_10[28];
18535 __IO uint32_t TFWR;
18536 uint8_t RESERVED_11[56];
18537 __IO uint32_t RDSR;
18538 __IO uint32_t TDSR;
18539 __IO uint32_t MRBR;
18540 uint8_t RESERVED_12[4];
18541 __IO uint32_t RSFL;
18542 __IO uint32_t RSEM;
18543 __IO uint32_t RAEM;
18544 __IO uint32_t RAFL;
18545 __IO uint32_t TSEM;
18546 __IO uint32_t TAEM;
18547 __IO uint32_t TAFL;
18548 __IO uint32_t TIPG;
18549 __IO uint32_t FTRL;
18550 uint8_t RESERVED_13[12];
18551 __IO uint32_t TACC;
18552 __IO uint32_t RACC;
18553 uint8_t RESERVED_14[60];
18554 __I uint32_t RMON_T_PACKETS;
18555 __I uint32_t RMON_T_BC_PKT;
18556 __I uint32_t RMON_T_MC_PKT;
18557 __I uint32_t RMON_T_CRC_ALIGN;
18558 __I uint32_t RMON_T_UNDERSIZE;
18559 __I uint32_t RMON_T_OVERSIZE;
18560 __I uint32_t RMON_T_FRAG;
18561 __I uint32_t RMON_T_JAB;
18562 __I uint32_t RMON_T_COL;
18563 __I uint32_t RMON_T_P64;
18564 __I uint32_t RMON_T_P65TO127;
18565 __I uint32_t RMON_T_P128TO255;
18566 __I uint32_t RMON_T_P256TO511;
18567 __I uint32_t RMON_T_P512TO1023;
18568 __I uint32_t RMON_T_P1024TO2047;
18569 __I uint32_t RMON_T_P_GTE2048;
18570 __I uint32_t RMON_T_OCTETS;
18571 uint8_t RESERVED_15[4];
18572 __I uint32_t IEEE_T_FRAME_OK;
18573 __I uint32_t IEEE_T_1COL;
18574 __I uint32_t IEEE_T_MCOL;
18575 __I uint32_t IEEE_T_DEF;
18576 __I uint32_t IEEE_T_LCOL;
18577 __I uint32_t IEEE_T_EXCOL;
18578 __I uint32_t IEEE_T_MACERR;
18579 __I uint32_t IEEE_T_CSERR;
18580 __I uint32_t IEEE_T_SQE;
18581 __I uint32_t IEEE_T_FDXFC;
18582 __I uint32_t IEEE_T_OCTETS_OK;
18583 uint8_t RESERVED_16[12];
18584 __I uint32_t RMON_R_PACKETS;
18585 __I uint32_t RMON_R_BC_PKT;
18586 __I uint32_t RMON_R_MC_PKT;
18587 __I uint32_t RMON_R_CRC_ALIGN;
18588 __I uint32_t RMON_R_UNDERSIZE;
18589 __I uint32_t RMON_R_OVERSIZE;
18590 __I uint32_t RMON_R_FRAG;
18591 __I uint32_t RMON_R_JAB;
18592 uint8_t RESERVED_17[4];
18593 __I uint32_t RMON_R_P64;
18594 __I uint32_t RMON_R_P65TO127;
18595 __I uint32_t RMON_R_P128TO255;
18596 __I uint32_t RMON_R_P256TO511;
18597 __I uint32_t RMON_R_P512TO1023;
18598 __I uint32_t RMON_R_P1024TO2047;
18599 __I uint32_t RMON_R_P_GTE2048;
18600 __I uint32_t RMON_R_OCTETS;
18601 __I uint32_t IEEE_R_DROP;
18602 __I uint32_t IEEE_R_FRAME_OK;
18603 __I uint32_t IEEE_R_CRC;
18604 __I uint32_t IEEE_R_ALIGN;
18605 __I uint32_t IEEE_R_MACERR;
18606 __I uint32_t IEEE_R_FDXFC;
18607 __I uint32_t IEEE_R_OCTETS_OK;
18608 uint8_t RESERVED_18[284];
18609 __IO uint32_t ATCR;
18610 __IO uint32_t ATVR;
18611 __IO uint32_t ATOFF;
18612 __IO uint32_t ATPER;
18613 __IO uint32_t ATCOR;
18614 __IO uint32_t ATINC;
18615 __I uint32_t ATSTMP;
18616 uint8_t RESERVED_19[488];
18617 __IO uint32_t TGSR;
18618 struct { /* offset: 0x608, array step: 0x8 */
18619 __IO uint32_t TCSR;
18620 __IO uint32_t TCCR;
18621 } CHANNEL[4];
18622} ENET_Type;
18623
18624/* ----------------------------------------------------------------------------
18625 -- ENET Register Masks
18626 ---------------------------------------------------------------------------- */
18627
18636#define ENET_EIR_TS_TIMER_MASK (0x8000U)
18637#define ENET_EIR_TS_TIMER_SHIFT (15U)
18640#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
18641
18642#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
18643#define ENET_EIR_TS_AVAIL_SHIFT (16U)
18646#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
18647
18648#define ENET_EIR_WAKEUP_MASK (0x20000U)
18649#define ENET_EIR_WAKEUP_SHIFT (17U)
18652#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
18653
18654#define ENET_EIR_PLR_MASK (0x40000U)
18655#define ENET_EIR_PLR_SHIFT (18U)
18658#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
18659
18660#define ENET_EIR_UN_MASK (0x80000U)
18661#define ENET_EIR_UN_SHIFT (19U)
18664#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
18665
18666#define ENET_EIR_RL_MASK (0x100000U)
18667#define ENET_EIR_RL_SHIFT (20U)
18670#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
18671
18672#define ENET_EIR_LC_MASK (0x200000U)
18673#define ENET_EIR_LC_SHIFT (21U)
18676#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
18677
18678#define ENET_EIR_EBERR_MASK (0x400000U)
18679#define ENET_EIR_EBERR_SHIFT (22U)
18682#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
18683
18684#define ENET_EIR_MII_MASK (0x800000U)
18685#define ENET_EIR_MII_SHIFT (23U)
18688#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
18689
18690#define ENET_EIR_RXB_MASK (0x1000000U)
18691#define ENET_EIR_RXB_SHIFT (24U)
18694#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
18695
18696#define ENET_EIR_RXF_MASK (0x2000000U)
18697#define ENET_EIR_RXF_SHIFT (25U)
18700#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
18701
18702#define ENET_EIR_TXB_MASK (0x4000000U)
18703#define ENET_EIR_TXB_SHIFT (26U)
18706#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
18707
18708#define ENET_EIR_TXF_MASK (0x8000000U)
18709#define ENET_EIR_TXF_SHIFT (27U)
18712#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
18713
18714#define ENET_EIR_GRA_MASK (0x10000000U)
18715#define ENET_EIR_GRA_SHIFT (28U)
18718#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
18719
18720#define ENET_EIR_BABT_MASK (0x20000000U)
18721#define ENET_EIR_BABT_SHIFT (29U)
18724#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
18725
18726#define ENET_EIR_BABR_MASK (0x40000000U)
18727#define ENET_EIR_BABR_SHIFT (30U)
18730#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
18736#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
18737#define ENET_EIMR_TS_TIMER_SHIFT (15U)
18742#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
18743
18744#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
18745#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
18750#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
18751
18752#define ENET_EIMR_WAKEUP_MASK (0x20000U)
18753#define ENET_EIMR_WAKEUP_SHIFT (17U)
18758#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
18759
18760#define ENET_EIMR_PLR_MASK (0x40000U)
18761#define ENET_EIMR_PLR_SHIFT (18U)
18766#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
18767
18768#define ENET_EIMR_UN_MASK (0x80000U)
18769#define ENET_EIMR_UN_SHIFT (19U)
18774#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
18775
18776#define ENET_EIMR_RL_MASK (0x100000U)
18777#define ENET_EIMR_RL_SHIFT (20U)
18782#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
18783
18784#define ENET_EIMR_LC_MASK (0x200000U)
18785#define ENET_EIMR_LC_SHIFT (21U)
18790#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
18791
18792#define ENET_EIMR_EBERR_MASK (0x400000U)
18793#define ENET_EIMR_EBERR_SHIFT (22U)
18798#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
18799
18800#define ENET_EIMR_MII_MASK (0x800000U)
18801#define ENET_EIMR_MII_SHIFT (23U)
18806#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
18807
18808#define ENET_EIMR_RXB_MASK (0x1000000U)
18809#define ENET_EIMR_RXB_SHIFT (24U)
18814#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
18815
18816#define ENET_EIMR_RXF_MASK (0x2000000U)
18817#define ENET_EIMR_RXF_SHIFT (25U)
18822#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
18823
18824#define ENET_EIMR_TXB_MASK (0x4000000U)
18825#define ENET_EIMR_TXB_SHIFT (26U)
18830#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
18831
18832#define ENET_EIMR_TXF_MASK (0x8000000U)
18833#define ENET_EIMR_TXF_SHIFT (27U)
18838#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
18839
18840#define ENET_EIMR_GRA_MASK (0x10000000U)
18841#define ENET_EIMR_GRA_SHIFT (28U)
18846#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
18847
18848#define ENET_EIMR_BABT_MASK (0x20000000U)
18849#define ENET_EIMR_BABT_SHIFT (29U)
18854#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
18855
18856#define ENET_EIMR_BABR_MASK (0x40000000U)
18857#define ENET_EIMR_BABR_SHIFT (30U)
18862#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
18868#define ENET_RDAR_RDAR_MASK (0x1000000U)
18869#define ENET_RDAR_RDAR_SHIFT (24U)
18872#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
18878#define ENET_TDAR_TDAR_MASK (0x1000000U)
18879#define ENET_TDAR_TDAR_SHIFT (24U)
18882#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
18888#define ENET_ECR_RESET_MASK (0x1U)
18889#define ENET_ECR_RESET_SHIFT (0U)
18892#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
18893
18894#define ENET_ECR_ETHEREN_MASK (0x2U)
18895#define ENET_ECR_ETHEREN_SHIFT (1U)
18900#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
18901
18902#define ENET_ECR_MAGICEN_MASK (0x4U)
18903#define ENET_ECR_MAGICEN_SHIFT (2U)
18908#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
18909
18910#define ENET_ECR_SLEEP_MASK (0x8U)
18911#define ENET_ECR_SLEEP_SHIFT (3U)
18916#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
18917
18918#define ENET_ECR_EN1588_MASK (0x10U)
18919#define ENET_ECR_EN1588_SHIFT (4U)
18924#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
18925
18926#define ENET_ECR_DBGEN_MASK (0x40U)
18927#define ENET_ECR_DBGEN_SHIFT (6U)
18932#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
18933
18934#define ENET_ECR_DBSWP_MASK (0x100U)
18935#define ENET_ECR_DBSWP_SHIFT (8U)
18940#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
18946#define ENET_MMFR_DATA_MASK (0xFFFFU)
18947#define ENET_MMFR_DATA_SHIFT (0U)
18950#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
18951
18952#define ENET_MMFR_TA_MASK (0x30000U)
18953#define ENET_MMFR_TA_SHIFT (16U)
18956#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
18957
18958#define ENET_MMFR_RA_MASK (0x7C0000U)
18959#define ENET_MMFR_RA_SHIFT (18U)
18962#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
18963
18964#define ENET_MMFR_PA_MASK (0xF800000U)
18965#define ENET_MMFR_PA_SHIFT (23U)
18968#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
18969
18970#define ENET_MMFR_OP_MASK (0x30000000U)
18971#define ENET_MMFR_OP_SHIFT (28U)
18974#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
18975
18976#define ENET_MMFR_ST_MASK (0xC0000000U)
18977#define ENET_MMFR_ST_SHIFT (30U)
18980#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
18986#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
18987#define ENET_MSCR_MII_SPEED_SHIFT (1U)
18990#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
18991
18992#define ENET_MSCR_DIS_PRE_MASK (0x80U)
18993#define ENET_MSCR_DIS_PRE_SHIFT (7U)
18998#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
18999
19000#define ENET_MSCR_HOLDTIME_MASK (0x700U)
19001#define ENET_MSCR_HOLDTIME_SHIFT (8U)
19008#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
19014#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
19015#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
19020#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
19021
19022#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
19023#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
19028#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
19029
19030#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
19031#define ENET_MIBC_MIB_DIS_SHIFT (31U)
19036#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
19042#define ENET_RCR_LOOP_MASK (0x1U)
19043#define ENET_RCR_LOOP_SHIFT (0U)
19048#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
19049
19050#define ENET_RCR_DRT_MASK (0x2U)
19051#define ENET_RCR_DRT_SHIFT (1U)
19056#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
19057
19058#define ENET_RCR_MII_MODE_MASK (0x4U)
19059#define ENET_RCR_MII_MODE_SHIFT (2U)
19064#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
19065
19066#define ENET_RCR_PROM_MASK (0x8U)
19067#define ENET_RCR_PROM_SHIFT (3U)
19072#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
19073
19074#define ENET_RCR_BC_REJ_MASK (0x10U)
19075#define ENET_RCR_BC_REJ_SHIFT (4U)
19080#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
19081
19082#define ENET_RCR_FCE_MASK (0x20U)
19083#define ENET_RCR_FCE_SHIFT (5U)
19088#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
19089
19090#define ENET_RCR_RMII_MODE_MASK (0x100U)
19091#define ENET_RCR_RMII_MODE_SHIFT (8U)
19096#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
19097
19098#define ENET_RCR_RMII_10T_MASK (0x200U)
19099#define ENET_RCR_RMII_10T_SHIFT (9U)
19104#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
19105
19106#define ENET_RCR_PADEN_MASK (0x1000U)
19107#define ENET_RCR_PADEN_SHIFT (12U)
19112#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
19113
19114#define ENET_RCR_PAUFWD_MASK (0x2000U)
19115#define ENET_RCR_PAUFWD_SHIFT (13U)
19120#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
19121
19122#define ENET_RCR_CRCFWD_MASK (0x4000U)
19123#define ENET_RCR_CRCFWD_SHIFT (14U)
19128#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
19129
19130#define ENET_RCR_CFEN_MASK (0x8000U)
19131#define ENET_RCR_CFEN_SHIFT (15U)
19136#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
19137
19138#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
19139#define ENET_RCR_MAX_FL_SHIFT (16U)
19142#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
19143
19144#define ENET_RCR_NLC_MASK (0x40000000U)
19145#define ENET_RCR_NLC_SHIFT (30U)
19150#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
19151
19152#define ENET_RCR_GRS_MASK (0x80000000U)
19153#define ENET_RCR_GRS_SHIFT (31U)
19158#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
19164#define ENET_TCR_GTS_MASK (0x1U)
19165#define ENET_TCR_GTS_SHIFT (0U)
19170#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
19171
19172#define ENET_TCR_FDEN_MASK (0x4U)
19173#define ENET_TCR_FDEN_SHIFT (2U)
19178#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
19179
19180#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
19181#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
19186#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
19187
19188#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
19189#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
19192#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
19193
19194#define ENET_TCR_ADDSEL_MASK (0xE0U)
19195#define ENET_TCR_ADDSEL_SHIFT (5U)
19202#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
19203
19204#define ENET_TCR_ADDINS_MASK (0x100U)
19205#define ENET_TCR_ADDINS_SHIFT (8U)
19210#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
19211
19212#define ENET_TCR_CRCFWD_MASK (0x200U)
19213#define ENET_TCR_CRCFWD_SHIFT (9U)
19218#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
19224#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
19225#define ENET_PALR_PADDR1_SHIFT (0U)
19228#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
19234#define ENET_PAUR_TYPE_MASK (0xFFFFU)
19235#define ENET_PAUR_TYPE_SHIFT (0U)
19238#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
19239
19240#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
19241#define ENET_PAUR_PADDR2_SHIFT (16U)
19242#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
19248#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
19249#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
19252#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
19253
19254#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
19255#define ENET_OPD_OPCODE_SHIFT (16U)
19258#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
19264#define ENET_TXIC_ICTT_MASK (0xFFFFU)
19265#define ENET_TXIC_ICTT_SHIFT (0U)
19268#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
19269
19270#define ENET_TXIC_ICFT_MASK (0xFF00000U)
19271#define ENET_TXIC_ICFT_SHIFT (20U)
19274#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
19275
19276#define ENET_TXIC_ICCS_MASK (0x40000000U)
19277#define ENET_TXIC_ICCS_SHIFT (30U)
19282#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
19283
19284#define ENET_TXIC_ICEN_MASK (0x80000000U)
19285#define ENET_TXIC_ICEN_SHIFT (31U)
19290#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
19293/* The count of ENET_TXIC */
19294#define ENET_TXIC_COUNT (1U)
19295
19299#define ENET_RXIC_ICTT_MASK (0xFFFFU)
19300#define ENET_RXIC_ICTT_SHIFT (0U)
19303#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
19304
19305#define ENET_RXIC_ICFT_MASK (0xFF00000U)
19306#define ENET_RXIC_ICFT_SHIFT (20U)
19309#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
19310
19311#define ENET_RXIC_ICCS_MASK (0x40000000U)
19312#define ENET_RXIC_ICCS_SHIFT (30U)
19317#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
19318
19319#define ENET_RXIC_ICEN_MASK (0x80000000U)
19320#define ENET_RXIC_ICEN_SHIFT (31U)
19325#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
19328/* The count of ENET_RXIC */
19329#define ENET_RXIC_COUNT (1U)
19330
19334#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
19335#define ENET_IAUR_IADDR1_SHIFT (0U)
19336#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
19342#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
19343#define ENET_IALR_IADDR2_SHIFT (0U)
19344#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
19350#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
19351#define ENET_GAUR_GADDR1_SHIFT (0U)
19352#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
19358#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
19359#define ENET_GALR_GADDR2_SHIFT (0U)
19360#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
19366#define ENET_TFWR_TFWR_MASK (0x3FU)
19367#define ENET_TFWR_TFWR_SHIFT (0U)
19375#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
19376
19377#define ENET_TFWR_STRFWD_MASK (0x100U)
19378#define ENET_TFWR_STRFWD_SHIFT (8U)
19383#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
19389#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
19390#define ENET_RDSR_R_DES_START_SHIFT (3U)
19391#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
19397#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
19398#define ENET_TDSR_X_DES_START_SHIFT (3U)
19399#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
19405#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
19406#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
19407#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
19413#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
19414#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
19417#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
19423#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
19424#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
19427#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
19428
19429#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
19430#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
19433#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
19439#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
19440#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
19443#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
19449#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
19450#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
19453#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
19459#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
19460#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
19463#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
19469#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
19470#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
19473#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
19479#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
19480#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
19483#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
19489#define ENET_TIPG_IPG_MASK (0x1FU)
19490#define ENET_TIPG_IPG_SHIFT (0U)
19493#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
19499#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
19500#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
19503#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
19509#define ENET_TACC_SHIFT16_MASK (0x1U)
19510#define ENET_TACC_SHIFT16_SHIFT (0U)
19518#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
19519
19520#define ENET_TACC_IPCHK_MASK (0x8U)
19521#define ENET_TACC_IPCHK_SHIFT (3U)
19527#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
19528
19529#define ENET_TACC_PROCHK_MASK (0x10U)
19530#define ENET_TACC_PROCHK_SHIFT (4U)
19536#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
19542#define ENET_RACC_PADREM_MASK (0x1U)
19543#define ENET_RACC_PADREM_SHIFT (0U)
19548#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
19549
19550#define ENET_RACC_IPDIS_MASK (0x2U)
19551#define ENET_RACC_IPDIS_SHIFT (1U)
19558#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
19559
19560#define ENET_RACC_PRODIS_MASK (0x4U)
19561#define ENET_RACC_PRODIS_SHIFT (2U)
19568#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
19569
19570#define ENET_RACC_LINEDIS_MASK (0x40U)
19571#define ENET_RACC_LINEDIS_SHIFT (6U)
19576#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
19577
19578#define ENET_RACC_SHIFT16_MASK (0x80U)
19579#define ENET_RACC_SHIFT16_SHIFT (7U)
19584#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
19590#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
19591#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
19594#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
19600#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
19601#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
19604#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
19610#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
19611#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
19614#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
19620#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
19621#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
19624#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
19630#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
19631#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
19634#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
19640#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
19641#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
19644#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
19650#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
19651#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
19654#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
19660#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
19661#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
19664#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
19670#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
19671#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
19674#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
19680#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
19681#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
19684#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
19690#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
19691#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
19694#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
19700#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
19701#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
19704#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
19710#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
19711#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
19714#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
19720#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
19721#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
19724#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
19730#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
19731#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
19734#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
19740#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
19741#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
19744#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
19750#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
19751#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
19754#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
19760#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
19761#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
19764#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
19770#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
19771#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
19774#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
19780#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
19781#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
19784#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
19790#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
19791#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
19794#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
19800#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
19801#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
19804#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
19810#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
19811#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
19814#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
19820#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
19821#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
19824#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
19830#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
19831#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
19834#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
19840#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
19841#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
19844#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
19850#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
19851#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
19854#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
19860#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
19861#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
19864#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
19870#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
19871#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
19874#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
19880#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
19881#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
19884#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
19890#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
19891#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
19894#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
19900#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
19901#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
19904#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
19910#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
19911#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
19914#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
19920#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
19921#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
19924#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
19930#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
19931#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
19934#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
19940#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
19941#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
19944#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
19950#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
19951#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
19954#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
19960#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
19961#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
19964#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
19970#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
19971#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
19974#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
19980#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
19981#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
19984#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
19990#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
19991#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
19994#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
20000#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
20001#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
20004#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
20010#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
20011#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
20014#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
20020#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
20021#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
20024#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
20030#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
20031#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
20034#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
20040#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
20041#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
20044#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
20050#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
20051#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
20054#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
20060#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
20061#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
20064#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
20070#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
20071#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
20074#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
20080#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
20081#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
20084#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
20090#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
20091#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
20094#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
20100#define ENET_ATCR_EN_MASK (0x1U)
20101#define ENET_ATCR_EN_SHIFT (0U)
20106#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
20107
20108#define ENET_ATCR_OFFEN_MASK (0x4U)
20109#define ENET_ATCR_OFFEN_SHIFT (2U)
20116#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
20117
20118#define ENET_ATCR_OFFRST_MASK (0x8U)
20119#define ENET_ATCR_OFFRST_SHIFT (3U)
20124#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
20125
20126#define ENET_ATCR_PEREN_MASK (0x10U)
20127#define ENET_ATCR_PEREN_SHIFT (4U)
20134#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
20135
20136#define ENET_ATCR_PINPER_MASK (0x80U)
20137#define ENET_ATCR_PINPER_SHIFT (7U)
20142#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
20143
20144#define ENET_ATCR_RESTART_MASK (0x200U)
20145#define ENET_ATCR_RESTART_SHIFT (9U)
20148#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
20149
20150#define ENET_ATCR_CAPTURE_MASK (0x800U)
20151#define ENET_ATCR_CAPTURE_SHIFT (11U)
20156#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
20157
20158#define ENET_ATCR_SLAVE_MASK (0x2000U)
20159#define ENET_ATCR_SLAVE_SHIFT (13U)
20165#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
20171#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
20172#define ENET_ATVR_ATIME_SHIFT (0U)
20173#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
20179#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
20180#define ENET_ATOFF_OFFSET_SHIFT (0U)
20181#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
20187#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
20188#define ENET_ATPER_PERIOD_SHIFT (0U)
20191#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
20197#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
20198#define ENET_ATCOR_COR_SHIFT (0U)
20201#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
20207#define ENET_ATINC_INC_MASK (0x7FU)
20208#define ENET_ATINC_INC_SHIFT (0U)
20211#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
20212
20213#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
20214#define ENET_ATINC_INC_CORR_SHIFT (8U)
20217#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
20223#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
20224#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
20228#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
20234#define ENET_TGSR_TF0_MASK (0x1U)
20235#define ENET_TGSR_TF0_SHIFT (0U)
20240#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
20241
20242#define ENET_TGSR_TF1_MASK (0x2U)
20243#define ENET_TGSR_TF1_SHIFT (1U)
20248#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
20249
20250#define ENET_TGSR_TF2_MASK (0x4U)
20251#define ENET_TGSR_TF2_SHIFT (2U)
20256#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
20257
20258#define ENET_TGSR_TF3_MASK (0x8U)
20259#define ENET_TGSR_TF3_SHIFT (3U)
20264#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
20270#define ENET_TCSR_TDRE_MASK (0x1U)
20271#define ENET_TCSR_TDRE_SHIFT (0U)
20276#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
20277
20278#define ENET_TCSR_TMODE_MASK (0x3CU)
20279#define ENET_TCSR_TMODE_SHIFT (2U)
20296#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
20297
20298#define ENET_TCSR_TIE_MASK (0x40U)
20299#define ENET_TCSR_TIE_SHIFT (6U)
20304#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
20305
20306#define ENET_TCSR_TF_MASK (0x80U)
20307#define ENET_TCSR_TF_SHIFT (7U)
20312#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
20313
20314#define ENET_TCSR_TPWC_MASK (0xF800U)
20315#define ENET_TCSR_TPWC_SHIFT (11U)
20323#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
20326/* The count of ENET_TCSR */
20327#define ENET_TCSR_COUNT (4U)
20328
20332#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
20333#define ENET_TCCR_TCC_SHIFT (0U)
20336#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
20339/* The count of ENET_TCCR */
20340#define ENET_TCCR_COUNT (4U)
20341
20342 /* end of group ENET_Register_Masks */
20346
20347
20348/* ENET - Peripheral instance base addresses */
20350#define ENET_BASE (0x402D8000u)
20352#define ENET ((ENET_Type *)ENET_BASE)
20354#define ENET_BASE_ADDRS { ENET_BASE }
20356#define ENET_BASE_PTRS { ENET }
20358#define ENET_Transmit_IRQS { ENET_IRQn }
20359#define ENET_Receive_IRQS { ENET_IRQn }
20360#define ENET_Error_IRQS { ENET_IRQn }
20361#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
20362#define ENET_Ts_IRQS { ENET_IRQn }
20363/* ENET Buffer Descriptor and Buffer Address Alignment. */
20364#define ENET_BUFF_ALIGNMENT (64U)
20365
20366 /* end of group ENET_Peripheral_Access_Layer */
20370
20371
20372/* ----------------------------------------------------------------------------
20373 -- EWM Peripheral Access Layer
20374 ---------------------------------------------------------------------------- */
20375
20382typedef struct {
20383 __IO uint8_t CTRL;
20384 __O uint8_t SERV;
20385 __IO uint8_t CMPL;
20386 __IO uint8_t CMPH;
20387 __IO uint8_t CLKCTRL;
20388 __IO uint8_t CLKPRESCALER;
20389} EWM_Type;
20390
20391/* ----------------------------------------------------------------------------
20392 -- EWM Register Masks
20393 ---------------------------------------------------------------------------- */
20394
20403#define EWM_CTRL_EWMEN_MASK (0x1U)
20404#define EWM_CTRL_EWMEN_SHIFT (0U)
20407#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
20408
20409#define EWM_CTRL_ASSIN_MASK (0x2U)
20410#define EWM_CTRL_ASSIN_SHIFT (1U)
20413#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
20414
20415#define EWM_CTRL_INEN_MASK (0x4U)
20416#define EWM_CTRL_INEN_SHIFT (2U)
20419#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
20420
20421#define EWM_CTRL_INTEN_MASK (0x8U)
20422#define EWM_CTRL_INTEN_SHIFT (3U)
20425#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
20431#define EWM_SERV_SERVICE_MASK (0xFFU)
20432#define EWM_SERV_SERVICE_SHIFT (0U)
20435#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
20441#define EWM_CMPL_COMPAREL_MASK (0xFFU)
20442#define EWM_CMPL_COMPAREL_SHIFT (0U)
20445#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
20451#define EWM_CMPH_COMPAREH_MASK (0xFFU)
20452#define EWM_CMPH_COMPAREH_SHIFT (0U)
20455#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
20461#define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
20462#define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
20465#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
20471#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
20472#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
20475#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) /* end of group EWM_Register_Masks */
20482
20483
20484/* EWM - Peripheral instance base addresses */
20486#define EWM_BASE (0x400B4000u)
20488#define EWM ((EWM_Type *)EWM_BASE)
20490#define EWM_BASE_ADDRS { EWM_BASE }
20492#define EWM_BASE_PTRS { EWM }
20494#define EWM_IRQS { EWM_IRQn }
20495 /* end of group EWM_Peripheral_Access_Layer */
20499
20500
20501/* ----------------------------------------------------------------------------
20502 -- FLEXIO Peripheral Access Layer
20503 ---------------------------------------------------------------------------- */
20504
20511typedef struct {
20512 __I uint32_t VERID;
20513 __I uint32_t PARAM;
20514 __IO uint32_t CTRL;
20515 __I uint32_t PIN;
20516 __IO uint32_t SHIFTSTAT;
20517 __IO uint32_t SHIFTERR;
20518 __IO uint32_t TIMSTAT;
20519 uint8_t RESERVED_0[4];
20520 __IO uint32_t SHIFTSIEN;
20521 __IO uint32_t SHIFTEIEN;
20522 __IO uint32_t TIMIEN;
20523 uint8_t RESERVED_1[4];
20524 __IO uint32_t SHIFTSDEN;
20525 uint8_t RESERVED_2[12];
20526 __IO uint32_t SHIFTSTATE;
20527 uint8_t RESERVED_3[60];
20528 __IO uint32_t SHIFTCTL[4];
20529 uint8_t RESERVED_4[112];
20530 __IO uint32_t SHIFTCFG[4];
20531 uint8_t RESERVED_5[240];
20532 __IO uint32_t SHIFTBUF[4];
20533 uint8_t RESERVED_6[112];
20534 __IO uint32_t SHIFTBUFBIS[4];
20535 uint8_t RESERVED_7[112];
20536 __IO uint32_t SHIFTBUFBYS[4];
20537 uint8_t RESERVED_8[112];
20538 __IO uint32_t SHIFTBUFBBS[4];
20539 uint8_t RESERVED_9[112];
20540 __IO uint32_t TIMCTL[4];
20541 uint8_t RESERVED_10[112];
20542 __IO uint32_t TIMCFG[4];
20543 uint8_t RESERVED_11[112];
20544 __IO uint32_t TIMCMP[4];
20545 uint8_t RESERVED_12[368];
20546 __IO uint32_t SHIFTBUFNBS[4];
20547 uint8_t RESERVED_13[112];
20548 __IO uint32_t SHIFTBUFHWS[4];
20549 uint8_t RESERVED_14[112];
20550 __IO uint32_t SHIFTBUFNIS[4];
20551} FLEXIO_Type;
20552
20553/* ----------------------------------------------------------------------------
20554 -- FLEXIO Register Masks
20555 ---------------------------------------------------------------------------- */
20556
20565#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
20566#define FLEXIO_VERID_FEATURE_SHIFT (0U)
20571#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
20572
20573#define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
20574#define FLEXIO_VERID_MINOR_SHIFT (16U)
20577#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
20578
20579#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
20580#define FLEXIO_VERID_MAJOR_SHIFT (24U)
20583#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
20589#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
20590#define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
20593#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
20594
20595#define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
20596#define FLEXIO_PARAM_TIMER_SHIFT (8U)
20599#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
20600
20601#define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
20602#define FLEXIO_PARAM_PIN_SHIFT (16U)
20605#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
20606
20607#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
20608#define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
20611#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
20617#define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
20618#define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
20623#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
20624
20625#define FLEXIO_CTRL_SWRST_MASK (0x2U)
20626#define FLEXIO_CTRL_SWRST_SHIFT (1U)
20631#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
20632
20633#define FLEXIO_CTRL_FASTACC_MASK (0x4U)
20634#define FLEXIO_CTRL_FASTACC_SHIFT (2U)
20639#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
20640
20641#define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
20642#define FLEXIO_CTRL_DBGE_SHIFT (30U)
20647#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
20648
20649#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
20650#define FLEXIO_CTRL_DOZEN_SHIFT (31U)
20655#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
20661#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
20662#define FLEXIO_PIN_PDI_SHIFT (0U)
20665#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
20671#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU)
20672#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
20675#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
20681#define FLEXIO_SHIFTERR_SEF_MASK (0xFU)
20682#define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
20685#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
20691#define FLEXIO_TIMSTAT_TSF_MASK (0xFU)
20692#define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
20695#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
20701#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)
20702#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
20705#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
20711#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)
20712#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
20715#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
20721#define FLEXIO_TIMIEN_TEIE_MASK (0xFU)
20722#define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
20725#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
20731#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)
20732#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
20735#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
20741#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
20742#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
20745#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
20751#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
20752#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
20763#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
20764
20765#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
20766#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
20771#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
20772
20773#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20774#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
20777#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20778
20779#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
20780#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
20787#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
20788
20789#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
20790#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
20795#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
20796
20797#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)
20798#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
20801#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
20804/* The count of FLEXIO_SHIFTCTL */
20805#define FLEXIO_SHIFTCTL_COUNT (4U)
20806
20810#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
20811#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
20818#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
20819
20820#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
20821#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
20828#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
20829
20830#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
20831#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
20836#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
20837
20838#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20839#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
20842#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20845/* The count of FLEXIO_SHIFTCFG */
20846#define FLEXIO_SHIFTCFG_COUNT (4U)
20847
20851#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
20852#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
20855#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
20858/* The count of FLEXIO_SHIFTBUF */
20859#define FLEXIO_SHIFTBUF_COUNT (4U)
20860
20864#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
20865#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
20868#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
20871/* The count of FLEXIO_SHIFTBUFBIS */
20872#define FLEXIO_SHIFTBUFBIS_COUNT (4U)
20873
20877#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
20878#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
20881#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
20884/* The count of FLEXIO_SHIFTBUFBYS */
20885#define FLEXIO_SHIFTBUFBYS_COUNT (4U)
20886
20890#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
20891#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
20894#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
20897/* The count of FLEXIO_SHIFTBUFBBS */
20898#define FLEXIO_SHIFTBUFBBS_COUNT (4U)
20899
20903#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
20904#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
20911#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
20912
20913#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
20914#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
20919#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
20920
20921#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20922#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
20925#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
20926
20927#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
20928#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
20935#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
20936
20937#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
20938#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
20943#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
20944
20945#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
20946#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
20951#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
20952
20953#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
20954#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
20957#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
20960/* The count of FLEXIO_TIMCTL */
20961#define FLEXIO_TIMCTL_COUNT (4U)
20962
20966#define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
20967#define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
20972#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
20973
20974#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
20975#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
20982#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
20983
20984#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
20985#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
20996#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
20997
20998#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
20999#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
21010#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
21011
21012#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
21013#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
21024#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
21025
21026#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
21027#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
21034#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
21035
21036#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
21037#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
21044#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
21047/* The count of FLEXIO_TIMCFG */
21048#define FLEXIO_TIMCFG_COUNT (4U)
21049
21053#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
21054#define FLEXIO_TIMCMP_CMP_SHIFT (0U)
21057#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
21060/* The count of FLEXIO_TIMCMP */
21061#define FLEXIO_TIMCMP_COUNT (4U)
21062
21066#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
21067#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
21070#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
21073/* The count of FLEXIO_SHIFTBUFNBS */
21074#define FLEXIO_SHIFTBUFNBS_COUNT (4U)
21075
21079#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
21080#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
21083#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
21086/* The count of FLEXIO_SHIFTBUFHWS */
21087#define FLEXIO_SHIFTBUFHWS_COUNT (4U)
21088
21092#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
21093#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
21096#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
21099/* The count of FLEXIO_SHIFTBUFNIS */
21100#define FLEXIO_SHIFTBUFNIS_COUNT (4U)
21101
21102 /* end of group FLEXIO_Register_Masks */
21106
21107
21108/* FLEXIO - Peripheral instance base addresses */
21110#define FLEXIO1_BASE (0x401AC000u)
21112#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)
21114#define FLEXIO2_BASE (0x401B0000u)
21116#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)
21118#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
21120#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
21122#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
21123 /* end of group FLEXIO_Peripheral_Access_Layer */
21127
21128
21129/* ----------------------------------------------------------------------------
21130 -- FLEXRAM Peripheral Access Layer
21131 ---------------------------------------------------------------------------- */
21132
21139typedef struct {
21140 __IO uint32_t TCM_CTRL;
21141 uint8_t RESERVED_0[12];
21142 __IO uint32_t INT_STATUS;
21143 __IO uint32_t INT_STAT_EN;
21144 __IO uint32_t INT_SIG_EN;
21145} FLEXRAM_Type;
21146
21147/* ----------------------------------------------------------------------------
21148 -- FLEXRAM Register Masks
21149 ---------------------------------------------------------------------------- */
21150
21159#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)
21160#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)
21165#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
21166
21167#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)
21168#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)
21173#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
21174
21175#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)
21176#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)
21179#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
21185#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)
21186#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
21191#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
21192
21193#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)
21194#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
21199#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
21200
21201#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
21202#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
21207#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
21213#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
21214#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
21219#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
21220
21221#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
21222#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
21227#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
21228
21229#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
21230#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
21235#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
21241#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)
21242#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
21247#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
21248
21249#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)
21250#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
21255#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
21256
21257#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
21258#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
21263#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) /* end of group FLEXRAM_Register_Masks */
21270
21271
21272/* FLEXRAM - Peripheral instance base addresses */
21274#define FLEXRAM_BASE (0x400B0000u)
21276#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)
21278#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE }
21280#define FLEXRAM_BASE_PTRS { FLEXRAM }
21282#define FLEXRAM_IRQS { FLEXRAM_IRQn }
21283 /* end of group FLEXRAM_Peripheral_Access_Layer */
21287
21288
21289/* ----------------------------------------------------------------------------
21290 -- FLEXSPI Peripheral Access Layer
21291 ---------------------------------------------------------------------------- */
21292
21299typedef struct {
21300 __IO uint32_t MCR0;
21301 __IO uint32_t MCR1;
21302 __IO uint32_t MCR2;
21303 __IO uint32_t AHBCR;
21304 __IO uint32_t INTEN;
21305 __IO uint32_t INTR;
21306 __IO uint32_t LUTKEY;
21307 __IO uint32_t LUTCR;
21308 __IO uint32_t AHBRXBUFCR0[4];
21309 uint8_t RESERVED_0[48];
21310 __IO uint32_t FLSHCR0[4];
21311 __IO uint32_t FLSHCR1[4];
21312 __IO uint32_t FLSHCR2[4];
21313 uint8_t RESERVED_1[4];
21314 __IO uint32_t FLSHCR4;
21315 uint8_t RESERVED_2[8];
21316 __IO uint32_t IPCR0;
21317 __IO uint32_t IPCR1;
21318 uint8_t RESERVED_3[8];
21319 __IO uint32_t IPCMD;
21320 uint8_t RESERVED_4[4];
21321 __IO uint32_t IPRXFCR;
21322 __IO uint32_t IPTXFCR;
21323 __IO uint32_t DLLCR[2];
21324 uint8_t RESERVED_5[24];
21325 __I uint32_t STS0;
21326 __I uint32_t STS1;
21327 __I uint32_t STS2;
21328 __I uint32_t AHBSPNDSTS;
21329 __I uint32_t IPRXFSTS;
21330 __I uint32_t IPTXFSTS;
21331 uint8_t RESERVED_6[8];
21332 __I uint32_t RFDR[32];
21333 __O uint32_t TFDR[32];
21334 __IO uint32_t LUT[64];
21335} FLEXSPI_Type;
21336
21337/* ----------------------------------------------------------------------------
21338 -- FLEXSPI Register Masks
21339 ---------------------------------------------------------------------------- */
21340
21349#define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
21350#define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
21353#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
21354
21355#define FLEXSPI_MCR0_MDIS_MASK (0x2U)
21356#define FLEXSPI_MCR0_MDIS_SHIFT (1U)
21359#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
21360
21361#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
21362#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
21369#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
21370
21371#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
21372#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
21377#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
21378
21379#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
21380#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
21385#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
21386
21387#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U)
21388#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U)
21399#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
21400
21401#define FLEXSPI_MCR0_HSEN_MASK (0x800U)
21402#define FLEXSPI_MCR0_HSEN_SHIFT (11U)
21407#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
21408
21409#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
21410#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
21415#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
21416
21417#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
21418#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
21423#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
21424
21425#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
21426#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
21433#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
21434
21435#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
21436#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
21439#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
21440
21441#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
21442#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
21445#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
21451#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
21452#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
21453#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
21454
21455#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
21456#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
21457#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
21463#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
21464#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
21472#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
21473
21474#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
21475#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
21479#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
21480
21481#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
21482#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
21490#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
21491
21492#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
21493#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
21500#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
21501
21502#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
21503#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
21506#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
21512#define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
21513#define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
21518#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
21519
21520#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
21521#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
21526#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
21527
21528#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
21529#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
21537#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
21538
21539#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
21540#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
21543#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
21544
21545#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
21546#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
21552#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
21558#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
21559#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
21562#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
21563
21564#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
21565#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
21568#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
21569
21570#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
21571#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
21574#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
21575
21576#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
21577#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
21580#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
21581
21582#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
21583#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
21586#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
21587
21588#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
21589#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
21592#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
21593
21594#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
21595#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
21598#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
21599
21600#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
21601#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
21604#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
21605
21606#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
21607#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
21610#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
21611
21612#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
21613#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
21616#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
21617
21618#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
21619#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
21622#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
21628#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
21629#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
21633#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
21634
21635#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
21636#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
21639#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
21640
21641#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
21642#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
21645#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
21646
21647#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
21648#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
21652#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
21653
21654#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
21655#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
21659#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
21660
21661#define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
21662#define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
21665#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
21666
21667#define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
21668#define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
21671#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
21672
21673#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
21674#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
21677#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
21678
21679#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
21680#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
21683#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
21684
21685#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
21686#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
21689#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
21690
21691#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
21692#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
21695#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
21701#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
21702#define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
21705#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
21711#define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
21712#define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
21715#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
21716
21717#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
21718#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
21721#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
21727#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)
21728#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
21731#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
21732
21733#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
21734#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
21737#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
21738
21739#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)
21740#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
21743#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
21744
21745#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
21746#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
21749#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
21752/* The count of FLEXSPI_AHBRXBUFCR0 */
21753#define FLEXSPI_AHBRXBUFCR0_COUNT (4U)
21754
21758#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
21759#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
21762#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
21765/* The count of FLEXSPI_FLSHCR0 */
21766#define FLEXSPI_FLSHCR0_COUNT (4U)
21767
21771#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
21772#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
21775#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
21776
21777#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
21778#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
21781#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
21782
21783#define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
21784#define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
21787#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
21788
21789#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
21790#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
21793#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
21794
21795#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
21796#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
21801#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
21802
21803#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
21804#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
21810#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
21813/* The count of FLEXSPI_FLSHCR1 */
21814#define FLEXSPI_FLSHCR1_COUNT (4U)
21815
21819#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)
21820#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
21823#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
21824
21825#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
21826#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
21829#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
21830
21831#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)
21832#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
21835#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
21836
21837#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
21838#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
21841#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
21842
21843#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
21844#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
21845#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
21846
21847#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
21848#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
21859#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
21860
21861#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
21862#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
21866#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
21869/* The count of FLEXSPI_FLSHCR2 */
21870#define FLEXSPI_FLSHCR2_COUNT (4U)
21871
21875#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
21876#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
21883#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
21884
21885#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
21886#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
21892#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
21893
21894#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
21895#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
21901#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
21907#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
21908#define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
21911#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
21917#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
21918#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
21921#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
21922
21923#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)
21924#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
21927#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
21928
21929#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
21930#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
21933#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
21934
21935#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
21936#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
21941#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
21947#define FLEXSPI_IPCMD_TRG_MASK (0x1U)
21948#define FLEXSPI_IPCMD_TRG_SHIFT (0U)
21951#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
21957#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
21958#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
21961#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
21962
21963#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
21964#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
21969#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
21970
21971#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)
21972#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
21975#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
21981#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
21982#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
21985#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
21986
21987#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
21988#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
21993#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
21994
21995#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)
21996#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
21999#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
22005#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
22006#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
22009#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
22010
22011#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
22012#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
22018#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
22019
22020#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
22021#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
22024#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
22025
22026#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
22027#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
22030#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
22031
22032#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
22033#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
22036#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
22039/* The count of FLEXSPI_DLLCR */
22040#define FLEXSPI_DLLCR_COUNT (2U)
22041
22045#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
22046#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
22050#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
22051
22052#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
22053#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
22059#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
22060
22061#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
22062#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
22070#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
22076#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)
22077#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
22081#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
22082
22083#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
22084#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
22094#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
22095
22096#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)
22097#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
22101#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
22102
22103#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
22104#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
22116#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
22122#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
22123#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
22126#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
22127
22128#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
22129#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
22132#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
22133
22134#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
22135#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
22138#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
22139
22140#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
22141#define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
22144#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
22145
22146#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
22147#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
22150#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
22151
22152#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
22153#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
22156#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
22157
22158#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
22159#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
22162#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
22163
22164#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
22165#define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
22168#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
22174#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
22175#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
22178#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
22179
22180#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
22181#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
22184#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
22185
22186#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
22187#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
22190#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
22196#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
22197#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
22200#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
22201
22202#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
22203#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
22206#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
22212#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
22213#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
22216#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
22217
22218#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
22219#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
22222#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
22228#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
22229#define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
22232#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
22235/* The count of FLEXSPI_RFDR */
22236#define FLEXSPI_RFDR_COUNT (32U)
22237
22241#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
22242#define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
22245#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
22248/* The count of FLEXSPI_TFDR */
22249#define FLEXSPI_TFDR_COUNT (32U)
22250
22254#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
22255#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
22258#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
22259
22260#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
22261#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
22264#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
22265
22266#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
22267#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
22270#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
22271
22272#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
22273#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
22276#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
22277
22278#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
22279#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
22282#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
22283
22284#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
22285#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
22288#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
22291/* The count of FLEXSPI_LUT */
22292#define FLEXSPI_LUT_COUNT (64U)
22293
22294 /* end of group FLEXSPI_Register_Masks */
22298
22299
22300/* FLEXSPI - Peripheral instance base addresses */
22302#define FLEXSPI_BASE (0x402A8000u)
22304#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)
22306#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE }
22308#define FLEXSPI_BASE_PTRS { FLEXSPI }
22310#define FLEXSPI_IRQS { FLEXSPI_IRQn }
22311/* FlexSPI AMBA address. */
22312#define FlexSPI_AMBA_BASE (0x60000000U)
22313/* FlexSPI ASFM address. */
22314#define FlexSPI_ASFM_BASE (0x00000000U)
22315/* Base Address of AHB address space mapped to IP RX FIFO. */
22316#define FlexSPI_ARDF_BASE (0x7FC00000U)
22317/* Base Address of AHB address space mapped to IP TX FIFO. */
22318#define FlexSPI_ATDF_BASE (0x7F800000U)
22319
22320 /* end of group FLEXSPI_Peripheral_Access_Layer */
22324
22325
22326/* ----------------------------------------------------------------------------
22327 -- GPC Peripheral Access Layer
22328 ---------------------------------------------------------------------------- */
22329
22336typedef struct {
22337 __IO uint32_t CNTR;
22338 uint8_t RESERVED_0[4];
22339 __IO uint32_t IMR[4];
22340 __I uint32_t ISR[4];
22341 uint8_t RESERVED_1[12];
22342 __IO uint32_t IMR5;
22343 __I uint32_t ISR5;
22344} GPC_Type;
22345
22346/* ----------------------------------------------------------------------------
22347 -- GPC Register Masks
22348 ---------------------------------------------------------------------------- */
22349
22358#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)
22359#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)
22364#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
22365
22366#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)
22367#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)
22372#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
22373
22374#define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U)
22375#define GPC_CNTR_PDRAM0_PGE_SHIFT (22U)
22380#define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)
22386#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU)
22387#define GPC_IMR_IMR1_SHIFT (0U)
22388#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
22389
22390#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU)
22391#define GPC_IMR_IMR2_SHIFT (0U)
22392#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)
22393
22394#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU)
22395#define GPC_IMR_IMR3_SHIFT (0U)
22396#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)
22397
22398#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU)
22399#define GPC_IMR_IMR4_SHIFT (0U)
22400#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
22403/* The count of GPC_IMR */
22404#define GPC_IMR_COUNT (4U)
22405
22409#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU)
22410#define GPC_ISR_ISR1_SHIFT (0U)
22411#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)
22412
22413#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU)
22414#define GPC_ISR_ISR2_SHIFT (0U)
22415#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)
22416
22417#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU)
22418#define GPC_ISR_ISR3_SHIFT (0U)
22419#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)
22420
22421#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU)
22422#define GPC_ISR_ISR4_SHIFT (0U)
22423#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)
22426/* The count of GPC_ISR */
22427#define GPC_ISR_COUNT (4U)
22428
22432#define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU)
22433#define GPC_IMR5_IMR5_SHIFT (0U)
22434#define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)
22440#define GPC_ISR5_ISR5_MASK (0xFFFFFFFFU)
22441#define GPC_ISR5_ISR5_SHIFT (0U)
22442#define GPC_ISR5_ISR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR5_SHIFT)) & GPC_ISR5_ISR5_MASK) /* end of group GPC_Register_Masks */
22449
22450
22451/* GPC - Peripheral instance base addresses */
22453#define GPC_BASE (0x400F4000u)
22455#define GPC ((GPC_Type *)GPC_BASE)
22457#define GPC_BASE_ADDRS { GPC_BASE }
22459#define GPC_BASE_PTRS { GPC }
22461#define GPC_IRQS { GPC_IRQn }
22462 /* end of group GPC_Peripheral_Access_Layer */
22466
22467
22468/* ----------------------------------------------------------------------------
22469 -- GPIO Peripheral Access Layer
22470 ---------------------------------------------------------------------------- */
22471
22478typedef struct {
22479 __IO uint32_t DR;
22480 __IO uint32_t GDIR;
22481 __I uint32_t PSR;
22482 __IO uint32_t ICR1;
22483 __IO uint32_t ICR2;
22484 __IO uint32_t IMR;
22485 __IO uint32_t ISR;
22486 __IO uint32_t EDGE_SEL;
22487 uint8_t RESERVED_0[100];
22488 __O uint32_t DR_SET;
22489 __O uint32_t DR_CLEAR;
22490 __O uint32_t DR_TOGGLE;
22491} GPIO_Type;
22492
22493/* ----------------------------------------------------------------------------
22494 -- GPIO Register Masks
22495 ---------------------------------------------------------------------------- */
22496
22505#define GPIO_DR_DR_MASK (0xFFFFFFFFU)
22506#define GPIO_DR_DR_SHIFT (0U)
22509#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
22515#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
22516#define GPIO_GDIR_GDIR_SHIFT (0U)
22519#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
22525#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
22526#define GPIO_PSR_PSR_SHIFT (0U)
22529#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
22535#define GPIO_ICR1_ICR0_MASK (0x3U)
22536#define GPIO_ICR1_ICR0_SHIFT (0U)
22543#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
22544
22545#define GPIO_ICR1_ICR1_MASK (0xCU)
22546#define GPIO_ICR1_ICR1_SHIFT (2U)
22553#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
22554
22555#define GPIO_ICR1_ICR2_MASK (0x30U)
22556#define GPIO_ICR1_ICR2_SHIFT (4U)
22563#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
22564
22565#define GPIO_ICR1_ICR3_MASK (0xC0U)
22566#define GPIO_ICR1_ICR3_SHIFT (6U)
22573#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
22574
22575#define GPIO_ICR1_ICR4_MASK (0x300U)
22576#define GPIO_ICR1_ICR4_SHIFT (8U)
22583#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
22584
22585#define GPIO_ICR1_ICR5_MASK (0xC00U)
22586#define GPIO_ICR1_ICR5_SHIFT (10U)
22593#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
22594
22595#define GPIO_ICR1_ICR6_MASK (0x3000U)
22596#define GPIO_ICR1_ICR6_SHIFT (12U)
22603#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
22604
22605#define GPIO_ICR1_ICR7_MASK (0xC000U)
22606#define GPIO_ICR1_ICR7_SHIFT (14U)
22613#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
22614
22615#define GPIO_ICR1_ICR8_MASK (0x30000U)
22616#define GPIO_ICR1_ICR8_SHIFT (16U)
22623#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
22624
22625#define GPIO_ICR1_ICR9_MASK (0xC0000U)
22626#define GPIO_ICR1_ICR9_SHIFT (18U)
22633#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
22634
22635#define GPIO_ICR1_ICR10_MASK (0x300000U)
22636#define GPIO_ICR1_ICR10_SHIFT (20U)
22643#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
22644
22645#define GPIO_ICR1_ICR11_MASK (0xC00000U)
22646#define GPIO_ICR1_ICR11_SHIFT (22U)
22653#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
22654
22655#define GPIO_ICR1_ICR12_MASK (0x3000000U)
22656#define GPIO_ICR1_ICR12_SHIFT (24U)
22663#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
22664
22665#define GPIO_ICR1_ICR13_MASK (0xC000000U)
22666#define GPIO_ICR1_ICR13_SHIFT (26U)
22673#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
22674
22675#define GPIO_ICR1_ICR14_MASK (0x30000000U)
22676#define GPIO_ICR1_ICR14_SHIFT (28U)
22683#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
22684
22685#define GPIO_ICR1_ICR15_MASK (0xC0000000U)
22686#define GPIO_ICR1_ICR15_SHIFT (30U)
22693#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
22699#define GPIO_ICR2_ICR16_MASK (0x3U)
22700#define GPIO_ICR2_ICR16_SHIFT (0U)
22707#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
22708
22709#define GPIO_ICR2_ICR17_MASK (0xCU)
22710#define GPIO_ICR2_ICR17_SHIFT (2U)
22717#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
22718
22719#define GPIO_ICR2_ICR18_MASK (0x30U)
22720#define GPIO_ICR2_ICR18_SHIFT (4U)
22727#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
22728
22729#define GPIO_ICR2_ICR19_MASK (0xC0U)
22730#define GPIO_ICR2_ICR19_SHIFT (6U)
22737#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
22738
22739#define GPIO_ICR2_ICR20_MASK (0x300U)
22740#define GPIO_ICR2_ICR20_SHIFT (8U)
22747#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
22748
22749#define GPIO_ICR2_ICR21_MASK (0xC00U)
22750#define GPIO_ICR2_ICR21_SHIFT (10U)
22757#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
22758
22759#define GPIO_ICR2_ICR22_MASK (0x3000U)
22760#define GPIO_ICR2_ICR22_SHIFT (12U)
22767#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
22768
22769#define GPIO_ICR2_ICR23_MASK (0xC000U)
22770#define GPIO_ICR2_ICR23_SHIFT (14U)
22777#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
22778
22779#define GPIO_ICR2_ICR24_MASK (0x30000U)
22780#define GPIO_ICR2_ICR24_SHIFT (16U)
22787#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
22788
22789#define GPIO_ICR2_ICR25_MASK (0xC0000U)
22790#define GPIO_ICR2_ICR25_SHIFT (18U)
22797#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
22798
22799#define GPIO_ICR2_ICR26_MASK (0x300000U)
22800#define GPIO_ICR2_ICR26_SHIFT (20U)
22807#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
22808
22809#define GPIO_ICR2_ICR27_MASK (0xC00000U)
22810#define GPIO_ICR2_ICR27_SHIFT (22U)
22817#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
22818
22819#define GPIO_ICR2_ICR28_MASK (0x3000000U)
22820#define GPIO_ICR2_ICR28_SHIFT (24U)
22827#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
22828
22829#define GPIO_ICR2_ICR29_MASK (0xC000000U)
22830#define GPIO_ICR2_ICR29_SHIFT (26U)
22837#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
22838
22839#define GPIO_ICR2_ICR30_MASK (0x30000000U)
22840#define GPIO_ICR2_ICR30_SHIFT (28U)
22847#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
22848
22849#define GPIO_ICR2_ICR31_MASK (0xC0000000U)
22850#define GPIO_ICR2_ICR31_SHIFT (30U)
22857#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
22863#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
22864#define GPIO_IMR_IMR_SHIFT (0U)
22867#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
22873#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
22874#define GPIO_ISR_ISR_SHIFT (0U)
22877#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
22883#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
22884#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
22887#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
22893#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)
22894#define GPIO_DR_SET_DR_SET_SHIFT (0U)
22897#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
22903#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)
22904#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)
22907#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
22913#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)
22914#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)
22917#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) /* end of group GPIO_Register_Masks */
22924
22925
22926/* GPIO - Peripheral instance base addresses */
22928#define GPIO1_BASE (0x401B8000u)
22930#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
22932#define GPIO2_BASE (0x401BC000u)
22934#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
22936#define GPIO3_BASE (0x401C0000u)
22938#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
22940#define GPIO4_BASE (0x401C4000u)
22942#define GPIO4 ((GPIO_Type *)GPIO4_BASE)
22944#define GPIO5_BASE (0x400C0000u)
22946#define GPIO5 ((GPIO_Type *)GPIO5_BASE)
22948#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }
22950#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
22952#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
22953#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn }
22954#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn }
22955 /* end of group GPIO_Peripheral_Access_Layer */
22959
22960
22961/* ----------------------------------------------------------------------------
22962 -- GPT Peripheral Access Layer
22963 ---------------------------------------------------------------------------- */
22964
22971typedef struct {
22972 __IO uint32_t CR;
22973 __IO uint32_t PR;
22974 __IO uint32_t SR;
22975 __IO uint32_t IR;
22976 __IO uint32_t OCR[3];
22977 __I uint32_t ICR[2];
22978 __I uint32_t CNT;
22979} GPT_Type;
22980
22981/* ----------------------------------------------------------------------------
22982 -- GPT Register Masks
22983 ---------------------------------------------------------------------------- */
22984
22993#define GPT_CR_EN_MASK (0x1U)
22994#define GPT_CR_EN_SHIFT (0U)
22999#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
23000
23001#define GPT_CR_ENMOD_MASK (0x2U)
23002#define GPT_CR_ENMOD_SHIFT (1U)
23007#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
23008
23009#define GPT_CR_DBGEN_MASK (0x4U)
23010#define GPT_CR_DBGEN_SHIFT (2U)
23015#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
23016
23017#define GPT_CR_WAITEN_MASK (0x8U)
23018#define GPT_CR_WAITEN_SHIFT (3U)
23023#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
23024
23025#define GPT_CR_DOZEEN_MASK (0x10U)
23026#define GPT_CR_DOZEEN_SHIFT (4U)
23031#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
23032
23033#define GPT_CR_STOPEN_MASK (0x20U)
23034#define GPT_CR_STOPEN_SHIFT (5U)
23039#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
23040
23041#define GPT_CR_CLKSRC_MASK (0x1C0U)
23042#define GPT_CR_CLKSRC_SHIFT (6U)
23051#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
23052
23053#define GPT_CR_FRR_MASK (0x200U)
23054#define GPT_CR_FRR_SHIFT (9U)
23059#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
23060
23061#define GPT_CR_EN_24M_MASK (0x400U)
23062#define GPT_CR_EN_24M_SHIFT (10U)
23067#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
23068
23069#define GPT_CR_SWR_MASK (0x8000U)
23070#define GPT_CR_SWR_SHIFT (15U)
23075#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
23076
23077#define GPT_CR_IM1_MASK (0x30000U)
23078#define GPT_CR_IM1_SHIFT (16U)
23079#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
23080
23081#define GPT_CR_IM2_MASK (0xC0000U)
23082#define GPT_CR_IM2_SHIFT (18U)
23089#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
23090
23091#define GPT_CR_OM1_MASK (0x700000U)
23092#define GPT_CR_OM1_SHIFT (20U)
23093#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
23094
23095#define GPT_CR_OM2_MASK (0x3800000U)
23096#define GPT_CR_OM2_SHIFT (23U)
23097#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
23098
23099#define GPT_CR_OM3_MASK (0x1C000000U)
23100#define GPT_CR_OM3_SHIFT (26U)
23108#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
23109
23110#define GPT_CR_FO1_MASK (0x20000000U)
23111#define GPT_CR_FO1_SHIFT (29U)
23112#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
23113
23114#define GPT_CR_FO2_MASK (0x40000000U)
23115#define GPT_CR_FO2_SHIFT (30U)
23116#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
23117
23118#define GPT_CR_FO3_MASK (0x80000000U)
23119#define GPT_CR_FO3_SHIFT (31U)
23124#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
23130#define GPT_PR_PRESCALER_MASK (0xFFFU)
23131#define GPT_PR_PRESCALER_SHIFT (0U)
23137#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
23138
23139#define GPT_PR_PRESCALER24M_MASK (0xF000U)
23140#define GPT_PR_PRESCALER24M_SHIFT (12U)
23146#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
23152#define GPT_SR_OF1_MASK (0x1U)
23153#define GPT_SR_OF1_SHIFT (0U)
23154#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
23155
23156#define GPT_SR_OF2_MASK (0x2U)
23157#define GPT_SR_OF2_SHIFT (1U)
23158#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
23159
23160#define GPT_SR_OF3_MASK (0x4U)
23161#define GPT_SR_OF3_SHIFT (2U)
23166#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
23167
23168#define GPT_SR_IF1_MASK (0x8U)
23169#define GPT_SR_IF1_SHIFT (3U)
23170#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
23171
23172#define GPT_SR_IF2_MASK (0x10U)
23173#define GPT_SR_IF2_SHIFT (4U)
23178#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
23179
23180#define GPT_SR_ROV_MASK (0x20U)
23181#define GPT_SR_ROV_SHIFT (5U)
23186#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
23192#define GPT_IR_OF1IE_MASK (0x1U)
23193#define GPT_IR_OF1IE_SHIFT (0U)
23194#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
23195
23196#define GPT_IR_OF2IE_MASK (0x2U)
23197#define GPT_IR_OF2IE_SHIFT (1U)
23198#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
23199
23200#define GPT_IR_OF3IE_MASK (0x4U)
23201#define GPT_IR_OF3IE_SHIFT (2U)
23206#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
23207
23208#define GPT_IR_IF1IE_MASK (0x8U)
23209#define GPT_IR_IF1IE_SHIFT (3U)
23210#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
23211
23212#define GPT_IR_IF2IE_MASK (0x10U)
23213#define GPT_IR_IF2IE_SHIFT (4U)
23218#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
23219
23220#define GPT_IR_ROVIE_MASK (0x20U)
23221#define GPT_IR_ROVIE_SHIFT (5U)
23226#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
23232#define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
23233#define GPT_OCR_COMP_SHIFT (0U)
23234#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
23237/* The count of GPT_OCR */
23238#define GPT_OCR_COUNT (3U)
23239
23243#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
23244#define GPT_ICR_CAPT_SHIFT (0U)
23245#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
23248/* The count of GPT_ICR */
23249#define GPT_ICR_COUNT (2U)
23250
23254#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
23255#define GPT_CNT_COUNT_SHIFT (0U)
23256#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) /* end of group GPT_Register_Masks */
23263
23264
23265/* GPT - Peripheral instance base addresses */
23267#define GPT1_BASE (0x401EC000u)
23269#define GPT1 ((GPT_Type *)GPT1_BASE)
23271#define GPT2_BASE (0x401F0000u)
23273#define GPT2 ((GPT_Type *)GPT2_BASE)
23275#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }
23277#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }
23279#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }
23280 /* end of group GPT_Peripheral_Access_Layer */
23284
23285
23286/* ----------------------------------------------------------------------------
23287 -- I2S Peripheral Access Layer
23288 ---------------------------------------------------------------------------- */
23289
23296typedef struct {
23297 __I uint32_t VERID;
23298 __I uint32_t PARAM;
23299 __IO uint32_t TCSR;
23300 __IO uint32_t TCR1;
23301 __IO uint32_t TCR2;
23302 __IO uint32_t TCR3;
23303 __IO uint32_t TCR4;
23304 __IO uint32_t TCR5;
23305 __O uint32_t TDR[4];
23306 uint8_t RESERVED_0[16];
23307 __I uint32_t TFR[4];
23308 uint8_t RESERVED_1[16];
23309 __IO uint32_t TMR;
23310 uint8_t RESERVED_2[36];
23311 __IO uint32_t RCSR;
23312 __IO uint32_t RCR1;
23313 __IO uint32_t RCR2;
23314 __IO uint32_t RCR3;
23315 __IO uint32_t RCR4;
23316 __IO uint32_t RCR5;
23317 __I uint32_t RDR[4];
23318 uint8_t RESERVED_3[16];
23319 __I uint32_t RFR[4];
23320 uint8_t RESERVED_4[16];
23321 __IO uint32_t RMR;
23322} I2S_Type;
23323
23324/* ----------------------------------------------------------------------------
23325 -- I2S Register Masks
23326 ---------------------------------------------------------------------------- */
23327
23336#define I2S_VERID_FEATURE_MASK (0xFFFFU)
23337#define I2S_VERID_FEATURE_SHIFT (0U)
23341#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
23342
23343#define I2S_VERID_MINOR_MASK (0xFF0000U)
23344#define I2S_VERID_MINOR_SHIFT (16U)
23347#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
23348
23349#define I2S_VERID_MAJOR_MASK (0xFF000000U)
23350#define I2S_VERID_MAJOR_SHIFT (24U)
23353#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
23359#define I2S_PARAM_DATALINE_MASK (0xFU)
23360#define I2S_PARAM_DATALINE_SHIFT (0U)
23363#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
23364
23365#define I2S_PARAM_FIFO_MASK (0xF00U)
23366#define I2S_PARAM_FIFO_SHIFT (8U)
23369#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
23370
23371#define I2S_PARAM_FRAME_MASK (0xF0000U)
23372#define I2S_PARAM_FRAME_SHIFT (16U)
23375#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
23381#define I2S_TCSR_FRDE_MASK (0x1U)
23382#define I2S_TCSR_FRDE_SHIFT (0U)
23387#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
23388
23389#define I2S_TCSR_FWDE_MASK (0x2U)
23390#define I2S_TCSR_FWDE_SHIFT (1U)
23395#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
23396
23397#define I2S_TCSR_FRIE_MASK (0x100U)
23398#define I2S_TCSR_FRIE_SHIFT (8U)
23403#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
23404
23405#define I2S_TCSR_FWIE_MASK (0x200U)
23406#define I2S_TCSR_FWIE_SHIFT (9U)
23411#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
23412
23413#define I2S_TCSR_FEIE_MASK (0x400U)
23414#define I2S_TCSR_FEIE_SHIFT (10U)
23419#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
23420
23421#define I2S_TCSR_SEIE_MASK (0x800U)
23422#define I2S_TCSR_SEIE_SHIFT (11U)
23427#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
23428
23429#define I2S_TCSR_WSIE_MASK (0x1000U)
23430#define I2S_TCSR_WSIE_SHIFT (12U)
23435#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
23436
23437#define I2S_TCSR_FRF_MASK (0x10000U)
23438#define I2S_TCSR_FRF_SHIFT (16U)
23443#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
23444
23445#define I2S_TCSR_FWF_MASK (0x20000U)
23446#define I2S_TCSR_FWF_SHIFT (17U)
23451#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
23452
23453#define I2S_TCSR_FEF_MASK (0x40000U)
23454#define I2S_TCSR_FEF_SHIFT (18U)
23459#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
23460
23461#define I2S_TCSR_SEF_MASK (0x80000U)
23462#define I2S_TCSR_SEF_SHIFT (19U)
23467#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
23468
23469#define I2S_TCSR_WSF_MASK (0x100000U)
23470#define I2S_TCSR_WSF_SHIFT (20U)
23475#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
23476
23477#define I2S_TCSR_SR_MASK (0x1000000U)
23478#define I2S_TCSR_SR_SHIFT (24U)
23483#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
23484
23485#define I2S_TCSR_FR_MASK (0x2000000U)
23486#define I2S_TCSR_FR_SHIFT (25U)
23491#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
23492
23493#define I2S_TCSR_BCE_MASK (0x10000000U)
23494#define I2S_TCSR_BCE_SHIFT (28U)
23499#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
23500
23501#define I2S_TCSR_DBGE_MASK (0x20000000U)
23502#define I2S_TCSR_DBGE_SHIFT (29U)
23507#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
23508
23509#define I2S_TCSR_STOPE_MASK (0x40000000U)
23510#define I2S_TCSR_STOPE_SHIFT (30U)
23515#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
23516
23517#define I2S_TCSR_TE_MASK (0x80000000U)
23518#define I2S_TCSR_TE_SHIFT (31U)
23523#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
23529#define I2S_TCR1_TFW_MASK (0x1FU)
23530#define I2S_TCR1_TFW_SHIFT (0U)
23533#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
23539#define I2S_TCR2_DIV_MASK (0xFFU)
23540#define I2S_TCR2_DIV_SHIFT (0U)
23543#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
23544
23545#define I2S_TCR2_BCD_MASK (0x1000000U)
23546#define I2S_TCR2_BCD_SHIFT (24U)
23551#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
23552
23553#define I2S_TCR2_BCP_MASK (0x2000000U)
23554#define I2S_TCR2_BCP_SHIFT (25U)
23559#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
23560
23561#define I2S_TCR2_MSEL_MASK (0xC000000U)
23562#define I2S_TCR2_MSEL_SHIFT (26U)
23569#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
23570
23571#define I2S_TCR2_BCI_MASK (0x10000000U)
23572#define I2S_TCR2_BCI_SHIFT (28U)
23577#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
23578
23579#define I2S_TCR2_BCS_MASK (0x20000000U)
23580#define I2S_TCR2_BCS_SHIFT (29U)
23585#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
23586
23587#define I2S_TCR2_SYNC_MASK (0x40000000U)
23588#define I2S_TCR2_SYNC_SHIFT (30U)
23593#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
23599#define I2S_TCR3_WDFL_MASK (0x1FU)
23600#define I2S_TCR3_WDFL_SHIFT (0U)
23603#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
23604
23605#define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
23606#define I2S_TCR3_TCE_SHIFT (16U)
23609#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
23610
23611#define I2S_TCR3_CFR_MASK (0xF000000U)
23612#define I2S_TCR3_CFR_SHIFT (24U)
23615#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
23621#define I2S_TCR4_FSD_MASK (0x1U)
23622#define I2S_TCR4_FSD_SHIFT (0U)
23627#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
23628
23629#define I2S_TCR4_FSP_MASK (0x2U)
23630#define I2S_TCR4_FSP_SHIFT (1U)
23635#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
23636
23637#define I2S_TCR4_ONDEM_MASK (0x4U)
23638#define I2S_TCR4_ONDEM_SHIFT (2U)
23643#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
23644
23645#define I2S_TCR4_FSE_MASK (0x8U)
23646#define I2S_TCR4_FSE_SHIFT (3U)
23651#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
23652
23653#define I2S_TCR4_MF_MASK (0x10U)
23654#define I2S_TCR4_MF_SHIFT (4U)
23659#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
23660
23661#define I2S_TCR4_CHMOD_MASK (0x20U)
23662#define I2S_TCR4_CHMOD_SHIFT (5U)
23667#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
23668
23669#define I2S_TCR4_SYWD_MASK (0x1F00U)
23670#define I2S_TCR4_SYWD_SHIFT (8U)
23673#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
23674
23675#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
23676#define I2S_TCR4_FRSZ_SHIFT (16U)
23679#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
23680
23681#define I2S_TCR4_FPACK_MASK (0x3000000U)
23682#define I2S_TCR4_FPACK_SHIFT (24U)
23689#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
23690
23691#define I2S_TCR4_FCOMB_MASK (0xC000000U)
23692#define I2S_TCR4_FCOMB_SHIFT (26U)
23699#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
23700
23701#define I2S_TCR4_FCONT_MASK (0x10000000U)
23702#define I2S_TCR4_FCONT_SHIFT (28U)
23707#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
23713#define I2S_TCR5_FBT_MASK (0x1F00U)
23714#define I2S_TCR5_FBT_SHIFT (8U)
23717#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
23718
23719#define I2S_TCR5_W0W_MASK (0x1F0000U)
23720#define I2S_TCR5_W0W_SHIFT (16U)
23723#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
23724
23725#define I2S_TCR5_WNW_MASK (0x1F000000U)
23726#define I2S_TCR5_WNW_SHIFT (24U)
23729#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
23735#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
23736#define I2S_TDR_TDR_SHIFT (0U)
23739#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
23742/* The count of I2S_TDR */
23743#define I2S_TDR_COUNT (4U)
23744
23748#define I2S_TFR_RFP_MASK (0x3FU)
23749#define I2S_TFR_RFP_SHIFT (0U)
23752#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
23753
23754#define I2S_TFR_WFP_MASK (0x3F0000U)
23755#define I2S_TFR_WFP_SHIFT (16U)
23758#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
23759
23760#define I2S_TFR_WCP_MASK (0x80000000U)
23761#define I2S_TFR_WCP_SHIFT (31U)
23766#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
23769/* The count of I2S_TFR */
23770#define I2S_TFR_COUNT (4U)
23771
23775#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
23776#define I2S_TMR_TWM_SHIFT (0U)
23781#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
23787#define I2S_RCSR_FRDE_MASK (0x1U)
23788#define I2S_RCSR_FRDE_SHIFT (0U)
23793#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
23794
23795#define I2S_RCSR_FWDE_MASK (0x2U)
23796#define I2S_RCSR_FWDE_SHIFT (1U)
23801#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
23802
23803#define I2S_RCSR_FRIE_MASK (0x100U)
23804#define I2S_RCSR_FRIE_SHIFT (8U)
23809#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
23810
23811#define I2S_RCSR_FWIE_MASK (0x200U)
23812#define I2S_RCSR_FWIE_SHIFT (9U)
23817#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
23818
23819#define I2S_RCSR_FEIE_MASK (0x400U)
23820#define I2S_RCSR_FEIE_SHIFT (10U)
23825#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
23826
23827#define I2S_RCSR_SEIE_MASK (0x800U)
23828#define I2S_RCSR_SEIE_SHIFT (11U)
23833#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
23834
23835#define I2S_RCSR_WSIE_MASK (0x1000U)
23836#define I2S_RCSR_WSIE_SHIFT (12U)
23841#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
23842
23843#define I2S_RCSR_FRF_MASK (0x10000U)
23844#define I2S_RCSR_FRF_SHIFT (16U)
23849#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
23850
23851#define I2S_RCSR_FWF_MASK (0x20000U)
23852#define I2S_RCSR_FWF_SHIFT (17U)
23857#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
23858
23859#define I2S_RCSR_FEF_MASK (0x40000U)
23860#define I2S_RCSR_FEF_SHIFT (18U)
23865#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
23866
23867#define I2S_RCSR_SEF_MASK (0x80000U)
23868#define I2S_RCSR_SEF_SHIFT (19U)
23873#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
23874
23875#define I2S_RCSR_WSF_MASK (0x100000U)
23876#define I2S_RCSR_WSF_SHIFT (20U)
23881#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
23882
23883#define I2S_RCSR_SR_MASK (0x1000000U)
23884#define I2S_RCSR_SR_SHIFT (24U)
23889#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
23890
23891#define I2S_RCSR_FR_MASK (0x2000000U)
23892#define I2S_RCSR_FR_SHIFT (25U)
23897#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
23898
23899#define I2S_RCSR_BCE_MASK (0x10000000U)
23900#define I2S_RCSR_BCE_SHIFT (28U)
23905#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
23906
23907#define I2S_RCSR_DBGE_MASK (0x20000000U)
23908#define I2S_RCSR_DBGE_SHIFT (29U)
23913#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
23914
23915#define I2S_RCSR_STOPE_MASK (0x40000000U)
23916#define I2S_RCSR_STOPE_SHIFT (30U)
23921#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
23922
23923#define I2S_RCSR_RE_MASK (0x80000000U)
23924#define I2S_RCSR_RE_SHIFT (31U)
23929#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
23935#define I2S_RCR1_RFW_MASK (0x1FU)
23936#define I2S_RCR1_RFW_SHIFT (0U)
23939#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
23945#define I2S_RCR2_DIV_MASK (0xFFU)
23946#define I2S_RCR2_DIV_SHIFT (0U)
23949#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
23950
23951#define I2S_RCR2_BCD_MASK (0x1000000U)
23952#define I2S_RCR2_BCD_SHIFT (24U)
23957#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
23958
23959#define I2S_RCR2_BCP_MASK (0x2000000U)
23960#define I2S_RCR2_BCP_SHIFT (25U)
23965#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
23966
23967#define I2S_RCR2_MSEL_MASK (0xC000000U)
23968#define I2S_RCR2_MSEL_SHIFT (26U)
23975#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
23976
23977#define I2S_RCR2_BCI_MASK (0x10000000U)
23978#define I2S_RCR2_BCI_SHIFT (28U)
23983#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
23984
23985#define I2S_RCR2_BCS_MASK (0x20000000U)
23986#define I2S_RCR2_BCS_SHIFT (29U)
23991#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
23992
23993#define I2S_RCR2_SYNC_MASK (0x40000000U)
23994#define I2S_RCR2_SYNC_SHIFT (30U)
23999#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
24005#define I2S_RCR3_WDFL_MASK (0x1FU)
24006#define I2S_RCR3_WDFL_SHIFT (0U)
24009#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
24010
24011#define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
24012#define I2S_RCR3_RCE_SHIFT (16U)
24015#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
24016
24017#define I2S_RCR3_CFR_MASK (0xF000000U)
24018#define I2S_RCR3_CFR_SHIFT (24U)
24021#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
24027#define I2S_RCR4_FSD_MASK (0x1U)
24028#define I2S_RCR4_FSD_SHIFT (0U)
24033#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
24034
24035#define I2S_RCR4_FSP_MASK (0x2U)
24036#define I2S_RCR4_FSP_SHIFT (1U)
24041#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
24042
24043#define I2S_RCR4_ONDEM_MASK (0x4U)
24044#define I2S_RCR4_ONDEM_SHIFT (2U)
24049#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
24050
24051#define I2S_RCR4_FSE_MASK (0x8U)
24052#define I2S_RCR4_FSE_SHIFT (3U)
24057#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
24058
24059#define I2S_RCR4_MF_MASK (0x10U)
24060#define I2S_RCR4_MF_SHIFT (4U)
24065#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
24066
24067#define I2S_RCR4_SYWD_MASK (0x1F00U)
24068#define I2S_RCR4_SYWD_SHIFT (8U)
24071#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
24072
24073#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
24074#define I2S_RCR4_FRSZ_SHIFT (16U)
24077#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
24078
24079#define I2S_RCR4_FPACK_MASK (0x3000000U)
24080#define I2S_RCR4_FPACK_SHIFT (24U)
24087#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
24088
24089#define I2S_RCR4_FCOMB_MASK (0xC000000U)
24090#define I2S_RCR4_FCOMB_SHIFT (26U)
24097#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
24098
24099#define I2S_RCR4_FCONT_MASK (0x10000000U)
24100#define I2S_RCR4_FCONT_SHIFT (28U)
24105#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
24111#define I2S_RCR5_FBT_MASK (0x1F00U)
24112#define I2S_RCR5_FBT_SHIFT (8U)
24115#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
24116
24117#define I2S_RCR5_W0W_MASK (0x1F0000U)
24118#define I2S_RCR5_W0W_SHIFT (16U)
24121#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
24122
24123#define I2S_RCR5_WNW_MASK (0x1F000000U)
24124#define I2S_RCR5_WNW_SHIFT (24U)
24127#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
24133#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
24134#define I2S_RDR_RDR_SHIFT (0U)
24137#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
24140/* The count of I2S_RDR */
24141#define I2S_RDR_COUNT (4U)
24142
24146#define I2S_RFR_RFP_MASK (0x3FU)
24147#define I2S_RFR_RFP_SHIFT (0U)
24150#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
24151
24152#define I2S_RFR_RCP_MASK (0x8000U)
24153#define I2S_RFR_RCP_SHIFT (15U)
24158#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
24159
24160#define I2S_RFR_WFP_MASK (0x3F0000U)
24161#define I2S_RFR_WFP_SHIFT (16U)
24164#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
24167/* The count of I2S_RFR */
24168#define I2S_RFR_COUNT (4U)
24169
24173#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
24174#define I2S_RMR_RWM_SHIFT (0U)
24179#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /* end of group I2S_Register_Masks */
24186
24187
24188/* I2S - Peripheral instance base addresses */
24190#define SAI1_BASE (0x40384000u)
24192#define SAI1 ((I2S_Type *)SAI1_BASE)
24194#define SAI2_BASE (0x40388000u)
24196#define SAI2 ((I2S_Type *)SAI2_BASE)
24198#define SAI3_BASE (0x4038C000u)
24200#define SAI3 ((I2S_Type *)SAI3_BASE)
24202#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }
24204#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }
24206#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }
24207#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }
24208 /* end of group I2S_Peripheral_Access_Layer */
24212
24213
24214/* ----------------------------------------------------------------------------
24215 -- IOMUXC Peripheral Access Layer
24216 ---------------------------------------------------------------------------- */
24217
24224typedef struct {
24225 uint8_t RESERVED_0[20];
24226 __IO uint32_t SW_MUX_CTL_PAD[124];
24227 __IO uint32_t SW_PAD_CTL_PAD[124];
24228 __IO uint32_t SELECT_INPUT[154];
24229} IOMUXC_Type;
24230
24231/* ----------------------------------------------------------------------------
24232 -- IOMUXC Register Masks
24233 ---------------------------------------------------------------------------- */
24234
24243#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)
24244#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
24256#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
24257
24258#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
24259#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
24264#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
24267/* The count of IOMUXC_SW_MUX_CTL_PAD */
24268#define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U)
24269
24273#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
24274#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
24279#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
24280
24281#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)
24282#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)
24293#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
24294
24295#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)
24296#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)
24303#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)
24304
24305#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)
24306#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)
24311#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
24312
24313#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)
24314#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)
24319#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)
24320
24321#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)
24322#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)
24327#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
24328
24329#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)
24330#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)
24337#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
24338
24339#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)
24340#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)
24345#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
24348/* The count of IOMUXC_SW_PAD_CTL_PAD */
24349#define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U)
24350
24354#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
24355#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
24363#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
24366/* The count of IOMUXC_SELECT_INPUT */
24367#define IOMUXC_SELECT_INPUT_COUNT (154U)
24368
24369 /* end of group IOMUXC_Register_Masks */
24373
24374
24375/* IOMUXC - Peripheral instance base addresses */
24377#define IOMUXC_BASE (0x401F8000u)
24379#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
24381#define IOMUXC_BASE_ADDRS { IOMUXC_BASE }
24383#define IOMUXC_BASE_PTRS { IOMUXC }
24384 /* end of group IOMUXC_Peripheral_Access_Layer */
24388
24389
24390/* ----------------------------------------------------------------------------
24391 -- IOMUXC_GPR Peripheral Access Layer
24392 ---------------------------------------------------------------------------- */
24393
24400typedef struct {
24401 uint32_t GPR0;
24402 __IO uint32_t GPR1;
24403 __IO uint32_t GPR2;
24404 __IO uint32_t GPR3;
24405 __IO uint32_t GPR4;
24406 __IO uint32_t GPR5;
24407 __IO uint32_t GPR6;
24408 __IO uint32_t GPR7;
24409 __IO uint32_t GPR8;
24410 uint32_t GPR9;
24411 __IO uint32_t GPR10;
24412 __IO uint32_t GPR11;
24413 __IO uint32_t GPR12;
24414 __IO uint32_t GPR13;
24415 __IO uint32_t GPR14;
24416 uint32_t GPR15;
24417 __IO uint32_t GPR16;
24418 __IO uint32_t GPR17;
24419 __IO uint32_t GPR18;
24420 __IO uint32_t GPR19;
24421 __IO uint32_t GPR20;
24422 __IO uint32_t GPR21;
24423 __IO uint32_t GPR22;
24424 __IO uint32_t GPR23;
24425 __IO uint32_t GPR24;
24426 __IO uint32_t GPR25;
24427} IOMUXC_GPR_Type;
24428
24429/* ----------------------------------------------------------------------------
24430 -- IOMUXC_GPR Register Masks
24431 ---------------------------------------------------------------------------- */
24432
24441#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)
24442#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)
24453#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
24454
24455#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)
24456#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)
24467#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
24468
24469#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)
24470#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)
24477#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
24478
24479#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)
24480#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)
24487#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
24488
24489#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)
24490#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)
24497#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
24498
24499#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)
24500#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U)
24505#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
24506
24507#define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK (0x2000U)
24508#define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_SHIFT (13U)
24513#define IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET_TX_CLK_SEL_MASK)
24514
24515#define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK (0x20000U)
24516#define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_SHIFT (17U)
24521#define IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
24522
24523#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)
24524#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)
24529#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
24530
24531#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)
24532#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)
24537#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
24538
24539#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)
24540#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)
24545#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
24546
24547#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)
24548#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)
24553#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
24554
24555#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)
24556#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)
24561#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
24567#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)
24568#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)
24573#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
24574
24575#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)
24576#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)
24581#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
24582
24583#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)
24584#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)
24843#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
24844
24845#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)
24846#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)
24851#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
24852
24853#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)
24854#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)
24859#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
24860
24861#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)
24862#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)
24867#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
24868
24869#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)
24870#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)
24875#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
24876
24877#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)
24878#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)
24883#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
24884
24885#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)
24886#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)
24891#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
24892
24893#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)
24894#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)
24899#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)
24905#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)
24906#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)
24911#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
24917#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)
24918#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)
24923#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
24924
24925#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)
24926#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)
24931#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
24932
24933#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)
24934#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)
24939#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
24940
24941#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)
24942#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)
24947#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
24948
24949#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)
24950#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)
24955#define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
24956
24957#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)
24958#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)
24963#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
24964
24965#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)
24966#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)
24971#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
24972
24973#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)
24974#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)
24979#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
24980
24981#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)
24982#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)
24987#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
24988
24989#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)
24990#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)
24995#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
24996
24997#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)
24998#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)
25003#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
25004
25005#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)
25006#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)
25011#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
25012
25013#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U)
25014#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U)
25019#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
25020
25021#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)
25022#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)
25027#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
25028
25029#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)
25030#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)
25035#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
25036
25037#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)
25038#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)
25043#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
25044
25045#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)
25046#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)
25051#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
25052
25053#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)
25054#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)
25059#define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
25060
25061#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)
25062#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)
25067#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
25068
25069#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)
25070#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)
25075#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
25076
25077#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)
25078#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)
25083#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
25084
25085#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)
25086#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)
25091#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
25092
25093#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)
25094#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)
25099#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
25100
25101#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)
25102#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)
25107#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
25108
25109#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)
25110#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)
25115#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
25116
25117#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U)
25118#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U)
25123#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
25129#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)
25130#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)
25135#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
25136
25137#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)
25138#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)
25143#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
25144
25145#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)
25146#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)
25151#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
25152
25153#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)
25154#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)
25159#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
25160
25161#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)
25162#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)
25170#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
25171
25172#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)
25173#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)
25181#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
25187#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)
25188#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)
25193#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
25194
25195#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)
25196#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)
25201#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
25202
25203#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)
25204#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)
25209#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
25210
25211#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)
25212#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)
25217#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
25218
25219#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)
25220#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)
25225#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
25226
25227#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)
25228#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)
25233#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
25234
25235#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)
25236#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)
25241#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
25242
25243#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)
25244#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)
25249#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
25250
25251#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
25252#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
25257#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
25258
25259#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
25260#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
25265#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
25266
25267#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
25268#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
25273#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
25274
25275#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
25276#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
25281#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
25282
25283#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)
25284#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)
25289#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
25290
25291#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)
25292#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)
25297#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
25298
25299#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)
25300#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)
25305#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
25306
25307#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)
25308#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)
25313#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
25314
25315#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)
25316#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)
25321#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
25322
25323#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)
25324#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)
25329#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
25330
25331#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)
25332#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)
25337#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
25338
25339#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)
25340#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)
25345#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
25346
25347#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)
25348#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)
25353#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
25354
25355#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)
25356#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)
25361#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
25362
25363#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)
25364#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)
25369#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
25370
25371#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)
25372#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)
25377#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
25378
25379#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)
25380#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)
25385#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
25386
25387#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)
25388#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)
25393#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
25394
25395#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)
25396#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)
25401#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
25402
25403#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)
25404#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)
25409#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
25410
25411#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)
25412#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)
25417#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
25418
25419#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)
25420#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)
25425#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
25426
25427#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)
25428#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)
25433#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
25434
25435#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)
25436#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)
25441#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
25447#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)
25448#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)
25453#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
25454
25455#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)
25456#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)
25461#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
25462
25463#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)
25464#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)
25469#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
25470
25471#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)
25472#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)
25477#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
25478
25479#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)
25480#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)
25485#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
25486
25487#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)
25488#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)
25493#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
25494
25495#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)
25496#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)
25501#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
25502
25503#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)
25504#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)
25509#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
25510
25511#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)
25512#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)
25517#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
25518
25519#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)
25520#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)
25525#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
25526
25527#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)
25528#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)
25533#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
25534
25535#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)
25536#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)
25541#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
25542
25543#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)
25544#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)
25549#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
25550
25551#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)
25552#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)
25557#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
25558
25559#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)
25560#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)
25565#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
25566
25567#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)
25568#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)
25573#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
25574
25575#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)
25576#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)
25581#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
25582
25583#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)
25584#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)
25589#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
25590
25591#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)
25592#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)
25597#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
25598
25599#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)
25600#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)
25605#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
25606
25607#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)
25608#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)
25613#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
25614
25615#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)
25616#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)
25621#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
25622
25623#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)
25624#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)
25629#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
25630
25631#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)
25632#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)
25637#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
25638
25639#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)
25640#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)
25645#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
25646
25647#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)
25648#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)
25653#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
25654
25655#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)
25656#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)
25661#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
25662
25663#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)
25664#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)
25669#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
25670
25671#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)
25672#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)
25677#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
25678
25679#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)
25680#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)
25685#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
25686
25687#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)
25688#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)
25693#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
25694
25695#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)
25696#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)
25701#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
25707#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)
25708#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)
25713#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
25714
25715#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)
25716#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)
25721#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
25722
25723#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)
25724#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)
25729#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
25730
25731#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)
25732#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)
25737#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
25738
25739#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)
25740#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)
25745#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
25746
25747#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)
25748#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)
25753#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
25754
25755#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)
25756#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)
25761#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
25762
25763#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)
25764#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)
25769#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
25770
25771#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)
25772#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)
25777#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
25778
25779#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)
25780#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)
25785#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
25786
25787#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)
25788#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)
25793#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
25794
25795#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)
25796#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)
25801#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
25802
25803#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)
25804#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)
25809#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
25810
25811#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)
25812#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)
25817#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
25818
25819#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)
25820#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)
25825#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
25826
25827#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)
25828#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)
25833#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
25834
25835#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)
25836#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)
25841#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
25842
25843#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)
25844#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)
25849#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
25850
25851#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)
25852#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)
25857#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
25858
25859#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)
25860#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)
25865#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
25866
25867#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)
25868#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)
25873#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
25874
25875#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)
25876#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)
25881#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
25882
25883#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)
25884#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)
25889#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
25890
25891#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)
25892#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)
25897#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
25898
25899#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)
25900#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)
25905#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
25906
25907#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)
25908#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)
25913#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
25914
25915#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)
25916#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)
25921#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
25922
25923#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)
25924#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)
25929#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
25930
25931#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)
25932#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)
25937#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
25938
25939#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)
25940#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)
25945#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
25946
25947#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)
25948#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)
25953#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
25954
25955#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)
25956#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)
25961#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
25967#define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)
25968#define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)
25973#define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
25974
25975#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)
25976#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)
25981#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
25982
25983#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)
25984#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)
25989#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
25990
25991#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)
25992#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)
25997#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
25998
25999#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)
26000#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)
26006#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
26007
26008#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U)
26009#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)
26010#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
26011
26012#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)
26013#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)
26018#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
26019
26020#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)
26021#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)
26026#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
26027
26028#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)
26029#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)
26034#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
26035
26036#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)
26037#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)
26042#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
26043
26044#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)
26045#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)
26050#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
26051
26052#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)
26053#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)
26058#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
26064#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)
26065#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)
26073#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
26074
26075#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)
26076#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)
26084#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
26085
26086#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)
26087#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)
26095#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
26096
26097#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)
26098#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)
26106#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
26107
26108#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)
26109#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)
26114#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)
26115
26116#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U)
26117#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U)
26122#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)
26123
26124#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U)
26125#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U)
26130#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)
26131
26132#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U)
26133#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U)
26138#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)
26139
26140#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U)
26141#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U)
26146#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)
26147
26148#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U)
26149#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U)
26154#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)
26160#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)
26161#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)
26166#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
26167
26168#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)
26169#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)
26174#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
26175
26176#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)
26177#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)
26182#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
26183
26184#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U)
26185#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U)
26190#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
26191
26192#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)
26193#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)
26198#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
26204#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)
26205#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)
26210#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
26211
26212#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)
26213#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)
26218#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
26219
26220#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)
26221#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)
26226#define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
26227
26228#define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)
26229#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)
26234#define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
26240#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)
26241#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)
26246#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
26247
26248#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)
26249#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)
26254#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
26255
26256#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)
26257#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)
26262#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
26263
26264#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)
26265#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)
26270#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
26271
26272#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)
26273#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)
26278#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
26279
26280#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)
26281#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)
26286#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
26287
26288#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)
26289#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)
26294#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
26295
26296#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)
26297#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)
26302#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
26303
26304#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)
26305#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)
26310#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
26311
26312#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)
26313#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)
26318#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
26319
26320#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)
26321#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)
26326#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
26327
26328#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)
26329#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)
26334#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
26340#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
26341#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
26346#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
26347
26348#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U)
26349#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U)
26350#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK)
26356#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU)
26357#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)
26360#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)
26366#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)
26367#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)
26372#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
26373
26374#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)
26375#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)
26378#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)
26384#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)
26385#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)
26390#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
26391
26392#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)
26393#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)
26396#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)
26402#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)
26403#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)
26408#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
26409
26410#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)
26411#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)
26414#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)
26420#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
26421#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
26426#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
26427
26428#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)
26429#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)
26432#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)
26438#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)
26439#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)
26444#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
26445
26446#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
26447#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)
26450#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)
26456#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)
26457#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)
26462#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
26463
26464#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)
26465#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)
26468#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
26474#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)
26475#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)
26480#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
26481
26482#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)
26483#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U)
26486#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)
26492#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)
26493#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)
26498#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
26499
26500#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)
26501#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)
26504#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK) /* end of group IOMUXC_GPR_Register_Masks */
26511
26512
26513/* IOMUXC_GPR - Peripheral instance base addresses */
26515#define IOMUXC_GPR_BASE (0x400AC000u)
26517#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
26519#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
26521#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
26522 /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
26526
26527
26528/* ----------------------------------------------------------------------------
26529 -- IOMUXC_SNVS Peripheral Access Layer
26530 ---------------------------------------------------------------------------- */
26531
26538typedef struct {
26539 __IO uint32_t SW_MUX_CTL_PAD_WAKEUP;
26540 __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ;
26541 __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ;
26542 __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE;
26543 __IO uint32_t SW_PAD_CTL_PAD_POR_B;
26544 __IO uint32_t SW_PAD_CTL_PAD_ONOFF;
26545 __IO uint32_t SW_PAD_CTL_PAD_WAKEUP;
26546 __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ;
26547 __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ;
26548} IOMUXC_SNVS_Type;
26549
26550/* ----------------------------------------------------------------------------
26551 -- IOMUXC_SNVS Register Masks
26552 ---------------------------------------------------------------------------- */
26553
26562#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)
26563#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)
26568#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)
26569
26570#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)
26571#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)
26576#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)
26582#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)
26583#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)
26588#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)
26589
26590#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)
26591#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)
26596#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)
26602#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)
26603#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)
26608#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)
26609
26610#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)
26611#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)
26616#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)
26622#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)
26623#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)
26628#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)
26629
26630#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)
26631#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)
26642#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
26643
26644#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)
26645#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)
26649#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)
26650
26651#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)
26652#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)
26657#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)
26658
26659#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)
26660#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)
26665#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)
26666
26667#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)
26668#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)
26673#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)
26674
26675#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)
26676#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)
26683#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)
26684
26685#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)
26686#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)
26691#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)
26697#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)
26698#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)
26703#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)
26704
26705#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)
26706#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)
26717#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)
26718
26719#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)
26720#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)
26724#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)
26725
26726#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)
26727#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)
26732#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)
26733
26734#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)
26735#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)
26740#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)
26741
26742#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)
26743#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)
26748#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)
26749
26750#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)
26751#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)
26758#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)
26759
26760#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)
26761#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)
26766#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)
26772#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)
26773#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)
26778#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)
26779
26780#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)
26781#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)
26792#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)
26793
26794#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)
26795#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)
26799#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)
26800
26801#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)
26802#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)
26807#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)
26808
26809#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)
26810#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)
26815#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)
26816
26817#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)
26818#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)
26823#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)
26824
26825#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)
26826#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)
26833#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)
26834
26835#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)
26836#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)
26841#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)
26847#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)
26848#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)
26853#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)
26854
26855#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)
26856#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)
26867#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)
26868
26869#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)
26870#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)
26874#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)
26875
26876#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)
26877#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)
26882#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)
26883
26884#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)
26885#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)
26890#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)
26891
26892#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)
26893#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)
26898#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)
26899
26900#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)
26901#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)
26908#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)
26909
26910#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)
26911#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)
26916#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)
26922#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)
26923#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)
26928#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)
26929
26930#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)
26931#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)
26942#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)
26943
26944#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)
26945#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)
26949#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)
26950
26951#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)
26952#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)
26957#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)
26958
26959#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)
26960#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)
26965#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)
26966
26967#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)
26968#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)
26973#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)
26974
26975#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)
26976#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)
26983#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)
26984
26985#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)
26986#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)
26991#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)
26997#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)
26998#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)
27003#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)
27004
27005#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)
27006#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)
27017#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)
27018
27019#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)
27020#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)
27024#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)
27025
27026#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)
27027#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)
27032#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)
27033
27034#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)
27035#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)
27040#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)
27041
27042#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)
27043#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)
27048#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)
27049
27050#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)
27051#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)
27058#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)
27059
27060#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)
27061#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)
27066#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK) /* end of group IOMUXC_SNVS_Register_Masks */
27073
27074
27075/* IOMUXC_SNVS - Peripheral instance base addresses */
27077#define IOMUXC_SNVS_BASE (0x400A8000u)
27079#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
27081#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }
27083#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }
27084 /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
27088
27089
27090/* ----------------------------------------------------------------------------
27091 -- IOMUXC_SNVS_GPR Peripheral Access Layer
27092 ---------------------------------------------------------------------------- */
27093
27100typedef struct {
27101 uint32_t GPR0;
27102 uint32_t GPR1;
27103 uint32_t GPR2;
27104 __IO uint32_t GPR3;
27105} IOMUXC_SNVS_GPR_Type;
27106
27107/* ----------------------------------------------------------------------------
27108 -- IOMUXC_SNVS_GPR Register Masks
27109 ---------------------------------------------------------------------------- */
27110
27119#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)
27120#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)
27125#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
27126
27127#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
27128#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
27131#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
27132
27133#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)
27134#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)
27141#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
27142
27143#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)
27144#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)
27149#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
27150
27151#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)
27152#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)
27157#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
27158
27159#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)
27160#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)
27165#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
27166
27167#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)
27168#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)
27173#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) /* end of group IOMUXC_SNVS_GPR_Register_Masks */
27180
27181
27182/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
27184#define IOMUXC_SNVS_GPR_BASE (0x400A4000u)
27186#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
27188#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }
27190#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }
27191 /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
27195
27196
27197/* ----------------------------------------------------------------------------
27198 -- KPP Peripheral Access Layer
27199 ---------------------------------------------------------------------------- */
27200
27207typedef struct {
27208 __IO uint16_t KPCR;
27209 __IO uint16_t KPSR;
27210 __IO uint16_t KDDR;
27211 __IO uint16_t KPDR;
27212} KPP_Type;
27213
27214/* ----------------------------------------------------------------------------
27215 -- KPP Register Masks
27216 ---------------------------------------------------------------------------- */
27217
27226#define KPP_KPCR_KRE_MASK (0xFFU)
27227#define KPP_KPCR_KRE_SHIFT (0U)
27232#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
27233
27234#define KPP_KPCR_KCO_MASK (0xFF00U)
27235#define KPP_KPCR_KCO_SHIFT (8U)
27240#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
27246#define KPP_KPSR_KPKD_MASK (0x1U)
27247#define KPP_KPSR_KPKD_SHIFT (0U)
27252#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
27253
27254#define KPP_KPSR_KPKR_MASK (0x2U)
27255#define KPP_KPSR_KPKR_SHIFT (1U)
27260#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
27261
27262#define KPP_KPSR_KDSC_MASK (0x4U)
27263#define KPP_KPSR_KDSC_SHIFT (2U)
27268#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
27269
27270#define KPP_KPSR_KRSS_MASK (0x8U)
27271#define KPP_KPSR_KRSS_SHIFT (3U)
27276#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
27277
27278#define KPP_KPSR_KDIE_MASK (0x100U)
27279#define KPP_KPSR_KDIE_SHIFT (8U)
27284#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
27285
27286#define KPP_KPSR_KRIE_MASK (0x200U)
27287#define KPP_KPSR_KRIE_SHIFT (9U)
27292#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
27298#define KPP_KDDR_KRDD_MASK (0xFFU)
27299#define KPP_KDDR_KRDD_SHIFT (0U)
27304#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
27305
27306#define KPP_KDDR_KCDD_MASK (0xFF00U)
27307#define KPP_KDDR_KCDD_SHIFT (8U)
27312#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
27318#define KPP_KPDR_KRD_MASK (0xFFU)
27319#define KPP_KPDR_KRD_SHIFT (0U)
27320#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
27321
27322#define KPP_KPDR_KCD_MASK (0xFF00U)
27323#define KPP_KPDR_KCD_SHIFT (8U)
27324#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) /* end of group KPP_Register_Masks */
27331
27332
27333/* KPP - Peripheral instance base addresses */
27335#define KPP_BASE (0x401FC000u)
27337#define KPP ((KPP_Type *)KPP_BASE)
27339#define KPP_BASE_ADDRS { KPP_BASE }
27341#define KPP_BASE_PTRS { KPP }
27343#define KPP_IRQS { KPP_IRQn }
27344 /* end of group KPP_Peripheral_Access_Layer */
27348
27349
27350/* ----------------------------------------------------------------------------
27351 -- LCDIF Peripheral Access Layer
27352 ---------------------------------------------------------------------------- */
27353
27360typedef struct {
27361 __IO uint32_t CTRL;
27362 __IO uint32_t CTRL_SET;
27363 __IO uint32_t CTRL_CLR;
27364 __IO uint32_t CTRL_TOG;
27365 __IO uint32_t CTRL1;
27366 __IO uint32_t CTRL1_SET;
27367 __IO uint32_t CTRL1_CLR;
27368 __IO uint32_t CTRL1_TOG;
27369 __IO uint32_t CTRL2;
27370 __IO uint32_t CTRL2_SET;
27371 __IO uint32_t CTRL2_CLR;
27372 __IO uint32_t CTRL2_TOG;
27373 __IO uint32_t TRANSFER_COUNT;
27374 uint8_t RESERVED_0[12];
27375 __IO uint32_t CUR_BUF;
27376 uint8_t RESERVED_1[12];
27377 __IO uint32_t NEXT_BUF;
27378 uint8_t RESERVED_2[28];
27379 __IO uint32_t VDCTRL0;
27380 __IO uint32_t VDCTRL0_SET;
27381 __IO uint32_t VDCTRL0_CLR;
27382 __IO uint32_t VDCTRL0_TOG;
27383 __IO uint32_t VDCTRL1;
27384 uint8_t RESERVED_3[12];
27385 __IO uint32_t VDCTRL2;
27386 uint8_t RESERVED_4[12];
27387 __IO uint32_t VDCTRL3;
27388 uint8_t RESERVED_5[12];
27389 __IO uint32_t VDCTRL4;
27390 uint8_t RESERVED_6[220];
27391 __IO uint32_t BM_ERROR_STAT;
27392 uint8_t RESERVED_7[12];
27393 __IO uint32_t CRC_STAT;
27394 uint8_t RESERVED_8[12];
27395 __I uint32_t STAT;
27396 uint8_t RESERVED_9[236];
27397 __IO uint32_t RGB_ADJUST;
27398 __IO uint32_t RGB_ADJUST_SET;
27399 __IO uint32_t RGB_ADJUST_CLR;
27400 __IO uint32_t RGB_ADJUST_TOG;
27401 uint8_t RESERVED_10[208];
27402 __IO uint32_t PIGEONCTRL0;
27403 __IO uint32_t PIGEONCTRL0_SET;
27404 __IO uint32_t PIGEONCTRL0_CLR;
27405 __IO uint32_t PIGEONCTRL0_TOG;
27406 __IO uint32_t PIGEONCTRL1;
27407 __IO uint32_t PIGEONCTRL1_SET;
27408 __IO uint32_t PIGEONCTRL1_CLR;
27409 __IO uint32_t PIGEONCTRL1_TOG;
27410 __IO uint32_t PIGEONCTRL2;
27411 __IO uint32_t PIGEONCTRL2_SET;
27412 __IO uint32_t PIGEONCTRL2_CLR;
27413 __IO uint32_t PIGEONCTRL2_TOG;
27414 uint8_t RESERVED_11[1104];
27415 struct { /* offset: 0x800, array step: 0x40 */
27416 __IO uint32_t PIGEON_0;
27417 uint8_t RESERVED_0[12];
27418 __IO uint32_t PIGEON_1;
27419 uint8_t RESERVED_1[12];
27420 __IO uint32_t PIGEON_2;
27421 uint8_t RESERVED_2[28];
27422 } PIGEON[12];
27423 __IO uint32_t LUT_CTRL;
27424 uint8_t RESERVED_12[12];
27425 __IO uint32_t LUT0_ADDR;
27426 uint8_t RESERVED_13[12];
27427 __IO uint32_t LUT0_DATA;
27428 uint8_t RESERVED_14[12];
27429 __IO uint32_t LUT1_ADDR;
27430 uint8_t RESERVED_15[12];
27431 __IO uint32_t LUT1_DATA;
27432} LCDIF_Type;
27433
27434/* ----------------------------------------------------------------------------
27435 -- LCDIF Register Masks
27436 ---------------------------------------------------------------------------- */
27437
27446#define LCDIF_CTRL_RUN_MASK (0x1U)
27447#define LCDIF_CTRL_RUN_SHIFT (0U)
27448#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
27449
27450#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)
27451#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)
27457#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
27458
27459#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)
27460#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)
27465#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
27466
27467#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)
27468#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)
27469#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
27470
27471#define LCDIF_CTRL_RSRVD0_MASK (0x10U)
27472#define LCDIF_CTRL_RSRVD0_SHIFT (4U)
27473#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
27474
27475#define LCDIF_CTRL_MASTER_MASK (0x20U)
27476#define LCDIF_CTRL_MASTER_SHIFT (5U)
27477#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
27478
27479#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
27480#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
27481#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
27482
27483#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)
27484#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)
27491#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
27492
27493#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)
27494#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)
27501#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
27502
27503#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)
27504#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)
27513#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
27514
27515#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)
27516#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)
27525#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
27526
27527#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)
27528#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)
27529#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
27530
27531#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)
27532#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)
27533#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
27534
27535#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)
27536#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)
27537#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
27538
27539#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)
27540#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)
27545#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
27546
27547#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U)
27548#define LCDIF_CTRL_CLKGATE_SHIFT (30U)
27549#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
27550
27551#define LCDIF_CTRL_SFTRST_MASK (0x80000000U)
27552#define LCDIF_CTRL_SFTRST_SHIFT (31U)
27553#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
27559#define LCDIF_CTRL_SET_RUN_MASK (0x1U)
27560#define LCDIF_CTRL_SET_RUN_SHIFT (0U)
27561#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
27562
27563#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)
27564#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)
27570#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
27571
27572#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)
27573#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)
27578#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
27579
27580#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)
27581#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)
27582#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
27583
27584#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)
27585#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)
27586#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
27587
27588#define LCDIF_CTRL_SET_MASTER_MASK (0x20U)
27589#define LCDIF_CTRL_SET_MASTER_SHIFT (5U)
27590#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
27591
27592#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
27593#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
27594#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
27595
27596#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)
27597#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)
27604#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
27605
27606#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)
27607#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)
27614#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
27615
27616#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)
27617#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)
27626#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
27627
27628#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)
27629#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)
27638#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
27639
27640#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)
27641#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)
27642#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
27643
27644#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)
27645#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)
27646#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
27647
27648#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)
27649#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)
27650#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
27651
27652#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)
27653#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)
27658#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
27659
27660#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)
27661#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)
27662#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
27663
27664#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)
27665#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U)
27666#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
27672#define LCDIF_CTRL_CLR_RUN_MASK (0x1U)
27673#define LCDIF_CTRL_CLR_RUN_SHIFT (0U)
27674#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
27675
27676#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)
27677#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)
27683#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
27684
27685#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)
27686#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)
27691#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
27692
27693#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)
27694#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)
27695#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
27696
27697#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)
27698#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)
27699#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
27700
27701#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U)
27702#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U)
27703#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
27704
27705#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
27706#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
27707#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
27708
27709#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)
27710#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)
27717#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
27718
27719#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)
27720#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)
27727#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
27728
27729#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)
27730#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)
27739#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
27740
27741#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)
27742#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)
27751#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
27752
27753#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)
27754#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)
27755#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
27756
27757#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)
27758#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)
27759#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
27760
27761#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)
27762#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)
27763#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
27764
27765#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)
27766#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)
27771#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
27772
27773#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)
27774#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)
27775#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
27776
27777#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)
27778#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)
27779#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
27785#define LCDIF_CTRL_TOG_RUN_MASK (0x1U)
27786#define LCDIF_CTRL_TOG_RUN_SHIFT (0U)
27787#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
27788
27789#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)
27790#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)
27796#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
27797
27798#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)
27799#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)
27804#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
27805
27806#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)
27807#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)
27808#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
27809
27810#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)
27811#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)
27812#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
27813
27814#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U)
27815#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U)
27816#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
27817
27818#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
27819#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
27820#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
27821
27822#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)
27823#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)
27830#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
27831
27832#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)
27833#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)
27840#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
27841
27842#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)
27843#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)
27852#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
27853
27854#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)
27855#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)
27864#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
27865
27866#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)
27867#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)
27868#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
27869
27870#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)
27871#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)
27872#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
27873
27874#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)
27875#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)
27876#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
27877
27878#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)
27879#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)
27884#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
27885
27886#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)
27887#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)
27888#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
27889
27890#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)
27891#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)
27892#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
27898#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U)
27899#define LCDIF_CTRL1_RSRVD0_SHIFT (3U)
27900#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
27901
27902#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)
27903#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)
27908#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
27909
27910#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)
27911#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)
27916#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
27917
27918#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)
27919#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)
27924#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
27925
27926#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)
27927#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)
27932#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
27933
27934#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
27935#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
27936#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
27937
27938#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
27939#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
27940#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
27941
27942#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)
27943#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)
27944#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
27945
27946#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)
27947#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)
27948#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
27949
27950#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)
27951#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)
27952#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
27953
27954#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
27955#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
27956#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
27957
27958#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)
27959#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)
27960#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
27961
27962#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
27963#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
27964#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
27965
27966#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)
27967#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)
27968#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
27969
27970#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
27971#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)
27972#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
27973
27974#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)
27975#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)
27980#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
27981
27982#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)
27983#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)
27984#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
27985
27986#define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)
27987#define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)
27988#define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
27989
27990#define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)
27991#define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)
27992#define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
27998#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)
27999#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)
28000#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
28001
28002#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)
28003#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)
28008#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
28009
28010#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)
28011#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
28016#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
28017
28018#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)
28019#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)
28024#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
28025
28026#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)
28027#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)
28032#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
28033
28034#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
28035#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
28036#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
28037
28038#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
28039#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
28040#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
28041
28042#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)
28043#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)
28044#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
28045
28046#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)
28047#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)
28048#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
28049
28050#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
28051#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
28052#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
28053
28054#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
28055#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
28056#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
28057
28058#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)
28059#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)
28060#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
28061
28062#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
28063#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
28064#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
28065
28066#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)
28067#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)
28068#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
28069
28070#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
28071#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
28072#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
28073
28074#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)
28075#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)
28080#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
28081
28082#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)
28083#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)
28084#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
28085
28086#define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)
28087#define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)
28088#define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
28089
28090#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)
28091#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)
28092#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
28098#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)
28099#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)
28100#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
28101
28102#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)
28103#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)
28108#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
28109
28110#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)
28111#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
28116#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
28117
28118#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)
28119#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)
28124#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
28125
28126#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)
28127#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)
28132#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
28133
28134#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
28135#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
28136#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
28137
28138#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
28139#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
28140#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
28141
28142#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)
28143#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)
28144#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
28145
28146#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)
28147#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)
28148#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
28149
28150#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
28151#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
28152#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
28153
28154#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
28155#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
28156#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
28157
28158#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)
28159#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)
28160#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
28161
28162#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
28163#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
28164#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
28165
28166#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)
28167#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)
28168#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
28169
28170#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
28171#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
28172#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
28173
28174#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)
28175#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)
28180#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
28181
28182#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)
28183#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)
28184#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
28185
28186#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)
28187#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)
28188#define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
28189
28190#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)
28191#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)
28192#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
28198#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)
28199#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)
28200#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
28201
28202#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)
28203#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)
28208#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
28209
28210#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)
28211#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
28216#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
28217
28218#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)
28219#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)
28224#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
28225
28226#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)
28227#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)
28232#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
28233
28234#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
28235#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
28236#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
28237
28238#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
28239#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
28240#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
28241
28242#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)
28243#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)
28244#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
28245
28246#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)
28247#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)
28248#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
28249
28250#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
28251#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
28252#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
28253
28254#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
28255#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
28256#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
28257
28258#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)
28259#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)
28260#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
28261
28262#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
28263#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
28264#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
28265
28266#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)
28267#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)
28268#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
28269
28270#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
28271#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
28272#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
28273
28274#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)
28275#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)
28280#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
28281
28282#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)
28283#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)
28284#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
28285
28286#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)
28287#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)
28288#define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
28289
28290#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)
28291#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)
28292#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
28298#define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU)
28299#define LCDIF_CTRL2_RSRVD0_SHIFT (0U)
28300#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
28301
28302#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)
28303#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)
28312#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
28313
28314#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U)
28315#define LCDIF_CTRL2_RSRVD3_SHIFT (15U)
28316#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
28317
28318#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)
28319#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)
28328#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
28329
28330#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U)
28331#define LCDIF_CTRL2_RSRVD4_SHIFT (19U)
28332#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
28333
28334#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)
28335#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)
28336#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
28337
28338#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)
28339#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)
28347#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
28348
28349#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)
28350#define LCDIF_CTRL2_RSRVD5_SHIFT (24U)
28351#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
28357#define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)
28358#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)
28359#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
28360
28361#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)
28362#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)
28371#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
28372
28373#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)
28374#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)
28375#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
28376
28377#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)
28378#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)
28387#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
28388
28389#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)
28390#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)
28391#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
28392
28393#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)
28394#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)
28395#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
28396
28397#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)
28398#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)
28406#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
28407
28408#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)
28409#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)
28410#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
28416#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)
28417#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)
28418#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
28419
28420#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)
28421#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)
28430#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
28431
28432#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)
28433#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)
28434#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
28435
28436#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)
28437#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)
28446#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
28447
28448#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)
28449#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)
28450#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
28451
28452#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)
28453#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)
28454#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
28455
28456#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)
28457#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)
28465#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
28466
28467#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)
28468#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)
28469#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
28475#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)
28476#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)
28477#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
28478
28479#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)
28480#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)
28489#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
28490
28491#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)
28492#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)
28493#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
28494
28495#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)
28496#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)
28505#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
28506
28507#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)
28508#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)
28509#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
28510
28511#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)
28512#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)
28513#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
28514
28515#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)
28516#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)
28524#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
28525
28526#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)
28527#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)
28528#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
28534#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)
28535#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)
28536#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
28537
28538#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)
28539#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)
28540#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
28546#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)
28547#define LCDIF_CUR_BUF_ADDR_SHIFT (0U)
28548#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
28554#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
28555#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U)
28556#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
28562#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
28563#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)
28564#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
28565
28566#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)
28567#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)
28568#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
28569
28570#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)
28571#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)
28572#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
28573
28574#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28575#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28576#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
28577
28578#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)
28579#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)
28580#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
28581
28582#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)
28583#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)
28584#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
28585
28586#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)
28587#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)
28588#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
28589
28590#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)
28591#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)
28592#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
28593
28594#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)
28595#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)
28596#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
28597
28598#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)
28599#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)
28600#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
28601
28602#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)
28603#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)
28604#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
28605
28606#define LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U)
28607#define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U)
28608#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
28614#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
28615#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
28616#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
28617
28618#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)
28619#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)
28620#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
28621
28622#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)
28623#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)
28624#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
28625
28626#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28627#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28628#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
28629
28630#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
28631#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
28632#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
28633
28634#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)
28635#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)
28636#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
28637
28638#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)
28639#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)
28640#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
28641
28642#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)
28643#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)
28644#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
28645
28646#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)
28647#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)
28648#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
28649
28650#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)
28651#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)
28652#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
28653
28654#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)
28655#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)
28656#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
28657
28658#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U)
28659#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U)
28660#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
28666#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
28667#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
28668#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
28669
28670#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)
28671#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)
28672#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
28673
28674#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)
28675#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)
28676#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
28677
28678#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28679#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28680#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
28681
28682#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
28683#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
28684#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
28685
28686#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)
28687#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)
28688#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
28689
28690#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)
28691#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)
28692#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
28693
28694#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)
28695#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)
28696#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
28697
28698#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)
28699#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)
28700#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
28701
28702#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)
28703#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)
28704#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
28705
28706#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)
28707#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)
28708#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
28709
28710#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U)
28711#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U)
28712#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
28718#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
28719#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
28720#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
28721
28722#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)
28723#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)
28724#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
28725
28726#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)
28727#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)
28728#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
28729
28730#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
28731#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
28732#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
28733
28734#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
28735#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
28736#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
28737
28738#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)
28739#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)
28740#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
28741
28742#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)
28743#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)
28744#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
28745
28746#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)
28747#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)
28748#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
28749
28750#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)
28751#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)
28752#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
28753
28754#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)
28755#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)
28756#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
28757
28758#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)
28759#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)
28760#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
28761
28762#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U)
28763#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U)
28764#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
28770#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)
28771#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)
28772#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
28778#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)
28779#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)
28780#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
28781
28782#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)
28783#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)
28784#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
28790#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)
28791#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)
28792#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
28793
28794#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)
28795#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)
28796#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
28797
28798#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)
28799#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)
28800#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
28801
28802#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)
28803#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)
28804#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
28805
28806#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)
28807#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)
28808#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
28814#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
28815#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
28816#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
28817
28818#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)
28819#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)
28820#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
28821
28822#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)
28823#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)
28824#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
28825
28826#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)
28827#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)
28828#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
28834#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)
28835#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)
28836#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
28842#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)
28843#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)
28844#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
28850#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)
28851#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)
28852#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
28853
28854#define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)
28855#define LCDIF_STAT_RSRVD0_SHIFT (9U)
28856#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
28857
28858#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)
28859#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)
28860#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
28861
28862#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)
28863#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)
28864#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
28865
28866#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)
28867#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)
28868#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
28869
28870#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)
28871#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U)
28872#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
28873
28874#define LCDIF_STAT_PRESENT_MASK (0x80000000U)
28875#define LCDIF_STAT_PRESENT_SHIFT (31U)
28876#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
28882#define LCDIF_RGB_ADJUST_PIXEL_MASK (0xFFFFFFU)
28883#define LCDIF_RGB_ADJUST_PIXEL_SHIFT (0U)
28884#define LCDIF_RGB_ADJUST_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_PIXEL_MASK)
28885
28886#define LCDIF_RGB_ADJUST_RGB_ADJ_MODE_MASK (0xC0000000U)
28887#define LCDIF_RGB_ADJUST_RGB_ADJ_MODE_SHIFT (30U)
28894#define LCDIF_RGB_ADJUST_RGB_ADJ_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_RGB_ADJ_MODE_MASK)
28900#define LCDIF_RGB_ADJUST_SET_PIXEL_MASK (0xFFFFFFU)
28901#define LCDIF_RGB_ADJUST_SET_PIXEL_SHIFT (0U)
28902#define LCDIF_RGB_ADJUST_SET_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_SET_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_SET_PIXEL_MASK)
28903
28904#define LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_MASK (0xC0000000U)
28905#define LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_SHIFT (30U)
28912#define LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_SET_RGB_ADJ_MODE_MASK)
28918#define LCDIF_RGB_ADJUST_CLR_PIXEL_MASK (0xFFFFFFU)
28919#define LCDIF_RGB_ADJUST_CLR_PIXEL_SHIFT (0U)
28920#define LCDIF_RGB_ADJUST_CLR_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_CLR_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_CLR_PIXEL_MASK)
28921
28922#define LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_MASK (0xC0000000U)
28923#define LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_SHIFT (30U)
28930#define LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_CLR_RGB_ADJ_MODE_MASK)
28936#define LCDIF_RGB_ADJUST_TOG_PIXEL_MASK (0xFFFFFFU)
28937#define LCDIF_RGB_ADJUST_TOG_PIXEL_SHIFT (0U)
28938#define LCDIF_RGB_ADJUST_TOG_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_TOG_PIXEL_SHIFT)) & LCDIF_RGB_ADJUST_TOG_PIXEL_MASK)
28939
28940#define LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_MASK (0xC0000000U)
28941#define LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_SHIFT (30U)
28948#define LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_SHIFT)) & LCDIF_RGB_ADJUST_TOG_RGB_ADJ_MODE_MASK)
28954#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)
28955#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)
28956#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
28957
28958#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)
28959#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)
28960#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
28966#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)
28967#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)
28968#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
28969
28970#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)
28971#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)
28972#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
28978#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)
28979#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)
28980#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
28981
28982#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)
28983#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)
28984#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
28990#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)
28991#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)
28992#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
28993
28994#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)
28995#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)
28996#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
29002#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)
29003#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
29004#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
29005
29006#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
29007#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
29008#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
29014#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
29015#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
29016#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
29017
29018#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
29019#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
29020#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
29026#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
29027#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
29028#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
29029
29030#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
29031#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
29032#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
29038#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
29039#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
29040#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
29041
29042#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
29043#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
29044#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
29050#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)
29051#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)
29052#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
29053
29054#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)
29055#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)
29056#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
29062#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
29063#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
29064#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
29065
29066#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
29067#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
29068#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
29074#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
29075#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
29076#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
29077
29078#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
29079#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
29080#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
29086#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
29087#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
29088#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
29089
29090#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
29091#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
29092#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
29098#define LCDIF_PIGEON_0_EN_MASK (0x1U)
29099#define LCDIF_PIGEON_0_EN_SHIFT (0U)
29100#define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
29101
29102#define LCDIF_PIGEON_0_POL_MASK (0x2U)
29103#define LCDIF_PIGEON_0_POL_SHIFT (1U)
29108#define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
29109
29110#define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU)
29111#define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U)
29118#define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
29119
29120#define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U)
29121#define LCDIF_PIGEON_0_OFFSET_SHIFT (4U)
29122#define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
29123
29124#define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)
29125#define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)
29136#define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
29137
29138#define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)
29139#define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)
29140#define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
29141
29142#define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)
29143#define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)
29154#define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
29157/* The count of LCDIF_PIGEON_0 */
29158#define LCDIF_PIGEON_0_COUNT (12U)
29159
29163#define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)
29164#define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U)
29168#define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
29169
29170#define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)
29171#define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)
29175#define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
29178/* The count of LCDIF_PIGEON_1 */
29179#define LCDIF_PIGEON_1_COUNT (12U)
29180
29184#define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)
29185#define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)
29192#define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
29193
29194#define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)
29195#define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)
29199#define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
29200
29201#define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)
29202#define LCDIF_PIGEON_2_RSVD_SHIFT (9U)
29203#define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
29206/* The count of LCDIF_PIGEON_2 */
29207#define LCDIF_PIGEON_2_COUNT (12U)
29208
29212#define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)
29213#define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)
29214#define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
29220#define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)
29221#define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U)
29222#define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
29228#define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)
29229#define LCDIF_LUT0_DATA_DATA_SHIFT (0U)
29230#define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
29236#define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)
29237#define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U)
29238#define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
29244#define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)
29245#define LCDIF_LUT1_DATA_DATA_SHIFT (0U)
29246#define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) /* end of group LCDIF_Register_Masks */
29253
29254
29255/* LCDIF - Peripheral instance base addresses */
29257#define LCDIF_BASE (0x402B8000u)
29259#define LCDIF ((LCDIF_Type *)LCDIF_BASE)
29261#define LCDIF_BASE_ADDRS { LCDIF_BASE }
29263#define LCDIF_BASE_PTRS { LCDIF }
29265#define LCDIF_IRQ0_IRQS { LCDIF_IRQn }
29266 /* end of group LCDIF_Peripheral_Access_Layer */
29270
29271
29272/* ----------------------------------------------------------------------------
29273 -- LPI2C Peripheral Access Layer
29274 ---------------------------------------------------------------------------- */
29275
29282typedef struct {
29283 __I uint32_t VERID;
29284 __I uint32_t PARAM;
29285 uint8_t RESERVED_0[8];
29286 __IO uint32_t MCR;
29287 __IO uint32_t MSR;
29288 __IO uint32_t MIER;
29289 __IO uint32_t MDER;
29290 __IO uint32_t MCFGR0;
29291 __IO uint32_t MCFGR1;
29292 __IO uint32_t MCFGR2;
29293 __IO uint32_t MCFGR3;
29294 uint8_t RESERVED_1[16];
29295 __IO uint32_t MDMR;
29296 uint8_t RESERVED_2[4];
29297 __IO uint32_t MCCR0;
29298 uint8_t RESERVED_3[4];
29299 __IO uint32_t MCCR1;
29300 uint8_t RESERVED_4[4];
29301 __IO uint32_t MFCR;
29302 __I uint32_t MFSR;
29303 __O uint32_t MTDR;
29304 uint8_t RESERVED_5[12];
29305 __I uint32_t MRDR;
29306 uint8_t RESERVED_6[156];
29307 __IO uint32_t SCR;
29308 __IO uint32_t SSR;
29309 __IO uint32_t SIER;
29310 __IO uint32_t SDER;
29311 uint8_t RESERVED_7[4];
29312 __IO uint32_t SCFGR1;
29313 __IO uint32_t SCFGR2;
29314 uint8_t RESERVED_8[20];
29315 __IO uint32_t SAMR;
29316 uint8_t RESERVED_9[12];
29317 __I uint32_t SASR;
29318 __IO uint32_t STAR;
29319 uint8_t RESERVED_10[8];
29320 __O uint32_t STDR;
29321 uint8_t RESERVED_11[12];
29322 __I uint32_t SRDR;
29323} LPI2C_Type;
29324
29325/* ----------------------------------------------------------------------------
29326 -- LPI2C Register Masks
29327 ---------------------------------------------------------------------------- */
29328
29337#define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
29338#define LPI2C_VERID_FEATURE_SHIFT (0U)
29343#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
29344
29345#define LPI2C_VERID_MINOR_MASK (0xFF0000U)
29346#define LPI2C_VERID_MINOR_SHIFT (16U)
29349#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
29350
29351#define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
29352#define LPI2C_VERID_MAJOR_SHIFT (24U)
29355#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
29361#define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
29362#define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
29365#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
29366
29367#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
29368#define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
29371#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
29377#define LPI2C_MCR_MEN_MASK (0x1U)
29378#define LPI2C_MCR_MEN_SHIFT (0U)
29383#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
29384
29385#define LPI2C_MCR_RST_MASK (0x2U)
29386#define LPI2C_MCR_RST_SHIFT (1U)
29391#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
29392
29393#define LPI2C_MCR_DOZEN_MASK (0x4U)
29394#define LPI2C_MCR_DOZEN_SHIFT (2U)
29399#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
29400
29401#define LPI2C_MCR_DBGEN_MASK (0x8U)
29402#define LPI2C_MCR_DBGEN_SHIFT (3U)
29407#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
29408
29409#define LPI2C_MCR_RTF_MASK (0x100U)
29410#define LPI2C_MCR_RTF_SHIFT (8U)
29415#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
29416
29417#define LPI2C_MCR_RRF_MASK (0x200U)
29418#define LPI2C_MCR_RRF_SHIFT (9U)
29423#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
29429#define LPI2C_MSR_TDF_MASK (0x1U)
29430#define LPI2C_MSR_TDF_SHIFT (0U)
29435#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
29436
29437#define LPI2C_MSR_RDF_MASK (0x2U)
29438#define LPI2C_MSR_RDF_SHIFT (1U)
29443#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
29444
29445#define LPI2C_MSR_EPF_MASK (0x100U)
29446#define LPI2C_MSR_EPF_SHIFT (8U)
29451#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
29452
29453#define LPI2C_MSR_SDF_MASK (0x200U)
29454#define LPI2C_MSR_SDF_SHIFT (9U)
29459#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
29460
29461#define LPI2C_MSR_NDF_MASK (0x400U)
29462#define LPI2C_MSR_NDF_SHIFT (10U)
29467#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
29468
29469#define LPI2C_MSR_ALF_MASK (0x800U)
29470#define LPI2C_MSR_ALF_SHIFT (11U)
29475#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
29476
29477#define LPI2C_MSR_FEF_MASK (0x1000U)
29478#define LPI2C_MSR_FEF_SHIFT (12U)
29483#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
29484
29485#define LPI2C_MSR_PLTF_MASK (0x2000U)
29486#define LPI2C_MSR_PLTF_SHIFT (13U)
29491#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
29492
29493#define LPI2C_MSR_DMF_MASK (0x4000U)
29494#define LPI2C_MSR_DMF_SHIFT (14U)
29499#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
29500
29501#define LPI2C_MSR_MBF_MASK (0x1000000U)
29502#define LPI2C_MSR_MBF_SHIFT (24U)
29507#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
29508
29509#define LPI2C_MSR_BBF_MASK (0x2000000U)
29510#define LPI2C_MSR_BBF_SHIFT (25U)
29515#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
29521#define LPI2C_MIER_TDIE_MASK (0x1U)
29522#define LPI2C_MIER_TDIE_SHIFT (0U)
29527#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
29528
29529#define LPI2C_MIER_RDIE_MASK (0x2U)
29530#define LPI2C_MIER_RDIE_SHIFT (1U)
29535#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
29536
29537#define LPI2C_MIER_EPIE_MASK (0x100U)
29538#define LPI2C_MIER_EPIE_SHIFT (8U)
29543#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
29544
29545#define LPI2C_MIER_SDIE_MASK (0x200U)
29546#define LPI2C_MIER_SDIE_SHIFT (9U)
29551#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
29552
29553#define LPI2C_MIER_NDIE_MASK (0x400U)
29554#define LPI2C_MIER_NDIE_SHIFT (10U)
29559#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
29560
29561#define LPI2C_MIER_ALIE_MASK (0x800U)
29562#define LPI2C_MIER_ALIE_SHIFT (11U)
29567#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
29568
29569#define LPI2C_MIER_FEIE_MASK (0x1000U)
29570#define LPI2C_MIER_FEIE_SHIFT (12U)
29575#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
29576
29577#define LPI2C_MIER_PLTIE_MASK (0x2000U)
29578#define LPI2C_MIER_PLTIE_SHIFT (13U)
29583#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
29584
29585#define LPI2C_MIER_DMIE_MASK (0x4000U)
29586#define LPI2C_MIER_DMIE_SHIFT (14U)
29591#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
29597#define LPI2C_MDER_TDDE_MASK (0x1U)
29598#define LPI2C_MDER_TDDE_SHIFT (0U)
29603#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
29604
29605#define LPI2C_MDER_RDDE_MASK (0x2U)
29606#define LPI2C_MDER_RDDE_SHIFT (1U)
29611#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
29617#define LPI2C_MCFGR0_HREN_MASK (0x1U)
29618#define LPI2C_MCFGR0_HREN_SHIFT (0U)
29623#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
29624
29625#define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
29626#define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
29631#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
29632
29633#define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
29634#define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
29639#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
29640
29641#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
29642#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
29647#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
29648
29649#define LPI2C_MCFGR0_RDMO_MASK (0x200U)
29650#define LPI2C_MCFGR0_RDMO_SHIFT (9U)
29655#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
29661#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
29662#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
29673#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
29674
29675#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
29676#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
29681#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
29682
29683#define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
29684#define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
29689#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
29690
29691#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
29692#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
29697#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
29698
29699#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
29700#define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
29711#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
29712
29713#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
29714#define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
29725#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
29731#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
29732#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
29735#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
29736
29737#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
29738#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
29741#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
29742
29743#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
29744#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
29747#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
29753#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
29754#define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
29757#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
29763#define LPI2C_MDMR_MATCH0_MASK (0xFFU)
29764#define LPI2C_MDMR_MATCH0_SHIFT (0U)
29767#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
29768
29769#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
29770#define LPI2C_MDMR_MATCH1_SHIFT (16U)
29773#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
29779#define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
29780#define LPI2C_MCCR0_CLKLO_SHIFT (0U)
29783#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
29784
29785#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
29786#define LPI2C_MCCR0_CLKHI_SHIFT (8U)
29789#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
29790
29791#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
29792#define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
29795#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
29796
29797#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
29798#define LPI2C_MCCR0_DATAVD_SHIFT (24U)
29801#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
29807#define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
29808#define LPI2C_MCCR1_CLKLO_SHIFT (0U)
29811#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
29812
29813#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
29814#define LPI2C_MCCR1_CLKHI_SHIFT (8U)
29817#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
29818
29819#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
29820#define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
29823#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
29824
29825#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
29826#define LPI2C_MCCR1_DATAVD_SHIFT (24U)
29829#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
29835#define LPI2C_MFCR_TXWATER_MASK (0x3U)
29836#define LPI2C_MFCR_TXWATER_SHIFT (0U)
29839#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
29840
29841#define LPI2C_MFCR_RXWATER_MASK (0x30000U)
29842#define LPI2C_MFCR_RXWATER_SHIFT (16U)
29845#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
29851#define LPI2C_MFSR_TXCOUNT_MASK (0x7U)
29852#define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
29855#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
29856
29857#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U)
29858#define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
29861#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
29867#define LPI2C_MTDR_DATA_MASK (0xFFU)
29868#define LPI2C_MTDR_DATA_SHIFT (0U)
29871#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
29872
29873#define LPI2C_MTDR_CMD_MASK (0x700U)
29874#define LPI2C_MTDR_CMD_SHIFT (8U)
29885#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
29891#define LPI2C_MRDR_DATA_MASK (0xFFU)
29892#define LPI2C_MRDR_DATA_SHIFT (0U)
29895#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
29896
29897#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
29898#define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
29903#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
29909#define LPI2C_SCR_SEN_MASK (0x1U)
29910#define LPI2C_SCR_SEN_SHIFT (0U)
29915#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
29916
29917#define LPI2C_SCR_RST_MASK (0x2U)
29918#define LPI2C_SCR_RST_SHIFT (1U)
29923#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
29924
29925#define LPI2C_SCR_FILTEN_MASK (0x10U)
29926#define LPI2C_SCR_FILTEN_SHIFT (4U)
29931#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
29932
29933#define LPI2C_SCR_FILTDZ_MASK (0x20U)
29934#define LPI2C_SCR_FILTDZ_SHIFT (5U)
29939#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
29940
29941#define LPI2C_SCR_RTF_MASK (0x100U)
29942#define LPI2C_SCR_RTF_SHIFT (8U)
29947#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
29948
29949#define LPI2C_SCR_RRF_MASK (0x200U)
29950#define LPI2C_SCR_RRF_SHIFT (9U)
29955#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
29961#define LPI2C_SSR_TDF_MASK (0x1U)
29962#define LPI2C_SSR_TDF_SHIFT (0U)
29967#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
29968
29969#define LPI2C_SSR_RDF_MASK (0x2U)
29970#define LPI2C_SSR_RDF_SHIFT (1U)
29975#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
29976
29977#define LPI2C_SSR_AVF_MASK (0x4U)
29978#define LPI2C_SSR_AVF_SHIFT (2U)
29983#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
29984
29985#define LPI2C_SSR_TAF_MASK (0x8U)
29986#define LPI2C_SSR_TAF_SHIFT (3U)
29991#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
29992
29993#define LPI2C_SSR_RSF_MASK (0x100U)
29994#define LPI2C_SSR_RSF_SHIFT (8U)
29999#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
30000
30001#define LPI2C_SSR_SDF_MASK (0x200U)
30002#define LPI2C_SSR_SDF_SHIFT (9U)
30007#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
30008
30009#define LPI2C_SSR_BEF_MASK (0x400U)
30010#define LPI2C_SSR_BEF_SHIFT (10U)
30015#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
30016
30017#define LPI2C_SSR_FEF_MASK (0x800U)
30018#define LPI2C_SSR_FEF_SHIFT (11U)
30023#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
30024
30025#define LPI2C_SSR_AM0F_MASK (0x1000U)
30026#define LPI2C_SSR_AM0F_SHIFT (12U)
30031#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
30032
30033#define LPI2C_SSR_AM1F_MASK (0x2000U)
30034#define LPI2C_SSR_AM1F_SHIFT (13U)
30039#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
30040
30041#define LPI2C_SSR_GCF_MASK (0x4000U)
30042#define LPI2C_SSR_GCF_SHIFT (14U)
30047#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
30048
30049#define LPI2C_SSR_SARF_MASK (0x8000U)
30050#define LPI2C_SSR_SARF_SHIFT (15U)
30055#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
30056
30057#define LPI2C_SSR_SBF_MASK (0x1000000U)
30058#define LPI2C_SSR_SBF_SHIFT (24U)
30063#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
30064
30065#define LPI2C_SSR_BBF_MASK (0x2000000U)
30066#define LPI2C_SSR_BBF_SHIFT (25U)
30071#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
30077#define LPI2C_SIER_TDIE_MASK (0x1U)
30078#define LPI2C_SIER_TDIE_SHIFT (0U)
30083#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
30084
30085#define LPI2C_SIER_RDIE_MASK (0x2U)
30086#define LPI2C_SIER_RDIE_SHIFT (1U)
30091#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
30092
30093#define LPI2C_SIER_AVIE_MASK (0x4U)
30094#define LPI2C_SIER_AVIE_SHIFT (2U)
30099#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
30100
30101#define LPI2C_SIER_TAIE_MASK (0x8U)
30102#define LPI2C_SIER_TAIE_SHIFT (3U)
30107#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
30108
30109#define LPI2C_SIER_RSIE_MASK (0x100U)
30110#define LPI2C_SIER_RSIE_SHIFT (8U)
30115#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
30116
30117#define LPI2C_SIER_SDIE_MASK (0x200U)
30118#define LPI2C_SIER_SDIE_SHIFT (9U)
30123#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
30124
30125#define LPI2C_SIER_BEIE_MASK (0x400U)
30126#define LPI2C_SIER_BEIE_SHIFT (10U)
30131#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
30132
30133#define LPI2C_SIER_FEIE_MASK (0x800U)
30134#define LPI2C_SIER_FEIE_SHIFT (11U)
30139#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
30140
30141#define LPI2C_SIER_AM0IE_MASK (0x1000U)
30142#define LPI2C_SIER_AM0IE_SHIFT (12U)
30147#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
30148
30149#define LPI2C_SIER_AM1F_MASK (0x2000U)
30150#define LPI2C_SIER_AM1F_SHIFT (13U)
30155#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
30156
30157#define LPI2C_SIER_GCIE_MASK (0x4000U)
30158#define LPI2C_SIER_GCIE_SHIFT (14U)
30163#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
30164
30165#define LPI2C_SIER_SARIE_MASK (0x8000U)
30166#define LPI2C_SIER_SARIE_SHIFT (15U)
30171#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
30177#define LPI2C_SDER_TDDE_MASK (0x1U)
30178#define LPI2C_SDER_TDDE_SHIFT (0U)
30183#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
30184
30185#define LPI2C_SDER_RDDE_MASK (0x2U)
30186#define LPI2C_SDER_RDDE_SHIFT (1U)
30191#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
30192
30193#define LPI2C_SDER_AVDE_MASK (0x4U)
30194#define LPI2C_SDER_AVDE_SHIFT (2U)
30199#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
30205#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
30206#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
30211#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
30212
30213#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
30214#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
30219#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
30220
30221#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
30222#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
30227#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
30228
30229#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
30230#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
30235#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
30236
30237#define LPI2C_SCFGR1_GCEN_MASK (0x100U)
30238#define LPI2C_SCFGR1_GCEN_SHIFT (8U)
30243#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
30244
30245#define LPI2C_SCFGR1_SAEN_MASK (0x200U)
30246#define LPI2C_SCFGR1_SAEN_SHIFT (9U)
30251#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
30252
30253#define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
30254#define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
30259#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
30260
30261#define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
30262#define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
30269#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
30270
30271#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
30272#define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
30277#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
30278
30279#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
30280#define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
30285#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
30286
30287#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
30288#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
30299#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
30305#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
30306#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
30309#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
30310
30311#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
30312#define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
30315#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
30316
30317#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
30318#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
30321#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
30322
30323#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
30324#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
30327#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
30333#define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
30334#define LPI2C_SAMR_ADDR0_SHIFT (1U)
30337#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
30338
30339#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
30340#define LPI2C_SAMR_ADDR1_SHIFT (17U)
30343#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
30349#define LPI2C_SASR_RADDR_MASK (0x7FFU)
30350#define LPI2C_SASR_RADDR_SHIFT (0U)
30353#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
30354
30355#define LPI2C_SASR_ANV_MASK (0x4000U)
30356#define LPI2C_SASR_ANV_SHIFT (14U)
30361#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
30367#define LPI2C_STAR_TXNACK_MASK (0x1U)
30368#define LPI2C_STAR_TXNACK_SHIFT (0U)
30373#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
30379#define LPI2C_STDR_DATA_MASK (0xFFU)
30380#define LPI2C_STDR_DATA_SHIFT (0U)
30383#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
30389#define LPI2C_SRDR_DATA_MASK (0xFFU)
30390#define LPI2C_SRDR_DATA_SHIFT (0U)
30393#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
30394
30395#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
30396#define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
30401#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
30402
30403#define LPI2C_SRDR_SOF_MASK (0x8000U)
30404#define LPI2C_SRDR_SOF_SHIFT (15U)
30409#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) /* end of group LPI2C_Register_Masks */
30416
30417
30418/* LPI2C - Peripheral instance base addresses */
30420#define LPI2C1_BASE (0x403F0000u)
30422#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
30424#define LPI2C2_BASE (0x403F4000u)
30426#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
30428#define LPI2C3_BASE (0x403F8000u)
30430#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE)
30432#define LPI2C4_BASE (0x403FC000u)
30434#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE)
30436#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }
30438#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }
30440#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }
30441 /* end of group LPI2C_Peripheral_Access_Layer */
30445
30446
30447/* ----------------------------------------------------------------------------
30448 -- LPSPI Peripheral Access Layer
30449 ---------------------------------------------------------------------------- */
30450
30457typedef struct {
30458 __I uint32_t VERID;
30459 __I uint32_t PARAM;
30460 uint8_t RESERVED_0[8];
30461 __IO uint32_t CR;
30462 __IO uint32_t SR;
30463 __IO uint32_t IER;
30464 __IO uint32_t DER;
30465 __IO uint32_t CFGR0;
30466 __IO uint32_t CFGR1;
30467 uint8_t RESERVED_1[8];
30468 __IO uint32_t DMR0;
30469 __IO uint32_t DMR1;
30470 uint8_t RESERVED_2[8];
30471 __IO uint32_t CCR;
30472 uint8_t RESERVED_3[20];
30473 __IO uint32_t FCR;
30474 __I uint32_t FSR;
30475 __IO uint32_t TCR;
30476 __O uint32_t TDR;
30477 uint8_t RESERVED_4[8];
30478 __I uint32_t RSR;
30479 __I uint32_t RDR;
30480} LPSPI_Type;
30481
30482/* ----------------------------------------------------------------------------
30483 -- LPSPI Register Masks
30484 ---------------------------------------------------------------------------- */
30485
30494#define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
30495#define LPSPI_VERID_FEATURE_SHIFT (0U)
30499#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
30500
30501#define LPSPI_VERID_MINOR_MASK (0xFF0000U)
30502#define LPSPI_VERID_MINOR_SHIFT (16U)
30505#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
30506
30507#define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
30508#define LPSPI_VERID_MAJOR_SHIFT (24U)
30511#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
30517#define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
30518#define LPSPI_PARAM_TXFIFO_SHIFT (0U)
30521#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
30522
30523#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
30524#define LPSPI_PARAM_RXFIFO_SHIFT (8U)
30527#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
30533#define LPSPI_CR_MEN_MASK (0x1U)
30534#define LPSPI_CR_MEN_SHIFT (0U)
30539#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
30540
30541#define LPSPI_CR_RST_MASK (0x2U)
30542#define LPSPI_CR_RST_SHIFT (1U)
30547#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
30548
30549#define LPSPI_CR_DOZEN_MASK (0x4U)
30550#define LPSPI_CR_DOZEN_SHIFT (2U)
30555#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
30556
30557#define LPSPI_CR_DBGEN_MASK (0x8U)
30558#define LPSPI_CR_DBGEN_SHIFT (3U)
30563#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
30564
30565#define LPSPI_CR_RTF_MASK (0x100U)
30566#define LPSPI_CR_RTF_SHIFT (8U)
30571#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
30572
30573#define LPSPI_CR_RRF_MASK (0x200U)
30574#define LPSPI_CR_RRF_SHIFT (9U)
30579#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
30585#define LPSPI_SR_TDF_MASK (0x1U)
30586#define LPSPI_SR_TDF_SHIFT (0U)
30591#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
30592
30593#define LPSPI_SR_RDF_MASK (0x2U)
30594#define LPSPI_SR_RDF_SHIFT (1U)
30599#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
30600
30601#define LPSPI_SR_WCF_MASK (0x100U)
30602#define LPSPI_SR_WCF_SHIFT (8U)
30607#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
30608
30609#define LPSPI_SR_FCF_MASK (0x200U)
30610#define LPSPI_SR_FCF_SHIFT (9U)
30615#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
30616
30617#define LPSPI_SR_TCF_MASK (0x400U)
30618#define LPSPI_SR_TCF_SHIFT (10U)
30623#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
30624
30625#define LPSPI_SR_TEF_MASK (0x800U)
30626#define LPSPI_SR_TEF_SHIFT (11U)
30631#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
30632
30633#define LPSPI_SR_REF_MASK (0x1000U)
30634#define LPSPI_SR_REF_SHIFT (12U)
30639#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
30640
30641#define LPSPI_SR_DMF_MASK (0x2000U)
30642#define LPSPI_SR_DMF_SHIFT (13U)
30647#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
30648
30649#define LPSPI_SR_MBF_MASK (0x1000000U)
30650#define LPSPI_SR_MBF_SHIFT (24U)
30655#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
30661#define LPSPI_IER_TDIE_MASK (0x1U)
30662#define LPSPI_IER_TDIE_SHIFT (0U)
30667#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
30668
30669#define LPSPI_IER_RDIE_MASK (0x2U)
30670#define LPSPI_IER_RDIE_SHIFT (1U)
30675#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
30676
30677#define LPSPI_IER_WCIE_MASK (0x100U)
30678#define LPSPI_IER_WCIE_SHIFT (8U)
30683#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
30684
30685#define LPSPI_IER_FCIE_MASK (0x200U)
30686#define LPSPI_IER_FCIE_SHIFT (9U)
30691#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
30692
30693#define LPSPI_IER_TCIE_MASK (0x400U)
30694#define LPSPI_IER_TCIE_SHIFT (10U)
30699#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
30700
30701#define LPSPI_IER_TEIE_MASK (0x800U)
30702#define LPSPI_IER_TEIE_SHIFT (11U)
30707#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
30708
30709#define LPSPI_IER_REIE_MASK (0x1000U)
30710#define LPSPI_IER_REIE_SHIFT (12U)
30715#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
30716
30717#define LPSPI_IER_DMIE_MASK (0x2000U)
30718#define LPSPI_IER_DMIE_SHIFT (13U)
30723#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
30729#define LPSPI_DER_TDDE_MASK (0x1U)
30730#define LPSPI_DER_TDDE_SHIFT (0U)
30735#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
30736
30737#define LPSPI_DER_RDDE_MASK (0x2U)
30738#define LPSPI_DER_RDDE_SHIFT (1U)
30743#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
30749#define LPSPI_CFGR0_HREN_MASK (0x1U)
30750#define LPSPI_CFGR0_HREN_SHIFT (0U)
30755#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
30756
30757#define LPSPI_CFGR0_HRPOL_MASK (0x2U)
30758#define LPSPI_CFGR0_HRPOL_SHIFT (1U)
30763#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
30764
30765#define LPSPI_CFGR0_HRSEL_MASK (0x4U)
30766#define LPSPI_CFGR0_HRSEL_SHIFT (2U)
30771#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
30772
30773#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
30774#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
30779#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
30780
30781#define LPSPI_CFGR0_RDMO_MASK (0x200U)
30782#define LPSPI_CFGR0_RDMO_SHIFT (9U)
30787#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
30793#define LPSPI_CFGR1_MASTER_MASK (0x1U)
30794#define LPSPI_CFGR1_MASTER_SHIFT (0U)
30799#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
30800
30801#define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
30802#define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
30807#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
30808
30809#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
30810#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
30815#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
30816
30817#define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
30818#define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
30823#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
30824
30825#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
30826#define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
30829#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
30830
30831#define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
30832#define LPSPI_CFGR1_MATCFG_SHIFT (16U)
30845#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
30846
30847#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
30848#define LPSPI_CFGR1_PINCFG_SHIFT (24U)
30855#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
30856
30857#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
30858#define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
30863#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
30864
30865#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
30866#define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
30871#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
30877#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
30878#define LPSPI_DMR0_MATCH0_SHIFT (0U)
30881#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
30887#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
30888#define LPSPI_DMR1_MATCH1_SHIFT (0U)
30891#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
30897#define LPSPI_CCR_SCKDIV_MASK (0xFFU)
30898#define LPSPI_CCR_SCKDIV_SHIFT (0U)
30901#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
30902
30903#define LPSPI_CCR_DBT_MASK (0xFF00U)
30904#define LPSPI_CCR_DBT_SHIFT (8U)
30907#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
30908
30909#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
30910#define LPSPI_CCR_PCSSCK_SHIFT (16U)
30913#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
30914
30915#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
30916#define LPSPI_CCR_SCKPCS_SHIFT (24U)
30919#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
30925#define LPSPI_FCR_TXWATER_MASK (0xFU)
30926#define LPSPI_FCR_TXWATER_SHIFT (0U)
30929#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
30930
30931#define LPSPI_FCR_RXWATER_MASK (0xF0000U)
30932#define LPSPI_FCR_RXWATER_SHIFT (16U)
30935#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
30941#define LPSPI_FSR_TXCOUNT_MASK (0x1FU)
30942#define LPSPI_FSR_TXCOUNT_SHIFT (0U)
30945#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
30946
30947#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)
30948#define LPSPI_FSR_RXCOUNT_SHIFT (16U)
30951#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
30957#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
30958#define LPSPI_TCR_FRAMESZ_SHIFT (0U)
30961#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
30962
30963#define LPSPI_TCR_WIDTH_MASK (0x30000U)
30964#define LPSPI_TCR_WIDTH_SHIFT (16U)
30971#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
30972
30973#define LPSPI_TCR_TXMSK_MASK (0x40000U)
30974#define LPSPI_TCR_TXMSK_SHIFT (18U)
30979#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
30980
30981#define LPSPI_TCR_RXMSK_MASK (0x80000U)
30982#define LPSPI_TCR_RXMSK_SHIFT (19U)
30987#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
30988
30989#define LPSPI_TCR_CONTC_MASK (0x100000U)
30990#define LPSPI_TCR_CONTC_SHIFT (20U)
30995#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
30996
30997#define LPSPI_TCR_CONT_MASK (0x200000U)
30998#define LPSPI_TCR_CONT_SHIFT (21U)
31003#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
31004
31005#define LPSPI_TCR_BYSW_MASK (0x400000U)
31006#define LPSPI_TCR_BYSW_SHIFT (22U)
31011#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
31012
31013#define LPSPI_TCR_LSBF_MASK (0x800000U)
31014#define LPSPI_TCR_LSBF_SHIFT (23U)
31019#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
31020
31021#define LPSPI_TCR_PCS_MASK (0x3000000U)
31022#define LPSPI_TCR_PCS_SHIFT (24U)
31029#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
31030
31031#define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
31032#define LPSPI_TCR_PRESCALE_SHIFT (27U)
31043#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
31044
31045#define LPSPI_TCR_CPHA_MASK (0x40000000U)
31046#define LPSPI_TCR_CPHA_SHIFT (30U)
31051#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
31052
31053#define LPSPI_TCR_CPOL_MASK (0x80000000U)
31054#define LPSPI_TCR_CPOL_SHIFT (31U)
31059#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
31065#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
31066#define LPSPI_TDR_DATA_SHIFT (0U)
31069#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
31075#define LPSPI_RSR_SOF_MASK (0x1U)
31076#define LPSPI_RSR_SOF_SHIFT (0U)
31081#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
31082
31083#define LPSPI_RSR_RXEMPTY_MASK (0x2U)
31084#define LPSPI_RSR_RXEMPTY_SHIFT (1U)
31089#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
31095#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
31096#define LPSPI_RDR_DATA_SHIFT (0U)
31099#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) /* end of group LPSPI_Register_Masks */
31106
31107
31108/* LPSPI - Peripheral instance base addresses */
31110#define LPSPI1_BASE (0x40394000u)
31112#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
31114#define LPSPI2_BASE (0x40398000u)
31116#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
31118#define LPSPI3_BASE (0x4039C000u)
31120#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE)
31122#define LPSPI4_BASE (0x403A0000u)
31124#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE)
31126#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }
31128#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }
31130#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }
31131 /* end of group LPSPI_Peripheral_Access_Layer */
31135
31136
31137/* ----------------------------------------------------------------------------
31138 -- LPUART Peripheral Access Layer
31139 ---------------------------------------------------------------------------- */
31140
31147typedef struct {
31148 __I uint32_t VERID;
31149 __I uint32_t PARAM;
31150 __IO uint32_t GLOBAL;
31151 __IO uint32_t PINCFG;
31152 __IO uint32_t BAUD;
31153 __IO uint32_t STAT;
31154 __IO uint32_t CTRL;
31155 __IO uint32_t DATA;
31156 __IO uint32_t MATCH;
31157 __IO uint32_t MODIR;
31158 __IO uint32_t FIFO;
31159 __IO uint32_t WATER;
31160} LPUART_Type;
31161
31162/* ----------------------------------------------------------------------------
31163 -- LPUART Register Masks
31164 ---------------------------------------------------------------------------- */
31165
31174#define LPUART_VERID_FEATURE_MASK (0xFFFFU)
31175#define LPUART_VERID_FEATURE_SHIFT (0U)
31180#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
31181
31182#define LPUART_VERID_MINOR_MASK (0xFF0000U)
31183#define LPUART_VERID_MINOR_SHIFT (16U)
31186#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
31187
31188#define LPUART_VERID_MAJOR_MASK (0xFF000000U)
31189#define LPUART_VERID_MAJOR_SHIFT (24U)
31192#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
31198#define LPUART_PARAM_TXFIFO_MASK (0xFFU)
31199#define LPUART_PARAM_TXFIFO_SHIFT (0U)
31202#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
31203
31204#define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
31205#define LPUART_PARAM_RXFIFO_SHIFT (8U)
31208#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
31214#define LPUART_GLOBAL_RST_MASK (0x2U)
31215#define LPUART_GLOBAL_RST_SHIFT (1U)
31220#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
31226#define LPUART_PINCFG_TRGSEL_MASK (0x3U)
31227#define LPUART_PINCFG_TRGSEL_SHIFT (0U)
31234#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
31240#define LPUART_BAUD_SBR_MASK (0x1FFFU)
31241#define LPUART_BAUD_SBR_SHIFT (0U)
31244#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
31245
31246#define LPUART_BAUD_SBNS_MASK (0x2000U)
31247#define LPUART_BAUD_SBNS_SHIFT (13U)
31252#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
31253
31254#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
31255#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
31260#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
31261
31262#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
31263#define LPUART_BAUD_LBKDIE_SHIFT (15U)
31268#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
31269
31270#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
31271#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
31276#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
31277
31278#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
31279#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
31284#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
31285
31286#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
31287#define LPUART_BAUD_MATCFG_SHIFT (18U)
31294#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
31295
31296#define LPUART_BAUD_RIDMAE_MASK (0x100000U)
31297#define LPUART_BAUD_RIDMAE_SHIFT (20U)
31302#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
31303
31304#define LPUART_BAUD_RDMAE_MASK (0x200000U)
31305#define LPUART_BAUD_RDMAE_SHIFT (21U)
31310#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
31311
31312#define LPUART_BAUD_TDMAE_MASK (0x800000U)
31313#define LPUART_BAUD_TDMAE_SHIFT (23U)
31318#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
31319
31320#define LPUART_BAUD_OSR_MASK (0x1F000000U)
31321#define LPUART_BAUD_OSR_SHIFT (24U)
31356#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
31357
31358#define LPUART_BAUD_M10_MASK (0x20000000U)
31359#define LPUART_BAUD_M10_SHIFT (29U)
31364#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
31365
31366#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
31367#define LPUART_BAUD_MAEN2_SHIFT (30U)
31372#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
31373
31374#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
31375#define LPUART_BAUD_MAEN1_SHIFT (31U)
31380#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
31386#define LPUART_STAT_MA2F_MASK (0x4000U)
31387#define LPUART_STAT_MA2F_SHIFT (14U)
31392#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
31393
31394#define LPUART_STAT_MA1F_MASK (0x8000U)
31395#define LPUART_STAT_MA1F_SHIFT (15U)
31400#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
31401
31402#define LPUART_STAT_PF_MASK (0x10000U)
31403#define LPUART_STAT_PF_SHIFT (16U)
31408#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
31409
31410#define LPUART_STAT_FE_MASK (0x20000U)
31411#define LPUART_STAT_FE_SHIFT (17U)
31416#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
31417
31418#define LPUART_STAT_NF_MASK (0x40000U)
31419#define LPUART_STAT_NF_SHIFT (18U)
31424#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
31425
31426#define LPUART_STAT_OR_MASK (0x80000U)
31427#define LPUART_STAT_OR_SHIFT (19U)
31432#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
31433
31434#define LPUART_STAT_IDLE_MASK (0x100000U)
31435#define LPUART_STAT_IDLE_SHIFT (20U)
31440#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
31441
31442#define LPUART_STAT_RDRF_MASK (0x200000U)
31443#define LPUART_STAT_RDRF_SHIFT (21U)
31448#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
31449
31450#define LPUART_STAT_TC_MASK (0x400000U)
31451#define LPUART_STAT_TC_SHIFT (22U)
31456#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
31457
31458#define LPUART_STAT_TDRE_MASK (0x800000U)
31459#define LPUART_STAT_TDRE_SHIFT (23U)
31464#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
31465
31466#define LPUART_STAT_RAF_MASK (0x1000000U)
31467#define LPUART_STAT_RAF_SHIFT (24U)
31472#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
31473
31474#define LPUART_STAT_LBKDE_MASK (0x2000000U)
31475#define LPUART_STAT_LBKDE_SHIFT (25U)
31480#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
31481
31482#define LPUART_STAT_BRK13_MASK (0x4000000U)
31483#define LPUART_STAT_BRK13_SHIFT (26U)
31488#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
31489
31490#define LPUART_STAT_RWUID_MASK (0x8000000U)
31491#define LPUART_STAT_RWUID_SHIFT (27U)
31498#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
31499
31500#define LPUART_STAT_RXINV_MASK (0x10000000U)
31501#define LPUART_STAT_RXINV_SHIFT (28U)
31506#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
31507
31508#define LPUART_STAT_MSBF_MASK (0x20000000U)
31509#define LPUART_STAT_MSBF_SHIFT (29U)
31517#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
31518
31519#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
31520#define LPUART_STAT_RXEDGIF_SHIFT (30U)
31525#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
31526
31527#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
31528#define LPUART_STAT_LBKDIF_SHIFT (31U)
31533#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
31539#define LPUART_CTRL_PT_MASK (0x1U)
31540#define LPUART_CTRL_PT_SHIFT (0U)
31545#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
31546
31547#define LPUART_CTRL_PE_MASK (0x2U)
31548#define LPUART_CTRL_PE_SHIFT (1U)
31553#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
31554
31555#define LPUART_CTRL_ILT_MASK (0x4U)
31556#define LPUART_CTRL_ILT_SHIFT (2U)
31561#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
31562
31563#define LPUART_CTRL_WAKE_MASK (0x8U)
31564#define LPUART_CTRL_WAKE_SHIFT (3U)
31569#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
31570
31571#define LPUART_CTRL_M_MASK (0x10U)
31572#define LPUART_CTRL_M_SHIFT (4U)
31577#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
31578
31579#define LPUART_CTRL_RSRC_MASK (0x20U)
31580#define LPUART_CTRL_RSRC_SHIFT (5U)
31585#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
31586
31587#define LPUART_CTRL_DOZEEN_MASK (0x40U)
31588#define LPUART_CTRL_DOZEEN_SHIFT (6U)
31593#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
31594
31595#define LPUART_CTRL_LOOPS_MASK (0x80U)
31596#define LPUART_CTRL_LOOPS_SHIFT (7U)
31601#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
31602
31603#define LPUART_CTRL_IDLECFG_MASK (0x700U)
31604#define LPUART_CTRL_IDLECFG_SHIFT (8U)
31615#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
31616
31617#define LPUART_CTRL_M7_MASK (0x800U)
31618#define LPUART_CTRL_M7_SHIFT (11U)
31623#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
31624
31625#define LPUART_CTRL_MA2IE_MASK (0x4000U)
31626#define LPUART_CTRL_MA2IE_SHIFT (14U)
31631#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
31632
31633#define LPUART_CTRL_MA1IE_MASK (0x8000U)
31634#define LPUART_CTRL_MA1IE_SHIFT (15U)
31639#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
31640
31641#define LPUART_CTRL_SBK_MASK (0x10000U)
31642#define LPUART_CTRL_SBK_SHIFT (16U)
31647#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
31648
31649#define LPUART_CTRL_RWU_MASK (0x20000U)
31650#define LPUART_CTRL_RWU_SHIFT (17U)
31655#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
31656
31657#define LPUART_CTRL_RE_MASK (0x40000U)
31658#define LPUART_CTRL_RE_SHIFT (18U)
31663#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
31664
31665#define LPUART_CTRL_TE_MASK (0x80000U)
31666#define LPUART_CTRL_TE_SHIFT (19U)
31671#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
31672
31673#define LPUART_CTRL_ILIE_MASK (0x100000U)
31674#define LPUART_CTRL_ILIE_SHIFT (20U)
31679#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
31680
31681#define LPUART_CTRL_RIE_MASK (0x200000U)
31682#define LPUART_CTRL_RIE_SHIFT (21U)
31687#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
31688
31689#define LPUART_CTRL_TCIE_MASK (0x400000U)
31690#define LPUART_CTRL_TCIE_SHIFT (22U)
31695#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
31696
31697#define LPUART_CTRL_TIE_MASK (0x800000U)
31698#define LPUART_CTRL_TIE_SHIFT (23U)
31703#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
31704
31705#define LPUART_CTRL_PEIE_MASK (0x1000000U)
31706#define LPUART_CTRL_PEIE_SHIFT (24U)
31711#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
31712
31713#define LPUART_CTRL_FEIE_MASK (0x2000000U)
31714#define LPUART_CTRL_FEIE_SHIFT (25U)
31719#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
31720
31721#define LPUART_CTRL_NEIE_MASK (0x4000000U)
31722#define LPUART_CTRL_NEIE_SHIFT (26U)
31727#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
31728
31729#define LPUART_CTRL_ORIE_MASK (0x8000000U)
31730#define LPUART_CTRL_ORIE_SHIFT (27U)
31735#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
31736
31737#define LPUART_CTRL_TXINV_MASK (0x10000000U)
31738#define LPUART_CTRL_TXINV_SHIFT (28U)
31743#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
31744
31745#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
31746#define LPUART_CTRL_TXDIR_SHIFT (29U)
31751#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
31752
31753#define LPUART_CTRL_R9T8_MASK (0x40000000U)
31754#define LPUART_CTRL_R9T8_SHIFT (30U)
31757#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
31758
31759#define LPUART_CTRL_R8T9_MASK (0x80000000U)
31760#define LPUART_CTRL_R8T9_SHIFT (31U)
31763#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
31769#define LPUART_DATA_R0T0_MASK (0x1U)
31770#define LPUART_DATA_R0T0_SHIFT (0U)
31773#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
31774
31775#define LPUART_DATA_R1T1_MASK (0x2U)
31776#define LPUART_DATA_R1T1_SHIFT (1U)
31779#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
31780
31781#define LPUART_DATA_R2T2_MASK (0x4U)
31782#define LPUART_DATA_R2T2_SHIFT (2U)
31785#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
31786
31787#define LPUART_DATA_R3T3_MASK (0x8U)
31788#define LPUART_DATA_R3T3_SHIFT (3U)
31791#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
31792
31793#define LPUART_DATA_R4T4_MASK (0x10U)
31794#define LPUART_DATA_R4T4_SHIFT (4U)
31797#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
31798
31799#define LPUART_DATA_R5T5_MASK (0x20U)
31800#define LPUART_DATA_R5T5_SHIFT (5U)
31803#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
31804
31805#define LPUART_DATA_R6T6_MASK (0x40U)
31806#define LPUART_DATA_R6T6_SHIFT (6U)
31809#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
31810
31811#define LPUART_DATA_R7T7_MASK (0x80U)
31812#define LPUART_DATA_R7T7_SHIFT (7U)
31815#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
31816
31817#define LPUART_DATA_R8T8_MASK (0x100U)
31818#define LPUART_DATA_R8T8_SHIFT (8U)
31821#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
31822
31823#define LPUART_DATA_R9T9_MASK (0x200U)
31824#define LPUART_DATA_R9T9_SHIFT (9U)
31827#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
31828
31829#define LPUART_DATA_IDLINE_MASK (0x800U)
31830#define LPUART_DATA_IDLINE_SHIFT (11U)
31835#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
31836
31837#define LPUART_DATA_RXEMPT_MASK (0x1000U)
31838#define LPUART_DATA_RXEMPT_SHIFT (12U)
31843#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
31844
31845#define LPUART_DATA_FRETSC_MASK (0x2000U)
31846#define LPUART_DATA_FRETSC_SHIFT (13U)
31851#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
31852
31853#define LPUART_DATA_PARITYE_MASK (0x4000U)
31854#define LPUART_DATA_PARITYE_SHIFT (14U)
31859#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
31860
31861#define LPUART_DATA_NOISY_MASK (0x8000U)
31862#define LPUART_DATA_NOISY_SHIFT (15U)
31867#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
31873#define LPUART_MATCH_MA1_MASK (0x3FFU)
31874#define LPUART_MATCH_MA1_SHIFT (0U)
31877#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
31878
31879#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
31880#define LPUART_MATCH_MA2_SHIFT (16U)
31883#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
31889#define LPUART_MODIR_TXCTSE_MASK (0x1U)
31890#define LPUART_MODIR_TXCTSE_SHIFT (0U)
31898#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
31899
31900#define LPUART_MODIR_TXRTSE_MASK (0x2U)
31901#define LPUART_MODIR_TXRTSE_SHIFT (1U)
31908#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
31909
31910#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
31911#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
31916#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
31917
31918#define LPUART_MODIR_RXRTSE_MASK (0x8U)
31919#define LPUART_MODIR_RXRTSE_SHIFT (3U)
31926#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
31927
31928#define LPUART_MODIR_TXCTSC_MASK (0x10U)
31929#define LPUART_MODIR_TXCTSC_SHIFT (4U)
31934#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
31935
31936#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
31937#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
31942#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
31943
31944#define LPUART_MODIR_RTSWATER_MASK (0x300U)
31945#define LPUART_MODIR_RTSWATER_SHIFT (8U)
31948#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
31949
31950#define LPUART_MODIR_TNP_MASK (0x30000U)
31951#define LPUART_MODIR_TNP_SHIFT (16U)
31958#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
31959
31960#define LPUART_MODIR_IREN_MASK (0x40000U)
31961#define LPUART_MODIR_IREN_SHIFT (18U)
31966#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
31972#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
31973#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
31984#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
31985
31986#define LPUART_FIFO_RXFE_MASK (0x8U)
31987#define LPUART_FIFO_RXFE_SHIFT (3U)
31992#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
31993
31994#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
31995#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
32006#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
32007
32008#define LPUART_FIFO_TXFE_MASK (0x80U)
32009#define LPUART_FIFO_TXFE_SHIFT (7U)
32014#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
32015
32016#define LPUART_FIFO_RXUFE_MASK (0x100U)
32017#define LPUART_FIFO_RXUFE_SHIFT (8U)
32022#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
32023
32024#define LPUART_FIFO_TXOFE_MASK (0x200U)
32025#define LPUART_FIFO_TXOFE_SHIFT (9U)
32030#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
32031
32032#define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
32033#define LPUART_FIFO_RXIDEN_SHIFT (10U)
32044#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
32045
32046#define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
32047#define LPUART_FIFO_RXFLUSH_SHIFT (14U)
32052#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
32053
32054#define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
32055#define LPUART_FIFO_TXFLUSH_SHIFT (15U)
32060#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
32061
32062#define LPUART_FIFO_RXUF_MASK (0x10000U)
32063#define LPUART_FIFO_RXUF_SHIFT (16U)
32068#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
32069
32070#define LPUART_FIFO_TXOF_MASK (0x20000U)
32071#define LPUART_FIFO_TXOF_SHIFT (17U)
32076#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
32077
32078#define LPUART_FIFO_RXEMPT_MASK (0x400000U)
32079#define LPUART_FIFO_RXEMPT_SHIFT (22U)
32084#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
32085
32086#define LPUART_FIFO_TXEMPT_MASK (0x800000U)
32087#define LPUART_FIFO_TXEMPT_SHIFT (23U)
32092#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
32098#define LPUART_WATER_TXWATER_MASK (0x3U)
32099#define LPUART_WATER_TXWATER_SHIFT (0U)
32102#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
32103
32104#define LPUART_WATER_TXCOUNT_MASK (0x700U)
32105#define LPUART_WATER_TXCOUNT_SHIFT (8U)
32108#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
32109
32110#define LPUART_WATER_RXWATER_MASK (0x30000U)
32111#define LPUART_WATER_RXWATER_SHIFT (16U)
32114#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
32115
32116#define LPUART_WATER_RXCOUNT_MASK (0x7000000U)
32117#define LPUART_WATER_RXCOUNT_SHIFT (24U)
32120#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) /* end of group LPUART_Register_Masks */
32127
32128
32129/* LPUART - Peripheral instance base addresses */
32131#define LPUART1_BASE (0x40184000u)
32133#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
32135#define LPUART2_BASE (0x40188000u)
32137#define LPUART2 ((LPUART_Type *)LPUART2_BASE)
32139#define LPUART3_BASE (0x4018C000u)
32141#define LPUART3 ((LPUART_Type *)LPUART3_BASE)
32143#define LPUART4_BASE (0x40190000u)
32145#define LPUART4 ((LPUART_Type *)LPUART4_BASE)
32147#define LPUART5_BASE (0x40194000u)
32149#define LPUART5 ((LPUART_Type *)LPUART5_BASE)
32151#define LPUART6_BASE (0x40198000u)
32153#define LPUART6 ((LPUART_Type *)LPUART6_BASE)
32155#define LPUART7_BASE (0x4019C000u)
32157#define LPUART7 ((LPUART_Type *)LPUART7_BASE)
32159#define LPUART8_BASE (0x401A0000u)
32161#define LPUART8 ((LPUART_Type *)LPUART8_BASE)
32163#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }
32165#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }
32167#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }
32168 /* end of group LPUART_Peripheral_Access_Layer */
32172
32173
32174/* ----------------------------------------------------------------------------
32175 -- OCOTP Peripheral Access Layer
32176 ---------------------------------------------------------------------------- */
32177
32184typedef struct {
32185 __IO uint32_t CTRL;
32186 __IO uint32_t CTRL_SET;
32187 __IO uint32_t CTRL_CLR;
32188 __IO uint32_t CTRL_TOG;
32189 __IO uint32_t TIMING;
32190 uint8_t RESERVED_0[12];
32191 __IO uint32_t DATA;
32192 uint8_t RESERVED_1[12];
32193 __IO uint32_t READ_CTRL;
32194 uint8_t RESERVED_2[12];
32195 __IO uint32_t READ_FUSE_DATA;
32196 uint8_t RESERVED_3[12];
32197 __IO uint32_t SW_STICKY;
32198 uint8_t RESERVED_4[12];
32199 __IO uint32_t SCS;
32200 __IO uint32_t SCS_SET;
32201 __IO uint32_t SCS_CLR;
32202 __IO uint32_t SCS_TOG;
32203 uint8_t RESERVED_5[32];
32204 __I uint32_t VERSION;
32205 uint8_t RESERVED_6[108];
32206 __IO uint32_t TIMING2;
32207 uint8_t RESERVED_7[764];
32208 __IO uint32_t LOCK;
32209 uint8_t RESERVED_8[12];
32210 __IO uint32_t CFG0;
32211 uint8_t RESERVED_9[12];
32212 __IO uint32_t CFG1;
32213 uint8_t RESERVED_10[12];
32214 __IO uint32_t CFG2;
32215 uint8_t RESERVED_11[12];
32216 __IO uint32_t CFG3;
32217 uint8_t RESERVED_12[12];
32218 __IO uint32_t CFG4;
32219 uint8_t RESERVED_13[12];
32220 __IO uint32_t CFG5;
32221 uint8_t RESERVED_14[12];
32222 __IO uint32_t CFG6;
32223 uint8_t RESERVED_15[12];
32224 __IO uint32_t MEM0;
32225 uint8_t RESERVED_16[12];
32226 __IO uint32_t MEM1;
32227 uint8_t RESERVED_17[12];
32228 __IO uint32_t MEM2;
32229 uint8_t RESERVED_18[12];
32230 __IO uint32_t MEM3;
32231 uint8_t RESERVED_19[12];
32232 __IO uint32_t MEM4;
32233 uint8_t RESERVED_20[12];
32234 __IO uint32_t ANA0;
32235 uint8_t RESERVED_21[12];
32236 __IO uint32_t ANA1;
32237 uint8_t RESERVED_22[12];
32238 __IO uint32_t ANA2;
32239 uint8_t RESERVED_23[140];
32240 __IO uint32_t SRK0;
32241 uint8_t RESERVED_24[12];
32242 __IO uint32_t SRK1;
32243 uint8_t RESERVED_25[12];
32244 __IO uint32_t SRK2;
32245 uint8_t RESERVED_26[12];
32246 __IO uint32_t SRK3;
32247 uint8_t RESERVED_27[12];
32248 __IO uint32_t SRK4;
32249 uint8_t RESERVED_28[12];
32250 __IO uint32_t SRK5;
32251 uint8_t RESERVED_29[12];
32252 __IO uint32_t SRK6;
32253 uint8_t RESERVED_30[12];
32254 __IO uint32_t SRK7;
32255 uint8_t RESERVED_31[12];
32256 __IO uint32_t SJC_RESP0;
32257 uint8_t RESERVED_32[12];
32258 __IO uint32_t SJC_RESP1;
32259 uint8_t RESERVED_33[12];
32260 __IO uint32_t MAC0;
32261 uint8_t RESERVED_34[12];
32262 __IO uint32_t MAC1;
32263 uint8_t RESERVED_35[12];
32264 __IO uint32_t GP3;
32265 uint8_t RESERVED_36[28];
32266 __IO uint32_t GP1;
32267 uint8_t RESERVED_37[12];
32268 __IO uint32_t GP2;
32269 uint8_t RESERVED_38[12];
32270 __IO uint32_t SW_GP1;
32271 uint8_t RESERVED_39[12];
32272 __IO uint32_t SW_GP20;
32273 uint8_t RESERVED_40[12];
32274 __IO uint32_t SW_GP21;
32275 uint8_t RESERVED_41[12];
32276 __IO uint32_t SW_GP22;
32277 uint8_t RESERVED_42[12];
32278 __IO uint32_t SW_GP23;
32279 uint8_t RESERVED_43[12];
32280 __IO uint32_t MISC_CONF0;
32281 uint8_t RESERVED_44[12];
32282 __IO uint32_t MISC_CONF1;
32283 uint8_t RESERVED_45[12];
32284 __IO uint32_t SRK_REVOKE;
32285} OCOTP_Type;
32286
32287/* ----------------------------------------------------------------------------
32288 -- OCOTP Register Masks
32289 ---------------------------------------------------------------------------- */
32290
32299#define OCOTP_CTRL_ADDR_MASK (0x3FU)
32300#define OCOTP_CTRL_ADDR_SHIFT (0U)
32303#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
32304
32305#define OCOTP_CTRL_BUSY_MASK (0x100U)
32306#define OCOTP_CTRL_BUSY_SHIFT (8U)
32311#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
32312
32313#define OCOTP_CTRL_ERROR_MASK (0x200U)
32314#define OCOTP_CTRL_ERROR_SHIFT (9U)
32319#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
32320
32321#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)
32322#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)
32327#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
32328
32329#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
32330#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
32335#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
32341#define OCOTP_CTRL_SET_ADDR_MASK (0x3FU)
32342#define OCOTP_CTRL_SET_ADDR_SHIFT (0U)
32345#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
32346
32347#define OCOTP_CTRL_SET_BUSY_MASK (0x100U)
32348#define OCOTP_CTRL_SET_BUSY_SHIFT (8U)
32351#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
32352
32353#define OCOTP_CTRL_SET_ERROR_MASK (0x200U)
32354#define OCOTP_CTRL_SET_ERROR_SHIFT (9U)
32357#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
32358
32359#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
32360#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
32363#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
32364
32365#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
32366#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
32369#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
32375#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU)
32376#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
32379#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
32380
32381#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U)
32382#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U)
32385#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
32386
32387#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U)
32388#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U)
32391#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
32392
32393#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
32394#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
32397#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
32398
32399#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
32400#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
32403#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
32409#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU)
32410#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
32413#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
32414
32415#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U)
32416#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U)
32419#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
32420
32421#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U)
32422#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U)
32425#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
32426
32427#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
32428#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
32431#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
32432
32433#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
32434#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
32437#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
32443#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)
32444#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U)
32447#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)
32448
32449#define OCOTP_TIMING_RELAX_MASK (0xF000U)
32450#define OCOTP_TIMING_RELAX_SHIFT (12U)
32453#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)
32454
32455#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)
32456#define OCOTP_TIMING_STROBE_READ_SHIFT (16U)
32459#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)
32460
32461#define OCOTP_TIMING_WAIT_MASK (0xFC00000U)
32462#define OCOTP_TIMING_WAIT_SHIFT (22U)
32465#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)
32471#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
32472#define OCOTP_DATA_DATA_SHIFT (0U)
32475#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
32481#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
32482#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
32485#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
32491#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
32492#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
32495#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
32501#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)
32502#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)
32507#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)
32508
32509#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)
32510#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)
32515#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)
32521#define OCOTP_SCS_HAB_JDE_MASK (0x1U)
32522#define OCOTP_SCS_HAB_JDE_SHIFT (0U)
32527#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)
32528
32529#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)
32530#define OCOTP_SCS_SPARE_SHIFT (1U)
32533#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)
32534
32535#define OCOTP_SCS_LOCK_MASK (0x80000000U)
32536#define OCOTP_SCS_LOCK_SHIFT (31U)
32542#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)
32548#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U)
32549#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U)
32552#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)
32553
32554#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)
32555#define OCOTP_SCS_SET_SPARE_SHIFT (1U)
32558#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)
32559
32560#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U)
32561#define OCOTP_SCS_SET_LOCK_SHIFT (31U)
32564#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)
32570#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)
32571#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)
32574#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)
32575
32576#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)
32577#define OCOTP_SCS_CLR_SPARE_SHIFT (1U)
32580#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)
32581
32582#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)
32583#define OCOTP_SCS_CLR_LOCK_SHIFT (31U)
32586#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)
32592#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)
32593#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)
32596#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)
32597
32598#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)
32599#define OCOTP_SCS_TOG_SPARE_SHIFT (1U)
32602#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)
32603
32604#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)
32605#define OCOTP_SCS_TOG_LOCK_SHIFT (31U)
32608#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)
32614#define OCOTP_VERSION_STEP_MASK (0xFFFFU)
32615#define OCOTP_VERSION_STEP_SHIFT (0U)
32618#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
32619
32620#define OCOTP_VERSION_MINOR_MASK (0xFF0000U)
32621#define OCOTP_VERSION_MINOR_SHIFT (16U)
32624#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
32625
32626#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
32627#define OCOTP_VERSION_MAJOR_SHIFT (24U)
32630#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
32636#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU)
32637#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U)
32640#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)
32641
32642#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U)
32643#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U)
32646#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)
32652#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU)
32653#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U)
32656#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)
32657
32658#define OCOTP_LOCK_SJC_RESP_MASK (0x40U)
32659#define OCOTP_LOCK_SJC_RESP_SHIFT (6U)
32665#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)
32666
32667#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U)
32668#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U)
32671#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)
32672
32673#define OCOTP_LOCK_GP1_MASK (0xC00U)
32674#define OCOTP_LOCK_GP1_SHIFT (10U)
32677#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)
32678
32679#define OCOTP_LOCK_GP2_MASK (0x3000U)
32680#define OCOTP_LOCK_GP2_SHIFT (12U)
32683#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)
32684
32685#define OCOTP_LOCK_SW_GP1_MASK (0x10000U)
32686#define OCOTP_LOCK_SW_GP1_SHIFT (16U)
32691#define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)
32692
32693#define OCOTP_LOCK_ANALOG_MASK (0xC0000U)
32694#define OCOTP_LOCK_ANALOG_SHIFT (18U)
32697#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)
32698
32699#define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U)
32700#define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U)
32705#define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)
32706
32707#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U)
32708#define OCOTP_LOCK_MISC_CONF_SHIFT (22U)
32713#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)
32714
32715#define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U)
32716#define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U)
32721#define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)
32722
32723#define OCOTP_LOCK_GP3_MASK (0xC000000U)
32724#define OCOTP_LOCK_GP3_SHIFT (26U)
32727#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)
32728
32729#define OCOTP_LOCK_FIELD_RETURN_MASK (0x80000000U)
32730#define OCOTP_LOCK_FIELD_RETURN_SHIFT (31U)
32735#define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)
32741#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU)
32742#define OCOTP_CFG0_BITS_SHIFT (0U)
32745#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)
32751#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU)
32752#define OCOTP_CFG1_BITS_SHIFT (0U)
32755#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)
32761#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU)
32762#define OCOTP_CFG2_BITS_SHIFT (0U)
32765#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)
32771#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU)
32772#define OCOTP_CFG3_BITS_SHIFT (0U)
32775#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)
32781#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU)
32782#define OCOTP_CFG4_BITS_SHIFT (0U)
32785#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)
32791#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU)
32792#define OCOTP_CFG5_BITS_SHIFT (0U)
32795#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)
32801#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU)
32802#define OCOTP_CFG6_BITS_SHIFT (0U)
32805#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)
32811#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU)
32812#define OCOTP_MEM0_BITS_SHIFT (0U)
32815#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)
32821#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU)
32822#define OCOTP_MEM1_BITS_SHIFT (0U)
32825#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)
32831#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU)
32832#define OCOTP_MEM2_BITS_SHIFT (0U)
32835#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)
32841#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)
32842#define OCOTP_MEM3_BITS_SHIFT (0U)
32845#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)
32851#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)
32852#define OCOTP_MEM4_BITS_SHIFT (0U)
32855#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)
32861#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)
32862#define OCOTP_ANA0_BITS_SHIFT (0U)
32865#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)
32871#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)
32872#define OCOTP_ANA1_BITS_SHIFT (0U)
32875#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)
32881#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)
32882#define OCOTP_ANA2_BITS_SHIFT (0U)
32885#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)
32891#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)
32892#define OCOTP_SRK0_BITS_SHIFT (0U)
32895#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)
32901#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)
32902#define OCOTP_SRK1_BITS_SHIFT (0U)
32905#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)
32911#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)
32912#define OCOTP_SRK2_BITS_SHIFT (0U)
32915#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)
32921#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)
32922#define OCOTP_SRK3_BITS_SHIFT (0U)
32925#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)
32931#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)
32932#define OCOTP_SRK4_BITS_SHIFT (0U)
32935#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)
32941#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)
32942#define OCOTP_SRK5_BITS_SHIFT (0U)
32945#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)
32951#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)
32952#define OCOTP_SRK6_BITS_SHIFT (0U)
32955#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)
32961#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)
32962#define OCOTP_SRK7_BITS_SHIFT (0U)
32965#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)
32971#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)
32972#define OCOTP_SJC_RESP0_BITS_SHIFT (0U)
32975#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)
32981#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)
32982#define OCOTP_SJC_RESP1_BITS_SHIFT (0U)
32985#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)
32991#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)
32992#define OCOTP_MAC0_BITS_SHIFT (0U)
32995#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)
33001#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)
33002#define OCOTP_MAC1_BITS_SHIFT (0U)
33005#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)
33011#define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU)
33012#define OCOTP_GP3_BITS_SHIFT (0U)
33015#define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK)
33021#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU)
33022#define OCOTP_GP1_BITS_SHIFT (0U)
33025#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)
33031#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU)
33032#define OCOTP_GP2_BITS_SHIFT (0U)
33035#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)
33041#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)
33042#define OCOTP_SW_GP1_BITS_SHIFT (0U)
33045#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)
33051#define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)
33052#define OCOTP_SW_GP20_BITS_SHIFT (0U)
33055#define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)
33061#define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)
33062#define OCOTP_SW_GP21_BITS_SHIFT (0U)
33065#define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)
33071#define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)
33072#define OCOTP_SW_GP22_BITS_SHIFT (0U)
33075#define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)
33081#define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)
33082#define OCOTP_SW_GP23_BITS_SHIFT (0U)
33085#define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)
33091#define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)
33092#define OCOTP_MISC_CONF0_BITS_SHIFT (0U)
33095#define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)
33101#define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)
33102#define OCOTP_MISC_CONF1_BITS_SHIFT (0U)
33105#define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)
33111#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)
33112#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U)
33115#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) /* end of group OCOTP_Register_Masks */
33122
33123
33124/* OCOTP - Peripheral instance base addresses */
33126#define OCOTP_BASE (0x401F4000u)
33128#define OCOTP ((OCOTP_Type *)OCOTP_BASE)
33130#define OCOTP_BASE_ADDRS { OCOTP_BASE }
33132#define OCOTP_BASE_PTRS { OCOTP }
33133 /* end of group OCOTP_Peripheral_Access_Layer */
33137
33138
33139/* ----------------------------------------------------------------------------
33140 -- PGC Peripheral Access Layer
33141 ---------------------------------------------------------------------------- */
33142
33149typedef struct {
33150 uint8_t RESERVED_0[544];
33151 __IO uint32_t MEGA_CTRL;
33152 __IO uint32_t MEGA_PUPSCR;
33153 __IO uint32_t MEGA_PDNSCR;
33154 __IO uint32_t MEGA_SR;
33155 uint8_t RESERVED_1[112];
33156 __IO uint32_t CPU_CTRL;
33157 __IO uint32_t CPU_PUPSCR;
33158 __IO uint32_t CPU_PDNSCR;
33159 __IO uint32_t CPU_SR;
33160} PGC_Type;
33161
33162/* ----------------------------------------------------------------------------
33163 -- PGC Register Masks
33164 ---------------------------------------------------------------------------- */
33165
33174#define PGC_MEGA_CTRL_PCR_MASK (0x1U)
33175#define PGC_MEGA_CTRL_PCR_SHIFT (0U)
33180#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)
33186#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU)
33187#define PGC_MEGA_PUPSCR_SW_SHIFT (0U)
33188#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)
33189
33190#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)
33191#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)
33192#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)
33198#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU)
33199#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U)
33200#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)
33201
33202#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)
33203#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)
33204#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)
33210#define PGC_MEGA_SR_PSR_MASK (0x1U)
33211#define PGC_MEGA_SR_PSR_SHIFT (0U)
33216#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)
33222#define PGC_CPU_CTRL_PCR_MASK (0x1U)
33223#define PGC_CPU_CTRL_PCR_SHIFT (0U)
33228#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)
33234#define PGC_CPU_PUPSCR_SW_MASK (0x3FU)
33235#define PGC_CPU_PUPSCR_SW_SHIFT (0U)
33236#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)
33237
33238#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)
33239#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)
33240#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
33246#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU)
33247#define PGC_CPU_PDNSCR_ISO_SHIFT (0U)
33248#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)
33249
33250#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)
33251#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)
33252#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
33258#define PGC_CPU_SR_PSR_MASK (0x1U)
33259#define PGC_CPU_SR_PSR_SHIFT (0U)
33264#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) /* end of group PGC_Register_Masks */
33271
33272
33273/* PGC - Peripheral instance base addresses */
33275#define PGC_BASE (0x400F4000u)
33277#define PGC ((PGC_Type *)PGC_BASE)
33279#define PGC_BASE_ADDRS { PGC_BASE }
33281#define PGC_BASE_PTRS { PGC }
33282 /* end of group PGC_Peripheral_Access_Layer */
33286
33287
33288/* ----------------------------------------------------------------------------
33289 -- PIT Peripheral Access Layer
33290 ---------------------------------------------------------------------------- */
33291
33298typedef struct {
33299 __IO uint32_t MCR;
33300 uint8_t RESERVED_0[220];
33301 __I uint32_t LTMR64H;
33302 __I uint32_t LTMR64L;
33303 uint8_t RESERVED_1[24];
33304 struct { /* offset: 0x100, array step: 0x10 */
33305 __IO uint32_t LDVAL;
33306 __I uint32_t CVAL;
33307 __IO uint32_t TCTRL;
33308 __IO uint32_t TFLG;
33309 } CHANNEL[4];
33310} PIT_Type;
33311
33312/* ----------------------------------------------------------------------------
33313 -- PIT Register Masks
33314 ---------------------------------------------------------------------------- */
33315
33324#define PIT_MCR_FRZ_MASK (0x1U)
33325#define PIT_MCR_FRZ_SHIFT (0U)
33330#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
33331
33332#define PIT_MCR_MDIS_MASK (0x2U)
33333#define PIT_MCR_MDIS_SHIFT (1U)
33338#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
33344#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
33345#define PIT_LTMR64H_LTH_SHIFT (0U)
33348#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
33354#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
33355#define PIT_LTMR64L_LTL_SHIFT (0U)
33358#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
33364#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
33365#define PIT_LDVAL_TSV_SHIFT (0U)
33368#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
33371/* The count of PIT_LDVAL */
33372#define PIT_LDVAL_COUNT (4U)
33373
33377#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
33378#define PIT_CVAL_TVL_SHIFT (0U)
33381#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
33384/* The count of PIT_CVAL */
33385#define PIT_CVAL_COUNT (4U)
33386
33390#define PIT_TCTRL_TEN_MASK (0x1U)
33391#define PIT_TCTRL_TEN_SHIFT (0U)
33396#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
33397
33398#define PIT_TCTRL_TIE_MASK (0x2U)
33399#define PIT_TCTRL_TIE_SHIFT (1U)
33404#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
33405
33406#define PIT_TCTRL_CHN_MASK (0x4U)
33407#define PIT_TCTRL_CHN_SHIFT (2U)
33412#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
33415/* The count of PIT_TCTRL */
33416#define PIT_TCTRL_COUNT (4U)
33417
33421#define PIT_TFLG_TIF_MASK (0x1U)
33422#define PIT_TFLG_TIF_SHIFT (0U)
33427#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
33430/* The count of PIT_TFLG */
33431#define PIT_TFLG_COUNT (4U)
33432
33433 /* end of group PIT_Register_Masks */
33437
33438
33439/* PIT - Peripheral instance base addresses */
33441#define PIT_BASE (0x40084000u)
33443#define PIT ((PIT_Type *)PIT_BASE)
33445#define PIT_BASE_ADDRS { PIT_BASE }
33447#define PIT_BASE_PTRS { PIT }
33449#define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
33450 /* end of group PIT_Peripheral_Access_Layer */
33454
33455
33456/* ----------------------------------------------------------------------------
33457 -- PMU Peripheral Access Layer
33458 ---------------------------------------------------------------------------- */
33459
33466typedef struct {
33467 uint8_t RESERVED_0[272];
33468 __IO uint32_t REG_1P1;
33469 __IO uint32_t REG_1P1_SET;
33470 __IO uint32_t REG_1P1_CLR;
33471 __IO uint32_t REG_1P1_TOG;
33472 __IO uint32_t REG_3P0;
33473 __IO uint32_t REG_3P0_SET;
33474 __IO uint32_t REG_3P0_CLR;
33475 __IO uint32_t REG_3P0_TOG;
33476 __IO uint32_t REG_2P5;
33477 __IO uint32_t REG_2P5_SET;
33478 __IO uint32_t REG_2P5_CLR;
33479 __IO uint32_t REG_2P5_TOG;
33480 __IO uint32_t REG_CORE;
33481 __IO uint32_t REG_CORE_SET;
33482 __IO uint32_t REG_CORE_CLR;
33483 __IO uint32_t REG_CORE_TOG;
33484 __IO uint32_t MISC0;
33485 __IO uint32_t MISC0_SET;
33486 __IO uint32_t MISC0_CLR;
33487 __IO uint32_t MISC0_TOG;
33488 __IO uint32_t MISC1;
33489 __IO uint32_t MISC1_SET;
33490 __IO uint32_t MISC1_CLR;
33491 __IO uint32_t MISC1_TOG;
33492 __IO uint32_t MISC2;
33493 __IO uint32_t MISC2_SET;
33494 __IO uint32_t MISC2_CLR;
33495 __IO uint32_t MISC2_TOG;
33496} PMU_Type;
33497
33498/* ----------------------------------------------------------------------------
33499 -- PMU Register Masks
33500 ---------------------------------------------------------------------------- */
33501
33510#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)
33511#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)
33512#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)
33513
33514#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U)
33515#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U)
33516#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)
33517
33518#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)
33519#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)
33520#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
33521
33522#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)
33523#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)
33524#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)
33525
33526#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U)
33527#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U)
33528#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)
33529
33530#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)
33531#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)
33537#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)
33538
33539#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)
33540#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)
33541#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)
33542
33543#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)
33544#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)
33545#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)
33546
33547#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)
33548#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)
33549#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)
33550
33551#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)
33552#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)
33557#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)
33563#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)
33564#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)
33565#define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)
33566
33567#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)
33568#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)
33569#define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)
33570
33571#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)
33572#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)
33573#define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)
33574
33575#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)
33576#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)
33577#define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)
33578
33579#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)
33580#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)
33581#define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)
33582
33583#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)
33584#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)
33590#define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)
33591
33592#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)
33593#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)
33594#define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)
33595
33596#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)
33597#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)
33598#define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)
33599
33600#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
33601#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
33602#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)
33603
33604#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)
33605#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)
33610#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)
33616#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)
33617#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)
33618#define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)
33619
33620#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)
33621#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)
33622#define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)
33623
33624#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)
33625#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)
33626#define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)
33627
33628#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)
33629#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)
33630#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)
33631
33632#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)
33633#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)
33634#define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)
33635
33636#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)
33637#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)
33643#define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)
33644
33645#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)
33646#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)
33647#define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)
33648
33649#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)
33650#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)
33651#define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)
33652
33653#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
33654#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
33655#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)
33656
33657#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)
33658#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)
33663#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)
33669#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)
33670#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)
33671#define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)
33672
33673#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)
33674#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)
33675#define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)
33676
33677#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)
33678#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)
33679#define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)
33680
33681#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)
33682#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)
33683#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)
33684
33685#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)
33686#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)
33687#define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)
33688
33689#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)
33690#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)
33696#define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)
33697
33698#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)
33699#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)
33700#define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)
33701
33702#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)
33703#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)
33704#define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)
33705
33706#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
33707#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
33708#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)
33709
33710#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)
33711#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)
33716#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)
33722#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)
33723#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)
33724#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
33725
33726#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U)
33727#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U)
33728#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)
33729
33730#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)
33731#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)
33732#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
33733
33734#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U)
33735#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U)
33736#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)
33737
33738#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U)
33739#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U)
33744#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)
33745
33746#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)
33747#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)
33753#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)
33754
33755#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)
33756#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)
33757#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)
33758
33759#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)
33760#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)
33761#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)
33767#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)
33768#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)
33769#define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)
33770
33771#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)
33772#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)
33773#define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)
33774
33775#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)
33776#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)
33777#define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)
33778
33779#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)
33780#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)
33781#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)
33782
33783#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)
33784#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)
33789#define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)
33790
33791#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)
33792#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)
33798#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
33799
33800#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)
33801#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)
33802#define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)
33803
33804#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)
33805#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)
33806#define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)
33812#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)
33813#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)
33814#define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)
33815
33816#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)
33817#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)
33818#define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)
33819
33820#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)
33821#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)
33822#define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)
33823
33824#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)
33825#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)
33826#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)
33827
33828#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)
33829#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)
33834#define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)
33835
33836#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)
33837#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)
33843#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
33844
33845#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)
33846#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)
33847#define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)
33848
33849#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)
33850#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)
33851#define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)
33857#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)
33858#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)
33859#define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)
33860
33861#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)
33862#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)
33863#define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)
33864
33865#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)
33866#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)
33867#define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)
33868
33869#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)
33870#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)
33871#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)
33872
33873#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)
33874#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)
33879#define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)
33880
33881#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)
33882#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)
33888#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
33889
33890#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)
33891#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)
33892#define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)
33893
33894#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)
33895#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)
33896#define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)
33902#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)
33903#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)
33904#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)
33905
33906#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U)
33907#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U)
33908#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)
33909
33910#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)
33911#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)
33912#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)
33913
33914#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)
33915#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)
33916#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)
33917
33918#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U)
33919#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U)
33920#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)
33921
33922#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)
33923#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)
33929#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
33930
33931#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)
33932#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)
33933#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)
33934
33935#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)
33936#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)
33937#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)
33938
33939#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)
33940#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)
33941#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)
33947#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)
33948#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)
33949#define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)
33950
33951#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)
33952#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)
33953#define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)
33954
33955#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)
33956#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)
33957#define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)
33958
33959#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)
33960#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)
33961#define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)
33962
33963#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)
33964#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)
33965#define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)
33966
33967#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)
33968#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)
33974#define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)
33975
33976#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)
33977#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)
33978#define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)
33979
33980#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)
33981#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)
33982#define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)
33983
33984#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
33985#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
33986#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)
33992#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)
33993#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)
33994#define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)
33995
33996#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)
33997#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)
33998#define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)
33999
34000#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)
34001#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)
34002#define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)
34003
34004#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)
34005#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)
34006#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)
34007
34008#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)
34009#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)
34010#define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)
34011
34012#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)
34013#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)
34019#define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)
34020
34021#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)
34022#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)
34023#define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)
34024
34025#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)
34026#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)
34027#define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)
34028
34029#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
34030#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
34031#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)
34037#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)
34038#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)
34039#define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)
34040
34041#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)
34042#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)
34043#define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)
34044
34045#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)
34046#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)
34047#define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)
34048
34049#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)
34050#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)
34051#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)
34052
34053#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)
34054#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)
34055#define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)
34056
34057#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)
34058#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)
34064#define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)
34065
34066#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)
34067#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)
34068#define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)
34069
34070#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)
34071#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)
34072#define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)
34073
34074#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
34075#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
34076#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)
34082#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU)
34083#define PMU_REG_CORE_REG0_TARG_SHIFT (0U)
34093#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)
34094
34095#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)
34096#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U)
34117#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)
34118
34119#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)
34120#define PMU_REG_CORE_REG1_TARG_SHIFT (9U)
34132#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)
34133
34134#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)
34135#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U)
34156#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)
34157
34158#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)
34159#define PMU_REG_CORE_REG2_TARG_SHIFT (18U)
34169#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)
34170
34171#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)
34172#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U)
34193#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)
34194
34195#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)
34196#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U)
34203#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)
34204
34205#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)
34206#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)
34207#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)
34213#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)
34214#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)
34224#define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)
34225
34226#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)
34227#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)
34248#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)
34249
34250#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)
34251#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)
34263#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)
34264
34265#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)
34266#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)
34287#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)
34288
34289#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)
34290#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)
34300#define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)
34301
34302#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)
34303#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)
34324#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)
34325
34326#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)
34327#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)
34334#define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)
34335
34336#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)
34337#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)
34338#define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)
34344#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)
34345#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)
34355#define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)
34356
34357#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)
34358#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)
34379#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)
34380
34381#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)
34382#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)
34394#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)
34395
34396#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)
34397#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)
34418#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)
34419
34420#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)
34421#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)
34431#define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)
34432
34433#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)
34434#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)
34455#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)
34456
34457#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)
34458#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)
34465#define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)
34466
34467#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)
34468#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)
34469#define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)
34475#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)
34476#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)
34486#define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)
34487
34488#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)
34489#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)
34510#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)
34511
34512#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)
34513#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)
34525#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)
34526
34527#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)
34528#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)
34549#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)
34550
34551#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)
34552#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)
34562#define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)
34563
34564#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)
34565#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)
34586#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)
34587
34588#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)
34589#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)
34596#define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)
34597
34598#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)
34599#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)
34600#define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)
34606#define PMU_MISC0_REFTOP_PWD_MASK (0x1U)
34607#define PMU_MISC0_REFTOP_PWD_SHIFT (0U)
34608#define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)
34609
34610#define PMU_MISC0_REFTOP_PWDVBGUP_MASK (0x2U)
34611#define PMU_MISC0_REFTOP_PWDVBGUP_SHIFT (1U)
34612#define PMU_MISC0_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_REFTOP_PWDVBGUP_MASK)
34613
34614#define PMU_MISC0_REFTOP_LOWPOWER_MASK (0x4U)
34615#define PMU_MISC0_REFTOP_LOWPOWER_SHIFT (2U)
34616#define PMU_MISC0_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_REFTOP_LOWPOWER_MASK)
34617
34618#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
34619#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
34624#define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)
34625
34626#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)
34627#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)
34638#define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)
34639
34640#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)
34641#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)
34642#define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)
34643
34644#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
34645#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
34652#define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)
34653
34654#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
34655#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
34660#define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)
34661
34662#define PMU_MISC0_OSC_I_MASK (0x6000U)
34663#define PMU_MISC0_OSC_I_SHIFT (13U)
34670#define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)
34671
34672#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U)
34673#define PMU_MISC0_OSC_XTALOK_SHIFT (15U)
34674#define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)
34675
34676#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
34677#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)
34678#define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)
34679
34680#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
34681#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)
34686#define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)
34687
34688#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
34689#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)
34700#define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)
34701
34702#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
34703#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
34708#define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)
34709
34710#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
34711#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)
34712#define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)
34713
34714#define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
34715#define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)
34720#define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)
34726#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)
34727#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)
34728#define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)
34729
34730#define PMU_MISC0_SET_REFTOP_PWDVBGUP_MASK (0x2U)
34731#define PMU_MISC0_SET_REFTOP_PWDVBGUP_SHIFT (1U)
34732#define PMU_MISC0_SET_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_PWDVBGUP_MASK)
34733
34734#define PMU_MISC0_SET_REFTOP_LOWPOWER_MASK (0x4U)
34735#define PMU_MISC0_SET_REFTOP_LOWPOWER_SHIFT (2U)
34736#define PMU_MISC0_SET_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_SET_REFTOP_LOWPOWER_MASK)
34737
34738#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
34739#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
34744#define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
34745
34746#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
34747#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
34758#define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)
34759
34760#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
34761#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
34762#define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)
34763
34764#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
34765#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
34772#define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)
34773
34774#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
34775#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
34780#define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)
34781
34782#define PMU_MISC0_SET_OSC_I_MASK (0x6000U)
34783#define PMU_MISC0_SET_OSC_I_SHIFT (13U)
34790#define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)
34791
34792#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
34793#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)
34794#define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)
34795
34796#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
34797#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
34798#define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)
34799
34800#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
34801#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
34806#define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)
34807
34808#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
34809#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
34820#define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)
34821
34822#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
34823#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
34828#define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)
34829
34830#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
34831#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
34832#define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)
34833
34834#define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
34835#define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
34840#define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)
34846#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
34847#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
34848#define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)
34849
34850#define PMU_MISC0_CLR_REFTOP_PWDVBGUP_MASK (0x2U)
34851#define PMU_MISC0_CLR_REFTOP_PWDVBGUP_SHIFT (1U)
34852#define PMU_MISC0_CLR_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWDVBGUP_MASK)
34853
34854#define PMU_MISC0_CLR_REFTOP_LOWPOWER_MASK (0x4U)
34855#define PMU_MISC0_CLR_REFTOP_LOWPOWER_SHIFT (2U)
34856#define PMU_MISC0_CLR_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_CLR_REFTOP_LOWPOWER_MASK)
34857
34858#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
34859#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
34864#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
34865
34866#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
34867#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
34878#define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)
34879
34880#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
34881#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
34882#define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)
34883
34884#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
34885#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
34892#define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)
34893
34894#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
34895#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
34900#define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
34901
34902#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U)
34903#define PMU_MISC0_CLR_OSC_I_SHIFT (13U)
34910#define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)
34911
34912#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
34913#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
34914#define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)
34915
34916#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
34917#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
34918#define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)
34919
34920#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
34921#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
34926#define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)
34927
34928#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
34929#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
34940#define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)
34941
34942#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
34943#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
34948#define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
34949
34950#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
34951#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
34952#define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)
34953
34954#define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
34955#define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
34960#define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)
34966#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
34967#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
34968#define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)
34969
34970#define PMU_MISC0_TOG_REFTOP_PWDVBGUP_MASK (0x2U)
34971#define PMU_MISC0_TOG_REFTOP_PWDVBGUP_SHIFT (1U)
34972#define PMU_MISC0_TOG_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWDVBGUP_MASK)
34973
34974#define PMU_MISC0_TOG_REFTOP_LOWPOWER_MASK (0x4U)
34975#define PMU_MISC0_TOG_REFTOP_LOWPOWER_SHIFT (2U)
34976#define PMU_MISC0_TOG_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_TOG_REFTOP_LOWPOWER_MASK)
34977
34978#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
34979#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
34984#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
34985
34986#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
34987#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
34998#define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)
34999
35000#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
35001#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
35002#define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)
35003
35004#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
35005#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
35012#define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)
35013
35014#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
35015#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
35020#define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
35021
35022#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U)
35023#define PMU_MISC0_TOG_OSC_I_SHIFT (13U)
35030#define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)
35031
35032#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
35033#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
35034#define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)
35035
35036#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
35037#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
35038#define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)
35039
35040#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
35041#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
35046#define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)
35047
35048#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
35049#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
35060#define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)
35061
35062#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
35063#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
35068#define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
35069
35070#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
35071#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
35072#define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)
35073
35074#define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
35075#define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
35080#define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)
35086#define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
35087#define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
35106#define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)
35107
35108#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)
35109#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)
35133#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
35134
35135#define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
35136#define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
35137#define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)
35138
35139#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)
35140#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)
35141#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)
35142
35143#define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
35144#define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
35145#define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)
35146
35147#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)
35148#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)
35149#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
35150
35151#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
35152#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
35153#define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)
35154
35155#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
35156#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
35157#define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)
35158
35159#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
35160#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
35161#define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)
35162
35163#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
35164#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)
35165#define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)
35166
35167#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
35168#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
35169#define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)
35170
35171#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
35172#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)
35173#define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)
35174
35175#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
35176#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)
35177#define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)
35183#define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
35184#define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
35203#define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)
35204
35205#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)
35206#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)
35230#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
35231
35232#define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
35233#define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
35234#define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)
35235
35236#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)
35237#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)
35238#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)
35239
35240#define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
35241#define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
35242#define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)
35243
35244#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)
35245#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)
35246#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)
35247
35248#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
35249#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
35250#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
35251
35252#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
35253#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
35254#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
35255
35256#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
35257#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
35258#define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)
35259
35260#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
35261#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
35262#define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
35263
35264#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
35265#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
35266#define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)
35267
35268#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
35269#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
35270#define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)
35271
35272#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
35273#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
35274#define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)
35280#define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
35281#define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
35300#define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
35301
35302#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)
35303#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)
35327#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)
35328
35329#define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
35330#define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
35331#define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)
35332
35333#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)
35334#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)
35335#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)
35336
35337#define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
35338#define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
35339#define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)
35340
35341#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)
35342#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)
35343#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)
35344
35345#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
35346#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
35347#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
35348
35349#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
35350#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
35351#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
35352
35353#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
35354#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
35355#define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)
35356
35357#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
35358#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
35359#define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)
35360
35361#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
35362#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
35363#define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)
35364
35365#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
35366#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
35367#define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)
35368
35369#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
35370#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
35371#define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)
35377#define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
35378#define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
35397#define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)
35398
35399#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)
35400#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)
35424#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)
35425
35426#define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
35427#define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
35428#define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)
35429
35430#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)
35431#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)
35432#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)
35433
35434#define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
35435#define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
35436#define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)
35437
35438#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)
35439#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)
35440#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)
35441
35442#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
35443#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
35444#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
35445
35446#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
35447#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
35448#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
35449
35450#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
35451#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
35452#define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)
35453
35454#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
35455#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
35456#define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)
35457
35458#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
35459#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
35460#define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)
35461
35462#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
35463#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
35464#define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)
35465
35466#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
35467#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
35468#define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)
35474#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)
35475#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)
35480#define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)
35481
35482#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)
35483#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)
35487#define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)
35488
35489#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)
35490#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)
35491#define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)
35492
35493#define PMU_MISC2_PLL3_disable_MASK (0x80U)
35494#define PMU_MISC2_PLL3_disable_SHIFT (7U)
35495#define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)
35496
35497#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)
35498#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)
35503#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)
35504
35505#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)
35506#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)
35510#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)
35511
35512#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
35513#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)
35514#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)
35515
35516#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
35517#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
35522#define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)
35523
35524#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
35525#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)
35530#define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
35531
35532#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)
35533#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)
35534#define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)
35535
35536#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
35537#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)
35538#define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)
35539
35540#define PMU_MISC2_REG2_OK_MASK (0x400000U)
35541#define PMU_MISC2_REG2_OK_SHIFT (22U)
35542#define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)
35543
35544#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
35545#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
35550#define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)
35551
35552#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
35553#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)
35560#define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)
35561
35562#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
35563#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)
35570#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)
35571
35572#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
35573#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)
35580#define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)
35581
35582#define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)
35583#define PMU_MISC2_VIDEO_DIV_SHIFT (30U)
35590#define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)
35596#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
35597#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
35602#define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
35603
35604#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
35605#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
35609#define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)
35610
35611#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
35612#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
35613#define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)
35614
35615#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U)
35616#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U)
35617#define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)
35618
35619#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
35620#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
35625#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
35626
35627#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
35628#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
35632#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)
35633
35634#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
35635#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
35636#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)
35637
35638#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
35639#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
35644#define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)
35645
35646#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
35647#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
35652#define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
35653
35654#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
35655#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
35656#define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)
35657
35658#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
35659#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
35660#define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)
35661
35662#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U)
35663#define PMU_MISC2_SET_REG2_OK_SHIFT (22U)
35664#define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)
35665
35666#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
35667#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
35672#define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)
35673
35674#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
35675#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
35682#define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)
35683
35684#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
35685#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
35692#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)
35693
35694#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
35695#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
35702#define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)
35703
35704#define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
35705#define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)
35712#define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)
35718#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
35719#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
35724#define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
35725
35726#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
35727#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
35731#define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)
35732
35733#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
35734#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
35735#define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)
35736
35737#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)
35738#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)
35739#define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)
35740
35741#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
35742#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
35747#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
35748
35749#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
35750#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
35754#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)
35755
35756#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
35757#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
35758#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)
35759
35760#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
35761#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
35766#define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)
35767
35768#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
35769#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
35774#define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
35775
35776#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
35777#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
35778#define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)
35779
35780#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
35781#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
35782#define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)
35783
35784#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)
35785#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U)
35786#define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)
35787
35788#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
35789#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
35794#define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)
35795
35796#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
35797#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
35804#define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
35805
35806#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
35807#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
35814#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
35815
35816#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
35817#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
35824#define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
35825
35826#define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
35827#define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
35834#define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
35840#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
35841#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
35846#define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
35847
35848#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
35849#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
35853#define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)
35854
35855#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
35856#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
35857#define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)
35858
35859#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)
35860#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)
35861#define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)
35862
35863#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
35864#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
35869#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
35870
35871#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
35872#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
35876#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)
35877
35878#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
35879#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
35880#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)
35881
35882#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
35883#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
35888#define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)
35889
35890#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
35891#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
35896#define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
35897
35898#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
35899#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
35900#define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)
35901
35902#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
35903#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
35904#define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)
35905
35906#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)
35907#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U)
35908#define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)
35909
35910#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
35911#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
35916#define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)
35917
35918#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
35919#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
35926#define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
35927
35928#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
35929#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
35936#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
35937
35938#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
35939#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
35946#define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)
35947
35948#define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
35949#define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
35956#define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK) /* end of group PMU_Register_Masks */
35963
35964
35965/* PMU - Peripheral instance base addresses */
35967#define PMU_BASE (0x400D8000u)
35969#define PMU ((PMU_Type *)PMU_BASE)
35971#define PMU_BASE_ADDRS { PMU_BASE }
35973#define PMU_BASE_PTRS { PMU }
35974 /* end of group PMU_Peripheral_Access_Layer */
35978
35979
35980/* ----------------------------------------------------------------------------
35981 -- PWM Peripheral Access Layer
35982 ---------------------------------------------------------------------------- */
35983
35990typedef struct {
35991 struct { /* offset: 0x0, array step: 0x60 */
35992 __I uint16_t CNT;
35993 __IO uint16_t INIT;
35994 __IO uint16_t CTRL2;
35995 __IO uint16_t CTRL;
35996 uint8_t RESERVED_0[2];
35997 __IO uint16_t VAL0;
35998 __IO uint16_t FRACVAL1;
35999 __IO uint16_t VAL1;
36000 __IO uint16_t FRACVAL2;
36001 __IO uint16_t VAL2;
36002 __IO uint16_t FRACVAL3;
36003 __IO uint16_t VAL3;
36004 __IO uint16_t FRACVAL4;
36005 __IO uint16_t VAL4;
36006 __IO uint16_t FRACVAL5;
36007 __IO uint16_t VAL5;
36008 __IO uint16_t FRCTRL;
36009 __IO uint16_t OCTRL;
36010 __IO uint16_t STS;
36011 __IO uint16_t INTEN;
36012 __IO uint16_t DMAEN;
36013 __IO uint16_t TCTRL;
36014 __IO uint16_t DISMAP[2];
36015 __IO uint16_t DTCNT0;
36016 __IO uint16_t DTCNT1;
36017 __IO uint16_t CAPTCTRLA;
36018 __IO uint16_t CAPTCOMPA;
36019 __IO uint16_t CAPTCTRLB;
36020 __IO uint16_t CAPTCOMPB;
36021 __IO uint16_t CAPTCTRLX;
36022 __IO uint16_t CAPTCOMPX;
36023 __I uint16_t CVAL0;
36024 __I uint16_t CVAL0CYC;
36025 __I uint16_t CVAL1;
36026 __I uint16_t CVAL1CYC;
36027 __I uint16_t CVAL2;
36028 __I uint16_t CVAL2CYC;
36029 __I uint16_t CVAL3;
36030 __I uint16_t CVAL3CYC;
36031 __I uint16_t CVAL4;
36032 __I uint16_t CVAL4CYC;
36033 __I uint16_t CVAL5;
36034 __I uint16_t CVAL5CYC;
36035 uint8_t RESERVED_1[8];
36036 } SM[4];
36037 __IO uint16_t OUTEN;
36038 __IO uint16_t MASK;
36039 __IO uint16_t SWCOUT;
36040 __IO uint16_t DTSRCSEL;
36041 __IO uint16_t MCTRL;
36042 __IO uint16_t MCTRL2;
36043 __IO uint16_t FCTRL;
36044 __IO uint16_t FSTS;
36045 __IO uint16_t FFILT;
36046 __IO uint16_t FTST;
36047 __IO uint16_t FCTRL2;
36048} PWM_Type;
36049
36050/* ----------------------------------------------------------------------------
36051 -- PWM Register Masks
36052 ---------------------------------------------------------------------------- */
36053
36062#define PWM_CNT_CNT_MASK (0xFFFFU)
36063#define PWM_CNT_CNT_SHIFT (0U)
36066#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
36069/* The count of PWM_CNT */
36070#define PWM_CNT_COUNT (4U)
36071
36075#define PWM_INIT_INIT_MASK (0xFFFFU)
36076#define PWM_INIT_INIT_SHIFT (0U)
36079#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
36082/* The count of PWM_INIT */
36083#define PWM_INIT_COUNT (4U)
36084
36088#define PWM_CTRL2_CLK_SEL_MASK (0x3U)
36089#define PWM_CTRL2_CLK_SEL_SHIFT (0U)
36097#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
36098
36099#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
36100#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
36106#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
36107
36108#define PWM_CTRL2_FORCE_SEL_MASK (0x38U)
36109#define PWM_CTRL2_FORCE_SEL_SHIFT (3U)
36123#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
36124
36125#define PWM_CTRL2_FORCE_MASK (0x40U)
36126#define PWM_CTRL2_FORCE_SHIFT (6U)
36129#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
36130
36131#define PWM_CTRL2_FRCEN_MASK (0x80U)
36132#define PWM_CTRL2_FRCEN_SHIFT (7U)
36137#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
36138
36139#define PWM_CTRL2_INIT_SEL_MASK (0x300U)
36140#define PWM_CTRL2_INIT_SEL_SHIFT (8U)
36150#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
36151
36152#define PWM_CTRL2_PWMX_INIT_MASK (0x400U)
36153#define PWM_CTRL2_PWMX_INIT_SHIFT (10U)
36156#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
36157
36158#define PWM_CTRL2_PWM45_INIT_MASK (0x800U)
36159#define PWM_CTRL2_PWM45_INIT_SHIFT (11U)
36162#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
36163
36164#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
36165#define PWM_CTRL2_PWM23_INIT_SHIFT (12U)
36168#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
36169
36170#define PWM_CTRL2_INDEP_MASK (0x2000U)
36171#define PWM_CTRL2_INDEP_SHIFT (13U)
36176#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
36177
36178#define PWM_CTRL2_WAITEN_MASK (0x4000U)
36179#define PWM_CTRL2_WAITEN_SHIFT (14U)
36182#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
36183
36184#define PWM_CTRL2_DBGEN_MASK (0x8000U)
36185#define PWM_CTRL2_DBGEN_SHIFT (15U)
36188#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
36191/* The count of PWM_CTRL2 */
36192#define PWM_CTRL2_COUNT (4U)
36193
36197#define PWM_CTRL_DBLEN_MASK (0x1U)
36198#define PWM_CTRL_DBLEN_SHIFT (0U)
36203#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
36204
36205#define PWM_CTRL_DBLX_MASK (0x2U)
36206#define PWM_CTRL_DBLX_SHIFT (1U)
36211#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
36212
36213#define PWM_CTRL_LDMOD_MASK (0x4U)
36214#define PWM_CTRL_LDMOD_SHIFT (2U)
36220#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
36221
36222#define PWM_CTRL_SPLIT_MASK (0x8U)
36223#define PWM_CTRL_SPLIT_SHIFT (3U)
36228#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
36229
36230#define PWM_CTRL_PRSC_MASK (0x70U)
36231#define PWM_CTRL_PRSC_SHIFT (4U)
36242#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
36243
36244#define PWM_CTRL_COMPMODE_MASK (0x80U)
36245#define PWM_CTRL_COMPMODE_SHIFT (7U)
36256#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
36257
36258#define PWM_CTRL_DT_MASK (0x300U)
36259#define PWM_CTRL_DT_SHIFT (8U)
36262#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
36263
36264#define PWM_CTRL_FULL_MASK (0x400U)
36265#define PWM_CTRL_FULL_SHIFT (10U)
36270#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
36271
36272#define PWM_CTRL_HALF_MASK (0x800U)
36273#define PWM_CTRL_HALF_SHIFT (11U)
36278#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
36279
36280#define PWM_CTRL_LDFQ_MASK (0xF000U)
36281#define PWM_CTRL_LDFQ_SHIFT (12U)
36300#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
36303/* The count of PWM_CTRL */
36304#define PWM_CTRL_COUNT (4U)
36305
36309#define PWM_VAL0_VAL0_MASK (0xFFFFU)
36310#define PWM_VAL0_VAL0_SHIFT (0U)
36313#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
36316/* The count of PWM_VAL0 */
36317#define PWM_VAL0_COUNT (4U)
36318
36322#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)
36323#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U)
36326#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
36329/* The count of PWM_FRACVAL1 */
36330#define PWM_FRACVAL1_COUNT (4U)
36331
36335#define PWM_VAL1_VAL1_MASK (0xFFFFU)
36336#define PWM_VAL1_VAL1_SHIFT (0U)
36339#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
36342/* The count of PWM_VAL1 */
36343#define PWM_VAL1_COUNT (4U)
36344
36348#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)
36349#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U)
36352#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
36355/* The count of PWM_FRACVAL2 */
36356#define PWM_FRACVAL2_COUNT (4U)
36357
36361#define PWM_VAL2_VAL2_MASK (0xFFFFU)
36362#define PWM_VAL2_VAL2_SHIFT (0U)
36365#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
36368/* The count of PWM_VAL2 */
36369#define PWM_VAL2_COUNT (4U)
36370
36374#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)
36375#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U)
36378#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
36381/* The count of PWM_FRACVAL3 */
36382#define PWM_FRACVAL3_COUNT (4U)
36383
36387#define PWM_VAL3_VAL3_MASK (0xFFFFU)
36388#define PWM_VAL3_VAL3_SHIFT (0U)
36391#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
36394/* The count of PWM_VAL3 */
36395#define PWM_VAL3_COUNT (4U)
36396
36400#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)
36401#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U)
36404#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
36407/* The count of PWM_FRACVAL4 */
36408#define PWM_FRACVAL4_COUNT (4U)
36409
36413#define PWM_VAL4_VAL4_MASK (0xFFFFU)
36414#define PWM_VAL4_VAL4_SHIFT (0U)
36417#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
36420/* The count of PWM_VAL4 */
36421#define PWM_VAL4_COUNT (4U)
36422
36426#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)
36427#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U)
36430#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
36433/* The count of PWM_FRACVAL5 */
36434#define PWM_FRACVAL5_COUNT (4U)
36435
36439#define PWM_VAL5_VAL5_MASK (0xFFFFU)
36440#define PWM_VAL5_VAL5_SHIFT (0U)
36443#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
36446/* The count of PWM_VAL5 */
36447#define PWM_VAL5_COUNT (4U)
36448
36452#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U)
36453#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U)
36458#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
36459
36460#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U)
36461#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U)
36466#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
36467
36468#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U)
36469#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U)
36474#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
36475
36476#define PWM_FRCTRL_FRAC_PU_MASK (0x100U)
36477#define PWM_FRCTRL_FRAC_PU_SHIFT (8U)
36482#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
36483
36484#define PWM_FRCTRL_TEST_MASK (0x8000U)
36485#define PWM_FRCTRL_TEST_SHIFT (15U)
36488#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
36491/* The count of PWM_FRCTRL */
36492#define PWM_FRCTRL_COUNT (4U)
36493
36497#define PWM_OCTRL_PWMXFS_MASK (0x3U)
36498#define PWM_OCTRL_PWMXFS_SHIFT (0U)
36505#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
36506
36507#define PWM_OCTRL_PWMBFS_MASK (0xCU)
36508#define PWM_OCTRL_PWMBFS_SHIFT (2U)
36515#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
36516
36517#define PWM_OCTRL_PWMAFS_MASK (0x30U)
36518#define PWM_OCTRL_PWMAFS_SHIFT (4U)
36525#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
36526
36527#define PWM_OCTRL_POLX_MASK (0x100U)
36528#define PWM_OCTRL_POLX_SHIFT (8U)
36533#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
36534
36535#define PWM_OCTRL_POLB_MASK (0x200U)
36536#define PWM_OCTRL_POLB_SHIFT (9U)
36541#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
36542
36543#define PWM_OCTRL_POLA_MASK (0x400U)
36544#define PWM_OCTRL_POLA_SHIFT (10U)
36549#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
36550
36551#define PWM_OCTRL_PWMX_IN_MASK (0x2000U)
36552#define PWM_OCTRL_PWMX_IN_SHIFT (13U)
36555#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
36556
36557#define PWM_OCTRL_PWMB_IN_MASK (0x4000U)
36558#define PWM_OCTRL_PWMB_IN_SHIFT (14U)
36561#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
36562
36563#define PWM_OCTRL_PWMA_IN_MASK (0x8000U)
36564#define PWM_OCTRL_PWMA_IN_SHIFT (15U)
36567#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
36570/* The count of PWM_OCTRL */
36571#define PWM_OCTRL_COUNT (4U)
36572
36576#define PWM_STS_CMPF_MASK (0x3FU)
36577#define PWM_STS_CMPF_SHIFT (0U)
36582#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
36583
36584#define PWM_STS_CFX0_MASK (0x40U)
36585#define PWM_STS_CFX0_SHIFT (6U)
36588#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
36589
36590#define PWM_STS_CFX1_MASK (0x80U)
36591#define PWM_STS_CFX1_SHIFT (7U)
36594#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
36595
36596#define PWM_STS_CFB0_MASK (0x100U)
36597#define PWM_STS_CFB0_SHIFT (8U)
36600#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
36601
36602#define PWM_STS_CFB1_MASK (0x200U)
36603#define PWM_STS_CFB1_SHIFT (9U)
36606#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
36607
36608#define PWM_STS_CFA0_MASK (0x400U)
36609#define PWM_STS_CFA0_SHIFT (10U)
36612#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
36613
36614#define PWM_STS_CFA1_MASK (0x800U)
36615#define PWM_STS_CFA1_SHIFT (11U)
36618#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
36619
36620#define PWM_STS_RF_MASK (0x1000U)
36621#define PWM_STS_RF_SHIFT (12U)
36626#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
36627
36628#define PWM_STS_REF_MASK (0x2000U)
36629#define PWM_STS_REF_SHIFT (13U)
36634#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
36635
36636#define PWM_STS_RUF_MASK (0x4000U)
36637#define PWM_STS_RUF_SHIFT (14U)
36642#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
36645/* The count of PWM_STS */
36646#define PWM_STS_COUNT (4U)
36647
36651#define PWM_INTEN_CMPIE_MASK (0x3FU)
36652#define PWM_INTEN_CMPIE_SHIFT (0U)
36657#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
36658
36659#define PWM_INTEN_CX0IE_MASK (0x40U)
36660#define PWM_INTEN_CX0IE_SHIFT (6U)
36665#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
36666
36667#define PWM_INTEN_CX1IE_MASK (0x80U)
36668#define PWM_INTEN_CX1IE_SHIFT (7U)
36673#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
36674
36675#define PWM_INTEN_CB0IE_MASK (0x100U)
36676#define PWM_INTEN_CB0IE_SHIFT (8U)
36681#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
36682
36683#define PWM_INTEN_CB1IE_MASK (0x200U)
36684#define PWM_INTEN_CB1IE_SHIFT (9U)
36689#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
36690
36691#define PWM_INTEN_CA0IE_MASK (0x400U)
36692#define PWM_INTEN_CA0IE_SHIFT (10U)
36697#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
36698
36699#define PWM_INTEN_CA1IE_MASK (0x800U)
36700#define PWM_INTEN_CA1IE_SHIFT (11U)
36705#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
36706
36707#define PWM_INTEN_RIE_MASK (0x1000U)
36708#define PWM_INTEN_RIE_SHIFT (12U)
36713#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
36714
36715#define PWM_INTEN_REIE_MASK (0x2000U)
36716#define PWM_INTEN_REIE_SHIFT (13U)
36721#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
36724/* The count of PWM_INTEN */
36725#define PWM_INTEN_COUNT (4U)
36726
36730#define PWM_DMAEN_CX0DE_MASK (0x1U)
36731#define PWM_DMAEN_CX0DE_SHIFT (0U)
36734#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
36735
36736#define PWM_DMAEN_CX1DE_MASK (0x2U)
36737#define PWM_DMAEN_CX1DE_SHIFT (1U)
36740#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
36741
36742#define PWM_DMAEN_CB0DE_MASK (0x4U)
36743#define PWM_DMAEN_CB0DE_SHIFT (2U)
36746#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
36747
36748#define PWM_DMAEN_CB1DE_MASK (0x8U)
36749#define PWM_DMAEN_CB1DE_SHIFT (3U)
36752#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
36753
36754#define PWM_DMAEN_CA0DE_MASK (0x10U)
36755#define PWM_DMAEN_CA0DE_SHIFT (4U)
36758#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
36759
36760#define PWM_DMAEN_CA1DE_MASK (0x20U)
36761#define PWM_DMAEN_CA1DE_SHIFT (5U)
36764#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
36765
36766#define PWM_DMAEN_CAPTDE_MASK (0xC0U)
36767#define PWM_DMAEN_CAPTDE_SHIFT (6U)
36776#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
36777
36778#define PWM_DMAEN_FAND_MASK (0x100U)
36779#define PWM_DMAEN_FAND_SHIFT (8U)
36784#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
36785
36786#define PWM_DMAEN_VALDE_MASK (0x200U)
36787#define PWM_DMAEN_VALDE_SHIFT (9U)
36792#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
36795/* The count of PWM_DMAEN */
36796#define PWM_DMAEN_COUNT (4U)
36797
36801#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
36802#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
36807#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
36808
36809#define PWM_TCTRL_TRGFRQ_MASK (0x1000U)
36810#define PWM_TCTRL_TRGFRQ_SHIFT (12U)
36816#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
36817
36818#define PWM_TCTRL_PWBOT1_MASK (0x4000U)
36819#define PWM_TCTRL_PWBOT1_SHIFT (14U)
36824#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
36825
36826#define PWM_TCTRL_PWAOT0_MASK (0x8000U)
36827#define PWM_TCTRL_PWAOT0_SHIFT (15U)
36832#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
36835/* The count of PWM_TCTRL */
36836#define PWM_TCTRL_COUNT (4U)
36837
36841#define PWM_DISMAP_DIS0A_MASK (0xFU)
36842#define PWM_DISMAP_DIS0A_SHIFT (0U)
36845#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
36846
36847#define PWM_DISMAP_DIS1A_MASK (0xFU)
36848#define PWM_DISMAP_DIS1A_SHIFT (0U)
36851#define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)
36852
36853#define PWM_DISMAP_DIS0B_MASK (0xF0U)
36854#define PWM_DISMAP_DIS0B_SHIFT (4U)
36857#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
36858
36859#define PWM_DISMAP_DIS1B_MASK (0xF0U)
36860#define PWM_DISMAP_DIS1B_SHIFT (4U)
36863#define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)
36864
36865#define PWM_DISMAP_DIS0X_MASK (0xF00U)
36866#define PWM_DISMAP_DIS0X_SHIFT (8U)
36869#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
36870
36871#define PWM_DISMAP_DIS1X_MASK (0xF00U)
36872#define PWM_DISMAP_DIS1X_SHIFT (8U)
36875#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)
36878/* The count of PWM_DISMAP */
36879#define PWM_DISMAP_COUNT (4U)
36880
36881/* The count of PWM_DISMAP */
36882#define PWM_DISMAP_COUNT2 (2U)
36883
36887#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)
36888#define PWM_DTCNT0_DTCNT0_SHIFT (0U)
36891#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
36894/* The count of PWM_DTCNT0 */
36895#define PWM_DTCNT0_COUNT (4U)
36896
36900#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)
36901#define PWM_DTCNT1_DTCNT1_SHIFT (0U)
36904#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
36907/* The count of PWM_DTCNT1 */
36908#define PWM_DTCNT1_COUNT (4U)
36909
36913#define PWM_CAPTCTRLA_ARMA_MASK (0x1U)
36914#define PWM_CAPTCTRLA_ARMA_SHIFT (0U)
36919#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
36920
36921#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)
36922#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)
36935#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
36936
36937#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU)
36938#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U)
36945#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
36946
36947#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U)
36948#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U)
36955#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
36956
36957#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)
36958#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)
36966#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
36967
36968#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)
36969#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)
36974#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
36975
36976#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U)
36977#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U)
36980#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
36981
36982#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)
36983#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)
36986#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
36987
36988#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)
36989#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)
36992#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
36995/* The count of PWM_CAPTCTRLA */
36996#define PWM_CAPTCTRLA_COUNT (4U)
36997
37001#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)
37002#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)
37005#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
37006
37007#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)
37008#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)
37011#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
37014/* The count of PWM_CAPTCOMPA */
37015#define PWM_CAPTCOMPA_COUNT (4U)
37016
37020#define PWM_CAPTCTRLB_ARMB_MASK (0x1U)
37021#define PWM_CAPTCTRLB_ARMB_SHIFT (0U)
37026#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
37027
37028#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)
37029#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)
37042#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
37043
37044#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU)
37045#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U)
37052#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
37053
37054#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U)
37055#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U)
37062#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
37063
37064#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)
37065#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)
37073#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
37074
37075#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)
37076#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)
37081#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
37082
37083#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U)
37084#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U)
37087#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
37088
37089#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)
37090#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)
37093#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
37094
37095#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)
37096#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)
37099#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
37102/* The count of PWM_CAPTCTRLB */
37103#define PWM_CAPTCTRLB_COUNT (4U)
37104
37108#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)
37109#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)
37112#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
37113
37114#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)
37115#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)
37118#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
37121/* The count of PWM_CAPTCOMPB */
37122#define PWM_CAPTCOMPB_COUNT (4U)
37123
37127#define PWM_CAPTCTRLX_ARMX_MASK (0x1U)
37128#define PWM_CAPTCTRLX_ARMX_SHIFT (0U)
37133#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
37134
37135#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
37136#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
37149#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
37150
37151#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
37152#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
37159#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
37160
37161#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
37162#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
37169#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
37170
37171#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
37172#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
37180#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
37181
37182#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
37183#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
37188#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
37189
37190#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
37191#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
37194#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
37195
37196#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
37197#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
37200#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
37201
37202#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
37203#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
37206#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
37209/* The count of PWM_CAPTCTRLX */
37210#define PWM_CAPTCTRLX_COUNT (4U)
37211
37215#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
37216#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
37219#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
37220
37221#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
37222#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
37225#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
37228/* The count of PWM_CAPTCOMPX */
37229#define PWM_CAPTCOMPX_COUNT (4U)
37230
37234#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
37235#define PWM_CVAL0_CAPTVAL0_SHIFT (0U)
37238#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
37241/* The count of PWM_CVAL0 */
37242#define PWM_CVAL0_COUNT (4U)
37243
37247#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
37248#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
37251#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
37254/* The count of PWM_CVAL0CYC */
37255#define PWM_CVAL0CYC_COUNT (4U)
37256
37260#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
37261#define PWM_CVAL1_CAPTVAL1_SHIFT (0U)
37264#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
37267/* The count of PWM_CVAL1 */
37268#define PWM_CVAL1_COUNT (4U)
37269
37273#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
37274#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
37277#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
37280/* The count of PWM_CVAL1CYC */
37281#define PWM_CVAL1CYC_COUNT (4U)
37282
37286#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)
37287#define PWM_CVAL2_CAPTVAL2_SHIFT (0U)
37290#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
37293/* The count of PWM_CVAL2 */
37294#define PWM_CVAL2_COUNT (4U)
37295
37299#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)
37300#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)
37303#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
37306/* The count of PWM_CVAL2CYC */
37307#define PWM_CVAL2CYC_COUNT (4U)
37308
37312#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)
37313#define PWM_CVAL3_CAPTVAL3_SHIFT (0U)
37316#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
37319/* The count of PWM_CVAL3 */
37320#define PWM_CVAL3_COUNT (4U)
37321
37325#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)
37326#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)
37329#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
37332/* The count of PWM_CVAL3CYC */
37333#define PWM_CVAL3CYC_COUNT (4U)
37334
37338#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)
37339#define PWM_CVAL4_CAPTVAL4_SHIFT (0U)
37342#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
37345/* The count of PWM_CVAL4 */
37346#define PWM_CVAL4_COUNT (4U)
37347
37351#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)
37352#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)
37355#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
37358/* The count of PWM_CVAL4CYC */
37359#define PWM_CVAL4CYC_COUNT (4U)
37360
37364#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)
37365#define PWM_CVAL5_CAPTVAL5_SHIFT (0U)
37368#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
37371/* The count of PWM_CVAL5 */
37372#define PWM_CVAL5_COUNT (4U)
37373
37377#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)
37378#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)
37381#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
37384/* The count of PWM_CVAL5CYC */
37385#define PWM_CVAL5CYC_COUNT (4U)
37386
37390#define PWM_OUTEN_PWMX_EN_MASK (0xFU)
37391#define PWM_OUTEN_PWMX_EN_SHIFT (0U)
37396#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
37397
37398#define PWM_OUTEN_PWMB_EN_MASK (0xF0U)
37399#define PWM_OUTEN_PWMB_EN_SHIFT (4U)
37404#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
37405
37406#define PWM_OUTEN_PWMA_EN_MASK (0xF00U)
37407#define PWM_OUTEN_PWMA_EN_SHIFT (8U)
37412#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
37418#define PWM_MASK_MASKX_MASK (0xFU)
37419#define PWM_MASK_MASKX_SHIFT (0U)
37424#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
37425
37426#define PWM_MASK_MASKB_MASK (0xF0U)
37427#define PWM_MASK_MASKB_SHIFT (4U)
37432#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
37433
37434#define PWM_MASK_MASKA_MASK (0xF00U)
37435#define PWM_MASK_MASKA_SHIFT (8U)
37440#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
37446#define PWM_SWCOUT_SM0OUT45_MASK (0x1U)
37447#define PWM_SWCOUT_SM0OUT45_SHIFT (0U)
37452#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
37453
37454#define PWM_SWCOUT_SM0OUT23_MASK (0x2U)
37455#define PWM_SWCOUT_SM0OUT23_SHIFT (1U)
37460#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
37461
37462#define PWM_SWCOUT_SM1OUT45_MASK (0x4U)
37463#define PWM_SWCOUT_SM1OUT45_SHIFT (2U)
37468#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
37469
37470#define PWM_SWCOUT_SM1OUT23_MASK (0x8U)
37471#define PWM_SWCOUT_SM1OUT23_SHIFT (3U)
37476#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
37477
37478#define PWM_SWCOUT_SM2OUT45_MASK (0x10U)
37479#define PWM_SWCOUT_SM2OUT45_SHIFT (4U)
37484#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
37485
37486#define PWM_SWCOUT_SM2OUT23_MASK (0x20U)
37487#define PWM_SWCOUT_SM2OUT23_SHIFT (5U)
37492#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
37493
37494#define PWM_SWCOUT_SM3OUT45_MASK (0x40U)
37495#define PWM_SWCOUT_SM3OUT45_SHIFT (6U)
37500#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
37501
37502#define PWM_SWCOUT_SM3OUT23_MASK (0x80U)
37503#define PWM_SWCOUT_SM3OUT23_SHIFT (7U)
37508#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
37514#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
37515#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
37522#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
37523
37524#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
37525#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
37532#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
37533
37534#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
37535#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
37542#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
37543
37544#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
37545#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
37552#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
37553
37554#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
37555#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
37562#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
37563
37564#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
37565#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
37572#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
37573
37574#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)
37575#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)
37582#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
37583
37584#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)
37585#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)
37592#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
37598#define PWM_MCTRL_LDOK_MASK (0xFU)
37599#define PWM_MCTRL_LDOK_SHIFT (0U)
37604#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
37605
37606#define PWM_MCTRL_CLDOK_MASK (0xF0U)
37607#define PWM_MCTRL_CLDOK_SHIFT (4U)
37610#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
37611
37612#define PWM_MCTRL_RUN_MASK (0xF00U)
37613#define PWM_MCTRL_RUN_SHIFT (8U)
37618#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
37619
37620#define PWM_MCTRL_IPOL_MASK (0xF000U)
37621#define PWM_MCTRL_IPOL_SHIFT (12U)
37626#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
37632#define PWM_MCTRL2_MONPLL_MASK (0x3U)
37633#define PWM_MCTRL2_MONPLL_SHIFT (0U)
37642#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
37648#define PWM_FCTRL_FIE_MASK (0xFU)
37649#define PWM_FCTRL_FIE_SHIFT (0U)
37654#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
37655
37656#define PWM_FCTRL_FSAFE_MASK (0xF0U)
37657#define PWM_FCTRL_FSAFE_SHIFT (4U)
37669#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
37670
37671#define PWM_FCTRL_FAUTO_MASK (0xF00U)
37672#define PWM_FCTRL_FAUTO_SHIFT (8U)
37683#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
37684
37685#define PWM_FCTRL_FLVL_MASK (0xF000U)
37686#define PWM_FCTRL_FLVL_SHIFT (12U)
37691#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
37697#define PWM_FSTS_FFLAG_MASK (0xFU)
37698#define PWM_FSTS_FFLAG_SHIFT (0U)
37703#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
37704
37705#define PWM_FSTS_FFULL_MASK (0xF0U)
37706#define PWM_FSTS_FFULL_SHIFT (4U)
37711#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
37712
37713#define PWM_FSTS_FFPIN_MASK (0xF00U)
37714#define PWM_FSTS_FFPIN_SHIFT (8U)
37717#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
37718
37719#define PWM_FSTS_FHALF_MASK (0xF000U)
37720#define PWM_FSTS_FHALF_SHIFT (12U)
37725#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
37731#define PWM_FFILT_FILT_PER_MASK (0xFFU)
37732#define PWM_FFILT_FILT_PER_SHIFT (0U)
37735#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
37736
37737#define PWM_FFILT_FILT_CNT_MASK (0x700U)
37738#define PWM_FFILT_FILT_CNT_SHIFT (8U)
37741#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
37742
37743#define PWM_FFILT_GSTR_MASK (0x8000U)
37744#define PWM_FFILT_GSTR_SHIFT (15U)
37749#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
37755#define PWM_FTST_FTEST_MASK (0x1U)
37756#define PWM_FTST_FTEST_SHIFT (0U)
37761#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
37767#define PWM_FCTRL2_NOCOMB_MASK (0xFU)
37768#define PWM_FCTRL2_NOCOMB_SHIFT (0U)
37775#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) /* end of group PWM_Register_Masks */
37782
37783
37784/* PWM - Peripheral instance base addresses */
37786#define PWM1_BASE (0x403DC000u)
37788#define PWM1 ((PWM_Type *)PWM1_BASE)
37790#define PWM2_BASE (0x403E0000u)
37792#define PWM2 ((PWM_Type *)PWM2_BASE)
37794#define PWM3_BASE (0x403E4000u)
37796#define PWM3 ((PWM_Type *)PWM3_BASE)
37798#define PWM4_BASE (0x403E8000u)
37800#define PWM4 ((PWM_Type *)PWM4_BASE)
37802#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
37804#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
37806#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
37807#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
37808#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
37809#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
37810#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
37811 /* end of group PWM_Peripheral_Access_Layer */
37815
37816
37817/* ----------------------------------------------------------------------------
37818 -- PXP Peripheral Access Layer
37819 ---------------------------------------------------------------------------- */
37820
37827typedef struct {
37828 __IO uint32_t CTRL;
37829 __IO uint32_t CTRL_SET;
37830 __IO uint32_t CTRL_CLR;
37831 __IO uint32_t CTRL_TOG;
37832 __IO uint32_t STAT;
37833 __IO uint32_t STAT_SET;
37834 __IO uint32_t STAT_CLR;
37835 __IO uint32_t STAT_TOG;
37836 __IO uint32_t OUT_CTRL;
37837 __IO uint32_t OUT_CTRL_SET;
37838 __IO uint32_t OUT_CTRL_CLR;
37839 __IO uint32_t OUT_CTRL_TOG;
37840 __IO uint32_t OUT_BUF;
37841 uint8_t RESERVED_0[12];
37842 __IO uint32_t OUT_BUF2;
37843 uint8_t RESERVED_1[12];
37844 __IO uint32_t OUT_PITCH;
37845 uint8_t RESERVED_2[12];
37846 __IO uint32_t OUT_LRC;
37847 uint8_t RESERVED_3[12];
37848 __IO uint32_t OUT_PS_ULC;
37849 uint8_t RESERVED_4[12];
37850 __IO uint32_t OUT_PS_LRC;
37851 uint8_t RESERVED_5[12];
37852 __IO uint32_t OUT_AS_ULC;
37853 uint8_t RESERVED_6[12];
37854 __IO uint32_t OUT_AS_LRC;
37855 uint8_t RESERVED_7[12];
37856 __IO uint32_t PS_CTRL;
37857 __IO uint32_t PS_CTRL_SET;
37858 __IO uint32_t PS_CTRL_CLR;
37859 __IO uint32_t PS_CTRL_TOG;
37860 __IO uint32_t PS_BUF;
37861 uint8_t RESERVED_8[12];
37862 __IO uint32_t PS_UBUF;
37863 uint8_t RESERVED_9[12];
37864 __IO uint32_t PS_VBUF;
37865 uint8_t RESERVED_10[12];
37866 __IO uint32_t PS_PITCH;
37867 uint8_t RESERVED_11[12];
37868 __IO uint32_t PS_BACKGROUND;
37869 uint8_t RESERVED_12[12];
37870 __IO uint32_t PS_SCALE;
37871 uint8_t RESERVED_13[12];
37872 __IO uint32_t PS_OFFSET;
37873 uint8_t RESERVED_14[12];
37874 __IO uint32_t PS_CLRKEYLOW;
37875 uint8_t RESERVED_15[12];
37876 __IO uint32_t PS_CLRKEYHIGH;
37877 uint8_t RESERVED_16[12];
37878 __IO uint32_t AS_CTRL;
37879 uint8_t RESERVED_17[12];
37880 __IO uint32_t AS_BUF;
37881 uint8_t RESERVED_18[12];
37882 __IO uint32_t AS_PITCH;
37883 uint8_t RESERVED_19[12];
37884 __IO uint32_t AS_CLRKEYLOW;
37885 uint8_t RESERVED_20[12];
37886 __IO uint32_t AS_CLRKEYHIGH;
37887 uint8_t RESERVED_21[12];
37888 __IO uint32_t CSC1_COEF0;
37889 uint8_t RESERVED_22[12];
37890 __IO uint32_t CSC1_COEF1;
37891 uint8_t RESERVED_23[12];
37892 __IO uint32_t CSC1_COEF2;
37893 uint8_t RESERVED_24[348];
37894 __IO uint32_t POWER;
37895 uint8_t RESERVED_25[220];
37896 __IO uint32_t NEXT;
37897 uint8_t RESERVED_26[60];
37898 __IO uint32_t PORTER_DUFF_CTRL;
37899} PXP_Type;
37900
37901/* ----------------------------------------------------------------------------
37902 -- PXP Register Masks
37903 ---------------------------------------------------------------------------- */
37904
37913#define PXP_CTRL_ENABLE_MASK (0x1U)
37914#define PXP_CTRL_ENABLE_SHIFT (0U)
37919#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
37920
37921#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U)
37922#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U)
37927#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
37928
37929#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)
37930#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)
37935#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
37936
37937#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
37938#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
37939#define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
37940
37941#define PXP_CTRL_ROTATE_MASK (0x300U)
37942#define PXP_CTRL_ROTATE_SHIFT (8U)
37949#define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
37950
37951#define PXP_CTRL_HFLIP_MASK (0x400U)
37952#define PXP_CTRL_HFLIP_SHIFT (10U)
37957#define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
37958
37959#define PXP_CTRL_VFLIP_MASK (0x800U)
37960#define PXP_CTRL_VFLIP_SHIFT (11U)
37965#define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
37966
37967#define PXP_CTRL_ROT_POS_MASK (0x400000U)
37968#define PXP_CTRL_ROT_POS_SHIFT (22U)
37969#define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
37970
37971#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)
37972#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U)
37977#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
37978
37979#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U)
37980#define PXP_CTRL_EN_REPEAT_SHIFT (28U)
37985#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
37986
37987#define PXP_CTRL_CLKGATE_MASK (0x40000000U)
37988#define PXP_CTRL_CLKGATE_SHIFT (30U)
37993#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
37994
37995#define PXP_CTRL_SFTRST_MASK (0x80000000U)
37996#define PXP_CTRL_SFTRST_SHIFT (31U)
38001#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
38007#define PXP_CTRL_SET_ENABLE_MASK (0x1U)
38008#define PXP_CTRL_SET_ENABLE_SHIFT (0U)
38013#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
38014
38015#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)
38016#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)
38021#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
38022
38023#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)
38024#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)
38029#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
38030
38031#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
38032#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
38033#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
38034
38035#define PXP_CTRL_SET_ROTATE_MASK (0x300U)
38036#define PXP_CTRL_SET_ROTATE_SHIFT (8U)
38043#define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
38044
38045#define PXP_CTRL_SET_HFLIP_MASK (0x400U)
38046#define PXP_CTRL_SET_HFLIP_SHIFT (10U)
38051#define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
38052
38053#define PXP_CTRL_SET_VFLIP_MASK (0x800U)
38054#define PXP_CTRL_SET_VFLIP_SHIFT (11U)
38059#define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
38060
38061#define PXP_CTRL_SET_ROT_POS_MASK (0x400000U)
38062#define PXP_CTRL_SET_ROT_POS_SHIFT (22U)
38063#define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
38064
38065#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)
38066#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)
38071#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
38072
38073#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)
38074#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)
38079#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
38080
38081#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U)
38082#define PXP_CTRL_SET_CLKGATE_SHIFT (30U)
38087#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
38088
38089#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U)
38090#define PXP_CTRL_SET_SFTRST_SHIFT (31U)
38095#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
38101#define PXP_CTRL_CLR_ENABLE_MASK (0x1U)
38102#define PXP_CTRL_CLR_ENABLE_SHIFT (0U)
38107#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
38108
38109#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)
38110#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)
38115#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
38116
38117#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)
38118#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)
38123#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
38124
38125#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
38126#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
38127#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
38128
38129#define PXP_CTRL_CLR_ROTATE_MASK (0x300U)
38130#define PXP_CTRL_CLR_ROTATE_SHIFT (8U)
38137#define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
38138
38139#define PXP_CTRL_CLR_HFLIP_MASK (0x400U)
38140#define PXP_CTRL_CLR_HFLIP_SHIFT (10U)
38145#define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
38146
38147#define PXP_CTRL_CLR_VFLIP_MASK (0x800U)
38148#define PXP_CTRL_CLR_VFLIP_SHIFT (11U)
38153#define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
38154
38155#define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)
38156#define PXP_CTRL_CLR_ROT_POS_SHIFT (22U)
38157#define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
38158
38159#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)
38160#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)
38165#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
38166
38167#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)
38168#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)
38173#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
38174
38175#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
38176#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U)
38181#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
38182
38183#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)
38184#define PXP_CTRL_CLR_SFTRST_SHIFT (31U)
38189#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
38195#define PXP_CTRL_TOG_ENABLE_MASK (0x1U)
38196#define PXP_CTRL_TOG_ENABLE_SHIFT (0U)
38201#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
38202
38203#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)
38204#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)
38209#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
38210
38211#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)
38212#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)
38217#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
38218
38219#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
38220#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
38221#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
38222
38223#define PXP_CTRL_TOG_ROTATE_MASK (0x300U)
38224#define PXP_CTRL_TOG_ROTATE_SHIFT (8U)
38231#define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
38232
38233#define PXP_CTRL_TOG_HFLIP_MASK (0x400U)
38234#define PXP_CTRL_TOG_HFLIP_SHIFT (10U)
38239#define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
38240
38241#define PXP_CTRL_TOG_VFLIP_MASK (0x800U)
38242#define PXP_CTRL_TOG_VFLIP_SHIFT (11U)
38247#define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
38248
38249#define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)
38250#define PXP_CTRL_TOG_ROT_POS_SHIFT (22U)
38251#define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
38252
38253#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)
38254#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)
38259#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
38260
38261#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)
38262#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)
38267#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
38268
38269#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
38270#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U)
38275#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
38276
38277#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)
38278#define PXP_CTRL_TOG_SFTRST_SHIFT (31U)
38283#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
38289#define PXP_STAT_IRQ_MASK (0x1U)
38290#define PXP_STAT_IRQ_SHIFT (0U)
38295#define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
38296
38297#define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)
38298#define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)
38303#define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
38304
38305#define PXP_STAT_AXI_READ_ERROR_MASK (0x4U)
38306#define PXP_STAT_AXI_READ_ERROR_SHIFT (2U)
38311#define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
38312
38313#define PXP_STAT_NEXT_IRQ_MASK (0x8U)
38314#define PXP_STAT_NEXT_IRQ_SHIFT (3U)
38315#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
38316
38317#define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U)
38318#define PXP_STAT_AXI_ERROR_ID_SHIFT (4U)
38319#define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
38320
38321#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
38322#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
38327#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
38328
38329#define PXP_STAT_BLOCKY_MASK (0xFF0000U)
38330#define PXP_STAT_BLOCKY_SHIFT (16U)
38331#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
38332
38333#define PXP_STAT_BLOCKX_MASK (0xFF000000U)
38334#define PXP_STAT_BLOCKX_SHIFT (24U)
38335#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
38341#define PXP_STAT_SET_IRQ_MASK (0x1U)
38342#define PXP_STAT_SET_IRQ_SHIFT (0U)
38347#define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
38348
38349#define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)
38350#define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)
38355#define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
38356
38357#define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)
38358#define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)
38363#define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
38364
38365#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)
38366#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)
38367#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
38368
38369#define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)
38370#define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)
38371#define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
38372
38373#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
38374#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
38379#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
38380
38381#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)
38382#define PXP_STAT_SET_BLOCKY_SHIFT (16U)
38383#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
38384
38385#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)
38386#define PXP_STAT_SET_BLOCKX_SHIFT (24U)
38387#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
38393#define PXP_STAT_CLR_IRQ_MASK (0x1U)
38394#define PXP_STAT_CLR_IRQ_SHIFT (0U)
38399#define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
38400
38401#define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)
38402#define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)
38407#define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
38408
38409#define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)
38410#define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)
38415#define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
38416
38417#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)
38418#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)
38419#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
38420
38421#define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)
38422#define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)
38423#define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
38424
38425#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
38426#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
38431#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
38432
38433#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)
38434#define PXP_STAT_CLR_BLOCKY_SHIFT (16U)
38435#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
38436
38437#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)
38438#define PXP_STAT_CLR_BLOCKX_SHIFT (24U)
38439#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
38445#define PXP_STAT_TOG_IRQ_MASK (0x1U)
38446#define PXP_STAT_TOG_IRQ_SHIFT (0U)
38451#define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
38452
38453#define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)
38454#define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)
38459#define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
38460
38461#define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)
38462#define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)
38467#define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
38468
38469#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)
38470#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)
38471#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
38472
38473#define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)
38474#define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)
38475#define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
38476
38477#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
38478#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
38483#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
38484
38485#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)
38486#define PXP_STAT_TOG_BLOCKY_SHIFT (16U)
38487#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
38488
38489#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)
38490#define PXP_STAT_TOG_BLOCKX_SHIFT (24U)
38491#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
38497#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU)
38498#define PXP_OUT_CTRL_FORMAT_SHIFT (0U)
38518#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
38519
38520#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)
38521#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)
38528#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
38529
38530#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)
38531#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)
38536#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
38537
38538#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)
38539#define PXP_OUT_CTRL_ALPHA_SHIFT (24U)
38540#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
38546#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)
38547#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)
38567#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
38568
38569#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)
38570#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
38577#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
38578
38579#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)
38580#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)
38585#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
38586
38587#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)
38588#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)
38589#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
38595#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)
38596#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)
38616#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
38617
38618#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)
38619#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
38626#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
38627
38628#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)
38629#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)
38634#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
38635
38636#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)
38637#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)
38638#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
38644#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)
38645#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)
38665#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
38666
38667#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)
38668#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
38675#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
38676
38677#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)
38678#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)
38683#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
38684
38685#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)
38686#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)
38687#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
38693#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)
38694#define PXP_OUT_BUF_ADDR_SHIFT (0U)
38695#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
38701#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)
38702#define PXP_OUT_BUF2_ADDR_SHIFT (0U)
38703#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
38709#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)
38710#define PXP_OUT_PITCH_PITCH_SHIFT (0U)
38711#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
38717#define PXP_OUT_LRC_Y_MASK (0x3FFFU)
38718#define PXP_OUT_LRC_Y_SHIFT (0U)
38719#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
38720
38721#define PXP_OUT_LRC_X_MASK (0x3FFF0000U)
38722#define PXP_OUT_LRC_X_SHIFT (16U)
38723#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
38729#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)
38730#define PXP_OUT_PS_ULC_Y_SHIFT (0U)
38731#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
38732
38733#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)
38734#define PXP_OUT_PS_ULC_X_SHIFT (16U)
38735#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
38741#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)
38742#define PXP_OUT_PS_LRC_Y_SHIFT (0U)
38743#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
38744
38745#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)
38746#define PXP_OUT_PS_LRC_X_SHIFT (16U)
38747#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
38753#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)
38754#define PXP_OUT_AS_ULC_Y_SHIFT (0U)
38755#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
38756
38757#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)
38758#define PXP_OUT_AS_ULC_X_SHIFT (16U)
38759#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
38765#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU)
38766#define PXP_OUT_AS_LRC_Y_SHIFT (0U)
38767#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
38768
38769#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)
38770#define PXP_OUT_AS_LRC_X_SHIFT (16U)
38771#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
38777#define PXP_PS_CTRL_FORMAT_MASK (0x3FU)
38778#define PXP_PS_CTRL_FORMAT_SHIFT (0U)
38799#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
38800
38801#define PXP_PS_CTRL_WB_SWAP_MASK (0x40U)
38802#define PXP_PS_CTRL_WB_SWAP_SHIFT (6U)
38807#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
38808
38809#define PXP_PS_CTRL_DECY_MASK (0x300U)
38810#define PXP_PS_CTRL_DECY_SHIFT (8U)
38817#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
38818
38819#define PXP_PS_CTRL_DECX_MASK (0xC00U)
38820#define PXP_PS_CTRL_DECX_SHIFT (10U)
38827#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
38833#define PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU)
38834#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)
38855#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
38856
38857#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U)
38858#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U)
38863#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
38864
38865#define PXP_PS_CTRL_SET_DECY_MASK (0x300U)
38866#define PXP_PS_CTRL_SET_DECY_SHIFT (8U)
38873#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
38874
38875#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U)
38876#define PXP_PS_CTRL_SET_DECX_SHIFT (10U)
38883#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
38889#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU)
38890#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)
38911#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
38912
38913#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U)
38914#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U)
38919#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
38920
38921#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U)
38922#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U)
38929#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
38930
38931#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)
38932#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U)
38939#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
38945#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU)
38946#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)
38967#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
38968
38969#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U)
38970#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U)
38975#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
38976
38977#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U)
38978#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U)
38985#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
38986
38987#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)
38988#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U)
38995#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
39001#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)
39002#define PXP_PS_BUF_ADDR_SHIFT (0U)
39003#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
39009#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)
39010#define PXP_PS_UBUF_ADDR_SHIFT (0U)
39011#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
39017#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)
39018#define PXP_PS_VBUF_ADDR_SHIFT (0U)
39019#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
39025#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU)
39026#define PXP_PS_PITCH_PITCH_SHIFT (0U)
39027#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
39033#define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)
39034#define PXP_PS_BACKGROUND_COLOR_SHIFT (0U)
39035#define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
39041#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU)
39042#define PXP_PS_SCALE_XSCALE_SHIFT (0U)
39043#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
39044
39045#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)
39046#define PXP_PS_SCALE_YSCALE_SHIFT (16U)
39047#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
39053#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)
39054#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U)
39055#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
39056
39057#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)
39058#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U)
39059#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
39065#define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
39066#define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)
39067#define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
39073#define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
39074#define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)
39075#define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
39081#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)
39082#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)
39090#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
39091
39092#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)
39093#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)
39098#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
39099
39100#define PXP_AS_CTRL_FORMAT_MASK (0xF0U)
39101#define PXP_AS_CTRL_FORMAT_SHIFT (4U)
39114#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
39115
39116#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U)
39117#define PXP_AS_CTRL_ALPHA_SHIFT (8U)
39118#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
39119
39120#define PXP_AS_CTRL_ROP_MASK (0xF0000U)
39121#define PXP_AS_CTRL_ROP_SHIFT (16U)
39136#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
39137
39138#define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)
39139#define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)
39144#define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
39150#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)
39151#define PXP_AS_BUF_ADDR_SHIFT (0U)
39152#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
39158#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU)
39159#define PXP_AS_PITCH_PITCH_SHIFT (0U)
39160#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
39166#define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
39167#define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)
39168#define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
39174#define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
39175#define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)
39176#define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
39182#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)
39183#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)
39184#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
39185
39186#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)
39187#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)
39188#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
39189
39190#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)
39191#define PXP_CSC1_COEF0_C0_SHIFT (18U)
39192#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
39193
39194#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)
39195#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U)
39196#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
39197
39198#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)
39199#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)
39204#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
39210#define PXP_CSC1_COEF1_C4_MASK (0x7FFU)
39211#define PXP_CSC1_COEF1_C4_SHIFT (0U)
39212#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
39213
39214#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U)
39215#define PXP_CSC1_COEF1_C1_SHIFT (16U)
39216#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
39222#define PXP_CSC1_COEF2_C3_MASK (0x7FFU)
39223#define PXP_CSC1_COEF2_C3_SHIFT (0U)
39224#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
39225
39226#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U)
39227#define PXP_CSC1_COEF2_C2_SHIFT (16U)
39228#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
39234#define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)
39235#define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)
39242#define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
39243
39244#define PXP_POWER_CTRL_MASK (0xFFFFF000U)
39245#define PXP_POWER_CTRL_SHIFT (12U)
39246#define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK)
39252#define PXP_NEXT_ENABLED_MASK (0x1U)
39253#define PXP_NEXT_ENABLED_SHIFT (0U)
39254#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
39255
39256#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)
39257#define PXP_NEXT_POINTER_SHIFT (2U)
39258#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
39264#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)
39265#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)
39270#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)
39271
39272#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
39273#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
39280#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
39281
39282#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
39283#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
39290#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
39291
39292#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)
39293#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
39298#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
39299
39300#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)
39301#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
39306#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
39307
39308#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
39309#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
39316#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
39317
39318#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
39319#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
39326#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
39327
39328#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)
39329#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
39334#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
39335
39336#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)
39337#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
39342#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
39343
39344#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
39345#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
39346#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
39347
39348#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
39349#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
39350#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK) /* end of group PXP_Register_Masks */
39357
39358
39359/* PXP - Peripheral instance base addresses */
39361#define PXP_BASE (0x402B4000u)
39363#define PXP ((PXP_Type *)PXP_BASE)
39365#define PXP_BASE_ADDRS { PXP_BASE }
39367#define PXP_BASE_PTRS { PXP }
39369#define PXP_IRQ0_IRQS { PXP_IRQn }
39370 /* end of group PXP_Peripheral_Access_Layer */
39374
39375
39376/* ----------------------------------------------------------------------------
39377 -- ROMC Peripheral Access Layer
39378 ---------------------------------------------------------------------------- */
39379
39386typedef struct {
39387 uint8_t RESERVED_0[212];
39388 __IO uint32_t ROMPATCHD[8];
39389 __IO uint32_t ROMPATCHCNTL;
39390 uint32_t ROMPATCHENH;
39391 __IO uint32_t ROMPATCHENL;
39392 __IO uint32_t ROMPATCHA[16];
39393 uint8_t RESERVED_1[200];
39394 __IO uint32_t ROMPATCHSR;
39395} ROMC_Type;
39396
39397/* ----------------------------------------------------------------------------
39398 -- ROMC Register Masks
39399 ---------------------------------------------------------------------------- */
39400
39409#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)
39410#define ROMC_ROMPATCHD_DATAX_SHIFT (0U)
39411#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)
39414/* The count of ROMC_ROMPATCHD */
39415#define ROMC_ROMPATCHD_COUNT (8U)
39416
39420#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)
39421#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)
39426#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)
39427
39428#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)
39429#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U)
39434#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)
39440#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)
39441#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U)
39446#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)
39452#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U)
39453#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U)
39458#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)
39459
39460#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)
39461#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U)
39462#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)
39465/* The count of ROMC_ROMPATCHA */
39466#define ROMC_ROMPATCHA_COUNT (16U)
39467
39471#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)
39472#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U)
39478#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)
39479
39480#define ROMC_ROMPATCHSR_SW_MASK (0x20000U)
39481#define ROMC_ROMPATCHSR_SW_SHIFT (17U)
39486#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) /* end of group ROMC_Register_Masks */
39493
39494
39495/* ROMC - Peripheral instance base addresses */
39497#define ROMC_BASE (0x40180000u)
39499#define ROMC ((ROMC_Type *)ROMC_BASE)
39501#define ROMC_BASE_ADDRS { ROMC_BASE }
39503#define ROMC_BASE_PTRS { ROMC }
39504 /* end of group ROMC_Peripheral_Access_Layer */
39508
39509
39510/* ----------------------------------------------------------------------------
39511 -- RTWDOG Peripheral Access Layer
39512 ---------------------------------------------------------------------------- */
39513
39520typedef struct {
39521 __IO uint32_t CS;
39522 __IO uint32_t CNT;
39523 __IO uint32_t TOVAL;
39524 __IO uint32_t WIN;
39525} RTWDOG_Type;
39526
39527/* ----------------------------------------------------------------------------
39528 -- RTWDOG Register Masks
39529 ---------------------------------------------------------------------------- */
39530
39539#define RTWDOG_CS_STOP_MASK (0x1U)
39540#define RTWDOG_CS_STOP_SHIFT (0U)
39545#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
39546
39547#define RTWDOG_CS_WAIT_MASK (0x2U)
39548#define RTWDOG_CS_WAIT_SHIFT (1U)
39553#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
39554
39555#define RTWDOG_CS_DBG_MASK (0x4U)
39556#define RTWDOG_CS_DBG_SHIFT (2U)
39561#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
39562
39563#define RTWDOG_CS_TST_MASK (0x18U)
39564#define RTWDOG_CS_TST_SHIFT (3U)
39572#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
39573
39574#define RTWDOG_CS_UPDATE_MASK (0x20U)
39575#define RTWDOG_CS_UPDATE_SHIFT (5U)
39580#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
39581
39582#define RTWDOG_CS_INT_MASK (0x40U)
39583#define RTWDOG_CS_INT_SHIFT (6U)
39588#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
39589
39590#define RTWDOG_CS_EN_MASK (0x80U)
39591#define RTWDOG_CS_EN_SHIFT (7U)
39596#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
39597
39598#define RTWDOG_CS_CLK_MASK (0x300U)
39599#define RTWDOG_CS_CLK_SHIFT (8U)
39602#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
39603
39604#define RTWDOG_CS_RCS_MASK (0x400U)
39605#define RTWDOG_CS_RCS_SHIFT (10U)
39610#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
39611
39612#define RTWDOG_CS_ULK_MASK (0x800U)
39613#define RTWDOG_CS_ULK_SHIFT (11U)
39618#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
39619
39620#define RTWDOG_CS_PRES_MASK (0x1000U)
39621#define RTWDOG_CS_PRES_SHIFT (12U)
39626#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
39627
39628#define RTWDOG_CS_CMD32EN_MASK (0x2000U)
39629#define RTWDOG_CS_CMD32EN_SHIFT (13U)
39634#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
39635
39636#define RTWDOG_CS_FLG_MASK (0x4000U)
39637#define RTWDOG_CS_FLG_SHIFT (14U)
39642#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
39643
39644#define RTWDOG_CS_WIN_MASK (0x8000U)
39645#define RTWDOG_CS_WIN_SHIFT (15U)
39650#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
39656#define RTWDOG_CNT_CNTLOW_MASK (0xFFU)
39657#define RTWDOG_CNT_CNTLOW_SHIFT (0U)
39660#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
39661
39662#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)
39663#define RTWDOG_CNT_CNTHIGH_SHIFT (8U)
39666#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
39672#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)
39673#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)
39676#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
39677
39678#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
39679#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)
39682#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
39688#define RTWDOG_WIN_WINLOW_MASK (0xFFU)
39689#define RTWDOG_WIN_WINLOW_SHIFT (0U)
39692#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
39693
39694#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U)
39695#define RTWDOG_WIN_WINHIGH_SHIFT (8U)
39698#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) /* end of group RTWDOG_Register_Masks */
39705
39706
39707/* RTWDOG - Peripheral instance base addresses */
39709#define RTWDOG_BASE (0x400BC000u)
39711#define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE)
39713#define RTWDOG_BASE_ADDRS { RTWDOG_BASE }
39715#define RTWDOG_BASE_PTRS { RTWDOG }
39717#define RTWDOG_IRQS { RTWDOG_IRQn }
39718/* Extra definition */
39719#define RTWDOG_UPDATE_KEY (0xD928C520U)
39720#define RTWDOG_REFRESH_KEY (0xB480A602U)
39721
39722 /* end of group RTWDOG_Peripheral_Access_Layer */
39726
39727
39728/* ----------------------------------------------------------------------------
39729 -- SEMC Peripheral Access Layer
39730 ---------------------------------------------------------------------------- */
39731
39738typedef struct {
39739 __IO uint32_t MCR;
39740 __IO uint32_t IOCR;
39741 __IO uint32_t BMCR0;
39742 __IO uint32_t BMCR1;
39743 __IO uint32_t BR[9];
39744 uint8_t RESERVED_0[4];
39745 __IO uint32_t INTEN;
39746 __IO uint32_t INTR;
39747 __IO uint32_t SDRAMCR0;
39748 __IO uint32_t SDRAMCR1;
39749 __IO uint32_t SDRAMCR2;
39750 __IO uint32_t SDRAMCR3;
39751 __IO uint32_t NANDCR0;
39752 __IO uint32_t NANDCR1;
39753 __IO uint32_t NANDCR2;
39754 __IO uint32_t NANDCR3;
39755 __IO uint32_t NORCR0;
39756 __IO uint32_t NORCR1;
39757 __IO uint32_t NORCR2;
39758 uint32_t NORCR3;
39759 __IO uint32_t SRAMCR0;
39760 __IO uint32_t SRAMCR1;
39761 __IO uint32_t SRAMCR2;
39762 uint32_t SRAMCR3;
39763 __IO uint32_t DBICR0;
39764 __IO uint32_t DBICR1;
39765 uint8_t RESERVED_1[8];
39766 __IO uint32_t IPCR0;
39767 __IO uint32_t IPCR1;
39768 __IO uint32_t IPCR2;
39769 __IO uint32_t IPCMD;
39770 __IO uint32_t IPTXDAT;
39771 uint8_t RESERVED_2[12];
39772 __I uint32_t IPRXDAT;
39773 uint8_t RESERVED_3[12];
39774 __I uint32_t STS0;
39775 uint32_t STS1;
39776 __I uint32_t STS2;
39777 uint32_t STS3;
39778 uint32_t STS4;
39779 uint32_t STS5;
39780 uint32_t STS6;
39781 uint32_t STS7;
39782 uint32_t STS8;
39783 uint32_t STS9;
39784 uint32_t STS10;
39785 uint32_t STS11;
39786 __I uint32_t STS12;
39787 uint32_t STS13;
39788 uint32_t STS14;
39789 uint32_t STS15;
39790} SEMC_Type;
39791
39792/* ----------------------------------------------------------------------------
39793 -- SEMC Register Masks
39794 ---------------------------------------------------------------------------- */
39795
39804#define SEMC_MCR_SWRST_MASK (0x1U)
39805#define SEMC_MCR_SWRST_SHIFT (0U)
39808#define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
39809
39810#define SEMC_MCR_MDIS_MASK (0x2U)
39811#define SEMC_MCR_MDIS_SHIFT (1U)
39816#define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
39817
39818#define SEMC_MCR_DQSMD_MASK (0x4U)
39819#define SEMC_MCR_DQSMD_SHIFT (2U)
39824#define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
39825
39826#define SEMC_MCR_WPOL0_MASK (0x40U)
39827#define SEMC_MCR_WPOL0_SHIFT (6U)
39832#define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
39833
39834#define SEMC_MCR_WPOL1_MASK (0x80U)
39835#define SEMC_MCR_WPOL1_SHIFT (7U)
39840#define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
39841
39842#define SEMC_MCR_CTO_MASK (0xFF0000U)
39843#define SEMC_MCR_CTO_SHIFT (16U)
39846#define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
39847
39848#define SEMC_MCR_BTO_MASK (0x1F000000U)
39849#define SEMC_MCR_BTO_SHIFT (24U)
39855#define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
39861#define SEMC_IOCR_MUX_A8_MASK (0x7U)
39862#define SEMC_IOCR_MUX_A8_SHIFT (0U)
39873#define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
39874
39875#define SEMC_IOCR_MUX_CSX0_MASK (0x38U)
39876#define SEMC_IOCR_MUX_CSX0_SHIFT (3U)
39887#define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
39888
39889#define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)
39890#define SEMC_IOCR_MUX_CSX1_SHIFT (6U)
39901#define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
39902
39903#define SEMC_IOCR_MUX_CSX2_MASK (0xE00U)
39904#define SEMC_IOCR_MUX_CSX2_SHIFT (9U)
39915#define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
39916
39917#define SEMC_IOCR_MUX_CSX3_MASK (0x7000U)
39918#define SEMC_IOCR_MUX_CSX3_SHIFT (12U)
39929#define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
39930
39931#define SEMC_IOCR_MUX_RDY_MASK (0x38000U)
39932#define SEMC_IOCR_MUX_RDY_SHIFT (15U)
39943#define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
39949#define SEMC_BMCR0_WQOS_MASK (0xFU)
39950#define SEMC_BMCR0_WQOS_SHIFT (0U)
39955#define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
39956
39957#define SEMC_BMCR0_WAGE_MASK (0xF0U)
39958#define SEMC_BMCR0_WAGE_SHIFT (4U)
39962#define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
39963
39964#define SEMC_BMCR0_WSH_MASK (0xFF00U)
39965#define SEMC_BMCR0_WSH_SHIFT (8U)
39969#define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
39970
39971#define SEMC_BMCR0_WRWS_MASK (0xFF0000U)
39972#define SEMC_BMCR0_WRWS_SHIFT (16U)
39976#define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
39982#define SEMC_BMCR1_WQOS_MASK (0xFU)
39983#define SEMC_BMCR1_WQOS_SHIFT (0U)
39988#define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
39989
39990#define SEMC_BMCR1_WAGE_MASK (0xF0U)
39991#define SEMC_BMCR1_WAGE_SHIFT (4U)
39995#define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
39996
39997#define SEMC_BMCR1_WPH_MASK (0xFF00U)
39998#define SEMC_BMCR1_WPH_SHIFT (8U)
40001#define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
40002
40003#define SEMC_BMCR1_WRWS_MASK (0xFF0000U)
40004#define SEMC_BMCR1_WRWS_SHIFT (16U)
40008#define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
40009
40010#define SEMC_BMCR1_WBR_MASK (0xFF000000U)
40011#define SEMC_BMCR1_WBR_SHIFT (24U)
40014#define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
40020#define SEMC_BR_VLD_MASK (0x1U)
40021#define SEMC_BR_VLD_SHIFT (0U)
40024#define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
40025
40026#define SEMC_BR_MS_MASK (0x3EU)
40027#define SEMC_BR_MS_SHIFT (1U)
40051#define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
40052
40053#define SEMC_BR_BA_MASK (0xFFFFF000U)
40054#define SEMC_BR_BA_SHIFT (12U)
40057#define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
40060/* The count of SEMC_BR */
40061#define SEMC_BR_COUNT (9U)
40062
40066#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)
40067#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)
40072#define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
40073
40074#define SEMC_INTEN_IPCMDERREN_MASK (0x2U)
40075#define SEMC_INTEN_IPCMDERREN_SHIFT (1U)
40080#define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
40081
40082#define SEMC_INTEN_AXICMDERREN_MASK (0x4U)
40083#define SEMC_INTEN_AXICMDERREN_SHIFT (2U)
40088#define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
40089
40090#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U)
40091#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U)
40096#define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
40097
40098#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)
40099#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)
40104#define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
40105
40106#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U)
40107#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U)
40112#define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
40118#define SEMC_INTR_IPCMDDONE_MASK (0x1U)
40119#define SEMC_INTR_IPCMDDONE_SHIFT (0U)
40122#define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
40123
40124#define SEMC_INTR_IPCMDERR_MASK (0x2U)
40125#define SEMC_INTR_IPCMDERR_SHIFT (1U)
40128#define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
40129
40130#define SEMC_INTR_AXICMDERR_MASK (0x4U)
40131#define SEMC_INTR_AXICMDERR_SHIFT (2U)
40134#define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
40135
40136#define SEMC_INTR_AXIBUSERR_MASK (0x8U)
40137#define SEMC_INTR_AXIBUSERR_SHIFT (3U)
40140#define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
40141
40142#define SEMC_INTR_NDPAGEEND_MASK (0x10U)
40143#define SEMC_INTR_NDPAGEEND_SHIFT (4U)
40146#define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
40147
40148#define SEMC_INTR_NDNOPEND_MASK (0x20U)
40149#define SEMC_INTR_NDNOPEND_SHIFT (5U)
40152#define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
40158#define SEMC_SDRAMCR0_PS_MASK (0x1U)
40159#define SEMC_SDRAMCR0_PS_SHIFT (0U)
40164#define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
40165
40166#define SEMC_SDRAMCR0_BL_MASK (0x70U)
40167#define SEMC_SDRAMCR0_BL_SHIFT (4U)
40178#define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
40179
40180#define SEMC_SDRAMCR0_COL_MASK (0x300U)
40181#define SEMC_SDRAMCR0_COL_SHIFT (8U)
40188#define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
40189
40190#define SEMC_SDRAMCR0_CL_MASK (0xC00U)
40191#define SEMC_SDRAMCR0_CL_SHIFT (10U)
40198#define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
40204#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)
40205#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)
40208#define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
40209
40210#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)
40211#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)
40214#define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
40215
40216#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)
40217#define SEMC_SDRAMCR1_RFRC_SHIFT (8U)
40220#define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
40221
40222#define SEMC_SDRAMCR1_WRC_MASK (0xE000U)
40223#define SEMC_SDRAMCR1_WRC_SHIFT (13U)
40226#define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
40227
40228#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)
40229#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)
40232#define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
40233
40234#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)
40235#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)
40238#define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
40244#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU)
40245#define SEMC_SDRAMCR2_SRRC_SHIFT (0U)
40248#define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
40249
40250#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)
40251#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U)
40254#define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
40255
40256#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)
40257#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)
40260#define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
40261
40262#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)
40263#define SEMC_SDRAMCR2_ITO_SHIFT (24U)
40268#define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
40274#define SEMC_SDRAMCR3_REN_MASK (0x1U)
40275#define SEMC_SDRAMCR3_REN_SHIFT (0U)
40278#define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
40279
40280#define SEMC_SDRAMCR3_REBL_MASK (0xEU)
40281#define SEMC_SDRAMCR3_REBL_SHIFT (1U)
40292#define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
40293
40294#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)
40295#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)
40300#define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
40301
40302#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U)
40303#define SEMC_SDRAMCR3_RT_SHIFT (16U)
40308#define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
40309
40310#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U)
40311#define SEMC_SDRAMCR3_UT_SHIFT (24U)
40316#define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
40322#define SEMC_NANDCR0_PS_MASK (0x1U)
40323#define SEMC_NANDCR0_PS_SHIFT (0U)
40328#define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
40329
40330#define SEMC_NANDCR0_BL_MASK (0x70U)
40331#define SEMC_NANDCR0_BL_SHIFT (4U)
40342#define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
40343
40344#define SEMC_NANDCR0_EDO_MASK (0x80U)
40345#define SEMC_NANDCR0_EDO_SHIFT (7U)
40350#define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
40351
40352#define SEMC_NANDCR0_COL_MASK (0x700U)
40353#define SEMC_NANDCR0_COL_SHIFT (8U)
40364#define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
40370#define SEMC_NANDCR1_CES_MASK (0xFU)
40371#define SEMC_NANDCR1_CES_SHIFT (0U)
40374#define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
40375
40376#define SEMC_NANDCR1_CEH_MASK (0xF0U)
40377#define SEMC_NANDCR1_CEH_SHIFT (4U)
40380#define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
40381
40382#define SEMC_NANDCR1_WEL_MASK (0xF00U)
40383#define SEMC_NANDCR1_WEL_SHIFT (8U)
40386#define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
40387
40388#define SEMC_NANDCR1_WEH_MASK (0xF000U)
40389#define SEMC_NANDCR1_WEH_SHIFT (12U)
40392#define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
40393
40394#define SEMC_NANDCR1_REL_MASK (0xF0000U)
40395#define SEMC_NANDCR1_REL_SHIFT (16U)
40398#define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
40399
40400#define SEMC_NANDCR1_REH_MASK (0xF00000U)
40401#define SEMC_NANDCR1_REH_SHIFT (20U)
40404#define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
40405
40406#define SEMC_NANDCR1_TA_MASK (0xF000000U)
40407#define SEMC_NANDCR1_TA_SHIFT (24U)
40410#define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
40411
40412#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U)
40413#define SEMC_NANDCR1_CEITV_SHIFT (28U)
40416#define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
40422#define SEMC_NANDCR2_TWHR_MASK (0x3FU)
40423#define SEMC_NANDCR2_TWHR_SHIFT (0U)
40426#define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
40427
40428#define SEMC_NANDCR2_TRHW_MASK (0xFC0U)
40429#define SEMC_NANDCR2_TRHW_SHIFT (6U)
40432#define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
40433
40434#define SEMC_NANDCR2_TADL_MASK (0x3F000U)
40435#define SEMC_NANDCR2_TADL_SHIFT (12U)
40438#define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
40439
40440#define SEMC_NANDCR2_TRR_MASK (0xFC0000U)
40441#define SEMC_NANDCR2_TRR_SHIFT (18U)
40444#define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
40445
40446#define SEMC_NANDCR2_TWB_MASK (0x3F000000U)
40447#define SEMC_NANDCR2_TWB_SHIFT (24U)
40450#define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
40456#define SEMC_NANDCR3_NDOPT1_MASK (0x1U)
40457#define SEMC_NANDCR3_NDOPT1_SHIFT (0U)
40460#define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
40461
40462#define SEMC_NANDCR3_NDOPT2_MASK (0x2U)
40463#define SEMC_NANDCR3_NDOPT2_SHIFT (1U)
40466#define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
40467
40468#define SEMC_NANDCR3_NDOPT3_MASK (0x4U)
40469#define SEMC_NANDCR3_NDOPT3_SHIFT (2U)
40472#define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
40478#define SEMC_NORCR0_PS_MASK (0x1U)
40479#define SEMC_NORCR0_PS_SHIFT (0U)
40484#define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
40485
40486#define SEMC_NORCR0_BL_MASK (0x70U)
40487#define SEMC_NORCR0_BL_SHIFT (4U)
40498#define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
40499
40500#define SEMC_NORCR0_AM_MASK (0x300U)
40501#define SEMC_NORCR0_AM_SHIFT (8U)
40508#define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
40509
40510#define SEMC_NORCR0_ADVP_MASK (0x400U)
40511#define SEMC_NORCR0_ADVP_SHIFT (10U)
40516#define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
40517
40518#define SEMC_NORCR0_COL_MASK (0xF000U)
40519#define SEMC_NORCR0_COL_SHIFT (12U)
40538#define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
40544#define SEMC_NORCR1_CES_MASK (0xFU)
40545#define SEMC_NORCR1_CES_SHIFT (0U)
40548#define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
40549
40550#define SEMC_NORCR1_CEH_MASK (0xF0U)
40551#define SEMC_NORCR1_CEH_SHIFT (4U)
40554#define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
40555
40556#define SEMC_NORCR1_AS_MASK (0xF00U)
40557#define SEMC_NORCR1_AS_SHIFT (8U)
40560#define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
40561
40562#define SEMC_NORCR1_AH_MASK (0xF000U)
40563#define SEMC_NORCR1_AH_SHIFT (12U)
40566#define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
40567
40568#define SEMC_NORCR1_WEL_MASK (0xF0000U)
40569#define SEMC_NORCR1_WEL_SHIFT (16U)
40572#define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
40573
40574#define SEMC_NORCR1_WEH_MASK (0xF00000U)
40575#define SEMC_NORCR1_WEH_SHIFT (20U)
40578#define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
40579
40580#define SEMC_NORCR1_REL_MASK (0xF000000U)
40581#define SEMC_NORCR1_REL_SHIFT (24U)
40584#define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
40585
40586#define SEMC_NORCR1_REH_MASK (0xF0000000U)
40587#define SEMC_NORCR1_REH_SHIFT (28U)
40590#define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
40596#define SEMC_NORCR2_TA_MASK (0xF00U)
40597#define SEMC_NORCR2_TA_SHIFT (8U)
40600#define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
40601
40602#define SEMC_NORCR2_AWDH_MASK (0xF000U)
40603#define SEMC_NORCR2_AWDH_SHIFT (12U)
40606#define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
40607
40608#define SEMC_NORCR2_CEITV_MASK (0xF000000U)
40609#define SEMC_NORCR2_CEITV_SHIFT (24U)
40612#define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
40618#define SEMC_SRAMCR0_PS_MASK (0x1U)
40619#define SEMC_SRAMCR0_PS_SHIFT (0U)
40624#define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
40625
40626#define SEMC_SRAMCR0_BL_MASK (0x70U)
40627#define SEMC_SRAMCR0_BL_SHIFT (4U)
40638#define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
40639
40640#define SEMC_SRAMCR0_AM_MASK (0x300U)
40641#define SEMC_SRAMCR0_AM_SHIFT (8U)
40648#define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
40649
40650#define SEMC_SRAMCR0_ADVP_MASK (0x400U)
40651#define SEMC_SRAMCR0_ADVP_SHIFT (10U)
40656#define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
40657
40658#define SEMC_SRAMCR0_COL_MASK (0xF000U)
40659#define SEMC_SRAMCR0_COL_SHIFT (12U)
40678#define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
40684#define SEMC_SRAMCR1_CES_MASK (0xFU)
40685#define SEMC_SRAMCR1_CES_SHIFT (0U)
40688#define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
40689
40690#define SEMC_SRAMCR1_CEH_MASK (0xF0U)
40691#define SEMC_SRAMCR1_CEH_SHIFT (4U)
40694#define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
40695
40696#define SEMC_SRAMCR1_AS_MASK (0xF00U)
40697#define SEMC_SRAMCR1_AS_SHIFT (8U)
40700#define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
40701
40702#define SEMC_SRAMCR1_AH_MASK (0xF000U)
40703#define SEMC_SRAMCR1_AH_SHIFT (12U)
40706#define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
40707
40708#define SEMC_SRAMCR1_WEL_MASK (0xF0000U)
40709#define SEMC_SRAMCR1_WEL_SHIFT (16U)
40712#define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
40713
40714#define SEMC_SRAMCR1_WEH_MASK (0xF00000U)
40715#define SEMC_SRAMCR1_WEH_SHIFT (20U)
40718#define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
40719
40720#define SEMC_SRAMCR1_REL_MASK (0xF000000U)
40721#define SEMC_SRAMCR1_REL_SHIFT (24U)
40724#define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
40725
40726#define SEMC_SRAMCR1_REH_MASK (0xF0000000U)
40727#define SEMC_SRAMCR1_REH_SHIFT (28U)
40730#define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
40736#define SEMC_SRAMCR2_TA_MASK (0xF00U)
40737#define SEMC_SRAMCR2_TA_SHIFT (8U)
40740#define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
40741
40742#define SEMC_SRAMCR2_AWDH_MASK (0xF000U)
40743#define SEMC_SRAMCR2_AWDH_SHIFT (12U)
40746#define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
40747
40748#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U)
40749#define SEMC_SRAMCR2_CEITV_SHIFT (24U)
40752#define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
40758#define SEMC_DBICR0_PS_MASK (0x1U)
40759#define SEMC_DBICR0_PS_SHIFT (0U)
40764#define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
40765
40766#define SEMC_DBICR0_BL_MASK (0x70U)
40767#define SEMC_DBICR0_BL_SHIFT (4U)
40778#define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
40779
40780#define SEMC_DBICR0_COL_MASK (0xF000U)
40781#define SEMC_DBICR0_COL_SHIFT (12U)
40800#define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
40806#define SEMC_DBICR1_CES_MASK (0xFU)
40807#define SEMC_DBICR1_CES_SHIFT (0U)
40810#define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
40811
40812#define SEMC_DBICR1_CEH_MASK (0xF0U)
40813#define SEMC_DBICR1_CEH_SHIFT (4U)
40816#define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
40817
40818#define SEMC_DBICR1_WEL_MASK (0xF00U)
40819#define SEMC_DBICR1_WEL_SHIFT (8U)
40822#define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
40823
40824#define SEMC_DBICR1_WEH_MASK (0xF000U)
40825#define SEMC_DBICR1_WEH_SHIFT (12U)
40828#define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
40829
40830#define SEMC_DBICR1_REL_MASK (0xF0000U)
40831#define SEMC_DBICR1_REL_SHIFT (16U)
40834#define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
40835
40836#define SEMC_DBICR1_REH_MASK (0xF00000U)
40837#define SEMC_DBICR1_REH_SHIFT (20U)
40840#define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
40841
40842#define SEMC_DBICR1_CEITV_MASK (0xF000000U)
40843#define SEMC_DBICR1_CEITV_SHIFT (24U)
40846#define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)
40847
40848#define SEMC_DBICR1_REL2_MASK (0x30000000U)
40849#define SEMC_DBICR1_REL2_SHIFT (28U)
40852#define SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK)
40853
40854#define SEMC_DBICR1_REH2_MASK (0xC0000000U)
40855#define SEMC_DBICR1_REH2_SHIFT (30U)
40858#define SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK)
40864#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)
40865#define SEMC_IPCR0_SA_SHIFT (0U)
40868#define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
40874#define SEMC_IPCR1_DATSZ_MASK (0x7U)
40875#define SEMC_IPCR1_DATSZ_SHIFT (0U)
40886#define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
40892#define SEMC_IPCR2_BM0_MASK (0x1U)
40893#define SEMC_IPCR2_BM0_SHIFT (0U)
40898#define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
40899
40900#define SEMC_IPCR2_BM1_MASK (0x2U)
40901#define SEMC_IPCR2_BM1_SHIFT (1U)
40906#define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
40907
40908#define SEMC_IPCR2_BM2_MASK (0x4U)
40909#define SEMC_IPCR2_BM2_SHIFT (2U)
40914#define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
40915
40916#define SEMC_IPCR2_BM3_MASK (0x8U)
40917#define SEMC_IPCR2_BM3_SHIFT (3U)
40922#define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
40928#define SEMC_IPCMD_CMD_MASK (0xFFFFU)
40929#define SEMC_IPCMD_CMD_SHIFT (0U)
40930#define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
40931
40932#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U)
40933#define SEMC_IPCMD_KEY_SHIFT (16U)
40936#define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
40942#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)
40943#define SEMC_IPTXDAT_DAT_SHIFT (0U)
40946#define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
40952#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)
40953#define SEMC_IPRXDAT_DAT_SHIFT (0U)
40956#define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
40962#define SEMC_STS0_IDLE_MASK (0x1U)
40963#define SEMC_STS0_IDLE_SHIFT (0U)
40966#define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
40967
40968#define SEMC_STS0_NARDY_MASK (0x2U)
40969#define SEMC_STS0_NARDY_SHIFT (1U)
40974#define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
40980#define SEMC_STS2_NDWRPEND_MASK (0x8U)
40981#define SEMC_STS2_NDWRPEND_SHIFT (3U)
40986#define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
40992#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)
40993#define SEMC_STS12_NDADDR_SHIFT (0U)
40996#define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) /* end of group SEMC_Register_Masks */
41003
41004
41005/* SEMC - Peripheral instance base addresses */
41007#define SEMC_BASE (0x402F0000u)
41009#define SEMC ((SEMC_Type *)SEMC_BASE)
41011#define SEMC_BASE_ADDRS { SEMC_BASE }
41013#define SEMC_BASE_PTRS { SEMC }
41015#define SEMC_IRQS { SEMC_IRQn }
41016 /* end of group SEMC_Peripheral_Access_Layer */
41020
41021
41022/* ----------------------------------------------------------------------------
41023 -- SNVS Peripheral Access Layer
41024 ---------------------------------------------------------------------------- */
41025
41032typedef struct {
41033 __IO uint32_t HPLR;
41034 __IO uint32_t HPCOMR;
41035 __IO uint32_t HPCR;
41036 __IO uint32_t HPSICR;
41037 __IO uint32_t HPSVCR;
41038 __IO uint32_t HPSR;
41039 __IO uint32_t HPSVSR;
41040 __IO uint32_t HPHACIVR;
41041 __I uint32_t HPHACR;
41042 __IO uint32_t HPRTCMR;
41043 __IO uint32_t HPRTCLR;
41044 __IO uint32_t HPTAMR;
41045 __IO uint32_t HPTALR;
41046 __IO uint32_t LPLR;
41047 __IO uint32_t LPCR;
41048 __IO uint32_t LPMKCR;
41049 __IO uint32_t LPSVCR;
41050 uint8_t RESERVED_0[4];
41051 __IO uint32_t LPSECR;
41052 __IO uint32_t LPSR;
41053 __IO uint32_t LPSRTCMR;
41054 __IO uint32_t LPSRTCLR;
41055 __IO uint32_t LPTAR;
41056 __IO uint32_t LPSMCMR;
41057 __IO uint32_t LPSMCLR;
41058 __IO uint32_t LPLVDR;
41059 __IO uint32_t LPGPR0_LEGACY_ALIAS;
41060 __IO uint32_t LPZMKR[8];
41061 uint8_t RESERVED_1[4];
41062 __IO uint32_t LPGPR_ALIAS[4];
41063 uint8_t RESERVED_2[96];
41064 __IO uint32_t LPGPR[8];
41065 uint8_t RESERVED_3[2776];
41066 __I uint32_t HPVIDR1;
41067 __I uint32_t HPVIDR2;
41068} SNVS_Type;
41069
41070/* ----------------------------------------------------------------------------
41071 -- SNVS Register Masks
41072 ---------------------------------------------------------------------------- */
41073
41082#define SNVS_HPLR_ZMK_WSL_MASK (0x1U)
41083#define SNVS_HPLR_ZMK_WSL_SHIFT (0U)
41088#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
41089
41090#define SNVS_HPLR_ZMK_RSL_MASK (0x2U)
41091#define SNVS_HPLR_ZMK_RSL_SHIFT (1U)
41096#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
41097
41098#define SNVS_HPLR_SRTC_SL_MASK (0x4U)
41099#define SNVS_HPLR_SRTC_SL_SHIFT (2U)
41104#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
41105
41106#define SNVS_HPLR_LPCALB_SL_MASK (0x8U)
41107#define SNVS_HPLR_LPCALB_SL_SHIFT (3U)
41112#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
41113
41114#define SNVS_HPLR_MC_SL_MASK (0x10U)
41115#define SNVS_HPLR_MC_SL_SHIFT (4U)
41120#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
41121
41122#define SNVS_HPLR_GPR_SL_MASK (0x20U)
41123#define SNVS_HPLR_GPR_SL_SHIFT (5U)
41128#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
41129
41130#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U)
41131#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U)
41136#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
41137
41138#define SNVS_HPLR_LPSECR_SL_MASK (0x100U)
41139#define SNVS_HPLR_LPSECR_SL_SHIFT (8U)
41144#define SNVS_HPLR_LPSECR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)
41145
41146#define SNVS_HPLR_MKS_SL_MASK (0x200U)
41147#define SNVS_HPLR_MKS_SL_SHIFT (9U)
41152#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
41153
41154#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U)
41155#define SNVS_HPLR_HPSVCR_L_SHIFT (16U)
41160#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
41161
41162#define SNVS_HPLR_HPSICR_L_MASK (0x20000U)
41163#define SNVS_HPLR_HPSICR_L_SHIFT (17U)
41168#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
41169
41170#define SNVS_HPLR_HAC_L_MASK (0x40000U)
41171#define SNVS_HPLR_HAC_L_SHIFT (18U)
41176#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
41182#define SNVS_HPCOMR_SSM_ST_MASK (0x1U)
41183#define SNVS_HPCOMR_SSM_ST_SHIFT (0U)
41184#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
41185
41186#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)
41187#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)
41192#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
41193
41194#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)
41195#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)
41200#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
41201
41202#define SNVS_HPCOMR_LP_SWR_MASK (0x10U)
41203#define SNVS_HPCOMR_LP_SWR_SHIFT (4U)
41208#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
41209
41210#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
41211#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
41216#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
41217
41218#define SNVS_HPCOMR_SW_SV_MASK (0x100U)
41219#define SNVS_HPCOMR_SW_SV_SHIFT (8U)
41220#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
41221
41222#define SNVS_HPCOMR_SW_FSV_MASK (0x200U)
41223#define SNVS_HPCOMR_SW_FSV_SHIFT (9U)
41224#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
41225
41226#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U)
41227#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U)
41228#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
41229
41230#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)
41231#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)
41236#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
41237
41238#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U)
41239#define SNVS_HPCOMR_MKS_EN_SHIFT (13U)
41244#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
41245
41246#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U)
41247#define SNVS_HPCOMR_HAC_EN_SHIFT (16U)
41252#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
41253
41254#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)
41255#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)
41260#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
41261
41262#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)
41263#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)
41268#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
41269
41270#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)
41271#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U)
41272#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
41273
41274#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
41275#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
41276#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
41282#define SNVS_HPCR_RTC_EN_MASK (0x1U)
41283#define SNVS_HPCR_RTC_EN_SHIFT (0U)
41288#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
41289
41290#define SNVS_HPCR_HPTA_EN_MASK (0x2U)
41291#define SNVS_HPCR_HPTA_EN_SHIFT (1U)
41296#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
41297
41298#define SNVS_HPCR_DIS_PI_MASK (0x4U)
41299#define SNVS_HPCR_DIS_PI_SHIFT (2U)
41304#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
41305
41306#define SNVS_HPCR_PI_EN_MASK (0x8U)
41307#define SNVS_HPCR_PI_EN_SHIFT (3U)
41312#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
41313
41314#define SNVS_HPCR_PI_FREQ_MASK (0xF0U)
41315#define SNVS_HPCR_PI_FREQ_SHIFT (4U)
41334#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
41335
41336#define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
41337#define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
41342#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
41343
41344#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
41345#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
41356#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
41357
41358#define SNVS_HPCR_HP_TS_MASK (0x10000U)
41359#define SNVS_HPCR_HP_TS_SHIFT (16U)
41364#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
41365
41366#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
41367#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
41368#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
41369
41370#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
41371#define SNVS_HPCR_BTN_MASK_SHIFT (27U)
41372#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
41378#define SNVS_HPSICR_SV0_EN_MASK (0x1U)
41379#define SNVS_HPSICR_SV0_EN_SHIFT (0U)
41384#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
41385
41386#define SNVS_HPSICR_SV1_EN_MASK (0x2U)
41387#define SNVS_HPSICR_SV1_EN_SHIFT (1U)
41392#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
41393
41394#define SNVS_HPSICR_SV2_EN_MASK (0x4U)
41395#define SNVS_HPSICR_SV2_EN_SHIFT (2U)
41400#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
41401
41402#define SNVS_HPSICR_SV3_EN_MASK (0x8U)
41403#define SNVS_HPSICR_SV3_EN_SHIFT (3U)
41408#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
41409
41410#define SNVS_HPSICR_SV4_EN_MASK (0x10U)
41411#define SNVS_HPSICR_SV4_EN_SHIFT (4U)
41416#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
41417
41418#define SNVS_HPSICR_SV5_EN_MASK (0x20U)
41419#define SNVS_HPSICR_SV5_EN_SHIFT (5U)
41424#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
41425
41426#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)
41427#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U)
41432#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
41438#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U)
41439#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U)
41444#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
41445
41446#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U)
41447#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U)
41452#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
41453
41454#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U)
41455#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U)
41460#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
41461
41462#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U)
41463#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U)
41468#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
41469
41470#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U)
41471#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U)
41476#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
41477
41478#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U)
41479#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U)
41485#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
41486
41487#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)
41488#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)
41494#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
41500#define SNVS_HPSR_HPTA_MASK (0x1U)
41501#define SNVS_HPSR_HPTA_SHIFT (0U)
41506#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
41507
41508#define SNVS_HPSR_PI_MASK (0x2U)
41509#define SNVS_HPSR_PI_SHIFT (1U)
41514#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
41515
41516#define SNVS_HPSR_LPDIS_MASK (0x10U)
41517#define SNVS_HPSR_LPDIS_SHIFT (4U)
41518#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
41519
41520#define SNVS_HPSR_BTN_MASK (0x40U)
41521#define SNVS_HPSR_BTN_SHIFT (6U)
41522#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
41523
41524#define SNVS_HPSR_BI_MASK (0x80U)
41525#define SNVS_HPSR_BI_SHIFT (7U)
41526#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
41527
41528#define SNVS_HPSR_SSM_STATE_MASK (0xF00U)
41529#define SNVS_HPSR_SSM_STATE_SHIFT (8U)
41540#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
41541
41542#define SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U)
41543#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U)
41550#define SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)
41551
41552#define SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U)
41553#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U)
41554#define SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)
41555
41556#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)
41557#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)
41558#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
41559
41560#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)
41561#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)
41566#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
41567
41568#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)
41569#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U)
41574#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
41580#define SNVS_HPSVSR_SV0_MASK (0x1U)
41581#define SNVS_HPSVSR_SV0_SHIFT (0U)
41586#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
41587
41588#define SNVS_HPSVSR_SV1_MASK (0x2U)
41589#define SNVS_HPSVSR_SV1_SHIFT (1U)
41594#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
41595
41596#define SNVS_HPSVSR_SV2_MASK (0x4U)
41597#define SNVS_HPSVSR_SV2_SHIFT (2U)
41602#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
41603
41604#define SNVS_HPSVSR_SV3_MASK (0x8U)
41605#define SNVS_HPSVSR_SV3_SHIFT (3U)
41610#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
41611
41612#define SNVS_HPSVSR_SV4_MASK (0x10U)
41613#define SNVS_HPSVSR_SV4_SHIFT (4U)
41618#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
41619
41620#define SNVS_HPSVSR_SV5_MASK (0x20U)
41621#define SNVS_HPSVSR_SV5_SHIFT (5U)
41626#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
41627
41628#define SNVS_HPSVSR_SW_SV_MASK (0x2000U)
41629#define SNVS_HPSVSR_SW_SV_SHIFT (13U)
41630#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
41631
41632#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U)
41633#define SNVS_HPSVSR_SW_FSV_SHIFT (14U)
41634#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
41635
41636#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)
41637#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U)
41638#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
41639
41640#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)
41641#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)
41642#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
41643
41644#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)
41645#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)
41650#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
41651
41652#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)
41653#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)
41654#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
41660#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)
41661#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)
41662#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
41668#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)
41669#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)
41670#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
41676#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
41677#define SNVS_HPRTCMR_RTC_SHIFT (0U)
41678#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
41684#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
41685#define SNVS_HPRTCLR_RTC_SHIFT (0U)
41686#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
41692#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
41693#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
41694#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
41700#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
41701#define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
41702#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
41708#define SNVS_LPLR_ZMK_WHL_MASK (0x1U)
41709#define SNVS_LPLR_ZMK_WHL_SHIFT (0U)
41714#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
41715
41716#define SNVS_LPLR_ZMK_RHL_MASK (0x2U)
41717#define SNVS_LPLR_ZMK_RHL_SHIFT (1U)
41722#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
41723
41724#define SNVS_LPLR_SRTC_HL_MASK (0x4U)
41725#define SNVS_LPLR_SRTC_HL_SHIFT (2U)
41730#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
41731
41732#define SNVS_LPLR_LPCALB_HL_MASK (0x8U)
41733#define SNVS_LPLR_LPCALB_HL_SHIFT (3U)
41738#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
41739
41740#define SNVS_LPLR_MC_HL_MASK (0x10U)
41741#define SNVS_LPLR_MC_HL_SHIFT (4U)
41746#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
41747
41748#define SNVS_LPLR_GPR_HL_MASK (0x20U)
41749#define SNVS_LPLR_GPR_HL_SHIFT (5U)
41754#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
41755
41756#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U)
41757#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U)
41762#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
41763
41764#define SNVS_LPLR_LPSECR_HL_MASK (0x100U)
41765#define SNVS_LPLR_LPSECR_HL_SHIFT (8U)
41770#define SNVS_LPLR_LPSECR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)
41771
41772#define SNVS_LPLR_MKS_HL_MASK (0x200U)
41773#define SNVS_LPLR_MKS_HL_SHIFT (9U)
41778#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
41784#define SNVS_LPCR_SRTC_ENV_MASK (0x1U)
41785#define SNVS_LPCR_SRTC_ENV_SHIFT (0U)
41790#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
41791
41792#define SNVS_LPCR_LPTA_EN_MASK (0x2U)
41793#define SNVS_LPCR_LPTA_EN_SHIFT (1U)
41798#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
41799
41800#define SNVS_LPCR_MC_ENV_MASK (0x4U)
41801#define SNVS_LPCR_MC_ENV_SHIFT (2U)
41806#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
41807
41808#define SNVS_LPCR_LPWUI_EN_MASK (0x8U)
41809#define SNVS_LPCR_LPWUI_EN_SHIFT (3U)
41810#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
41811
41812#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)
41813#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)
41818#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
41819
41820#define SNVS_LPCR_DP_EN_MASK (0x20U)
41821#define SNVS_LPCR_DP_EN_SHIFT (5U)
41826#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
41827
41828#define SNVS_LPCR_TOP_MASK (0x40U)
41829#define SNVS_LPCR_TOP_SHIFT (6U)
41834#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
41835
41836#define SNVS_LPCR_LVD_EN_MASK (0x80U)
41837#define SNVS_LPCR_LVD_EN_SHIFT (7U)
41838#define SNVS_LPCR_LVD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK)
41839
41840#define SNVS_LPCR_LPCALB_EN_MASK (0x100U)
41841#define SNVS_LPCR_LPCALB_EN_SHIFT (8U)
41846#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
41847
41848#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)
41849#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U)
41860#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
41861
41862#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
41863#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
41864#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
41865
41866#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
41867#define SNVS_LPCR_DEBOUNCE_SHIFT (18U)
41868#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
41869
41870#define SNVS_LPCR_ON_TIME_MASK (0x300000U)
41871#define SNVS_LPCR_ON_TIME_SHIFT (20U)
41872#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
41873
41874#define SNVS_LPCR_PK_EN_MASK (0x400000U)
41875#define SNVS_LPCR_PK_EN_SHIFT (22U)
41876#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
41877
41878#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
41879#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
41880#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
41881
41882#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)
41883#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)
41884#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
41890#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)
41891#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)
41897#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
41898
41899#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)
41900#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)
41905#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
41906
41907#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)
41908#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)
41913#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
41914
41915#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)
41916#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)
41921#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
41922
41923#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)
41924#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)
41925#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
41931#define SNVS_LPSVCR_SV0_EN_MASK (0x1U)
41932#define SNVS_LPSVCR_SV0_EN_SHIFT (0U)
41937#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
41938
41939#define SNVS_LPSVCR_SV1_EN_MASK (0x2U)
41940#define SNVS_LPSVCR_SV1_EN_SHIFT (1U)
41945#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
41946
41947#define SNVS_LPSVCR_SV2_EN_MASK (0x4U)
41948#define SNVS_LPSVCR_SV2_EN_SHIFT (2U)
41953#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
41954
41955#define SNVS_LPSVCR_SV3_EN_MASK (0x8U)
41956#define SNVS_LPSVCR_SV3_EN_SHIFT (3U)
41961#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
41962
41963#define SNVS_LPSVCR_SV4_EN_MASK (0x10U)
41964#define SNVS_LPSVCR_SV4_EN_SHIFT (4U)
41969#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
41970
41971#define SNVS_LPSVCR_SV5_EN_MASK (0x20U)
41972#define SNVS_LPSVCR_SV5_EN_SHIFT (5U)
41977#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
41983#define SNVS_LPSECR_SRTCR_EN_MASK (0x2U)
41984#define SNVS_LPSECR_SRTCR_EN_SHIFT (1U)
41989#define SNVS_LPSECR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_SRTCR_EN_SHIFT)) & SNVS_LPSECR_SRTCR_EN_MASK)
41990
41991#define SNVS_LPSECR_MCR_EN_MASK (0x4U)
41992#define SNVS_LPSECR_MCR_EN_SHIFT (2U)
41997#define SNVS_LPSECR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_MCR_EN_SHIFT)) & SNVS_LPSECR_MCR_EN_MASK)
41998
41999#define SNVS_LPSECR_PFD_OBSERV_MASK (0x4000U)
42000#define SNVS_LPSECR_PFD_OBSERV_SHIFT (14U)
42001#define SNVS_LPSECR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_PFD_OBSERV_SHIFT)) & SNVS_LPSECR_PFD_OBSERV_MASK)
42002
42003#define SNVS_LPSECR_POR_OBSERV_MASK (0x8000U)
42004#define SNVS_LPSECR_POR_OBSERV_SHIFT (15U)
42005#define SNVS_LPSECR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_POR_OBSERV_SHIFT)) & SNVS_LPSECR_POR_OBSERV_MASK)
42006
42007#define SNVS_LPSECR_LTDC_MASK (0x70000U)
42008#define SNVS_LPSECR_LTDC_SHIFT (16U)
42009#define SNVS_LPSECR_LTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_LTDC_SHIFT)) & SNVS_LPSECR_LTDC_MASK)
42010
42011#define SNVS_LPSECR_HTDC_MASK (0x700000U)
42012#define SNVS_LPSECR_HTDC_SHIFT (20U)
42013#define SNVS_LPSECR_HTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_HTDC_SHIFT)) & SNVS_LPSECR_HTDC_MASK)
42014
42015#define SNVS_LPSECR_VRC_MASK (0x7000000U)
42016#define SNVS_LPSECR_VRC_SHIFT (24U)
42017#define SNVS_LPSECR_VRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_VRC_SHIFT)) & SNVS_LPSECR_VRC_MASK)
42018
42019#define SNVS_LPSECR_OSCB_MASK (0x10000000U)
42020#define SNVS_LPSECR_OSCB_SHIFT (28U)
42025#define SNVS_LPSECR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_OSCB_SHIFT)) & SNVS_LPSECR_OSCB_MASK)
42031#define SNVS_LPSR_LPTA_MASK (0x1U)
42032#define SNVS_LPSR_LPTA_SHIFT (0U)
42037#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
42038
42039#define SNVS_LPSR_SRTCR_MASK (0x2U)
42040#define SNVS_LPSR_SRTCR_SHIFT (1U)
42045#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
42046
42047#define SNVS_LPSR_MCR_MASK (0x4U)
42048#define SNVS_LPSR_MCR_SHIFT (2U)
42053#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
42054
42055#define SNVS_LPSR_LVD_MASK (0x8U)
42056#define SNVS_LPSR_LVD_SHIFT (3U)
42061#define SNVS_LPSR_LVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)
42062
42063#define SNVS_LPSR_ESVD_MASK (0x10000U)
42064#define SNVS_LPSR_ESVD_SHIFT (16U)
42069#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
42070
42071#define SNVS_LPSR_EO_MASK (0x20000U)
42072#define SNVS_LPSR_EO_SHIFT (17U)
42077#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
42078
42079#define SNVS_LPSR_SPOF_MASK (0x40000U)
42080#define SNVS_LPSR_SPOF_SHIFT (18U)
42085#define SNVS_LPSR_SPOF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
42086
42087#define SNVS_LPSR_SPON_MASK (0x80000U)
42088#define SNVS_LPSR_SPON_SHIFT (19U)
42093#define SNVS_LPSR_SPON(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPON_SHIFT)) & SNVS_LPSR_SPON_MASK)
42094
42095#define SNVS_LPSR_LPNS_MASK (0x40000000U)
42096#define SNVS_LPSR_LPNS_SHIFT (30U)
42101#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
42102
42103#define SNVS_LPSR_LPS_MASK (0x80000000U)
42104#define SNVS_LPSR_LPS_SHIFT (31U)
42109#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
42115#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)
42116#define SNVS_LPSRTCMR_SRTC_SHIFT (0U)
42117#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
42123#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)
42124#define SNVS_LPSRTCLR_SRTC_SHIFT (0U)
42125#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
42131#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)
42132#define SNVS_LPTAR_LPTA_SHIFT (0U)
42133#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
42139#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
42140#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
42141#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
42142
42143#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
42144#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
42145#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
42151#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
42152#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
42153#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
42159#define SNVS_LPLVDR_LVD_MASK (0xFFFFFFFFU)
42160#define SNVS_LPLVDR_LVD_SHIFT (0U)
42161#define SNVS_LPLVDR_LVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK)
42167#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
42168#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
42169#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
42175#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)
42176#define SNVS_LPZMKR_ZMK_SHIFT (0U)
42177#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
42180/* The count of SNVS_LPZMKR */
42181#define SNVS_LPZMKR_COUNT (8U)
42182
42186#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
42187#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
42188#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
42191/* The count of SNVS_LPGPR_ALIAS */
42192#define SNVS_LPGPR_ALIAS_COUNT (4U)
42193
42197#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
42198#define SNVS_LPGPR_GPR_SHIFT (0U)
42199#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
42202/* The count of SNVS_LPGPR */
42203#define SNVS_LPGPR_COUNT (8U)
42204
42208#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
42209#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
42210#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
42211
42212#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
42213#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
42214#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
42215
42216#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
42217#define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
42218#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
42224#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)
42225#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)
42226#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
42227
42228#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
42229#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
42230#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
42231
42232#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)
42233#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)
42234#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
42235
42236#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
42237#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
42238#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) /* end of group SNVS_Register_Masks */
42245
42246
42247/* SNVS - Peripheral instance base addresses */
42249#define SNVS_BASE (0x400D4000u)
42251#define SNVS ((SNVS_Type *)SNVS_BASE)
42253#define SNVS_BASE_ADDRS { SNVS_BASE }
42255#define SNVS_BASE_PTRS { SNVS }
42257#define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }
42258#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }
42259#define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }
42260 /* end of group SNVS_Peripheral_Access_Layer */
42264
42265
42266/* ----------------------------------------------------------------------------
42267 -- SPDIF Peripheral Access Layer
42268 ---------------------------------------------------------------------------- */
42269
42276typedef struct {
42277 __IO uint32_t SCR;
42278 __IO uint32_t SRCD;
42279 __IO uint32_t SRPC;
42280 __IO uint32_t SIE;
42281 union { /* offset: 0x10 */
42282 __O uint32_t SIC;
42283 __I uint32_t SIS;
42284 };
42285 __I uint32_t SRL;
42286 __I uint32_t SRR;
42287 __I uint32_t SRCSH;
42288 __I uint32_t SRCSL;
42289 __I uint32_t SRU;
42290 __I uint32_t SRQ;
42291 __O uint32_t STL;
42292 __O uint32_t STR;
42293 __IO uint32_t STCSCH;
42294 __IO uint32_t STCSCL;
42295 uint8_t RESERVED_0[8];
42296 __I uint32_t SRFM;
42297 uint8_t RESERVED_1[8];
42298 __IO uint32_t STC;
42299} SPDIF_Type;
42300
42301/* ----------------------------------------------------------------------------
42302 -- SPDIF Register Masks
42303 ---------------------------------------------------------------------------- */
42304
42313#define SPDIF_SCR_USRC_SEL_MASK (0x3U)
42314#define SPDIF_SCR_USRC_SEL_SHIFT (0U)
42321#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
42322
42323#define SPDIF_SCR_TXSEL_MASK (0x1CU)
42324#define SPDIF_SCR_TXSEL_SHIFT (2U)
42330#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
42331
42332#define SPDIF_SCR_VALCTRL_MASK (0x20U)
42333#define SPDIF_SCR_VALCTRL_SHIFT (5U)
42338#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
42339
42340#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U)
42341#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U)
42342#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
42343
42344#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U)
42345#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U)
42346#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
42347
42348#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)
42349#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)
42356#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
42357
42358#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U)
42359#define SPDIF_SCR_SOFT_RESET_SHIFT (12U)
42360#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
42361
42362#define SPDIF_SCR_LOW_POWER_MASK (0x2000U)
42363#define SPDIF_SCR_LOW_POWER_SHIFT (13U)
42364#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
42365
42366#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)
42367#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)
42374#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
42375
42376#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)
42377#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)
42382#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
42383
42384#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)
42385#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)
42390#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
42391
42392#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)
42393#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)
42400#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
42401
42402#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)
42403#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U)
42408#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
42409
42410#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)
42411#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)
42416#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
42417
42418#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)
42419#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)
42424#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
42430#define SPDIF_SRCD_USYNCMODE_MASK (0x2U)
42431#define SPDIF_SRCD_USYNCMODE_SHIFT (1U)
42436#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
42442#define SPDIF_SRPC_GAINSEL_MASK (0x38U)
42443#define SPDIF_SRPC_GAINSEL_SHIFT (3U)
42453#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
42454
42455#define SPDIF_SRPC_LOCK_MASK (0x40U)
42456#define SPDIF_SRPC_LOCK_SHIFT (6U)
42457#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
42458
42459#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)
42460#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)
42469#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
42475#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U)
42476#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U)
42477#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
42478
42479#define SPDIF_SIE_TXEM_MASK (0x2U)
42480#define SPDIF_SIE_TXEM_SHIFT (1U)
42481#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
42482
42483#define SPDIF_SIE_LOCKLOSS_MASK (0x4U)
42484#define SPDIF_SIE_LOCKLOSS_SHIFT (2U)
42485#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
42486
42487#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U)
42488#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U)
42489#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
42490
42491#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)
42492#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)
42493#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
42494
42495#define SPDIF_SIE_UQERR_MASK (0x20U)
42496#define SPDIF_SIE_UQERR_SHIFT (5U)
42497#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
42498
42499#define SPDIF_SIE_UQSYNC_MASK (0x40U)
42500#define SPDIF_SIE_UQSYNC_SHIFT (6U)
42501#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
42502
42503#define SPDIF_SIE_QRXOV_MASK (0x80U)
42504#define SPDIF_SIE_QRXOV_SHIFT (7U)
42505#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
42506
42507#define SPDIF_SIE_QRXFUL_MASK (0x100U)
42508#define SPDIF_SIE_QRXFUL_SHIFT (8U)
42509#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
42510
42511#define SPDIF_SIE_URXOV_MASK (0x200U)
42512#define SPDIF_SIE_URXOV_SHIFT (9U)
42513#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
42514
42515#define SPDIF_SIE_URXFUL_MASK (0x400U)
42516#define SPDIF_SIE_URXFUL_SHIFT (10U)
42517#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
42518
42519#define SPDIF_SIE_BITERR_MASK (0x4000U)
42520#define SPDIF_SIE_BITERR_SHIFT (14U)
42521#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
42522
42523#define SPDIF_SIE_SYMERR_MASK (0x8000U)
42524#define SPDIF_SIE_SYMERR_SHIFT (15U)
42525#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
42526
42527#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U)
42528#define SPDIF_SIE_VALNOGOOD_SHIFT (16U)
42529#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
42530
42531#define SPDIF_SIE_CNEW_MASK (0x20000U)
42532#define SPDIF_SIE_CNEW_SHIFT (17U)
42533#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
42534
42535#define SPDIF_SIE_TXRESYN_MASK (0x40000U)
42536#define SPDIF_SIE_TXRESYN_SHIFT (18U)
42537#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
42538
42539#define SPDIF_SIE_TXUNOV_MASK (0x80000U)
42540#define SPDIF_SIE_TXUNOV_SHIFT (19U)
42541#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
42542
42543#define SPDIF_SIE_LOCK_MASK (0x100000U)
42544#define SPDIF_SIE_LOCK_SHIFT (20U)
42545#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
42551#define SPDIF_SIC_LOCKLOSS_MASK (0x4U)
42552#define SPDIF_SIC_LOCKLOSS_SHIFT (2U)
42553#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
42554
42555#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U)
42556#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U)
42557#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
42558
42559#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)
42560#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)
42561#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
42562
42563#define SPDIF_SIC_UQERR_MASK (0x20U)
42564#define SPDIF_SIC_UQERR_SHIFT (5U)
42565#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
42566
42567#define SPDIF_SIC_UQSYNC_MASK (0x40U)
42568#define SPDIF_SIC_UQSYNC_SHIFT (6U)
42569#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
42570
42571#define SPDIF_SIC_QRXOV_MASK (0x80U)
42572#define SPDIF_SIC_QRXOV_SHIFT (7U)
42573#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
42574
42575#define SPDIF_SIC_URXOV_MASK (0x200U)
42576#define SPDIF_SIC_URXOV_SHIFT (9U)
42577#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
42578
42579#define SPDIF_SIC_BITERR_MASK (0x4000U)
42580#define SPDIF_SIC_BITERR_SHIFT (14U)
42581#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
42582
42583#define SPDIF_SIC_SYMERR_MASK (0x8000U)
42584#define SPDIF_SIC_SYMERR_SHIFT (15U)
42585#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
42586
42587#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U)
42588#define SPDIF_SIC_VALNOGOOD_SHIFT (16U)
42589#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
42590
42591#define SPDIF_SIC_CNEW_MASK (0x20000U)
42592#define SPDIF_SIC_CNEW_SHIFT (17U)
42593#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
42594
42595#define SPDIF_SIC_TXRESYN_MASK (0x40000U)
42596#define SPDIF_SIC_TXRESYN_SHIFT (18U)
42597#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
42598
42599#define SPDIF_SIC_TXUNOV_MASK (0x80000U)
42600#define SPDIF_SIC_TXUNOV_SHIFT (19U)
42601#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
42602
42603#define SPDIF_SIC_LOCK_MASK (0x100000U)
42604#define SPDIF_SIC_LOCK_SHIFT (20U)
42605#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
42611#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U)
42612#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U)
42613#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
42614
42615#define SPDIF_SIS_TXEM_MASK (0x2U)
42616#define SPDIF_SIS_TXEM_SHIFT (1U)
42617#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
42618
42619#define SPDIF_SIS_LOCKLOSS_MASK (0x4U)
42620#define SPDIF_SIS_LOCKLOSS_SHIFT (2U)
42621#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
42622
42623#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U)
42624#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U)
42625#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
42626
42627#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)
42628#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)
42629#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
42630
42631#define SPDIF_SIS_UQERR_MASK (0x20U)
42632#define SPDIF_SIS_UQERR_SHIFT (5U)
42633#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
42634
42635#define SPDIF_SIS_UQSYNC_MASK (0x40U)
42636#define SPDIF_SIS_UQSYNC_SHIFT (6U)
42637#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
42638
42639#define SPDIF_SIS_QRXOV_MASK (0x80U)
42640#define SPDIF_SIS_QRXOV_SHIFT (7U)
42641#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
42642
42643#define SPDIF_SIS_QRXFUL_MASK (0x100U)
42644#define SPDIF_SIS_QRXFUL_SHIFT (8U)
42645#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
42646
42647#define SPDIF_SIS_URXOV_MASK (0x200U)
42648#define SPDIF_SIS_URXOV_SHIFT (9U)
42649#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
42650
42651#define SPDIF_SIS_URXFUL_MASK (0x400U)
42652#define SPDIF_SIS_URXFUL_SHIFT (10U)
42653#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
42654
42655#define SPDIF_SIS_BITERR_MASK (0x4000U)
42656#define SPDIF_SIS_BITERR_SHIFT (14U)
42657#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
42658
42659#define SPDIF_SIS_SYMERR_MASK (0x8000U)
42660#define SPDIF_SIS_SYMERR_SHIFT (15U)
42661#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
42662
42663#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U)
42664#define SPDIF_SIS_VALNOGOOD_SHIFT (16U)
42665#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
42666
42667#define SPDIF_SIS_CNEW_MASK (0x20000U)
42668#define SPDIF_SIS_CNEW_SHIFT (17U)
42669#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
42670
42671#define SPDIF_SIS_TXRESYN_MASK (0x40000U)
42672#define SPDIF_SIS_TXRESYN_SHIFT (18U)
42673#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
42674
42675#define SPDIF_SIS_TXUNOV_MASK (0x80000U)
42676#define SPDIF_SIS_TXUNOV_SHIFT (19U)
42677#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
42678
42679#define SPDIF_SIS_LOCK_MASK (0x100000U)
42680#define SPDIF_SIS_LOCK_SHIFT (20U)
42681#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
42687#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)
42688#define SPDIF_SRL_RXDATALEFT_SHIFT (0U)
42689#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
42695#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)
42696#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U)
42697#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
42703#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)
42704#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)
42705#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
42711#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)
42712#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)
42713#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
42719#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)
42720#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U)
42721#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
42727#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)
42728#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)
42729#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
42735#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)
42736#define SPDIF_STL_TXDATALEFT_SHIFT (0U)
42737#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
42743#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)
42744#define SPDIF_STR_TXDATARIGHT_SHIFT (0U)
42745#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
42751#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)
42752#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)
42753#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
42759#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)
42760#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)
42761#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
42767#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)
42768#define SPDIF_SRFM_FREQMEAS_SHIFT (0U)
42769#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
42775#define SPDIF_STC_TXCLK_DF_MASK (0x7FU)
42776#define SPDIF_STC_TXCLK_DF_SHIFT (0U)
42782#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
42783
42784#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)
42785#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)
42790#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
42791
42792#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)
42793#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)
42803#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
42804
42805#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
42806#define SPDIF_STC_SYSCLK_DF_SHIFT (11U)
42812#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) /* end of group SPDIF_Register_Masks */
42819
42820
42821/* SPDIF - Peripheral instance base addresses */
42823#define SPDIF_BASE (0x40380000u)
42825#define SPDIF ((SPDIF_Type *)SPDIF_BASE)
42827#define SPDIF_BASE_ADDRS { SPDIF_BASE }
42829#define SPDIF_BASE_PTRS { SPDIF }
42831#define SPDIF_IRQS { SPDIF_IRQn }
42832 /* end of group SPDIF_Peripheral_Access_Layer */
42836
42837
42838/* ----------------------------------------------------------------------------
42839 -- SRC Peripheral Access Layer
42840 ---------------------------------------------------------------------------- */
42841
42848typedef struct {
42849 __IO uint32_t SCR;
42850 __I uint32_t SBMR1;
42851 __IO uint32_t SRSR;
42852 uint8_t RESERVED_0[16];
42853 __I uint32_t SBMR2;
42854 __IO uint32_t GPR[10];
42855} SRC_Type;
42856
42857/* ----------------------------------------------------------------------------
42858 -- SRC Register Masks
42859 ---------------------------------------------------------------------------- */
42860
42869#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U)
42870#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U)
42875#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)
42876
42877#define SRC_SCR_CORE0_RST_MASK (0x2000U)
42878#define SRC_SCR_CORE0_RST_SHIFT (13U)
42883#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)
42884
42885#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)
42886#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U)
42891#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)
42892
42893#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)
42894#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)
42899#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)
42900
42901#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)
42902#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)
42907#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)
42913#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)
42914#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U)
42915#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
42916
42917#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)
42918#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U)
42919#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
42920
42921#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)
42922#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U)
42923#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
42924
42925#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)
42926#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U)
42927#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
42933#define SRC_SRSR_IPP_RESET_B_MASK (0x1U)
42934#define SRC_SRSR_IPP_RESET_B_SHIFT (0U)
42939#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)
42940
42941#define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)
42942#define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)
42947#define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)
42948
42949#define SRC_SRSR_CSU_RESET_B_MASK (0x4U)
42950#define SRC_SRSR_CSU_RESET_B_SHIFT (2U)
42955#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
42956
42957#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)
42958#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)
42963#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
42964
42965#define SRC_SRSR_WDOG_RST_B_MASK (0x10U)
42966#define SRC_SRSR_WDOG_RST_B_SHIFT (4U)
42971#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)
42972
42973#define SRC_SRSR_JTAG_RST_B_MASK (0x20U)
42974#define SRC_SRSR_JTAG_RST_B_SHIFT (5U)
42979#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
42980
42981#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U)
42982#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U)
42987#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
42988
42989#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U)
42990#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U)
42995#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
42996
42997#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)
42998#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)
43003#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)
43009#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
43010#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
43011#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
43012
43013#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
43014#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
43015#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
43016
43017#define SRC_SBMR2_BMOD_MASK (0x3000000U)
43018#define SRC_SBMR2_BMOD_SHIFT (24U)
43019#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
43025#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)
43026#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)
43027#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)
43028
43029#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)
43030#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)
43031#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)
43032
43033#define SRC_GPR_PERSIST_REDUNDANT_BOOT_MASK (0xC000000U)
43034#define SRC_GPR_PERSIST_REDUNDANT_BOOT_SHIFT (26U)
43035#define SRC_GPR_PERSIST_REDUNDANT_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSIST_REDUNDANT_BOOT_SHIFT)) & SRC_GPR_PERSIST_REDUNDANT_BOOT_MASK)
43036
43037#define SRC_GPR_PERSIST_SECONDARY_BOOT_MASK (0x40000000U)
43038#define SRC_GPR_PERSIST_SECONDARY_BOOT_SHIFT (30U)
43039#define SRC_GPR_PERSIST_SECONDARY_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSIST_SECONDARY_BOOT_SHIFT)) & SRC_GPR_PERSIST_SECONDARY_BOOT_MASK)
43042/* The count of SRC_GPR */
43043#define SRC_GPR_COUNT (10U)
43044
43045 /* end of group SRC_Register_Masks */
43049
43050
43051/* SRC - Peripheral instance base addresses */
43053#define SRC_BASE (0x400F8000u)
43055#define SRC ((SRC_Type *)SRC_BASE)
43057#define SRC_BASE_ADDRS { SRC_BASE }
43059#define SRC_BASE_PTRS { SRC }
43061#define SRC_IRQS { SRC_IRQn }
43062/* Backward compatibility */
43063#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK
43064#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT
43065#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)
43066#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK
43067#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT
43068#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)
43069#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK
43070#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT
43071#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)
43072#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK
43073#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT
43074#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)
43075#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK
43076#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT
43077#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)
43078/* Extra definition */
43079#define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \
43080 | SRC_SRSR_JTAG_SW_RST_MASK \
43081 | SRC_SRSR_JTAG_RST_B_MASK \
43082 | SRC_SRSR_WDOG_RST_B_MASK \
43083 | SRC_SRSR_IPP_USER_RESET_B_MASK \
43084 | SRC_SRSR_CSU_RESET_B_MASK \
43085 | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \
43086 | SRC_SRSR_IPP_RESET_B_MASK)
43087
43088 /* end of group SRC_Peripheral_Access_Layer */
43092
43093
43094/* ----------------------------------------------------------------------------
43095 -- TEMPMON Peripheral Access Layer
43096 ---------------------------------------------------------------------------- */
43097
43104typedef struct {
43105 uint8_t RESERVED_0[384];
43106 __IO uint32_t TEMPSENSE0;
43107 __IO uint32_t TEMPSENSE0_SET;
43108 __IO uint32_t TEMPSENSE0_CLR;
43109 __IO uint32_t TEMPSENSE0_TOG;
43110 __IO uint32_t TEMPSENSE1;
43111 __IO uint32_t TEMPSENSE1_SET;
43112 __IO uint32_t TEMPSENSE1_CLR;
43113 __IO uint32_t TEMPSENSE1_TOG;
43114 uint8_t RESERVED_1[240];
43115 __IO uint32_t TEMPSENSE2;
43116 __IO uint32_t TEMPSENSE2_SET;
43117 __IO uint32_t TEMPSENSE2_CLR;
43118 __IO uint32_t TEMPSENSE2_TOG;
43119} TEMPMON_Type;
43120
43121/* ----------------------------------------------------------------------------
43122 -- TEMPMON Register Masks
43123 ---------------------------------------------------------------------------- */
43124
43133#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)
43134#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)
43139#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)
43140
43141#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)
43142#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)
43147#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)
43148
43149#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)
43150#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)
43155#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)
43156
43157#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)
43158#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)
43159#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)
43160
43161#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)
43162#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)
43163#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)
43169#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)
43170#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)
43175#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)
43176
43177#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)
43178#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)
43183#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)
43184
43185#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)
43186#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)
43191#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
43192
43193#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)
43194#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)
43195#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)
43196
43197#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)
43198#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)
43199#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)
43205#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)
43206#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)
43211#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)
43212
43213#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)
43214#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)
43219#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)
43220
43221#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)
43222#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)
43227#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
43228
43229#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)
43230#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)
43231#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)
43232
43233#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)
43234#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)
43235#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)
43241#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)
43242#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)
43247#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)
43248
43249#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)
43250#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)
43255#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)
43256
43257#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)
43258#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)
43263#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)
43264
43265#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)
43266#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)
43267#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)
43268
43269#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)
43270#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)
43271#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)
43277#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)
43278#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)
43285#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)
43291#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)
43292#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)
43299#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
43305#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)
43306#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)
43313#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
43319#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)
43320#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)
43327#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
43333#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)
43334#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)
43335#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)
43336
43337#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
43338#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)
43339#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)
43345#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)
43346#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)
43347#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)
43348
43349#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
43350#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)
43351#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)
43357#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)
43358#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)
43359#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)
43360
43361#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
43362#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)
43363#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)
43369#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)
43370#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)
43371#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)
43372
43373#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
43374#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)
43375#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) /* end of group TEMPMON_Register_Masks */
43382
43383
43384/* TEMPMON - Peripheral instance base addresses */
43386#define TEMPMON_BASE (0x400D8000u)
43388#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE)
43390#define TEMPMON_BASE_ADDRS { TEMPMON_BASE }
43392#define TEMPMON_BASE_PTRS { TEMPMON }
43393 /* end of group TEMPMON_Peripheral_Access_Layer */
43397
43398
43399/* ----------------------------------------------------------------------------
43400 -- TMR Peripheral Access Layer
43401 ---------------------------------------------------------------------------- */
43402
43409typedef struct {
43410 struct { /* offset: 0x0, array step: 0x20 */
43411 __IO uint16_t COMP1;
43412 __IO uint16_t COMP2;
43413 __IO uint16_t CAPT;
43414 __IO uint16_t LOAD;
43415 __IO uint16_t HOLD;
43416 __IO uint16_t CNTR;
43417 __IO uint16_t CTRL;
43418 __IO uint16_t SCTRL;
43419 __IO uint16_t CMPLD1;
43420 __IO uint16_t CMPLD2;
43421 __IO uint16_t CSCTRL;
43422 __IO uint16_t FILT;
43423 __IO uint16_t DMA;
43424 uint8_t RESERVED_0[4];
43425 __IO uint16_t ENBL;
43426 } CHANNEL[4];
43427} TMR_Type;
43428
43429/* ----------------------------------------------------------------------------
43430 -- TMR Register Masks
43431 ---------------------------------------------------------------------------- */
43432
43441#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)
43442#define TMR_COMP1_COMPARISON_1_SHIFT (0U)
43445#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
43448/* The count of TMR_COMP1 */
43449#define TMR_COMP1_COUNT (4U)
43450
43454#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)
43455#define TMR_COMP2_COMPARISON_2_SHIFT (0U)
43458#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
43461/* The count of TMR_COMP2 */
43462#define TMR_COMP2_COUNT (4U)
43463
43467#define TMR_CAPT_CAPTURE_MASK (0xFFFFU)
43468#define TMR_CAPT_CAPTURE_SHIFT (0U)
43471#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
43474/* The count of TMR_CAPT */
43475#define TMR_CAPT_COUNT (4U)
43476
43480#define TMR_LOAD_LOAD_MASK (0xFFFFU)
43481#define TMR_LOAD_LOAD_SHIFT (0U)
43484#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
43487/* The count of TMR_LOAD */
43488#define TMR_LOAD_COUNT (4U)
43489
43493#define TMR_HOLD_HOLD_MASK (0xFFFFU)
43494#define TMR_HOLD_HOLD_SHIFT (0U)
43495#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
43498/* The count of TMR_HOLD */
43499#define TMR_HOLD_COUNT (4U)
43500
43504#define TMR_CNTR_COUNTER_MASK (0xFFFFU)
43505#define TMR_CNTR_COUNTER_SHIFT (0U)
43506#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
43509/* The count of TMR_CNTR */
43510#define TMR_CNTR_COUNT (4U)
43511
43515#define TMR_CTRL_OUTMODE_MASK (0x7U)
43516#define TMR_CTRL_OUTMODE_SHIFT (0U)
43527#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
43528
43529#define TMR_CTRL_COINIT_MASK (0x8U)
43530#define TMR_CTRL_COINIT_SHIFT (3U)
43535#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
43536
43537#define TMR_CTRL_DIR_MASK (0x10U)
43538#define TMR_CTRL_DIR_SHIFT (4U)
43543#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
43544
43545#define TMR_CTRL_LENGTH_MASK (0x20U)
43546#define TMR_CTRL_LENGTH_SHIFT (5U)
43555#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
43556
43557#define TMR_CTRL_ONCE_MASK (0x40U)
43558#define TMR_CTRL_ONCE_SHIFT (6U)
43566#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
43567
43568#define TMR_CTRL_SCS_MASK (0x180U)
43569#define TMR_CTRL_SCS_SHIFT (7U)
43576#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
43577
43578#define TMR_CTRL_PCS_MASK (0x1E00U)
43579#define TMR_CTRL_PCS_SHIFT (9U)
43598#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
43599
43600#define TMR_CTRL_CM_MASK (0xE000U)
43601#define TMR_CTRL_CM_SHIFT (13U)
43615#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
43618/* The count of TMR_CTRL */
43619#define TMR_CTRL_COUNT (4U)
43620
43624#define TMR_SCTRL_OEN_MASK (0x1U)
43625#define TMR_SCTRL_OEN_SHIFT (0U)
43631#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
43632
43633#define TMR_SCTRL_OPS_MASK (0x2U)
43634#define TMR_SCTRL_OPS_SHIFT (1U)
43639#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
43640
43641#define TMR_SCTRL_FORCE_MASK (0x4U)
43642#define TMR_SCTRL_FORCE_SHIFT (2U)
43645#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
43646
43647#define TMR_SCTRL_VAL_MASK (0x8U)
43648#define TMR_SCTRL_VAL_SHIFT (3U)
43651#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
43652
43653#define TMR_SCTRL_EEOF_MASK (0x10U)
43654#define TMR_SCTRL_EEOF_SHIFT (4U)
43657#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
43658
43659#define TMR_SCTRL_MSTR_MASK (0x20U)
43660#define TMR_SCTRL_MSTR_SHIFT (5U)
43663#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
43664
43665#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)
43666#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)
43673#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
43674
43675#define TMR_SCTRL_INPUT_MASK (0x100U)
43676#define TMR_SCTRL_INPUT_SHIFT (8U)
43679#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
43680
43681#define TMR_SCTRL_IPS_MASK (0x200U)
43682#define TMR_SCTRL_IPS_SHIFT (9U)
43685#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
43686
43687#define TMR_SCTRL_IEFIE_MASK (0x400U)
43688#define TMR_SCTRL_IEFIE_SHIFT (10U)
43691#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
43692
43693#define TMR_SCTRL_IEF_MASK (0x800U)
43694#define TMR_SCTRL_IEF_SHIFT (11U)
43697#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
43698
43699#define TMR_SCTRL_TOFIE_MASK (0x1000U)
43700#define TMR_SCTRL_TOFIE_SHIFT (12U)
43703#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
43704
43705#define TMR_SCTRL_TOF_MASK (0x2000U)
43706#define TMR_SCTRL_TOF_SHIFT (13U)
43709#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
43710
43711#define TMR_SCTRL_TCFIE_MASK (0x4000U)
43712#define TMR_SCTRL_TCFIE_SHIFT (14U)
43715#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
43716
43717#define TMR_SCTRL_TCF_MASK (0x8000U)
43718#define TMR_SCTRL_TCF_SHIFT (15U)
43721#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
43724/* The count of TMR_SCTRL */
43725#define TMR_SCTRL_COUNT (4U)
43726
43730#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)
43731#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)
43732#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
43735/* The count of TMR_CMPLD1 */
43736#define TMR_CMPLD1_COUNT (4U)
43737
43741#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)
43742#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)
43743#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
43746/* The count of TMR_CMPLD2 */
43747#define TMR_CMPLD2_COUNT (4U)
43748
43752#define TMR_CSCTRL_CL1_MASK (0x3U)
43753#define TMR_CSCTRL_CL1_SHIFT (0U)
43760#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
43761
43762#define TMR_CSCTRL_CL2_MASK (0xCU)
43763#define TMR_CSCTRL_CL2_SHIFT (2U)
43770#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
43771
43772#define TMR_CSCTRL_TCF1_MASK (0x10U)
43773#define TMR_CSCTRL_TCF1_SHIFT (4U)
43776#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
43777
43778#define TMR_CSCTRL_TCF2_MASK (0x20U)
43779#define TMR_CSCTRL_TCF2_SHIFT (5U)
43782#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
43783
43784#define TMR_CSCTRL_TCF1EN_MASK (0x40U)
43785#define TMR_CSCTRL_TCF1EN_SHIFT (6U)
43788#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
43789
43790#define TMR_CSCTRL_TCF2EN_MASK (0x80U)
43791#define TMR_CSCTRL_TCF2EN_SHIFT (7U)
43794#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
43795
43796#define TMR_CSCTRL_UP_MASK (0x200U)
43797#define TMR_CSCTRL_UP_SHIFT (9U)
43802#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
43803
43804#define TMR_CSCTRL_TCI_MASK (0x400U)
43805#define TMR_CSCTRL_TCI_SHIFT (10U)
43810#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
43811
43812#define TMR_CSCTRL_ROC_MASK (0x800U)
43813#define TMR_CSCTRL_ROC_SHIFT (11U)
43818#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
43819
43820#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)
43821#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U)
43826#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
43827
43828#define TMR_CSCTRL_FAULT_MASK (0x2000U)
43829#define TMR_CSCTRL_FAULT_SHIFT (13U)
43834#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
43835
43836#define TMR_CSCTRL_DBG_EN_MASK (0xC000U)
43837#define TMR_CSCTRL_DBG_EN_SHIFT (14U)
43844#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
43847/* The count of TMR_CSCTRL */
43848#define TMR_CSCTRL_COUNT (4U)
43849
43853#define TMR_FILT_FILT_PER_MASK (0xFFU)
43854#define TMR_FILT_FILT_PER_SHIFT (0U)
43857#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
43858
43859#define TMR_FILT_FILT_CNT_MASK (0x700U)
43860#define TMR_FILT_FILT_CNT_SHIFT (8U)
43863#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
43866/* The count of TMR_FILT */
43867#define TMR_FILT_COUNT (4U)
43868
43872#define TMR_DMA_IEFDE_MASK (0x1U)
43873#define TMR_DMA_IEFDE_SHIFT (0U)
43876#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
43877
43878#define TMR_DMA_CMPLD1DE_MASK (0x2U)
43879#define TMR_DMA_CMPLD1DE_SHIFT (1U)
43882#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
43883
43884#define TMR_DMA_CMPLD2DE_MASK (0x4U)
43885#define TMR_DMA_CMPLD2DE_SHIFT (2U)
43888#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
43891/* The count of TMR_DMA */
43892#define TMR_DMA_COUNT (4U)
43893
43897#define TMR_ENBL_ENBL_MASK (0xFU)
43898#define TMR_ENBL_ENBL_SHIFT (0U)
43903#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
43906/* The count of TMR_ENBL */
43907#define TMR_ENBL_COUNT (4U)
43908
43909 /* end of group TMR_Register_Masks */
43913
43914
43915/* TMR - Peripheral instance base addresses */
43917#define TMR1_BASE (0x401DC000u)
43919#define TMR1 ((TMR_Type *)TMR1_BASE)
43921#define TMR2_BASE (0x401E0000u)
43923#define TMR2 ((TMR_Type *)TMR2_BASE)
43925#define TMR3_BASE (0x401E4000u)
43927#define TMR3 ((TMR_Type *)TMR3_BASE)
43929#define TMR4_BASE (0x401E8000u)
43931#define TMR4 ((TMR_Type *)TMR4_BASE)
43933#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
43935#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
43937#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
43938 /* end of group TMR_Peripheral_Access_Layer */
43942
43943
43944/* ----------------------------------------------------------------------------
43945 -- TRNG Peripheral Access Layer
43946 ---------------------------------------------------------------------------- */
43947
43954typedef struct {
43955 __IO uint32_t MCTL;
43956 __IO uint32_t SCMISC;
43957 __IO uint32_t PKRRNG;
43958 union { /* offset: 0xC */
43959 __IO uint32_t PKRMAX;
43960 __I uint32_t PKRSQ;
43961 };
43962 __IO uint32_t SDCTL;
43963 union { /* offset: 0x14 */
43964 __IO uint32_t SBLIM;
43965 __I uint32_t TOTSAM;
43966 };
43967 __IO uint32_t FRQMIN;
43968 union { /* offset: 0x1C */
43969 __I uint32_t FRQCNT;
43970 __IO uint32_t FRQMAX;
43971 };
43972 union { /* offset: 0x20 */
43973 __I uint32_t SCMC;
43974 __IO uint32_t SCML;
43975 };
43976 union { /* offset: 0x24 */
43977 __I uint32_t SCR1C;
43978 __IO uint32_t SCR1L;
43979 };
43980 union { /* offset: 0x28 */
43981 __I uint32_t SCR2C;
43982 __IO uint32_t SCR2L;
43983 };
43984 union { /* offset: 0x2C */
43985 __I uint32_t SCR3C;
43986 __IO uint32_t SCR3L;
43987 };
43988 union { /* offset: 0x30 */
43989 __I uint32_t SCR4C;
43990 __IO uint32_t SCR4L;
43991 };
43992 union { /* offset: 0x34 */
43993 __I uint32_t SCR5C;
43994 __IO uint32_t SCR5L;
43995 };
43996 union { /* offset: 0x38 */
43997 __I uint32_t SCR6PC;
43998 __IO uint32_t SCR6PL;
43999 };
44000 __I uint32_t STATUS;
44001 __I uint32_t ENT[16];
44002 __I uint32_t PKRCNT10;
44003 __I uint32_t PKRCNT32;
44004 __I uint32_t PKRCNT54;
44005 __I uint32_t PKRCNT76;
44006 __I uint32_t PKRCNT98;
44007 __I uint32_t PKRCNTBA;
44008 __I uint32_t PKRCNTDC;
44009 __I uint32_t PKRCNTFE;
44010 __IO uint32_t SEC_CFG;
44011 __IO uint32_t INT_CTRL;
44012 __IO uint32_t INT_MASK;
44013 __I uint32_t INT_STATUS;
44014 uint8_t RESERVED_0[64];
44015 __I uint32_t VID1;
44016 __I uint32_t VID2;
44017} TRNG_Type;
44018
44019/* ----------------------------------------------------------------------------
44020 -- TRNG Register Masks
44021 ---------------------------------------------------------------------------- */
44022
44031#define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
44032#define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
44039#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
44040
44041#define TRNG_MCTL_OSC_DIV_MASK (0xCU)
44042#define TRNG_MCTL_OSC_DIV_SHIFT (2U)
44049#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
44050
44051#define TRNG_MCTL_UNUSED4_MASK (0x10U)
44052#define TRNG_MCTL_UNUSED4_SHIFT (4U)
44053#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
44054
44055#define TRNG_MCTL_UNUSED5_MASK (0x20U)
44056#define TRNG_MCTL_UNUSED5_SHIFT (5U)
44057#define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)
44058
44059#define TRNG_MCTL_RST_DEF_MASK (0x40U)
44060#define TRNG_MCTL_RST_DEF_SHIFT (6U)
44061#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
44062
44063#define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
44064#define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
44065#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
44066
44067#define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
44068#define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
44069#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
44070
44071#define TRNG_MCTL_FCT_VAL_MASK (0x200U)
44072#define TRNG_MCTL_FCT_VAL_SHIFT (9U)
44073#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
44074
44075#define TRNG_MCTL_ENT_VAL_MASK (0x400U)
44076#define TRNG_MCTL_ENT_VAL_SHIFT (10U)
44077#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
44078
44079#define TRNG_MCTL_TST_OUT_MASK (0x800U)
44080#define TRNG_MCTL_TST_OUT_SHIFT (11U)
44081#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
44082
44083#define TRNG_MCTL_ERR_MASK (0x1000U)
44084#define TRNG_MCTL_ERR_SHIFT (12U)
44085#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
44086
44087#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
44088#define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
44089#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
44090
44091#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U)
44092#define TRNG_MCTL_LRUN_CONT_SHIFT (14U)
44093#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)
44094
44095#define TRNG_MCTL_PRGM_MASK (0x10000U)
44096#define TRNG_MCTL_PRGM_SHIFT (16U)
44097#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
44103#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
44104#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
44105#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
44106
44107#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
44108#define TRNG_SCMISC_RTY_CT_SHIFT (16U)
44109#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
44115#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
44116#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
44117#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
44123#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
44124#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
44127#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
44133#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
44134#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
44137#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
44143#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
44144#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
44145#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
44146
44147#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
44148#define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
44149#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
44155#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
44156#define TRNG_SBLIM_SB_LIM_SHIFT (0U)
44157#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
44163#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
44164#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
44165#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
44171#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
44172#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
44173#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
44179#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
44180#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
44181#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
44187#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
44188#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
44189#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
44195#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
44196#define TRNG_SCMC_MONO_CT_SHIFT (0U)
44197#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
44203#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
44204#define TRNG_SCML_MONO_MAX_SHIFT (0U)
44205#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
44206
44207#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
44208#define TRNG_SCML_MONO_RNG_SHIFT (16U)
44209#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
44215#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
44216#define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
44217#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
44218
44219#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
44220#define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
44221#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
44227#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
44228#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
44229#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
44230
44231#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
44232#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
44233#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
44239#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
44240#define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
44241#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
44242
44243#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
44244#define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
44245#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
44251#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
44252#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
44253#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
44254
44255#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
44256#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
44257#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
44263#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
44264#define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
44265#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
44266
44267#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
44268#define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
44269#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
44275#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
44276#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
44277#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
44278
44279#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
44280#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
44281#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
44287#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
44288#define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
44289#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
44290
44291#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
44292#define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
44293#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
44299#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
44300#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
44301#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
44302
44303#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
44304#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
44305#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
44311#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
44312#define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
44313#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
44314
44315#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
44316#define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
44317#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
44323#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
44324#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
44325#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
44326
44327#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
44328#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
44329#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
44335#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
44336#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
44337#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
44338
44339#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
44340#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
44341#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
44347#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
44348#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
44349#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
44350
44351#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
44352#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
44353#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
44359#define TRNG_STATUS_TF1BR0_MASK (0x1U)
44360#define TRNG_STATUS_TF1BR0_SHIFT (0U)
44361#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
44362
44363#define TRNG_STATUS_TF1BR1_MASK (0x2U)
44364#define TRNG_STATUS_TF1BR1_SHIFT (1U)
44365#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
44366
44367#define TRNG_STATUS_TF2BR0_MASK (0x4U)
44368#define TRNG_STATUS_TF2BR0_SHIFT (2U)
44369#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
44370
44371#define TRNG_STATUS_TF2BR1_MASK (0x8U)
44372#define TRNG_STATUS_TF2BR1_SHIFT (3U)
44373#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
44374
44375#define TRNG_STATUS_TF3BR0_MASK (0x10U)
44376#define TRNG_STATUS_TF3BR0_SHIFT (4U)
44377#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
44378
44379#define TRNG_STATUS_TF3BR1_MASK (0x20U)
44380#define TRNG_STATUS_TF3BR1_SHIFT (5U)
44381#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
44382
44383#define TRNG_STATUS_TF4BR0_MASK (0x40U)
44384#define TRNG_STATUS_TF4BR0_SHIFT (6U)
44385#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
44386
44387#define TRNG_STATUS_TF4BR1_MASK (0x80U)
44388#define TRNG_STATUS_TF4BR1_SHIFT (7U)
44389#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
44390
44391#define TRNG_STATUS_TF5BR0_MASK (0x100U)
44392#define TRNG_STATUS_TF5BR0_SHIFT (8U)
44393#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
44394
44395#define TRNG_STATUS_TF5BR1_MASK (0x200U)
44396#define TRNG_STATUS_TF5BR1_SHIFT (9U)
44397#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
44398
44399#define TRNG_STATUS_TF6PBR0_MASK (0x400U)
44400#define TRNG_STATUS_TF6PBR0_SHIFT (10U)
44401#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
44402
44403#define TRNG_STATUS_TF6PBR1_MASK (0x800U)
44404#define TRNG_STATUS_TF6PBR1_SHIFT (11U)
44405#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
44406
44407#define TRNG_STATUS_TFSB_MASK (0x1000U)
44408#define TRNG_STATUS_TFSB_SHIFT (12U)
44409#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
44410
44411#define TRNG_STATUS_TFLR_MASK (0x2000U)
44412#define TRNG_STATUS_TFLR_SHIFT (13U)
44413#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
44414
44415#define TRNG_STATUS_TFP_MASK (0x4000U)
44416#define TRNG_STATUS_TFP_SHIFT (14U)
44417#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
44418
44419#define TRNG_STATUS_TFMB_MASK (0x8000U)
44420#define TRNG_STATUS_TFMB_SHIFT (15U)
44421#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
44422
44423#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
44424#define TRNG_STATUS_RETRY_CT_SHIFT (16U)
44425#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
44431#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
44432#define TRNG_ENT_ENT_SHIFT (0U)
44433#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
44436/* The count of TRNG_ENT */
44437#define TRNG_ENT_COUNT (16U)
44438
44442#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
44443#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
44444#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
44445
44446#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
44447#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
44448#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
44454#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
44455#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
44456#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
44457
44458#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
44459#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
44460#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
44466#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
44467#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
44468#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
44469
44470#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
44471#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
44472#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
44478#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
44479#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
44480#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
44481
44482#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
44483#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
44484#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
44490#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
44491#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
44492#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
44493
44494#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
44495#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
44496#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
44502#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
44503#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
44504#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
44505
44506#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
44507#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
44508#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
44514#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
44515#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
44516#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
44517
44518#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
44519#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
44520#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
44526#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
44527#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
44528#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
44529
44530#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
44531#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
44532#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
44538#define TRNG_SEC_CFG_SH0_MASK (0x1U)
44539#define TRNG_SEC_CFG_SH0_SHIFT (0U)
44544#define TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)
44545
44546#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
44547#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
44552#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
44553
44554#define TRNG_SEC_CFG_SK_VAL_MASK (0x4U)
44555#define TRNG_SEC_CFG_SK_VAL_SHIFT (2U)
44560#define TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)
44566#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
44567#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
44572#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
44573
44574#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
44575#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
44580#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
44581
44582#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
44583#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
44588#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
44589
44590#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
44591#define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
44592#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
44598#define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
44599#define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
44604#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
44605
44606#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
44607#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
44612#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
44613
44614#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
44615#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
44620#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
44626#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
44627#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
44632#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
44633
44634#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
44635#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
44640#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
44641
44642#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
44643#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
44648#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
44654#define TRNG_VID1_MIN_REV_MASK (0xFFU)
44655#define TRNG_VID1_MIN_REV_SHIFT (0U)
44659#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
44660
44661#define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
44662#define TRNG_VID1_MAJ_REV_SHIFT (8U)
44666#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
44667
44668#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
44669#define TRNG_VID1_IP_ID_SHIFT (16U)
44673#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
44679#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
44680#define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
44684#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
44685
44686#define TRNG_VID2_ECO_REV_MASK (0xFF00U)
44687#define TRNG_VID2_ECO_REV_SHIFT (8U)
44691#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
44692
44693#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
44694#define TRNG_VID2_INTG_OPT_SHIFT (16U)
44698#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
44699
44700#define TRNG_VID2_ERA_MASK (0xFF000000U)
44701#define TRNG_VID2_ERA_SHIFT (24U)
44705#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) /* end of group TRNG_Register_Masks */
44712
44713
44714/* TRNG - Peripheral instance base addresses */
44716#define TRNG_BASE (0x400CC000u)
44718#define TRNG ((TRNG_Type *)TRNG_BASE)
44720#define TRNG_BASE_ADDRS { TRNG_BASE }
44722#define TRNG_BASE_PTRS { TRNG }
44724#define TRNG_IRQS { TRNG_IRQn }
44725 /* end of group TRNG_Peripheral_Access_Layer */
44729
44730
44731/* ----------------------------------------------------------------------------
44732 -- TSC Peripheral Access Layer
44733 ---------------------------------------------------------------------------- */
44734
44741typedef struct {
44742 __IO uint32_t BASIC_SETTING;
44743 uint8_t RESERVED_0[12];
44744 __IO uint32_t PRE_CHARGE_TIME;
44745 uint8_t RESERVED_1[12];
44746 __IO uint32_t FLOW_CONTROL;
44747 uint8_t RESERVED_2[12];
44748 __I uint32_t MEASEURE_VALUE;
44749 uint8_t RESERVED_3[12];
44750 __IO uint32_t INT_EN;
44751 uint8_t RESERVED_4[12];
44752 __IO uint32_t INT_SIG_EN;
44753 uint8_t RESERVED_5[12];
44754 __IO uint32_t INT_STATUS;
44755 uint8_t RESERVED_6[12];
44756 __IO uint32_t DEBUG_MODE;
44757 uint8_t RESERVED_7[12];
44758 __IO uint32_t DEBUG_MODE2;
44759} TSC_Type;
44760
44761/* ----------------------------------------------------------------------------
44762 -- TSC Register Masks
44763 ---------------------------------------------------------------------------- */
44764
44773#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U)
44774#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U)
44779#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK)
44780
44781#define TSC_BASIC_SETTING_WIRE_4_5_MASK (0x10U)
44782#define TSC_BASIC_SETTING_WIRE_4_5_SHIFT (4U)
44787#define TSC_BASIC_SETTING_WIRE_4_5(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_WIRE_4_5_SHIFT)) & TSC_BASIC_SETTING_WIRE_4_5_MASK)
44788
44789#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U)
44790#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U)
44793#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK)
44799#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU)
44800#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U)
44801#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK)
44807#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U)
44808#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U)
44811#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK)
44812
44813#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U)
44814#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U)
44819#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK)
44820
44821#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U)
44822#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U)
44827#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK)
44828
44829#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U)
44830#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U)
44835#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK)
44836
44837#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U)
44838#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U)
44843#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK)
44849#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU)
44850#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U)
44853#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK)
44854
44855#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U)
44856#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U)
44859#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK)
44865#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U)
44866#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U)
44871#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK)
44872
44873#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U)
44874#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U)
44879#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK)
44880
44881#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U)
44882#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U)
44887#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK)
44893#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U)
44894#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U)
44897#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK)
44898
44899#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U)
44900#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U)
44905#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK)
44906
44907#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U)
44908#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U)
44913#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK)
44914
44915#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U)
44916#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U)
44921#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK)
44927#define TSC_INT_STATUS_MEASURE_MASK (0x1U)
44928#define TSC_INT_STATUS_MEASURE_SHIFT (0U)
44933#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK)
44934
44935#define TSC_INT_STATUS_DETECT_MASK (0x10U)
44936#define TSC_INT_STATUS_DETECT_SHIFT (4U)
44941#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK)
44942
44943#define TSC_INT_STATUS_VALID_MASK (0x100U)
44944#define TSC_INT_STATUS_VALID_SHIFT (8U)
44949#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK)
44950
44951#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U)
44952#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U)
44957#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK)
44963#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU)
44964#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U)
44967#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK)
44968
44969#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U)
44970#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U)
44973#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK)
44974
44975#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U)
44976#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U)
44979#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK)
44980
44981#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U)
44982#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U)
44987#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK)
44988
44989#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U)
44990#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U)
44995#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK)
44996
44997#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U)
44998#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U)
45003#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK)
45004
45005#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U)
45006#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U)
45011#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK)
45017#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U)
45018#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U)
45023#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK)
45024
45025#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U)
45026#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U)
45031#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK)
45032
45033#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U)
45034#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U)
45039#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK)
45040
45041#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U)
45042#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U)
45047#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK)
45048
45049#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U)
45050#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U)
45055#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK)
45056
45057#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U)
45058#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U)
45063#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK)
45064
45065#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U)
45066#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U)
45071#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK)
45072
45073#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U)
45074#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U)
45079#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK)
45080
45081#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U)
45082#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U)
45087#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK)
45088
45089#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U)
45090#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U)
45095#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK)
45096
45097#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U)
45098#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U)
45103#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK)
45104
45105#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U)
45106#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U)
45111#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK)
45112
45113#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U)
45114#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U)
45119#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK)
45120
45121#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U)
45122#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U)
45127#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK)
45128
45129#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U)
45130#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U)
45135#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK)
45136
45137#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U)
45138#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U)
45143#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK)
45144
45145#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U)
45146#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U)
45151#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK)
45152
45153#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U)
45154#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U)
45164#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK)
45165
45166#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U)
45167#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U)
45172#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK)
45173
45174#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U)
45175#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U)
45180#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK)
45181
45182#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U)
45183#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U)
45188#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK)
45189
45190#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U)
45191#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U)
45198#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) /* end of group TSC_Register_Masks */
45205
45206
45207/* TSC - Peripheral instance base addresses */
45209#define TSC_BASE (0x400E0000u)
45211#define TSC ((TSC_Type *)TSC_BASE)
45213#define TSC_BASE_ADDRS { TSC_BASE }
45215#define TSC_BASE_PTRS { TSC }
45217#define TSC_IRQS { TSC_DIG_IRQn }
45218/* Backward compatibility */
45219#define TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_WIRE_4_5_MASK
45220#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_WIRE_4_5_SHIFT
45221#define TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_WIRE_4_5(x)
45222
45223 /* end of group TSC_Peripheral_Access_Layer */
45227
45228
45229/* ----------------------------------------------------------------------------
45230 -- USB Peripheral Access Layer
45231 ---------------------------------------------------------------------------- */
45232
45239typedef struct {
45240 __I uint32_t ID;
45241 __I uint32_t HWGENERAL;
45242 __I uint32_t HWHOST;
45243 __I uint32_t HWDEVICE;
45244 __I uint32_t HWTXBUF;
45245 __I uint32_t HWRXBUF;
45246 uint8_t RESERVED_0[104];
45247 __IO uint32_t GPTIMER0LD;
45248 __IO uint32_t GPTIMER0CTRL;
45249 __IO uint32_t GPTIMER1LD;
45250 __IO uint32_t GPTIMER1CTRL;
45251 __IO uint32_t SBUSCFG;
45252 uint8_t RESERVED_1[108];
45253 __I uint8_t CAPLENGTH;
45254 uint8_t RESERVED_2[1];
45255 __I uint16_t HCIVERSION;
45256 __I uint32_t HCSPARAMS;
45257 __I uint32_t HCCPARAMS;
45258 uint8_t RESERVED_3[20];
45259 __I uint16_t DCIVERSION;
45260 uint8_t RESERVED_4[2];
45261 __I uint32_t DCCPARAMS;
45262 uint8_t RESERVED_5[24];
45263 __IO uint32_t USBCMD;
45264 __IO uint32_t USBSTS;
45265 __IO uint32_t USBINTR;
45266 __IO uint32_t FRINDEX;
45267 uint8_t RESERVED_6[4];
45268 union { /* offset: 0x154 */
45269 __IO uint32_t DEVICEADDR;
45270 __IO uint32_t PERIODICLISTBASE;
45271 };
45272 union { /* offset: 0x158 */
45273 __IO uint32_t ASYNCLISTADDR;
45274 __IO uint32_t ENDPTLISTADDR;
45275 };
45276 uint8_t RESERVED_7[4];
45277 __IO uint32_t BURSTSIZE;
45278 __IO uint32_t TXFILLTUNING;
45279 uint8_t RESERVED_8[16];
45280 __IO uint32_t ENDPTNAK;
45281 __IO uint32_t ENDPTNAKEN;
45282 __I uint32_t CONFIGFLAG;
45283 __IO uint32_t PORTSC1;
45284 uint8_t RESERVED_9[28];
45285 __IO uint32_t OTGSC;
45286 __IO uint32_t USBMODE;
45287 __IO uint32_t ENDPTSETUPSTAT;
45288 __IO uint32_t ENDPTPRIME;
45289 __IO uint32_t ENDPTFLUSH;
45290 __I uint32_t ENDPTSTAT;
45291 __IO uint32_t ENDPTCOMPLETE;
45292 __IO uint32_t ENDPTCTRL0;
45293 __IO uint32_t ENDPTCTRL[7];
45294} USB_Type;
45295
45296/* ----------------------------------------------------------------------------
45297 -- USB Register Masks
45298 ---------------------------------------------------------------------------- */
45299
45308#define USB_ID_ID_MASK (0x3FU)
45309#define USB_ID_ID_SHIFT (0U)
45310#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
45311
45312#define USB_ID_NID_MASK (0x3F00U)
45313#define USB_ID_NID_SHIFT (8U)
45314#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
45315
45316#define USB_ID_REVISION_MASK (0xFF0000U)
45317#define USB_ID_REVISION_SHIFT (16U)
45318#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
45324#define USB_HWGENERAL_PHYW_MASK (0x30U)
45325#define USB_HWGENERAL_PHYW_SHIFT (4U)
45332#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
45333
45334#define USB_HWGENERAL_PHYM_MASK (0x1C0U)
45335#define USB_HWGENERAL_PHYM_SHIFT (6U)
45346#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
45347
45348#define USB_HWGENERAL_SM_MASK (0x600U)
45349#define USB_HWGENERAL_SM_SHIFT (9U)
45356#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
45362#define USB_HWHOST_HC_MASK (0x1U)
45363#define USB_HWHOST_HC_SHIFT (0U)
45368#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
45369
45370#define USB_HWHOST_NPORT_MASK (0xEU)
45371#define USB_HWHOST_NPORT_SHIFT (1U)
45372#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
45378#define USB_HWDEVICE_DC_MASK (0x1U)
45379#define USB_HWDEVICE_DC_SHIFT (0U)
45384#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
45385
45386#define USB_HWDEVICE_DEVEP_MASK (0x3EU)
45387#define USB_HWDEVICE_DEVEP_SHIFT (1U)
45388#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
45394#define USB_HWTXBUF_TXBURST_MASK (0xFFU)
45395#define USB_HWTXBUF_TXBURST_SHIFT (0U)
45396#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
45397
45398#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
45399#define USB_HWTXBUF_TXCHANADD_SHIFT (16U)
45400#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
45406#define USB_HWRXBUF_RXBURST_MASK (0xFFU)
45407#define USB_HWRXBUF_RXBURST_SHIFT (0U)
45408#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
45409
45410#define USB_HWRXBUF_RXADD_MASK (0xFF00U)
45411#define USB_HWRXBUF_RXADD_SHIFT (8U)
45412#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
45418#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
45419#define USB_GPTIMER0LD_GPTLD_SHIFT (0U)
45420#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
45426#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
45427#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
45428#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
45429
45430#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
45431#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
45436#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
45437
45438#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
45439#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)
45444#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
45445
45446#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
45447#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
45452#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
45458#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
45459#define USB_GPTIMER1LD_GPTLD_SHIFT (0U)
45460#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
45466#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
45467#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
45468#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
45469
45470#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
45471#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
45476#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
45477
45478#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
45479#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)
45484#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
45485
45486#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
45487#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
45492#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
45498#define USB_SBUSCFG_AHBBRST_MASK (0x7U)
45499#define USB_SBUSCFG_AHBBRST_SHIFT (0U)
45510#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
45516#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
45517#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
45518#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
45524#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)
45525#define USB_HCIVERSION_HCIVERSION_SHIFT (0U)
45526#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
45532#define USB_HCSPARAMS_N_PORTS_MASK (0xFU)
45533#define USB_HCSPARAMS_N_PORTS_SHIFT (0U)
45534#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
45535
45536#define USB_HCSPARAMS_PPC_MASK (0x10U)
45537#define USB_HCSPARAMS_PPC_SHIFT (4U)
45538#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
45539
45540#define USB_HCSPARAMS_N_PCC_MASK (0xF00U)
45541#define USB_HCSPARAMS_N_PCC_SHIFT (8U)
45542#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
45543
45544#define USB_HCSPARAMS_N_CC_MASK (0xF000U)
45545#define USB_HCSPARAMS_N_CC_SHIFT (12U)
45550#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
45551
45552#define USB_HCSPARAMS_PI_MASK (0x10000U)
45553#define USB_HCSPARAMS_PI_SHIFT (16U)
45554#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
45555
45556#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U)
45557#define USB_HCSPARAMS_N_PTT_SHIFT (20U)
45558#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
45559
45560#define USB_HCSPARAMS_N_TT_MASK (0xF000000U)
45561#define USB_HCSPARAMS_N_TT_SHIFT (24U)
45562#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
45568#define USB_HCCPARAMS_ADC_MASK (0x1U)
45569#define USB_HCCPARAMS_ADC_SHIFT (0U)
45570#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
45571
45572#define USB_HCCPARAMS_PFL_MASK (0x2U)
45573#define USB_HCCPARAMS_PFL_SHIFT (1U)
45574#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
45575
45576#define USB_HCCPARAMS_ASP_MASK (0x4U)
45577#define USB_HCCPARAMS_ASP_SHIFT (2U)
45578#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
45579
45580#define USB_HCCPARAMS_IST_MASK (0xF0U)
45581#define USB_HCCPARAMS_IST_SHIFT (4U)
45582#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
45583
45584#define USB_HCCPARAMS_EECP_MASK (0xFF00U)
45585#define USB_HCCPARAMS_EECP_SHIFT (8U)
45586#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
45592#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
45593#define USB_DCIVERSION_DCIVERSION_SHIFT (0U)
45594#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
45600#define USB_DCCPARAMS_DEN_MASK (0x1FU)
45601#define USB_DCCPARAMS_DEN_SHIFT (0U)
45602#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
45603
45604#define USB_DCCPARAMS_DC_MASK (0x80U)
45605#define USB_DCCPARAMS_DC_SHIFT (7U)
45606#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
45607
45608#define USB_DCCPARAMS_HC_MASK (0x100U)
45609#define USB_DCCPARAMS_HC_SHIFT (8U)
45610#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
45616#define USB_USBCMD_RS_MASK (0x1U)
45617#define USB_USBCMD_RS_SHIFT (0U)
45618#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
45619
45620#define USB_USBCMD_RST_MASK (0x2U)
45621#define USB_USBCMD_RST_SHIFT (1U)
45622#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
45623
45624#define USB_USBCMD_FS_1_MASK (0xCU)
45625#define USB_USBCMD_FS_1_SHIFT (2U)
45626#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
45627
45628#define USB_USBCMD_PSE_MASK (0x10U)
45629#define USB_USBCMD_PSE_SHIFT (4U)
45634#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
45635
45636#define USB_USBCMD_ASE_MASK (0x20U)
45637#define USB_USBCMD_ASE_SHIFT (5U)
45642#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
45643
45644#define USB_USBCMD_IAA_MASK (0x40U)
45645#define USB_USBCMD_IAA_SHIFT (6U)
45646#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
45647
45648#define USB_USBCMD_ASP_MASK (0x300U)
45649#define USB_USBCMD_ASP_SHIFT (8U)
45650#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
45651
45652#define USB_USBCMD_ASPE_MASK (0x800U)
45653#define USB_USBCMD_ASPE_SHIFT (11U)
45654#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
45655
45656#define USB_USBCMD_SUTW_MASK (0x2000U)
45657#define USB_USBCMD_SUTW_SHIFT (13U)
45658#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
45659
45660#define USB_USBCMD_ATDTW_MASK (0x4000U)
45661#define USB_USBCMD_ATDTW_SHIFT (14U)
45662#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
45663
45664#define USB_USBCMD_FS_2_MASK (0x8000U)
45665#define USB_USBCMD_FS_2_SHIFT (15U)
45670#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
45671
45672#define USB_USBCMD_ITC_MASK (0xFF0000U)
45673#define USB_USBCMD_ITC_SHIFT (16U)
45684#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
45690#define USB_USBSTS_UI_MASK (0x1U)
45691#define USB_USBSTS_UI_SHIFT (0U)
45692#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
45693
45694#define USB_USBSTS_UEI_MASK (0x2U)
45695#define USB_USBSTS_UEI_SHIFT (1U)
45696#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
45697
45698#define USB_USBSTS_PCI_MASK (0x4U)
45699#define USB_USBSTS_PCI_SHIFT (2U)
45700#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
45701
45702#define USB_USBSTS_FRI_MASK (0x8U)
45703#define USB_USBSTS_FRI_SHIFT (3U)
45704#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
45705
45706#define USB_USBSTS_SEI_MASK (0x10U)
45707#define USB_USBSTS_SEI_SHIFT (4U)
45708#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
45709
45710#define USB_USBSTS_AAI_MASK (0x20U)
45711#define USB_USBSTS_AAI_SHIFT (5U)
45712#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
45713
45714#define USB_USBSTS_URI_MASK (0x40U)
45715#define USB_USBSTS_URI_SHIFT (6U)
45716#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
45717
45718#define USB_USBSTS_SRI_MASK (0x80U)
45719#define USB_USBSTS_SRI_SHIFT (7U)
45720#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
45721
45722#define USB_USBSTS_SLI_MASK (0x100U)
45723#define USB_USBSTS_SLI_SHIFT (8U)
45724#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
45725
45726#define USB_USBSTS_ULPII_MASK (0x400U)
45727#define USB_USBSTS_ULPII_SHIFT (10U)
45728#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
45729
45730#define USB_USBSTS_HCH_MASK (0x1000U)
45731#define USB_USBSTS_HCH_SHIFT (12U)
45732#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
45733
45734#define USB_USBSTS_RCL_MASK (0x2000U)
45735#define USB_USBSTS_RCL_SHIFT (13U)
45736#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
45737
45738#define USB_USBSTS_PS_MASK (0x4000U)
45739#define USB_USBSTS_PS_SHIFT (14U)
45740#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
45741
45742#define USB_USBSTS_AS_MASK (0x8000U)
45743#define USB_USBSTS_AS_SHIFT (15U)
45744#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
45745
45746#define USB_USBSTS_NAKI_MASK (0x10000U)
45747#define USB_USBSTS_NAKI_SHIFT (16U)
45748#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
45749
45750#define USB_USBSTS_TI0_MASK (0x1000000U)
45751#define USB_USBSTS_TI0_SHIFT (24U)
45752#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
45753
45754#define USB_USBSTS_TI1_MASK (0x2000000U)
45755#define USB_USBSTS_TI1_SHIFT (25U)
45756#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
45762#define USB_USBINTR_UE_MASK (0x1U)
45763#define USB_USBINTR_UE_SHIFT (0U)
45764#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
45765
45766#define USB_USBINTR_UEE_MASK (0x2U)
45767#define USB_USBINTR_UEE_SHIFT (1U)
45768#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
45769
45770#define USB_USBINTR_PCE_MASK (0x4U)
45771#define USB_USBINTR_PCE_SHIFT (2U)
45772#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
45773
45774#define USB_USBINTR_FRE_MASK (0x8U)
45775#define USB_USBINTR_FRE_SHIFT (3U)
45776#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
45777
45778#define USB_USBINTR_SEE_MASK (0x10U)
45779#define USB_USBINTR_SEE_SHIFT (4U)
45780#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
45781
45782#define USB_USBINTR_AAE_MASK (0x20U)
45783#define USB_USBINTR_AAE_SHIFT (5U)
45784#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
45785
45786#define USB_USBINTR_URE_MASK (0x40U)
45787#define USB_USBINTR_URE_SHIFT (6U)
45788#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
45789
45790#define USB_USBINTR_SRE_MASK (0x80U)
45791#define USB_USBINTR_SRE_SHIFT (7U)
45792#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
45793
45794#define USB_USBINTR_SLE_MASK (0x100U)
45795#define USB_USBINTR_SLE_SHIFT (8U)
45796#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
45797
45798#define USB_USBINTR_ULPIE_MASK (0x400U)
45799#define USB_USBINTR_ULPIE_SHIFT (10U)
45800#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
45801
45802#define USB_USBINTR_NAKE_MASK (0x10000U)
45803#define USB_USBINTR_NAKE_SHIFT (16U)
45804#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
45805
45806#define USB_USBINTR_UAIE_MASK (0x40000U)
45807#define USB_USBINTR_UAIE_SHIFT (18U)
45808#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
45809
45810#define USB_USBINTR_UPIE_MASK (0x80000U)
45811#define USB_USBINTR_UPIE_SHIFT (19U)
45812#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
45813
45814#define USB_USBINTR_TIE0_MASK (0x1000000U)
45815#define USB_USBINTR_TIE0_SHIFT (24U)
45816#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
45817
45818#define USB_USBINTR_TIE1_MASK (0x2000000U)
45819#define USB_USBINTR_TIE1_SHIFT (25U)
45820#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
45826#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU)
45827#define USB_FRINDEX_FRINDEX_SHIFT (0U)
45838#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
45844#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U)
45845#define USB_DEVICEADDR_USBADRA_SHIFT (24U)
45846#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
45847
45848#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U)
45849#define USB_DEVICEADDR_USBADR_SHIFT (25U)
45850#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
45856#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)
45857#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)
45858#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
45864#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
45865#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
45866#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
45872#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)
45873#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)
45874#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
45880#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU)
45881#define USB_BURSTSIZE_RXPBURST_SHIFT (0U)
45882#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
45883
45884#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)
45885#define USB_BURSTSIZE_TXPBURST_SHIFT (8U)
45886#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
45892#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)
45893#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)
45894#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
45895
45896#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
45897#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
45898#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
45899
45900#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
45901#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
45902#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
45908#define USB_ENDPTNAK_EPRN_MASK (0xFFU)
45909#define USB_ENDPTNAK_EPRN_SHIFT (0U)
45910#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
45911
45912#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U)
45913#define USB_ENDPTNAK_EPTN_SHIFT (16U)
45914#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
45920#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)
45921#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U)
45922#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
45923
45924#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)
45925#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U)
45926#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
45932#define USB_CONFIGFLAG_CF_MASK (0x1U)
45933#define USB_CONFIGFLAG_CF_SHIFT (0U)
45938#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
45944#define USB_PORTSC1_CCS_MASK (0x1U)
45945#define USB_PORTSC1_CCS_SHIFT (0U)
45946#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
45947
45948#define USB_PORTSC1_CSC_MASK (0x2U)
45949#define USB_PORTSC1_CSC_SHIFT (1U)
45950#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
45951
45952#define USB_PORTSC1_PE_MASK (0x4U)
45953#define USB_PORTSC1_PE_SHIFT (2U)
45954#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
45955
45956#define USB_PORTSC1_PEC_MASK (0x8U)
45957#define USB_PORTSC1_PEC_SHIFT (3U)
45958#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
45959
45960#define USB_PORTSC1_OCA_MASK (0x10U)
45961#define USB_PORTSC1_OCA_SHIFT (4U)
45966#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
45967
45968#define USB_PORTSC1_OCC_MASK (0x20U)
45969#define USB_PORTSC1_OCC_SHIFT (5U)
45970#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
45971
45972#define USB_PORTSC1_FPR_MASK (0x40U)
45973#define USB_PORTSC1_FPR_SHIFT (6U)
45974#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
45975
45976#define USB_PORTSC1_SUSP_MASK (0x80U)
45977#define USB_PORTSC1_SUSP_SHIFT (7U)
45978#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
45979
45980#define USB_PORTSC1_PR_MASK (0x100U)
45981#define USB_PORTSC1_PR_SHIFT (8U)
45982#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
45983
45984#define USB_PORTSC1_HSP_MASK (0x200U)
45985#define USB_PORTSC1_HSP_SHIFT (9U)
45986#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
45987
45988#define USB_PORTSC1_LS_MASK (0xC00U)
45989#define USB_PORTSC1_LS_SHIFT (10U)
45996#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
45997
45998#define USB_PORTSC1_PP_MASK (0x1000U)
45999#define USB_PORTSC1_PP_SHIFT (12U)
46000#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
46001
46002#define USB_PORTSC1_PO_MASK (0x2000U)
46003#define USB_PORTSC1_PO_SHIFT (13U)
46004#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
46005
46006#define USB_PORTSC1_PIC_MASK (0xC000U)
46007#define USB_PORTSC1_PIC_SHIFT (14U)
46014#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
46015
46016#define USB_PORTSC1_PTC_MASK (0xF0000U)
46017#define USB_PORTSC1_PTC_SHIFT (16U)
46029#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
46030
46031#define USB_PORTSC1_WKCN_MASK (0x100000U)
46032#define USB_PORTSC1_WKCN_SHIFT (20U)
46033#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
46034
46035#define USB_PORTSC1_WKDC_MASK (0x200000U)
46036#define USB_PORTSC1_WKDC_SHIFT (21U)
46037#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
46038
46039#define USB_PORTSC1_WKOC_MASK (0x400000U)
46040#define USB_PORTSC1_WKOC_SHIFT (22U)
46041#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
46042
46043#define USB_PORTSC1_PHCD_MASK (0x800000U)
46044#define USB_PORTSC1_PHCD_SHIFT (23U)
46049#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
46050
46051#define USB_PORTSC1_PFSC_MASK (0x1000000U)
46052#define USB_PORTSC1_PFSC_SHIFT (24U)
46057#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
46058
46059#define USB_PORTSC1_PTS_2_MASK (0x2000000U)
46060#define USB_PORTSC1_PTS_2_SHIFT (25U)
46061#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
46062
46063#define USB_PORTSC1_PSPD_MASK (0xC000000U)
46064#define USB_PORTSC1_PSPD_SHIFT (26U)
46071#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
46072
46073#define USB_PORTSC1_PTW_MASK (0x10000000U)
46074#define USB_PORTSC1_PTW_SHIFT (28U)
46079#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
46080
46081#define USB_PORTSC1_STS_MASK (0x20000000U)
46082#define USB_PORTSC1_STS_SHIFT (29U)
46083#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
46084
46085#define USB_PORTSC1_PTS_1_MASK (0xC0000000U)
46086#define USB_PORTSC1_PTS_1_SHIFT (30U)
46087#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
46093#define USB_OTGSC_VD_MASK (0x1U)
46094#define USB_OTGSC_VD_SHIFT (0U)
46095#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
46096
46097#define USB_OTGSC_VC_MASK (0x2U)
46098#define USB_OTGSC_VC_SHIFT (1U)
46099#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
46100
46101#define USB_OTGSC_OT_MASK (0x8U)
46102#define USB_OTGSC_OT_SHIFT (3U)
46103#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
46104
46105#define USB_OTGSC_DP_MASK (0x10U)
46106#define USB_OTGSC_DP_SHIFT (4U)
46107#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
46108
46109#define USB_OTGSC_IDPU_MASK (0x20U)
46110#define USB_OTGSC_IDPU_SHIFT (5U)
46111#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
46112
46113#define USB_OTGSC_ID_MASK (0x100U)
46114#define USB_OTGSC_ID_SHIFT (8U)
46115#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
46116
46117#define USB_OTGSC_AVV_MASK (0x200U)
46118#define USB_OTGSC_AVV_SHIFT (9U)
46119#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
46120
46121#define USB_OTGSC_ASV_MASK (0x400U)
46122#define USB_OTGSC_ASV_SHIFT (10U)
46123#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
46124
46125#define USB_OTGSC_BSV_MASK (0x800U)
46126#define USB_OTGSC_BSV_SHIFT (11U)
46127#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
46128
46129#define USB_OTGSC_BSE_MASK (0x1000U)
46130#define USB_OTGSC_BSE_SHIFT (12U)
46131#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
46132
46133#define USB_OTGSC_TOG_1MS_MASK (0x2000U)
46134#define USB_OTGSC_TOG_1MS_SHIFT (13U)
46135#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
46136
46137#define USB_OTGSC_DPS_MASK (0x4000U)
46138#define USB_OTGSC_DPS_SHIFT (14U)
46139#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
46140
46141#define USB_OTGSC_IDIS_MASK (0x10000U)
46142#define USB_OTGSC_IDIS_SHIFT (16U)
46143#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
46144
46145#define USB_OTGSC_AVVIS_MASK (0x20000U)
46146#define USB_OTGSC_AVVIS_SHIFT (17U)
46147#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
46148
46149#define USB_OTGSC_ASVIS_MASK (0x40000U)
46150#define USB_OTGSC_ASVIS_SHIFT (18U)
46151#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
46152
46153#define USB_OTGSC_BSVIS_MASK (0x80000U)
46154#define USB_OTGSC_BSVIS_SHIFT (19U)
46155#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
46156
46157#define USB_OTGSC_BSEIS_MASK (0x100000U)
46158#define USB_OTGSC_BSEIS_SHIFT (20U)
46159#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
46160
46161#define USB_OTGSC_STATUS_1MS_MASK (0x200000U)
46162#define USB_OTGSC_STATUS_1MS_SHIFT (21U)
46163#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
46164
46165#define USB_OTGSC_DPIS_MASK (0x400000U)
46166#define USB_OTGSC_DPIS_SHIFT (22U)
46167#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
46168
46169#define USB_OTGSC_IDIE_MASK (0x1000000U)
46170#define USB_OTGSC_IDIE_SHIFT (24U)
46171#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
46172
46173#define USB_OTGSC_AVVIE_MASK (0x2000000U)
46174#define USB_OTGSC_AVVIE_SHIFT (25U)
46175#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
46176
46177#define USB_OTGSC_ASVIE_MASK (0x4000000U)
46178#define USB_OTGSC_ASVIE_SHIFT (26U)
46179#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
46180
46181#define USB_OTGSC_BSVIE_MASK (0x8000000U)
46182#define USB_OTGSC_BSVIE_SHIFT (27U)
46183#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
46184
46185#define USB_OTGSC_BSEIE_MASK (0x10000000U)
46186#define USB_OTGSC_BSEIE_SHIFT (28U)
46187#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
46188
46189#define USB_OTGSC_EN_1MS_MASK (0x20000000U)
46190#define USB_OTGSC_EN_1MS_SHIFT (29U)
46191#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
46192
46193#define USB_OTGSC_DPIE_MASK (0x40000000U)
46194#define USB_OTGSC_DPIE_SHIFT (30U)
46195#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
46201#define USB_USBMODE_CM_MASK (0x3U)
46202#define USB_USBMODE_CM_SHIFT (0U)
46209#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
46210
46211#define USB_USBMODE_ES_MASK (0x4U)
46212#define USB_USBMODE_ES_SHIFT (2U)
46217#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
46218
46219#define USB_USBMODE_SLOM_MASK (0x8U)
46220#define USB_USBMODE_SLOM_SHIFT (3U)
46225#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
46226
46227#define USB_USBMODE_SDIS_MASK (0x10U)
46228#define USB_USBMODE_SDIS_SHIFT (4U)
46229#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
46235#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
46236#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
46237#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
46243#define USB_ENDPTPRIME_PERB_MASK (0xFFU)
46244#define USB_ENDPTPRIME_PERB_SHIFT (0U)
46245#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
46246
46247#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U)
46248#define USB_ENDPTPRIME_PETB_SHIFT (16U)
46249#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
46255#define USB_ENDPTFLUSH_FERB_MASK (0xFFU)
46256#define USB_ENDPTFLUSH_FERB_SHIFT (0U)
46257#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
46258
46259#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)
46260#define USB_ENDPTFLUSH_FETB_SHIFT (16U)
46261#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
46267#define USB_ENDPTSTAT_ERBR_MASK (0xFFU)
46268#define USB_ENDPTSTAT_ERBR_SHIFT (0U)
46269#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
46270
46271#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)
46272#define USB_ENDPTSTAT_ETBR_SHIFT (16U)
46273#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
46279#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)
46280#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)
46281#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
46282
46283#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)
46284#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)
46285#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
46291#define USB_ENDPTCTRL0_RXS_MASK (0x1U)
46292#define USB_ENDPTCTRL0_RXS_SHIFT (0U)
46293#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
46294
46295#define USB_ENDPTCTRL0_RXT_MASK (0xCU)
46296#define USB_ENDPTCTRL0_RXT_SHIFT (2U)
46297#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
46298
46299#define USB_ENDPTCTRL0_RXE_MASK (0x80U)
46300#define USB_ENDPTCTRL0_RXE_SHIFT (7U)
46301#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
46302
46303#define USB_ENDPTCTRL0_TXS_MASK (0x10000U)
46304#define USB_ENDPTCTRL0_TXS_SHIFT (16U)
46305#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
46306
46307#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U)
46308#define USB_ENDPTCTRL0_TXT_SHIFT (18U)
46309#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
46310
46311#define USB_ENDPTCTRL0_TXE_MASK (0x800000U)
46312#define USB_ENDPTCTRL0_TXE_SHIFT (23U)
46313#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
46319#define USB_ENDPTCTRL_RXS_MASK (0x1U)
46320#define USB_ENDPTCTRL_RXS_SHIFT (0U)
46321#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
46322
46323#define USB_ENDPTCTRL_RXD_MASK (0x2U)
46324#define USB_ENDPTCTRL_RXD_SHIFT (1U)
46325#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
46326
46327#define USB_ENDPTCTRL_RXT_MASK (0xCU)
46328#define USB_ENDPTCTRL_RXT_SHIFT (2U)
46329#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
46330
46331#define USB_ENDPTCTRL_RXI_MASK (0x20U)
46332#define USB_ENDPTCTRL_RXI_SHIFT (5U)
46333#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
46334
46335#define USB_ENDPTCTRL_RXR_MASK (0x40U)
46336#define USB_ENDPTCTRL_RXR_SHIFT (6U)
46337#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
46338
46339#define USB_ENDPTCTRL_RXE_MASK (0x80U)
46340#define USB_ENDPTCTRL_RXE_SHIFT (7U)
46341#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
46342
46343#define USB_ENDPTCTRL_TXS_MASK (0x10000U)
46344#define USB_ENDPTCTRL_TXS_SHIFT (16U)
46345#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
46346
46347#define USB_ENDPTCTRL_TXD_MASK (0x20000U)
46348#define USB_ENDPTCTRL_TXD_SHIFT (17U)
46349#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
46350
46351#define USB_ENDPTCTRL_TXT_MASK (0xC0000U)
46352#define USB_ENDPTCTRL_TXT_SHIFT (18U)
46353#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
46354
46355#define USB_ENDPTCTRL_TXI_MASK (0x200000U)
46356#define USB_ENDPTCTRL_TXI_SHIFT (21U)
46357#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
46358
46359#define USB_ENDPTCTRL_TXR_MASK (0x400000U)
46360#define USB_ENDPTCTRL_TXR_SHIFT (22U)
46361#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
46362
46363#define USB_ENDPTCTRL_TXE_MASK (0x800000U)
46364#define USB_ENDPTCTRL_TXE_SHIFT (23U)
46365#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
46368/* The count of USB_ENDPTCTRL */
46369#define USB_ENDPTCTRL_COUNT (7U)
46370
46371 /* end of group USB_Register_Masks */
46375
46376
46377/* USB - Peripheral instance base addresses */
46379#define USB1_BASE (0x402E0000u)
46381#define USB1 ((USB_Type *)USB1_BASE)
46383#define USB2_BASE (0x402E0200u)
46385#define USB2 ((USB_Type *)USB2_BASE)
46387#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE }
46389#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 }
46391#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
46392/* Backward compatibility */
46393#define GPTIMER0CTL GPTIMER0CTRL
46394#define GPTIMER1CTL GPTIMER1CTRL
46395#define USB_SBUSCFG SBUSCFG
46396#define EPLISTADDR ENDPTLISTADDR
46397#define EPSETUPSR ENDPTSETUPSTAT
46398#define EPPRIME ENDPTPRIME
46399#define EPFLUSH ENDPTFLUSH
46400#define EPSR ENDPTSTAT
46401#define EPCOMPLETE ENDPTCOMPLETE
46402#define EPCR ENDPTCTRL
46403#define EPCR0 ENDPTCTRL0
46404#define USBHS_ID_ID_MASK USB_ID_ID_MASK
46405#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT
46406#define USBHS_ID_ID(x) USB_ID_ID(x)
46407#define USBHS_ID_NID_MASK USB_ID_NID_MASK
46408#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT
46409#define USBHS_ID_NID(x) USB_ID_NID(x)
46410#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK
46411#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT
46412#define USBHS_ID_REVISION(x) USB_ID_REVISION(x)
46413#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK
46414#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT
46415#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)
46416#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK
46417#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT
46418#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)
46419#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK
46420#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT
46421#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)
46422#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK
46423#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT
46424#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x)
46425#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK
46426#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT
46427#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)
46428#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK
46429#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT
46430#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)
46431#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK
46432#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT
46433#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)
46434#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK
46435#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT
46436#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)
46437#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK
46438#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT
46439#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)
46440#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK
46441#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT
46442#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)
46443#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK
46444#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT
46445#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)
46446#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK
46447#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT
46448#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)
46449#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK
46450#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT
46451#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)
46452#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK
46453#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT
46454#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)
46455#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK
46456#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT
46457#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)
46458#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK
46459#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT
46460#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)
46461#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK
46462#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT
46463#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)
46464#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK
46465#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT
46466#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)
46467#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK
46468#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT
46469#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)
46470#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK
46471#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT
46472#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)
46473#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK
46474#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT
46475#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)
46476#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK
46477#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT
46478#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)
46479#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)
46480#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK
46481#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT
46482#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)
46483#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK
46484#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT
46485#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)
46486#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK
46487#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT
46488#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)
46489#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK
46490#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT
46491#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)
46492#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK
46493#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT
46494#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)
46495#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK
46496#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT
46497#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)
46498#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK
46499#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT
46500#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)
46501#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK
46502#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT
46503#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)
46504#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK
46505#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT
46506#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)
46507#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK
46508#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT
46509#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)
46510#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK
46511#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT
46512#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)
46513#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK
46514#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT
46515#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)
46516#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK
46517#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT
46518#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)
46519#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK
46520#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT
46521#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)
46522#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK
46523#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT
46524#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)
46525#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK
46526#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT
46527#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)
46528#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK
46529#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT
46530#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)
46531#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK
46532#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT
46533#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)
46534#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK
46535#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT
46536#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)
46537#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK
46538#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT
46539#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)
46540#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK
46541#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT
46542#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)
46543#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK
46544#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT
46545#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)
46546#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK
46547#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT
46548#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)
46549#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK
46550#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT
46551#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)
46552#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK
46553#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT
46554#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)
46555#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK
46556#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT
46557#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)
46558#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK
46559#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT
46560#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)
46561#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK
46562#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT
46563#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)
46564#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK
46565#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT
46566#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)
46567#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK
46568#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT
46569#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x)
46570#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK
46571#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT
46572#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)
46573#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK
46574#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT
46575#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)
46576#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK
46577#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT
46578#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)
46579#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK
46580#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT
46581#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)
46582#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK
46583#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT
46584#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)
46585#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK
46586#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT
46587#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x)
46588#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK
46589#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT
46590#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)
46591#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK
46592#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT
46593#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)
46594#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK
46595#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT
46596#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)
46597#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK
46598#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT
46599#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)
46600#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK
46601#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT
46602#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)
46603#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK
46604#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT
46605#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x)
46606#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK
46607#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT
46608#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x)
46609#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK
46610#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT
46611#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)
46612#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK
46613#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT
46614#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)
46615#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK
46616#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT
46617#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)
46618#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK
46619#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT
46620#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x)
46621#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK
46622#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT
46623#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)
46624#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK
46625#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT
46626#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)
46627#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK
46628#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT
46629#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)
46630#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK
46631#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT
46632#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)
46633#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK
46634#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT
46635#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)
46636#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK
46637#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT
46638#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x)
46639#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK
46640#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT
46641#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)
46642#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK
46643#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT
46644#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)
46645#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK
46646#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT
46647#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)
46648#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK
46649#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT
46650#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)
46651#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK
46652#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT
46653#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)
46654#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK
46655#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT
46656#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)
46657#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK
46658#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT
46659#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)
46660#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK
46661#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT
46662#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)
46663#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK
46664#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT
46665#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)
46666#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK
46667#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT
46668#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)
46669#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK
46670#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT
46671#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)
46672#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK
46673#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT
46674#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)
46675#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK
46676#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT
46677#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)
46678#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK
46679#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT
46680#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)
46681#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK
46682#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT
46683#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)
46684#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK
46685#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT
46686#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)
46687#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK
46688#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT
46689#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)
46690#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK
46691#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
46692#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)
46693#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK
46694#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
46695#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)
46696#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK
46697#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT
46698#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)
46699#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK
46700#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT
46701#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)
46702#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK
46703#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT
46704#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)
46705#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK
46706#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT
46707#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)
46708#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK
46709#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT
46710#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)
46711#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK
46712#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT
46713#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)
46714#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK
46715#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT
46716#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)
46717#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK
46718#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT
46719#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)
46720#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK
46721#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT
46722#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)
46723#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK
46724#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT
46725#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)
46726#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK
46727#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT
46728#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)
46729#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK
46730#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT
46731#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)
46732#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK
46733#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT
46734#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)
46735#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK
46736#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT
46737#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)
46738#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK
46739#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT
46740#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)
46741#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK
46742#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT
46743#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)
46744#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK
46745#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT
46746#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)
46747#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK
46748#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT
46749#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)
46750#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK
46751#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT
46752#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)
46753#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK
46754#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT
46755#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)
46756#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK
46757#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT
46758#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)
46759#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK
46760#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT
46761#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)
46762#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK
46763#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT
46764#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)
46765#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK
46766#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT
46767#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)
46768#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK
46769#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT
46770#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)
46771#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK
46772#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT
46773#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)
46774#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK
46775#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT
46776#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)
46777#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK
46778#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT
46779#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)
46780#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK
46781#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT
46782#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)
46783#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK
46784#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT
46785#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)
46786#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK
46787#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT
46788#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x)
46789#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK
46790#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT
46791#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)
46792#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK
46793#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT
46794#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x)
46795#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK
46796#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT
46797#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x)
46798#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK
46799#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT
46800#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)
46801#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK
46802#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT
46803#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x)
46804#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK
46805#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT
46806#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)
46807#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK
46808#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT
46809#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)
46810#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK
46811#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT
46812#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)
46813#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK
46814#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT
46815#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)
46816#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK
46817#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT
46818#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)
46819#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK
46820#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT
46821#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)
46822#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK
46823#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT
46824#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)
46825#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK
46826#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT
46827#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)
46828#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK
46829#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT
46830#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)
46831#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK
46832#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT
46833#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)
46834#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK
46835#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT
46836#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)
46837#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK
46838#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT
46839#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)
46840#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK
46841#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT
46842#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)
46843#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK
46844#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT
46845#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)
46846#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK
46847#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT
46848#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)
46849#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK
46850#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT
46851#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)
46852#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK
46853#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT
46854#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)
46855#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK
46856#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT
46857#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)
46858#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK
46859#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT
46860#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)
46861#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK
46862#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT
46863#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)
46864#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK
46865#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT
46866#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x)
46867#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK
46868#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT
46869#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x)
46870#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK
46871#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT
46872#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)
46873#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK
46874#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT
46875#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)
46876#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
46877#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
46878#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
46879#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK
46880#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT
46881#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)
46882#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK
46883#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT
46884#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)
46885#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK
46886#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT
46887#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)
46888#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK
46889#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT
46890#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)
46891#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK
46892#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT
46893#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)
46894#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK
46895#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT
46896#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)
46897#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK
46898#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT
46899#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)
46900#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK
46901#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT
46902#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)
46903#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK
46904#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT
46905#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)
46906#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK
46907#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT
46908#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)
46909#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK
46910#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT
46911#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)
46912#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK
46913#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT
46914#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)
46915#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK
46916#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT
46917#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)
46918#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK
46919#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT
46920#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)
46921#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK
46922#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT
46923#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)
46924#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK
46925#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT
46926#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)
46927#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK
46928#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT
46929#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)
46930#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK
46931#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT
46932#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)
46933#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK
46934#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT
46935#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)
46936#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK
46937#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT
46938#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)
46939#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK
46940#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT
46941#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)
46942#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK
46943#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT
46944#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)
46945#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK
46946#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT
46947#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)
46948#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK
46949#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT
46950#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)
46951#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK
46952#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT
46953#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)
46954#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK
46955#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT
46956#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)
46957#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT
46958#define USBHS_Type USB_Type
46959#define USBHS_BASE_ADDRS USB_BASE_ADDRS
46960#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn }
46961#define USBHS_IRQHandler USB_OTG1_IRQHandler
46962#define USBHS_STACK_BASE_ADDRS { USB1_BASE, USB2_BASE }
46963
46964 /* end of group USB_Peripheral_Access_Layer */
46968
46969
46970/* ----------------------------------------------------------------------------
46971 -- USBNC Peripheral Access Layer
46972 ---------------------------------------------------------------------------- */
46973
46980typedef struct {
46981 uint8_t RESERVED_0[2048];
46982 __IO uint32_t USB_OTGn_CTRL;
46983 uint8_t RESERVED_1[20];
46984 __IO uint32_t USB_OTGn_PHY_CTRL_0;
46985} USBNC_Type;
46986
46987/* ----------------------------------------------------------------------------
46988 -- USBNC Register Masks
46989 ---------------------------------------------------------------------------- */
46990
46999#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)
47000#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)
47005#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)
47006
47007#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)
47008#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)
47013#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)
47014
47015#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)
47016#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)
47021#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)
47022
47023#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)
47024#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)
47029#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)
47030
47031#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)
47032#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)
47037#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)
47038
47039#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)
47040#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)
47045#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)
47046
47047#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)
47048#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)
47053#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)
47054
47055#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)
47056#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)
47061#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)
47062
47063#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)
47064#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)
47069#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)
47070
47071#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)
47072#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)
47077#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)
47083#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)
47084#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)
47089#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) /* end of group USBNC_Register_Masks */
47096
47097
47098/* USBNC - Peripheral instance base addresses */
47100#define USBNC1_BASE (0x402E0000u)
47102#define USBNC1 ((USBNC_Type *)USBNC1_BASE)
47104#define USBNC2_BASE (0x402E0004u)
47106#define USBNC2 ((USBNC_Type *)USBNC2_BASE)
47108#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE }
47110#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 }
47111/* Backward compatibility */
47112#define USBNC_STACK_BASE_ADDRS { USBNC1_BASE, USBNC2_BASE }
47113 /* end of group USBNC_Peripheral_Access_Layer */
47117
47118
47119/* ----------------------------------------------------------------------------
47120 -- USBPHY Peripheral Access Layer
47121 ---------------------------------------------------------------------------- */
47122
47129typedef struct {
47130 __IO uint32_t PWD;
47131 __IO uint32_t PWD_SET;
47132 __IO uint32_t PWD_CLR;
47133 __IO uint32_t PWD_TOG;
47134 __IO uint32_t TX;
47135 __IO uint32_t TX_SET;
47136 __IO uint32_t TX_CLR;
47137 __IO uint32_t TX_TOG;
47138 __IO uint32_t RX;
47139 __IO uint32_t RX_SET;
47140 __IO uint32_t RX_CLR;
47141 __IO uint32_t RX_TOG;
47142 __IO uint32_t CTRL;
47143 __IO uint32_t CTRL_SET;
47144 __IO uint32_t CTRL_CLR;
47145 __IO uint32_t CTRL_TOG;
47146 __IO uint32_t STATUS;
47147 uint8_t RESERVED_0[12];
47148 __IO uint32_t DEBUGr;
47149 __IO uint32_t DEBUG_SET;
47150 __IO uint32_t DEBUG_CLR;
47151 __IO uint32_t DEBUG_TOG;
47152 __I uint32_t DEBUG0_STATUS;
47153 uint8_t RESERVED_1[12];
47154 __IO uint32_t DEBUG1;
47155 __IO uint32_t DEBUG1_SET;
47156 __IO uint32_t DEBUG1_CLR;
47157 __IO uint32_t DEBUG1_TOG;
47158 __I uint32_t VERSION;
47159} USBPHY_Type;
47160
47161/* ----------------------------------------------------------------------------
47162 -- USBPHY Register Masks
47163 ---------------------------------------------------------------------------- */
47164
47173#define USBPHY_PWD_RSVD0_MASK (0x3FFU)
47174#define USBPHY_PWD_RSVD0_SHIFT (0U)
47175#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)
47176
47177#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
47178#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
47179#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
47180
47181#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
47182#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
47183#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
47184
47185#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
47186#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
47187#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
47188
47189#define USBPHY_PWD_RSVD1_MASK (0x1E000U)
47190#define USBPHY_PWD_RSVD1_SHIFT (13U)
47191#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)
47192
47193#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
47194#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
47195#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
47196
47197#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
47198#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
47199#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
47200
47201#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
47202#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
47203#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
47204
47205#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
47206#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
47207#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
47208
47209#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U)
47210#define USBPHY_PWD_RSVD2_SHIFT (21U)
47211#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)
47217#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)
47218#define USBPHY_PWD_SET_RSVD0_SHIFT (0U)
47219#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)
47220
47221#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
47222#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
47223#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
47224
47225#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
47226#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
47227#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
47228
47229#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
47230#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
47231#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
47232
47233#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U)
47234#define USBPHY_PWD_SET_RSVD1_SHIFT (13U)
47235#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)
47236
47237#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
47238#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
47239#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
47240
47241#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
47242#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
47243#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
47244
47245#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
47246#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
47247#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
47248
47249#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
47250#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
47251#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
47252
47253#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)
47254#define USBPHY_PWD_SET_RSVD2_SHIFT (21U)
47255#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)
47261#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)
47262#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U)
47263#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)
47264
47265#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
47266#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
47267#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
47268
47269#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
47270#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
47271#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
47272
47273#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
47274#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
47275#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
47276
47277#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)
47278#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U)
47279#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)
47280
47281#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
47282#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
47283#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
47284
47285#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
47286#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
47287#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
47288
47289#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
47290#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
47291#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
47292
47293#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
47294#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
47295#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
47296
47297#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)
47298#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U)
47299#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)
47305#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)
47306#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U)
47307#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)
47308
47309#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
47310#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
47311#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
47312
47313#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
47314#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
47315#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
47316
47317#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
47318#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
47319#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
47320
47321#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)
47322#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U)
47323#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)
47324
47325#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
47326#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
47327#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
47328
47329#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
47330#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
47331#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
47332
47333#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
47334#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
47335#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
47336
47337#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
47338#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
47339#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
47340
47341#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)
47342#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U)
47343#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)
47349#define USBPHY_TX_D_CAL_MASK (0xFU)
47350#define USBPHY_TX_D_CAL_SHIFT (0U)
47351#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
47352
47353#define USBPHY_TX_RSVD0_MASK (0xF0U)
47354#define USBPHY_TX_RSVD0_SHIFT (4U)
47355#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)
47356
47357#define USBPHY_TX_TXCAL45DN_MASK (0xF00U)
47358#define USBPHY_TX_TXCAL45DN_SHIFT (8U)
47359#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
47360
47361#define USBPHY_TX_RSVD1_MASK (0xF000U)
47362#define USBPHY_TX_RSVD1_SHIFT (12U)
47363#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)
47364
47365#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
47366#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
47367#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
47368
47369#define USBPHY_TX_RSVD2_MASK (0x3F00000U)
47370#define USBPHY_TX_RSVD2_SHIFT (20U)
47371#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)
47372
47373#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
47374#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
47375#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
47376
47377#define USBPHY_TX_RSVD5_MASK (0xE0000000U)
47378#define USBPHY_TX_RSVD5_SHIFT (29U)
47379#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)
47385#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
47386#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
47387#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
47388
47389#define USBPHY_TX_SET_RSVD0_MASK (0xF0U)
47390#define USBPHY_TX_SET_RSVD0_SHIFT (4U)
47391#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)
47392
47393#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)
47394#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)
47395#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
47396
47397#define USBPHY_TX_SET_RSVD1_MASK (0xF000U)
47398#define USBPHY_TX_SET_RSVD1_SHIFT (12U)
47399#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)
47400
47401#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
47402#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
47403#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
47404
47405#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)
47406#define USBPHY_TX_SET_RSVD2_SHIFT (20U)
47407#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)
47408
47409#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
47410#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
47411#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
47412
47413#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U)
47414#define USBPHY_TX_SET_RSVD5_SHIFT (29U)
47415#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)
47421#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
47422#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
47423#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
47424
47425#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U)
47426#define USBPHY_TX_CLR_RSVD0_SHIFT (4U)
47427#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)
47428
47429#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)
47430#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)
47431#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
47432
47433#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U)
47434#define USBPHY_TX_CLR_RSVD1_SHIFT (12U)
47435#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)
47436
47437#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
47438#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
47439#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
47440
47441#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)
47442#define USBPHY_TX_CLR_RSVD2_SHIFT (20U)
47443#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)
47444
47445#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
47446#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
47447#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
47448
47449#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)
47450#define USBPHY_TX_CLR_RSVD5_SHIFT (29U)
47451#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)
47457#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
47458#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
47459#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
47460
47461#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U)
47462#define USBPHY_TX_TOG_RSVD0_SHIFT (4U)
47463#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)
47464
47465#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)
47466#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)
47467#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
47468
47469#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U)
47470#define USBPHY_TX_TOG_RSVD1_SHIFT (12U)
47471#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)
47472
47473#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
47474#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
47475#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
47476
47477#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)
47478#define USBPHY_TX_TOG_RSVD2_SHIFT (20U)
47479#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)
47480
47481#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
47482#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
47483#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
47484
47485#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)
47486#define USBPHY_TX_TOG_RSVD5_SHIFT (29U)
47487#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)
47493#define USBPHY_RX_ENVADJ_MASK (0x7U)
47494#define USBPHY_RX_ENVADJ_SHIFT (0U)
47495#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
47496
47497#define USBPHY_RX_RSVD0_MASK (0x8U)
47498#define USBPHY_RX_RSVD0_SHIFT (3U)
47499#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)
47500
47501#define USBPHY_RX_DISCONADJ_MASK (0x70U)
47502#define USBPHY_RX_DISCONADJ_SHIFT (4U)
47503#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
47504
47505#define USBPHY_RX_RSVD1_MASK (0x3FFF80U)
47506#define USBPHY_RX_RSVD1_SHIFT (7U)
47507#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)
47508
47509#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
47510#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
47511#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
47512
47513#define USBPHY_RX_RSVD2_MASK (0xFF800000U)
47514#define USBPHY_RX_RSVD2_SHIFT (23U)
47515#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)
47521#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
47522#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
47523#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
47524
47525#define USBPHY_RX_SET_RSVD0_MASK (0x8U)
47526#define USBPHY_RX_SET_RSVD0_SHIFT (3U)
47527#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)
47528
47529#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
47530#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
47531#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
47532
47533#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)
47534#define USBPHY_RX_SET_RSVD1_SHIFT (7U)
47535#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)
47536
47537#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
47538#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
47539#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
47540
47541#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)
47542#define USBPHY_RX_SET_RSVD2_SHIFT (23U)
47543#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)
47549#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
47550#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
47551#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
47552
47553#define USBPHY_RX_CLR_RSVD0_MASK (0x8U)
47554#define USBPHY_RX_CLR_RSVD0_SHIFT (3U)
47555#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)
47556
47557#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
47558#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
47559#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
47560
47561#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)
47562#define USBPHY_RX_CLR_RSVD1_SHIFT (7U)
47563#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)
47564
47565#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
47566#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
47567#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
47568
47569#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)
47570#define USBPHY_RX_CLR_RSVD2_SHIFT (23U)
47571#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)
47577#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
47578#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
47579#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
47580
47581#define USBPHY_RX_TOG_RSVD0_MASK (0x8U)
47582#define USBPHY_RX_TOG_RSVD0_SHIFT (3U)
47583#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)
47584
47585#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
47586#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
47587#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
47588
47589#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)
47590#define USBPHY_RX_TOG_RSVD1_SHIFT (7U)
47591#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)
47592
47593#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
47594#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
47595#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
47596
47597#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)
47598#define USBPHY_RX_TOG_RSVD2_SHIFT (23U)
47599#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)
47605#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)
47606#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)
47607#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
47608
47609#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
47610#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
47611#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
47612
47613#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
47614#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
47615#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
47616
47617#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
47618#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
47619#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
47620
47621#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)
47622#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)
47623#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
47624
47625#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
47626#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
47627#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
47628
47629#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)
47630#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)
47631#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
47632
47633#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)
47634#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)
47635#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
47636
47637#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
47638#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
47639#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
47640
47641#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
47642#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
47643#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
47644
47645#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
47646#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
47647#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
47648
47649#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)
47650#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)
47651#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
47652
47653#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
47654#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
47655#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
47656
47657#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)
47658#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)
47659#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)
47660
47661#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
47662#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
47663#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
47664
47665#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
47666#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
47667#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
47668
47669#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
47670#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
47671#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
47672
47673#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
47674#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
47675#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
47676
47677#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)
47678#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)
47679#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)
47680
47681#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
47682#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
47683#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
47684
47685#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
47686#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
47687#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
47688
47689#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
47690#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
47691#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
47692
47693#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)
47694#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)
47695#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
47696
47697#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
47698#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
47699#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
47700
47701#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
47702#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
47703#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
47704
47705#define USBPHY_CTRL_RSVD1_MASK (0x6000000U)
47706#define USBPHY_CTRL_RSVD1_SHIFT (25U)
47707#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)
47708
47709#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
47710#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
47711#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
47712
47713#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
47714#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
47715#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
47716
47717#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
47718#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
47719#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
47720
47721#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
47722#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
47723#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
47724
47725#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
47726#define USBPHY_CTRL_SFTRST_SHIFT (31U)
47727#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
47733#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)
47734#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)
47735#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
47736
47737#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
47738#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
47739#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
47740
47741#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
47742#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
47743#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
47744
47745#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
47746#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
47747#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
47748
47749#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)
47750#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)
47751#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
47752
47753#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
47754#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
47755#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
47756
47757#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)
47758#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)
47759#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
47760
47761#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)
47762#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)
47763#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
47764
47765#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
47766#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
47767#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
47768
47769#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
47770#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
47771#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
47772
47773#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
47774#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
47775#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
47776
47777#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)
47778#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)
47779#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
47780
47781#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
47782#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
47783#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
47784
47785#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)
47786#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)
47787#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)
47788
47789#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
47790#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
47791#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
47792
47793#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
47794#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
47795#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
47796
47797#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
47798#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
47799#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
47800
47801#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
47802#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
47803#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
47804
47805#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)
47806#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)
47807#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)
47808
47809#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
47810#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
47811#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
47812
47813#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
47814#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
47815#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
47816
47817#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
47818#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
47819#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
47820
47821#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)
47822#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)
47823#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
47824
47825#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
47826#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
47827#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
47828
47829#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
47830#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
47831#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
47832
47833#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)
47834#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U)
47835#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)
47836
47837#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
47838#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
47839#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
47840
47841#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
47842#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
47843#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
47844
47845#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
47846#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
47847#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
47848
47849#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
47850#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
47851#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
47852
47853#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
47854#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
47855#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
47861#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)
47862#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)
47863#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
47864
47865#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
47866#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
47867#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
47868
47869#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
47870#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
47871#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
47872
47873#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
47874#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
47875#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
47876
47877#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)
47878#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)
47879#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
47880
47881#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
47882#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
47883#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
47884
47885#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)
47886#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)
47887#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
47888
47889#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)
47890#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)
47891#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
47892
47893#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
47894#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
47895#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
47896
47897#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
47898#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
47899#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
47900
47901#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
47902#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
47903#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
47904
47905#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)
47906#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)
47907#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
47908
47909#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
47910#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
47911#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
47912
47913#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)
47914#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)
47915#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)
47916
47917#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
47918#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
47919#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
47920
47921#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
47922#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
47923#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
47924
47925#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
47926#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
47927#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
47928
47929#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
47930#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
47931#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
47932
47933#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)
47934#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)
47935#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)
47936
47937#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
47938#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
47939#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
47940
47941#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
47942#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
47943#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
47944
47945#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
47946#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
47947#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
47948
47949#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)
47950#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)
47951#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
47952
47953#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
47954#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
47955#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
47956
47957#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
47958#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
47959#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
47960
47961#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)
47962#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U)
47963#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)
47964
47965#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
47966#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
47967#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
47968
47969#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
47970#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
47971#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
47972
47973#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
47974#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
47975#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
47976
47977#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
47978#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
47979#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
47980
47981#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
47982#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
47983#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
47989#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)
47990#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)
47991#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
47992
47993#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
47994#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
47995#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
47996
47997#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
47998#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
47999#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
48000
48001#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
48002#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
48003#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
48004
48005#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)
48006#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)
48007#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
48008
48009#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
48010#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
48011#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
48012
48013#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)
48014#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)
48015#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
48016
48017#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)
48018#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)
48019#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
48020
48021#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
48022#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
48023#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
48024
48025#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
48026#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
48027#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
48028
48029#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
48030#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
48031#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
48032
48033#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)
48034#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)
48035#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
48036
48037#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
48038#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
48039#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
48040
48041#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)
48042#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)
48043#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)
48044
48045#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
48046#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
48047#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
48048
48049#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
48050#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
48051#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
48052
48053#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
48054#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
48055#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
48056
48057#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
48058#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
48059#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
48060
48061#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)
48062#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)
48063#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)
48064
48065#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
48066#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
48067#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
48068
48069#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
48070#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
48071#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
48072
48073#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
48074#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
48075#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
48076
48077#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)
48078#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)
48079#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
48080
48081#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
48082#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
48083#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
48084
48085#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
48086#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
48087#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
48088
48089#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)
48090#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U)
48091#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)
48092
48093#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
48094#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
48095#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
48096
48097#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
48098#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
48099#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
48100
48101#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
48102#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
48103#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
48104
48105#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
48106#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
48107#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
48108
48109#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
48110#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
48111#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
48117#define USBPHY_STATUS_RSVD0_MASK (0x7U)
48118#define USBPHY_STATUS_RSVD0_SHIFT (0U)
48119#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)
48120
48121#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
48122#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
48123#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
48124
48125#define USBPHY_STATUS_RSVD1_MASK (0x30U)
48126#define USBPHY_STATUS_RSVD1_SHIFT (4U)
48127#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)
48128
48129#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
48130#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
48131#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
48132
48133#define USBPHY_STATUS_RSVD2_MASK (0x80U)
48134#define USBPHY_STATUS_RSVD2_SHIFT (7U)
48135#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)
48136
48137#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
48138#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
48139#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
48140
48141#define USBPHY_STATUS_RSVD3_MASK (0x200U)
48142#define USBPHY_STATUS_RSVD3_SHIFT (9U)
48143#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)
48144
48145#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
48146#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
48147#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
48148
48149#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)
48150#define USBPHY_STATUS_RSVD4_SHIFT (11U)
48151#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)
48157#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
48158#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
48159#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
48160
48161#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
48162#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
48163#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
48164
48165#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
48166#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
48167#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
48168
48169#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
48170#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
48171#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
48172
48173#define USBPHY_DEBUG_RSVD0_MASK (0xC0U)
48174#define USBPHY_DEBUG_RSVD0_SHIFT (6U)
48175#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
48176
48177#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
48178#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
48179#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
48180
48181#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
48182#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
48183#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
48184
48185#define USBPHY_DEBUG_RSVD1_MASK (0xE000U)
48186#define USBPHY_DEBUG_RSVD1_SHIFT (13U)
48187#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)
48188
48189#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
48190#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
48191#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
48192
48193#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U)
48194#define USBPHY_DEBUG_RSVD2_SHIFT (21U)
48195#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)
48196
48197#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
48198#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
48199#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
48200
48201#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
48202#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
48203#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
48204
48205#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
48206#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
48207#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
48208
48209#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
48210#define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
48211#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
48212
48213#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U)
48214#define USBPHY_DEBUG_RSVD3_SHIFT (31U)
48215#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)
48221#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
48222#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
48223#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
48224
48225#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
48226#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
48227#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
48228
48229#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
48230#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
48231#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
48232
48233#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
48234#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
48235#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
48236
48237#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)
48238#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)
48239#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)
48240
48241#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
48242#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
48243#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
48244
48245#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
48246#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
48247#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
48248
48249#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)
48250#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U)
48251#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)
48252
48253#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
48254#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
48255#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
48256
48257#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)
48258#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U)
48259#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)
48260
48261#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
48262#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
48263#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
48264
48265#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
48266#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
48267#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
48268
48269#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
48270#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
48271#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
48272
48273#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
48274#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
48275#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
48276
48277#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)
48278#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U)
48279#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)
48285#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
48286#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
48287#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
48288
48289#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
48290#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
48291#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
48292
48293#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
48294#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
48295#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
48296
48297#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
48298#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
48299#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
48300
48301#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)
48302#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)
48303#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)
48304
48305#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
48306#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
48307#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
48308
48309#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
48310#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
48311#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
48312
48313#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)
48314#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)
48315#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)
48316
48317#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
48318#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
48319#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
48320
48321#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)
48322#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)
48323#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)
48324
48325#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
48326#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
48327#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
48328
48329#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
48330#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
48331#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
48332
48333#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
48334#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
48335#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
48336
48337#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
48338#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
48339#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
48340
48341#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)
48342#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)
48343#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)
48349#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
48350#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
48351#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
48352
48353#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
48354#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
48355#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
48356
48357#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
48358#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
48359#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
48360
48361#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
48362#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
48363#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
48364
48365#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)
48366#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)
48367#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)
48368
48369#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
48370#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
48371#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
48372
48373#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
48374#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
48375#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
48376
48377#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)
48378#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)
48379#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)
48380
48381#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
48382#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
48383#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
48384
48385#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)
48386#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)
48387#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)
48388
48389#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
48390#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
48391#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
48392
48393#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
48394#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
48395#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
48396
48397#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
48398#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
48399#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
48400
48401#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
48402#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
48403#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
48404
48405#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)
48406#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)
48407#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)
48413#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
48414#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
48415#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
48416
48417#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
48418#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
48419#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
48420
48421#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
48422#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
48423#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
48429#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)
48430#define USBPHY_DEBUG1_RSVD0_SHIFT (0U)
48431#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)
48432
48433#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
48434#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
48435#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
48436
48437#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)
48438#define USBPHY_DEBUG1_RSVD1_SHIFT (15U)
48439#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)
48445#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)
48446#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)
48447#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)
48448
48449#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
48450#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
48451#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
48452
48453#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)
48454#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)
48455#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)
48461#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)
48462#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)
48463#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)
48464
48465#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
48466#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
48467#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
48468
48469#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)
48470#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)
48471#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)
48477#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)
48478#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)
48479#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)
48480
48481#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
48482#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
48483#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
48484
48485#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)
48486#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)
48487#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)
48493#define USBPHY_VERSION_STEP_MASK (0xFFFFU)
48494#define USBPHY_VERSION_STEP_SHIFT (0U)
48495#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
48496
48497#define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
48498#define USBPHY_VERSION_MINOR_SHIFT (16U)
48499#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
48500
48501#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
48502#define USBPHY_VERSION_MAJOR_SHIFT (24U)
48503#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) /* end of group USBPHY_Register_Masks */
48510
48511
48512/* USBPHY - Peripheral instance base addresses */
48514#define USBPHY1_BASE (0x400D9000u)
48516#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE)
48518#define USBPHY2_BASE (0x400DA000u)
48520#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE)
48522#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE }
48524#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
48526#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }
48527/* Backward compatibility */
48528#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
48529#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
48530#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)
48531#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK
48532#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT
48533#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)
48534#define USBPHY_STACK_BASE_ADDRS { USBPHY1_BASE, USBPHY2_BASE }
48535
48536 /* end of group USBPHY_Peripheral_Access_Layer */
48540
48541
48542/* ----------------------------------------------------------------------------
48543 -- USB_ANALOG Peripheral Access Layer
48544 ---------------------------------------------------------------------------- */
48545
48552typedef struct {
48553 uint8_t RESERVED_0[416];
48554 struct { /* offset: 0x1A0, array step: 0x60 */
48555 __IO uint32_t VBUS_DETECT;
48556 __IO uint32_t VBUS_DETECT_SET;
48557 __IO uint32_t VBUS_DETECT_CLR;
48558 __IO uint32_t VBUS_DETECT_TOG;
48559 __IO uint32_t CHRG_DETECT;
48560 __IO uint32_t CHRG_DETECT_SET;
48561 __IO uint32_t CHRG_DETECT_CLR;
48562 __IO uint32_t CHRG_DETECT_TOG;
48563 __I uint32_t VBUS_DETECT_STAT;
48564 uint8_t RESERVED_0[12];
48565 __I uint32_t CHRG_DETECT_STAT;
48566 uint8_t RESERVED_1[12];
48567 __IO uint32_t LOOPBACK;
48568 __IO uint32_t LOOPBACK_SET;
48569 __IO uint32_t LOOPBACK_CLR;
48570 __IO uint32_t LOOPBACK_TOG;
48571 __IO uint32_t MISC;
48572 __IO uint32_t MISC_SET;
48573 __IO uint32_t MISC_CLR;
48574 __IO uint32_t MISC_TOG;
48575 } INSTANCE[2];
48576 __I uint32_t DIGPROG;
48577} USB_ANALOG_Type;
48578
48579/* ----------------------------------------------------------------------------
48580 -- USB_ANALOG Register Masks
48581 ---------------------------------------------------------------------------- */
48582
48591#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
48592#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
48603#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)
48604
48605#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
48606#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
48607#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)
48608
48609#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
48610#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
48611#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)
48612
48613#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)
48614#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)
48615#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)
48618/* The count of USB_ANALOG_VBUS_DETECT */
48619#define USB_ANALOG_VBUS_DETECT_COUNT (2U)
48620
48624#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
48625#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
48636#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
48637
48638#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
48639#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
48640#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)
48641
48642#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
48643#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
48644#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
48645
48646#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)
48647#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)
48648#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)
48651/* The count of USB_ANALOG_VBUS_DETECT_SET */
48652#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U)
48653
48657#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
48658#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
48669#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
48670
48671#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
48672#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
48673#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)
48674
48675#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
48676#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
48677#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
48678
48679#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)
48680#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)
48681#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)
48684/* The count of USB_ANALOG_VBUS_DETECT_CLR */
48685#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U)
48686
48690#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
48691#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
48702#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
48703
48704#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
48705#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
48706#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)
48707
48708#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
48709#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
48710#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
48711
48712#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)
48713#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)
48714#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)
48717/* The count of USB_ANALOG_VBUS_DETECT_TOG */
48718#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U)
48719
48723#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)
48724#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)
48729#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)
48730
48731#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)
48732#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)
48737#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)
48738
48739#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)
48740#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)
48745#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)
48748/* The count of USB_ANALOG_CHRG_DETECT */
48749#define USB_ANALOG_CHRG_DETECT_COUNT (2U)
48750
48754#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)
48755#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)
48760#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)
48761
48762#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)
48763#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)
48768#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)
48769
48770#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)
48771#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)
48776#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)
48779/* The count of USB_ANALOG_CHRG_DETECT_SET */
48780#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U)
48781
48785#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)
48786#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)
48791#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)
48792
48793#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)
48794#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)
48799#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)
48800
48801#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)
48802#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)
48807#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)
48810/* The count of USB_ANALOG_CHRG_DETECT_CLR */
48811#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U)
48812
48816#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)
48817#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)
48822#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)
48823
48824#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)
48825#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)
48830#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)
48831
48832#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)
48833#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)
48838#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)
48841/* The count of USB_ANALOG_CHRG_DETECT_TOG */
48842#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U)
48843
48847#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)
48848#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)
48849#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)
48850
48851#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)
48852#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)
48853#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)
48854
48855#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)
48856#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)
48857#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)
48858
48859#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)
48860#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)
48861#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)
48864/* The count of USB_ANALOG_VBUS_DETECT_STAT */
48865#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U)
48866
48870#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)
48871#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)
48876#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)
48877
48878#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)
48879#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)
48884#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)
48885
48886#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)
48887#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)
48888#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)
48889
48890#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)
48891#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)
48892#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)
48895/* The count of USB_ANALOG_CHRG_DETECT_STAT */
48896#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U)
48897
48901#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
48902#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
48903#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK)
48906/* The count of USB_ANALOG_LOOPBACK */
48907#define USB_ANALOG_LOOPBACK_COUNT (2U)
48908
48912#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
48913#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
48914#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK)
48917/* The count of USB_ANALOG_LOOPBACK_SET */
48918#define USB_ANALOG_LOOPBACK_SET_COUNT (2U)
48919
48923#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
48924#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
48925#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
48928/* The count of USB_ANALOG_LOOPBACK_CLR */
48929#define USB_ANALOG_LOOPBACK_CLR_COUNT (2U)
48930
48934#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
48935#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
48936#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
48939/* The count of USB_ANALOG_LOOPBACK_TOG */
48940#define USB_ANALOG_LOOPBACK_TOG_COUNT (2U)
48941
48945#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)
48946#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)
48947#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)
48948
48949#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)
48950#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)
48951#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)
48952
48953#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)
48954#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)
48955#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)
48958/* The count of USB_ANALOG_MISC */
48959#define USB_ANALOG_MISC_COUNT (2U)
48960
48964#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)
48965#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)
48966#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)
48967
48968#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)
48969#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)
48970#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)
48971
48972#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)
48973#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)
48974#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)
48977/* The count of USB_ANALOG_MISC_SET */
48978#define USB_ANALOG_MISC_SET_COUNT (2U)
48979
48983#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)
48984#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)
48985#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)
48986
48987#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)
48988#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)
48989#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)
48990
48991#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)
48992#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)
48993#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)
48996/* The count of USB_ANALOG_MISC_CLR */
48997#define USB_ANALOG_MISC_CLR_COUNT (2U)
48998
49002#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)
49003#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)
49004#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)
49005
49006#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)
49007#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)
49008#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)
49009
49010#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)
49011#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)
49012#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)
49015/* The count of USB_ANALOG_MISC_TOG */
49016#define USB_ANALOG_MISC_TOG_COUNT (2U)
49017
49021#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)
49022#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)
49026#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK) /* end of group USB_ANALOG_Register_Masks */
49033
49034
49035/* USB_ANALOG - Peripheral instance base addresses */
49037#define USB_ANALOG_BASE (0x400D8000u)
49039#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)
49041#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }
49043#define USB_ANALOG_BASE_PTRS { USB_ANALOG }
49044 /* end of group USB_ANALOG_Peripheral_Access_Layer */
49048
49049
49050/* ----------------------------------------------------------------------------
49051 -- USDHC Peripheral Access Layer
49052 ---------------------------------------------------------------------------- */
49053
49060typedef struct {
49061 __IO uint32_t DS_ADDR;
49062 __IO uint32_t BLK_ATT;
49063 __IO uint32_t CMD_ARG;
49064 __IO uint32_t CMD_XFR_TYP;
49065 __I uint32_t CMD_RSP0;
49066 __I uint32_t CMD_RSP1;
49067 __I uint32_t CMD_RSP2;
49068 __I uint32_t CMD_RSP3;
49069 __IO uint32_t DATA_BUFF_ACC_PORT;
49070 __I uint32_t PRES_STATE;
49071 __IO uint32_t PROT_CTRL;
49072 __IO uint32_t SYS_CTRL;
49073 __IO uint32_t INT_STATUS;
49074 __IO uint32_t INT_STATUS_EN;
49075 __IO uint32_t INT_SIGNAL_EN;
49076 __IO uint32_t AUTOCMD12_ERR_STATUS;
49077 __IO uint32_t HOST_CTRL_CAP;
49078 __IO uint32_t WTMK_LVL;
49079 __IO uint32_t MIX_CTRL;
49080 uint8_t RESERVED_0[4];
49081 __O uint32_t FORCE_EVENT;
49082 __I uint32_t ADMA_ERR_STATUS;
49083 __IO uint32_t ADMA_SYS_ADDR;
49084 uint8_t RESERVED_1[4];
49085 __IO uint32_t DLL_CTRL;
49086 __I uint32_t DLL_STATUS;
49087 __IO uint32_t CLK_TUNE_CTRL_STATUS;
49088 uint8_t RESERVED_2[84];
49089 __IO uint32_t VEND_SPEC;
49090 __IO uint32_t MMC_BOOT;
49091 __IO uint32_t VEND_SPEC2;
49092 __IO uint32_t TUNING_CTRL;
49093} USDHC_Type;
49094
49095/* ----------------------------------------------------------------------------
49096 -- USDHC Register Masks
49097 ---------------------------------------------------------------------------- */
49098
49107#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
49108#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
49111#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
49117#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
49118#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
49130#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
49131
49132#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
49133#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
49140#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
49146#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
49147#define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
49150#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
49156#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
49157#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
49164#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
49165
49166#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
49167#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
49172#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
49173
49174#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
49175#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
49180#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
49181
49182#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
49183#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
49188#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
49189
49190#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
49191#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
49198#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
49199
49200#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
49201#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
49204#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
49210#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
49211#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
49214#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
49220#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
49221#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
49224#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
49230#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
49231#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
49234#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
49240#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
49241#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
49244#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
49250#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
49251#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
49254#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
49260#define USDHC_PRES_STATE_CIHB_MASK (0x1U)
49261#define USDHC_PRES_STATE_CIHB_SHIFT (0U)
49266#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
49267
49268#define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
49269#define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
49274#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
49275
49276#define USDHC_PRES_STATE_DLA_MASK (0x4U)
49277#define USDHC_PRES_STATE_DLA_SHIFT (2U)
49282#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
49283
49284#define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
49285#define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
49290#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
49291
49292#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
49293#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
49298#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
49299
49300#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
49301#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
49306#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
49307
49308#define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
49309#define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
49314#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
49315
49316#define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
49317#define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
49322#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
49323
49324#define USDHC_PRES_STATE_WTA_MASK (0x100U)
49325#define USDHC_PRES_STATE_WTA_SHIFT (8U)
49330#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
49331
49332#define USDHC_PRES_STATE_RTA_MASK (0x200U)
49333#define USDHC_PRES_STATE_RTA_SHIFT (9U)
49338#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
49339
49340#define USDHC_PRES_STATE_BWEN_MASK (0x400U)
49341#define USDHC_PRES_STATE_BWEN_SHIFT (10U)
49346#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
49347
49348#define USDHC_PRES_STATE_BREN_MASK (0x800U)
49349#define USDHC_PRES_STATE_BREN_SHIFT (11U)
49354#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
49355
49356#define USDHC_PRES_STATE_RTR_MASK (0x1000U)
49357#define USDHC_PRES_STATE_RTR_SHIFT (12U)
49362#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
49363
49364#define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
49365#define USDHC_PRES_STATE_TSCD_SHIFT (15U)
49370#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
49371
49372#define USDHC_PRES_STATE_CINST_MASK (0x10000U)
49373#define USDHC_PRES_STATE_CINST_SHIFT (16U)
49378#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
49379
49380#define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
49381#define USDHC_PRES_STATE_CDPL_SHIFT (18U)
49386#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
49387
49388#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
49389#define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
49394#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
49395
49396#define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
49397#define USDHC_PRES_STATE_CLSL_SHIFT (23U)
49400#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
49401
49402#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
49403#define USDHC_PRES_STATE_DLSL_SHIFT (24U)
49414#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
49420#define USDHC_PROT_CTRL_LCTL_MASK (0x1U)
49421#define USDHC_PROT_CTRL_LCTL_SHIFT (0U)
49426#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
49427
49428#define USDHC_PROT_CTRL_DTW_MASK (0x6U)
49429#define USDHC_PROT_CTRL_DTW_SHIFT (1U)
49436#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
49437
49438#define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
49439#define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
49444#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
49445
49446#define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
49447#define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
49454#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
49455
49456#define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
49457#define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
49462#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
49463
49464#define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
49465#define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
49470#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
49471
49472#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
49473#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
49480#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
49481
49482#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
49483#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
49488#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
49489
49490#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
49491#define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
49496#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
49497
49498#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
49499#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
49504#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
49505
49506#define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
49507#define USDHC_PROT_CTRL_IABG_SHIFT (19U)
49512#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
49513
49514#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
49515#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
49518#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
49519
49520#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
49521#define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
49526#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
49527
49528#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
49529#define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
49534#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
49535
49536#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
49537#define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
49542#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
49543
49544#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
49545#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
49551#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
49552
49553#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
49554#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
49559#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
49565#define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
49566#define USDHC_SYS_CTRL_DVS_SHIFT (4U)
49573#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
49574
49575#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
49576#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
49579#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
49580
49581#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
49582#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
49592#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
49593
49594#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
49595#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
49598#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
49599
49600#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
49601#define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
49606#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
49607
49608#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
49609#define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
49614#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
49615
49616#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
49617#define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
49622#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
49623
49624#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
49625#define USDHC_SYS_CTRL_INITA_SHIFT (27U)
49628#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
49629
49630#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
49631#define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
49634#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
49640#define USDHC_INT_STATUS_CC_MASK (0x1U)
49641#define USDHC_INT_STATUS_CC_SHIFT (0U)
49646#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
49647
49648#define USDHC_INT_STATUS_TC_MASK (0x2U)
49649#define USDHC_INT_STATUS_TC_SHIFT (1U)
49654#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
49655
49656#define USDHC_INT_STATUS_BGE_MASK (0x4U)
49657#define USDHC_INT_STATUS_BGE_SHIFT (2U)
49662#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
49663
49664#define USDHC_INT_STATUS_DINT_MASK (0x8U)
49665#define USDHC_INT_STATUS_DINT_SHIFT (3U)
49670#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
49671
49672#define USDHC_INT_STATUS_BWR_MASK (0x10U)
49673#define USDHC_INT_STATUS_BWR_SHIFT (4U)
49678#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
49679
49680#define USDHC_INT_STATUS_BRR_MASK (0x20U)
49681#define USDHC_INT_STATUS_BRR_SHIFT (5U)
49686#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
49687
49688#define USDHC_INT_STATUS_CINS_MASK (0x40U)
49689#define USDHC_INT_STATUS_CINS_SHIFT (6U)
49694#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
49695
49696#define USDHC_INT_STATUS_CRM_MASK (0x80U)
49697#define USDHC_INT_STATUS_CRM_SHIFT (7U)
49702#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
49703
49704#define USDHC_INT_STATUS_CINT_MASK (0x100U)
49705#define USDHC_INT_STATUS_CINT_SHIFT (8U)
49710#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
49711
49712#define USDHC_INT_STATUS_RTE_MASK (0x1000U)
49713#define USDHC_INT_STATUS_RTE_SHIFT (12U)
49718#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
49719
49720#define USDHC_INT_STATUS_TP_MASK (0x4000U)
49721#define USDHC_INT_STATUS_TP_SHIFT (14U)
49724#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
49725
49726#define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
49727#define USDHC_INT_STATUS_CTOE_SHIFT (16U)
49732#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
49733
49734#define USDHC_INT_STATUS_CCE_MASK (0x20000U)
49735#define USDHC_INT_STATUS_CCE_SHIFT (17U)
49740#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
49741
49742#define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
49743#define USDHC_INT_STATUS_CEBE_SHIFT (18U)
49748#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
49749
49750#define USDHC_INT_STATUS_CIE_MASK (0x80000U)
49751#define USDHC_INT_STATUS_CIE_SHIFT (19U)
49756#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
49757
49758#define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
49759#define USDHC_INT_STATUS_DTOE_SHIFT (20U)
49764#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
49765
49766#define USDHC_INT_STATUS_DCE_MASK (0x200000U)
49767#define USDHC_INT_STATUS_DCE_SHIFT (21U)
49772#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
49773
49774#define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
49775#define USDHC_INT_STATUS_DEBE_SHIFT (22U)
49780#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
49781
49782#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
49783#define USDHC_INT_STATUS_AC12E_SHIFT (24U)
49788#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
49789
49790#define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
49791#define USDHC_INT_STATUS_TNE_SHIFT (26U)
49794#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
49795
49796#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
49797#define USDHC_INT_STATUS_DMAE_SHIFT (28U)
49802#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
49808#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
49809#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
49814#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
49815
49816#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
49817#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
49822#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
49823
49824#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
49825#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
49830#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
49831
49832#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
49833#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
49838#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
49839
49840#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
49841#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
49846#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
49847
49848#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
49849#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
49854#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
49855
49856#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
49857#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
49862#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
49863
49864#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
49865#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
49870#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
49871
49872#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
49873#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
49878#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
49879
49880#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
49881#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
49886#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
49887
49888#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
49889#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
49894#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
49895
49896#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
49897#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
49902#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
49903
49904#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
49905#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
49910#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
49911
49912#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
49913#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
49918#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
49919
49920#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
49921#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
49926#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
49927
49928#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
49929#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
49934#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
49935
49936#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
49937#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
49942#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
49943
49944#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
49945#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
49950#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
49951
49952#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
49953#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
49958#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
49959
49960#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
49961#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
49966#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
49967
49968#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
49969#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
49974#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
49980#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
49981#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
49986#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
49987
49988#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
49989#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
49994#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
49995
49996#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
49997#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
50002#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
50003
50004#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
50005#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
50010#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
50011
50012#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
50013#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
50018#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
50019
50020#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
50021#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
50026#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
50027
50028#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
50029#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
50034#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
50035
50036#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
50037#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
50042#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
50043
50044#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
50045#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
50050#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
50051
50052#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
50053#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
50058#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
50059
50060#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
50061#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
50066#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
50067
50068#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
50069#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
50074#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
50075
50076#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
50077#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
50082#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
50083
50084#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
50085#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
50090#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
50091
50092#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
50093#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
50098#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
50099
50100#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
50101#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
50106#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
50107
50108#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
50109#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
50114#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
50115
50116#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
50117#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
50122#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
50123
50124#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
50125#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
50130#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
50131
50132#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
50133#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
50138#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
50139
50140#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
50141#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
50146#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
50152#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
50153#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
50158#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
50159
50160#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
50161#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
50166#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
50167
50168#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
50169#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
50174#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
50175
50176#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
50177#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
50182#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
50183
50184#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
50185#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
50190#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
50191
50192#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
50193#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
50198#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
50199
50200#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
50201#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
50204#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
50205
50206#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
50207#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
50212#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
50218#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
50219#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
50222#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
50223
50224#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
50225#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
50228#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
50229
50230#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
50231#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
50234#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
50235
50236#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
50237#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
50240#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
50241
50242#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
50243#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
50248#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
50249
50250#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
50251#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
50258#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
50259
50260#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
50261#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
50268#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
50269
50270#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
50271#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
50276#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
50277
50278#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
50279#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
50284#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
50285
50286#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
50287#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
50292#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
50293
50294#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
50295#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
50300#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
50301
50302#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
50303#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
50308#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
50309
50310#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
50311#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
50316#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
50317
50318#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
50319#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
50324#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
50330#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
50331#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
50334#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
50335
50336#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
50337#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
50340#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
50341
50342#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
50343#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
50346#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
50347
50348#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
50349#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
50352#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
50358#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
50359#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
50364#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
50365
50366#define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
50367#define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
50372#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
50373
50374#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
50375#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
50380#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
50381
50382#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
50383#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
50386#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
50387
50388#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
50389#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
50394#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
50395
50396#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
50397#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
50402#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
50403
50404#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
50405#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
50408#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
50409
50410#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
50411#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
50414#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
50415
50416#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
50417#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
50422#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
50423
50424#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
50425#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
50430#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
50431
50432#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
50433#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
50438#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
50439
50440#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
50441#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
50446#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
50452#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
50453#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
50456#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
50457
50458#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
50459#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
50462#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
50463
50464#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
50465#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
50468#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
50469
50470#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
50471#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
50474#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
50475
50476#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
50477#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
50480#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
50481
50482#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
50483#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
50486#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
50487
50488#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
50489#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
50492#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
50493
50494#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
50495#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
50498#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
50499
50500#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
50501#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
50504#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
50505
50506#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
50507#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
50510#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
50511
50512#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
50513#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
50516#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
50517
50518#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
50519#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
50522#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
50523
50524#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
50525#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
50528#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
50529
50530#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
50531#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
50534#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
50535
50536#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
50537#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
50540#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
50541
50542#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
50543#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
50546#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
50547
50548#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
50549#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
50552#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
50558#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
50559#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
50562#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
50563
50564#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
50565#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
50570#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
50571
50572#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
50573#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
50578#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
50584#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
50585#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
50588#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
50594#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
50595#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
50598#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
50599
50600#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
50601#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
50604#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
50605
50606#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
50607#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
50610#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
50611
50612#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
50613#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
50616#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
50617
50618#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
50619#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
50622#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
50623
50624#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
50625#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
50628#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
50629
50630#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
50631#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
50634#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
50635
50636#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
50637#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
50640#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
50641
50642#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
50643#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
50646#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
50647
50648#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
50649#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
50652#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
50658#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
50659#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
50662#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
50663
50664#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
50665#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
50668#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
50669
50670#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
50671#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
50674#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
50675
50676#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
50677#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
50680#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
50686#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
50687#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
50690#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
50691
50692#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
50693#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
50696#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
50697
50698#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
50699#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
50702#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
50703
50704#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
50705#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
50708#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
50709
50710#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
50711#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
50714#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
50715
50716#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
50717#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
50720#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
50721
50722#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
50723#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
50726#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
50727
50728#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
50729#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
50732#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
50738#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
50739#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
50744#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
50745
50746#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
50747#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
50752#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
50753
50754#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
50755#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
50760#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
50761
50762#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
50763#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
50768#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
50769
50770#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
50771#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
50776#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
50777
50778#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
50779#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
50784#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
50790#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
50791#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
50804#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
50805
50806#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
50807#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
50812#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
50813
50814#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
50815#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
50820#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
50821
50822#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
50823#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
50828#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
50829
50830#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
50831#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
50834#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
50835
50836#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
50837#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
50842#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
50843
50844#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
50845#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
50848#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
50854#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
50855#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
50860#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
50861
50862#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
50863#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
50866#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
50867
50868#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
50869#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
50872#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
50873
50874#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
50875#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
50880#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
50881
50882#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
50883#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
50888#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
50894#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
50895#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
50898#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
50899
50900#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
50901#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
50904#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
50905
50906#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
50907#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
50910#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
50911
50912#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
50913#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
50916#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
50917
50918#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
50919#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
50922#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) /* end of group USDHC_Register_Masks */
50929
50930
50931/* USDHC - Peripheral instance base addresses */
50933#define USDHC1_BASE (0x402C0000u)
50935#define USDHC1 ((USDHC_Type *)USDHC1_BASE)
50937#define USDHC2_BASE (0x402C4000u)
50939#define USDHC2 ((USDHC_Type *)USDHC2_BASE)
50941#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }
50943#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }
50945#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
50946 /* end of group USDHC_Peripheral_Access_Layer */
50950
50951
50952/* ----------------------------------------------------------------------------
50953 -- WDOG Peripheral Access Layer
50954 ---------------------------------------------------------------------------- */
50955
50962typedef struct {
50963 __IO uint16_t WCR;
50964 __IO uint16_t WSR;
50965 __I uint16_t WRSR;
50966 __IO uint16_t WICR;
50967 __IO uint16_t WMCR;
50968} WDOG_Type;
50969
50970/* ----------------------------------------------------------------------------
50971 -- WDOG Register Masks
50972 ---------------------------------------------------------------------------- */
50973
50982#define WDOG_WCR_WDZST_MASK (0x1U)
50983#define WDOG_WCR_WDZST_SHIFT (0U)
50988#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
50989
50990#define WDOG_WCR_WDBG_MASK (0x2U)
50991#define WDOG_WCR_WDBG_SHIFT (1U)
50996#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
50997
50998#define WDOG_WCR_WDE_MASK (0x4U)
50999#define WDOG_WCR_WDE_SHIFT (2U)
51004#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
51005
51006#define WDOG_WCR_WDT_MASK (0x8U)
51007#define WDOG_WCR_WDT_SHIFT (3U)
51012#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
51013
51014#define WDOG_WCR_SRS_MASK (0x10U)
51015#define WDOG_WCR_SRS_SHIFT (4U)
51020#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
51021
51022#define WDOG_WCR_WDA_MASK (0x20U)
51023#define WDOG_WCR_WDA_SHIFT (5U)
51028#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
51029
51030#define WDOG_WCR_SRE_MASK (0x40U)
51031#define WDOG_WCR_SRE_SHIFT (6U)
51036#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
51037
51038#define WDOG_WCR_WDW_MASK (0x80U)
51039#define WDOG_WCR_WDW_SHIFT (7U)
51044#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
51045
51046#define WDOG_WCR_WT_MASK (0xFF00U)
51047#define WDOG_WCR_WT_SHIFT (8U)
51055#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
51061#define WDOG_WSR_WSR_MASK (0xFFFFU)
51062#define WDOG_WSR_WSR_SHIFT (0U)
51067#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
51073#define WDOG_WRSR_SFTW_MASK (0x1U)
51074#define WDOG_WRSR_SFTW_SHIFT (0U)
51079#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
51080
51081#define WDOG_WRSR_TOUT_MASK (0x2U)
51082#define WDOG_WRSR_TOUT_SHIFT (1U)
51087#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
51088
51089#define WDOG_WRSR_POR_MASK (0x10U)
51090#define WDOG_WRSR_POR_SHIFT (4U)
51095#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
51101#define WDOG_WICR_WICT_MASK (0xFFU)
51102#define WDOG_WICR_WICT_SHIFT (0U)
51109#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
51110
51111#define WDOG_WICR_WTIS_MASK (0x4000U)
51112#define WDOG_WICR_WTIS_SHIFT (14U)
51117#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
51118
51119#define WDOG_WICR_WIE_MASK (0x8000U)
51120#define WDOG_WICR_WIE_SHIFT (15U)
51125#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
51131#define WDOG_WMCR_PDE_MASK (0x1U)
51132#define WDOG_WMCR_PDE_SHIFT (0U)
51137#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) /* end of group WDOG_Register_Masks */
51144
51145
51146/* WDOG - Peripheral instance base addresses */
51148#define WDOG1_BASE (0x400B8000u)
51150#define WDOG1 ((WDOG_Type *)WDOG1_BASE)
51152#define WDOG2_BASE (0x400D0000u)
51154#define WDOG2 ((WDOG_Type *)WDOG2_BASE)
51156#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }
51158#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }
51160#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
51161 /* end of group WDOG_Peripheral_Access_Layer */
51165
51166
51167/* ----------------------------------------------------------------------------
51168 -- XBARA Peripheral Access Layer
51169 ---------------------------------------------------------------------------- */
51170
51177typedef struct {
51178 __IO uint16_t SEL0;
51179 __IO uint16_t SEL1;
51180 __IO uint16_t SEL2;
51181 __IO uint16_t SEL3;
51182 __IO uint16_t SEL4;
51183 __IO uint16_t SEL5;
51184 __IO uint16_t SEL6;
51185 __IO uint16_t SEL7;
51186 __IO uint16_t SEL8;
51187 __IO uint16_t SEL9;
51188 __IO uint16_t SEL10;
51189 __IO uint16_t SEL11;
51190 __IO uint16_t SEL12;
51191 __IO uint16_t SEL13;
51192 __IO uint16_t SEL14;
51193 __IO uint16_t SEL15;
51194 __IO uint16_t SEL16;
51195 __IO uint16_t SEL17;
51196 __IO uint16_t SEL18;
51197 __IO uint16_t SEL19;
51198 __IO uint16_t SEL20;
51199 __IO uint16_t SEL21;
51200 __IO uint16_t SEL22;
51201 __IO uint16_t SEL23;
51202 __IO uint16_t SEL24;
51203 __IO uint16_t SEL25;
51204 __IO uint16_t SEL26;
51205 __IO uint16_t SEL27;
51206 __IO uint16_t SEL28;
51207 __IO uint16_t SEL29;
51208 __IO uint16_t SEL30;
51209 __IO uint16_t SEL31;
51210 __IO uint16_t SEL32;
51211 __IO uint16_t SEL33;
51212 __IO uint16_t SEL34;
51213 __IO uint16_t SEL35;
51214 __IO uint16_t SEL36;
51215 __IO uint16_t SEL37;
51216 __IO uint16_t SEL38;
51217 __IO uint16_t SEL39;
51218 __IO uint16_t SEL40;
51219 __IO uint16_t SEL41;
51220 __IO uint16_t SEL42;
51221 __IO uint16_t SEL43;
51222 __IO uint16_t SEL44;
51223 __IO uint16_t SEL45;
51224 __IO uint16_t SEL46;
51225 __IO uint16_t SEL47;
51226 __IO uint16_t SEL48;
51227 __IO uint16_t SEL49;
51228 __IO uint16_t SEL50;
51229 __IO uint16_t SEL51;
51230 __IO uint16_t SEL52;
51231 __IO uint16_t SEL53;
51232 __IO uint16_t SEL54;
51233 __IO uint16_t SEL55;
51234 __IO uint16_t SEL56;
51235 __IO uint16_t SEL57;
51236 __IO uint16_t SEL58;
51237 __IO uint16_t SEL59;
51238 __IO uint16_t SEL60;
51239 __IO uint16_t SEL61;
51240 __IO uint16_t SEL62;
51241 __IO uint16_t SEL63;
51242 __IO uint16_t SEL64;
51243 __IO uint16_t SEL65;
51244 __IO uint16_t CTRL0;
51245 __IO uint16_t CTRL1;
51246} XBARA_Type;
51247
51248/* ----------------------------------------------------------------------------
51249 -- XBARA Register Masks
51250 ---------------------------------------------------------------------------- */
51251
51260#define XBARA_SEL0_SEL0_MASK (0x7FU)
51261#define XBARA_SEL0_SEL0_SHIFT (0U)
51262#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
51263
51264#define XBARA_SEL0_SEL1_MASK (0x7F00U)
51265#define XBARA_SEL0_SEL1_SHIFT (8U)
51266#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
51272#define XBARA_SEL1_SEL2_MASK (0x7FU)
51273#define XBARA_SEL1_SEL2_SHIFT (0U)
51274#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
51275
51276#define XBARA_SEL1_SEL3_MASK (0x7F00U)
51277#define XBARA_SEL1_SEL3_SHIFT (8U)
51278#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
51284#define XBARA_SEL2_SEL4_MASK (0x7FU)
51285#define XBARA_SEL2_SEL4_SHIFT (0U)
51286#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
51287
51288#define XBARA_SEL2_SEL5_MASK (0x7F00U)
51289#define XBARA_SEL2_SEL5_SHIFT (8U)
51290#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
51296#define XBARA_SEL3_SEL6_MASK (0x7FU)
51297#define XBARA_SEL3_SEL6_SHIFT (0U)
51298#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
51299
51300#define XBARA_SEL3_SEL7_MASK (0x7F00U)
51301#define XBARA_SEL3_SEL7_SHIFT (8U)
51302#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
51308#define XBARA_SEL4_SEL8_MASK (0x7FU)
51309#define XBARA_SEL4_SEL8_SHIFT (0U)
51310#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
51311
51312#define XBARA_SEL4_SEL9_MASK (0x7F00U)
51313#define XBARA_SEL4_SEL9_SHIFT (8U)
51314#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
51320#define XBARA_SEL5_SEL10_MASK (0x7FU)
51321#define XBARA_SEL5_SEL10_SHIFT (0U)
51322#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
51323
51324#define XBARA_SEL5_SEL11_MASK (0x7F00U)
51325#define XBARA_SEL5_SEL11_SHIFT (8U)
51326#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
51332#define XBARA_SEL6_SEL12_MASK (0x7FU)
51333#define XBARA_SEL6_SEL12_SHIFT (0U)
51334#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
51335
51336#define XBARA_SEL6_SEL13_MASK (0x7F00U)
51337#define XBARA_SEL6_SEL13_SHIFT (8U)
51338#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
51344#define XBARA_SEL7_SEL14_MASK (0x7FU)
51345#define XBARA_SEL7_SEL14_SHIFT (0U)
51346#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
51347
51348#define XBARA_SEL7_SEL15_MASK (0x7F00U)
51349#define XBARA_SEL7_SEL15_SHIFT (8U)
51350#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
51356#define XBARA_SEL8_SEL16_MASK (0x7FU)
51357#define XBARA_SEL8_SEL16_SHIFT (0U)
51358#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
51359
51360#define XBARA_SEL8_SEL17_MASK (0x7F00U)
51361#define XBARA_SEL8_SEL17_SHIFT (8U)
51362#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
51368#define XBARA_SEL9_SEL18_MASK (0x7FU)
51369#define XBARA_SEL9_SEL18_SHIFT (0U)
51370#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
51371
51372#define XBARA_SEL9_SEL19_MASK (0x7F00U)
51373#define XBARA_SEL9_SEL19_SHIFT (8U)
51374#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
51380#define XBARA_SEL10_SEL20_MASK (0x7FU)
51381#define XBARA_SEL10_SEL20_SHIFT (0U)
51382#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
51383
51384#define XBARA_SEL10_SEL21_MASK (0x7F00U)
51385#define XBARA_SEL10_SEL21_SHIFT (8U)
51386#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
51392#define XBARA_SEL11_SEL22_MASK (0x7FU)
51393#define XBARA_SEL11_SEL22_SHIFT (0U)
51394#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
51395
51396#define XBARA_SEL11_SEL23_MASK (0x7F00U)
51397#define XBARA_SEL11_SEL23_SHIFT (8U)
51398#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
51404#define XBARA_SEL12_SEL24_MASK (0x7FU)
51405#define XBARA_SEL12_SEL24_SHIFT (0U)
51406#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
51407
51408#define XBARA_SEL12_SEL25_MASK (0x7F00U)
51409#define XBARA_SEL12_SEL25_SHIFT (8U)
51410#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
51416#define XBARA_SEL13_SEL26_MASK (0x7FU)
51417#define XBARA_SEL13_SEL26_SHIFT (0U)
51418#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
51419
51420#define XBARA_SEL13_SEL27_MASK (0x7F00U)
51421#define XBARA_SEL13_SEL27_SHIFT (8U)
51422#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
51428#define XBARA_SEL14_SEL28_MASK (0x7FU)
51429#define XBARA_SEL14_SEL28_SHIFT (0U)
51430#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
51431
51432#define XBARA_SEL14_SEL29_MASK (0x7F00U)
51433#define XBARA_SEL14_SEL29_SHIFT (8U)
51434#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
51440#define XBARA_SEL15_SEL30_MASK (0x7FU)
51441#define XBARA_SEL15_SEL30_SHIFT (0U)
51442#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
51443
51444#define XBARA_SEL15_SEL31_MASK (0x7F00U)
51445#define XBARA_SEL15_SEL31_SHIFT (8U)
51446#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
51452#define XBARA_SEL16_SEL32_MASK (0x7FU)
51453#define XBARA_SEL16_SEL32_SHIFT (0U)
51454#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
51455
51456#define XBARA_SEL16_SEL33_MASK (0x7F00U)
51457#define XBARA_SEL16_SEL33_SHIFT (8U)
51458#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
51464#define XBARA_SEL17_SEL34_MASK (0x7FU)
51465#define XBARA_SEL17_SEL34_SHIFT (0U)
51466#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
51467
51468#define XBARA_SEL17_SEL35_MASK (0x7F00U)
51469#define XBARA_SEL17_SEL35_SHIFT (8U)
51470#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
51476#define XBARA_SEL18_SEL36_MASK (0x7FU)
51477#define XBARA_SEL18_SEL36_SHIFT (0U)
51478#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
51479
51480#define XBARA_SEL18_SEL37_MASK (0x7F00U)
51481#define XBARA_SEL18_SEL37_SHIFT (8U)
51482#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
51488#define XBARA_SEL19_SEL38_MASK (0x7FU)
51489#define XBARA_SEL19_SEL38_SHIFT (0U)
51490#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
51491
51492#define XBARA_SEL19_SEL39_MASK (0x7F00U)
51493#define XBARA_SEL19_SEL39_SHIFT (8U)
51494#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
51500#define XBARA_SEL20_SEL40_MASK (0x7FU)
51501#define XBARA_SEL20_SEL40_SHIFT (0U)
51502#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
51503
51504#define XBARA_SEL20_SEL41_MASK (0x7F00U)
51505#define XBARA_SEL20_SEL41_SHIFT (8U)
51506#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
51512#define XBARA_SEL21_SEL42_MASK (0x7FU)
51513#define XBARA_SEL21_SEL42_SHIFT (0U)
51514#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
51515
51516#define XBARA_SEL21_SEL43_MASK (0x7F00U)
51517#define XBARA_SEL21_SEL43_SHIFT (8U)
51518#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
51524#define XBARA_SEL22_SEL44_MASK (0x7FU)
51525#define XBARA_SEL22_SEL44_SHIFT (0U)
51526#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
51527
51528#define XBARA_SEL22_SEL45_MASK (0x7F00U)
51529#define XBARA_SEL22_SEL45_SHIFT (8U)
51530#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
51536#define XBARA_SEL23_SEL46_MASK (0x7FU)
51537#define XBARA_SEL23_SEL46_SHIFT (0U)
51538#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
51539
51540#define XBARA_SEL23_SEL47_MASK (0x7F00U)
51541#define XBARA_SEL23_SEL47_SHIFT (8U)
51542#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
51548#define XBARA_SEL24_SEL48_MASK (0x7FU)
51549#define XBARA_SEL24_SEL48_SHIFT (0U)
51550#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
51551
51552#define XBARA_SEL24_SEL49_MASK (0x7F00U)
51553#define XBARA_SEL24_SEL49_SHIFT (8U)
51554#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
51560#define XBARA_SEL25_SEL50_MASK (0x7FU)
51561#define XBARA_SEL25_SEL50_SHIFT (0U)
51562#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
51563
51564#define XBARA_SEL25_SEL51_MASK (0x7F00U)
51565#define XBARA_SEL25_SEL51_SHIFT (8U)
51566#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
51572#define XBARA_SEL26_SEL52_MASK (0x7FU)
51573#define XBARA_SEL26_SEL52_SHIFT (0U)
51574#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
51575
51576#define XBARA_SEL26_SEL53_MASK (0x7F00U)
51577#define XBARA_SEL26_SEL53_SHIFT (8U)
51578#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
51584#define XBARA_SEL27_SEL54_MASK (0x7FU)
51585#define XBARA_SEL27_SEL54_SHIFT (0U)
51586#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
51587
51588#define XBARA_SEL27_SEL55_MASK (0x7F00U)
51589#define XBARA_SEL27_SEL55_SHIFT (8U)
51590#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
51596#define XBARA_SEL28_SEL56_MASK (0x7FU)
51597#define XBARA_SEL28_SEL56_SHIFT (0U)
51598#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
51599
51600#define XBARA_SEL28_SEL57_MASK (0x7F00U)
51601#define XBARA_SEL28_SEL57_SHIFT (8U)
51602#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
51608#define XBARA_SEL29_SEL58_MASK (0x7FU)
51609#define XBARA_SEL29_SEL58_SHIFT (0U)
51610#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
51611
51612#define XBARA_SEL29_SEL59_MASK (0x7F00U)
51613#define XBARA_SEL29_SEL59_SHIFT (8U)
51614#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
51620#define XBARA_SEL30_SEL60_MASK (0x7FU)
51621#define XBARA_SEL30_SEL60_SHIFT (0U)
51622#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
51623
51624#define XBARA_SEL30_SEL61_MASK (0x7F00U)
51625#define XBARA_SEL30_SEL61_SHIFT (8U)
51626#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
51632#define XBARA_SEL31_SEL62_MASK (0x7FU)
51633#define XBARA_SEL31_SEL62_SHIFT (0U)
51634#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
51635
51636#define XBARA_SEL31_SEL63_MASK (0x7F00U)
51637#define XBARA_SEL31_SEL63_SHIFT (8U)
51638#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
51644#define XBARA_SEL32_SEL64_MASK (0x7FU)
51645#define XBARA_SEL32_SEL64_SHIFT (0U)
51646#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
51647
51648#define XBARA_SEL32_SEL65_MASK (0x7F00U)
51649#define XBARA_SEL32_SEL65_SHIFT (8U)
51650#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
51656#define XBARA_SEL33_SEL66_MASK (0x7FU)
51657#define XBARA_SEL33_SEL66_SHIFT (0U)
51658#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
51659
51660#define XBARA_SEL33_SEL67_MASK (0x7F00U)
51661#define XBARA_SEL33_SEL67_SHIFT (8U)
51662#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
51668#define XBARA_SEL34_SEL68_MASK (0x7FU)
51669#define XBARA_SEL34_SEL68_SHIFT (0U)
51670#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
51671
51672#define XBARA_SEL34_SEL69_MASK (0x7F00U)
51673#define XBARA_SEL34_SEL69_SHIFT (8U)
51674#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
51680#define XBARA_SEL35_SEL70_MASK (0x7FU)
51681#define XBARA_SEL35_SEL70_SHIFT (0U)
51682#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
51683
51684#define XBARA_SEL35_SEL71_MASK (0x7F00U)
51685#define XBARA_SEL35_SEL71_SHIFT (8U)
51686#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
51692#define XBARA_SEL36_SEL72_MASK (0x7FU)
51693#define XBARA_SEL36_SEL72_SHIFT (0U)
51694#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
51695
51696#define XBARA_SEL36_SEL73_MASK (0x7F00U)
51697#define XBARA_SEL36_SEL73_SHIFT (8U)
51698#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
51704#define XBARA_SEL37_SEL74_MASK (0x7FU)
51705#define XBARA_SEL37_SEL74_SHIFT (0U)
51706#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
51707
51708#define XBARA_SEL37_SEL75_MASK (0x7F00U)
51709#define XBARA_SEL37_SEL75_SHIFT (8U)
51710#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
51716#define XBARA_SEL38_SEL76_MASK (0x7FU)
51717#define XBARA_SEL38_SEL76_SHIFT (0U)
51718#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
51719
51720#define XBARA_SEL38_SEL77_MASK (0x7F00U)
51721#define XBARA_SEL38_SEL77_SHIFT (8U)
51722#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
51728#define XBARA_SEL39_SEL78_MASK (0x7FU)
51729#define XBARA_SEL39_SEL78_SHIFT (0U)
51730#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
51731
51732#define XBARA_SEL39_SEL79_MASK (0x7F00U)
51733#define XBARA_SEL39_SEL79_SHIFT (8U)
51734#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
51740#define XBARA_SEL40_SEL80_MASK (0x7FU)
51741#define XBARA_SEL40_SEL80_SHIFT (0U)
51742#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
51743
51744#define XBARA_SEL40_SEL81_MASK (0x7F00U)
51745#define XBARA_SEL40_SEL81_SHIFT (8U)
51746#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
51752#define XBARA_SEL41_SEL82_MASK (0x7FU)
51753#define XBARA_SEL41_SEL82_SHIFT (0U)
51754#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
51755
51756#define XBARA_SEL41_SEL83_MASK (0x7F00U)
51757#define XBARA_SEL41_SEL83_SHIFT (8U)
51758#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
51764#define XBARA_SEL42_SEL84_MASK (0x7FU)
51765#define XBARA_SEL42_SEL84_SHIFT (0U)
51766#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
51767
51768#define XBARA_SEL42_SEL85_MASK (0x7F00U)
51769#define XBARA_SEL42_SEL85_SHIFT (8U)
51770#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
51776#define XBARA_SEL43_SEL86_MASK (0x7FU)
51777#define XBARA_SEL43_SEL86_SHIFT (0U)
51778#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
51779
51780#define XBARA_SEL43_SEL87_MASK (0x7F00U)
51781#define XBARA_SEL43_SEL87_SHIFT (8U)
51782#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
51788#define XBARA_SEL44_SEL88_MASK (0x7FU)
51789#define XBARA_SEL44_SEL88_SHIFT (0U)
51790#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
51791
51792#define XBARA_SEL44_SEL89_MASK (0x7F00U)
51793#define XBARA_SEL44_SEL89_SHIFT (8U)
51794#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
51800#define XBARA_SEL45_SEL90_MASK (0x7FU)
51801#define XBARA_SEL45_SEL90_SHIFT (0U)
51802#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
51803
51804#define XBARA_SEL45_SEL91_MASK (0x7F00U)
51805#define XBARA_SEL45_SEL91_SHIFT (8U)
51806#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
51812#define XBARA_SEL46_SEL92_MASK (0x7FU)
51813#define XBARA_SEL46_SEL92_SHIFT (0U)
51814#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
51815
51816#define XBARA_SEL46_SEL93_MASK (0x7F00U)
51817#define XBARA_SEL46_SEL93_SHIFT (8U)
51818#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
51824#define XBARA_SEL47_SEL94_MASK (0x7FU)
51825#define XBARA_SEL47_SEL94_SHIFT (0U)
51826#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
51827
51828#define XBARA_SEL47_SEL95_MASK (0x7F00U)
51829#define XBARA_SEL47_SEL95_SHIFT (8U)
51830#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
51836#define XBARA_SEL48_SEL96_MASK (0x7FU)
51837#define XBARA_SEL48_SEL96_SHIFT (0U)
51838#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
51839
51840#define XBARA_SEL48_SEL97_MASK (0x7F00U)
51841#define XBARA_SEL48_SEL97_SHIFT (8U)
51842#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
51848#define XBARA_SEL49_SEL98_MASK (0x7FU)
51849#define XBARA_SEL49_SEL98_SHIFT (0U)
51850#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
51851
51852#define XBARA_SEL49_SEL99_MASK (0x7F00U)
51853#define XBARA_SEL49_SEL99_SHIFT (8U)
51854#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
51860#define XBARA_SEL50_SEL100_MASK (0x7FU)
51861#define XBARA_SEL50_SEL100_SHIFT (0U)
51862#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
51863
51864#define XBARA_SEL50_SEL101_MASK (0x7F00U)
51865#define XBARA_SEL50_SEL101_SHIFT (8U)
51866#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
51872#define XBARA_SEL51_SEL102_MASK (0x7FU)
51873#define XBARA_SEL51_SEL102_SHIFT (0U)
51874#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
51875
51876#define XBARA_SEL51_SEL103_MASK (0x7F00U)
51877#define XBARA_SEL51_SEL103_SHIFT (8U)
51878#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
51884#define XBARA_SEL52_SEL104_MASK (0x7FU)
51885#define XBARA_SEL52_SEL104_SHIFT (0U)
51886#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
51887
51888#define XBARA_SEL52_SEL105_MASK (0x7F00U)
51889#define XBARA_SEL52_SEL105_SHIFT (8U)
51890#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
51896#define XBARA_SEL53_SEL106_MASK (0x7FU)
51897#define XBARA_SEL53_SEL106_SHIFT (0U)
51898#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
51899
51900#define XBARA_SEL53_SEL107_MASK (0x7F00U)
51901#define XBARA_SEL53_SEL107_SHIFT (8U)
51902#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
51908#define XBARA_SEL54_SEL108_MASK (0x7FU)
51909#define XBARA_SEL54_SEL108_SHIFT (0U)
51910#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
51911
51912#define XBARA_SEL54_SEL109_MASK (0x7F00U)
51913#define XBARA_SEL54_SEL109_SHIFT (8U)
51914#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
51920#define XBARA_SEL55_SEL110_MASK (0x7FU)
51921#define XBARA_SEL55_SEL110_SHIFT (0U)
51922#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
51923
51924#define XBARA_SEL55_SEL111_MASK (0x7F00U)
51925#define XBARA_SEL55_SEL111_SHIFT (8U)
51926#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
51932#define XBARA_SEL56_SEL112_MASK (0x7FU)
51933#define XBARA_SEL56_SEL112_SHIFT (0U)
51934#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
51935
51936#define XBARA_SEL56_SEL113_MASK (0x7F00U)
51937#define XBARA_SEL56_SEL113_SHIFT (8U)
51938#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
51944#define XBARA_SEL57_SEL114_MASK (0x7FU)
51945#define XBARA_SEL57_SEL114_SHIFT (0U)
51946#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
51947
51948#define XBARA_SEL57_SEL115_MASK (0x7F00U)
51949#define XBARA_SEL57_SEL115_SHIFT (8U)
51950#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
51956#define XBARA_SEL58_SEL116_MASK (0x7FU)
51957#define XBARA_SEL58_SEL116_SHIFT (0U)
51958#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
51959
51960#define XBARA_SEL58_SEL117_MASK (0x7F00U)
51961#define XBARA_SEL58_SEL117_SHIFT (8U)
51962#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
51968#define XBARA_SEL59_SEL118_MASK (0x7FU)
51969#define XBARA_SEL59_SEL118_SHIFT (0U)
51970#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
51971
51972#define XBARA_SEL59_SEL119_MASK (0x7F00U)
51973#define XBARA_SEL59_SEL119_SHIFT (8U)
51974#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
51980#define XBARA_SEL60_SEL120_MASK (0x7FU)
51981#define XBARA_SEL60_SEL120_SHIFT (0U)
51982#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
51983
51984#define XBARA_SEL60_SEL121_MASK (0x7F00U)
51985#define XBARA_SEL60_SEL121_SHIFT (8U)
51986#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
51992#define XBARA_SEL61_SEL122_MASK (0x7FU)
51993#define XBARA_SEL61_SEL122_SHIFT (0U)
51994#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
51995
51996#define XBARA_SEL61_SEL123_MASK (0x7F00U)
51997#define XBARA_SEL61_SEL123_SHIFT (8U)
51998#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
52004#define XBARA_SEL62_SEL124_MASK (0x7FU)
52005#define XBARA_SEL62_SEL124_SHIFT (0U)
52006#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
52007
52008#define XBARA_SEL62_SEL125_MASK (0x7F00U)
52009#define XBARA_SEL62_SEL125_SHIFT (8U)
52010#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
52016#define XBARA_SEL63_SEL126_MASK (0x7FU)
52017#define XBARA_SEL63_SEL126_SHIFT (0U)
52018#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
52019
52020#define XBARA_SEL63_SEL127_MASK (0x7F00U)
52021#define XBARA_SEL63_SEL127_SHIFT (8U)
52022#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
52028#define XBARA_SEL64_SEL128_MASK (0x7FU)
52029#define XBARA_SEL64_SEL128_SHIFT (0U)
52030#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
52031
52032#define XBARA_SEL64_SEL129_MASK (0x7F00U)
52033#define XBARA_SEL64_SEL129_SHIFT (8U)
52034#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
52040#define XBARA_SEL65_SEL130_MASK (0x7FU)
52041#define XBARA_SEL65_SEL130_SHIFT (0U)
52042#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
52043
52044#define XBARA_SEL65_SEL131_MASK (0x7F00U)
52045#define XBARA_SEL65_SEL131_SHIFT (8U)
52046#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
52052#define XBARA_CTRL0_DEN0_MASK (0x1U)
52053#define XBARA_CTRL0_DEN0_SHIFT (0U)
52058#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
52059
52060#define XBARA_CTRL0_IEN0_MASK (0x2U)
52061#define XBARA_CTRL0_IEN0_SHIFT (1U)
52066#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
52067
52068#define XBARA_CTRL0_EDGE0_MASK (0xCU)
52069#define XBARA_CTRL0_EDGE0_SHIFT (2U)
52076#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
52077
52078#define XBARA_CTRL0_STS0_MASK (0x10U)
52079#define XBARA_CTRL0_STS0_SHIFT (4U)
52084#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
52085
52086#define XBARA_CTRL0_DEN1_MASK (0x100U)
52087#define XBARA_CTRL0_DEN1_SHIFT (8U)
52092#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
52093
52094#define XBARA_CTRL0_IEN1_MASK (0x200U)
52095#define XBARA_CTRL0_IEN1_SHIFT (9U)
52100#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
52101
52102#define XBARA_CTRL0_EDGE1_MASK (0xC00U)
52103#define XBARA_CTRL0_EDGE1_SHIFT (10U)
52110#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
52111
52112#define XBARA_CTRL0_STS1_MASK (0x1000U)
52113#define XBARA_CTRL0_STS1_SHIFT (12U)
52118#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
52124#define XBARA_CTRL1_DEN2_MASK (0x1U)
52125#define XBARA_CTRL1_DEN2_SHIFT (0U)
52130#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
52131
52132#define XBARA_CTRL1_IEN2_MASK (0x2U)
52133#define XBARA_CTRL1_IEN2_SHIFT (1U)
52138#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
52139
52140#define XBARA_CTRL1_EDGE2_MASK (0xCU)
52141#define XBARA_CTRL1_EDGE2_SHIFT (2U)
52148#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
52149
52150#define XBARA_CTRL1_STS2_MASK (0x10U)
52151#define XBARA_CTRL1_STS2_SHIFT (4U)
52156#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
52157
52158#define XBARA_CTRL1_DEN3_MASK (0x100U)
52159#define XBARA_CTRL1_DEN3_SHIFT (8U)
52164#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
52165
52166#define XBARA_CTRL1_IEN3_MASK (0x200U)
52167#define XBARA_CTRL1_IEN3_SHIFT (9U)
52172#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
52173
52174#define XBARA_CTRL1_EDGE3_MASK (0xC00U)
52175#define XBARA_CTRL1_EDGE3_SHIFT (10U)
52182#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
52183
52184#define XBARA_CTRL1_STS3_MASK (0x1000U)
52185#define XBARA_CTRL1_STS3_SHIFT (12U)
52190#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) /* end of group XBARA_Register_Masks */
52197
52198
52199/* XBARA - Peripheral instance base addresses */
52201#define XBARA1_BASE (0x403BC000u)
52203#define XBARA1 ((XBARA_Type *)XBARA1_BASE)
52205#define XBARA_BASE_ADDRS { 0u, XBARA1_BASE }
52207#define XBARA_BASE_PTRS { (XBARA_Type *)0u, XBARA1 }
52208 /* end of group XBARA_Peripheral_Access_Layer */
52212
52213
52214/* ----------------------------------------------------------------------------
52215 -- XBARB Peripheral Access Layer
52216 ---------------------------------------------------------------------------- */
52217
52224typedef struct {
52225 __IO uint16_t SEL0;
52226 __IO uint16_t SEL1;
52227 __IO uint16_t SEL2;
52228 __IO uint16_t SEL3;
52229 __IO uint16_t SEL4;
52230 __IO uint16_t SEL5;
52231 __IO uint16_t SEL6;
52232 __IO uint16_t SEL7;
52233} XBARB_Type;
52234
52235/* ----------------------------------------------------------------------------
52236 -- XBARB Register Masks
52237 ---------------------------------------------------------------------------- */
52238
52247#define XBARB_SEL0_SEL0_MASK (0x3FU)
52248#define XBARB_SEL0_SEL0_SHIFT (0U)
52249#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
52250
52251#define XBARB_SEL0_SEL1_MASK (0x3F00U)
52252#define XBARB_SEL0_SEL1_SHIFT (8U)
52253#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
52259#define XBARB_SEL1_SEL2_MASK (0x3FU)
52260#define XBARB_SEL1_SEL2_SHIFT (0U)
52261#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
52262
52263#define XBARB_SEL1_SEL3_MASK (0x3F00U)
52264#define XBARB_SEL1_SEL3_SHIFT (8U)
52265#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
52271#define XBARB_SEL2_SEL4_MASK (0x3FU)
52272#define XBARB_SEL2_SEL4_SHIFT (0U)
52273#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
52274
52275#define XBARB_SEL2_SEL5_MASK (0x3F00U)
52276#define XBARB_SEL2_SEL5_SHIFT (8U)
52277#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
52283#define XBARB_SEL3_SEL6_MASK (0x3FU)
52284#define XBARB_SEL3_SEL6_SHIFT (0U)
52285#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
52286
52287#define XBARB_SEL3_SEL7_MASK (0x3F00U)
52288#define XBARB_SEL3_SEL7_SHIFT (8U)
52289#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
52295#define XBARB_SEL4_SEL8_MASK (0x3FU)
52296#define XBARB_SEL4_SEL8_SHIFT (0U)
52297#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
52298
52299#define XBARB_SEL4_SEL9_MASK (0x3F00U)
52300#define XBARB_SEL4_SEL9_SHIFT (8U)
52301#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
52307#define XBARB_SEL5_SEL10_MASK (0x3FU)
52308#define XBARB_SEL5_SEL10_SHIFT (0U)
52309#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
52310
52311#define XBARB_SEL5_SEL11_MASK (0x3F00U)
52312#define XBARB_SEL5_SEL11_SHIFT (8U)
52313#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
52319#define XBARB_SEL6_SEL12_MASK (0x3FU)
52320#define XBARB_SEL6_SEL12_SHIFT (0U)
52321#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
52322
52323#define XBARB_SEL6_SEL13_MASK (0x3F00U)
52324#define XBARB_SEL6_SEL13_SHIFT (8U)
52325#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
52331#define XBARB_SEL7_SEL14_MASK (0x3FU)
52332#define XBARB_SEL7_SEL14_SHIFT (0U)
52333#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
52334
52335#define XBARB_SEL7_SEL15_MASK (0x3F00U)
52336#define XBARB_SEL7_SEL15_SHIFT (8U)
52337#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) /* end of group XBARB_Register_Masks */
52344
52345
52346/* XBARB - Peripheral instance base addresses */
52348#define XBARB2_BASE (0x403C0000u)
52350#define XBARB2 ((XBARB_Type *)XBARB2_BASE)
52352#define XBARB3_BASE (0x403C4000u)
52354#define XBARB3 ((XBARB_Type *)XBARB3_BASE)
52356#define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
52358#define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
52359 /* end of group XBARB_Peripheral_Access_Layer */
52363
52364
52365/* ----------------------------------------------------------------------------
52366 -- XTALOSC24M Peripheral Access Layer
52367 ---------------------------------------------------------------------------- */
52368
52375typedef struct {
52376 uint8_t RESERVED_0[336];
52377 __IO uint32_t MISC0;
52378 __IO uint32_t MISC0_SET;
52379 __IO uint32_t MISC0_CLR;
52380 __IO uint32_t MISC0_TOG;
52381 uint8_t RESERVED_1[272];
52382 __IO uint32_t LOWPWR_CTRL;
52383 __IO uint32_t LOWPWR_CTRL_SET;
52384 __IO uint32_t LOWPWR_CTRL_CLR;
52385 __IO uint32_t LOWPWR_CTRL_TOG;
52386 uint8_t RESERVED_2[32];
52387 __IO uint32_t OSC_CONFIG0;
52388 __IO uint32_t OSC_CONFIG0_SET;
52389 __IO uint32_t OSC_CONFIG0_CLR;
52390 __IO uint32_t OSC_CONFIG0_TOG;
52391 __IO uint32_t OSC_CONFIG1;
52392 __IO uint32_t OSC_CONFIG1_SET;
52393 __IO uint32_t OSC_CONFIG1_CLR;
52394 __IO uint32_t OSC_CONFIG1_TOG;
52395 __IO uint32_t OSC_CONFIG2;
52396 __IO uint32_t OSC_CONFIG2_SET;
52397 __IO uint32_t OSC_CONFIG2_CLR;
52398 __IO uint32_t OSC_CONFIG2_TOG;
52399} XTALOSC24M_Type;
52400
52401/* ----------------------------------------------------------------------------
52402 -- XTALOSC24M Register Masks
52403 ---------------------------------------------------------------------------- */
52404
52413#define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)
52414#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)
52415#define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)
52416
52417#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
52418#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
52423#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)
52424
52425#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)
52426#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)
52437#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)
52438
52439#define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)
52440#define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)
52441#define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)
52442
52443#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
52444#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
52451#define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)
52452
52453#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
52454#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
52459#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)
52460
52461#define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)
52462#define XTALOSC24M_MISC0_OSC_I_SHIFT (13U)
52469#define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)
52470
52471#define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)
52472#define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)
52473#define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)
52474
52475#define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
52476#define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)
52477#define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)
52478
52479#define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
52480#define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)
52485#define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)
52486
52487#define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
52488#define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)
52499#define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)
52500
52501#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
52502#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
52507#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)
52508
52509#define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
52510#define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)
52511#define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)
52512
52513#define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
52514#define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)
52519#define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)
52525#define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)
52526#define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)
52527#define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)
52528
52529#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
52530#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
52535#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
52536
52537#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
52538#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
52549#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)
52550
52551#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
52552#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
52553#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)
52554
52555#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
52556#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
52563#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)
52564
52565#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
52566#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
52571#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)
52572
52573#define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)
52574#define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)
52581#define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)
52582
52583#define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
52584#define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)
52585#define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)
52586
52587#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
52588#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
52589#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)
52590
52591#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
52592#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
52597#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)
52598
52599#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
52600#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
52611#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)
52612
52613#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
52614#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
52619#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)
52620
52621#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
52622#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
52623#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)
52624
52625#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
52626#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
52631#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)
52637#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
52638#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
52639#define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)
52640
52641#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
52642#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
52647#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
52648
52649#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
52650#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
52661#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)
52662
52663#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
52664#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
52665#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)
52666
52667#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
52668#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
52675#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)
52676
52677#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
52678#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
52683#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
52684
52685#define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)
52686#define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)
52693#define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)
52694
52695#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
52696#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
52697#define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)
52698
52699#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
52700#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
52701#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)
52702
52703#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
52704#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
52709#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)
52710
52711#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
52712#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
52723#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)
52724
52725#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
52726#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
52731#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
52732
52733#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
52734#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
52735#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)
52736
52737#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
52738#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
52743#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)
52749#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
52750#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
52751#define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)
52752
52753#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
52754#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
52759#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
52760
52761#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
52762#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
52773#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)
52774
52775#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
52776#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
52777#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)
52778
52779#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
52780#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
52787#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)
52788
52789#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
52790#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
52795#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
52796
52797#define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)
52798#define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)
52805#define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)
52806
52807#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
52808#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
52809#define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)
52810
52811#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
52812#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
52813#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)
52814
52815#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
52816#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
52821#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)
52822
52823#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
52824#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
52835#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)
52836
52837#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
52838#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
52843#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
52844
52845#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
52846#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
52847#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)
52848
52849#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
52850#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
52855#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)
52861#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)
52862#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)
52867#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)
52868
52869#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)
52870#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)
52875#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)
52876
52877#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)
52878#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)
52883#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
52884
52885#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)
52886#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)
52887#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)
52888
52889#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)
52890#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)
52891#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)
52892
52893#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)
52894#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)
52895#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)
52896
52897#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)
52898#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)
52899#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)
52900
52901#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)
52902#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)
52903#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)
52904
52905#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)
52906#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)
52907#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)
52908
52909#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)
52910#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)
52911#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)
52912
52913#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
52914#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)
52921#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)
52922
52923#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)
52924#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)
52929#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)
52930
52931#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)
52932#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)
52933#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)
52934
52935#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)
52936#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)
52937#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)
52943#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)
52944#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)
52949#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)
52950
52951#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)
52952#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)
52957#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)
52958
52959#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)
52960#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)
52965#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)
52966
52967#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)
52968#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)
52969#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)
52970
52971#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)
52972#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)
52973#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)
52974
52975#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)
52976#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)
52977#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)
52978
52979#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)
52980#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)
52981#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)
52982
52983#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)
52984#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)
52985#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
52986
52987#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)
52988#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)
52989#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)
52990
52991#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)
52992#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)
52993#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)
52994
52995#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
52996#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)
53003#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
53004
53005#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)
53006#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)
53011#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)
53012
53013#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)
53014#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)
53015#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)
53016
53017#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)
53018#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)
53019#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)
53025#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)
53026#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)
53031#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)
53032
53033#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)
53034#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)
53039#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)
53040
53041#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)
53042#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)
53047#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)
53048
53049#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)
53050#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)
53051#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)
53052
53053#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)
53054#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)
53055#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)
53056
53057#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)
53058#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)
53059#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)
53060
53061#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)
53062#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)
53063#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)
53064
53065#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)
53066#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)
53067#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
53068
53069#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)
53070#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)
53071#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)
53072
53073#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)
53074#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)
53075#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)
53076
53077#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
53078#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)
53085#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
53086
53087#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)
53088#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)
53093#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)
53094
53095#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)
53096#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)
53097#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)
53098
53099#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)
53100#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)
53101#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)
53107#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)
53108#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)
53113#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)
53114
53115#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)
53116#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)
53121#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)
53122
53123#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)
53124#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)
53129#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)
53130
53131#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)
53132#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)
53133#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)
53134
53135#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)
53136#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)
53137#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)
53138
53139#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)
53140#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)
53141#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)
53142
53143#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)
53144#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)
53145#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)
53146
53147#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)
53148#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)
53149#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)
53150
53151#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)
53152#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)
53153#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)
53154
53155#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)
53156#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)
53157#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)
53158
53159#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
53160#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)
53167#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
53168
53169#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)
53170#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)
53175#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)
53176
53177#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)
53178#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)
53179#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)
53180
53181#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)
53182#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)
53183#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)
53189#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)
53190#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)
53191#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)
53192
53193#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)
53194#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)
53195#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)
53196
53197#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)
53198#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)
53199#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)
53200
53201#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)
53202#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)
53203#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)
53204
53205#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)
53206#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)
53207#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)
53208
53209#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)
53210#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)
53211#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)
53212
53213#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)
53214#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)
53215#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)
53216
53217#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)
53218#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)
53219#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)
53225#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)
53226#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)
53227#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)
53228
53229#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)
53230#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)
53231#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)
53232
53233#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)
53234#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)
53235#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)
53236
53237#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)
53238#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)
53239#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)
53240
53241#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)
53242#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)
53243#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)
53244
53245#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)
53246#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)
53247#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)
53248
53249#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)
53250#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)
53251#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)
53252
53253#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)
53254#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)
53255#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)
53261#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)
53262#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)
53263#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)
53264
53265#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)
53266#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)
53267#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)
53268
53269#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)
53270#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)
53271#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)
53272
53273#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)
53274#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)
53275#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)
53276
53277#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)
53278#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)
53279#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)
53280
53281#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)
53282#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)
53283#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)
53284
53285#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)
53286#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)
53287#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)
53288
53289#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)
53290#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)
53291#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)
53297#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)
53298#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)
53299#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)
53300
53301#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)
53302#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)
53303#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)
53304
53305#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)
53306#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)
53307#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)
53308
53309#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)
53310#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)
53311#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)
53312
53313#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)
53314#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)
53315#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)
53316
53317#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)
53318#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)
53319#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)
53320
53321#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)
53322#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)
53323#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)
53324
53325#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)
53326#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)
53327#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)
53333#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)
53334#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)
53335#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)
53336
53337#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)
53338#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)
53339#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)
53345#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)
53346#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)
53347#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)
53348
53349#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)
53350#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)
53351#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)
53357#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)
53358#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)
53359#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)
53360
53361#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)
53362#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)
53363#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)
53369#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)
53370#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)
53371#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)
53372
53373#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)
53374#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)
53375#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)
53381#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)
53382#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)
53383#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)
53384
53385#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)
53386#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)
53387#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
53388
53389#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)
53390#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)
53391#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)
53392
53393#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)
53394#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)
53395#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)
53401#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)
53402#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)
53403#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)
53404
53405#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)
53406#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)
53407#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)
53408
53409#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)
53410#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)
53411#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)
53412
53413#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)
53414#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)
53415#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)
53421#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)
53422#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)
53423#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)
53424
53425#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)
53426#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)
53427#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)
53428
53429#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)
53430#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)
53431#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)
53432
53433#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)
53434#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)
53435#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)
53441#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)
53442#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)
53443#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)
53444
53445#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)
53446#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)
53447#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)
53448
53449#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)
53450#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)
53451#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)
53452
53453#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)
53454#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)
53455#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) /* end of group XTALOSC24M_Register_Masks */
53462
53463
53464/* XTALOSC24M - Peripheral instance base addresses */
53466#define XTALOSC24M_BASE (0x400D8000u)
53468#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)
53470#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }
53472#define XTALOSC24M_BASE_PTRS { XTALOSC24M }
53473 /* end of group XTALOSC24M_Peripheral_Access_Layer */
53477
53478
53479/*
53480** End of section using anonymous unions
53481*/
53482
53483#if defined(__ARMCC_VERSION)
53484 #if (__ARMCC_VERSION >= 6010050)
53485 #pragma clang diagnostic pop
53486 #else
53487 #pragma pop
53488 #endif
53489#elif defined(__CWCC__)
53490 #pragma pop
53491#elif defined(__GNUC__)
53492 /* leave anonymous unions enabled */
53493#elif defined(__IAR_SYSTEMS_ICC__)
53494 #pragma language=default
53495#else
53496 #error Not supported compiler type
53497#endif
53498 /* end of group Peripheral_access_layer */
53502
53503
53504/* ----------------------------------------------------------------------------
53505 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
53506 ---------------------------------------------------------------------------- */
53507
53513#if defined(__ARMCC_VERSION)
53514 #if (__ARMCC_VERSION >= 6010050)
53515 #pragma clang system_header
53516 #endif
53517#elif defined(__IAR_SYSTEMS_ICC__)
53518 #pragma system_include
53519#endif
53520
53527#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
53534#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
53535 /* end of group Bit_Field_Generic_Macros */
53539
53540
53541/* ----------------------------------------------------------------------------
53542 -- SDK Compatibility
53543 ---------------------------------------------------------------------------- */
53544
53550/* No SDK compatibility issues. */
53551 /* end of group SDK_Compatibility_Symbols */
53555
53556
53557#endif /* _MIMXRT1052_H_ */
53558
__O
#define __O
Definition: core_cm4.h:238
__IO
#define __IO
Definition: core_cm4.h:239
__I
#define __I
Definition: core_cm4.h:236
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
PWM2_2_IRQn
@ PWM2_2_IRQn
Definition: MIMXRT1052.h:235
PendSV_IRQn
@ PendSV_IRQn
Definition: MIMXRT1052.h:92
LPI2C1_IRQn
@ LPI2C1_IRQn
Definition: MIMXRT1052.h:124
PWM1_0_IRQn
@ PWM1_0_IRQn
Definition: MIMXRT1052.h:198
SJC_IRQn
@ SJC_IRQn
Definition: MIMXRT1052.h:150
GPIO4_Combined_16_31_IRQn
@ GPIO4_Combined_16_31_IRQn
Definition: MIMXRT1052.h:183
ADC_ETC_ERROR_IRQ_IRQn
@ ADC_ETC_ERROR_IRQ_IRQn
Definition: MIMXRT1052.h:217
TSC_DIG_IRQn
@ TSC_DIG_IRQn
Definition: MIMXRT1052.h:136
GPIO3_Combined_0_15_IRQn
@ GPIO3_Combined_0_15_IRQn
Definition: MIMXRT1052.h:180
DMA0_DMA16_IRQn
@ DMA0_DMA16_IRQn
Definition: MIMXRT1052.h:96
GPIO1_INT0_IRQn
@ GPIO1_INT0_IRQn
Definition: MIMXRT1052.h:168
DMA14_DMA30_IRQn
@ DMA14_DMA30_IRQn
Definition: MIMXRT1052.h:110
PMU_EVENT_IRQn
@ PMU_EVENT_IRQn
Definition: MIMXRT1052.h:157
NotAvail_IRQn
@ NotAvail_IRQn
Definition: MIMXRT1052.h:82
DMA13_DMA29_IRQn
@ DMA13_DMA29_IRQn
Definition: MIMXRT1052.h:109
USDHC1_IRQn
@ USDHC1_IRQn
Definition: MIMXRT1052.h:206
CORE_IRQn
@ CORE_IRQn
Definition: MIMXRT1052.h:115
SNVS_HP_WRAPPER_TZ_IRQn
@ SNVS_HP_WRAPPER_TZ_IRQn
Definition: MIMXRT1052.h:143
KPP_IRQn
@ KPP_IRQn
Definition: MIMXRT1052.h:135
GPIO1_INT2_IRQn
@ GPIO1_INT2_IRQn
Definition: MIMXRT1052.h:170
PWM4_2_IRQn
@ PWM4_2_IRQn
Definition: MIMXRT1052.h:245
SEMC_IRQn
@ SEMC_IRQn
Definition: MIMXRT1052.h:205
FLEXIO2_IRQn
@ FLEXIO2_IRQn
Definition: MIMXRT1052.h:187
ACMP3_IRQn
@ ACMP3_IRQn
Definition: MIMXRT1052.h:221
SNVS_LP_WRAPPER_IRQn
@ SNVS_LP_WRAPPER_IRQn
Definition: MIMXRT1052.h:144
FLEXSPI_IRQn
@ FLEXSPI_IRQn
Definition: MIMXRT1052.h:204
PWM2_1_IRQn
@ PWM2_1_IRQn
Definition: MIMXRT1052.h:234
CCM_2_IRQn
@ CCM_2_IRQn
Definition: MIMXRT1052.h:192
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: MIMXRT1052.h:87
GPIO5_Combined_0_15_IRQn
@ GPIO5_Combined_0_15_IRQn
Definition: MIMXRT1052.h:184
ADC1_IRQn
@ ADC1_IRQn
Definition: MIMXRT1052.h:163
SAI1_IRQn
@ SAI1_IRQn
Definition: MIMXRT1052.h:152
LPUART2_IRQn
@ LPUART2_IRQn
Definition: MIMXRT1052.h:117
GPT1_IRQn
@ GPT1_IRQn
Definition: MIMXRT1052.h:196
USB_PHY2_IRQn
@ USB_PHY2_IRQn
Definition: MIMXRT1052.h:162
LPI2C4_IRQn
@ LPI2C4_IRQn
Definition: MIMXRT1052.h:127
DMA15_DMA31_IRQn
@ DMA15_DMA31_IRQn
Definition: MIMXRT1052.h:111
ACMP1_IRQn
@ ACMP1_IRQn
Definition: MIMXRT1052.h:219
TMR4_IRQn
@ TMR4_IRQn
Definition: MIMXRT1052.h:232
PWM1_1_IRQn
@ PWM1_1_IRQn
Definition: MIMXRT1052.h:199
GPIO1_INT4_IRQn
@ GPIO1_INT4_IRQn
Definition: MIMXRT1052.h:172
Reserved68_IRQn
@ Reserved68_IRQn
Definition: MIMXRT1052.h:148
PWM2_3_IRQn
@ PWM2_3_IRQn
Definition: MIMXRT1052.h:236
RTWDOG_IRQn
@ RTWDOG_IRQn
Definition: MIMXRT1052.h:189
CTI0_ERROR_IRQn
@ CTI0_ERROR_IRQn
Definition: MIMXRT1052.h:113
Reserved78_IRQn
@ Reserved78_IRQn
Definition: MIMXRT1052.h:158
GPIO1_INT1_IRQn
@ GPIO1_INT1_IRQn
Definition: MIMXRT1052.h:169
PWM1_FAULT_IRQn
@ PWM1_FAULT_IRQn
Definition: MIMXRT1052.h:202
PWM4_0_IRQn
@ PWM4_0_IRQn
Definition: MIMXRT1052.h:243
PWM4_1_IRQn
@ PWM4_1_IRQn
Definition: MIMXRT1052.h:244
USB_PHY1_IRQn
@ USB_PHY1_IRQn
Definition: MIMXRT1052.h:161
SVCall_IRQn
@ SVCall_IRQn
Definition: MIMXRT1052.h:90
DMA_ERROR_IRQn
@ DMA_ERROR_IRQn
Definition: MIMXRT1052.h:112
DMA10_DMA26_IRQn
@ DMA10_DMA26_IRQn
Definition: MIMXRT1052.h:106
BEE_IRQn
@ BEE_IRQn
Definition: MIMXRT1052.h:151
TEMP_PANIC_IRQn
@ TEMP_PANIC_IRQn
Definition: MIMXRT1052.h:160
LPUART7_IRQn
@ LPUART7_IRQn
Definition: MIMXRT1052.h:122
SAI3_RX_IRQn
@ SAI3_RX_IRQn
Definition: MIMXRT1052.h:154
DMA5_DMA21_IRQn
@ DMA5_DMA21_IRQn
Definition: MIMXRT1052.h:101
CCM_1_IRQn
@ CCM_1_IRQn
Definition: MIMXRT1052.h:191
GPIO1_INT3_IRQn
@ GPIO1_INT3_IRQn
Definition: MIMXRT1052.h:171
LPI2C3_IRQn
@ LPI2C3_IRQn
Definition: MIMXRT1052.h:126
GPIO2_Combined_0_15_IRQn
@ GPIO2_Combined_0_15_IRQn
Definition: MIMXRT1052.h:178
ENC3_IRQn
@ ENC3_IRQn
Definition: MIMXRT1052.h:227
PWM3_0_IRQn
@ PWM3_0_IRQn
Definition: MIMXRT1052.h:238
USB_OTG1_IRQn
@ USB_OTG1_IRQn
Definition: MIMXRT1052.h:209
DMA3_DMA19_IRQn
@ DMA3_DMA19_IRQn
Definition: MIMXRT1052.h:99
USDHC2_IRQn
@ USDHC2_IRQn
Definition: MIMXRT1052.h:207
UsageFault_IRQn
@ UsageFault_IRQn
Definition: MIMXRT1052.h:89
XBAR1_IRQ_2_3_IRQn
@ XBAR1_IRQ_2_3_IRQn
Definition: MIMXRT1052.h:213
LPUART5_IRQn
@ LPUART5_IRQn
Definition: MIMXRT1052.h:120
GPC_IRQn
@ GPC_IRQn
Definition: MIMXRT1052.h:193
Reserved115_IRQn
@ Reserved115_IRQn
Definition: MIMXRT1052.h:195
DCP_IRQn
@ DCP_IRQn
Definition: MIMXRT1052.h:146
SysTick_IRQn
@ SysTick_IRQn
Definition: MIMXRT1052.h:93
Reserved144_IRQn
@ Reserved144_IRQn
Definition: MIMXRT1052.h:224
CSI_IRQn
@ CSI_IRQn
Definition: MIMXRT1052.h:139
DMA4_DMA20_IRQn
@ DMA4_DMA20_IRQn
Definition: MIMXRT1052.h:100
LPSPI3_IRQn
@ LPSPI3_IRQn
Definition: MIMXRT1052.h:130
TEMP_LOW_HIGH_IRQn
@ TEMP_LOW_HIGH_IRQn
Definition: MIMXRT1052.h:159
Reserved143_IRQn
@ Reserved143_IRQn
Definition: MIMXRT1052.h:223
CAN1_IRQn
@ CAN1_IRQn
Definition: MIMXRT1052.h:132
LCDIF_IRQn
@ LCDIF_IRQn
Definition: MIMXRT1052.h:138
LPUART4_IRQn
@ LPUART4_IRQn
Definition: MIMXRT1052.h:119
CTI1_ERROR_IRQn
@ CTI1_ERROR_IRQn
Definition: MIMXRT1052.h:114
GPIO1_INT6_IRQn
@ GPIO1_INT6_IRQn
Definition: MIMXRT1052.h:174
TMR1_IRQn
@ TMR1_IRQn
Definition: MIMXRT1052.h:229
BusFault_IRQn
@ BusFault_IRQn
Definition: MIMXRT1052.h:88
PWM4_3_IRQn
@ PWM4_3_IRQn
Definition: MIMXRT1052.h:246
ADC_ETC_IRQ2_IRQn
@ ADC_ETC_IRQ2_IRQn
Definition: MIMXRT1052.h:216
Reserved87_IRQn
@ Reserved87_IRQn
Definition: MIMXRT1052.h:167
CSU_IRQn
@ CSU_IRQn
Definition: MIMXRT1052.h:145
LPUART8_IRQn
@ LPUART8_IRQn
Definition: MIMXRT1052.h:123
ACMP2_IRQn
@ ACMP2_IRQn
Definition: MIMXRT1052.h:220
DMA7_DMA23_IRQn
@ DMA7_DMA23_IRQn
Definition: MIMXRT1052.h:103
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: MIMXRT1052.h:91
ADC2_IRQn
@ ADC2_IRQn
Definition: MIMXRT1052.h:164
TMR2_IRQn
@ TMR2_IRQn
Definition: MIMXRT1052.h:230
SRC_IRQn
@ SRC_IRQn
Definition: MIMXRT1052.h:194
LPI2C2_IRQn
@ LPI2C2_IRQn
Definition: MIMXRT1052.h:125
ADC_ETC_IRQ0_IRQn
@ ADC_ETC_IRQ0_IRQn
Definition: MIMXRT1052.h:214
EWM_IRQn
@ EWM_IRQn
Definition: MIMXRT1052.h:190
GPR_IRQ_IRQn
@ GPR_IRQ_IRQn
Definition: MIMXRT1052.h:137
DMA8_DMA24_IRQn
@ DMA8_DMA24_IRQn
Definition: MIMXRT1052.h:104
GPIO4_Combined_0_15_IRQn
@ GPIO4_Combined_0_15_IRQn
Definition: MIMXRT1052.h:182
Reserved86_IRQn
@ Reserved86_IRQn
Definition: MIMXRT1052.h:166
PWM3_3_IRQn
@ PWM3_3_IRQn
Definition: MIMXRT1052.h:241
DMA6_DMA22_IRQn
@ DMA6_DMA22_IRQn
Definition: MIMXRT1052.h:102
ADC_ETC_IRQ1_IRQn
@ ADC_ETC_IRQ1_IRQn
Definition: MIMXRT1052.h:215
WDOG2_IRQn
@ WDOG2_IRQn
Definition: MIMXRT1052.h:141
PWM2_0_IRQn
@ PWM2_0_IRQn
Definition: MIMXRT1052.h:233
XBAR1_IRQ_0_1_IRQn
@ XBAR1_IRQ_0_1_IRQn
Definition: MIMXRT1052.h:212
HardFault_IRQn
@ HardFault_IRQn
Definition: MIMXRT1052.h:86
ENC2_IRQn
@ ENC2_IRQn
Definition: MIMXRT1052.h:226
DCDC_IRQn
@ DCDC_IRQn
Definition: MIMXRT1052.h:165
TRNG_IRQn
@ TRNG_IRQn
Definition: MIMXRT1052.h:149
ACMP4_IRQn
@ ACMP4_IRQn
Definition: MIMXRT1052.h:222
WDOG1_IRQn
@ WDOG1_IRQn
Definition: MIMXRT1052.h:188
USB_OTG2_IRQn
@ USB_OTG2_IRQn
Definition: MIMXRT1052.h:208
PWM1_2_IRQn
@ PWM1_2_IRQn
Definition: MIMXRT1052.h:200
ENET_1588_Timer_IRQn
@ ENET_1588_Timer_IRQn
Definition: MIMXRT1052.h:211
FLEXRAM_IRQn
@ FLEXRAM_IRQn
Definition: MIMXRT1052.h:134
LPSPI1_IRQn
@ LPSPI1_IRQn
Definition: MIMXRT1052.h:128
SAI2_IRQn
@ SAI2_IRQn
Definition: MIMXRT1052.h:153
PIT_IRQn
@ PIT_IRQn
Definition: MIMXRT1052.h:218
DMA11_DMA27_IRQn
@ DMA11_DMA27_IRQn
Definition: MIMXRT1052.h:107
GPIO5_Combined_16_31_IRQn
@ GPIO5_Combined_16_31_IRQn
Definition: MIMXRT1052.h:185
SAI3_TX_IRQn
@ SAI3_TX_IRQn
Definition: MIMXRT1052.h:155
LPUART3_IRQn
@ LPUART3_IRQn
Definition: MIMXRT1052.h:118
GPT2_IRQn
@ GPT2_IRQn
Definition: MIMXRT1052.h:197
CAN2_IRQn
@ CAN2_IRQn
Definition: MIMXRT1052.h:133
FLEXIO1_IRQn
@ FLEXIO1_IRQn
Definition: MIMXRT1052.h:186
PWM3_FAULT_IRQn
@ PWM3_FAULT_IRQn
Definition: MIMXRT1052.h:242
ENC1_IRQn
@ ENC1_IRQn
Definition: MIMXRT1052.h:225
DMA2_DMA18_IRQn
@ DMA2_DMA18_IRQn
Definition: MIMXRT1052.h:98
PXP_IRQn
@ PXP_IRQn
Definition: MIMXRT1052.h:140
GPIO2_Combined_16_31_IRQn
@ GPIO2_Combined_16_31_IRQn
Definition: MIMXRT1052.h:179
GPIO1_INT7_IRQn
@ GPIO1_INT7_IRQn
Definition: MIMXRT1052.h:175
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: MIMXRT1052.h:85
TMR3_IRQn
@ TMR3_IRQn
Definition: MIMXRT1052.h:231
GPIO3_Combined_16_31_IRQn
@ GPIO3_Combined_16_31_IRQn
Definition: MIMXRT1052.h:181
LPSPI2_IRQn
@ LPSPI2_IRQn
Definition: MIMXRT1052.h:129
PWM3_1_IRQn
@ PWM3_1_IRQn
Definition: MIMXRT1052.h:239
PWM4_FAULT_IRQn
@ PWM4_FAULT_IRQn
Definition: MIMXRT1052.h:247
Reserved123_IRQn
@ Reserved123_IRQn
Definition: MIMXRT1052.h:203
ENC4_IRQn
@ ENC4_IRQn
Definition: MIMXRT1052.h:228
PWM1_3_IRQn
@ PWM1_3_IRQn
Definition: MIMXRT1052.h:201
LPUART6_IRQn
@ LPUART6_IRQn
Definition: MIMXRT1052.h:121
GPIO1_INT5_IRQn
@ GPIO1_INT5_IRQn
Definition: MIMXRT1052.h:173
SNVS_HP_WRAPPER_IRQn
@ SNVS_HP_WRAPPER_IRQn
Definition: MIMXRT1052.h:142
DMA9_DMA25_IRQn
@ DMA9_DMA25_IRQn
Definition: MIMXRT1052.h:105
SPDIF_IRQn
@ SPDIF_IRQn
Definition: MIMXRT1052.h:156
ENET_IRQn
@ ENET_IRQn
Definition: MIMXRT1052.h:210
DMA12_DMA28_IRQn
@ DMA12_DMA28_IRQn
Definition: MIMXRT1052.h:108
LPSPI4_IRQn
@ LPSPI4_IRQn
Definition: MIMXRT1052.h:131
LPUART1_IRQn
@ LPUART1_IRQn
Definition: MIMXRT1052.h:116
GPIO1_Combined_0_15_IRQn
@ GPIO1_Combined_0_15_IRQn
Definition: MIMXRT1052.h:176
PWM2_FAULT_IRQn
@ PWM2_FAULT_IRQn
Definition: MIMXRT1052.h:237
DCP_VMI_IRQn
@ DCP_VMI_IRQn
Definition: MIMXRT1052.h:147
PWM3_2_IRQn
@ PWM3_2_IRQn
Definition: MIMXRT1052.h:240
DMA1_DMA17_IRQn
@ DMA1_DMA17_IRQn
Definition: MIMXRT1052.h:97
GPIO1_Combined_16_31_IRQn
@ GPIO1_Combined_16_31_IRQn
Definition: MIMXRT1052.h:177
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h723xx.h:49
dma_request_source_t
enum _dma_request_source dma_request_source_t
Structure for the DMA hardware request.
_dma_request_source
_dma_request_source
Structure for the DMA hardware request.
Definition: MIMXRT1052.h:1131
kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1
@ kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1052.h:1185
kDmaRequestMuxSai3Rx
@ kDmaRequestMuxSai3Rx
Definition: MIMXRT1052.h:1207
kDmaRequestMuxFlexPWM3CaptureSub0
@ kDmaRequestMuxFlexPWM3CaptureSub0
Definition: MIMXRT1052.h:1169
kDmaRequestMuxFlexPWM4ValueSub1
@ kDmaRequestMuxFlexPWM4ValueSub1
Definition: MIMXRT1052.h:1231
kDmaRequestMuxFlexPWM1ValueSub0
@ kDmaRequestMuxFlexPWM1ValueSub0
Definition: MIMXRT1052.h:1165
kDmaRequestMuxLPUART3Rx
@ kDmaRequestMuxLPUART3Rx
Definition: MIMXRT1052.h:1137
kDmaRequestMuxLPUART7Rx
@ kDmaRequestMuxLPUART7Rx
Definition: MIMXRT1052.h:1141
kDmaRequestMuxFlexPWM1CaptureSub0
@ kDmaRequestMuxFlexPWM1CaptureSub0
Definition: MIMXRT1052.h:1161
kDmaRequestMuxFlexPWM3ValueSub3
@ kDmaRequestMuxFlexPWM3ValueSub3
Definition: MIMXRT1052.h:1176
kDmaRequestMuxFlexPWM3CaptureSub2
@ kDmaRequestMuxFlexPWM3CaptureSub2
Definition: MIMXRT1052.h:1171
kDmaRequestMuxLPSPI3Rx
@ kDmaRequestMuxLPSPI3Rx
Definition: MIMXRT1052.h:1145
kDmaRequestMuxFlexPWM3CaptureSub3
@ kDmaRequestMuxFlexPWM3CaptureSub3
Definition: MIMXRT1052.h:1172
kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0
@ kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1052.h:1182
kDmaRequestMuxLPI2C1
@ kDmaRequestMuxLPI2C1
Definition: MIMXRT1052.h:1147
kDmaRequestMuxLPUART5Tx
@ kDmaRequestMuxLPUART5Tx
Definition: MIMXRT1052.h:1138
kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2
@ kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1052.h:1245
kDmaRequestMuxLPUART8Rx
@ kDmaRequestMuxLPUART8Rx
Definition: MIMXRT1052.h:1198
kDmaRequestMuxACMP2
@ kDmaRequestMuxACMP2
Definition: MIMXRT1052.h:1212
kDmaRequestMuxFlexPWM2CaptureSub1
@ kDmaRequestMuxFlexPWM2CaptureSub1
Definition: MIMXRT1052.h:1219
kDmaRequestMuxFlexPWM1ValueSub3
@ kDmaRequestMuxFlexPWM1ValueSub3
Definition: MIMXRT1052.h:1168
kDmaRequestMuxFlexPWM1ValueSub1
@ kDmaRequestMuxFlexPWM1ValueSub1
Definition: MIMXRT1052.h:1166
kDmaRequestMuxLPSPI4Rx
@ kDmaRequestMuxLPSPI4Rx
Definition: MIMXRT1052.h:1203
kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2
@ kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1052.h:1241
kDmaRequestMuxXBAR1Request1
@ kDmaRequestMuxXBAR1Request1
Definition: MIMXRT1052.h:1160
kDmaRequestMuxQTIMER1CaptTimer0
@ kDmaRequestMuxQTIMER1CaptTimer0
Definition: MIMXRT1052.h:1177
kDmaRequestMuxFlexIO1Request2Request3
@ kDmaRequestMuxFlexIO1Request2Request3
Definition: MIMXRT1052.h:1189
kDmaRequestMuxSai1Rx
@ kDmaRequestMuxSai1Rx
Definition: MIMXRT1052.h:1149
kDmaRequestMuxLPUART2Tx
@ kDmaRequestMuxLPUART2Tx
Definition: MIMXRT1052.h:1191
kDmaRequestMuxADC1
@ kDmaRequestMuxADC1
Definition: MIMXRT1052.h:1154
kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0
@ kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1052.h:1239
kDmaRequestMuxQTIMER1CaptTimer2
@ kDmaRequestMuxQTIMER1CaptTimer2
Definition: MIMXRT1052.h:1179
kDmaRequestMuxQTIMER2CaptTimer1
@ kDmaRequestMuxQTIMER2CaptTimer1
Definition: MIMXRT1052.h:1235
kDmaRequestMuxSai2Tx
@ kDmaRequestMuxSai2Tx
Definition: MIMXRT1052.h:1152
kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3
@ kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1052.h:1187
kDmaRequestMuxQTIMER1CaptTimer3
@ kDmaRequestMuxQTIMER1CaptTimer3
Definition: MIMXRT1052.h:1180
kDmaRequestMuxSpdifRx
@ kDmaRequestMuxSpdifRx
Definition: MIMXRT1052.h:1209
kDmaRequestMuxACMP1
@ kDmaRequestMuxACMP1
Definition: MIMXRT1052.h:1155
kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1
@ kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1052.h:1181
kDmaRequestMuxLPUART3Tx
@ kDmaRequestMuxLPUART3Tx
Definition: MIMXRT1052.h:1136
kDmaRequestMuxFlexPWM2CaptureSub3
@ kDmaRequestMuxFlexPWM2CaptureSub3
Definition: MIMXRT1052.h:1221
kDmaRequestMuxQTIMER2CaptTimer3
@ kDmaRequestMuxQTIMER2CaptTimer3
Definition: MIMXRT1052.h:1237
kDmaRequestMuxLPSPI1Rx
@ kDmaRequestMuxLPSPI1Rx
Definition: MIMXRT1052.h:1143
kDmaRequestMuxLPUART1Rx
@ kDmaRequestMuxLPUART1Rx
Definition: MIMXRT1052.h:1135
kDmaRequestMuxFlexIO1Request0Request1
@ kDmaRequestMuxFlexIO1Request0Request1
Definition: MIMXRT1052.h:1132
kDmaRequestMuxQTIMER1CaptTimer1
@ kDmaRequestMuxQTIMER1CaptTimer1
Definition: MIMXRT1052.h:1178
kDmaRequestMuxFlexPWM3ValueSub2
@ kDmaRequestMuxFlexPWM3ValueSub2
Definition: MIMXRT1052.h:1175
kDmaRequestMuxXBAR1Request0
@ kDmaRequestMuxXBAR1Request0
Definition: MIMXRT1052.h:1159
kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3
@ kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1052.h:1240
kDmaRequestMuxXBAR1Request3
@ kDmaRequestMuxXBAR1Request3
Definition: MIMXRT1052.h:1217
kDmaRequestMuxEnetTimer0
@ kDmaRequestMuxEnetTimer0
Definition: MIMXRT1052.h:1214
kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2
@ kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1052.h:1184
kDmaRequestMuxLPUART2Rx
@ kDmaRequestMuxLPUART2Rx
Definition: MIMXRT1052.h:1192
kDmaRequestMuxLPSPI2Rx
@ kDmaRequestMuxLPSPI2Rx
Definition: MIMXRT1052.h:1201
kDmaRequestMuxFlexIO2Request0Request1
@ kDmaRequestMuxFlexIO2Request0Request1
Definition: MIMXRT1052.h:1133
kDmaRequestMuxFlexPWM4CaptureSub0
@ kDmaRequestMuxFlexPWM4CaptureSub0
Definition: MIMXRT1052.h:1226
kDmaRequestMuxLPI2C3
@ kDmaRequestMuxLPI2C3
Definition: MIMXRT1052.h:1148
kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0
@ kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1052.h:1243
kDmaRequestMuxFlexPWM4CaptureSub1
@ kDmaRequestMuxFlexPWM4CaptureSub1
Definition: MIMXRT1052.h:1227
kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3
@ kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1052.h:1244
kDmaRequestMuxCSI
@ kDmaRequestMuxCSI
Definition: MIMXRT1052.h:1142
kDmaRequestMuxFlexPWM2ValueSub0
@ kDmaRequestMuxFlexPWM2ValueSub0
Definition: MIMXRT1052.h:1222
kDmaRequestMuxLPUART5Rx
@ kDmaRequestMuxLPUART5Rx
Definition: MIMXRT1052.h:1139
kDmaRequestMuxLPUART1Tx
@ kDmaRequestMuxLPUART1Tx
Definition: MIMXRT1052.h:1134
kDmaRequestMuxLPUART4Rx
@ kDmaRequestMuxLPUART4Rx
Definition: MIMXRT1052.h:1194
kDmaRequestMuxSai1Tx
@ kDmaRequestMuxSai1Tx
Definition: MIMXRT1052.h:1150
kDmaRequestMuxADC2
@ kDmaRequestMuxADC2
Definition: MIMXRT1052.h:1211
kDmaRequestMuxFlexPWM4ValueSub3
@ kDmaRequestMuxFlexPWM4ValueSub3
Definition: MIMXRT1052.h:1233
kDmaRequestMuxQTIMER2CaptTimer0
@ kDmaRequestMuxQTIMER2CaptTimer0
Definition: MIMXRT1052.h:1234
kDmaRequestMuxFlexPWM4CaptureSub2
@ kDmaRequestMuxFlexPWM4CaptureSub2
Definition: MIMXRT1052.h:1228
kDmaRequestMuxEnetTimer1
@ kDmaRequestMuxEnetTimer1
Definition: MIMXRT1052.h:1215
kDmaRequestMuxFlexPWM4ValueSub0
@ kDmaRequestMuxFlexPWM4ValueSub0
Definition: MIMXRT1052.h:1230
kDmaRequestMuxSpdifTx
@ kDmaRequestMuxSpdifTx
Definition: MIMXRT1052.h:1210
kDmaRequestMuxFlexPWM1CaptureSub2
@ kDmaRequestMuxFlexPWM1CaptureSub2
Definition: MIMXRT1052.h:1163
kDmaRequestMuxLPUART4Tx
@ kDmaRequestMuxLPUART4Tx
Definition: MIMXRT1052.h:1193
kDmaRequestMuxFlexPWM3CaptureSub1
@ kDmaRequestMuxFlexPWM3CaptureSub1
Definition: MIMXRT1052.h:1170
kDmaRequestMuxFlexPWM2ValueSub1
@ kDmaRequestMuxFlexPWM2ValueSub1
Definition: MIMXRT1052.h:1223
kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0
@ kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0
Definition: MIMXRT1052.h:1186
kDmaRequestMuxFlexPWM2CaptureSub2
@ kDmaRequestMuxFlexPWM2CaptureSub2
Definition: MIMXRT1052.h:1220
kDmaRequestMuxFlexPWM4ValueSub2
@ kDmaRequestMuxFlexPWM4ValueSub2
Definition: MIMXRT1052.h:1232
kDmaRequestMuxQTIMER2CaptTimer2
@ kDmaRequestMuxQTIMER2CaptTimer2
Definition: MIMXRT1052.h:1236
kDmaRequestMuxXBAR1Request2
@ kDmaRequestMuxXBAR1Request2
Definition: MIMXRT1052.h:1216
kDmaRequestMuxLPSPI2Tx
@ kDmaRequestMuxLPSPI2Tx
Definition: MIMXRT1052.h:1202
kDmaRequestMuxFlexPWM1ValueSub2
@ kDmaRequestMuxFlexPWM1ValueSub2
Definition: MIMXRT1052.h:1167
kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1
@ kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1052.h:1242
kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1
@ kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1
Definition: MIMXRT1052.h:1238
kDmaRequestMuxPxp
@ kDmaRequestMuxPxp
Definition: MIMXRT1052.h:1199
kDmaRequestMuxLPUART8Tx
@ kDmaRequestMuxLPUART8Tx
Definition: MIMXRT1052.h:1197
kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2
@ kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2
Definition: MIMXRT1052.h:1188
kDmaRequestMuxFlexPWM3ValueSub1
@ kDmaRequestMuxFlexPWM3ValueSub1
Definition: MIMXRT1052.h:1174
kDmaRequestMuxLPUART7Tx
@ kDmaRequestMuxLPUART7Tx
Definition: MIMXRT1052.h:1140
kDmaRequestMuxACMP4
@ kDmaRequestMuxACMP4
Definition: MIMXRT1052.h:1213
kDmaRequestMuxLPSPI1Tx
@ kDmaRequestMuxLPSPI1Tx
Definition: MIMXRT1052.h:1144
kDmaRequestMuxADC_ETC
@ kDmaRequestMuxADC_ETC
Definition: MIMXRT1052.h:1153
kDmaRequestMuxFlexSPIRx
@ kDmaRequestMuxFlexSPIRx
Definition: MIMXRT1052.h:1157
kDmaRequestMuxFlexPWM1CaptureSub1
@ kDmaRequestMuxFlexPWM1CaptureSub1
Definition: MIMXRT1052.h:1162
kDmaRequestMuxLPI2C2
@ kDmaRequestMuxLPI2C2
Definition: MIMXRT1052.h:1205
kDmaRequestMuxSai3Tx
@ kDmaRequestMuxSai3Tx
Definition: MIMXRT1052.h:1208
kDmaRequestMuxFlexIO2Request2Request3
@ kDmaRequestMuxFlexIO2Request2Request3
Definition: MIMXRT1052.h:1190
kDmaRequestMuxFlexPWM1CaptureSub3
@ kDmaRequestMuxFlexPWM1CaptureSub3
Definition: MIMXRT1052.h:1164
kDmaRequestMuxFlexPWM2ValueSub3
@ kDmaRequestMuxFlexPWM2ValueSub3
Definition: MIMXRT1052.h:1225
kDmaRequestMuxFlexPWM3ValueSub0
@ kDmaRequestMuxFlexPWM3ValueSub0
Definition: MIMXRT1052.h:1173
kDmaRequestMuxLPUART6Tx
@ kDmaRequestMuxLPUART6Tx
Definition: MIMXRT1052.h:1195
kDmaRequestMuxLCDIF
@ kDmaRequestMuxLCDIF
Definition: MIMXRT1052.h:1200
kDmaRequestMuxFlexPWM2ValueSub2
@ kDmaRequestMuxFlexPWM2ValueSub2
Definition: MIMXRT1052.h:1224
kDmaRequestMuxLPSPI4Tx
@ kDmaRequestMuxLPSPI4Tx
Definition: MIMXRT1052.h:1204
kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3
@ kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3
Definition: MIMXRT1052.h:1183
kDmaRequestMuxFlexPWM2CaptureSub0
@ kDmaRequestMuxFlexPWM2CaptureSub0
Definition: MIMXRT1052.h:1218
kDmaRequestMuxFlexPWM4CaptureSub3
@ kDmaRequestMuxFlexPWM4CaptureSub3
Definition: MIMXRT1052.h:1229
kDmaRequestMuxSai2Rx
@ kDmaRequestMuxSai2Rx
Definition: MIMXRT1052.h:1151
kDmaRequestMuxFlexSPITx
@ kDmaRequestMuxFlexSPITx
Definition: MIMXRT1052.h:1158
kDmaRequestMuxLPUART6Rx
@ kDmaRequestMuxLPUART6Rx
Definition: MIMXRT1052.h:1196
kDmaRequestMuxLPSPI3Tx
@ kDmaRequestMuxLPSPI3Tx
Definition: MIMXRT1052.h:1146
kDmaRequestMuxACMP3
@ kDmaRequestMuxACMP3
Definition: MIMXRT1052.h:1156
kDmaRequestMuxLPI2C4
@ kDmaRequestMuxLPI2C4
Definition: MIMXRT1052.h:1206
SEMC_Type::DBICR0
__IO uint32_t DBICR0
Definition: MIMXRT1052.h:39763
CCM_Type::CCSR
__IO uint32_t CCSR
Definition: MIMXRT1052.h:5072
TEMPMON_Type::TEMPSENSE0_SET
__IO uint32_t TEMPSENSE0_SET
Definition: MIMXRT1052.h:43107
TRNG_Type::SEC_CFG
__IO uint32_t SEC_CFG
Definition: MIMXRT1052.h:44010
XTALOSC24M_Type::LOWPWR_CTRL_TOG
__IO uint32_t LOWPWR_CTRL_TOG
Definition: MIMXRT1052.h:52385
IOMUXC_SNVS_GPR_Type::GPR1
uint32_t GPR1
Definition: MIMXRT1052.h:27102
ENET_Type::IEEE_R_OCTETS_OK
__I uint32_t IEEE_R_OCTETS_OK
Definition: MIMXRT1052.h:18607
ENET_Type::IEEE_T_DEF
__I uint32_t IEEE_T_DEF
Definition: MIMXRT1052.h:18575
LCDIF_Type::PIGEONCTRL1_CLR
__IO uint32_t PIGEONCTRL1_CLR
Definition: MIMXRT1052.h:27408
USBPHY_Type::RX_SET
__IO uint32_t RX_SET
Definition: MIMXRT1052.h:47139
USDHC_Type::SYS_CTRL
__IO uint32_t SYS_CTRL
Definition: MIMXRT1052.h:49072
TRNG_Type::PKRCNT76
__I uint32_t PKRCNT76
Definition: MIMXRT1052.h:44005
PWM_Type::CVAL5
__I uint16_t CVAL5
Definition: MIMXRT1052.h:36033
XBARA_Type::CTRL1
__IO uint16_t CTRL1
Definition: MIMXRT1052.h:51245
LCDIF_Type::CUR_BUF
__IO uint32_t CUR_BUF
Definition: MIMXRT1052.h:27375
ADC_ETC_Type::TRIGn_CHAIN_7_6
__IO uint32_t TRIGn_CHAIN_7_6
Definition: MIMXRT1052.h:1694
ENET_Type::TCCR
__IO uint32_t TCCR
Definition: MIMXRT1052.h:18620
ENET_Type::ECR
__IO uint32_t ECR
Definition: MIMXRT1052.h:18512
PXP_Type::OUT_CTRL_SET
__IO uint32_t OUT_CTRL_SET
Definition: MIMXRT1052.h:37837
DCP_Type::CH0OPTS_TOG
__IO uint32_t CH0OPTS_TOG
Definition: MIMXRT1052.h:12409
SNVS_Type::HPSICR
__IO uint32_t HPSICR
Definition: MIMXRT1052.h:41036
DMA_Type::DCHPRI10
__IO uint8_t DCHPRI10
Definition: MIMXRT1052.h:14391
USBPHY_Type::DEBUG1_CLR
__IO uint32_t DEBUG1_CLR
Definition: MIMXRT1052.h:47156
DCP_Type::KEYDATA
__IO uint32_t KEYDATA
Definition: MIMXRT1052.h:12382
OCOTP_Type::MEM3
__IO uint32_t MEM3
Definition: MIMXRT1052.h:32230
CCM_ANALOG_Type::PLL_USB1_CLR
__IO uint32_t PLL_USB1_CLR
Definition: MIMXRT1052.h:7215
LCDIF_Type::PIGEONCTRL2
__IO uint32_t PIGEONCTRL2
Definition: MIMXRT1052.h:27410
XBARA_Type::SEL34
__IO uint16_t SEL34
Definition: MIMXRT1052.h:51212
TRNG_Type::VID1
__I uint32_t VID1
Definition: MIMXRT1052.h:44015
TRNG_Type::SCMC
__I uint32_t SCMC
Definition: MIMXRT1052.h:43973
BEE_Type::CTR_NONCE1_W3
__O uint32_t CTR_NONCE1_W3
Definition: MIMXRT1052.h:3791
TRNG_Type::SCR5L
__IO uint32_t SCR5L
Definition: MIMXRT1052.h:43994
DCP_Type::CH0OPTS
__IO uint32_t CH0OPTS
Definition: MIMXRT1052.h:12406
XBARA_Type::SEL60
__IO uint16_t SEL60
Definition: MIMXRT1052.h:51238
USB_Type::ENDPTCOMPLETE
__IO uint32_t ENDPTCOMPLETE
Definition: MIMXRT1052.h:45291
AOI_Type::BFCRT01
__IO uint16_t BFCRT01
Definition: MIMXRT1052.h:3552
PWM_Type::OUTEN
__IO uint16_t OUTEN
Definition: MIMXRT1052.h:36037
PXP_Type::PS_CTRL_CLR
__IO uint32_t PS_CTRL_CLR
Definition: MIMXRT1052.h:37858
CCM_ANALOG_Type::PLL_AUDIO_TOG
__IO uint32_t PLL_AUDIO_TOG
Definition: MIMXRT1052.h:7234
ENET_Type::IEEE_R_CRC
__I uint32_t IEEE_R_CRC
Definition: MIMXRT1052.h:18603
PMU_Type::MISC0_SET
__IO uint32_t MISC0_SET
Definition: MIMXRT1052.h:33485
OCOTP_Type::ANA0
__IO uint32_t ANA0
Definition: MIMXRT1052.h:32234
EWM_Type::CLKCTRL
__IO uint8_t CLKCTRL
Definition: MIMXRT1052.h:20387
PGC_Type::CPU_PUPSCR
__IO uint32_t CPU_PUPSCR
Definition: MIMXRT1052.h:33157
IOMUXC_GPR_Type::GPR9
uint32_t GPR9
Definition: MIMXRT1052.h:24410
BEE_Type::ADDR_OFFSET0
__IO uint32_t ADDR_OFFSET0
Definition: MIMXRT1052.h:3777
USDHC_Type::DLL_STATUS
__I uint32_t DLL_STATUS
Definition: MIMXRT1052.h:49086
SPDIF_Type::SIC
__O uint32_t SIC
Definition: MIMXRT1052.h:42282
USBPHY_Type::DEBUG_TOG
__IO uint32_t DEBUG_TOG
Definition: MIMXRT1052.h:47151
CSU_Type::HPCONTROL0
__IO uint32_t HPCONTROL0
Definition: MIMXRT1052.h:11327
ROMC_Type::ROMPATCHENH
uint32_t ROMPATCHENH
Definition: MIMXRT1052.h:39390
USB_ANALOG_Type::VBUS_DETECT
__IO uint32_t VBUS_DETECT
Definition: MIMXRT1052.h:48555
CCM_Type::CACRR
__IO uint32_t CACRR
Definition: MIMXRT1052.h:5073
DCP_Type::CH2STAT_SET
__IO uint32_t CH2STAT_SET
Definition: MIMXRT1052.h:12427
CAN_Type::RXMGMASK
__IO uint32_t RXMGMASK
Definition: MIMXRT1052.h:4127
LPI2C_Type::SDER
__IO uint32_t SDER
Definition: MIMXRT1052.h:29310
LPSPI_Type::CR
__IO uint32_t CR
Definition: MIMXRT1052.h:30461
PWM_Type::DTCNT0
__IO uint16_t DTCNT0
Definition: MIMXRT1052.h:36015
PMU_Type::REG_2P5_TOG
__IO uint32_t REG_2P5_TOG
Definition: MIMXRT1052.h:33479
ENET_Type::RAFL
__IO uint32_t RAFL
Definition: MIMXRT1052.h:18544
USB_Type::ENDPTSETUPSTAT
__IO uint32_t ENDPTSETUPSTAT
Definition: MIMXRT1052.h:45287
GPT_Type::CR
__IO uint32_t CR
Definition: MIMXRT1052.h:22972
ENET_Type::RMON_R_JAB
__I uint32_t RMON_R_JAB
Definition: MIMXRT1052.h:18591
USBPHY_Type::TX
__IO uint32_t TX
Definition: MIMXRT1052.h:47134
CAN_Type::RX15MASK
__IO uint32_t RX15MASK
Definition: MIMXRT1052.h:4129
SEMC_Type::IPCMD
__IO uint32_t IPCMD
Definition: MIMXRT1052.h:39769
TEMPMON_Type::TEMPSENSE1_CLR
__IO uint32_t TEMPSENSE1_CLR
Definition: MIMXRT1052.h:43112
USDHC_Type::DATA_BUFF_ACC_PORT
__IO uint32_t DATA_BUFF_ACC_PORT
Definition: MIMXRT1052.h:49069
ENC_Type::LMOD
__IO uint16_t LMOD
Definition: MIMXRT1052.h:17964
SEMC_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1052.h:39739
ENET_Type::TAEM
__IO uint32_t TAEM
Definition: MIMXRT1052.h:18546
TEMPMON_Type::TEMPSENSE0
__IO uint32_t TEMPSENSE0
Definition: MIMXRT1052.h:43106
LPUART_Type::WATER
__IO uint32_t WATER
Definition: MIMXRT1052.h:31159
PWM_Type::MCTRL2
__IO uint16_t MCTRL2
Definition: MIMXRT1052.h:36042
PWM_Type::STS
__IO uint16_t STS
Definition: MIMXRT1052.h:36010
ADC_Type::OFS
__IO uint32_t OFS
Definition: MIMXRT1052.h:1306
ADC_Type::CAL
__IO uint32_t CAL
Definition: MIMXRT1052.h:1307
USBPHY_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1052.h:47145
LCDIF_Type::CTRL2_SET
__IO uint32_t CTRL2_SET
Definition: MIMXRT1052.h:27370
PXP_Type::PS_BUF
__IO uint32_t PS_BUF
Definition: MIMXRT1052.h:37860
LPI2C_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1052.h:29283
FLEXSPI_Type::AHBSPNDSTS
__I uint32_t AHBSPNDSTS
Definition: MIMXRT1052.h:21328
PGC_Type::MEGA_PUPSCR
__IO uint32_t MEGA_PUPSCR
Definition: MIMXRT1052.h:33152
FLEXIO_Type::PIN
__I uint32_t PIN
Definition: MIMXRT1052.h:20515
TRNG_Type::PKRRNG
__IO uint32_t PKRRNG
Definition: MIMXRT1052.h:43957
SNVS_Type::HPTAMR
__IO uint32_t HPTAMR
Definition: MIMXRT1052.h:41044
XBARA_Type::SEL26
__IO uint16_t SEL26
Definition: MIMXRT1052.h:51204
CSI_Type::FBUF_PARA
__IO uint32_t FBUF_PARA
Definition: MIMXRT1052.h:10551
DMA_Type::CITER_ELINKYES
__IO uint16_t CITER_ELINKYES
Definition: MIMXRT1052.h:14429
IOMUXC_GPR_Type::GPR21
__IO uint32_t GPR21
Definition: MIMXRT1052.h:24422
CMP_Type::DACCR
__IO uint8_t DACCR
Definition: MIMXRT1052.h:10272
ADC_ETC_Type::DMA_CTRL
__IO uint32_t DMA_CTRL
Definition: MIMXRT1052.h:1687
DCP_Type::CAPABILITY1
__I uint32_t CAPABILITY1
Definition: MIMXRT1052.h:12376
TRNG_Type::SBLIM
__IO uint32_t SBLIM
Definition: MIMXRT1052.h:43964
PXP_Type::STAT
__IO uint32_t STAT
Definition: MIMXRT1052.h:37832
PWM_Type::CVAL2
__I uint16_t CVAL2
Definition: MIMXRT1052.h:36027
FLEXSPI_Type::IPCR1
__IO uint32_t IPCR1
Definition: MIMXRT1052.h:21317
USB_Type::DEVICEADDR
__IO uint32_t DEVICEADDR
Definition: MIMXRT1052.h:45269
XTALOSC24M_Type::OSC_CONFIG1
__IO uint32_t OSC_CONFIG1
Definition: MIMXRT1052.h:52391
TSC_Type::BASIC_SETTING
__IO uint32_t BASIC_SETTING
Definition: MIMXRT1052.h:44742
ENC_Type::REV
__IO uint16_t REV
Definition: MIMXRT1052.h:17952
PXP_Type::OUT_PS_LRC
__IO uint32_t OUT_PS_LRC
Definition: MIMXRT1052.h:37850
CAN_Type::DBG1
__I uint32_t DBG1
Definition: MIMXRT1052.h:4143
LPSPI_Type::FCR
__IO uint32_t FCR
Definition: MIMXRT1052.h:30473
OCOTP_Type::GP3
__IO uint32_t GP3
Definition: MIMXRT1052.h:32264
ENET_Type::RMON_T_P256TO511
__I uint32_t RMON_T_P256TO511
Definition: MIMXRT1052.h:18566
LPI2C_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1052.h:29286
SEMC_Type::STS12
__I uint32_t STS12
Definition: MIMXRT1052.h:39786
PGC_Type::MEGA_SR
__IO uint32_t MEGA_SR
Definition: MIMXRT1052.h:33154
DMA_Type::DCHPRI18
__IO uint8_t DCHPRI18
Definition: MIMXRT1052.h:14399
GPT_Type::SR
__IO uint32_t SR
Definition: MIMXRT1052.h:22974
OCOTP_Type::SRK3
__IO uint32_t SRK3
Definition: MIMXRT1052.h:32246
FLEXSPI_Type::AHBCR
__IO uint32_t AHBCR
Definition: MIMXRT1052.h:21303
LPI2C_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1052.h:29284
CSI_Type::CR19
__IO uint32_t CR19
Definition: MIMXRT1052.h:10555
OCOTP_Type::SCS_SET
__IO uint32_t SCS_SET
Definition: MIMXRT1052.h:32200
DCP_Type::CAPABILITY0
__IO uint32_t CAPABILITY0
Definition: MIMXRT1052.h:12374
LPI2C_Type::MFSR
__I uint32_t MFSR
Definition: MIMXRT1052.h:29302
IOMUXC_SNVS_GPR_Type::GPR3
__IO uint32_t GPR3
Definition: MIMXRT1052.h:27104
SEMC_Type::NANDCR0
__IO uint32_t NANDCR0
Definition: MIMXRT1052.h:39751
TRNG_Type::SCR2L
__IO uint32_t SCR2L
Definition: MIMXRT1052.h:43982
IOMUXC_GPR_Type::GPR17
__IO uint32_t GPR17
Definition: MIMXRT1052.h:24418
ENET_Type::RMON_R_P65TO127
__I uint32_t RMON_R_P65TO127
Definition: MIMXRT1052.h:18594
PXP_Type::AS_CLRKEYHIGH
__IO uint32_t AS_CLRKEYHIGH
Definition: MIMXRT1052.h:37886
ENET_Type::IEEE_R_ALIGN
__I uint32_t IEEE_R_ALIGN
Definition: MIMXRT1052.h:18604
ENET_Type::RMON_T_FRAG
__I uint32_t RMON_T_FRAG
Definition: MIMXRT1052.h:18560
SEMC_Type::IPRXDAT
__I uint32_t IPRXDAT
Definition: MIMXRT1052.h:39772
SPDIF_Type::STCSCL
__IO uint32_t STCSCL
Definition: MIMXRT1052.h:42294
KPP_Type::KPDR
__IO uint16_t KPDR
Definition: MIMXRT1052.h:27211
ADC_Type::CV
__IO uint32_t CV
Definition: MIMXRT1052.h:1305
CAN_Type::DBG2
__I uint32_t DBG2
Definition: MIMXRT1052.h:4144
CAN_Type::RXFIR
__I uint32_t RXFIR
Definition: MIMXRT1052.h:4141
OCOTP_Type::CFG4
__IO uint32_t CFG4
Definition: MIMXRT1052.h:32218
USBPHY_Type::TX_CLR
__IO uint32_t TX_CLR
Definition: MIMXRT1052.h:47136
PWM_Type::VAL1
__IO uint16_t VAL1
Definition: MIMXRT1052.h:35999
ENC_Type::POSDH
__I uint16_t POSDH
Definition: MIMXRT1052.h:17951
PMU_Type::REG_1P1_SET
__IO uint32_t REG_1P1_SET
Definition: MIMXRT1052.h:33469
LPI2C_Type::MCFGR0
__IO uint32_t MCFGR0
Definition: MIMXRT1052.h:29290
LCDIF_Type::BM_ERROR_STAT
__IO uint32_t BM_ERROR_STAT
Definition: MIMXRT1052.h:27391
XTALOSC24M_Type::OSC_CONFIG2_TOG
__IO uint32_t OSC_CONFIG2_TOG
Definition: MIMXRT1052.h:52398
SNVS_Type::HPLR
__IO uint32_t HPLR
Definition: MIMXRT1052.h:41033
IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_ON_REQ
__IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ
Definition: MIMXRT1052.h:26540
TSC_Type::DEBUG_MODE
__IO uint32_t DEBUG_MODE
Definition: MIMXRT1052.h:44756
IOMUXC_GPR_Type::GPR3
__IO uint32_t GPR3
Definition: MIMXRT1052.h:24404
ENET_Type::RCR
__IO uint32_t RCR
Definition: MIMXRT1052.h:18519
OCOTP_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1052.h:32186
PIT_Type::TCTRL
__IO uint32_t TCTRL
Definition: MIMXRT1052.h:33307
PXP_Type::PS_SCALE
__IO uint32_t PS_SCALE
Definition: MIMXRT1052.h:37870
DCP_Type::CH2OPTS
__IO uint32_t CH2OPTS
Definition: MIMXRT1052.h:12430
SNVS_Type::HPVIDR1
__I uint32_t HPVIDR1
Definition: MIMXRT1052.h:41066
OCOTP_Type::CFG0
__IO uint32_t CFG0
Definition: MIMXRT1052.h:32210
DCP_Type::DBGDATA
__I uint32_t DBGDATA
Definition: MIMXRT1052.h:12449
TEMPMON_Type::TEMPSENSE2
__IO uint32_t TEMPSENSE2
Definition: MIMXRT1052.h:43115
CSI_Type::RXCNT
__IO uint32_t RXCNT
Definition: MIMXRT1052.h:10544
XBARA_Type::SEL15
__IO uint16_t SEL15
Definition: MIMXRT1052.h:51193
DCDC_Type::REG2
__IO uint32_t REG2
Definition: MIMXRT1052.h:12016
OCOTP_Type::ANA1
__IO uint32_t ANA1
Definition: MIMXRT1052.h:32236
LPI2C_Type::MRDR
__I uint32_t MRDR
Definition: MIMXRT1052.h:29305
CSI_Type::DMASA_FB2
__IO uint32_t DMASA_FB2
Definition: MIMXRT1052.h:10550
CCM_Type::CIMR
__IO uint32_t CIMR
Definition: MIMXRT1052.h:5090
BEE_Type::AES_KEY0_W2
__IO uint32_t AES_KEY0_W2
Definition: MIMXRT1052.h:3781
DMA_Type::DCHPRI25
__IO uint8_t DCHPRI25
Definition: MIMXRT1052.h:14408
TRNG_Type::PKRCNT32
__I uint32_t PKRCNT32
Definition: MIMXRT1052.h:44003
LPUART_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:31154
OCOTP_Type::SJC_RESP1
__IO uint32_t SJC_RESP1
Definition: MIMXRT1052.h:32258
CCM_ANALOG_Type::MISC0_TOG
__IO uint32_t MISC0_TOG
Definition: MIMXRT1052.h:7263
CCM_ANALOG_Type::MISC2_TOG
__IO uint32_t MISC2_TOG
Definition: MIMXRT1052.h:7271
SNVS_Type::LPTAR
__IO uint32_t LPTAR
Definition: MIMXRT1052.h:41055
IOMUXC_GPR_Type::GPR4
__IO uint32_t GPR4
Definition: MIMXRT1052.h:24405
ADC_Type::GC
__IO uint32_t GC
Definition: MIMXRT1052.h:1303
LPSPI_Type::CCR
__IO uint32_t CCR
Definition: MIMXRT1052.h:30471
USBPHY_Type::TX_TOG
__IO uint32_t TX_TOG
Definition: MIMXRT1052.h:47137
DMA_Type::ERQ
__IO uint32_t ERQ
Definition: MIMXRT1052.h:14362
SEMC_Type::IPCR1
__IO uint32_t IPCR1
Definition: MIMXRT1052.h:39767
ENET_Type::RMON_T_JAB
__I uint32_t RMON_T_JAB
Definition: MIMXRT1052.h:18561
DCP_Type::CH2SEMA
__IO uint32_t CH2SEMA
Definition: MIMXRT1052.h:12424
FLEXSPI_Type::INTR
__IO uint32_t INTR
Definition: MIMXRT1052.h:21305
XBARA_Type::SEL0
__IO uint16_t SEL0
Definition: MIMXRT1052.h:51178
FLEXIO_Type::SHIFTSTAT
__IO uint32_t SHIFTSTAT
Definition: MIMXRT1052.h:20516
CCM_ANALOG_Type::PLL_AUDIO_SET
__IO uint32_t PLL_AUDIO_SET
Definition: MIMXRT1052.h:7232
TRNG_Type::INT_MASK
__IO uint32_t INT_MASK
Definition: MIMXRT1052.h:44012
SNVS_Type::LPLR
__IO uint32_t LPLR
Definition: MIMXRT1052.h:41046
SEMC_Type::SRAMCR2
__IO uint32_t SRAMCR2
Definition: MIMXRT1052.h:39761
GPIO_Type::DR_SET
__O uint32_t DR_SET
Definition: MIMXRT1052.h:22488
SNVS_Type::LPSMCMR
__IO uint32_t LPSMCMR
Definition: MIMXRT1052.h:41056
IOMUXC_GPR_Type::GPR24
__IO uint32_t GPR24
Definition: MIMXRT1052.h:24425
ENET_Type::TGSR
__IO uint32_t TGSR
Definition: MIMXRT1052.h:18617
LCDIF_Type::LUT_CTRL
__IO uint32_t LUT_CTRL
Definition: MIMXRT1052.h:27423
TMR_Type::HOLD
__IO uint16_t HOLD
Definition: MIMXRT1052.h:43415
BEE_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:3776
XBARA_Type::SEL7
__IO uint16_t SEL7
Definition: MIMXRT1052.h:51185
XBARA_Type::SEL35
__IO uint16_t SEL35
Definition: MIMXRT1052.h:51213
PWM_Type::CAPTCOMPX
__IO uint16_t CAPTCOMPX
Definition: MIMXRT1052.h:36022
LPI2C_Type::MCCR0
__IO uint32_t MCCR0
Definition: MIMXRT1052.h:29297
OCOTP_Type::SRK_REVOKE
__IO uint32_t SRK_REVOKE
Definition: MIMXRT1052.h:32284
TRNG_Type::SCR4C
__I uint32_t SCR4C
Definition: MIMXRT1052.h:43989
I2S_Type::RCR4
__IO uint32_t RCR4
Definition: MIMXRT1052.h:23315
LCDIF_Type::LUT0_DATA
__IO uint32_t LUT0_DATA
Definition: MIMXRT1052.h:27427
USB_Type::HCIVERSION
__I uint16_t HCIVERSION
Definition: MIMXRT1052.h:45255
SNVS_Type::HPTALR
__IO uint32_t HPTALR
Definition: MIMXRT1052.h:41045
RTWDOG_Type::TOVAL
__IO uint32_t TOVAL
Definition: MIMXRT1052.h:39523
XBARA_Type::SEL37
__IO uint16_t SEL37
Definition: MIMXRT1052.h:51215
DCP_Type::PACKET6
__I uint32_t PACKET6
Definition: MIMXRT1052.h:12396
DCP_Type::CH2STAT_CLR
__IO uint32_t CH2STAT_CLR
Definition: MIMXRT1052.h:12428
ENET_Type::IEEE_R_FDXFC
__I uint32_t IEEE_R_FDXFC
Definition: MIMXRT1052.h:18606
OCOTP_Type::CFG3
__IO uint32_t CFG3
Definition: MIMXRT1052.h:32216
OCOTP_Type::SRK5
__IO uint32_t SRK5
Definition: MIMXRT1052.h:32250
LPUART_Type::PINCFG
__IO uint32_t PINCFG
Definition: MIMXRT1052.h:31151
LCDIF_Type::VDCTRL0_SET
__IO uint32_t VDCTRL0_SET
Definition: MIMXRT1052.h:27380
PGC_Type::CPU_CTRL
__IO uint32_t CPU_CTRL
Definition: MIMXRT1052.h:33156
XBARA_Type::SEL29
__IO uint16_t SEL29
Definition: MIMXRT1052.h:51207
PXP_Type::CSC1_COEF0
__IO uint32_t CSC1_COEF0
Definition: MIMXRT1052.h:37888
WDOG_Type::WMCR
__IO uint16_t WMCR
Definition: MIMXRT1052.h:50967
I2S_Type::TMR
__IO uint32_t TMR
Definition: MIMXRT1052.h:23309
PIT_Type::LTMR64L
__I uint32_t LTMR64L
Definition: MIMXRT1052.h:33302
ADC_ETC_Type::TRIGn_CHAIN_3_2
__IO uint32_t TRIGn_CHAIN_3_2
Definition: MIMXRT1052.h:1692
TSC_Type::DEBUG_MODE2
__IO uint32_t DEBUG_MODE2
Definition: MIMXRT1052.h:44758
CCM_Type::CCOSR
__IO uint32_t CCOSR
Definition: MIMXRT1052.h:5091
PXP_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1052.h:37830
PMU_Type::MISC0_CLR
__IO uint32_t MISC0_CLR
Definition: MIMXRT1052.h:33486
SNVS_Type::HPRTCLR
__IO uint32_t HPRTCLR
Definition: MIMXRT1052.h:41043
CCM_Type::CCGR2
__IO uint32_t CCGR2
Definition: MIMXRT1052.h:5095
USDHC_Type::CMD_XFR_TYP
__IO uint32_t CMD_XFR_TYP
Definition: MIMXRT1052.h:49064
ENET_Type::RACC
__IO uint32_t RACC
Definition: MIMXRT1052.h:18552
FLEXRAM_Type::INT_SIG_EN
__IO uint32_t INT_SIG_EN
Definition: MIMXRT1052.h:21144
ENET_Type::EIR
__IO uint32_t EIR
Definition: MIMXRT1052.h:18506
SNVS_Type::LPSR
__IO uint32_t LPSR
Definition: MIMXRT1052.h:41052
DMA_Type::CERR
__O uint8_t CERR
Definition: MIMXRT1052.h:14371
XTALOSC24M_Type::OSC_CONFIG0_TOG
__IO uint32_t OSC_CONFIG0_TOG
Definition: MIMXRT1052.h:52390
IOMUXC_GPR_Type::GPR20
__IO uint32_t GPR20
Definition: MIMXRT1052.h:24421
USB_Type::ID
__I uint32_t ID
Definition: MIMXRT1052.h:45240
USB_Type::GPTIMER1CTRL
__IO uint32_t GPTIMER1CTRL
Definition: MIMXRT1052.h:45250
PMU_Type::REG_CORE_CLR
__IO uint32_t REG_CORE_CLR
Definition: MIMXRT1052.h:33482
DMA_Type::DLAST_SGA
__IO int32_t DLAST_SGA
Definition: MIMXRT1052.h:14431
CCM_ANALOG_Type::PLL_AUDIO
__IO uint32_t PLL_AUDIO
Definition: MIMXRT1052.h:7231
CCM_ANALOG_Type::PFD_480_SET
__IO uint32_t PFD_480_SET
Definition: MIMXRT1052.h:7252
OCOTP_Type::READ_CTRL
__IO uint32_t READ_CTRL
Definition: MIMXRT1052.h:32193
IOMUXC_GPR_Type::GPR5
__IO uint32_t GPR5
Definition: MIMXRT1052.h:24406
TMR_Type::COMP1
__IO uint16_t COMP1
Definition: MIMXRT1052.h:43411
FLEXSPI_Type::IPTXFSTS
__I uint32_t IPTXFSTS
Definition: MIMXRT1052.h:21330
OCOTP_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1052.h:32187
XBARB_Type::SEL2
__IO uint16_t SEL2
Definition: MIMXRT1052.h:52227
LCDIF_Type::VDCTRL2
__IO uint32_t VDCTRL2
Definition: MIMXRT1052.h:27385
GPIO_Type::EDGE_SEL
__IO uint32_t EDGE_SEL
Definition: MIMXRT1052.h:22486
RTWDOG_Type::CNT
__IO uint32_t CNT
Definition: MIMXRT1052.h:39522
LPSPI_Type::CFGR1
__IO uint32_t CFGR1
Definition: MIMXRT1052.h:30466
PXP_Type::OUT_BUF
__IO uint32_t OUT_BUF
Definition: MIMXRT1052.h:37840
PXP_Type::OUT_CTRL_TOG
__IO uint32_t OUT_CTRL_TOG
Definition: MIMXRT1052.h:37839
LCDIF_Type::LUT0_ADDR
__IO uint32_t LUT0_ADDR
Definition: MIMXRT1052.h:27425
ENET_Type::TCSR
__IO uint32_t TCSR
Definition: MIMXRT1052.h:18619
ENET_Type::IEEE_T_EXCOL
__I uint32_t IEEE_T_EXCOL
Definition: MIMXRT1052.h:18577
USB_ANALOG_Type::CHRG_DETECT_TOG
__IO uint32_t CHRG_DETECT_TOG
Definition: MIMXRT1052.h:48562
EWM_Type::CTRL
__IO uint8_t CTRL
Definition: MIMXRT1052.h:20383
FLEXRAM_Type::INT_STATUS
__IO uint32_t INT_STATUS
Definition: MIMXRT1052.h:21142
WDOG_Type::WCR
__IO uint16_t WCR
Definition: MIMXRT1052.h:50963
OCOTP_Type::CFG1
__IO uint32_t CFG1
Definition: MIMXRT1052.h:32212
BEE_Type::CTR_NONCE0_W0
__O uint32_t CTR_NONCE0_W0
Definition: MIMXRT1052.h:3784
DMA_Type::ATTR
__IO uint16_t ATTR
Definition: MIMXRT1052.h:14418
ENET_Type::MMFR
__IO uint32_t MMFR
Definition: MIMXRT1052.h:18514
PWM_Type::FTST
__IO uint16_t FTST
Definition: MIMXRT1052.h:36046
BEE_Type::CTR_NONCE0_W1
__O uint32_t CTR_NONCE0_W1
Definition: MIMXRT1052.h:3785
DCP_Type::CH3STAT_CLR
__IO uint32_t CH3STAT_CLR
Definition: MIMXRT1052.h:12440
IOMUXC_GPR_Type::GPR22
__IO uint32_t GPR22
Definition: MIMXRT1052.h:24423
KPP_Type::KPSR
__IO uint16_t KPSR
Definition: MIMXRT1052.h:27209
ENET_Type::RMON_T_OVERSIZE
__I uint32_t RMON_T_OVERSIZE
Definition: MIMXRT1052.h:18559
PXP_Type::PS_PITCH
__IO uint32_t PS_PITCH
Definition: MIMXRT1052.h:37866
CSU_Type::SA
__IO uint32_t SA
Definition: MIMXRT1052.h:11325
PGC_Type::CPU_PDNSCR
__IO uint32_t CPU_PDNSCR
Definition: MIMXRT1052.h:33158
FLEXSPI_Type::IPRXFSTS
__I uint32_t IPRXFSTS
Definition: MIMXRT1052.h:21329
DCP_Type::CONTEXT
__IO uint32_t CONTEXT
Definition: MIMXRT1052.h:12378
PXP_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:37828
USDHC_Type::INT_STATUS
__IO uint32_t INT_STATUS
Definition: MIMXRT1052.h:49073
OCOTP_Type::GP1
__IO uint32_t GP1
Definition: MIMXRT1052.h:32266
XBARA_Type::SEL36
__IO uint16_t SEL36
Definition: MIMXRT1052.h:51214
CCM_ANALOG_Type::PLL_ARM
__IO uint32_t PLL_ARM
Definition: MIMXRT1052.h:7209
PXP_Type::OUT_AS_ULC
__IO uint32_t OUT_AS_ULC
Definition: MIMXRT1052.h:37852
OCOTP_Type::SW_GP22
__IO uint32_t SW_GP22
Definition: MIMXRT1052.h:32276
SNVS_Type::HPSVCR
__IO uint32_t HPSVCR
Definition: MIMXRT1052.h:41037
LPI2C_Type::MIER
__IO uint32_t MIER
Definition: MIMXRT1052.h:29288
DMA_Type::DCHPRI17
__IO uint8_t DCHPRI17
Definition: MIMXRT1052.h:14400
AIPSTZ_Type::OPACR
__IO uint32_t OPACR
Definition: MIMXRT1052.h:2803
TRNG_Type::PKRCNTDC
__I uint32_t PKRCNTDC
Definition: MIMXRT1052.h:44008
PMU_Type::REG_1P1_TOG
__IO uint32_t REG_1P1_TOG
Definition: MIMXRT1052.h:33471
USB_Type::CAPLENGTH
__I uint8_t CAPLENGTH
Definition: MIMXRT1052.h:45253
XBARA_Type::SEL63
__IO uint16_t SEL63
Definition: MIMXRT1052.h:51241
LPI2C_Type::MCFGR3
__IO uint32_t MCFGR3
Definition: MIMXRT1052.h:29293
DMA_Type::SOFF
__IO uint16_t SOFF
Definition: MIMXRT1052.h:14417
CCM_Type::CBCDR
__IO uint32_t CBCDR
Definition: MIMXRT1052.h:5074
I2S_Type::TCR3
__IO uint32_t TCR3
Definition: MIMXRT1052.h:23302
SNVS_Type::HPCOMR
__IO uint32_t HPCOMR
Definition: MIMXRT1052.h:41034
LCDIF_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1052.h:27364
TMR_Type::ENBL
__IO uint16_t ENBL
Definition: MIMXRT1052.h:43425
XTALOSC24M_Type::OSC_CONFIG1_TOG
__IO uint32_t OSC_CONFIG1_TOG
Definition: MIMXRT1052.h:52394
ENET_Type::GAUR
__IO uint32_t GAUR
Definition: MIMXRT1052.h:18532
PXP_Type::PS_CLRKEYLOW
__IO uint32_t PS_CLRKEYLOW
Definition: MIMXRT1052.h:37874
USB_Type::TXFILLTUNING
__IO uint32_t TXFILLTUNING
Definition: MIMXRT1052.h:45278
TSC_Type::INT_STATUS
__IO uint32_t INT_STATUS
Definition: MIMXRT1052.h:44754
CCM_ANALOG_Type::PLL_AUDIO_CLR
__IO uint32_t PLL_AUDIO_CLR
Definition: MIMXRT1052.h:7233
USBPHY_Type::RX_TOG
__IO uint32_t RX_TOG
Definition: MIMXRT1052.h:47141
PWM_Type::CVAL3CYC
__I uint16_t CVAL3CYC
Definition: MIMXRT1052.h:36030
CCM_Type::CCGR6
__IO uint32_t CCGR6
Definition: MIMXRT1052.h:5099
CAN_Type::RX14MASK
__IO uint32_t RX14MASK
Definition: MIMXRT1052.h:4128
GPIO_Type::ICR1
__IO uint32_t ICR1
Definition: MIMXRT1052.h:22482
XBARA_Type::SEL62
__IO uint16_t SEL62
Definition: MIMXRT1052.h:51240
DCP_Type::PAGETABLE
__IO uint32_t PAGETABLE
Definition: MIMXRT1052.h:12451
CCM_Type::CISR
__IO uint32_t CISR
Definition: MIMXRT1052.h:5089
ENET_Type::ATVR
__IO uint32_t ATVR
Definition: MIMXRT1052.h:18610
I2S_Type::RCSR
__IO uint32_t RCSR
Definition: MIMXRT1052.h:23311
XBARA_Type::SEL57
__IO uint16_t SEL57
Definition: MIMXRT1052.h:51235
USBPHY_Type::DEBUG_CLR
__IO uint32_t DEBUG_CLR
Definition: MIMXRT1052.h:47150
PXP_Type::PS_CTRL_SET
__IO uint32_t PS_CTRL_SET
Definition: MIMXRT1052.h:37857
CAN_Type::CRCR
__I uint32_t CRCR
Definition: MIMXRT1052.h:4139
XBARA_Type::SEL12
__IO uint16_t SEL12
Definition: MIMXRT1052.h:51190
USB_ANALOG_Type::LOOPBACK
__IO uint32_t LOOPBACK
Definition: MIMXRT1052.h:48567
LCDIF_Type::CTRL2_TOG
__IO uint32_t CTRL2_TOG
Definition: MIMXRT1052.h:27372
SNVS_Type::LPLVDR
__IO uint32_t LPLVDR
Definition: MIMXRT1052.h:41058
AIPSTZ_Type::OPACR2
__IO uint32_t OPACR2
Definition: MIMXRT1052.h:2805
ENET_Type::PAUR
__IO uint32_t PAUR
Definition: MIMXRT1052.h:18524
I2S_Type::TCR1
__IO uint32_t TCR1
Definition: MIMXRT1052.h:23300
USB_Type::HWTXBUF
__I uint32_t HWTXBUF
Definition: MIMXRT1052.h:45244
TMR_Type::FILT
__IO uint16_t FILT
Definition: MIMXRT1052.h:43422
XBARA_Type::SEL65
__IO uint16_t SEL65
Definition: MIMXRT1052.h:51243
DMA_Type::DCHPRI19
__IO uint8_t DCHPRI19
Definition: MIMXRT1052.h:14398
I2S_Type::TCR2
__IO uint32_t TCR2
Definition: MIMXRT1052.h:23301
XBARA_Type::SEL5
__IO uint16_t SEL5
Definition: MIMXRT1052.h:51183
PXP_Type::CSC1_COEF2
__IO uint32_t CSC1_COEF2
Definition: MIMXRT1052.h:37892
LPI2C_Type::MCFGR1
__IO uint32_t MCFGR1
Definition: MIMXRT1052.h:29291
XTALOSC24M_Type::MISC0_SET
__IO uint32_t MISC0_SET
Definition: MIMXRT1052.h:52378
USDHC_Type::BLK_ATT
__IO uint32_t BLK_ATT
Definition: MIMXRT1052.h:49062
LCDIF_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1052.h:27362
TRNG_Type::MCTL
__IO uint32_t MCTL
Definition: MIMXRT1052.h:43955
PXP_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1052.h:37831
CCM_ANALOG_Type::MISC0
__IO uint32_t MISC0
Definition: MIMXRT1052.h:7260
iomuxc_select_input_t
enum _iomuxc_select_input iomuxc_select_input_t
Enumeration for the IOMUXC select input.
DCP_Type::CH0CMDPTR
__IO uint32_t CH0CMDPTR
Definition: MIMXRT1052.h:12398
DCP_Type::PACKET1
__I uint32_t PACKET1
Definition: MIMXRT1052.h:12386
BEE_Type::CTR_NONCE1_W2
__O uint32_t CTR_NONCE1_W2
Definition: MIMXRT1052.h:3790
ENC_Type::CTRL
__IO uint16_t CTRL
Definition: MIMXRT1052.h:17947
ENET_Type::TCR
__IO uint32_t TCR
Definition: MIMXRT1052.h:18521
USB_Type::FRINDEX
__IO uint32_t FRINDEX
Definition: MIMXRT1052.h:45266
USBPHY_Type::PWD_SET
__IO uint32_t PWD_SET
Definition: MIMXRT1052.h:47131
SNVS_Type::HPSVSR
__IO uint32_t HPSVSR
Definition: MIMXRT1052.h:41039
GPIO_Type::DR
__IO uint32_t DR
Definition: MIMXRT1052.h:22479
SPDIF_Type::SIE
__IO uint32_t SIE
Definition: MIMXRT1052.h:42280
ENET_Type::RMON_T_P_GTE2048
__I uint32_t RMON_T_P_GTE2048
Definition: MIMXRT1052.h:18569
DMA_Type::BITER_ELINKYES
__IO uint16_t BITER_ELINKYES
Definition: MIMXRT1052.h:14435
PMU_Type::REG_2P5
__IO uint32_t REG_2P5
Definition: MIMXRT1052.h:33476
CCM_ANALOG_Type::MISC2_SET
__IO uint32_t MISC2_SET
Definition: MIMXRT1052.h:7269
XBARA_Type::SEL42
__IO uint16_t SEL42
Definition: MIMXRT1052.h:51220
PWM_Type::OCTRL
__IO uint16_t OCTRL
Definition: MIMXRT1052.h:36009
CCM_ANALOG_Type::PLL_VIDEO_DENOM
__IO uint32_t PLL_VIDEO_DENOM
Definition: MIMXRT1052.h:7245
XTALOSC24M_Type::MISC0
__IO uint32_t MISC0
Definition: MIMXRT1052.h:52377
BEE_Type::AES_KEY0_W0
__IO uint32_t AES_KEY0_W0
Definition: MIMXRT1052.h:3779
CMP_Type::CR1
__IO uint8_t CR1
Definition: MIMXRT1052.h:10269
CMP_Type::FPR
__IO uint8_t FPR
Definition: MIMXRT1052.h:10270
ENET_Type::MRBR
__IO uint32_t MRBR
Definition: MIMXRT1052.h:18539
ENET_Type::RAEM
__IO uint32_t RAEM
Definition: MIMXRT1052.h:18543
LCDIF_Type::VDCTRL3
__IO uint32_t VDCTRL3
Definition: MIMXRT1052.h:27387
CCM_Type::CSCMR1
__IO uint32_t CSCMR1
Definition: MIMXRT1052.h:5076
OCOTP_Type::SRK1
__IO uint32_t SRK1
Definition: MIMXRT1052.h:32242
ENET_Type::RSEM
__IO uint32_t RSEM
Definition: MIMXRT1052.h:18542
XTALOSC24M_Type::MISC0_CLR
__IO uint32_t MISC0_CLR
Definition: MIMXRT1052.h:52379
XBARA_Type::SEL1
__IO uint16_t SEL1
Definition: MIMXRT1052.h:51179
PWM_Type::FCTRL2
__IO uint16_t FCTRL2
Definition: MIMXRT1052.h:36047
DCP_Type::CHANNELCTRL_TOG
__IO uint32_t CHANNELCTRL_TOG
Definition: MIMXRT1052.h:12373
DMA_Type::DCHPRI2
__IO uint8_t DCHPRI2
Definition: MIMXRT1052.h:14383
AIPSTZ_Type::OPACR1
__IO uint32_t OPACR1
Definition: MIMXRT1052.h:2804
IOMUXC_GPR_Type::GPR14
__IO uint32_t GPR14
Definition: MIMXRT1052.h:24415
BEE_Type::REGION1_TOP
__IO uint32_t REGION1_TOP
Definition: MIMXRT1052.h:3792
CCM_Type::CDHIPR
__I uint32_t CDHIPR
Definition: MIMXRT1052.h:5086
CAN_Type::WORD1
__IO uint32_t WORD1
Definition: MIMXRT1052.h:4150
LPI2C_Type::SSR
__IO uint32_t SSR
Definition: MIMXRT1052.h:29308
PWM_Type::FRACVAL4
__IO uint16_t FRACVAL4
Definition: MIMXRT1052.h:36004
FLEXIO_Type::SHIFTSIEN
__IO uint32_t SHIFTSIEN
Definition: MIMXRT1052.h:20520
LPSPI_Type::DMR0
__IO uint32_t DMR0
Definition: MIMXRT1052.h:30468
I2S_Type::RCR3
__IO uint32_t RCR3
Definition: MIMXRT1052.h:23314
XBARB_Type::SEL3
__IO uint16_t SEL3
Definition: MIMXRT1052.h:52228
CCM_Type::CBCMR
__IO uint32_t CBCMR
Definition: MIMXRT1052.h:5075
CCM_Type::CCGR3
__IO uint32_t CCGR3
Definition: MIMXRT1052.h:5096
SPDIF_Type::STR
__O uint32_t STR
Definition: MIMXRT1052.h:42292
DMA_Type::DCHPRI12
__IO uint8_t DCHPRI12
Definition: MIMXRT1052.h:14397
TSC_Type::INT_SIG_EN
__IO uint32_t INT_SIG_EN
Definition: MIMXRT1052.h:44752
SEMC_Type::INTR
__IO uint32_t INTR
Definition: MIMXRT1052.h:39746
LCDIF_Type::CTRL1_TOG
__IO uint32_t CTRL1_TOG
Definition: MIMXRT1052.h:27368
ENET_Type::IEEE_T_FRAME_OK
__I uint32_t IEEE_T_FRAME_OK
Definition: MIMXRT1052.h:18572
PWM_Type::CNT
__I uint16_t CNT
Definition: MIMXRT1052.h:35992
XBARA_Type::SEL56
__IO uint16_t SEL56
Definition: MIMXRT1052.h:51234
USB_Type::OTGSC
__IO uint32_t OTGSC
Definition: MIMXRT1052.h:45285
CCM_ANALOG_Type::PFD_528_CLR
__IO uint32_t PFD_528_CLR
Definition: MIMXRT1052.h:7257
XBARA_Type::SEL9
__IO uint16_t SEL9
Definition: MIMXRT1052.h:51187
XBARA_Type::SEL54
__IO uint16_t SEL54
Definition: MIMXRT1052.h:51232
ENET_Type::RMON_R_P64
__I uint32_t RMON_R_P64
Definition: MIMXRT1052.h:18593
_xbar_input_signal
_xbar_input_signal
Definition: MIMXRT1052.h:740
OCOTP_Type::SJC_RESP0
__IO uint32_t SJC_RESP0
Definition: MIMXRT1052.h:32256
DMA_Type::DCHPRI5
__IO uint8_t DCHPRI5
Definition: MIMXRT1052.h:14388
PMU_Type::REG_1P1
__IO uint32_t REG_1P1
Definition: MIMXRT1052.h:33468
ENET_Type::RMON_R_FRAG
__I uint32_t RMON_R_FRAG
Definition: MIMXRT1052.h:18590
IOMUXC_GPR_Type::GPR19
__IO uint32_t GPR19
Definition: MIMXRT1052.h:24420
KPP_Type::KDDR
__IO uint16_t KDDR
Definition: MIMXRT1052.h:27210
PMU_Type::MISC1_TOG
__IO uint32_t MISC1_TOG
Definition: MIMXRT1052.h:33491
XBARA_Type::SEL17
__IO uint16_t SEL17
Definition: MIMXRT1052.h:51195
ADC_ETC_Type::TRIGn_CHAIN_1_0
__IO uint32_t TRIGn_CHAIN_1_0
Definition: MIMXRT1052.h:1691
SEMC_Type::SDRAMCR0
__IO uint32_t SDRAMCR0
Definition: MIMXRT1052.h:39747
TRNG_Type::SCR1L
__IO uint32_t SCR1L
Definition: MIMXRT1052.h:43978
CCM_Type::CS2CDR
__IO uint32_t CS2CDR
Definition: MIMXRT1052.h:5080
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_WAKEUP
__IO uint32_t SW_PAD_CTL_PAD_WAKEUP
Definition: MIMXRT1052.h:26545
CCM_ANALOG_Type::PLL_ARM_CLR
__IO uint32_t PLL_ARM_CLR
Definition: MIMXRT1052.h:7211
CAN_Type::IFLAG1
__IO uint32_t IFLAG1
Definition: MIMXRT1052.h:4135
SEMC_Type::SRAMCR3
uint32_t SRAMCR3
Definition: MIMXRT1052.h:39762
LCDIF_Type::VDCTRL0_CLR
__IO uint32_t VDCTRL0_CLR
Definition: MIMXRT1052.h:27381
LPSPI_Type::TDR
__O uint32_t TDR
Definition: MIMXRT1052.h:30476
LPI2C_Type::SAMR
__IO uint32_t SAMR
Definition: MIMXRT1052.h:29315
TMR_Type::CSCTRL
__IO uint16_t CSCTRL
Definition: MIMXRT1052.h:43421
USB_ANALOG_Type::CHRG_DETECT_STAT
__I uint32_t CHRG_DETECT_STAT
Definition: MIMXRT1052.h:48565
USB_Type::USBCMD
__IO uint32_t USBCMD
Definition: MIMXRT1052.h:45263
XBARB_Type::SEL1
__IO uint16_t SEL1
Definition: MIMXRT1052.h:52226
PWM_Type::CVAL1CYC
__I uint16_t CVAL1CYC
Definition: MIMXRT1052.h:36026
TEMPMON_Type::TEMPSENSE0_TOG
__IO uint32_t TEMPSENSE0_TOG
Definition: MIMXRT1052.h:43109
TEMPMON_Type::TEMPSENSE1_TOG
__IO uint32_t TEMPSENSE1_TOG
Definition: MIMXRT1052.h:43113
ENET_Type::RMON_T_UNDERSIZE
__I uint32_t RMON_T_UNDERSIZE
Definition: MIMXRT1052.h:18558
TMR_Type::CTRL
__IO uint16_t CTRL
Definition: MIMXRT1052.h:43417
CAN_Type::ECR
__IO uint32_t ECR
Definition: MIMXRT1052.h:4130
LCDIF_Type::PIGEON_1
__IO uint32_t PIGEON_1
Definition: MIMXRT1052.h:27418
DCP_Type::CHANNELCTRL_CLR
__IO uint32_t CHANNELCTRL_CLR
Definition: MIMXRT1052.h:12372
FLEXSPI_Type::LUTKEY
__IO uint32_t LUTKEY
Definition: MIMXRT1052.h:21306
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_ON_REQ
__IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ
Definition: MIMXRT1052.h:26546
USB_Type::ENDPTLISTADDR
__IO uint32_t ENDPTLISTADDR
Definition: MIMXRT1052.h:45274
PMU_Type::MISC1_SET
__IO uint32_t MISC1_SET
Definition: MIMXRT1052.h:33489
XTALOSC24M_Type::LOWPWR_CTRL
__IO uint32_t LOWPWR_CTRL
Definition: MIMXRT1052.h:52382
CCM_Type::CMEOR
__IO uint32_t CMEOR
Definition: MIMXRT1052.h:5101
XBARA_Type::SEL16
__IO uint16_t SEL16
Definition: MIMXRT1052.h:51194
IOMUXC_GPR_Type::GPR16
__IO uint32_t GPR16
Definition: MIMXRT1052.h:24417
USB_Type::ENDPTNAK
__IO uint32_t ENDPTNAK
Definition: MIMXRT1052.h:45280
DMA_Type::HRS
__I uint32_t HRS
Definition: MIMXRT1052.h:14378
USBPHY_Type::PWD_CLR
__IO uint32_t PWD_CLR
Definition: MIMXRT1052.h:47132
TRNG_Type::SCR2C
__I uint32_t SCR2C
Definition: MIMXRT1052.h:43981
TRNG_Type::SCMISC
__IO uint32_t SCMISC
Definition: MIMXRT1052.h:43956
IOMUXC_GPR_Type::GPR11
__IO uint32_t GPR11
Definition: MIMXRT1052.h:24412
GPIO_Type::IMR
__IO uint32_t IMR
Definition: MIMXRT1052.h:22484
TRNG_Type::INT_STATUS
__I uint32_t INT_STATUS
Definition: MIMXRT1052.h:44013
SEMC_Type::SDRAMCR1
__IO uint32_t SDRAMCR1
Definition: MIMXRT1052.h:39748
FLEXSPI_Type::MCR1
__IO uint32_t MCR1
Definition: MIMXRT1052.h:21301
OCOTP_Type::SRK4
__IO uint32_t SRK4
Definition: MIMXRT1052.h:32248
CMP_Type::SCR
__IO uint8_t SCR
Definition: MIMXRT1052.h:10271
PWM_Type::CAPTCTRLB
__IO uint16_t CAPTCTRLB
Definition: MIMXRT1052.h:36019
XBARA_Type::SEL4
__IO uint16_t SEL4
Definition: MIMXRT1052.h:51182
IOMUXC_GPR_Type::GPR13
__IO uint32_t GPR13
Definition: MIMXRT1052.h:24414
SPDIF_Type::SRFM
__I uint32_t SRFM
Definition: MIMXRT1052.h:42296
ENET_Type::RMON_R_OCTETS
__I uint32_t RMON_R_OCTETS
Definition: MIMXRT1052.h:18600
PXP_Type::PS_OFFSET
__IO uint32_t PS_OFFSET
Definition: MIMXRT1052.h:37872
PXP_Type::OUT_LRC
__IO uint32_t OUT_LRC
Definition: MIMXRT1052.h:37846
BEE_Type::AES_KEY0_W1
__IO uint32_t AES_KEY0_W1
Definition: MIMXRT1052.h:3780
iomuxc_sw_mux_ctl_pad_t
enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
ENET_Type::ATSTMP
__I uint32_t ATSTMP
Definition: MIMXRT1052.h:18615
LCDIF_Type::PIGEONCTRL2_TOG
__IO uint32_t PIGEONCTRL2_TOG
Definition: MIMXRT1052.h:27413
TEMPMON_Type::TEMPSENSE0_CLR
__IO uint32_t TEMPSENSE0_CLR
Definition: MIMXRT1052.h:43108
LCDIF_Type::PIGEONCTRL1
__IO uint32_t PIGEONCTRL1
Definition: MIMXRT1052.h:27406
SPDIF_Type::SRR
__I uint32_t SRR
Definition: MIMXRT1052.h:42286
DMA_Type::NBYTES_MLOFFYES
__IO uint32_t NBYTES_MLOFFYES
Definition: MIMXRT1052.h:14422
USB_Type::PORTSC1
__IO uint32_t PORTSC1
Definition: MIMXRT1052.h:45283
SRC_Type::SCR
__IO uint32_t SCR
Definition: MIMXRT1052.h:42849
TRNG_Type::FRQMAX
__IO uint32_t FRQMAX
Definition: MIMXRT1052.h:43970
OCOTP_Type::TIMING2
__IO uint32_t TIMING2
Definition: MIMXRT1052.h:32206
XBARA_Type::SEL50
__IO uint16_t SEL50
Definition: MIMXRT1052.h:51228
PMU_Type::REG_CORE
__IO uint32_t REG_CORE
Definition: MIMXRT1052.h:33480
DCP_Type::CH2OPTS_TOG
__IO uint32_t CH2OPTS_TOG
Definition: MIMXRT1052.h:12433
OCOTP_Type::SRK0
__IO uint32_t SRK0
Definition: MIMXRT1052.h:32240
GPT_Type::CNT
__I uint32_t CNT
Definition: MIMXRT1052.h:22978
XTALOSC24M_Type::MISC0_TOG
__IO uint32_t MISC0_TOG
Definition: MIMXRT1052.h:52380
DMA_Type::CSR
__IO uint16_t CSR
Definition: MIMXRT1052.h:14432
PXP_Type::AS_CTRL
__IO uint32_t AS_CTRL
Definition: MIMXRT1052.h:37878
LPSPI_Type::DER
__IO uint32_t DER
Definition: MIMXRT1052.h:30464
RTWDOG_Type::CS
__IO uint32_t CS
Definition: MIMXRT1052.h:39521
PMU_Type::REG_CORE_SET
__IO uint32_t REG_CORE_SET
Definition: MIMXRT1052.h:33481
DCP_Type::DBGSELECT
__IO uint32_t DBGSELECT
Definition: MIMXRT1052.h:12447
CCM_ANALOG_Type::PLL_AUDIO_NUM
__IO uint32_t PLL_AUDIO_NUM
Definition: MIMXRT1052.h:7235
PWM_Type::DMAEN
__IO uint16_t DMAEN
Definition: MIMXRT1052.h:36012
PXP_Type::PS_BACKGROUND
__IO uint32_t PS_BACKGROUND
Definition: MIMXRT1052.h:37868
XBARA_Type::SEL28
__IO uint16_t SEL28
Definition: MIMXRT1052.h:51206
CCM_ANALOG_Type::MISC1_TOG
__IO uint32_t MISC1_TOG
Definition: MIMXRT1052.h:7267
IOMUXC_SNVS_GPR_Type::GPR2
uint32_t GPR2
Definition: MIMXRT1052.h:27103
TRNG_Type::PKRCNTFE
__I uint32_t PKRCNTFE
Definition: MIMXRT1052.h:44009
OCOTP_Type::GP2
__IO uint32_t GP2
Definition: MIMXRT1052.h:32268
EWM_Type::CLKPRESCALER
__IO uint8_t CLKPRESCALER
Definition: MIMXRT1052.h:20388
ADC_ETC_Type::DONE0_1_IRQ
__IO uint32_t DONE0_1_IRQ
Definition: MIMXRT1052.h:1685
BEE_Type::STATUS
__IO uint32_t STATUS
Definition: MIMXRT1052.h:3783
ENET_Type::ATCOR
__IO uint32_t ATCOR
Definition: MIMXRT1052.h:18613
DMA_Type::DCHPRI14
__IO uint8_t DCHPRI14
Definition: MIMXRT1052.h:14395
DMA_Type::CR
__IO uint32_t CR
Definition: MIMXRT1052.h:14359
DMA_Type::DCHPRI8
__IO uint8_t DCHPRI8
Definition: MIMXRT1052.h:14393
SPDIF_Type::SRQ
__I uint32_t SRQ
Definition: MIMXRT1052.h:42290
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_ONOFF
__IO uint32_t SW_PAD_CTL_PAD_ONOFF
Definition: MIMXRT1052.h:26544
XBARA_Type::SEL53
__IO uint16_t SEL53
Definition: MIMXRT1052.h:51231
LCDIF_Type::PIGEON_0
__IO uint32_t PIGEON_0
Definition: MIMXRT1052.h:27416
XBARA_Type::SEL32
__IO uint16_t SEL32
Definition: MIMXRT1052.h:51210
ENET_Type::RMON_T_BC_PKT
__I uint32_t RMON_T_BC_PKT
Definition: MIMXRT1052.h:18555
TMR_Type::SCTRL
__IO uint16_t SCTRL
Definition: MIMXRT1052.h:43418
DCP_Type::PACKET0
__I uint32_t PACKET0
Definition: MIMXRT1052.h:12384
ENET_Type::IEEE_T_OCTETS_OK
__I uint32_t IEEE_T_OCTETS_OK
Definition: MIMXRT1052.h:18582
_xbar_output_signal
_xbar_output_signal
Definition: MIMXRT1052.h:948
PIT_Type::LDVAL
__IO uint32_t LDVAL
Definition: MIMXRT1052.h:33305
LPUART_Type::DATA
__IO uint32_t DATA
Definition: MIMXRT1052.h:31155
PXP_Type::CSC1_COEF1
__IO uint32_t CSC1_COEF1
Definition: MIMXRT1052.h:37890
_iomuxc_sw_pad_ctl_pad
_iomuxc_sw_pad_ctl_pad
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
Definition: MIMXRT1052.h:447
TRNG_Type::SCR1C
__I uint32_t SCR1C
Definition: MIMXRT1052.h:43977
DCP_Type::CH1STAT_TOG
__IO uint32_t CH1STAT_TOG
Definition: MIMXRT1052.h:12417
OCOTP_Type::MISC_CONF1
__IO uint32_t MISC_CONF1
Definition: MIMXRT1052.h:32282
PXP_Type::PS_CTRL_TOG
__IO uint32_t PS_CTRL_TOG
Definition: MIMXRT1052.h:37859
ENET_Type::RMON_T_P128TO255
__I uint32_t RMON_T_P128TO255
Definition: MIMXRT1052.h:18565
LCDIF_Type::RGB_ADJUST
__IO uint32_t RGB_ADJUST
Definition: MIMXRT1052.h:27397
ENET_Type::RMON_R_CRC_ALIGN
__I uint32_t RMON_R_CRC_ALIGN
Definition: MIMXRT1052.h:18587
LCDIF_Type::CTRL1
__IO uint32_t CTRL1
Definition: MIMXRT1052.h:27365
ADC_ETC_Type::TRIGn_RESULT_7_6
__I uint32_t TRIGn_RESULT_7_6
Definition: MIMXRT1052.h:1698
LCDIF_Type::NEXT_BUF
__IO uint32_t NEXT_BUF
Definition: MIMXRT1052.h:27377
DMA_Type::DCHPRI7
__IO uint8_t DCHPRI7
Definition: MIMXRT1052.h:14386
PXP_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1052.h:37829
CCM_ANALOG_Type::MISC0_CLR
__IO uint32_t MISC0_CLR
Definition: MIMXRT1052.h:7262
IOMUXC_GPR_Type::GPR12
__IO uint32_t GPR12
Definition: MIMXRT1052.h:24413
DMA_Type::NBYTES_MLOFFNO
__IO uint32_t NBYTES_MLOFFNO
Definition: MIMXRT1052.h:14421
GPIO_Type::ISR
__IO uint32_t ISR
Definition: MIMXRT1052.h:22485
PWM_Type::VAL0
__IO uint16_t VAL0
Definition: MIMXRT1052.h:35997
GPIO_Type::PSR
__I uint32_t PSR
Definition: MIMXRT1052.h:22481
LCDIF_Type::LUT1_DATA
__IO uint32_t LUT1_DATA
Definition: MIMXRT1052.h:27431
PWM_Type::VAL2
__IO uint16_t VAL2
Definition: MIMXRT1052.h:36001
ENC_Type::WTR
__IO uint16_t WTR
Definition: MIMXRT1052.h:17949
SEMC_Type::NORCR2
__IO uint32_t NORCR2
Definition: MIMXRT1052.h:39757
XBARA_Type::SEL13
__IO uint16_t SEL13
Definition: MIMXRT1052.h:51191
ENC_Type::IMR
__I uint16_t IMR
Definition: MIMXRT1052.h:17960
CMP_Type::MUXCR
__IO uint8_t MUXCR
Definition: MIMXRT1052.h:10273
ADC_ETC_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:1684
DCP_Type::CH3OPTS_CLR
__IO uint32_t CH3OPTS_CLR
Definition: MIMXRT1052.h:12444
DCP_Type::KEY
__IO uint32_t KEY
Definition: MIMXRT1052.h:12380
PMU_Type::MISC1_CLR
__IO uint32_t MISC1_CLR
Definition: MIMXRT1052.h:33490
OCOTP_Type::SW_GP1
__IO uint32_t SW_GP1
Definition: MIMXRT1052.h:32270
WDOG_Type::WICR
__IO uint16_t WICR
Definition: MIMXRT1052.h:50966
LPUART_Type::FIFO
__IO uint32_t FIFO
Definition: MIMXRT1052.h:31158
PXP_Type::PS_CTRL
__IO uint32_t PS_CTRL
Definition: MIMXRT1052.h:37856
ENC_Type::UMOD
__IO uint16_t UMOD
Definition: MIMXRT1052.h:17963
SNVS_Type::HPSR
__IO uint32_t HPSR
Definition: MIMXRT1052.h:41038
DMA_Type::CINT
__O uint8_t CINT
Definition: MIMXRT1052.h:14372
ENET_Type::RMON_T_P65TO127
__I uint32_t RMON_T_P65TO127
Definition: MIMXRT1052.h:18564
OCOTP_Type::MAC0
__IO uint32_t MAC0
Definition: MIMXRT1052.h:32260
PMU_Type::REG_2P5_CLR
__IO uint32_t REG_2P5_CLR
Definition: MIMXRT1052.h:33478
DCDC_Type::REG0
__IO uint32_t REG0
Definition: MIMXRT1052.h:12014
TSC_Type::PRE_CHARGE_TIME
__IO uint32_t PRE_CHARGE_TIME
Definition: MIMXRT1052.h:44744
USDHC_Type::CLK_TUNE_CTRL_STATUS
__IO uint32_t CLK_TUNE_CTRL_STATUS
Definition: MIMXRT1052.h:49087
FLEXIO_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1052.h:20513
DCP_Type::CH1SEMA
__IO uint32_t CH1SEMA
Definition: MIMXRT1052.h:12412
XBARA_Type::CTRL0
__IO uint16_t CTRL0
Definition: MIMXRT1052.h:51244
CCM_ANALOG_Type::PLL_VIDEO_SET
__IO uint32_t PLL_VIDEO_SET
Definition: MIMXRT1052.h:7240
PWM_Type::FRACVAL5
__IO uint16_t FRACVAL5
Definition: MIMXRT1052.h:36006
CCM_ANALOG_Type::PLL_USB2_SET
__IO uint32_t PLL_USB2_SET
Definition: MIMXRT1052.h:7218
XBARA_Type::SEL33
__IO uint16_t SEL33
Definition: MIMXRT1052.h:51211
LCDIF_Type::VDCTRL0
__IO uint32_t VDCTRL0
Definition: MIMXRT1052.h:27379
ENC_Type::FILT
__IO uint16_t FILT
Definition: MIMXRT1052.h:17948
IOMUXC_GPR_Type::GPR8
__IO uint32_t GPR8
Definition: MIMXRT1052.h:24409
USB_ANALOG_Type::VBUS_DETECT_SET
__IO uint32_t VBUS_DETECT_SET
Definition: MIMXRT1052.h:48556
TRNG_Type::SCR4L
__IO uint32_t SCR4L
Definition: MIMXRT1052.h:43990
USBPHY_Type::PWD
__IO uint32_t PWD
Definition: MIMXRT1052.h:47130
USDHC_Type::WTMK_LVL
__IO uint32_t WTMK_LVL
Definition: MIMXRT1052.h:49078
DCP_Type::CH1OPTS_SET
__IO uint32_t CH1OPTS_SET
Definition: MIMXRT1052.h:12419
GPT_Type::PR
__IO uint32_t PR
Definition: MIMXRT1052.h:22973
XBARB_Type::SEL5
__IO uint16_t SEL5
Definition: MIMXRT1052.h:52230
ENET_Type::MIBC
__IO uint32_t MIBC
Definition: MIMXRT1052.h:18517
ENET_Type::IEEE_T_CSERR
__I uint32_t IEEE_T_CSERR
Definition: MIMXRT1052.h:18579
FLEXIO_Type::SHIFTERR
__IO uint32_t SHIFTERR
Definition: MIMXRT1052.h:20517
SEMC_Type::STS15
uint32_t STS15
Definition: MIMXRT1052.h:39789
CCM_Type::CSCDR2
__IO uint32_t CSCDR2
Definition: MIMXRT1052.h:5083
USB_Type::ENDPTSTAT
__I uint32_t ENDPTSTAT
Definition: MIMXRT1052.h:45290
DMA_Type::DCHPRI21
__IO uint8_t DCHPRI21
Definition: MIMXRT1052.h:14404
ENC_Type::LPOSH
__I uint16_t LPOSH
Definition: MIMXRT1052.h:17957
XTALOSC24M_Type::OSC_CONFIG2_SET
__IO uint32_t OSC_CONFIG2_SET
Definition: MIMXRT1052.h:52396
USB_Type::HCSPARAMS
__I uint32_t HCSPARAMS
Definition: MIMXRT1052.h:45256
PXP_Type::OUT_BUF2
__IO uint32_t OUT_BUF2
Definition: MIMXRT1052.h:37842
ENC_Type::TST
__IO uint16_t TST
Definition: MIMXRT1052.h:17961
SEMC_Type::NORCR0
__IO uint32_t NORCR0
Definition: MIMXRT1052.h:39755
I2S_Type::RCR1
__IO uint32_t RCR1
Definition: MIMXRT1052.h:23312
PWM_Type::FFILT
__IO uint16_t FFILT
Definition: MIMXRT1052.h:36045
DMA_Type::DCHPRI27
__IO uint8_t DCHPRI27
Definition: MIMXRT1052.h:14406
CSI_Type::CR2
__IO uint32_t CR2
Definition: MIMXRT1052.h:10540
SEMC_Type::STS5
uint32_t STS5
Definition: MIMXRT1052.h:39779
LPI2C_Type::MCCR1
__IO uint32_t MCCR1
Definition: MIMXRT1052.h:29299
ENET_Type::RSFL
__IO uint32_t RSFL
Definition: MIMXRT1052.h:18541
ENET_Type::TACC
__IO uint32_t TACC
Definition: MIMXRT1052.h:18551
CAN_Type::ESR2
__I uint32_t ESR2
Definition: MIMXRT1052.h:4137
PXP_Type::NEXT
__IO uint32_t NEXT
Definition: MIMXRT1052.h:37896
TEMPMON_Type::TEMPSENSE1
__IO uint32_t TEMPSENSE1
Definition: MIMXRT1052.h:43110
LPI2C_Type::MDER
__IO uint32_t MDER
Definition: MIMXRT1052.h:29289
LPSPI_Type::CFGR0
__IO uint32_t CFGR0
Definition: MIMXRT1052.h:30465
USBPHY_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1052.h:47143
ENET_Type::OPD
__IO uint32_t OPD
Definition: MIMXRT1052.h:18525
SPDIF_Type::SIS
__I uint32_t SIS
Definition: MIMXRT1052.h:42283
CAN_Type::CTRL1
__IO uint32_t CTRL1
Definition: MIMXRT1052.h:4124
iomuxc_sw_pad_ctl_pad_t
enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
DMA_Type::DCHPRI24
__IO uint8_t DCHPRI24
Definition: MIMXRT1052.h:14409
I2S_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1052.h:23298
CCM_ANALOG_Type::MISC0_SET
__IO uint32_t MISC0_SET
Definition: MIMXRT1052.h:7261
DCP_Type::CH0SEMA
__IO uint32_t CH0SEMA
Definition: MIMXRT1052.h:12400
GPT_Type::IR
__IO uint32_t IR
Definition: MIMXRT1052.h:22975
ENET_Type::IEEE_R_DROP
__I uint32_t IEEE_R_DROP
Definition: MIMXRT1052.h:18601
TEMPMON_Type::TEMPSENSE1_SET
__IO uint32_t TEMPSENSE1_SET
Definition: MIMXRT1052.h:43111
FLEXRAM_Type::TCM_CTRL
__IO uint32_t TCM_CTRL
Definition: MIMXRT1052.h:21140
XBARA_Type::SEL2
__IO uint16_t SEL2
Definition: MIMXRT1052.h:51180
LPSPI_Type::IER
__IO uint32_t IER
Definition: MIMXRT1052.h:30463
USBPHY_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1052.h:47144
USBPHY_Type::DEBUG1_TOG
__IO uint32_t DEBUG1_TOG
Definition: MIMXRT1052.h:47157
PWM_Type::FRACVAL3
__IO uint16_t FRACVAL3
Definition: MIMXRT1052.h:36002
SEMC_Type::STS4
uint32_t STS4
Definition: MIMXRT1052.h:39778
XBARA_Type::SEL19
__IO uint16_t SEL19
Definition: MIMXRT1052.h:51197
USB_Type::DCCPARAMS
__I uint32_t DCCPARAMS
Definition: MIMXRT1052.h:45261
ENET_Type::ATOFF
__IO uint32_t ATOFF
Definition: MIMXRT1052.h:18611
CSI_Type::DMASA_STATFIFO
__IO uint32_t DMASA_STATFIFO
Definition: MIMXRT1052.h:10547
DMA_Type::DCHPRI23
__IO uint8_t DCHPRI23
Definition: MIMXRT1052.h:14402
CCM_ANALOG_Type::PLL_USB2_CLR
__IO uint32_t PLL_USB2_CLR
Definition: MIMXRT1052.h:7219
FLEXIO_Type::SHIFTSDEN
__IO uint32_t SHIFTSDEN
Definition: MIMXRT1052.h:20524
PWM_Type::INIT
__IO uint16_t INIT
Definition: MIMXRT1052.h:35993
XTALOSC24M_Type::OSC_CONFIG0_SET
__IO uint32_t OSC_CONFIG0_SET
Definition: MIMXRT1052.h:52388
CCM_Type::CSR
__I uint32_t CSR
Definition: MIMXRT1052.h:5071
CAN_Type::CTRL2
__IO uint32_t CTRL2
Definition: MIMXRT1052.h:4136
LPUART_Type::GLOBAL
__IO uint32_t GLOBAL
Definition: MIMXRT1052.h:31150
LCDIF_Type::CTRL2_CLR
__IO uint32_t CTRL2_CLR
Definition: MIMXRT1052.h:27371
XBARB_Type::SEL6
__IO uint16_t SEL6
Definition: MIMXRT1052.h:52231
PWM_Type::SWCOUT
__IO uint16_t SWCOUT
Definition: MIMXRT1052.h:36039
LCDIF_Type::CTRL1_SET
__IO uint32_t CTRL1_SET
Definition: MIMXRT1052.h:27366
_iomuxc_select_input
_iomuxc_select_input
Enumeration for the IOMUXC select input.
Definition: MIMXRT1052.h:582
USB_Type::HWRXBUF
__I uint32_t HWRXBUF
Definition: MIMXRT1052.h:45245
CCM_ANALOG_Type::PLL_USB1_SET
__IO uint32_t PLL_USB1_SET
Definition: MIMXRT1052.h:7214
PWM_Type::CVAL1
__I uint16_t CVAL1
Definition: MIMXRT1052.h:36025
XBARA_Type::SEL31
__IO uint16_t SEL31
Definition: MIMXRT1052.h:51209
RTWDOG_Type::WIN
__IO uint32_t WIN
Definition: MIMXRT1052.h:39524
SPDIF_Type::SRPC
__IO uint32_t SRPC
Definition: MIMXRT1052.h:42279
PWM_Type::MCTRL
__IO uint16_t MCTRL
Definition: MIMXRT1052.h:36041
DCP_Type::CH1STAT_CLR
__IO uint32_t CH1STAT_CLR
Definition: MIMXRT1052.h:12416
USDHC_Type::PRES_STATE
__I uint32_t PRES_STATE
Definition: MIMXRT1052.h:49070
ENET_Type::PALR
__IO uint32_t PALR
Definition: MIMXRT1052.h:18523
ENET_Type::TSEM
__IO uint32_t TSEM
Definition: MIMXRT1052.h:18545
OCOTP_Type::READ_FUSE_DATA
__IO uint32_t READ_FUSE_DATA
Definition: MIMXRT1052.h:32195
GPIO_Type::DR_CLEAR
__O uint32_t DR_CLEAR
Definition: MIMXRT1052.h:22489
CSI_Type::IMAG_PARA
__IO uint32_t IMAG_PARA
Definition: MIMXRT1052.h:10552
DCP_Type::CH3OPTS_SET
__IO uint32_t CH3OPTS_SET
Definition: MIMXRT1052.h:12443
LPSPI_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1052.h:30459
SEMC_Type::STS0
__I uint32_t STS0
Definition: MIMXRT1052.h:39774
DMA_Type::DCHPRI30
__IO uint8_t DCHPRI30
Definition: MIMXRT1052.h:14411
DMA_Type::DCHPRI0
__IO uint8_t DCHPRI0
Definition: MIMXRT1052.h:14385
SEMC_Type::STS10
uint32_t STS10
Definition: MIMXRT1052.h:39784
CCM_ANALOG_Type::PLL_USB2_TOG
__IO uint32_t PLL_USB2_TOG
Definition: MIMXRT1052.h:7220
LPSPI_Type::FSR
__I uint32_t FSR
Definition: MIMXRT1052.h:30474
LCDIF_Type::PIGEONCTRL2_SET
__IO uint32_t PIGEONCTRL2_SET
Definition: MIMXRT1052.h:27411
TRNG_Type::SCR5C
__I uint32_t SCR5C
Definition: MIMXRT1052.h:43993
XTALOSC24M_Type::OSC_CONFIG2_CLR
__IO uint32_t OSC_CONFIG2_CLR
Definition: MIMXRT1052.h:52397
DCP_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:12362
LCDIF_Type::STAT
__I uint32_t STAT
Definition: MIMXRT1052.h:27395
OCOTP_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1052.h:32188
CSI_Type::DMATS_STATFIFO
__IO uint32_t DMATS_STATFIFO
Definition: MIMXRT1052.h:10548
USB_Type::HCCPARAMS
__I uint32_t HCCPARAMS
Definition: MIMXRT1052.h:45257
SEMC_Type::BMCR1
__IO uint32_t BMCR1
Definition: MIMXRT1052.h:39742
USB_Type::USBSTS
__IO uint32_t USBSTS
Definition: MIMXRT1052.h:45264
LPUART_Type::MATCH
__IO uint32_t MATCH
Definition: MIMXRT1052.h:31156
USDHC_Type::TUNING_CTRL
__IO uint32_t TUNING_CTRL
Definition: MIMXRT1052.h:49092
OCOTP_Type::DATA
__IO uint32_t DATA
Definition: MIMXRT1052.h:32191
SNVS_Type::LPSMCLR
__IO uint32_t LPSMCLR
Definition: MIMXRT1052.h:41057
OCOTP_Type::SRK6
__IO uint32_t SRK6
Definition: MIMXRT1052.h:32252
FLEXSPI_Type::STS2
__I uint32_t STS2
Definition: MIMXRT1052.h:21327
USBPHY_Type::DEBUG_SET
__IO uint32_t DEBUG_SET
Definition: MIMXRT1052.h:47149
OCOTP_Type::SW_GP21
__IO uint32_t SW_GP21
Definition: MIMXRT1052.h:32274
LCDIF_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1052.h:27363
SPDIF_Type::STCSCH
__IO uint32_t STCSCH
Definition: MIMXRT1052.h:42293
IOMUXC_GPR_Type::GPR6
__IO uint32_t GPR6
Definition: MIMXRT1052.h:24407
XBARA_Type::SEL25
__IO uint16_t SEL25
Definition: MIMXRT1052.h:51203
XBARA_Type::SEL48
__IO uint16_t SEL48
Definition: MIMXRT1052.h:51226
TSC_Type::MEASEURE_VALUE
__I uint32_t MEASEURE_VALUE
Definition: MIMXRT1052.h:44748
PXP_Type::OUT_CTRL_CLR
__IO uint32_t OUT_CTRL_CLR
Definition: MIMXRT1052.h:37838
PWM_Type::CVAL0CYC
__I uint16_t CVAL0CYC
Definition: MIMXRT1052.h:36024
OCOTP_Type::CFG5
__IO uint32_t CFG5
Definition: MIMXRT1052.h:32220
EWM_Type::SERV
__O uint8_t SERV
Definition: MIMXRT1052.h:20384
TRNG_Type::VID2
__I uint32_t VID2
Definition: MIMXRT1052.h:44016
LPSPI_Type::SR
__IO uint32_t SR
Definition: MIMXRT1052.h:30462
SEMC_Type::STS8
uint32_t STS8
Definition: MIMXRT1052.h:39782
SEMC_Type::SRAMCR0
__IO uint32_t SRAMCR0
Definition: MIMXRT1052.h:39759
BEE_Type::AES_KEY0_W3
__IO uint32_t AES_KEY0_W3
Definition: MIMXRT1052.h:3782
BEE_Type::CTR_NONCE1_W1
__O uint32_t CTR_NONCE1_W1
Definition: MIMXRT1052.h:3789
XBARA_Type::SEL46
__IO uint16_t SEL46
Definition: MIMXRT1052.h:51224
ENET_Type::RMON_R_P_GTE2048
__I uint32_t RMON_R_P_GTE2048
Definition: MIMXRT1052.h:18599
CSI_Type::DMASA_FB1
__IO uint32_t DMASA_FB1
Definition: MIMXRT1052.h:10549
SEMC_Type::STS14
uint32_t STS14
Definition: MIMXRT1052.h:39788
LCDIF_Type::PIGEONCTRL2_CLR
__IO uint32_t PIGEONCTRL2_CLR
Definition: MIMXRT1052.h:27412
PWM_Type::VAL5
__IO uint16_t VAL5
Definition: MIMXRT1052.h:36007
PWM_Type::CVAL3
__I uint16_t CVAL3
Definition: MIMXRT1052.h:36029
DCP_Type::CH2OPTS_SET
__IO uint32_t CH2OPTS_SET
Definition: MIMXRT1052.h:12431
ENET_Type::IEEE_T_FDXFC
__I uint32_t IEEE_T_FDXFC
Definition: MIMXRT1052.h:18581
OCOTP_Type::SCS_CLR
__IO uint32_t SCS_CLR
Definition: MIMXRT1052.h:32201
DMA_Type::DCHPRI26
__IO uint8_t DCHPRI26
Definition: MIMXRT1052.h:14407
FLEXIO_Type::SHIFTSTATE
__IO uint32_t SHIFTSTATE
Definition: MIMXRT1052.h:20526
ENET_Type::RMON_T_COL
__I uint32_t RMON_T_COL
Definition: MIMXRT1052.h:18562
TRNG_Type::PKRSQ
__I uint32_t PKRSQ
Definition: MIMXRT1052.h:43960
XBARB_Type::SEL7
__IO uint16_t SEL7
Definition: MIMXRT1052.h:52232
SEMC_Type::STS3
uint32_t STS3
Definition: MIMXRT1052.h:39777
XBARA_Type::SEL38
__IO uint16_t SEL38
Definition: MIMXRT1052.h:51216
USDHC_Type::CMD_ARG
__IO uint32_t CMD_ARG
Definition: MIMXRT1052.h:49063
KPP_Type::KPCR
__IO uint16_t KPCR
Definition: MIMXRT1052.h:27208
CCM_ANALOG_Type::PLL_SYS
__IO uint32_t PLL_SYS
Definition: MIMXRT1052.h:7221
SEMC_Type::DBICR1
__IO uint32_t DBICR1
Definition: MIMXRT1052.h:39764
I2S_Type::TCR5
__IO uint32_t TCR5
Definition: MIMXRT1052.h:23304
USBPHY_Type::DEBUGr
__IO uint32_t DEBUGr
Definition: MIMXRT1052.h:47148
CCM_ANALOG_Type::MISC1_SET
__IO uint32_t MISC1_SET
Definition: MIMXRT1052.h:7265
OCOTP_Type::MAC1
__IO uint32_t MAC1
Definition: MIMXRT1052.h:32262
SEMC_Type::STS1
uint32_t STS1
Definition: MIMXRT1052.h:39775
DMA_Type::EARS
__IO uint32_t EARS
Definition: MIMXRT1052.h:14380
GPIO_Type::GDIR
__IO uint32_t GDIR
Definition: MIMXRT1052.h:22480
DCP_Type::CH0OPTS_CLR
__IO uint32_t CH0OPTS_CLR
Definition: MIMXRT1052.h:12408
PMU_Type::MISC1
__IO uint32_t MISC1
Definition: MIMXRT1052.h:33488
ENET_Type::RMON_R_OVERSIZE
__I uint32_t RMON_R_OVERSIZE
Definition: MIMXRT1052.h:18589
EWM_Type::CMPH
__IO uint8_t CMPH
Definition: MIMXRT1052.h:20386
CCM_Type::CCGR5
__IO uint32_t CCGR5
Definition: MIMXRT1052.h:5098
USDHC_Type::CMD_RSP0
__I uint32_t CMD_RSP0
Definition: MIMXRT1052.h:49065
LPI2C_Type::SCFGR2
__IO uint32_t SCFGR2
Definition: MIMXRT1052.h:29313
FLEXSPI_Type::IPTXFCR
__IO uint32_t IPTXFCR
Definition: MIMXRT1052.h:21322
LPI2C_Type::SCFGR1
__IO uint32_t SCFGR1
Definition: MIMXRT1052.h:29312
USB_ANALOG_Type::CHRG_DETECT
__IO uint32_t CHRG_DETECT
Definition: MIMXRT1052.h:48559
PGC_Type::MEGA_PDNSCR
__IO uint32_t MEGA_PDNSCR
Definition: MIMXRT1052.h:33153
CCM_ANALOG_Type::PLL_VIDEO
__IO uint32_t PLL_VIDEO
Definition: MIMXRT1052.h:7239
PMU_Type::MISC0
__IO uint32_t MISC0
Definition: MIMXRT1052.h:33484
PXP_Type::PS_CLRKEYHIGH
__IO uint32_t PS_CLRKEYHIGH
Definition: MIMXRT1052.h:37876
LPI2C_Type::SRDR
__I uint32_t SRDR
Definition: MIMXRT1052.h:29322
ENET_Type::RMON_T_P1024TO2047
__I uint32_t RMON_T_P1024TO2047
Definition: MIMXRT1052.h:18568
BEE_Type::CTR_NONCE0_W3
__O uint32_t CTR_NONCE0_W3
Definition: MIMXRT1052.h:3787
LPSPI_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1052.h:30458
ENET_Type::ATPER
__IO uint32_t ATPER
Definition: MIMXRT1052.h:18612
DMA_Type::CDNE
__O uint8_t CDNE
Definition: MIMXRT1052.h:14369
DMA_Type::CITER_ELINKNO
__IO uint16_t CITER_ELINKNO
Definition: MIMXRT1052.h:14428
PWM_Type::DTCNT1
__IO uint16_t DTCNT1
Definition: MIMXRT1052.h:36016
DCP_Type::CH1STAT_SET
__IO uint32_t CH1STAT_SET
Definition: MIMXRT1052.h:12415
USB_ANALOG_Type::MISC_TOG
__IO uint32_t MISC_TOG
Definition: MIMXRT1052.h:48574
CCM_ANALOG_Type::PLL_SYS_DENOM
__IO uint32_t PLL_SYS_DENOM
Definition: MIMXRT1052.h:7229
CCM_ANALOG_Type::PLL_SYS_TOG
__IO uint32_t PLL_SYS_TOG
Definition: MIMXRT1052.h:7224
SEMC_Type::INTEN
__IO uint32_t INTEN
Definition: MIMXRT1052.h:39745
LCDIF_Type::PIGEONCTRL1_TOG
__IO uint32_t PIGEONCTRL1_TOG
Definition: MIMXRT1052.h:27409
XBARA_Type::SEL44
__IO uint16_t SEL44
Definition: MIMXRT1052.h:51222
CCM_ANALOG_Type::PLL_USB2
__IO uint32_t PLL_USB2
Definition: MIMXRT1052.h:7217
XBARA_Type::SEL18
__IO uint16_t SEL18
Definition: MIMXRT1052.h:51196
ADC_ETC_Type::TRIGn_RESULT_5_4
__I uint32_t TRIGn_RESULT_5_4
Definition: MIMXRT1052.h:1697
CCM_ANALOG_Type::PLL_SYS_SET
__IO uint32_t PLL_SYS_SET
Definition: MIMXRT1052.h:7222
XTALOSC24M_Type::OSC_CONFIG1_SET
__IO uint32_t OSC_CONFIG1_SET
Definition: MIMXRT1052.h:52392
TRNG_Type::SCML
__IO uint32_t SCML
Definition: MIMXRT1052.h:43974
TSC_Type::INT_EN
__IO uint32_t INT_EN
Definition: MIMXRT1052.h:44750
CCM_Type::CDCDR
__IO uint32_t CDCDR
Definition: MIMXRT1052.h:5081
XBARA_Type::SEL52
__IO uint16_t SEL52
Definition: MIMXRT1052.h:51230
PMU_Type::REG_3P0
__IO uint32_t REG_3P0
Definition: MIMXRT1052.h:33472
CSI_Type::CR1
__IO uint32_t CR1
Definition: MIMXRT1052.h:10539
EWM_Type::CMPL
__IO uint8_t CMPL
Definition: MIMXRT1052.h:20385
DMA_Type::SSRT
__O uint8_t SSRT
Definition: MIMXRT1052.h:14370
DCP_Type::CH2STAT_TOG
__IO uint32_t CH2STAT_TOG
Definition: MIMXRT1052.h:12429
CAN_Type::WORD0
__IO uint32_t WORD0
Definition: MIMXRT1052.h:4149
DMA_Type::NBYTES_MLNO
__IO uint32_t NBYTES_MLNO
Definition: MIMXRT1052.h:14420
DCP_Type::CH3OPTS
__IO uint32_t CH3OPTS
Definition: MIMXRT1052.h:12442
CSI_Type::CR3
__IO uint32_t CR3
Definition: MIMXRT1052.h:10541
IOMUXC_GPR_Type::GPR2
__IO uint32_t GPR2
Definition: MIMXRT1052.h:24403
ENET_Type::IEEE_T_MACERR
__I uint32_t IEEE_T_MACERR
Definition: MIMXRT1052.h:18578
IOMUXC_GPR_Type::GPR15
uint32_t GPR15
Definition: MIMXRT1052.h:24416
CAN_Type::IFLAG2
__IO uint32_t IFLAG2
Definition: MIMXRT1052.h:4134
USDHC_Type::AUTOCMD12_ERR_STATUS
__IO uint32_t AUTOCMD12_ERR_STATUS
Definition: MIMXRT1052.h:49076
DCP_Type::CH3SEMA
__IO uint32_t CH3SEMA
Definition: MIMXRT1052.h:12436
TRNG_Type::FRQCNT
__I uint32_t FRQCNT
Definition: MIMXRT1052.h:43969
LCDIF_Type::RGB_ADJUST_SET
__IO uint32_t RGB_ADJUST_SET
Definition: MIMXRT1052.h:27398
USDHC_Type::VEND_SPEC
__IO uint32_t VEND_SPEC
Definition: MIMXRT1052.h:49089
IOMUXC_GPR_Type::GPR0
uint32_t GPR0
Definition: MIMXRT1052.h:24401
DCP_Type::CH0STAT_TOG
__IO uint32_t CH0STAT_TOG
Definition: MIMXRT1052.h:12405
DCP_Type::CH1STAT
__IO uint32_t CH1STAT
Definition: MIMXRT1052.h:12414
CAN_Type::ESR1
__IO uint32_t ESR1
Definition: MIMXRT1052.h:4131
LPUART_Type::PARAM
__I uint32_t PARAM
Definition: MIMXRT1052.h:31149
PXP_Type::PS_UBUF
__IO uint32_t PS_UBUF
Definition: MIMXRT1052.h:37862
USDHC_Type::DS_ADDR
__IO uint32_t DS_ADDR
Definition: MIMXRT1052.h:49061
LPI2C_Type::STAR
__IO uint32_t STAR
Definition: MIMXRT1052.h:29318
PMU_Type::MISC2_TOG
__IO uint32_t MISC2_TOG
Definition: MIMXRT1052.h:33495
DCP_Type::CH3STAT_TOG
__IO uint32_t CH3STAT_TOG
Definition: MIMXRT1052.h:12441
GPC_Type::IMR5
__IO uint32_t IMR5
Definition: MIMXRT1052.h:22342
CCM_ANALOG_Type::PLL_SYS_NUM
__IO uint32_t PLL_SYS_NUM
Definition: MIMXRT1052.h:7227
CAN_Type::ID
__IO uint32_t ID
Definition: MIMXRT1052.h:4148
USB_Type::SBUSCFG
__IO uint32_t SBUSCFG
Definition: MIMXRT1052.h:45251
DCP_Type::CH0STAT_CLR
__IO uint32_t CH0STAT_CLR
Definition: MIMXRT1052.h:12404
SNVS_Type::LPSRTCMR
__IO uint32_t LPSRTCMR
Definition: MIMXRT1052.h:41053
USDHC_Type::HOST_CTRL_CAP
__IO uint32_t HOST_CTRL_CAP
Definition: MIMXRT1052.h:49077
ADC_ETC_Type::TRIGn_RESULT_3_2
__I uint32_t TRIGn_RESULT_3_2
Definition: MIMXRT1052.h:1696
PMU_Type::REG_3P0_CLR
__IO uint32_t REG_3P0_CLR
Definition: MIMXRT1052.h:33474
DMA_Type::SADDR
__IO uint32_t SADDR
Definition: MIMXRT1052.h:14416
USDHC_Type::ADMA_ERR_STATUS
__I uint32_t ADMA_ERR_STATUS
Definition: MIMXRT1052.h:49082
OCOTP_Type::MEM2
__IO uint32_t MEM2
Definition: MIMXRT1052.h:32228
SNVS_Type::LPCR
__IO uint32_t LPCR
Definition: MIMXRT1052.h:41047
FLEXSPI_Type::IPCR0
__IO uint32_t IPCR0
Definition: MIMXRT1052.h:21316
TMR_Type::COMP2
__IO uint16_t COMP2
Definition: MIMXRT1052.h:43412
CCM_ANALOG_Type::MISC1
__IO uint32_t MISC1
Definition: MIMXRT1052.h:7264
DMA_Type::SEEI
__O uint8_t SEEI
Definition: MIMXRT1052.h:14366
USDHC_Type::MIX_CTRL
__IO uint32_t MIX_CTRL
Definition: MIMXRT1052.h:49079
ENET_Type::TDAR
__IO uint32_t TDAR
Definition: MIMXRT1052.h:18510
ENC_Type::REVH
__I uint16_t REVH
Definition: MIMXRT1052.h:17953
USDHC_Type::FORCE_EVENT
__O uint32_t FORCE_EVENT
Definition: MIMXRT1052.h:49081
XBARA_Type::SEL59
__IO uint16_t SEL59
Definition: MIMXRT1052.h:51237
CCM_ANALOG_Type::PLL_VIDEO_CLR
__IO uint32_t PLL_VIDEO_CLR
Definition: MIMXRT1052.h:7241
LPI2C_Type::SIER
__IO uint32_t SIER
Definition: MIMXRT1052.h:29309
XBARA_Type::SEL40
__IO uint16_t SEL40
Definition: MIMXRT1052.h:51218
OCOTP_Type::CFG6
__IO uint32_t CFG6
Definition: MIMXRT1052.h:32222
OCOTP_Type::MEM1
__IO uint32_t MEM1
Definition: MIMXRT1052.h:32226
IOMUXC_GPR_Type::GPR18
__IO uint32_t GPR18
Definition: MIMXRT1052.h:24419
DMA_Type::SERQ
__O uint8_t SERQ
Definition: MIMXRT1052.h:14368
CCM_Type::CSCDR3
__IO uint32_t CSCDR3
Definition: MIMXRT1052.h:5084
TRNG_Type::SDCTL
__IO uint32_t SDCTL
Definition: MIMXRT1052.h:43962
PXP_Type::POWER
__IO uint32_t POWER
Definition: MIMXRT1052.h:37894
PMU_Type::REG_2P5_SET
__IO uint32_t REG_2P5_SET
Definition: MIMXRT1052.h:33477
SEMC_Type::NORCR3
uint32_t NORCR3
Definition: MIMXRT1052.h:39758
PMU_Type::MISC2
__IO uint32_t MISC2
Definition: MIMXRT1052.h:33492
LCDIF_Type::PIGEON_2
__IO uint32_t PIGEON_2
Definition: MIMXRT1052.h:27420
PMU_Type::REG_3P0_TOG
__IO uint32_t REG_3P0_TOG
Definition: MIMXRT1052.h:33475
SEMC_Type::STS6
uint32_t STS6
Definition: MIMXRT1052.h:39780
LPSPI_Type::RDR
__I uint32_t RDR
Definition: MIMXRT1052.h:30479
USDHC_Type::CMD_RSP2
__I uint32_t CMD_RSP2
Definition: MIMXRT1052.h:49067
PXP_Type::OUT_PS_ULC
__IO uint32_t OUT_PS_ULC
Definition: MIMXRT1052.h:37848
DMA_Type::DCHPRI20
__IO uint8_t DCHPRI20
Definition: MIMXRT1052.h:14405
ADC_Type::HS
__I uint32_t HS
Definition: MIMXRT1052.h:1300
LPUART_Type::MODIR
__IO uint32_t MODIR
Definition: MIMXRT1052.h:31157
ENET_Type::TDSR
__IO uint32_t TDSR
Definition: MIMXRT1052.h:18538
DMA_Type::CERQ
__O uint8_t CERQ
Definition: MIMXRT1052.h:14367
GPIO_Type::ICR2
__IO uint32_t ICR2
Definition: MIMXRT1052.h:22483
DMA_Type::DCHPRI28
__IO uint8_t DCHPRI28
Definition: MIMXRT1052.h:14413
XTALOSC24M_Type::OSC_CONFIG2
__IO uint32_t OSC_CONFIG2
Definition: MIMXRT1052.h:52395
USBPHY_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:47142
DCP_Type::CH1OPTS
__IO uint32_t CH1OPTS
Definition: MIMXRT1052.h:12418
SEMC_Type::SRAMCR1
__IO uint32_t SRAMCR1
Definition: MIMXRT1052.h:39760
BEE_Type::CTR_NONCE1_W0
__O uint32_t CTR_NONCE1_W0
Definition: MIMXRT1052.h:3788
SPDIF_Type::SRCSL
__I uint32_t SRCSL
Definition: MIMXRT1052.h:42288
USB_ANALOG_Type::MISC
__IO uint32_t MISC
Definition: MIMXRT1052.h:48571
BEE_Type::ADDR_OFFSET1
__IO uint32_t ADDR_OFFSET1
Definition: MIMXRT1052.h:3778
ADC_ETC_Type::DONE2_3_ERR_IRQ
__IO uint32_t DONE2_3_ERR_IRQ
Definition: MIMXRT1052.h:1686
ENET_Type::IEEE_T_1COL
__I uint32_t IEEE_T_1COL
Definition: MIMXRT1052.h:18573
SNVS_Type::HPCR
__IO uint32_t HPCR
Definition: MIMXRT1052.h:41035
PWM_Type::CTRL2
__IO uint16_t CTRL2
Definition: MIMXRT1052.h:35994
USB_Type::CONFIGFLAG
__I uint32_t CONFIGFLAG
Definition: MIMXRT1052.h:45282
ENET_Type::IAUR
__IO uint32_t IAUR
Definition: MIMXRT1052.h:18530
SEMC_Type::IPCR0
__IO uint32_t IPCR0
Definition: MIMXRT1052.h:39766
DMA_Type::SLAST
__IO int32_t SLAST
Definition: MIMXRT1052.h:14424
USB_ANALOG_Type::LOOPBACK_SET
__IO uint32_t LOOPBACK_SET
Definition: MIMXRT1052.h:48568
LCDIF_Type::LUT1_ADDR
__IO uint32_t LUT1_ADDR
Definition: MIMXRT1052.h:27429
DCP_Type::CH2CMDPTR
__IO uint32_t CH2CMDPTR
Definition: MIMXRT1052.h:12422
CCM_ANALOG_Type::PLL_ENET_SET
__IO uint32_t PLL_ENET_SET
Definition: MIMXRT1052.h:7248
ENET_Type::RMON_R_BC_PKT
__I uint32_t RMON_R_BC_PKT
Definition: MIMXRT1052.h:18585
OCOTP_Type::MEM0
__IO uint32_t MEM0
Definition: MIMXRT1052.h:32224
CCM_ANALOG_Type::PLL_VIDEO_NUM
__IO uint32_t PLL_VIDEO_NUM
Definition: MIMXRT1052.h:7243
LCDIF_Type::CRC_STAT
__IO uint32_t CRC_STAT
Definition: MIMXRT1052.h:27393
TEMPMON_Type::TEMPSENSE2_TOG
__IO uint32_t TEMPSENSE2_TOG
Definition: MIMXRT1052.h:43118
CCM_ANALOG_Type::PLL_ARM_SET
__IO uint32_t PLL_ARM_SET
Definition: MIMXRT1052.h:7210
ENET_Type::RMON_T_MC_PKT
__I uint32_t RMON_T_MC_PKT
Definition: MIMXRT1052.h:18556
ENET_Type::RMON_R_P512TO1023
__I uint32_t RMON_R_P512TO1023
Definition: MIMXRT1052.h:18597
DCDC_Type::REG3
__IO uint32_t REG3
Definition: MIMXRT1052.h:12017
OCOTP_Type::SCS
__IO uint32_t SCS
Definition: MIMXRT1052.h:32199
XBARA_Type::SEL20
__IO uint16_t SEL20
Definition: MIMXRT1052.h:51198
XBARA_Type::SEL10
__IO uint16_t SEL10
Definition: MIMXRT1052.h:51188
ENET_Type::RDAR
__IO uint32_t RDAR
Definition: MIMXRT1052.h:18509
TMR_Type::CMPLD1
__IO uint16_t CMPLD1
Definition: MIMXRT1052.h:43419
SNVS_Type::LPGPR0_LEGACY_ALIAS
__IO uint32_t LPGPR0_LEGACY_ALIAS
Definition: MIMXRT1052.h:41059
CAN_Type::IMASK1
__IO uint32_t IMASK1
Definition: MIMXRT1052.h:4133
USB_Type::ENDPTPRIME
__IO uint32_t ENDPTPRIME
Definition: MIMXRT1052.h:45288
XBARA_Type::SEL64
__IO uint16_t SEL64
Definition: MIMXRT1052.h:51242
DCP_Type::CTRL_CLR
__IO uint32_t CTRL_CLR
Definition: MIMXRT1052.h:12364
ENET_Type::RMON_R_P128TO255
__I uint32_t RMON_R_P128TO255
Definition: MIMXRT1052.h:18595
USB_ANALOG_Type::CHRG_DETECT_CLR
__IO uint32_t CHRG_DETECT_CLR
Definition: MIMXRT1052.h:48561
FLEXSPI_Type::IPRXFCR
__IO uint32_t IPRXFCR
Definition: MIMXRT1052.h:21321
DMA_Type::DCHPRI15
__IO uint8_t DCHPRI15
Definition: MIMXRT1052.h:14394
SNVS_Type::LPSRTCLR
__IO uint32_t LPSRTCLR
Definition: MIMXRT1052.h:41054
PWM_Type::CVAL2CYC
__I uint16_t CVAL2CYC
Definition: MIMXRT1052.h:36028
I2S_Type::RMR
__IO uint32_t RMR
Definition: MIMXRT1052.h:23321
CCM_ANALOG_Type::PFD_480_TOG
__IO uint32_t PFD_480_TOG
Definition: MIMXRT1052.h:7254
PWM_Type::FSTS
__IO uint16_t FSTS
Definition: MIMXRT1052.h:36044
USB_Type::GPTIMER1LD
__IO uint32_t GPTIMER1LD
Definition: MIMXRT1052.h:45249
XBARA_Type::SEL8
__IO uint16_t SEL8
Definition: MIMXRT1052.h:51186
XBARA_Type::SEL41
__IO uint16_t SEL41
Definition: MIMXRT1052.h:51219
DCDC_Type::REG1
__IO uint32_t REG1
Definition: MIMXRT1052.h:12015
OCOTP_Type::SRK7
__IO uint32_t SRK7
Definition: MIMXRT1052.h:32254
CCM_ANALOG_Type::PLL_ARM_TOG
__IO uint32_t PLL_ARM_TOG
Definition: MIMXRT1052.h:7212
LCDIF_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:27361
PGC_Type::MEGA_CTRL
__IO uint32_t MEGA_CTRL
Definition: MIMXRT1052.h:33151
CCM_ANALOG_Type::PFD_480_CLR
__IO uint32_t PFD_480_CLR
Definition: MIMXRT1052.h:7253
ENC_Type::UPOS
__IO uint16_t UPOS
Definition: MIMXRT1052.h:17954
PXP_Type::OUT_AS_LRC
__IO uint32_t OUT_AS_LRC
Definition: MIMXRT1052.h:37854
DCP_Type::CH0STAT
__IO uint32_t CH0STAT
Definition: MIMXRT1052.h:12402
SRC_Type::SRSR
__IO uint32_t SRSR
Definition: MIMXRT1052.h:42851
LPI2C_Type::MTDR
__O uint32_t MTDR
Definition: MIMXRT1052.h:29303
LCDIF_Type::PIGEONCTRL1_SET
__IO uint32_t PIGEONCTRL1_SET
Definition: MIMXRT1052.h:27407
PGC_Type::CPU_SR
__IO uint32_t CPU_SR
Definition: MIMXRT1052.h:33159
DMA_Type::CEEI
__O uint8_t CEEI
Definition: MIMXRT1052.h:14365
SPDIF_Type::SRCD
__IO uint32_t SRCD
Definition: MIMXRT1052.h:42278
USBPHY_Type::VERSION
__I uint32_t VERSION
Definition: MIMXRT1052.h:47158
ENET_Type::RDSR
__IO uint32_t RDSR
Definition: MIMXRT1052.h:18537
USB_ANALOG_Type::LOOPBACK_CLR
__IO uint32_t LOOPBACK_CLR
Definition: MIMXRT1052.h:48569
PXP_Type::AS_BUF
__IO uint32_t AS_BUF
Definition: MIMXRT1052.h:37880
PXP_Type::STAT_SET
__IO uint32_t STAT_SET
Definition: MIMXRT1052.h:37833
USBNC_Type::USB_OTGn_CTRL
__IO uint32_t USB_OTGn_CTRL
Definition: MIMXRT1052.h:46982
DMA_Type::ES
__I uint32_t ES
Definition: MIMXRT1052.h:14360
TRNG_Type::PKRMAX
__IO uint32_t PKRMAX
Definition: MIMXRT1052.h:43959
ENET_Type::IEEE_R_MACERR
__I uint32_t IEEE_R_MACERR
Definition: MIMXRT1052.h:18605
PWM_Type::CVAL4CYC
__I uint16_t CVAL4CYC
Definition: MIMXRT1052.h:36032
LCDIF_Type::PIGEONCTRL0_CLR
__IO uint32_t PIGEONCTRL0_CLR
Definition: MIMXRT1052.h:27404
XBARA_Type::SEL49
__IO uint16_t SEL49
Definition: MIMXRT1052.h:51227
FLEXIO_Type::TIMSTAT
__IO uint32_t TIMSTAT
Definition: MIMXRT1052.h:20518
PMU_Type::REG_CORE_TOG
__IO uint32_t REG_CORE_TOG
Definition: MIMXRT1052.h:33483
DMA_Type::DCHPRI6
__IO uint8_t DCHPRI6
Definition: MIMXRT1052.h:14387
TSC_Type::FLOW_CONTROL
__IO uint32_t FLOW_CONTROL
Definition: MIMXRT1052.h:44746
SEMC_Type::NANDCR1
__IO uint32_t NANDCR1
Definition: MIMXRT1052.h:39752
FLEXIO_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1052.h:20512
PXP_Type::PS_VBUF
__IO uint32_t PS_VBUF
Definition: MIMXRT1052.h:37864
USDHC_Type::INT_SIGNAL_EN
__IO uint32_t INT_SIGNAL_EN
Definition: MIMXRT1052.h:49075
ADC_Type::GS
__IO uint32_t GS
Definition: MIMXRT1052.h:1304
DMA_Type::DCHPRI1
__IO uint8_t DCHPRI1
Definition: MIMXRT1052.h:14384
AOI_Type::BFCRT23
__IO uint16_t BFCRT23
Definition: MIMXRT1052.h:3553
XBARB_Type::SEL4
__IO uint16_t SEL4
Definition: MIMXRT1052.h:52229
FLEXSPI_Type::INTEN
__IO uint32_t INTEN
Definition: MIMXRT1052.h:21304
OCOTP_Type::MEM4
__IO uint32_t MEM4
Definition: MIMXRT1052.h:32232
USB_Type::ENDPTNAKEN
__IO uint32_t ENDPTNAKEN
Definition: MIMXRT1052.h:45281
ENET_Type::ATCR
__IO uint32_t ATCR
Definition: MIMXRT1052.h:18609
CCM_ANALOG_Type::MISC2_CLR
__IO uint32_t MISC2_CLR
Definition: MIMXRT1052.h:7270
LCDIF_Type::PIGEONCTRL0
__IO uint32_t PIGEONCTRL0
Definition: MIMXRT1052.h:27402
PWM_Type::VAL3
__IO uint16_t VAL3
Definition: MIMXRT1052.h:36003
ENET_Type::RMON_R_MC_PKT
__I uint32_t RMON_R_MC_PKT
Definition: MIMXRT1052.h:18586
PWM_Type::TCTRL
__IO uint16_t TCTRL
Definition: MIMXRT1052.h:36013
DCP_Type::CHANNELCTRL_SET
__IO uint32_t CHANNELCTRL_SET
Definition: MIMXRT1052.h:12371
USB_Type::USBINTR
__IO uint32_t USBINTR
Definition: MIMXRT1052.h:45265
I2S_Type::RCR2
__IO uint32_t RCR2
Definition: MIMXRT1052.h:23313
TRNG_Type::TOTSAM
__I uint32_t TOTSAM
Definition: MIMXRT1052.h:43965
XBARA_Type::SEL21
__IO uint16_t SEL21
Definition: MIMXRT1052.h:51199
IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_STBY_REQ
__IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ
Definition: MIMXRT1052.h:26541
USB_Type::GPTIMER0LD
__IO uint32_t GPTIMER0LD
Definition: MIMXRT1052.h:45247
ENET_Type::MSCR
__IO uint32_t MSCR
Definition: MIMXRT1052.h:18515
I2S_Type::TCSR
__IO uint32_t TCSR
Definition: MIMXRT1052.h:23299
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_STBY_REQ
__IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ
Definition: MIMXRT1052.h:26547
ENC_Type::UINIT
__IO uint16_t UINIT
Definition: MIMXRT1052.h:17958
PIT_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1052.h:33299
DCP_Type::CH1CMDPTR
__IO uint32_t CH1CMDPTR
Definition: MIMXRT1052.h:12410
PXP_Type::STAT_TOG
__IO uint32_t STAT_TOG
Definition: MIMXRT1052.h:37835
CCM_Type::CCR
__IO uint32_t CCR
Definition: MIMXRT1052.h:5069
WDOG_Type::WRSR
__I uint16_t WRSR
Definition: MIMXRT1052.h:50965
ENET_Type::RMON_T_CRC_ALIGN
__I uint32_t RMON_T_CRC_ALIGN
Definition: MIMXRT1052.h:18557
TRNG_Type::STATUS
__I uint32_t STATUS
Definition: MIMXRT1052.h:44000
DMA_Type::DOFF
__IO uint16_t DOFF
Definition: MIMXRT1052.h:14426
DCP_Type::CTRL_TOG
__IO uint32_t CTRL_TOG
Definition: MIMXRT1052.h:12365
PWM_Type::CVAL4
__I uint16_t CVAL4
Definition: MIMXRT1052.h:36031
PWM_Type::DTSRCSEL
__IO uint16_t DTSRCSEL
Definition: MIMXRT1052.h:36040
USDHC_Type::CMD_RSP3
__I uint32_t CMD_RSP3
Definition: MIMXRT1052.h:49068
OCOTP_Type::LOCK
__IO uint32_t LOCK
Definition: MIMXRT1052.h:32208
USB_ANALOG_Type::LOOPBACK_TOG
__IO uint32_t LOOPBACK_TOG
Definition: MIMXRT1052.h:48570
SEMC_Type::SDRAMCR3
__IO uint32_t SDRAMCR3
Definition: MIMXRT1052.h:39750
DMA_Type::DCHPRI13
__IO uint8_t DCHPRI13
Definition: MIMXRT1052.h:14396
ENET_Type::TAFL
__IO uint32_t TAFL
Definition: MIMXRT1052.h:18547
USB_ANALOG_Type::VBUS_DETECT_CLR
__IO uint32_t VBUS_DETECT_CLR
Definition: MIMXRT1052.h:48557
SNVS_Type::LPSVCR
__IO uint32_t LPSVCR
Definition: MIMXRT1052.h:41049
XTALOSC24M_Type::LOWPWR_CTRL_SET
__IO uint32_t LOWPWR_CTRL_SET
Definition: MIMXRT1052.h:52383
SNVS_Type::HPVIDR2
__I uint32_t HPVIDR2
Definition: MIMXRT1052.h:41067
DCP_Type::VERSION
__I uint32_t VERSION
Definition: MIMXRT1052.h:12453
USDHC_Type::VEND_SPEC2
__IO uint32_t VEND_SPEC2
Definition: MIMXRT1052.h:49091
SRC_Type::SBMR2
__I uint32_t SBMR2
Definition: MIMXRT1052.h:42853
XBARA_Type::SEL30
__IO uint16_t SEL30
Definition: MIMXRT1052.h:51208
USDHC_Type::DLL_CTRL
__IO uint32_t DLL_CTRL
Definition: MIMXRT1052.h:49085
USBPHY_Type::PWD_TOG
__IO uint32_t PWD_TOG
Definition: MIMXRT1052.h:47133
SNVS_Type::HPHACIVR
__IO uint32_t HPHACIVR
Definition: MIMXRT1052.h:41040
SEMC_Type::SDRAMCR2
__IO uint32_t SDRAMCR2
Definition: MIMXRT1052.h:39749
LPSPI_Type::DMR1
__IO uint32_t DMR1
Definition: MIMXRT1052.h:30469
ENET_Type::EIMR
__IO uint32_t EIMR
Definition: MIMXRT1052.h:18507
DCP_Type::PACKET4
__I uint32_t PACKET4
Definition: MIMXRT1052.h:12392
PWM_Type::VAL4
__IO uint16_t VAL4
Definition: MIMXRT1052.h:36005
LPI2C_Type::SASR
__I uint32_t SASR
Definition: MIMXRT1052.h:29317
XBARA_Type::SEL3
__IO uint16_t SEL3
Definition: MIMXRT1052.h:51181
USB_ANALOG_Type::VBUS_DETECT_STAT
__I uint32_t VBUS_DETECT_STAT
Definition: MIMXRT1052.h:48563
SNVS_Type::HPRTCMR
__IO uint32_t HPRTCMR
Definition: MIMXRT1052.h:41042
FLEXSPI_Type::FLSHCR4
__IO uint32_t FLSHCR4
Definition: MIMXRT1052.h:21314
TRNG_Type::PKRCNT98
__I uint32_t PKRCNT98
Definition: MIMXRT1052.h:44006
ENET_Type::TFWR
__IO uint32_t TFWR
Definition: MIMXRT1052.h:18535
TRNG_Type::PKRCNT10
__I uint32_t PKRCNT10
Definition: MIMXRT1052.h:44002
ENET_Type::IEEE_R_FRAME_OK
__I uint32_t IEEE_R_FRAME_OK
Definition: MIMXRT1052.h:18602
OCOTP_Type::SRK2
__IO uint32_t SRK2
Definition: MIMXRT1052.h:32244
ENET_Type::IALR
__IO uint32_t IALR
Definition: MIMXRT1052.h:18531
CCM_Type::CSCDR1
__IO uint32_t CSCDR1
Definition: MIMXRT1052.h:5078
TRNG_Type::SCR6PC
__I uint32_t SCR6PC
Definition: MIMXRT1052.h:43997
USBPHY_Type::DEBUG1_SET
__IO uint32_t DEBUG1_SET
Definition: MIMXRT1052.h:47155
LCDIF_Type::RGB_ADJUST_CLR
__IO uint32_t RGB_ADJUST_CLR
Definition: MIMXRT1052.h:27399
CCM_ANALOG_Type::PLL_AUDIO_DENOM
__IO uint32_t PLL_AUDIO_DENOM
Definition: MIMXRT1052.h:7237
IOMUXC_GPR_Type::GPR7
__IO uint32_t GPR7
Definition: MIMXRT1052.h:24408
DCP_Type::CH2STAT
__IO uint32_t CH2STAT
Definition: MIMXRT1052.h:12426
LPSPI_Type::RSR
__I uint32_t RSR
Definition: MIMXRT1052.h:30478
AIPSTZ_Type::OPACR4
__IO uint32_t OPACR4
Definition: MIMXRT1052.h:2807
PWM_Type::CVAL5CYC
__I uint16_t CVAL5CYC
Definition: MIMXRT1052.h:36034
XBARA_Type::SEL61
__IO uint16_t SEL61
Definition: MIMXRT1052.h:51239
SPDIF_Type::SCR
__IO uint32_t SCR
Definition: MIMXRT1052.h:42277
SEMC_Type::NANDCR3
__IO uint32_t NANDCR3
Definition: MIMXRT1052.h:39754
PWM_Type::FCTRL
__IO uint16_t FCTRL
Definition: MIMXRT1052.h:36043
XTALOSC24M_Type::OSC_CONFIG0_CLR
__IO uint32_t OSC_CONFIG0_CLR
Definition: MIMXRT1052.h:52389
DCP_Type::CH0STAT_SET
__IO uint32_t CH0STAT_SET
Definition: MIMXRT1052.h:12403
XBARA_Type::SEL45
__IO uint16_t SEL45
Definition: MIMXRT1052.h:51223
USB_Type::HWDEVICE
__I uint32_t HWDEVICE
Definition: MIMXRT1052.h:45243
FLEXSPI_Type::STS0
__I uint32_t STS0
Definition: MIMXRT1052.h:21325
CCM_ANALOG_Type::PLL_ENET
__IO uint32_t PLL_ENET
Definition: MIMXRT1052.h:7247
USB_Type::BURSTSIZE
__IO uint32_t BURSTSIZE
Definition: MIMXRT1052.h:45277
PWM_Type::CAPTCOMPB
__IO uint16_t CAPTCOMPB
Definition: MIMXRT1052.h:36020
USB_Type::ENDPTFLUSH
__IO uint32_t ENDPTFLUSH
Definition: MIMXRT1052.h:45289
LCDIF_Type::RGB_ADJUST_TOG
__IO uint32_t RGB_ADJUST_TOG
Definition: MIMXRT1052.h:27400
XTALOSC24M_Type::OSC_CONFIG0
__IO uint32_t OSC_CONFIG0
Definition: MIMXRT1052.h:52387
SEMC_Type::STS11
uint32_t STS11
Definition: MIMXRT1052.h:39785
XBARA_Type::SEL43
__IO uint16_t SEL43
Definition: MIMXRT1052.h:51221
LCDIF_Type::VDCTRL4
__IO uint32_t VDCTRL4
Definition: MIMXRT1052.h:27389
CCM_ANALOG_Type::PLL_ENET_CLR
__IO uint32_t PLL_ENET_CLR
Definition: MIMXRT1052.h:7249
DMA_Type::DCHPRI11
__IO uint8_t DCHPRI11
Definition: MIMXRT1052.h:14390
USB_Type::HWHOST
__I uint32_t HWHOST
Definition: MIMXRT1052.h:45242
XBARA_Type::SEL24
__IO uint16_t SEL24
Definition: MIMXRT1052.h:51202
CCM_ANALOG_Type::PLL_USB1_TOG
__IO uint32_t PLL_USB1_TOG
Definition: MIMXRT1052.h:7216
TRNG_Type::INT_CTRL
__IO uint32_t INT_CTRL
Definition: MIMXRT1052.h:44011
USB_Type::ASYNCLISTADDR
__IO uint32_t ASYNCLISTADDR
Definition: MIMXRT1052.h:45273
OCOTP_Type::VERSION
__I uint32_t VERSION
Definition: MIMXRT1052.h:32204
CCM_ANALOG_Type::PLL_VIDEO_TOG
__IO uint32_t PLL_VIDEO_TOG
Definition: MIMXRT1052.h:7242
DCP_Type::CH3STAT_SET
__IO uint32_t CH3STAT_SET
Definition: MIMXRT1052.h:12439
TMR_Type::CMPLD2
__IO uint16_t CMPLD2
Definition: MIMXRT1052.h:43420
GPC_Type::ISR5
__I uint32_t ISR5
Definition: MIMXRT1052.h:22343
DCP_Type::STAT_TOG
__IO uint32_t STAT_TOG
Definition: MIMXRT1052.h:12369
OCOTP_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:32185
PXP_Type::AS_CLRKEYLOW
__IO uint32_t AS_CLRKEYLOW
Definition: MIMXRT1052.h:37884
OCOTP_Type::SW_STICKY
__IO uint32_t SW_STICKY
Definition: MIMXRT1052.h:32197
ENET_Type::FTRL
__IO uint32_t FTRL
Definition: MIMXRT1052.h:18549
ENET_Type::IEEE_T_MCOL
__I uint32_t IEEE_T_MCOL
Definition: MIMXRT1052.h:18574
OCOTP_Type::ANA2
__IO uint32_t ANA2
Definition: MIMXRT1052.h:32238
DCP_Type::PACKET2
__I uint32_t PACKET2
Definition: MIMXRT1052.h:12388
USB_Type::DCIVERSION
__I uint16_t DCIVERSION
Definition: MIMXRT1052.h:45259
DMA_Type::EEI
__IO uint32_t EEI
Definition: MIMXRT1052.h:14364
XBARA_Type::SEL58
__IO uint16_t SEL58
Definition: MIMXRT1052.h:51236
USBPHY_Type::TX_SET
__IO uint32_t TX_SET
Definition: MIMXRT1052.h:47135
USB_Type::HWGENERAL
__I uint32_t HWGENERAL
Definition: MIMXRT1052.h:45241
SPDIF_Type::SRU
__I uint32_t SRU
Definition: MIMXRT1052.h:42289
ENC_Type::POSD
__IO uint16_t POSD
Definition: MIMXRT1052.h:17950
FLEXSPI_Type::MCR2
__IO uint32_t MCR2
Definition: MIMXRT1052.h:21302
TRNG_Type::PKRCNT54
__I uint32_t PKRCNT54
Definition: MIMXRT1052.h:44004
USDHC_Type::MMC_BOOT
__IO uint32_t MMC_BOOT
Definition: MIMXRT1052.h:49090
XBARA_Type::SEL6
__IO uint16_t SEL6
Definition: MIMXRT1052.h:51184
PXP_Type::AS_PITCH
__IO uint32_t AS_PITCH
Definition: MIMXRT1052.h:37882
PMU_Type::MISC2_CLR
__IO uint32_t MISC2_CLR
Definition: MIMXRT1052.h:33494
TRNG_Type::SCR3C
__I uint32_t SCR3C
Definition: MIMXRT1052.h:43985
TRNG_Type::SCR6PL
__IO uint32_t SCR6PL
Definition: MIMXRT1052.h:43998
SPDIF_Type::STL
__O uint32_t STL
Definition: MIMXRT1052.h:42291
ENET_Type::GALR
__IO uint32_t GALR
Definition: MIMXRT1052.h:18533
ENET_Type::RMON_T_P64
__I uint32_t RMON_T_P64
Definition: MIMXRT1052.h:18563
CAN_Type::MCR
__IO uint32_t MCR
Definition: MIMXRT1052.h:4123
ENET_Type::ATINC
__IO uint32_t ATINC
Definition: MIMXRT1052.h:18614
USBPHY_Type::RX
__IO uint32_t RX
Definition: MIMXRT1052.h:47138
LPI2C_Type::STDR
__O uint32_t STDR
Definition: MIMXRT1052.h:29320
ENET_Type::RMON_R_UNDERSIZE
__I uint32_t RMON_R_UNDERSIZE
Definition: MIMXRT1052.h:18588
ROMC_Type::ROMPATCHCNTL
__IO uint32_t ROMPATCHCNTL
Definition: MIMXRT1052.h:39389
SPDIF_Type::SRL
__I uint32_t SRL
Definition: MIMXRT1052.h:42285
CMP_Type::CR0
__IO uint8_t CR0
Definition: MIMXRT1052.h:10268
TEMPMON_Type::TEMPSENSE2_CLR
__IO uint32_t TEMPSENSE2_CLR
Definition: MIMXRT1052.h:43117
FLEXIO_Type::TIMIEN
__IO uint32_t TIMIEN
Definition: MIMXRT1052.h:20522
IOMUXC_GPR_Type::GPR10
__IO uint32_t GPR10
Definition: MIMXRT1052.h:24411
SEMC_Type::IOCR
__IO uint32_t IOCR
Definition: MIMXRT1052.h:39740
IOMUXC_GPR_Type::GPR1
__IO uint32_t GPR1
Definition: MIMXRT1052.h:24402
DCP_Type::CTRL_SET
__IO uint32_t CTRL_SET
Definition: MIMXRT1052.h:12363
USB_ANALOG_Type::MISC_CLR
__IO uint32_t MISC_CLR
Definition: MIMXRT1052.h:48573
OCOTP_Type::SW_GP20
__IO uint32_t SW_GP20
Definition: MIMXRT1052.h:32272
ROMC_Type::ROMPATCHSR
__IO uint32_t ROMPATCHSR
Definition: MIMXRT1052.h:39394
SEMC_Type::STS13
uint32_t STS13
Definition: MIMXRT1052.h:39787
TRNG_Type::PKRCNTBA
__I uint32_t PKRCNTBA
Definition: MIMXRT1052.h:44007
LPUART_Type::BAUD
__IO uint32_t BAUD
Definition: MIMXRT1052.h:31152
USBPHY_Type::DEBUG1
__IO uint32_t DEBUG1
Definition: MIMXRT1052.h:47154
SEMC_Type::NANDCR2
__IO uint32_t NANDCR2
Definition: MIMXRT1052.h:39753
ADC_ETC_Type::TRIGn_CTRL
__IO uint32_t TRIGn_CTRL
Definition: MIMXRT1052.h:1689
USDHC_Type::CMD_RSP1
__I uint32_t CMD_RSP1
Definition: MIMXRT1052.h:49066
PWM_Type::CTRL
__IO uint16_t CTRL
Definition: MIMXRT1052.h:35995
PMU_Type::MISC0_TOG
__IO uint32_t MISC0_TOG
Definition: MIMXRT1052.h:33487
ENET_Type::RMON_R_PACKETS
__I uint32_t RMON_R_PACKETS
Definition: MIMXRT1052.h:18584
OCOTP_Type::SW_GP23
__IO uint32_t SW_GP23
Definition: MIMXRT1052.h:32278
ENET_Type::IEEE_T_LCOL
__I uint32_t IEEE_T_LCOL
Definition: MIMXRT1052.h:18576
TRNG_Type::SCR3L
__IO uint32_t SCR3L
Definition: MIMXRT1052.h:43986
CCM_Type::CS1CDR
__IO uint32_t CS1CDR
Definition: MIMXRT1052.h:5079
PXP_Type::PORTER_DUFF_CTRL
__IO uint32_t PORTER_DUFF_CTRL
Definition: MIMXRT1052.h:37898
DCP_Type::PACKET5
__I uint32_t PACKET5
Definition: MIMXRT1052.h:12394
CCM_ANALOG_Type::PLL_ENET_TOG
__IO uint32_t PLL_ENET_TOG
Definition: MIMXRT1052.h:7250
ENET_Type::RMON_R_P1024TO2047
__I uint32_t RMON_R_P1024TO2047
Definition: MIMXRT1052.h:18598
DMA_Type::DCHPRI22
__IO uint8_t DCHPRI22
Definition: MIMXRT1052.h:14403
ENET_Type::RMON_T_P512TO1023
__I uint32_t RMON_T_P512TO1023
Definition: MIMXRT1052.h:18567
PWM_Type::CAPTCTRLX
__IO uint16_t CAPTCTRLX
Definition: MIMXRT1052.h:36021
TRNG_Type::FRQMIN
__IO uint32_t FRQMIN
Definition: MIMXRT1052.h:43967
ENC_Type::CTRL2
__IO uint16_t CTRL2
Definition: MIMXRT1052.h:17962
ENET_Type::RMON_T_PACKETS
__I uint32_t RMON_T_PACKETS
Definition: MIMXRT1052.h:18554
LCDIF_Type::PIGEONCTRL0_SET
__IO uint32_t PIGEONCTRL0_SET
Definition: MIMXRT1052.h:27403
DMA_Type::DCHPRI31
__IO uint8_t DCHPRI31
Definition: MIMXRT1052.h:14410
I2S_Type::TCR4
__IO uint32_t TCR4
Definition: MIMXRT1052.h:23303
XBARA_Type::SEL11
__IO uint16_t SEL11
Definition: MIMXRT1052.h:51189
SPDIF_Type::SRCSH
__I uint32_t SRCSH
Definition: MIMXRT1052.h:42287
DCP_Type::STAT_SET
__IO uint32_t STAT_SET
Definition: MIMXRT1052.h:12367
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_POR_B
__IO uint32_t SW_PAD_CTL_PAD_POR_B
Definition: MIMXRT1052.h:26543
ENC_Type::LPOS
__IO uint16_t LPOS
Definition: MIMXRT1052.h:17955
DMA_Type::DCHPRI9
__IO uint8_t DCHPRI9
Definition: MIMXRT1052.h:14392
PWM_Type::CVAL0
__I uint16_t CVAL0
Definition: MIMXRT1052.h:36023
CCM_ANALOG_Type::PLL_SYS_SS
__IO uint32_t PLL_SYS_SS
Definition: MIMXRT1052.h:7225
DMA_Type::DCHPRI16
__IO uint8_t DCHPRI16
Definition: MIMXRT1052.h:14401
IOMUXC_GPR_Type::GPR23
__IO uint32_t GPR23
Definition: MIMXRT1052.h:24424
GPC_Type::CNTR
__IO uint32_t CNTR
Definition: MIMXRT1052.h:22337
USB_Type::GPTIMER0CTRL
__IO uint32_t GPTIMER0CTRL
Definition: MIMXRT1052.h:45248
CCM_ANALOG_Type::PFD_528
__IO uint32_t PFD_528
Definition: MIMXRT1052.h:7255
CCM_ANALOG_Type::PLL_SYS_CLR
__IO uint32_t PLL_SYS_CLR
Definition: MIMXRT1052.h:7223
TMR_Type::LOAD
__IO uint16_t LOAD
Definition: MIMXRT1052.h:43414
SEMC_Type::IPTXDAT
__IO uint32_t IPTXDAT
Definition: MIMXRT1052.h:39770
USB_ANALOG_Type::CHRG_DETECT_SET
__IO uint32_t CHRG_DETECT_SET
Definition: MIMXRT1052.h:48560
CSU_Type::HP0
__IO uint32_t HP0
Definition: MIMXRT1052.h:11323
PWM_Type::FRACVAL1
__IO uint16_t FRACVAL1
Definition: MIMXRT1052.h:35998
USB_Type::PERIODICLISTBASE
__IO uint32_t PERIODICLISTBASE
Definition: MIMXRT1052.h:45270
SNVS_Type::LPMKCR
__IO uint32_t LPMKCR
Definition: MIMXRT1052.h:41048
SPDIF_Type::STC
__IO uint32_t STC
Definition: MIMXRT1052.h:42298
DCP_Type::CH1OPTS_CLR
__IO uint32_t CH1OPTS_CLR
Definition: MIMXRT1052.h:12420
SEMC_Type::IPCR2
__IO uint32_t IPCR2
Definition: MIMXRT1052.h:39768
OCOTP_Type::MISC_CONF0
__IO uint32_t MISC_CONF0
Definition: MIMXRT1052.h:32280
PMU_Type::MISC2_SET
__IO uint32_t MISC2_SET
Definition: MIMXRT1052.h:33493
PWM_Type::FRACVAL2
__IO uint16_t FRACVAL2
Definition: MIMXRT1052.h:36000
PXP_Type::OUT_CTRL
__IO uint32_t OUT_CTRL
Definition: MIMXRT1052.h:37836
XBARA_Type::SEL22
__IO uint16_t SEL22
Definition: MIMXRT1052.h:51200
DMA_Type::DCHPRI3
__IO uint8_t DCHPRI3
Definition: MIMXRT1052.h:14382
USBNC_Type::USB_OTGn_PHY_CTRL_0
__IO uint32_t USB_OTGn_PHY_CTRL_0
Definition: MIMXRT1052.h:46984
AIPSTZ_Type::OPACR3
__IO uint32_t OPACR3
Definition: MIMXRT1052.h:2806
TEMPMON_Type::TEMPSENSE2_SET
__IO uint32_t TEMPSENSE2_SET
Definition: MIMXRT1052.h:43116
WDOG_Type::WSR
__IO uint16_t WSR
Definition: MIMXRT1052.h:50964
CAN_Type::RXFGMASK
__IO uint32_t RXFGMASK
Definition: MIMXRT1052.h:4140
CCM_Type::CGPR
__IO uint32_t CGPR
Definition: MIMXRT1052.h:5092
USDHC_Type::ADMA_SYS_ADDR
__IO uint32_t ADMA_SYS_ADDR
Definition: MIMXRT1052.h:49083
ENET_Type::RMON_R_P256TO511
__I uint32_t RMON_R_P256TO511
Definition: MIMXRT1052.h:18596
LCDIF_Type::CTRL1_CLR
__IO uint32_t CTRL1_CLR
Definition: MIMXRT1052.h:27367
LCDIF_Type::TRANSFER_COUNT
__IO uint32_t TRANSFER_COUNT
Definition: MIMXRT1052.h:27373
ENC_Type::LINIT
__IO uint16_t LINIT
Definition: MIMXRT1052.h:17959
USB_Type::USBMODE
__IO uint32_t USBMODE
Definition: MIMXRT1052.h:45286
CCM_ANALOG_Type::PFD_528_TOG
__IO uint32_t PFD_528_TOG
Definition: MIMXRT1052.h:7258
DMA_Type::DCHPRI4
__IO uint8_t DCHPRI4
Definition: MIMXRT1052.h:14389
LPSPI_Type::TCR
__IO uint32_t TCR
Definition: MIMXRT1052.h:30475
LPI2C_Type::SCR
__IO uint32_t SCR
Definition: MIMXRT1052.h:29307
ADC_ETC_Type::TRIGn_RESULT_1_0
__I uint32_t TRIGn_RESULT_1_0
Definition: MIMXRT1052.h:1695
CCM_ANALOG_Type::MISC2
__IO uint32_t MISC2
Definition: MIMXRT1052.h:7268
DMA_Type::DADDR
__IO uint32_t DADDR
Definition: MIMXRT1052.h:14425
DCP_Type::PACKET3
__I uint32_t PACKET3
Definition: MIMXRT1052.h:12390
DCP_Type::CH2OPTS_CLR
__IO uint32_t CH2OPTS_CLR
Definition: MIMXRT1052.h:12432
XTALOSC24M_Type::OSC_CONFIG1_CLR
__IO uint32_t OSC_CONFIG1_CLR
Definition: MIMXRT1052.h:52393
PIT_Type::LTMR64H
__I uint32_t LTMR64H
Definition: MIMXRT1052.h:33301
SEMC_Type::BMCR0
__IO uint32_t BMCR0
Definition: MIMXRT1052.h:39741
LCDIF_Type::PIGEONCTRL0_TOG
__IO uint32_t PIGEONCTRL0_TOG
Definition: MIMXRT1052.h:27405
PXP_Type::OUT_PITCH
__IO uint32_t OUT_PITCH
Definition: MIMXRT1052.h:37844
ENC_Type::LCOMP
__IO uint16_t LCOMP
Definition: MIMXRT1052.h:17966
CSI_Type::RFIFO
__I uint32_t RFIFO
Definition: MIMXRT1052.h:10543
FLEXIO_Type::SHIFTEIEN
__IO uint32_t SHIFTEIEN
Definition: MIMXRT1052.h:20521
ENET_Type::RMON_T_OCTETS
__I uint32_t RMON_T_OCTETS
Definition: MIMXRT1052.h:18570
DCP_Type::CH1OPTS_TOG
__IO uint32_t CH1OPTS_TOG
Definition: MIMXRT1052.h:12421
PMU_Type::REG_1P1_CLR
__IO uint32_t REG_1P1_CLR
Definition: MIMXRT1052.h:33470
CSI_Type::STATFIFO
__I uint32_t STATFIFO
Definition: MIMXRT1052.h:10542
CCM_Type::CCGR4
__IO uint32_t CCGR4
Definition: MIMXRT1052.h:5097
CAN_Type::CS
__IO uint32_t CS
Definition: MIMXRT1052.h:4147
PWM_Type::FRCTRL
__IO uint16_t FRCTRL
Definition: MIMXRT1052.h:36008
DCP_Type::CH0OPTS_SET
__IO uint32_t CH0OPTS_SET
Definition: MIMXRT1052.h:12407
USDHC_Type::INT_STATUS_EN
__IO uint32_t INT_STATUS_EN
Definition: MIMXRT1052.h:49074
XBARA_Type::SEL14
__IO uint16_t SEL14
Definition: MIMXRT1052.h:51192
CCM_Type::CLPCR
__IO uint32_t CLPCR
Definition: MIMXRT1052.h:5088
PWM_Type::CAPTCTRLA
__IO uint16_t CAPTCTRLA
Definition: MIMXRT1052.h:36017
USDHC_Type::PROT_CTRL
__IO uint32_t PROT_CTRL
Definition: MIMXRT1052.h:49071
LPUART_Type::STAT
__IO uint32_t STAT
Definition: MIMXRT1052.h:31153
SNVS_Type::LPSECR
__IO uint32_t LPSECR
Definition: MIMXRT1052.h:41051
USBPHY_Type::DEBUG0_STATUS
__I uint32_t DEBUG0_STATUS
Definition: MIMXRT1052.h:47152
USB_ANALOG_Type::MISC_SET
__IO uint32_t MISC_SET
Definition: MIMXRT1052.h:48572
XBARA_Type::SEL51
__IO uint16_t SEL51
Definition: MIMXRT1052.h:51229
PMU_Type::REG_3P0_SET
__IO uint32_t REG_3P0_SET
Definition: MIMXRT1052.h:33473
DCP_Type::CH3CMDPTR
__IO uint32_t CH3CMDPTR
Definition: MIMXRT1052.h:12434
XBARA_Type::SEL23
__IO uint16_t SEL23
Definition: MIMXRT1052.h:51201
TMR_Type::CAPT
__IO uint16_t CAPT
Definition: MIMXRT1052.h:43413
IOMUXC_GPR_Type::GPR25
__IO uint32_t GPR25
Definition: MIMXRT1052.h:24426
DCP_Type::CH3STAT
__IO uint32_t CH3STAT
Definition: MIMXRT1052.h:12438
SEMC_Type::STS2
__I uint32_t STS2
Definition: MIMXRT1052.h:39776
GPIO_Type::DR_TOGGLE
__O uint32_t DR_TOGGLE
Definition: MIMXRT1052.h:22490
LPI2C_Type::MDMR
__IO uint32_t MDMR
Definition: MIMXRT1052.h:29295
DMA_Type::BITER_ELINKNO
__IO uint16_t BITER_ELINKNO
Definition: MIMXRT1052.h:14434
IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_TEST_MODE
__IO uint32_t SW_PAD_CTL_PAD_TEST_MODE
Definition: MIMXRT1052.h:26542
BEE_Type::CTR_NONCE0_W2
__O uint32_t CTR_NONCE0_W2
Definition: MIMXRT1052.h:3786
USB_ANALOG_Type::VBUS_DETECT_TOG
__IO uint32_t VBUS_DETECT_TOG
Definition: MIMXRT1052.h:48558
CCM_Type::CCGR0
__IO uint32_t CCGR0
Definition: MIMXRT1052.h:5093
FLEXRAM_Type::INT_STAT_EN
__IO uint32_t INT_STAT_EN
Definition: MIMXRT1052.h:21143
LCDIF_Type::VDCTRL0_TOG
__IO uint32_t VDCTRL0_TOG
Definition: MIMXRT1052.h:27382
CCM_Type::CCGR1
__IO uint32_t CCGR1
Definition: MIMXRT1052.h:5094
ENET_Type::IEEE_T_SQE
__I uint32_t IEEE_T_SQE
Definition: MIMXRT1052.h:18580
CM7_MCM_Type::ISCR
__IO uint32_t ISCR
Definition: MIMXRT1052.h:10100
IOMUXC_SNVS_GPR_Type::GPR0
uint32_t GPR0
Definition: MIMXRT1052.h:27101
DCP_Type::CHANNELCTRL
__IO uint32_t CHANNELCTRL
Definition: MIMXRT1052.h:12370
LPI2C_Type::MCFGR2
__IO uint32_t MCFGR2
Definition: MIMXRT1052.h:29292
CCM_Type::CSCMR2
__IO uint32_t CSCMR2
Definition: MIMXRT1052.h:5077
USB_Type::ENDPTCTRL0
__IO uint32_t ENDPTCTRL0
Definition: MIMXRT1052.h:45292
FLEXSPI_Type::STS1
__I uint32_t STS1
Definition: MIMXRT1052.h:21326
ROMC_Type::ROMPATCHENL
__IO uint32_t ROMPATCHENL
Definition: MIMXRT1052.h:39391
LPI2C_Type::MFCR
__IO uint32_t MFCR
Definition: MIMXRT1052.h:29301
ENET_Type::TIPG
__IO uint32_t TIPG
Definition: MIMXRT1052.h:18548
SEMC_Type::NORCR1
__IO uint32_t NORCR1
Definition: MIMXRT1052.h:39756
XBARB_Type::SEL0
__IO uint16_t SEL0
Definition: MIMXRT1052.h:52225
DCP_Type::STAT
__IO uint32_t STAT
Definition: MIMXRT1052.h:12366
DCP_Type::STAT_CLR
__IO uint32_t STAT_CLR
Definition: MIMXRT1052.h:12368
CSI_Type::CR18
__IO uint32_t CR18
Definition: MIMXRT1052.h:10554
FLEXSPI_Type::MCR0
__IO uint32_t MCR0
Definition: MIMXRT1052.h:21300
OCOTP_Type::TIMING
__IO uint32_t TIMING
Definition: MIMXRT1052.h:32189
ADC_ETC_Type::TRIGn_COUNTER
__IO uint32_t TRIGn_COUNTER
Definition: MIMXRT1052.h:1690
BEE_Type::REGION1_BOT
__IO uint32_t REGION1_BOT
Definition: MIMXRT1052.h:3793
PIT_Type::TFLG
__IO uint32_t TFLG
Definition: MIMXRT1052.h:33308
USBPHY_Type::RX_CLR
__IO uint32_t RX_CLR
Definition: MIMXRT1052.h:47140
FLEXIO_Type::CTRL
__IO uint32_t CTRL
Definition: MIMXRT1052.h:20514
DMA_Type::DCHPRI29
__IO uint8_t DCHPRI29
Definition: MIMXRT1052.h:14412
PWM_Type::CAPTCOMPA
__IO uint16_t CAPTCOMPA
Definition: MIMXRT1052.h:36018
LPUART_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1052.h:31148
ENC_Type::UPOSH
__I uint16_t UPOSH
Definition: MIMXRT1052.h:17956
IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_WAKEUP
__IO uint32_t SW_MUX_CTL_PAD_WAKEUP
Definition: MIMXRT1052.h:26539
I2S_Type::VERID
__I uint32_t VERID
Definition: MIMXRT1052.h:23297
OCOTP_Type::SCS_TOG
__IO uint32_t SCS_TOG
Definition: MIMXRT1052.h:32202
PXP_Type::STAT_CLR
__IO uint32_t STAT_CLR
Definition: MIMXRT1052.h:37834
XBARA_Type::SEL47
__IO uint16_t SEL47
Definition: MIMXRT1052.h:51225
XBARA_Type::SEL27
__IO uint16_t SEL27
Definition: MIMXRT1052.h:51205
SNVS_Type::HPHACR
__I uint32_t HPHACR
Definition: MIMXRT1052.h:41041
PIT_Type::CVAL
__I uint32_t CVAL
Definition: MIMXRT1052.h:33306
OCOTP_Type::CFG2
__IO uint32_t CFG2
Definition: MIMXRT1052.h:32214
USB_ANALOG_Type::DIGPROG
__I uint32_t DIGPROG
Definition: MIMXRT1052.h:48576
XBARA_Type::SEL39
__IO uint16_t SEL39
Definition: MIMXRT1052.h:51217
FLEXSPI_Type::IPCMD
__IO uint32_t IPCMD
Definition: MIMXRT1052.h:21319
ADC_Type::CFG
__IO uint32_t CFG
Definition: MIMXRT1052.h:1302
CAN_Type::TIMER
__IO uint32_t TIMER
Definition: MIMXRT1052.h:4125
CCM_ANALOG_Type::PFD_480
__IO uint32_t PFD_480
Definition: MIMXRT1052.h:7251
ENC_Type::UCOMP
__IO uint16_t UCOMP
Definition: MIMXRT1052.h:17965
CAN_Type::GFWR
__IO uint32_t GFWR
Definition: MIMXRT1052.h:4155
PWM_Type::INTEN
__IO uint16_t INTEN
Definition: MIMXRT1052.h:36011
DMA_Type::INT
__IO uint32_t INT
Definition: MIMXRT1052.h:14374
USBPHY_Type::STATUS
__IO uint32_t STATUS
Definition: MIMXRT1052.h:47146
LCDIF_Type::CTRL2
__IO uint32_t CTRL2
Definition: MIMXRT1052.h:27369
CSI_Type::SR
__IO uint32_t SR
Definition: MIMXRT1052.h:10545
LPI2C_Type::MSR
__IO uint32_t MSR
Definition: MIMXRT1052.h:29287
DMA_Type::ERR
__IO uint32_t ERR
Definition: MIMXRT1052.h:14376
_iomuxc_sw_mux_ctl_pad
_iomuxc_sw_mux_ctl_pad
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
Definition: MIMXRT1052.h:304
CAN_Type::IMASK2
__IO uint32_t IMASK2
Definition: MIMXRT1052.h:4132
CCM_ANALOG_Type::MISC1_CLR
__IO uint32_t MISC1_CLR
Definition: MIMXRT1052.h:7266
SEMC_Type::STS7
uint32_t STS7
Definition: MIMXRT1052.h:39781
CCM_ANALOG_Type::PFD_528_SET
__IO uint32_t PFD_528_SET
Definition: MIMXRT1052.h:7256
ADC_ETC_Type::TRIGn_CHAIN_5_4
__IO uint32_t TRIGn_CHAIN_5_4
Definition: MIMXRT1052.h:1693
SEMC_Type::STS9
uint32_t STS9
Definition: MIMXRT1052.h:39783
LCDIF_Type::VDCTRL1
__IO uint32_t VDCTRL1
Definition: MIMXRT1052.h:27383
AIPSTZ_Type::MPR
__IO uint32_t MPR
Definition: MIMXRT1052.h:2801
FLEXSPI_Type::LUTCR
__IO uint32_t LUTCR
Definition: MIMXRT1052.h:21307
XTALOSC24M_Type::LOWPWR_CTRL_CLR
__IO uint32_t LOWPWR_CTRL_CLR
Definition: MIMXRT1052.h:52384
DCP_Type::CH3OPTS_TOG
__IO uint32_t CH3OPTS_TOG
Definition: MIMXRT1052.h:12445
PWM_Type::MASK
__IO uint16_t MASK
Definition: MIMXRT1052.h:36038
TMR_Type::DMA
__IO uint16_t DMA
Definition: MIMXRT1052.h:43423
SRC_Type::SBMR1
__I uint32_t SBMR1
Definition: MIMXRT1052.h:42850
XBARA_Type::SEL55
__IO uint16_t SEL55
Definition: MIMXRT1052.h:51233
TMR_Type::CNTR
__IO uint16_t CNTR
Definition: MIMXRT1052.h:43416
CCM_ANALOG_Type::PLL_USB1
__IO uint32_t PLL_USB1
Definition: MIMXRT1052.h:7213
I2S_Type::RCR5
__IO uint32_t RCR5
Definition: MIMXRT1052.h:23316
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05
Definition: MIMXRT1052.h:527
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14
Definition: MIMXRT1052.h:504
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01
Definition: MIMXRT1052.h:491
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
Definition: MIMXRT1052.h:452
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13
Definition: MIMXRT1052.h:461
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03
Definition: MIMXRT1052.h:557
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06
Definition: MIMXRT1052.h:496
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14
Definition: MIMXRT1052.h:552
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10
Definition: MIMXRT1052.h:532
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03
Definition: MIMXRT1052.h:451
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01
Definition: MIMXRT1052.h:555
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09
Definition: MIMXRT1052.h:569
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06
Definition: MIMXRT1052.h:544
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15
Definition: MIMXRT1052.h:463
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15
Definition: MIMXRT1052.h:553
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34
Definition: MIMXRT1052.h:482
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11
Definition: MIMXRT1052.h:549
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15
Definition: MIMXRT1052.h:505
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02
Definition: MIMXRT1052.h:540
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06
Definition: MIMXRT1052.h:566
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11
Definition: MIMXRT1052.h:459
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02
Definition: MIMXRT1052.h:556
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10
Definition: MIMXRT1052.h:500
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
Definition: MIMXRT1052.h:455
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30
Definition: MIMXRT1052.h:478
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01
Definition: MIMXRT1052.h:539
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
Definition: MIMXRT1052.h:520
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21
Definition: MIMXRT1052.h:469
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
Definition: MIMXRT1052.h:508
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04
Definition: MIMXRT1052.h:494
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04
Definition: MIMXRT1052.h:510
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10
Definition: MIMXRT1052.h:458
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08
Definition: MIMXRT1052.h:498
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18
Definition: MIMXRT1052.h:466
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04
Definition: MIMXRT1052.h:542
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
Definition: MIMXRT1052.h:521
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12
Definition: MIMXRT1052.h:550
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03
Definition: MIMXRT1052.h:525
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16
Definition: MIMXRT1052.h:464
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
Definition: MIMXRT1052.h:513
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07
Definition: MIMXRT1052.h:529
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09
Definition: MIMXRT1052.h:457
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07
Definition: MIMXRT1052.h:497
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35
Definition: MIMXRT1052.h:483
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
Definition: MIMXRT1052.h:559
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
Definition: MIMXRT1052.h:517
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23
Definition: MIMXRT1052.h:471
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04
Definition: MIMXRT1052.h:564
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03
Definition: MIMXRT1052.h:541
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
Definition: MIMXRT1052.h:492
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07
Definition: MIMXRT1052.h:545
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15
Definition: MIMXRT1052.h:537
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38
Definition: MIMXRT1052.h:486
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26
Definition: MIMXRT1052.h:474
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00
Definition: MIMXRT1052.h:490
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08
Definition: MIMXRT1052.h:546
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22
Definition: MIMXRT1052.h:470
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00
Definition: MIMXRT1052.h:522
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00
Definition: MIMXRT1052.h:560
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11
Definition: MIMXRT1052.h:533
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05
Definition: MIMXRT1052.h:565
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05
Definition: MIMXRT1052.h:495
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
Definition: MIMXRT1052.h:454
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33
Definition: MIMXRT1052.h:481
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08
Definition: MIMXRT1052.h:530
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39
Definition: MIMXRT1052.h:487
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00
Definition: MIMXRT1052.h:538
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13
Definition: MIMXRT1052.h:519
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28
Definition: MIMXRT1052.h:476
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14
Definition: MIMXRT1052.h:462
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
Definition: MIMXRT1052.h:558
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
Definition: MIMXRT1052.h:514
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10
Definition: MIMXRT1052.h:570
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
Definition: MIMXRT1052.h:484
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
Definition: MIMXRT1052.h:509
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41
Definition: MIMXRT1052.h:489
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
Definition: MIMXRT1052.h:485
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11
Definition: MIMXRT1052.h:571
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01
Definition: MIMXRT1052.h:523
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25
Definition: MIMXRT1052.h:473
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09
Definition: MIMXRT1052.h:547
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09
Definition: MIMXRT1052.h:531
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27
Definition: MIMXRT1052.h:475
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01
Definition: MIMXRT1052.h:561
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
Definition: MIMXRT1052.h:507
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
Definition: MIMXRT1052.h:512
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02
Definition: MIMXRT1052.h:450
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29
Definition: MIMXRT1052.h:477
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
Definition: MIMXRT1052.h:456
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
Definition: MIMXRT1052.h:503
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08
Definition: MIMXRT1052.h:568
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02
Definition: MIMXRT1052.h:562
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05
Definition: MIMXRT1052.h:511
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06
Definition: MIMXRT1052.h:528
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05
Definition: MIMXRT1052.h:543
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02
Definition: MIMXRT1052.h:524
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
Definition: MIMXRT1052.h:516
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10
Definition: MIMXRT1052.h:548
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13
Definition: MIMXRT1052.h:551
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01
Definition: MIMXRT1052.h:449
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00
Definition: MIMXRT1052.h:448
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12
Definition: MIMXRT1052.h:460
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13
Definition: MIMXRT1052.h:535
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14
Definition: MIMXRT1052.h:536
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
Definition: MIMXRT1052.h:534
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
Definition: MIMXRT1052.h:453
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19
Definition: MIMXRT1052.h:467
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
Definition: MIMXRT1052.h:480
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
Definition: MIMXRT1052.h:506
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17
Definition: MIMXRT1052.h:465
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07
Definition: MIMXRT1052.h:567
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20
Definition: MIMXRT1052.h:468
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12
Definition: MIMXRT1052.h:518
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
Definition: MIMXRT1052.h:502
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
Definition: MIMXRT1052.h:493
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
Definition: MIMXRT1052.h:515
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11
Definition: MIMXRT1052.h:501
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03
Definition: MIMXRT1052.h:563
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04
Definition: MIMXRT1052.h:526
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
Definition: MIMXRT1052.h:479
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40
Definition: MIMXRT1052.h:488
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
Definition: MIMXRT1052.h:554
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09
Definition: MIMXRT1052.h:499
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
@ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
Definition: MIMXRT1052.h:472
kIOMUXC_XBAR_INOUT24_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT24_SELECT_INPUT
Definition: MIMXRT1052.h:730
kIOMUXC_NMI_SELECT_INPUT
@ kIOMUXC_NMI_SELECT_INPUT
Definition: MIMXRT1052.h:676
kIOMUXC_USDHC2_DATA6_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA6_SELECT_INPUT
Definition: MIMXRT1052.h:714
kIOMUXC_LPSPI1_SDI_SELECT_INPUT
@ kIOMUXC_LPSPI1_SDI_SELECT_INPUT
Definition: MIMXRT1052.h:647
kIOMUXC_XBAR_INOUT07_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT07_SELECT_INPUT
Definition: MIMXRT1052.h:722
kIOMUXC_XBAR_INOUT18_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT18_SELECT_INPUT
Definition: MIMXRT1052.h:726
kIOMUXC_ENET_TXCLK_SELECT_INPUT
@ kIOMUXC_ENET_TXCLK_SELECT_INPUT
Definition: MIMXRT1052.h:604
kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT
Definition: MIMXRT1052.h:679
kIOMUXC_XBAR_INOUT06_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT06_SELECT_INPUT
Definition: MIMXRT1052.h:721
kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT
Definition: MIMXRT1052.h:615
kIOMUXC_XBAR_INOUT23_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT23_SELECT_INPUT
Definition: MIMXRT1052.h:729
kIOMUXC_XBAR_INOUT17_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT17_SELECT_INPUT
Definition: MIMXRT1052.h:725
kIOMUXC_ENET_RXERR_SELECT_INPUT
@ kIOMUXC_ENET_RXERR_SELECT_INPUT
Definition: MIMXRT1052.h:602
kIOMUXC_LPI2C4_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C4_SCL_SELECT_INPUT
Definition: MIMXRT1052.h:643
kIOMUXC_USDHC1_WP_SELECT_INPUT
@ kIOMUXC_USDHC1_WP_SELECT_INPUT
Definition: MIMXRT1052.h:704
kIOMUXC_LPUART8_RX_SELECT_INPUT
@ kIOMUXC_LPUART8_RX_SELECT_INPUT
Definition: MIMXRT1052.h:674
kIOMUXC_CSI_PIXCLK_SELECT_INPUT
@ kIOMUXC_CSI_PIXCLK_SELECT_INPUT
Definition: MIMXRT1052.h:595
kIOMUXC_SAI1_MCLK2_SELECT_INPUT
@ kIOMUXC_SAI1_MCLK2_SELECT_INPUT
Definition: MIMXRT1052.h:685
kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT
Definition: MIMXRT1052.h:617
kIOMUXC_USB_OTG1_OC_SELECT_INPUT
@ kIOMUXC_USB_OTG1_OC_SELECT_INPUT
Definition: MIMXRT1052.h:702
kIOMUXC_FLEXSPI_A_SCK_SELECT_INPUT
@ kIOMUXC_FLEXSPI_A_SCK_SELECT_INPUT
Definition: MIMXRT1052.h:636
kIOMUXC_XBAR_INOUT19_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT19_SELECT_INPUT
Definition: MIMXRT1052.h:735
kIOMUXC_CSI_DATA09_SELECT_INPUT
@ kIOMUXC_CSI_DATA09_SELECT_INPUT
Definition: MIMXRT1052.h:593
kIOMUXC_LPI2C2_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C2_SDA_SELECT_INPUT
Definition: MIMXRT1052.h:640
kIOMUXC_LPUART4_RX_SELECT_INPUT
@ kIOMUXC_LPUART4_RX_SELECT_INPUT
Definition: MIMXRT1052.h:666
kIOMUXC_ENET0_TIMER_SELECT_INPUT
@ kIOMUXC_ENET0_TIMER_SELECT_INPUT
Definition: MIMXRT1052.h:603
kIOMUXC_LPSPI2_SDO_SELECT_INPUT
@ kIOMUXC_LPSPI2_SDO_SELECT_INPUT
Definition: MIMXRT1052.h:652
kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT
@ kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT
Definition: MIMXRT1052.h:630
kIOMUXC_FLEXCAN2_RX_SELECT_INPUT
@ kIOMUXC_FLEXCAN2_RX_SELECT_INPUT
Definition: MIMXRT1052.h:606
kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT
Definition: MIMXRT1052.h:610
kIOMUXC_USDHC2_DATA0_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA0_SELECT_INPUT
Definition: MIMXRT1052.h:708
kIOMUXC_XBAR_INOUT02_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT02_SELECT_INPUT
Definition: MIMXRT1052.h:717
kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT
@ kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT
Definition: MIMXRT1052.h:597
kIOMUXC_LPUART3_CTS_B_SELECT_INPUT
@ kIOMUXC_LPUART3_CTS_B_SELECT_INPUT
Definition: MIMXRT1052.h:663
kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT
Definition: MIMXRT1052.h:686
kIOMUXC_USDHC2_CMD_SELECT_INPUT
@ kIOMUXC_USDHC2_CMD_SELECT_INPUT
Definition: MIMXRT1052.h:707
kIOMUXC_XBAR_INOUT05_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT05_SELECT_INPUT
Definition: MIMXRT1052.h:720
kIOMUXC_CSI_DATA08_SELECT_INPUT
@ kIOMUXC_CSI_DATA08_SELECT_INPUT
Definition: MIMXRT1052.h:592
kIOMUXC_LPUART8_TX_SELECT_INPUT
@ kIOMUXC_LPUART8_TX_SELECT_INPUT
Definition: MIMXRT1052.h:675
kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT
Definition: MIMXRT1052.h:613
kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT
@ kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT
Definition: MIMXRT1052.h:628
kIOMUXC_SAI2_MCLK2_SELECT_INPUT
@ kIOMUXC_SAI2_MCLK2_SELECT_INPUT
Definition: MIMXRT1052.h:694
kIOMUXC_LPSPI2_SDI_SELECT_INPUT
@ kIOMUXC_LPSPI2_SDI_SELECT_INPUT
Definition: MIMXRT1052.h:651
kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT
Definition: MIMXRT1052.h:698
kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT
Definition: MIMXRT1052.h:612
kIOMUXC_LPUART6_RX_SELECT_INPUT
@ kIOMUXC_LPUART6_RX_SELECT_INPUT
Definition: MIMXRT1052.h:670
kIOMUXC_ENET1_RXDATA_SELECT_INPUT
@ kIOMUXC_ENET1_RXDATA_SELECT_INPUT
Definition: MIMXRT1052.h:600
kIOMUXC_XBAR_INOUT08_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT08_SELECT_INPUT
Definition: MIMXRT1052.h:723
kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT
Definition: MIMXRT1052.h:608
kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT
Definition: MIMXRT1052.h:607
kIOMUXC_USDHC2_WP_SELECT_INPUT
@ kIOMUXC_USDHC2_WP_SELECT_INPUT
Definition: MIMXRT1052.h:716
kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT
@ kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT
Definition: MIMXRT1052.h:696
kIOMUXC_LPSPI4_SDO_SELECT_INPUT
@ kIOMUXC_LPSPI4_SDO_SELECT_INPUT
Definition: MIMXRT1052.h:660
kIOMUXC_XBAR_INOUT04_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT04_SELECT_INPUT
Definition: MIMXRT1052.h:719
kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT
Definition: MIMXRT1052.h:697
kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT
@ kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT
Definition: MIMXRT1052.h:681
kIOMUXC_FLEXCAN1_RX_SELECT_INPUT
@ kIOMUXC_FLEXCAN1_RX_SELECT_INPUT
Definition: MIMXRT1052.h:605
kIOMUXC_CSI_HSYNC_SELECT_INPUT
@ kIOMUXC_CSI_HSYNC_SELECT_INPUT
Definition: MIMXRT1052.h:594
kIOMUXC_LPSPI3_PCS0_SELECT_INPUT
@ kIOMUXC_LPSPI3_PCS0_SELECT_INPUT
Definition: MIMXRT1052.h:653
kIOMUXC_LPSPI2_SCK_SELECT_INPUT
@ kIOMUXC_LPSPI2_SCK_SELECT_INPUT
Definition: MIMXRT1052.h:650
kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT
Definition: MIMXRT1052.h:618
kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT
Definition: MIMXRT1052.h:678
kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT
Definition: MIMXRT1052.h:621
kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT
Definition: MIMXRT1052.h:620
kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT
Definition: MIMXRT1052.h:693
kIOMUXC_FLEXSPI_A_DQS_SELECT_INPUT
@ kIOMUXC_FLEXSPI_A_DQS_SELECT_INPUT
Definition: MIMXRT1052.h:627
kIOMUXC_FLEXSPI_B_DATA1_SELECT_INPUT
@ kIOMUXC_FLEXSPI_B_DATA1_SELECT_INPUT
Definition: MIMXRT1052.h:633
kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT
Definition: MIMXRT1052.h:611
kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT
@ kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT
Definition: MIMXRT1052.h:584
kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT
Definition: MIMXRT1052.h:622
kIOMUXC_USDHC2_DATA1_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA1_SELECT_INPUT
Definition: MIMXRT1052.h:709
kIOMUXC_XBAR_INOUT22_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT22_SELECT_INPUT
Definition: MIMXRT1052.h:728
kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT
Definition: MIMXRT1052.h:614
kIOMUXC_LPI2C3_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C3_SDA_SELECT_INPUT
Definition: MIMXRT1052.h:642
kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT
Definition: MIMXRT1052.h:695
kIOMUXC_LPSPI3_SDI_SELECT_INPUT
@ kIOMUXC_LPSPI3_SDI_SELECT_INPUT
Definition: MIMXRT1052.h:655
kIOMUXC_XBAR_INOUT25_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT25_SELECT_INPUT
Definition: MIMXRT1052.h:734
kIOMUXC_LPUART7_RX_SELECT_INPUT
@ kIOMUXC_LPUART7_RX_SELECT_INPUT
Definition: MIMXRT1052.h:672
kIOMUXC_CCM_PMIC_READY_SELECT_INPUT
@ kIOMUXC_CCM_PMIC_READY_SELECT_INPUT
Definition: MIMXRT1052.h:585
kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT
@ kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT
Definition: MIMXRT1052.h:609
kIOMUXC_CSI_DATA02_SELECT_INPUT
@ kIOMUXC_CSI_DATA02_SELECT_INPUT
Definition: MIMXRT1052.h:586
kIOMUXC_XBAR_INOUT15_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT15_SELECT_INPUT
Definition: MIMXRT1052.h:732
kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT
Definition: MIMXRT1052.h:688
kIOMUXC_LPSPI4_SCK_SELECT_INPUT
@ kIOMUXC_LPSPI4_SCK_SELECT_INPUT
Definition: MIMXRT1052.h:658
kIOMUXC_USDHC2_DATA5_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA5_SELECT_INPUT
Definition: MIMXRT1052.h:713
kIOMUXC_XBAR_INOUT20_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT20_SELECT_INPUT
Definition: MIMXRT1052.h:727
kIOMUXC_USDHC2_DATA4_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA4_SELECT_INPUT
Definition: MIMXRT1052.h:712
kIOMUXC_LPSPI1_SDO_SELECT_INPUT
@ kIOMUXC_LPSPI1_SDO_SELECT_INPUT
Definition: MIMXRT1052.h:648
kIOMUXC_CSI_DATA04_SELECT_INPUT
@ kIOMUXC_CSI_DATA04_SELECT_INPUT
Definition: MIMXRT1052.h:588
kIOMUXC_FLEXSPI_B_DATA2_SELECT_INPUT
@ kIOMUXC_FLEXSPI_B_DATA2_SELECT_INPUT
Definition: MIMXRT1052.h:634
kIOMUXC_FLEXSPI_B_DATA0_SELECT_INPUT
@ kIOMUXC_FLEXSPI_B_DATA0_SELECT_INPUT
Definition: MIMXRT1052.h:632
kIOMUXC_USDHC2_CLK_SELECT_INPUT
@ kIOMUXC_USDHC2_CLK_SELECT_INPUT
Definition: MIMXRT1052.h:705
kIOMUXC_LPSPI1_PCS0_SELECT_INPUT
@ kIOMUXC_LPSPI1_PCS0_SELECT_INPUT
Definition: MIMXRT1052.h:645
kIOMUXC_FLEXSPI_B_DATA3_SELECT_INPUT
@ kIOMUXC_FLEXSPI_B_DATA3_SELECT_INPUT
Definition: MIMXRT1052.h:635
kIOMUXC_XBAR_INOUT21_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT21_SELECT_INPUT
Definition: MIMXRT1052.h:736
kIOMUXC_LPUART6_TX_SELECT_INPUT
@ kIOMUXC_LPUART6_TX_SELECT_INPUT
Definition: MIMXRT1052.h:671
kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT
@ kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT
Definition: MIMXRT1052.h:629
kIOMUXC_LPI2C1_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C1_SDA_SELECT_INPUT
Definition: MIMXRT1052.h:638
kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT
Definition: MIMXRT1052.h:687
kIOMUXC_CSI_DATA03_SELECT_INPUT
@ kIOMUXC_CSI_DATA03_SELECT_INPUT
Definition: MIMXRT1052.h:587
kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT
@ kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT
Definition: MIMXRT1052.h:623
kIOMUXC_USDHC2_CD_B_SELECT_INPUT
@ kIOMUXC_USDHC2_CD_B_SELECT_INPUT
Definition: MIMXRT1052.h:706
kIOMUXC_XBAR_INOUT09_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT09_SELECT_INPUT
Definition: MIMXRT1052.h:724
kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT
Definition: MIMXRT1052.h:691
kIOMUXC_LPSPI1_SCK_SELECT_INPUT
@ kIOMUXC_LPSPI1_SCK_SELECT_INPUT
Definition: MIMXRT1052.h:646
kIOMUXC_USDHC2_DATA3_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA3_SELECT_INPUT
Definition: MIMXRT1052.h:711
kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT
Definition: MIMXRT1052.h:689
kIOMUXC_USDHC2_DATA2_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA2_SELECT_INPUT
Definition: MIMXRT1052.h:710
kIOMUXC_LPI2C2_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C2_SCL_SELECT_INPUT
Definition: MIMXRT1052.h:639
kIOMUXC_LPSPI4_PCS0_SELECT_INPUT
@ kIOMUXC_LPSPI4_PCS0_SELECT_INPUT
Definition: MIMXRT1052.h:657
kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT
@ kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT
Definition: MIMXRT1052.h:692
kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT
@ kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT
Definition: MIMXRT1052.h:682
kIOMUXC_LPUART3_RX_SELECT_INPUT
@ kIOMUXC_LPUART3_RX_SELECT_INPUT
Definition: MIMXRT1052.h:664
kIOMUXC_LPI2C1_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C1_SCL_SELECT_INPUT
Definition: MIMXRT1052.h:637
kIOMUXC_CSI_DATA06_SELECT_INPUT
@ kIOMUXC_CSI_DATA06_SELECT_INPUT
Definition: MIMXRT1052.h:590
kIOMUXC_LPUART2_RX_SELECT_INPUT
@ kIOMUXC_LPUART2_RX_SELECT_INPUT
Definition: MIMXRT1052.h:661
kIOMUXC_USDHC2_DATA7_SELECT_INPUT
@ kIOMUXC_USDHC2_DATA7_SELECT_INPUT
Definition: MIMXRT1052.h:715
kIOMUXC_LPI2C3_SCL_SELECT_INPUT
@ kIOMUXC_LPI2C3_SCL_SELECT_INPUT
Definition: MIMXRT1052.h:641
kIOMUXC_XBAR_INOUT03_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT03_SELECT_INPUT
Definition: MIMXRT1052.h:718
kIOMUXC_LPUART2_TX_SELECT_INPUT
@ kIOMUXC_LPUART2_TX_SELECT_INPUT
Definition: MIMXRT1052.h:662
kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT
@ kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT
Definition: MIMXRT1052.h:690
kIOMUXC_LPUART5_TX_SELECT_INPUT
@ kIOMUXC_LPUART5_TX_SELECT_INPUT
Definition: MIMXRT1052.h:669
kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT
@ kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT
Definition: MIMXRT1052.h:624
kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT
@ kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT
Definition: MIMXRT1052.h:625
kIOMUXC_LPSPI3_SCK_SELECT_INPUT
@ kIOMUXC_LPSPI3_SCK_SELECT_INPUT
Definition: MIMXRT1052.h:654
kIOMUXC_LPSPI2_PCS0_SELECT_INPUT
@ kIOMUXC_LPSPI2_PCS0_SELECT_INPUT
Definition: MIMXRT1052.h:649
kIOMUXC_CSI_DATA07_SELECT_INPUT
@ kIOMUXC_CSI_DATA07_SELECT_INPUT
Definition: MIMXRT1052.h:591
kIOMUXC_CSI_DATA05_SELECT_INPUT
@ kIOMUXC_CSI_DATA05_SELECT_INPUT
Definition: MIMXRT1052.h:589
kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT
@ kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT
Definition: MIMXRT1052.h:683
kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT
Definition: MIMXRT1052.h:680
kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT
@ kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT
Definition: MIMXRT1052.h:631
kIOMUXC_ENET0_RXDATA_SELECT_INPUT
@ kIOMUXC_ENET0_RXDATA_SELECT_INPUT
Definition: MIMXRT1052.h:599
kIOMUXC_SPDIF_IN_SELECT_INPUT
@ kIOMUXC_SPDIF_IN_SELECT_INPUT
Definition: MIMXRT1052.h:700
kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT
@ kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT
Definition: MIMXRT1052.h:626
kIOMUXC_XBAR_INOUT14_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT14_SELECT_INPUT
Definition: MIMXRT1052.h:731
kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT
@ kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT
Definition: MIMXRT1052.h:699
kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT
@ kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT
Definition: MIMXRT1052.h:583
kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT
@ kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT
Definition: MIMXRT1052.h:684
kIOMUXC_XBAR_INOUT16_SELECT_INPUT
@ kIOMUXC_XBAR_INOUT16_SELECT_INPUT
Definition: MIMXRT1052.h:733
kIOMUXC_USB_OTG2_OC_SELECT_INPUT
@ kIOMUXC_USB_OTG2_OC_SELECT_INPUT
Definition: MIMXRT1052.h:701
kIOMUXC_LPUART7_TX_SELECT_INPUT
@ kIOMUXC_LPUART7_TX_SELECT_INPUT
Definition: MIMXRT1052.h:673
kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT
Definition: MIMXRT1052.h:619
kIOMUXC_LPUART5_RX_SELECT_INPUT
@ kIOMUXC_LPUART5_RX_SELECT_INPUT
Definition: MIMXRT1052.h:668
kIOMUXC_LPUART4_TX_SELECT_INPUT
@ kIOMUXC_LPUART4_TX_SELECT_INPUT
Definition: MIMXRT1052.h:667
kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT
@ kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT
Definition: MIMXRT1052.h:677
kIOMUXC_LPSPI3_SDO_SELECT_INPUT
@ kIOMUXC_LPSPI3_SDO_SELECT_INPUT
Definition: MIMXRT1052.h:656
kIOMUXC_ENET_RXEN_SELECT_INPUT
@ kIOMUXC_ENET_RXEN_SELECT_INPUT
Definition: MIMXRT1052.h:601
kIOMUXC_LPUART3_TX_SELECT_INPUT
@ kIOMUXC_LPUART3_TX_SELECT_INPUT
Definition: MIMXRT1052.h:665
kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT
@ kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT
Definition: MIMXRT1052.h:616
kIOMUXC_LPSPI4_SDI_SELECT_INPUT
@ kIOMUXC_LPSPI4_SDI_SELECT_INPUT
Definition: MIMXRT1052.h:659
kIOMUXC_USDHC1_CD_B_SELECT_INPUT
@ kIOMUXC_USDHC1_CD_B_SELECT_INPUT
Definition: MIMXRT1052.h:703
kIOMUXC_LPI2C4_SDA_SELECT_INPUT
@ kIOMUXC_LPI2C4_SDA_SELECT_INPUT
Definition: MIMXRT1052.h:644
kIOMUXC_ENET_MDIO_SELECT_INPUT
@ kIOMUXC_ENET_MDIO_SELECT_INPUT
Definition: MIMXRT1052.h:598
kIOMUXC_CSI_VSYNC_SELECT_INPUT
@ kIOMUXC_CSI_VSYNC_SELECT_INPUT
Definition: MIMXRT1052.h:596
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04
Definition: MIMXRT1052.h:399
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08
Definition: MIMXRT1052.h:387
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
Definition: MIMXRT1052.h:372
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21
Definition: MIMXRT1052.h:326
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05
Definition: MIMXRT1052.h:352
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10
Definition: MIMXRT1052.h:315
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
Definition: MIMXRT1052.h:342
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
Definition: MIMXRT1052.h:381
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07
Definition: MIMXRT1052.h:386
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08
Definition: MIMXRT1052.h:403
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
Definition: MIMXRT1052.h:382
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
Definition: MIMXRT1052.h:370
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09
Definition: MIMXRT1052.h:314
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18
Definition: MIMXRT1052.h:323
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35
Definition: MIMXRT1052.h:340
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
Definition: MIMXRT1052.h:389
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13
Definition: MIMXRT1052.h:376
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
Definition: MIMXRT1052.h:379
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00
Definition: MIMXRT1052.h:305
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
Definition: MIMXRT1052.h:416
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02
Definition: MIMXRT1052.h:397
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15
Definition: MIMXRT1052.h:394
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15
Definition: MIMXRT1052.h:362
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
Definition: MIMXRT1052.h:396
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12
Definition: MIMXRT1052.h:407
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11
Definition: MIMXRT1052.h:358
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
Definition: MIMXRT1052.h:371
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
Definition: MIMXRT1052.h:309
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
Definition: MIMXRT1052.h:350
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
Definition: MIMXRT1052.h:311
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
Definition: MIMXRT1052.h:364
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04
Definition: MIMXRT1052.h:351
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
Definition: MIMXRT1052.h:349
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15
Definition: MIMXRT1052.h:320
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07
Definition: MIMXRT1052.h:402
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
Definition: MIMXRT1052.h:414
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12
Definition: MIMXRT1052.h:317
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
Definition: MIMXRT1052.h:337
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40
Definition: MIMXRT1052.h:345
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
Definition: MIMXRT1052.h:366
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13
Definition: MIMXRT1052.h:408
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
Definition: MIMXRT1052.h:390
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04
Definition: MIMXRT1052.h:367
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08
Definition: MIMXRT1052.h:425
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09
Definition: MIMXRT1052.h:426
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23
Definition: MIMXRT1052.h:328
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03
Definition: MIMXRT1052.h:420
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07
Definition: MIMXRT1052.h:424
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38
Definition: MIMXRT1052.h:343
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
Definition: MIMXRT1052.h:359
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34
Definition: MIMXRT1052.h:339
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15
Definition: MIMXRT1052.h:410
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10
Definition: MIMXRT1052.h:427
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02
Definition: MIMXRT1052.h:307
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06
Definition: MIMXRT1052.h:423
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30
Definition: MIMXRT1052.h:335
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05
Definition: MIMXRT1052.h:368
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
Definition: MIMXRT1052.h:373
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
Definition: MIMXRT1052.h:312
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28
Definition: MIMXRT1052.h:333
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
Definition: MIMXRT1052.h:363
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14
Definition: MIMXRT1052.h:361
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11
Definition: MIMXRT1052.h:316
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14
Definition: MIMXRT1052.h:409
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00
Definition: MIMXRT1052.h:417
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39
Definition: MIMXRT1052.h:344
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11
Definition: MIMXRT1052.h:428
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01
Definition: MIMXRT1052.h:306
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01
Definition: MIMXRT1052.h:348
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14
Definition: MIMXRT1052.h:319
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13
Definition: MIMXRT1052.h:392
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11
Definition: MIMXRT1052.h:406
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
Definition: MIMXRT1052.h:378
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09
Definition: MIMXRT1052.h:356
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26
Definition: MIMXRT1052.h:331
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
Definition: MIMXRT1052.h:336
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33
Definition: MIMXRT1052.h:338
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
Definition: MIMXRT1052.h:412
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04
Definition: MIMXRT1052.h:421
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14
Definition: MIMXRT1052.h:393
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25
Definition: MIMXRT1052.h:330
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27
Definition: MIMXRT1052.h:332
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09
Definition: MIMXRT1052.h:388
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07
Definition: MIMXRT1052.h:354
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
Definition: MIMXRT1052.h:395
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16
Definition: MIMXRT1052.h:321
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
Definition: MIMXRT1052.h:341
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03
Definition: MIMXRT1052.h:308
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
Definition: MIMXRT1052.h:374
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05
Definition: MIMXRT1052.h:400
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20
Definition: MIMXRT1052.h:325
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19
Definition: MIMXRT1052.h:324
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
Definition: MIMXRT1052.h:360
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06
Definition: MIMXRT1052.h:353
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10
Definition: MIMXRT1052.h:357
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
Definition: MIMXRT1052.h:365
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09
Definition: MIMXRT1052.h:404
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41
Definition: MIMXRT1052.h:346
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
Definition: MIMXRT1052.h:415
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00
Definition: MIMXRT1052.h:347
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04
Definition: MIMXRT1052.h:383
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01
Definition: MIMXRT1052.h:418
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12
Definition: MIMXRT1052.h:375
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
Definition: MIMXRT1052.h:329
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10
Definition: MIMXRT1052.h:405
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
Definition: MIMXRT1052.h:377
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
Definition: MIMXRT1052.h:411
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
Definition: MIMXRT1052.h:413
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05
Definition: MIMXRT1052.h:422
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02
Definition: MIMXRT1052.h:419
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
Definition: MIMXRT1052.h:310
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03
Definition: MIMXRT1052.h:398
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06
Definition: MIMXRT1052.h:385
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
Definition: MIMXRT1052.h:380
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13
Definition: MIMXRT1052.h:318
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
Definition: MIMXRT1052.h:369
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06
Definition: MIMXRT1052.h:401
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29
Definition: MIMXRT1052.h:334
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
Definition: MIMXRT1052.h:327
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
Definition: MIMXRT1052.h:313
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
Definition: MIMXRT1052.h:391
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08
Definition: MIMXRT1052.h:355
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17
Definition: MIMXRT1052.h:322
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05
@ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05
Definition: MIMXRT1052.h:384
kXBARB2_InputAcmp1Out
@ kXBARB2_InputAcmp1Out
Definition: MIMXRT1052.h:835
kXBARA1_InputDmaDone7
@ kXBARA1_InputDmaDone7
Definition: MIMXRT1052.h:812
kXBARA1_InputDmaDone6
@ kXBARA1_InputDmaDone6
Definition: MIMXRT1052.h:811
kXBARB3_InputFlexpwm4Pwm4OutTrig01
@ kXBARB3_InputFlexpwm4Pwm4OutTrig01
Definition: MIMXRT1052.h:922
kXBARA1_InputIomuxXbarIn24
@ kXBARA1_InputIomuxXbarIn24
Definition: MIMXRT1052.h:765
kXBARB3_InputQtimer4Tmr0Output
@ kXBARB3_InputQtimer4Tmr0Output
Definition: MIMXRT1052.h:903
kXBARB2_InputQtimer4Tmr2Output
@ kXBARB2_InputQtimer4Tmr2Output
Definition: MIMXRT1052.h:847
kXBARB3_InputRESERVED11
@ kXBARB3_InputRESERVED11
Definition: MIMXRT1052.h:898
kXBARB3_InputDmaDone3
@ kXBARB3_InputDmaDone3
Definition: MIMXRT1052.h:940
kXBARB2_InputQtimer4Tmr3Output
@ kXBARB2_InputQtimer4Tmr3Output
Definition: MIMXRT1052.h:848
kXBARB2_InputDmaDone4
@ kXBARB2_InputDmaDone4
Definition: MIMXRT1052.h:883
kXBARA1_InputAoi2Out1
@ kXBARA1_InputAoi2Out1
Definition: MIMXRT1052.h:818
kXBARB3_InputFlexpwm4Pwm3OutTrig01
@ kXBARB3_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1052.h:921
kXBARA1_InputFlexpwm1Pwm3OutTrig01
@ kXBARA1_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1052.h:783
kXBARB3_InputQtimer3Tmr1Output
@ kXBARB3_InputQtimer3Tmr1Output
Definition: MIMXRT1052.h:900
kXBARB2_InputQtimer3Tmr0Output
@ kXBARB2_InputQtimer3Tmr0Output
Definition: MIMXRT1052.h:841
kXBARA1_InputIomuxXbarInout14
@ kXBARA1_InputIomuxXbarInout14
Definition: MIMXRT1052.h:755
kXBARB2_InputAdcEtcXbar1Coco0
@ kXBARB2_InputAdcEtcXbar1Coco0
Definition: MIMXRT1052.h:871
kXBARB3_InputQtimer4Tmr1Output
@ kXBARB3_InputQtimer4Tmr1Output
Definition: MIMXRT1052.h:904
kXBARA1_InputAdcEtcXbar0Coco3
@ kXBARA1_InputAdcEtcXbar0Coco3
Definition: MIMXRT1052.h:824
kXBARA1_InputQtimer4Tmr2Output
@ kXBARA1_InputQtimer4Tmr2Output
Definition: MIMXRT1052.h:779
kXBARA1_InputIomuxXbarIn03
@ kXBARA1_InputIomuxXbarIn03
Definition: MIMXRT1052.h:744
kXBARB2_InputFlexpwm2Pwm3OutTrig01
@ kXBARB2_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1052.h:855
kXBARB2_InputFlexpwm1Pwm1OutTrig01
@ kXBARB2_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1052.h:849
kXBARA1_InputIomuxXbarInout05
@ kXBARA1_InputIomuxXbarInout05
Definition: MIMXRT1052.h:746
kXBARB3_InputAcmp1Out
@ kXBARB3_InputAcmp1Out
Definition: MIMXRT1052.h:893
kXBARB3_InputAcmp2Out
@ kXBARB3_InputAcmp2Out
Definition: MIMXRT1052.h:894
kXBARB3_InputEnc1PosMatch
@ kXBARB3_InputEnc1PosMatch
Definition: MIMXRT1052.h:933
kXBARA1_InputDmaDone0
@ kXBARA1_InputDmaDone0
Definition: MIMXRT1052.h:805
kXBARB2_InputFlexpwm1Pwm3OutTrig01
@ kXBARB2_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1052.h:851
kXBARA1_InputIomuxXbarInout17
@ kXBARA1_InputIomuxXbarInout17
Definition: MIMXRT1052.h:758
kXBARA1_InputAoi2Out0
@ kXBARA1_InputAoi2Out0
Definition: MIMXRT1052.h:817
kXBARA1_InputIomuxXbarInout06
@ kXBARA1_InputIomuxXbarInout06
Definition: MIMXRT1052.h:747
kXBARA1_InputPitTrigger0
@ kXBARA1_InputPitTrigger0
Definition: MIMXRT1052.h:797
kXBARB2_InputFlexpwm2Pwm2OutTrig01
@ kXBARB2_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1052.h:854
kXBARA1_InputPitTrigger2
@ kXBARA1_InputPitTrigger2
Definition: MIMXRT1052.h:799
kXBARA1_InputIomuxXbarIn02
@ kXBARA1_InputIomuxXbarIn02
Definition: MIMXRT1052.h:743
kXBARA1_InputAoi1Out0
@ kXBARA1_InputAoi1Out0
Definition: MIMXRT1052.h:813
kXBARB3_InputDmaDone1
@ kXBARB3_InputDmaDone1
Definition: MIMXRT1052.h:938
kXBARA1_InputIomuxXbarInout11
@ kXBARA1_InputIomuxXbarInout11
Definition: MIMXRT1052.h:752
kXBARA1_InputIomuxXbarIn22
@ kXBARA1_InputIomuxXbarIn22
Definition: MIMXRT1052.h:763
kXBARA1_InputQtimer4Tmr1Output
@ kXBARA1_InputQtimer4Tmr1Output
Definition: MIMXRT1052.h:778
kXBARA1_InputFlexpwm1Pwm2OutTrig01
@ kXBARA1_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1052.h:782
kXBARB2_InputRESERVED11
@ kXBARB2_InputRESERVED11
Definition: MIMXRT1052.h:840
kXBARB2_InputFlexpwm3Pwm3OutTrig01
@ kXBARB2_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1052.h:859
kXBARA1_InputIomuxXbarInout18
@ kXBARA1_InputIomuxXbarInout18
Definition: MIMXRT1052.h:759
kXBARA1_InputFlexpwm3Pwm1OutTrig01
@ kXBARA1_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1052.h:789
kXBARB2_InputQtimer4Tmr0Output
@ kXBARB2_InputQtimer4Tmr0Output
Definition: MIMXRT1052.h:845
kXBARB2_InputDmaDone3
@ kXBARB2_InputDmaDone3
Definition: MIMXRT1052.h:882
kXBARB3_InputAdcEtcXbar1Coco2
@ kXBARB3_InputAdcEtcXbar1Coco2
Definition: MIMXRT1052.h:931
kXBARB3_InputFlexpwm3Pwm1OutTrig01
@ kXBARB3_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1052.h:915
kXBARB3_InputQtimer4Tmr3Output
@ kXBARB3_InputQtimer4Tmr3Output
Definition: MIMXRT1052.h:906
kXBARB3_InputEnc2PosMatch
@ kXBARB3_InputEnc2PosMatch
Definition: MIMXRT1052.h:934
kXBARB3_InputAdcEtcXbar0Coco1
@ kXBARB3_InputAdcEtcXbar0Coco1
Definition: MIMXRT1052.h:926
kXBARA1_InputAdcEtcXbar0Coco2
@ kXBARA1_InputAdcEtcXbar0Coco2
Definition: MIMXRT1052.h:823
kXBARB3_InputAdcEtcXbar0Coco0
@ kXBARB3_InputAdcEtcXbar0Coco0
Definition: MIMXRT1052.h:925
kXBARB2_InputDmaDone7
@ kXBARB2_InputDmaDone7
Definition: MIMXRT1052.h:886
kXBARB2_InputAdcEtcXbar0Coco2
@ kXBARB2_InputAdcEtcXbar0Coco2
Definition: MIMXRT1052.h:869
kXBARB2_InputRESERVED10
@ kXBARB2_InputRESERVED10
Definition: MIMXRT1052.h:839
kXBARB3_InputPitTrigger1
@ kXBARB3_InputPitTrigger1
Definition: MIMXRT1052.h:924
kXBARA1_InputQtimer4Tmr3Output
@ kXBARA1_InputQtimer4Tmr3Output
Definition: MIMXRT1052.h:780
kXBARB2_InputAcmp2Out
@ kXBARB2_InputAcmp2Out
Definition: MIMXRT1052.h:836
kXBARA1_InputIomuxXbarIn21
@ kXBARA1_InputIomuxXbarIn21
Definition: MIMXRT1052.h:762
kXBARA1_InputEnc3PosMatch
@ kXBARA1_InputEnc3PosMatch
Definition: MIMXRT1052.h:803
kXBARB3_InputRESERVED4
@ kXBARB3_InputRESERVED4
Definition: MIMXRT1052.h:891
kXBARB2_InputFlexpwm3Pwm2OutTrig01
@ kXBARB2_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1052.h:858
kXBARB2_InputEnc2PosMatch
@ kXBARB2_InputEnc2PosMatch
Definition: MIMXRT1052.h:876
kXBARA1_InputIomuxXbarIn20
@ kXBARA1_InputIomuxXbarIn20
Definition: MIMXRT1052.h:761
kXBARA1_InputAdcEtcXbar1Coco1
@ kXBARA1_InputAdcEtcXbar1Coco1
Definition: MIMXRT1052.h:826
kXBARB2_InputDmaDone2
@ kXBARB2_InputDmaDone2
Definition: MIMXRT1052.h:881
kXBARB3_InputLogicLow
@ kXBARB3_InputLogicLow
Definition: MIMXRT1052.h:887
kXBARA1_InputAdcEtcXbar0Coco0
@ kXBARA1_InputAdcEtcXbar0Coco0
Definition: MIMXRT1052.h:821
kXBARB3_InputFlexpwm3Pwm4OutTrig01
@ kXBARB3_InputFlexpwm3Pwm4OutTrig01
Definition: MIMXRT1052.h:918
kXBARB2_InputDmaDone5
@ kXBARB2_InputDmaDone5
Definition: MIMXRT1052.h:884
kXBARA1_InputAoi2Out3
@ kXBARA1_InputAoi2Out3
Definition: MIMXRT1052.h:820
kXBARA1_InputPitTrigger3
@ kXBARA1_InputPitTrigger3
Definition: MIMXRT1052.h:800
kXBARA1_InputEnc4PosMatch
@ kXBARA1_InputEnc4PosMatch
Definition: MIMXRT1052.h:804
kXBARB3_InputQtimer4Tmr2Output
@ kXBARB3_InputQtimer4Tmr2Output
Definition: MIMXRT1052.h:905
kXBARA1_InputRESERVED31
@ kXBARA1_InputRESERVED31
Definition: MIMXRT1052.h:772
kXBARA1_InputLogicLow
@ kXBARA1_InputLogicLow
Definition: MIMXRT1052.h:741
kXBARB3_InputQtimer3Tmr0Output
@ kXBARB3_InputQtimer3Tmr0Output
Definition: MIMXRT1052.h:899
kXBARB2_InputRESERVED2
@ kXBARB2_InputRESERVED2
Definition: MIMXRT1052.h:831
kXBARB2_InputAdcEtcXbar0Coco3
@ kXBARB2_InputAdcEtcXbar0Coco3
Definition: MIMXRT1052.h:870
kXBARA1_InputIomuxXbarInout16
@ kXBARA1_InputIomuxXbarInout16
Definition: MIMXRT1052.h:757
kXBARB3_InputFlexpwm1Pwm4OutTrig01
@ kXBARB3_InputFlexpwm1Pwm4OutTrig01
Definition: MIMXRT1052.h:910
kXBARB3_InputDmaDone7
@ kXBARB3_InputDmaDone7
Definition: MIMXRT1052.h:944
kXBARB3_InputDmaDone0
@ kXBARB3_InputDmaDone0
Definition: MIMXRT1052.h:937
kXBARB3_InputAdcEtcXbar1Coco1
@ kXBARB3_InputAdcEtcXbar1Coco1
Definition: MIMXRT1052.h:930
kXBARB2_InputRESERVED3
@ kXBARB2_InputRESERVED3
Definition: MIMXRT1052.h:832
kXBARA1_InputAcmp4Out
@ kXBARA1_InputAcmp4Out
Definition: MIMXRT1052.h:770
kXBARB3_InputEnc4PosMatch
@ kXBARB3_InputEnc4PosMatch
Definition: MIMXRT1052.h:936
kXBARA1_InputIomuxXbarInout07
@ kXBARA1_InputIomuxXbarInout07
Definition: MIMXRT1052.h:748
kXBARB2_InputRESERVED4
@ kXBARB2_InputRESERVED4
Definition: MIMXRT1052.h:833
kXBARB2_InputAdcEtcXbar1Coco3
@ kXBARB2_InputAdcEtcXbar1Coco3
Definition: MIMXRT1052.h:874
kXBARA1_InputFlexpwm2Pwm3OutTrig01
@ kXBARA1_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1052.h:787
kXBARA1_InputFlexpwm4Pwm4OutTrig01
@ kXBARA1_InputFlexpwm4Pwm4OutTrig01
Definition: MIMXRT1052.h:796
kXBARA1_InputFlexpwm3Pwm2OutTrig01
@ kXBARA1_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1052.h:790
kXBARA1_InputDmaDone4
@ kXBARA1_InputDmaDone4
Definition: MIMXRT1052.h:809
kXBARB3_InputDmaDone6
@ kXBARB3_InputDmaDone6
Definition: MIMXRT1052.h:943
kXBARB2_InputEnc3PosMatch
@ kXBARB2_InputEnc3PosMatch
Definition: MIMXRT1052.h:877
kXBARB3_InputAdcEtcXbar1Coco3
@ kXBARB3_InputAdcEtcXbar1Coco3
Definition: MIMXRT1052.h:932
kXBARB3_InputPitTrigger0
@ kXBARB3_InputPitTrigger0
Definition: MIMXRT1052.h:923
kXBARA1_InputFlexpwm3Pwm4OutTrig01
@ kXBARA1_InputFlexpwm3Pwm4OutTrig01
Definition: MIMXRT1052.h:792
kXBARB2_InputDmaDone0
@ kXBARB2_InputDmaDone0
Definition: MIMXRT1052.h:879
kXBARB3_InputFlexpwm4Pwm1OutTrig01
@ kXBARB3_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1052.h:919
kXBARB3_InputEnc3PosMatch
@ kXBARB3_InputEnc3PosMatch
Definition: MIMXRT1052.h:935
kXBARB2_InputEnc1PosMatch
@ kXBARB2_InputEnc1PosMatch
Definition: MIMXRT1052.h:875
kXBARA1_InputFlexpwm4Pwm2OutTrig01
@ kXBARA1_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1052.h:794
kXBARB2_InputRESERVED5
@ kXBARB2_InputRESERVED5
Definition: MIMXRT1052.h:834
kXBARB2_InputDmaDone6
@ kXBARB2_InputDmaDone6
Definition: MIMXRT1052.h:885
kXBARA1_InputAcmp2Out
@ kXBARA1_InputAcmp2Out
Definition: MIMXRT1052.h:768
kXBARA1_InputIomuxXbarIn23
@ kXBARA1_InputIomuxXbarIn23
Definition: MIMXRT1052.h:764
kXBARB2_InputFlexpwm3Pwm1OutTrig01
@ kXBARB2_InputFlexpwm3Pwm1OutTrig01
Definition: MIMXRT1052.h:857
kXBARA1_InputQtimer3Tmr2Output
@ kXBARA1_InputQtimer3Tmr2Output
Definition: MIMXRT1052.h:775
kXBARB3_InputLogicHigh
@ kXBARB3_InputLogicHigh
Definition: MIMXRT1052.h:888
kXBARA1_InputAcmp3Out
@ kXBARA1_InputAcmp3Out
Definition: MIMXRT1052.h:769
kXBARB2_InputAdcEtcXbar0Coco0
@ kXBARB2_InputAdcEtcXbar0Coco0
Definition: MIMXRT1052.h:867
kXBARB2_InputPitTrigger1
@ kXBARB2_InputPitTrigger1
Definition: MIMXRT1052.h:866
kXBARB2_InputEnc4PosMatch
@ kXBARB2_InputEnc4PosMatch
Definition: MIMXRT1052.h:878
kXBARB2_InputFlexpwm4Pwm4OutTrig01
@ kXBARB2_InputFlexpwm4Pwm4OutTrig01
Definition: MIMXRT1052.h:864
kXBARB2_InputFlexpwm4Pwm3OutTrig01
@ kXBARB2_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1052.h:863
kXBARB3_InputRESERVED3
@ kXBARB3_InputRESERVED3
Definition: MIMXRT1052.h:890
kXBARB2_InputFlexpwm4Pwm2OutTrig01
@ kXBARB2_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1052.h:862
kXBARB2_InputQtimer4Tmr1Output
@ kXBARB2_InputQtimer4Tmr1Output
Definition: MIMXRT1052.h:846
kXBARB2_InputFlexpwm2Pwm1OutTrig01
@ kXBARB2_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1052.h:853
kXBARB3_InputQtimer3Tmr2Output
@ kXBARB3_InputQtimer3Tmr2Output
Definition: MIMXRT1052.h:901
kXBARA1_InputAoi1Out3
@ kXBARA1_InputAoi1Out3
Definition: MIMXRT1052.h:816
kXBARB2_InputAcmp4Out
@ kXBARB2_InputAcmp4Out
Definition: MIMXRT1052.h:838
kXBARA1_InputAdcEtcXbar1Coco2
@ kXBARA1_InputAdcEtcXbar1Coco2
Definition: MIMXRT1052.h:827
kXBARA1_InputFlexpwm2Pwm4OutTrig01
@ kXBARA1_InputFlexpwm2Pwm4OutTrig01
Definition: MIMXRT1052.h:788
kXBARB2_InputAdcEtcXbar0Coco1
@ kXBARB2_InputAdcEtcXbar0Coco1
Definition: MIMXRT1052.h:868
kXBARB3_InputFlexpwm1Pwm1OutTrig01
@ kXBARB3_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1052.h:907
kXBARB2_InputQtimer3Tmr2Output
@ kXBARB2_InputQtimer3Tmr2Output
Definition: MIMXRT1052.h:843
kXBARA1_InputAcmp1Out
@ kXBARA1_InputAcmp1Out
Definition: MIMXRT1052.h:767
kXBARB2_InputQtimer3Tmr3Output
@ kXBARB2_InputQtimer3Tmr3Output
Definition: MIMXRT1052.h:844
kXBARA1_InputIomuxXbarInout10
@ kXBARA1_InputIomuxXbarInout10
Definition: MIMXRT1052.h:751
kXBARA1_InputEnc1PosMatch
@ kXBARA1_InputEnc1PosMatch
Definition: MIMXRT1052.h:801
kXBARB3_InputAdcEtcXbar1Coco0
@ kXBARB3_InputAdcEtcXbar1Coco0
Definition: MIMXRT1052.h:929
kXBARB3_InputFlexpwm3Pwm2OutTrig01
@ kXBARB3_InputFlexpwm3Pwm2OutTrig01
Definition: MIMXRT1052.h:916
kXBARA1_InputIomuxXbarInout12
@ kXBARA1_InputIomuxXbarInout12
Definition: MIMXRT1052.h:753
kXBARB2_InputAcmp3Out
@ kXBARB2_InputAcmp3Out
Definition: MIMXRT1052.h:837
kXBARB3_InputFlexpwm3Pwm3OutTrig01
@ kXBARB3_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1052.h:917
kXBARB3_InputQtimer3Tmr3Output
@ kXBARB3_InputQtimer3Tmr3Output
Definition: MIMXRT1052.h:902
kXBARB3_InputFlexpwm4Pwm2OutTrig01
@ kXBARB3_InputFlexpwm4Pwm2OutTrig01
Definition: MIMXRT1052.h:920
kXBARB2_InputFlexpwm2Pwm4OutTrig01
@ kXBARB2_InputFlexpwm2Pwm4OutTrig01
Definition: MIMXRT1052.h:856
kXBARB3_InputAdcEtcXbar0Coco2
@ kXBARB3_InputAdcEtcXbar0Coco2
Definition: MIMXRT1052.h:927
kXBARB3_InputDmaDone4
@ kXBARB3_InputDmaDone4
Definition: MIMXRT1052.h:941
kXBARB2_InputPitTrigger0
@ kXBARB2_InputPitTrigger0
Definition: MIMXRT1052.h:865
kXBARA1_InputDmaDone5
@ kXBARA1_InputDmaDone5
Definition: MIMXRT1052.h:810
kXBARB2_InputFlexpwm1Pwm4OutTrig01
@ kXBARB2_InputFlexpwm1Pwm4OutTrig01
Definition: MIMXRT1052.h:852
kXBARB2_InputLogicLow
@ kXBARB2_InputLogicLow
Definition: MIMXRT1052.h:829
kXBARA1_InputFlexpwm2Pwm2OutTrig01
@ kXBARA1_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1052.h:786
kXBARB2_InputFlexpwm1Pwm2OutTrig01
@ kXBARB2_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1052.h:850
kXBARA1_InputQtimer3Tmr0Output
@ kXBARA1_InputQtimer3Tmr0Output
Definition: MIMXRT1052.h:773
kXBARA1_InputAoi1Out1
@ kXBARA1_InputAoi1Out1
Definition: MIMXRT1052.h:814
kXBARA1_InputFlexpwm1Pwm1OutTrig01
@ kXBARA1_InputFlexpwm1Pwm1OutTrig01
Definition: MIMXRT1052.h:781
kXBARB2_InputFlexpwm3Pwm4OutTrig01
@ kXBARB2_InputFlexpwm3Pwm4OutTrig01
Definition: MIMXRT1052.h:860
kXBARA1_InputAoi1Out2
@ kXBARA1_InputAoi1Out2
Definition: MIMXRT1052.h:815
kXBARA1_InputDmaDone3
@ kXBARA1_InputDmaDone3
Definition: MIMXRT1052.h:808
kXBARA1_InputFlexpwm4Pwm3OutTrig01
@ kXBARA1_InputFlexpwm4Pwm3OutTrig01
Definition: MIMXRT1052.h:795
kXBARA1_InputIomuxXbarInout08
@ kXBARA1_InputIomuxXbarInout08
Definition: MIMXRT1052.h:749
kXBARB3_InputAcmp4Out
@ kXBARB3_InputAcmp4Out
Definition: MIMXRT1052.h:896
kXBARA1_InputIomuxXbarInout13
@ kXBARA1_InputIomuxXbarInout13
Definition: MIMXRT1052.h:754
kXBARA1_InputRESERVED30
@ kXBARA1_InputRESERVED30
Definition: MIMXRT1052.h:771
kXBARB3_InputDmaDone2
@ kXBARB3_InputDmaDone2
Definition: MIMXRT1052.h:939
kXBARB2_InputAdcEtcXbar1Coco2
@ kXBARB2_InputAdcEtcXbar1Coco2
Definition: MIMXRT1052.h:873
kXBARB3_InputFlexpwm2Pwm3OutTrig01
@ kXBARB3_InputFlexpwm2Pwm3OutTrig01
Definition: MIMXRT1052.h:913
kXBARB2_InputQtimer3Tmr1Output
@ kXBARB2_InputQtimer3Tmr1Output
Definition: MIMXRT1052.h:842
kXBARB3_InputFlexpwm2Pwm1OutTrig01
@ kXBARB3_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1052.h:911
kXBARA1_InputIomuxXbarIn25
@ kXBARA1_InputIomuxXbarIn25
Definition: MIMXRT1052.h:766
kXBARA1_InputPitTrigger1
@ kXBARA1_InputPitTrigger1
Definition: MIMXRT1052.h:798
kXBARA1_InputFlexpwm2Pwm1OutTrig01
@ kXBARA1_InputFlexpwm2Pwm1OutTrig01
Definition: MIMXRT1052.h:785
kXBARA1_InputLogicHigh
@ kXBARA1_InputLogicHigh
Definition: MIMXRT1052.h:742
kXBARA1_InputQtimer4Tmr0Output
@ kXBARA1_InputQtimer4Tmr0Output
Definition: MIMXRT1052.h:777
kXBARB3_InputFlexpwm1Pwm3OutTrig01
@ kXBARB3_InputFlexpwm1Pwm3OutTrig01
Definition: MIMXRT1052.h:909
kXBARA1_InputIomuxXbarInout04
@ kXBARA1_InputIomuxXbarInout04
Definition: MIMXRT1052.h:745
kXBARB3_InputAdcEtcXbar0Coco3
@ kXBARB3_InputAdcEtcXbar0Coco3
Definition: MIMXRT1052.h:928
kXBARB2_InputFlexpwm4Pwm1OutTrig01
@ kXBARB2_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1052.h:861
kXBARA1_InputQtimer3Tmr3Output
@ kXBARA1_InputQtimer3Tmr3Output
Definition: MIMXRT1052.h:776
kXBARA1_InputFlexpwm4Pwm1OutTrig01
@ kXBARA1_InputFlexpwm4Pwm1OutTrig01
Definition: MIMXRT1052.h:793
kXBARB2_InputLogicHigh
@ kXBARB2_InputLogicHigh
Definition: MIMXRT1052.h:830
kXBARA1_InputFlexpwm1Pwm4OutTrig01
@ kXBARA1_InputFlexpwm1Pwm4OutTrig01
Definition: MIMXRT1052.h:784
kXBARB3_InputFlexpwm1Pwm2OutTrig01
@ kXBARB3_InputFlexpwm1Pwm2OutTrig01
Definition: MIMXRT1052.h:908
kXBARA1_InputEnc2PosMatch
@ kXBARA1_InputEnc2PosMatch
Definition: MIMXRT1052.h:802
kXBARA1_InputAdcEtcXbar0Coco1
@ kXBARA1_InputAdcEtcXbar0Coco1
Definition: MIMXRT1052.h:822
kXBARA1_InputIomuxXbarInout19
@ kXBARA1_InputIomuxXbarInout19
Definition: MIMXRT1052.h:760
kXBARB3_InputRESERVED5
@ kXBARB3_InputRESERVED5
Definition: MIMXRT1052.h:892
kXBARB3_InputFlexpwm2Pwm2OutTrig01
@ kXBARB3_InputFlexpwm2Pwm2OutTrig01
Definition: MIMXRT1052.h:912
kXBARA1_InputAdcEtcXbar1Coco3
@ kXBARA1_InputAdcEtcXbar1Coco3
Definition: MIMXRT1052.h:828
kXBARB3_InputRESERVED2
@ kXBARB3_InputRESERVED2
Definition: MIMXRT1052.h:889
kXBARA1_InputFlexpwm3Pwm3OutTrig01
@ kXBARA1_InputFlexpwm3Pwm3OutTrig01
Definition: MIMXRT1052.h:791
kXBARB2_InputAdcEtcXbar1Coco1
@ kXBARB2_InputAdcEtcXbar1Coco1
Definition: MIMXRT1052.h:872
kXBARB3_InputFlexpwm2Pwm4OutTrig01
@ kXBARB3_InputFlexpwm2Pwm4OutTrig01
Definition: MIMXRT1052.h:914
kXBARA1_InputQtimer3Tmr1Output
@ kXBARA1_InputQtimer3Tmr1Output
Definition: MIMXRT1052.h:774
kXBARA1_InputDmaDone2
@ kXBARA1_InputDmaDone2
Definition: MIMXRT1052.h:807
kXBARA1_InputAoi2Out2
@ kXBARA1_InputAoi2Out2
Definition: MIMXRT1052.h:819
kXBARA1_InputIomuxXbarInout09
@ kXBARA1_InputIomuxXbarInout09
Definition: MIMXRT1052.h:750
kXBARA1_InputIomuxXbarInout15
@ kXBARA1_InputIomuxXbarInout15
Definition: MIMXRT1052.h:756
kXBARB3_InputRESERVED10
@ kXBARB3_InputRESERVED10
Definition: MIMXRT1052.h:897
kXBARB2_InputDmaDone1
@ kXBARB2_InputDmaDone1
Definition: MIMXRT1052.h:880
kXBARA1_InputDmaDone1
@ kXBARA1_InputDmaDone1
Definition: MIMXRT1052.h:806
kXBARA1_InputAdcEtcXbar1Coco0
@ kXBARA1_InputAdcEtcXbar1Coco0
Definition: MIMXRT1052.h:825
kXBARB3_InputDmaDone5
@ kXBARB3_InputDmaDone5
Definition: MIMXRT1052.h:942
kXBARB3_InputAcmp3Out
@ kXBARB3_InputAcmp3Out
Definition: MIMXRT1052.h:895
kXBARA1_OutputFlexpwm1ExtForce
@ kXBARA1_OutputFlexpwm1ExtForce
Definition: MIMXRT1052.h:988
kXBARB3_OutputAoi2In15
@ kXBARB3_OutputAoi2In15
Definition: MIMXRT1052.h:1111
kXBARA1_OutputQtimer4Tmr0Input
@ kXBARA1_OutputQtimer4Tmr0Input
Definition: MIMXRT1052.h:1047
kXBARA1_OutputFlexpwm3ExtSync3
@ kXBARA1_OutputFlexpwm3ExtSync3
Definition: MIMXRT1052.h:1004
kXBARA1_OutputAdcEtcXbar1Trig3
@ kXBARA1_OutputAdcEtcXbar1Trig3
Definition: MIMXRT1052.h:1059
kXBARA1_OutputFlexpwm234ExtClk
@ kXBARA1_OutputFlexpwm234ExtClk
Definition: MIMXRT1052.h:997
kXBARA1_OutputLpuart7TrgInput
@ kXBARA1_OutputLpuart7TrgInput
Definition: MIMXRT1052.h:1074
kXBARA1_OutputEnc2Home
@ kXBARA1_OutputEnc2Home
Definition: MIMXRT1052.h:1023
kXBARA1_OutputEnc4Trigger
@ kXBARA1_OutputEnc4Trigger
Definition: MIMXRT1052.h:1034
kXBARA1_OutputEnc1PhaseAInput
@ kXBARA1_OutputEnc1PhaseAInput
Definition: MIMXRT1052.h:1015
kXBARA1_OutputFlexpwm3Fault1
@ kXBARA1_OutputFlexpwm3Fault1
Definition: MIMXRT1052.h:1006
kXBARA1_OutputFlexpwm1Exta0
@ kXBARA1_OutputFlexpwm1Exta0
Definition: MIMXRT1052.h:975
kXBARA1_OutputQtimer3Tmr3Input
@ kXBARA1_OutputQtimer3Tmr3Input
Definition: MIMXRT1052.h:1046
kXBARA1_OutputIomuxXbarInout13
@ kXBARA1_OutputIomuxXbarInout13
Definition: MIMXRT1052.h:962
kXBARB3_OutputAoi2In08
@ kXBARB3_OutputAoi2In08
Definition: MIMXRT1052.h:1104
kXBARA1_OutputEnc1Index
@ kXBARA1_OutputEnc1Index
Definition: MIMXRT1052.h:1017
kXBARA1_OutputEnc3Index
@ kXBARA1_OutputEnc3Index
Definition: MIMXRT1052.h:1027
kXBARA1_OutputEnc2PhaseAInput
@ kXBARA1_OutputEnc2PhaseAInput
Definition: MIMXRT1052.h:1020
kXBARA1_OutputEnc3Home
@ kXBARA1_OutputEnc3Home
Definition: MIMXRT1052.h:1028
kXBARA1_OutputFlexpwm3ExtSync0
@ kXBARA1_OutputFlexpwm3ExtSync0
Definition: MIMXRT1052.h:1001
kXBARA1_OutputEnc1PhaseBInput
@ kXBARA1_OutputEnc1PhaseBInput
Definition: MIMXRT1052.h:1016
kXBARA1_OutputAdcEtcXbar1Trig0
@ kXBARA1_OutputAdcEtcXbar1Trig0
Definition: MIMXRT1052.h:1056
kXBARA1_OutputEnc3PhaseAInput
@ kXBARA1_OutputEnc3PhaseAInput
Definition: MIMXRT1052.h:1025
kXBARA1_OutputFlexpwm1234Fault3
@ kXBARA1_OutputFlexpwm1234Fault3
Definition: MIMXRT1052.h:987
kXBARA1_OutputFlexpwm2ExtForce
@ kXBARA1_OutputFlexpwm2ExtForce
Definition: MIMXRT1052.h:1000
kXBARA1_OutputEnc4PhaseBInput
@ kXBARA1_OutputEnc4PhaseBInput
Definition: MIMXRT1052.h:1031
kXBARA1_OutputIomuxXbarInout04
@ kXBARA1_OutputIomuxXbarInout04
Definition: MIMXRT1052.h:953
kXBARB3_OutputAoi2In10
@ kXBARB3_OutputAoi2In10
Definition: MIMXRT1052.h:1106
kXBARA1_OutputIomuxXbarInout16
@ kXBARA1_OutputIomuxXbarInout16
Definition: MIMXRT1052.h:965
kXBARA1_OutputQtimer4Tmr2Input
@ kXBARA1_OutputQtimer4Tmr2Input
Definition: MIMXRT1052.h:1049
kXBARA1_OutputQtimer1Tmr0Input
@ kXBARA1_OutputQtimer1Tmr0Input
Definition: MIMXRT1052.h:1035
kXBARB2_OutputAoi1In09
@ kXBARB2_OutputAoi1In09
Definition: MIMXRT1052.h:1089
kXBARA1_OutputRESERVED25
@ kXBARA1_OutputRESERVED25
Definition: MIMXRT1052.h:974
kXBARA1_OutputLpuart4TrgInput
@ kXBARA1_OutputLpuart4TrgInput
Definition: MIMXRT1052.h:1071
kXBARA1_OutputAcmp1Sample
@ kXBARA1_OutputAcmp1Sample
Definition: MIMXRT1052.h:969
kXBARA1_OutputLpi2c2TrgInput
@ kXBARA1_OutputLpi2c2TrgInput
Definition: MIMXRT1052.h:1061
kXBARA1_OutputFlexpwm1ExtSync2
@ kXBARA1_OutputFlexpwm1ExtSync2
Definition: MIMXRT1052.h:981
kXBARB3_OutputAoi2In01
@ kXBARB3_OutputAoi2In01
Definition: MIMXRT1052.h:1097
kXBARA1_OutputFlexpwm4Fault1
@ kXBARA1_OutputFlexpwm4Fault1
Definition: MIMXRT1052.h:1013
kXBARA1_OutputIomuxXbarInout15
@ kXBARA1_OutputIomuxXbarInout15
Definition: MIMXRT1052.h:964
kXBARB3_OutputAoi2In04
@ kXBARB3_OutputAoi2In04
Definition: MIMXRT1052.h:1100
kXBARA1_OutputFlexpwm2ExtSync0
@ kXBARA1_OutputFlexpwm2ExtSync0
Definition: MIMXRT1052.h:993
kXBARA1_OutputQtimer1Tmr1Input
@ kXBARA1_OutputQtimer1Tmr1Input
Definition: MIMXRT1052.h:1036
kXBARA1_OutputFlexpwm1ExtClk
@ kXBARA1_OutputFlexpwm1ExtClk
Definition: MIMXRT1052.h:983
kXBARA1_OutputQtimer1Tmr2Input
@ kXBARA1_OutputQtimer1Tmr2Input
Definition: MIMXRT1052.h:1037
kXBARA1_OutputAdcEtcXbar0Trig1
@ kXBARA1_OutputAdcEtcXbar0Trig1
Definition: MIMXRT1052.h:1053
kXBARB3_OutputAoi2In00
@ kXBARB3_OutputAoi2In00
Definition: MIMXRT1052.h:1096
kXBARA1_OutputQtimer2Tmr0Input
@ kXBARA1_OutputQtimer2Tmr0Input
Definition: MIMXRT1052.h:1039
kXBARA1_OutputAdcEtcXbar0Trig2
@ kXBARA1_OutputAdcEtcXbar0Trig2
Definition: MIMXRT1052.h:1054
kXBARB2_OutputAoi1In13
@ kXBARB2_OutputAoi1In13
Definition: MIMXRT1052.h:1093
kXBARA1_OutputIomuxXbarInout10
@ kXBARA1_OutputIomuxXbarInout10
Definition: MIMXRT1052.h:959
kXBARA1_OutputFlexpwm4ExtSync0
@ kXBARA1_OutputFlexpwm4ExtSync0
Definition: MIMXRT1052.h:1008
kXBARB3_OutputAoi2In09
@ kXBARB3_OutputAoi2In09
Definition: MIMXRT1052.h:1105
kXBARA1_OutputIomuxXbarInout17
@ kXBARA1_OutputIomuxXbarInout17
Definition: MIMXRT1052.h:966
kXBARA1_OutputIomuxXbarInout19
@ kXBARA1_OutputIomuxXbarInout19
Definition: MIMXRT1052.h:968
kXBARA1_OutputFlexio2TriggerIn1
@ kXBARA1_OutputFlexio2TriggerIn1
Definition: MIMXRT1052.h:1079
kXBARA1_OutputLpi2c1TrgInput
@ kXBARA1_OutputLpi2c1TrgInput
Definition: MIMXRT1052.h:1060
kXBARA1_OutputFlexio2TriggerIn0
@ kXBARA1_OutputFlexio2TriggerIn0
Definition: MIMXRT1052.h:1078
kXBARA1_OutputFlexpwm3Fault0
@ kXBARA1_OutputFlexpwm3Fault0
Definition: MIMXRT1052.h:1005
kXBARA1_OutputFlexpwm234Exta1
@ kXBARA1_OutputFlexpwm234Exta1
Definition: MIMXRT1052.h:990
kXBARA1_OutputLpuart8TrgInput
@ kXBARA1_OutputLpuart8TrgInput
Definition: MIMXRT1052.h:1075
kXBARB3_OutputAoi2In11
@ kXBARB3_OutputAoi2In11
Definition: MIMXRT1052.h:1107
kXBARA1_OutputFlexpwm1Exta3
@ kXBARA1_OutputFlexpwm1Exta3
Definition: MIMXRT1052.h:978
kXBARB3_OutputAoi2In06
@ kXBARB3_OutputAoi2In06
Definition: MIMXRT1052.h:1102
kXBARA1_OutputFlexpwm234Exta0
@ kXBARA1_OutputFlexpwm234Exta0
Definition: MIMXRT1052.h:989
kXBARB2_OutputAoi1In08
@ kXBARB2_OutputAoi1In08
Definition: MIMXRT1052.h:1088
kXBARA1_OutputQtimer4Tmr3Input
@ kXBARA1_OutputQtimer4Tmr3Input
Definition: MIMXRT1052.h:1050
kXBARA1_OutputEnc2PhaseBInput
@ kXBARA1_OutputEnc2PhaseBInput
Definition: MIMXRT1052.h:1021
kXBARA1_OutputFlexpwm2ExtSync2
@ kXBARA1_OutputFlexpwm2ExtSync2
Definition: MIMXRT1052.h:995
kXBARA1_OutputQtimer1Tmr3Input
@ kXBARA1_OutputQtimer1Tmr3Input
Definition: MIMXRT1052.h:1038
kXBARA1_OutputEnc3Trigger
@ kXBARA1_OutputEnc3Trigger
Definition: MIMXRT1052.h:1029
kXBARB3_OutputAoi2In14
@ kXBARB3_OutputAoi2In14
Definition: MIMXRT1052.h:1110
kXBARB2_OutputAoi1In04
@ kXBARB2_OutputAoi1In04
Definition: MIMXRT1052.h:1084
kXBARA1_OutputEwmEwmIn
@ kXBARA1_OutputEwmEwmIn
Definition: MIMXRT1052.h:1051
kXBARA1_OutputFlexpwm1Exta2
@ kXBARA1_OutputFlexpwm1Exta2
Definition: MIMXRT1052.h:977
kXBARB2_OutputAoi1In12
@ kXBARB2_OutputAoi1In12
Definition: MIMXRT1052.h:1092
kXBARA1_OutputFlexpwm4Fault0
@ kXBARA1_OutputFlexpwm4Fault0
Definition: MIMXRT1052.h:1012
kXBARA1_OutputIomuxXbarInout08
@ kXBARA1_OutputIomuxXbarInout08
Definition: MIMXRT1052.h:957
kXBARA1_OutputIomuxXbarInout06
@ kXBARA1_OutputIomuxXbarInout06
Definition: MIMXRT1052.h:955
kXBARA1_OutputFlexpwm3ExtSync2
@ kXBARA1_OutputFlexpwm3ExtSync2
Definition: MIMXRT1052.h:1003
kXBARA1_OutputRESERVED24
@ kXBARA1_OutputRESERVED24
Definition: MIMXRT1052.h:973
kXBARA1_OutputFlexpwm1Fault0
@ kXBARA1_OutputFlexpwm1Fault0
Definition: MIMXRT1052.h:984
kXBARA1_OutputFlexpwm1ExtSync1
@ kXBARA1_OutputFlexpwm1ExtSync1
Definition: MIMXRT1052.h:980
kXBARA1_OutputIomuxXbarInout05
@ kXBARA1_OutputIomuxXbarInout05
Definition: MIMXRT1052.h:954
kXBARB2_OutputAoi1In07
@ kXBARB2_OutputAoi1In07
Definition: MIMXRT1052.h:1087
kXBARB3_OutputAoi2In03
@ kXBARB3_OutputAoi2In03
Definition: MIMXRT1052.h:1099
kXBARA1_OutputQtimer4Tmr1Input
@ kXBARA1_OutputQtimer4Tmr1Input
Definition: MIMXRT1052.h:1048
kXBARA1_OutputIomuxXbarInout07
@ kXBARA1_OutputIomuxXbarInout07
Definition: MIMXRT1052.h:956
kXBARA1_OutputLpuart6TrgInput
@ kXBARA1_OutputLpuart6TrgInput
Definition: MIMXRT1052.h:1073
kXBARB2_OutputAoi1In00
@ kXBARB2_OutputAoi1In00
Definition: MIMXRT1052.h:1080
kXBARA1_OutputFlexpwm2ExtSync1
@ kXBARA1_OutputFlexpwm2ExtSync1
Definition: MIMXRT1052.h:994
kXBARA1_OutputLpi2c4TrgInput
@ kXBARA1_OutputLpi2c4TrgInput
Definition: MIMXRT1052.h:1063
kXBARA1_OutputAcmp2Sample
@ kXBARA1_OutputAcmp2Sample
Definition: MIMXRT1052.h:970
kXBARA1_OutputLpi2c3TrgInput
@ kXBARA1_OutputLpi2c3TrgInput
Definition: MIMXRT1052.h:1062
kXBARA1_OutputIomuxXbarInout12
@ kXBARA1_OutputIomuxXbarInout12
Definition: MIMXRT1052.h:961
kXBARB3_OutputAoi2In12
@ kXBARB3_OutputAoi2In12
Definition: MIMXRT1052.h:1108
kXBARA1_OutputQtimer3Tmr2Input
@ kXBARA1_OutputQtimer3Tmr2Input
Definition: MIMXRT1052.h:1045
kXBARB2_OutputAoi1In15
@ kXBARB2_OutputAoi1In15
Definition: MIMXRT1052.h:1095
kXBARA1_OutputFlexpwm1ExtSync0
@ kXBARA1_OutputFlexpwm1ExtSync0
Definition: MIMXRT1052.h:979
kXBARA1_OutputFlexpwm2ExtSync3
@ kXBARA1_OutputFlexpwm2ExtSync3
Definition: MIMXRT1052.h:996
kXBARA1_OutputFlexpwm2Fault1
@ kXBARA1_OutputFlexpwm2Fault1
Definition: MIMXRT1052.h:999
kXBARA1_OutputFlexpwm2Fault0
@ kXBARA1_OutputFlexpwm2Fault0
Definition: MIMXRT1052.h:998
kXBARB2_OutputAoi1In14
@ kXBARB2_OutputAoi1In14
Definition: MIMXRT1052.h:1094
kXBARA1_OutputFlexpwm3ExtForce
@ kXBARA1_OutputFlexpwm3ExtForce
Definition: MIMXRT1052.h:1007
kXBARA1_OutputFlexpwm1Fault1
@ kXBARA1_OutputFlexpwm1Fault1
Definition: MIMXRT1052.h:985
kXBARB3_OutputAoi2In13
@ kXBARB3_OutputAoi2In13
Definition: MIMXRT1052.h:1109
kXBARA1_OutputEnc2Trigger
@ kXBARA1_OutputEnc2Trigger
Definition: MIMXRT1052.h:1024
kXBARA1_OutputLpuart3TrgInput
@ kXBARA1_OutputLpuart3TrgInput
Definition: MIMXRT1052.h:1070
kXBARB2_OutputAoi1In10
@ kXBARB2_OutputAoi1In10
Definition: MIMXRT1052.h:1090
kXBARA1_OutputEnc1Home
@ kXBARA1_OutputEnc1Home
Definition: MIMXRT1052.h:1018
kXBARA1_OutputDmaChMuxReq31
@ kXBARA1_OutputDmaChMuxReq31
Definition: MIMXRT1052.h:950
kXBARA1_OutputFlexpwm1234Fault2
@ kXBARA1_OutputFlexpwm1234Fault2
Definition: MIMXRT1052.h:986
kXBARA1_OutputEnc1Trigger
@ kXBARA1_OutputEnc1Trigger
Definition: MIMXRT1052.h:1019
kXBARA1_OutputAdcEtcXbar0Trig3
@ kXBARA1_OutputAdcEtcXbar0Trig3
Definition: MIMXRT1052.h:1055
kXBARA1_OutputQtimer3Tmr0Input
@ kXBARA1_OutputQtimer3Tmr0Input
Definition: MIMXRT1052.h:1043
kXBARA1_OutputAdcEtcXbar1Trig2
@ kXBARA1_OutputAdcEtcXbar1Trig2
Definition: MIMXRT1052.h:1058
kXBARA1_OutputIomuxXbarInout14
@ kXBARA1_OutputIomuxXbarInout14
Definition: MIMXRT1052.h:963
kXBARA1_OutputEnc4Index
@ kXBARA1_OutputEnc4Index
Definition: MIMXRT1052.h:1032
kXBARA1_OutputDmaChMuxReq30
@ kXBARA1_OutputDmaChMuxReq30
Definition: MIMXRT1052.h:949
kXBARA1_OutputQtimer2Tmr3Input
@ kXBARA1_OutputQtimer2Tmr3Input
Definition: MIMXRT1052.h:1042
kXBARA1_OutputIomuxXbarInout09
@ kXBARA1_OutputIomuxXbarInout09
Definition: MIMXRT1052.h:958
kXBARA1_OutputQtimer3Tmr1Input
@ kXBARA1_OutputQtimer3Tmr1Input
Definition: MIMXRT1052.h:1044
kXBARA1_OutputLpspi1TrgInput
@ kXBARA1_OutputLpspi1TrgInput
Definition: MIMXRT1052.h:1064
kXBARA1_OutputQtimer2Tmr2Input
@ kXBARA1_OutputQtimer2Tmr2Input
Definition: MIMXRT1052.h:1041
kXBARB2_OutputAoi1In06
@ kXBARB2_OutputAoi1In06
Definition: MIMXRT1052.h:1086
kXBARA1_OutputFlexpwm4ExtSync3
@ kXBARA1_OutputFlexpwm4ExtSync3
Definition: MIMXRT1052.h:1011
kXBARB2_OutputAoi1In03
@ kXBARB2_OutputAoi1In03
Definition: MIMXRT1052.h:1083
kXBARB3_OutputAoi2In07
@ kXBARB3_OutputAoi2In07
Definition: MIMXRT1052.h:1103
kXBARB3_OutputAoi2In05
@ kXBARB3_OutputAoi2In05
Definition: MIMXRT1052.h:1101
kXBARA1_OutputLpuart5TrgInput
@ kXBARA1_OutputLpuart5TrgInput
Definition: MIMXRT1052.h:1072
kXBARB3_OutputAoi2In02
@ kXBARB3_OutputAoi2In02
Definition: MIMXRT1052.h:1098
kXBARA1_OutputFlexpwm4ExtSync1
@ kXBARA1_OutputFlexpwm4ExtSync1
Definition: MIMXRT1052.h:1009
kXBARA1_OutputIomuxXbarInout18
@ kXBARA1_OutputIomuxXbarInout18
Definition: MIMXRT1052.h:967
kXBARA1_OutputLpspi4TrgInput
@ kXBARA1_OutputLpspi4TrgInput
Definition: MIMXRT1052.h:1067
kXBARA1_OutputDmaChMuxReq95
@ kXBARA1_OutputDmaChMuxReq95
Definition: MIMXRT1052.h:952
kXBARA1_OutputQtimer2Tmr1Input
@ kXBARA1_OutputQtimer2Tmr1Input
Definition: MIMXRT1052.h:1040
kXBARA1_OutputFlexpwm3ExtSync1
@ kXBARA1_OutputFlexpwm3ExtSync1
Definition: MIMXRT1052.h:1002
kXBARB2_OutputAoi1In05
@ kXBARB2_OutputAoi1In05
Definition: MIMXRT1052.h:1085
kXBARA1_OutputEnc4Home
@ kXBARA1_OutputEnc4Home
Definition: MIMXRT1052.h:1033
kXBARA1_OutputEnc3PhaseBInput
@ kXBARA1_OutputEnc3PhaseBInput
Definition: MIMXRT1052.h:1026
kXBARA1_OutputDmaChMuxReq94
@ kXBARA1_OutputDmaChMuxReq94
Definition: MIMXRT1052.h:951
kXBARA1_OutputLpuart2TrgInput
@ kXBARA1_OutputLpuart2TrgInput
Definition: MIMXRT1052.h:1069
kXBARA1_OutputFlexpwm1ExtSync3
@ kXBARA1_OutputFlexpwm1ExtSync3
Definition: MIMXRT1052.h:982
kXBARA1_OutputFlexpwm4ExtSync2
@ kXBARA1_OutputFlexpwm4ExtSync2
Definition: MIMXRT1052.h:1010
kXBARA1_OutputFlexpwm234Exta2
@ kXBARA1_OutputFlexpwm234Exta2
Definition: MIMXRT1052.h:991
kXBARA1_OutputLpspi2TrgInput
@ kXBARA1_OutputLpspi2TrgInput
Definition: MIMXRT1052.h:1065
kXBARA1_OutputAcmp3Sample
@ kXBARA1_OutputAcmp3Sample
Definition: MIMXRT1052.h:971
kXBARA1_OutputLpspi3TrgInput
@ kXBARA1_OutputLpspi3TrgInput
Definition: MIMXRT1052.h:1066
kXBARA1_OutputAdcEtcXbar1Trig1
@ kXBARA1_OutputAdcEtcXbar1Trig1
Definition: MIMXRT1052.h:1057
kXBARA1_OutputFlexpwm4ExtForce
@ kXBARA1_OutputFlexpwm4ExtForce
Definition: MIMXRT1052.h:1014
kXBARA1_OutputEnc2Index
@ kXBARA1_OutputEnc2Index
Definition: MIMXRT1052.h:1022
kXBARA1_OutputFlexpwm1Exta1
@ kXBARA1_OutputFlexpwm1Exta1
Definition: MIMXRT1052.h:976
kXBARA1_OutputIomuxXbarInout11
@ kXBARA1_OutputIomuxXbarInout11
Definition: MIMXRT1052.h:960
kXBARA1_OutputAdcEtcXbar0Trig0
@ kXBARA1_OutputAdcEtcXbar0Trig0
Definition: MIMXRT1052.h:1052
kXBARB2_OutputAoi1In02
@ kXBARB2_OutputAoi1In02
Definition: MIMXRT1052.h:1082
kXBARA1_OutputEnc4PhaseAInput
@ kXBARA1_OutputEnc4PhaseAInput
Definition: MIMXRT1052.h:1030
kXBARB2_OutputAoi1In01
@ kXBARB2_OutputAoi1In01
Definition: MIMXRT1052.h:1081
kXBARA1_OutputLpuart1TrgInput
@ kXBARA1_OutputLpuart1TrgInput
Definition: MIMXRT1052.h:1068
kXBARA1_OutputFlexio1TriggerIn0
@ kXBARA1_OutputFlexio1TriggerIn0
Definition: MIMXRT1052.h:1076
kXBARA1_OutputAcmp4Sample
@ kXBARA1_OutputAcmp4Sample
Definition: MIMXRT1052.h:972
kXBARB2_OutputAoi1In11
@ kXBARB2_OutputAoi1In11
Definition: MIMXRT1052.h:1091
kXBARA1_OutputFlexio1TriggerIn1
@ kXBARA1_OutputFlexio1TriggerIn1
Definition: MIMXRT1052.h:1077
kXBARA1_OutputFlexpwm234Exta3
@ kXBARA1_OutputFlexpwm234Exta3
Definition: MIMXRT1052.h:992
ADC_ETC_Type
Definition: MIMXRT1052.h:1683
ADC_Type
Definition: MIMXRT1052.h:1298
AIPSTZ_Type
Definition: MIMXRT1052.h:2800
AOI_Type
Definition: MIMXRT1052.h:3550
BEE_Type
Definition: MIMXRT1052.h:3775
CAN_Type
Definition: MIMXRT1052.h:4122
CCM_ANALOG_Type
Definition: MIMXRT1052.h:7208
CCM_Type
Definition: MIMXRT1052.h:5068
CM7_MCM_Type
Definition: MIMXRT1052.h:10098
CMP_Type
Definition: MIMXRT1052.h:10267
CSI_Type
Definition: MIMXRT1052.h:10538
CSU_Type
Definition: MIMXRT1052.h:11320
DCDC_Type
Definition: MIMXRT1052.h:12013
DCP_Type
Definition: MIMXRT1052.h:12361
DMAMUX_Type
Definition: MIMXRT1052.h:17864
DMA_Type
Definition: MIMXRT1052.h:14358
ENC_Type
Definition: MIMXRT1052.h:17946
ENET_Type
Definition: MIMXRT1052.h:18504
EWM_Type
Definition: MIMXRT1052.h:20382
FLEXIO_Type
Definition: MIMXRT1052.h:20511
FLEXRAM_Type
Definition: MIMXRT1052.h:21139
FLEXSPI_Type
Definition: MIMXRT1052.h:21299
GPC_Type
Definition: MIMXRT1052.h:22336
GPIO_Type
Definition: MIMXRT1052.h:22478
GPT_Type
Definition: MIMXRT1052.h:22971
I2S_Type
Definition: MIMXRT1052.h:23296
IOMUXC_GPR_Type
Definition: MIMXRT1052.h:24400
IOMUXC_SNVS_GPR_Type
Definition: MIMXRT1052.h:27100
IOMUXC_SNVS_Type
Definition: MIMXRT1052.h:26538
IOMUXC_Type
Definition: MIMXRT1052.h:24224
KPP_Type
Definition: MIMXRT1052.h:27207
LCDIF_Type
Definition: MIMXRT1052.h:27360
LPI2C_Type
Definition: MIMXRT1052.h:29282
LPSPI_Type
Definition: MIMXRT1052.h:30457
LPUART_Type
Definition: MIMXRT1052.h:31147
OCOTP_Type
Definition: MIMXRT1052.h:32184
PGC_Type
Definition: MIMXRT1052.h:33149
PIT_Type
Definition: MIMXRT1052.h:33298
PMU_Type
Definition: MIMXRT1052.h:33466
PWM_Type
Definition: MIMXRT1052.h:35990
PXP_Type
Definition: MIMXRT1052.h:37827
ROMC_Type
Definition: MIMXRT1052.h:39386
RTWDOG_Type
Definition: MIMXRT1052.h:39520
SEMC_Type
Definition: MIMXRT1052.h:39738
SNVS_Type
Definition: MIMXRT1052.h:41032
SPDIF_Type
Definition: MIMXRT1052.h:42276
SRC_Type
Definition: MIMXRT1052.h:42848
TEMPMON_Type
Definition: MIMXRT1052.h:43104
TMR_Type
Definition: MIMXRT1052.h:43409
TRNG_Type
Definition: MIMXRT1052.h:43954
TSC_Type
Definition: MIMXRT1052.h:44741
USBNC_Type
Definition: MIMXRT1052.h:46980
USBPHY_Type
Definition: MIMXRT1052.h:47129
USB_ANALOG_Type
Definition: MIMXRT1052.h:48552
USB_Type
Definition: MIMXRT1052.h:45239
USDHC_Type
Definition: MIMXRT1052.h:49060
WDOG_Type
Definition: MIMXRT1052.h:50962
XBARA_Type
Definition: MIMXRT1052.h:51177
XBARB_Type
Definition: MIMXRT1052.h:52224
XTALOSC24M_Type
Definition: MIMXRT1052.h:52375
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