PIT Register Masks

Macros
#define	PIT_LDVAL_COUNT   (4U)
#define	PIT_CVAL_COUNT   (4U)
#define	PIT_TCTRL_COUNT   (4U)
#define	PIT_TFLG_COUNT   (4U)
#define	PIT_LDVAL_COUNT   (4U)
#define	PIT_CVAL_COUNT   (4U)
#define	PIT_TCTRL_COUNT   (4U)
#define	PIT_TFLG_COUNT   (4U)
#define	PIT_LDVAL_COUNT   (4U)
#define	PIT_CVAL_COUNT   (4U)
#define	PIT_TCTRL_COUNT   (4U)
#define	PIT_TFLG_COUNT   (4U)

MCR - PIT Module Control Register
#define	PIT_MCR_FRZ_MASK   (0x1U)
#define	PIT_MCR_FRZ_SHIFT   (0U)
#define	PIT_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
#define	PIT_MCR_MDIS_MASK   (0x2U)
#define	PIT_MCR_MDIS_SHIFT   (1U)
#define	PIT_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)

LTMR64H - PIT Upper Lifetime Timer Register
#define	PIT_LTMR64H_LTH_MASK   (0xFFFFFFFFU)
#define	PIT_LTMR64H_LTH_SHIFT   (0U)
#define	PIT_LTMR64H_LTH(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)

LTMR64L - PIT Lower Lifetime Timer Register
#define	PIT_LTMR64L_LTL_MASK   (0xFFFFFFFFU)
#define	PIT_LTMR64L_LTL_SHIFT   (0U)
#define	PIT_LTMR64L_LTL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)

LDVAL - Timer Load Value Register
#define	PIT_LDVAL_TSV_MASK   (0xFFFFFFFFU)
#define	PIT_LDVAL_TSV_SHIFT   (0U)
#define	PIT_LDVAL_TSV(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)

CVAL - Current Timer Value Register
#define	PIT_CVAL_TVL_MASK   (0xFFFFFFFFU)
#define	PIT_CVAL_TVL_SHIFT   (0U)
#define	PIT_CVAL_TVL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)

TCTRL - Timer Control Register
#define	PIT_TCTRL_TEN_MASK   (0x1U)
#define	PIT_TCTRL_TEN_SHIFT   (0U)
#define	PIT_TCTRL_TEN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
#define	PIT_TCTRL_TIE_MASK   (0x2U)
#define	PIT_TCTRL_TIE_SHIFT   (1U)
#define	PIT_TCTRL_TIE(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
#define	PIT_TCTRL_CHN_MASK   (0x4U)
#define	PIT_TCTRL_CHN_SHIFT   (2U)
#define	PIT_TCTRL_CHN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

TFLG - Timer Flag Register
#define	PIT_TFLG_TIF_MASK   (0x1U)
#define	PIT_TFLG_TIF_SHIFT   (0U)
#define	PIT_TFLG_TIF(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)

MCR - PIT Module Control Register
#define	PIT_MCR_FRZ_MASK   (0x1U)
#define	PIT_MCR_FRZ_SHIFT   (0U)
#define	PIT_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
#define	PIT_MCR_MDIS_MASK   (0x2U)
#define	PIT_MCR_MDIS_SHIFT   (1U)
#define	PIT_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)

LTMR64H - PIT Upper Lifetime Timer Register
#define	PIT_LTMR64H_LTH_MASK   (0xFFFFFFFFU)
#define	PIT_LTMR64H_LTH_SHIFT   (0U)
#define	PIT_LTMR64H_LTH(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)

LTMR64L - PIT Lower Lifetime Timer Register
#define	PIT_LTMR64L_LTL_MASK   (0xFFFFFFFFU)
#define	PIT_LTMR64L_LTL_SHIFT   (0U)
#define	PIT_LTMR64L_LTL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)

LDVAL - Timer Load Value Register
#define	PIT_LDVAL_TSV_MASK   (0xFFFFFFFFU)
#define	PIT_LDVAL_TSV_SHIFT   (0U)
#define	PIT_LDVAL_TSV(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)

CVAL - Current Timer Value Register
#define	PIT_CVAL_TVL_MASK   (0xFFFFFFFFU)
#define	PIT_CVAL_TVL_SHIFT   (0U)
#define	PIT_CVAL_TVL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)

TCTRL - Timer Control Register
#define	PIT_TCTRL_TEN_MASK   (0x1U)
#define	PIT_TCTRL_TEN_SHIFT   (0U)
#define	PIT_TCTRL_TEN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
#define	PIT_TCTRL_TIE_MASK   (0x2U)
#define	PIT_TCTRL_TIE_SHIFT   (1U)
#define	PIT_TCTRL_TIE(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
#define	PIT_TCTRL_CHN_MASK   (0x4U)
#define	PIT_TCTRL_CHN_SHIFT   (2U)
#define	PIT_TCTRL_CHN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

TFLG - Timer Flag Register
#define	PIT_TFLG_TIF_MASK   (0x1U)
#define	PIT_TFLG_TIF_SHIFT   (0U)
#define	PIT_TFLG_TIF(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)

MCR - PIT Module Control Register
#define	PIT_MCR_FRZ_MASK   (0x1U)
#define	PIT_MCR_FRZ_SHIFT   (0U)
#define	PIT_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
#define	PIT_MCR_MDIS_MASK   (0x2U)
#define	PIT_MCR_MDIS_SHIFT   (1U)
#define	PIT_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)

LTMR64H - PIT Upper Lifetime Timer Register
#define	PIT_LTMR64H_LTH_MASK   (0xFFFFFFFFU)
#define	PIT_LTMR64H_LTH_SHIFT   (0U)
#define	PIT_LTMR64H_LTH(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)

LTMR64L - PIT Lower Lifetime Timer Register
#define	PIT_LTMR64L_LTL_MASK   (0xFFFFFFFFU)
#define	PIT_LTMR64L_LTL_SHIFT   (0U)
#define	PIT_LTMR64L_LTL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)

LDVAL - Timer Load Value Register
#define	PIT_LDVAL_TSV_MASK   (0xFFFFFFFFU)
#define	PIT_LDVAL_TSV_SHIFT   (0U)
#define	PIT_LDVAL_TSV(x)   (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)

CVAL - Current Timer Value Register
#define	PIT_CVAL_TVL_MASK   (0xFFFFFFFFU)
#define	PIT_CVAL_TVL_SHIFT   (0U)
#define	PIT_CVAL_TVL(x)   (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)

TCTRL - Timer Control Register
#define	PIT_TCTRL_TEN_MASK   (0x1U)
#define	PIT_TCTRL_TEN_SHIFT   (0U)
#define	PIT_TCTRL_TEN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
#define	PIT_TCTRL_TIE_MASK   (0x2U)
#define	PIT_TCTRL_TIE_SHIFT   (1U)
#define	PIT_TCTRL_TIE(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
#define	PIT_TCTRL_CHN_MASK   (0x4U)
#define	PIT_TCTRL_CHN_SHIFT   (2U)
#define	PIT_TCTRL_CHN(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

TFLG - Timer Flag Register
#define	PIT_TFLG_TIF_MASK   (0x1U)
#define	PIT_TFLG_TIF_SHIFT   (0U)
#define	PIT_TFLG_TIF(x)   (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)

Detailed Description

Macro Definition Documentation

PIT_CVAL_TVL [1/3]

#define PIT_CVAL_TVL

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)

TVL - Current Timer Value

PIT_CVAL_TVL [2/3]

#define PIT_CVAL_TVL

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)

TVL - Current Timer Value

PIT_CVAL_TVL [3/3]

#define PIT_CVAL_TVL

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)

TVL - Current Timer Value

PIT_LDVAL_TSV [1/3]

#define PIT_LDVAL_TSV

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)

TSV - Timer Start Value

PIT_LDVAL_TSV [2/3]

#define PIT_LDVAL_TSV

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)

TSV - Timer Start Value

PIT_LDVAL_TSV [3/3]

#define PIT_LDVAL_TSV

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)

TSV - Timer Start Value

PIT_LTMR64H_LTH [1/3]

#define PIT_LTMR64H_LTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)

LTH - Life Timer value

PIT_LTMR64H_LTH [2/3]

#define PIT_LTMR64H_LTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)

LTH - Life Timer value

PIT_LTMR64H_LTH [3/3]

#define PIT_LTMR64H_LTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)

LTH - Life Timer value

PIT_LTMR64L_LTL [1/3]

#define PIT_LTMR64L_LTL

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)

LTL - Life Timer value

PIT_LTMR64L_LTL [2/3]

#define PIT_LTMR64L_LTL

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)

LTL - Life Timer value

PIT_LTMR64L_LTL [3/3]

#define PIT_LTMR64L_LTL

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)

LTL - Life Timer value

PIT_MCR_FRZ [1/3]

#define PIT_MCR_FRZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Timers continue to run in Debug mode. 0b1..Timers are stopped in Debug mode.

PIT_MCR_FRZ [2/3]

#define PIT_MCR_FRZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Timers continue to run in Debug mode. 0b1..Timers are stopped in Debug mode.

PIT_MCR_FRZ [3/3]

#define PIT_MCR_FRZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Timers continue to run in Debug mode. 0b1..Timers are stopped in Debug mode.

PIT_MCR_MDIS [1/3]

#define PIT_MCR_MDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)

MDIS - Module Disable for PIT 0b0..Clock for standard PIT timers is enabled. 0b1..Clock for standard PIT timers is disabled.

PIT_MCR_MDIS [2/3]

#define PIT_MCR_MDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)

MDIS - Module Disable for PIT 0b0..Clock for standard PIT timers is enabled. 0b1..Clock for standard PIT timers is disabled.

PIT_MCR_MDIS [3/3]

#define PIT_MCR_MDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)

MDIS - Module Disable for PIT 0b0..Clock for standard PIT timers is enabled. 0b1..Clock for standard PIT timers is disabled.

PIT_TCTRL_CHN [1/3]

#define PIT_TCTRL_CHN

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

CHN - Chain Mode 0b0..Timer is not chained. 0b1..Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1.

PIT_TCTRL_CHN [2/3]

#define PIT_TCTRL_CHN

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

CHN - Chain Mode 0b0..Timer is not chained. 0b1..Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1.

PIT_TCTRL_CHN [3/3]

#define PIT_TCTRL_CHN

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

CHN - Chain Mode 0b0..Timer is not chained. 0b1..Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1.

PIT_TCTRL_TEN [1/3]

#define PIT_TCTRL_TEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)

TEN - Timer Enable 0b0..Timer n is disabled. 0b1..Timer n is enabled.

PIT_TCTRL_TEN [2/3]

#define PIT_TCTRL_TEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)

TEN - Timer Enable 0b0..Timer n is disabled. 0b1..Timer n is enabled.

PIT_TCTRL_TEN [3/3]

#define PIT_TCTRL_TEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)

TEN - Timer Enable 0b0..Timer n is disabled. 0b1..Timer n is enabled.

PIT_TCTRL_TIE [1/3]

#define PIT_TCTRL_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt requests from Timer n are disabled. 0b1..Interrupt is requested whenever TIF is set.

PIT_TCTRL_TIE [2/3]

#define PIT_TCTRL_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt requests from Timer n are disabled. 0b1..Interrupt is requested whenever TIF is set.

PIT_TCTRL_TIE [3/3]

#define PIT_TCTRL_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt requests from Timer n are disabled. 0b1..Interrupt is requested whenever TIF is set.

PIT_TFLG_TIF [1/3]

#define PIT_TFLG_TIF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)

TIF - Timer Interrupt Flag 0b0..Timeout has not yet occurred. 0b1..Timeout has occurred.

PIT_TFLG_TIF [2/3]

#define PIT_TFLG_TIF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)

TIF - Timer Interrupt Flag 0b0..Timeout has not yet occurred. 0b1..Timeout has occurred.

PIT_TFLG_TIF [3/3]

#define PIT_TFLG_TIF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)

TIF - Timer Interrupt Flag 0b0..Timeout has not yet occurred. 0b1..Timeout has occurred.