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RTEMS 6.1-rc1
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RTEMS 6.1-rc1
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Modules | |
| Device Peripheral Access Layer | |
| Edma_request | |
| Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). | |
| SDK Compatibility | |
Typedefs | |
| typedef enum _iomuxc_sw_mux_ctl_pad | iomuxc_sw_mux_ctl_pad_t |
| Enumeration for the IOMUXC SW_MUX_CTL_PAD. More... | |
| typedef enum _iomuxc_sw_pad_ctl_pad | iomuxc_sw_pad_ctl_pad_t |
| Enumeration for the IOMUXC SW_PAD_CTL_PAD. More... | |
| typedef enum _iomuxc_select_input | iomuxc_select_input_t |
| Enumeration for the IOMUXC select input. More... | |
| typedef enum _xbar_input_signal | xbar_input_signal_t |
| typedef enum _xbar_output_signal | xbar_output_signal_t |
| typedef enum _iomuxc_sw_mux_ctl_pad | iomuxc_sw_mux_ctl_pad_t |
| Enumeration for the IOMUXC SW_MUX_CTL_PAD. More... | |
| typedef enum _iomuxc_sw_pad_ctl_pad | iomuxc_sw_pad_ctl_pad_t |
| Enumeration for the IOMUXC SW_PAD_CTL_PAD. More... | |
| typedef enum _iomuxc_select_input | iomuxc_select_input_t |
| Enumeration for the IOMUXC select input. More... | |
| typedef enum _iomuxc_sw_mux_ctl_pad | iomuxc_sw_mux_ctl_pad_t |
| Enumeration for the IOMUXC SW_MUX_CTL_PAD. More... | |
| typedef enum _iomuxc_sw_pad_ctl_pad | iomuxc_sw_pad_ctl_pad_t |
| Enumeration for the IOMUXC SW_PAD_CTL_PAD. More... | |
| typedef enum _iomuxc_select_input | iomuxc_select_input_t |
| Enumeration for the IOMUXC select input. More... | |
Mapping Information
| typedef enum _iomuxc_select_input iomuxc_select_input_t |
Enumeration for the IOMUXC select input.
Defines the enumeration for the IOMUXC select input collections.
| typedef enum _iomuxc_select_input iomuxc_select_input_t |
Enumeration for the IOMUXC select input.
Defines the enumeration for the IOMUXC select input collections.
| typedef enum _iomuxc_select_input iomuxc_select_input_t |
Enumeration for the IOMUXC select input.
Defines the enumeration for the IOMUXC select input collections.
| typedef enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t |
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
| typedef enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t |
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
| typedef enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t |
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
| typedef enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t |
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
| typedef enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t |
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
| typedef enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t |
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
| enum _iomuxc_select_input |
Enumeration for the IOMUXC select input.
Defines the enumeration for the IOMUXC select input collections.
| enum _iomuxc_select_input |
Enumeration for the IOMUXC select input.
Defines the enumeration for the IOMUXC select input collections.
| enum _iomuxc_select_input |
Enumeration for the IOMUXC select input.
Defines the enumeration for the IOMUXC select input collections.
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
Enumeration for the IOMUXC SW_MUX_CTL_PAD.
Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
Enumeration for the IOMUXC SW_PAD_CTL_PAD.
Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
| enum _xbar_input_signal |
| enum _xbar_output_signal |
| __O uint32_t CDOG_Type::ADD |
ADD Command, offset: 0x2C
| __O uint32_t CDOG_Type::ADD1 |
ADD1 Command, offset: 0x30
| __O uint32_t CDOG_Type::ADD16 |
ADD16 Command, offset: 0x34
| __O uint32_t CDOG_Type::ADD256 |
ADD256 Command, offset: 0x38
| __IO uint32_t BEE_Type::ADDR_OFFSET0 |
Offset region 0 Register, offset: 0x4
| __IO uint32_t BEE_Type::ADDR_OFFSET1 |
Offset region 1 Register, offset: 0x8
| __I uint32_t USDHC_Type::ADMA_ERR_STATUS |
ADMA Error Status, offset: 0x54
| __IO uint32_t USDHC_Type::ADMA_SYS_ADDR |
ADMA System Address, offset: 0x58
| __IO uint32_t BEE_Type::AES_KEY0_W0 |
AES Key 0 Register, offset: 0xC
| __IO uint32_t BEE_Type::AES_KEY0_W1 |
AES Key 1 Register, offset: 0x10
| __IO uint32_t BEE_Type::AES_KEY0_W2 |
AES Key 2 Register, offset: 0x14
| __IO uint32_t BEE_Type::AES_KEY0_W3 |
AES Key 3 Register, offset: 0x18
| __IO uint32_t IEE_Type::AES_TST_DB |
IEE AES Test Mode Data Buffer, array offset: 0xF00, array step: 0x4
| __I uint32_t IEE_Type::AESVID |
IEE AES Version ID Register, offset: 0xF8
| __IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND0 |
RX BUF region End address of region 0, offset: 0x444
| __IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND1 |
RX BUF region End address of region 1, offset: 0x44C
| __IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND2 |
RX BUF region End address of region 2, offset: 0x454
| __IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND3 |
RX BUF region End address of region 3, offset: 0x45C
| __IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART0 |
RX BUF Start address of region 0, offset: 0x440
| __IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART1 |
RX BUF Start address of region 1, offset: 0x448
| __IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART2 |
RX BUF Start address of region 2, offset: 0x450
| __IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART3 |
RX BUF Start address of region 3, offset: 0x458
| __IO uint32_t FLEXSPI_Type::AHBCR |
AHB Bus Control Register, offset: 0xC
| __IO uint32_t FLEXSPI_Type::AHBRXBUFCR0 |
AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4
AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4
| __I uint32_t FLEXSPI_Type::AHBSPNDSTS |
AHB Suspend Status Register, offset: 0xEC
| __I uint32_t PUF_Type::ALLOW |
PUF Allow Register, offset: 0x28
| __IO uint32_t OCOTP_Type::ANA0 |
Value of OTP Bank 1 Word 5 (Analog Info.), offset: 0x4D0
| __IO uint32_t OCOTP_Type::ANA1 |
Value of OTP Bank 1 Word 6 (Analog Info.), offset: 0x4E0
| __IO uint32_t OCOTP_Type::ANA2 |
Value of OTP Bank 1 Word 7 (Analog Info.), offset: 0x4F0
| __IO uint32_t USBPHY_Type::ANACTRL |
USB PHY Analog Control Register, offset: 0x100
| __IO uint32_t USBPHY_Type::ANACTRL_CLR |
USB PHY Analog Control Register, offset: 0x108
| __IO uint32_t USBPHY_Type::ANACTRL_SET |
USB PHY Analog Control Register, offset: 0x104
| __IO uint32_t USBPHY_Type::ANACTRL_TOG |
USB PHY Analog Control Register, offset: 0x10C
| __IO uint32_t ANADIG_PLL_Type::ARM_PLL_CTRL |
ARM_PLL_CTRL_REGISTER, offset: 0x200
| __IO uint32_t PXP_Type::AS_BUF |
Alpha Surface Buffer Pointer, offset: 0x160
| __IO uint32_t PXP_Type::AS_CLRKEYHIGH |
Overlay Color Key High, offset: 0x190
| __IO uint32_t PXP_Type::AS_CLRKEYLOW |
Overlay Color Key Low, offset: 0x180
| __IO uint32_t PXP_Type::AS_CTRL |
Alpha Surface Control, offset: 0x150
| __IO uint32_t PXP_Type::AS_PITCH |
Alpha Surface Pitch, offset: 0x170
| __IO uint32_t ASRC_Type::ASR56K |
ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C
| __IO uint32_t ASRC_Type::ASR76K |
ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98
| __IO uint32_t ASRC_Type::ASRCCR |
ASRC Channel Counter Register, offset: 0x5C
| __IO uint32_t ASRC_Type::ASRCDR1 |
ASRC Clock Divider Register 1, offset: 0x18
| __IO uint32_t ASRC_Type::ASRCDR2 |
ASRC Clock Divider Register 2, offset: 0x1C
| __IO uint32_t ASRC_Type::ASRCFG |
ASRC Filter Configuration Status Register, offset: 0x10
| __IO uint32_t ASRC_Type::ASRCNCR |
ASRC Channel Number Configuration Register, offset: 0xC
| __IO uint32_t ASRC_Type::ASRCSR |
ASRC Clock Source Register, offset: 0x14
| __IO uint32_t ASRC_Type::ASRCTR |
ASRC Control Register, offset: 0x0
| __O uint32_t ASRC_Type::ASRDIA |
ASRC Data Input Register for Pair x, offset: 0x60
| __O uint32_t ASRC_Type::ASRDIB |
ASRC Data Input Register for Pair x, offset: 0x68
| __O uint32_t ASRC_Type::ASRDIC |
ASRC Data Input Register for Pair x, offset: 0x70
| __I uint32_t ASRC_Type::ASRDOA |
ASRC Data Output Register for Pair x, offset: 0x64
| __I uint32_t ASRC_Type::ASRDOB |
ASRC Data Output Register for Pair x, offset: 0x6C
| __I uint32_t ASRC_Type::ASRDOC |
ASRC Data Output Register for Pair x, offset: 0x74
| __I uint32_t ASRC_Type::ASRFSTA |
ASRC FIFO Status Register for Pair A, offset: 0xA4
| __I uint32_t ASRC_Type::ASRFSTB |
ASRC FIFO Status Register for Pair B, offset: 0xAC
| __I uint32_t ASRC_Type::ASRFSTC |
ASRC FIFO Status Register for Pair C, offset: 0xB4
| __IO uint32_t ASRC_Type::ASRIDRHA |
ASRC Ideal Ratio for Pair A-High Part, offset: 0x80
| __IO uint32_t ASRC_Type::ASRIDRHB |
ASRC Ideal Ratio for Pair B-High Part, offset: 0x88
| __IO uint32_t ASRC_Type::ASRIDRHC |
ASRC Ideal Ratio for Pair C-High Part, offset: 0x90
| __IO uint32_t ASRC_Type::ASRIDRLA |
ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84
| __IO uint32_t ASRC_Type::ASRIDRLB |
ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C
| __IO uint32_t ASRC_Type::ASRIDRLC |
ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94
| __IO uint32_t ASRC_Type::ASRIER |
ASRC Interrupt Enable Register, offset: 0x4
| __IO uint32_t ASRC_Type::ASRMCR1 |
ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4
| __IO uint32_t ASRC_Type::ASRMCRA |
ASRC Misc Control Register for Pair A, offset: 0xA0
| __IO uint32_t ASRC_Type::ASRMCRB |
ASRC Misc Control Register for Pair B, offset: 0xA8
| __IO uint32_t ASRC_Type::ASRMCRC |
ASRC Misc Control Register for Pair C, offset: 0xB0
| __IO uint32_t ASRC_Type::ASRPM |
ASRC Parameter Register n, array offset: 0x40, array step: 0x4
| __I uint32_t ASRC_Type::ASRSTR |
ASRC Status Register, offset: 0x20
| __IO uint32_t ASRC_Type::ASRTFR1 |
ASRC Task Queue FIFO Register 1, offset: 0x54
| __IO uint32_t USB_Type::ASYNCLISTADDR |
Next Asynch. Address, offset: 0x158
| __IO uint32_t { ... } ::ASYNCLISTADDR |
Next Asynch. Address, offset: 0x158
| __IO uint32_t { ... } ::ASYNCLISTADDR |
Next Asynch. Address, offset: 0x158
| __IO uint32_t { ... } ::ASYNCLISTADDR |
Next Asynch. Address, offset: 0x158
| __IO uint32_t ENET_Type::ATCOR |
Timer Correction Register, offset: 0x410
| __IO uint32_t ENET_Type::ATCR |
Adjustable Timer Control Register, offset: 0x400
| __IO uint32_t ENET_Type::ATINC |
Time-Stamping Clock Period Register, offset: 0x414
| __IO uint32_t ENET_Type::ATOFF |
Timer Offset Register, offset: 0x408
| __IO uint32_t ENET_Type::ATPER |
Timer Period Register, offset: 0x40C
| __I uint32_t ENET_Type::ATSTMP |
Timestamp of Last Transmitted Frame, offset: 0x418
| __IO uint16_t DMA_Type::ATTR |
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
| __IO uint16_t { ... } ::ATTR |
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
| __IO uint16_t { ... } ::ATTR |
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
| __IO uint16_t { ... } ::ATTR |
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
| __IO uint32_t ENET_Type::ATVR |
Timer Value Register, offset: 0x404
| __IO uint32_t { ... } ::AUTHEN |
Clock root access control, array offset: 0x30, array step: 0x80
| __IO uint32_t CCM_Type::AUTHEN |
Clock root access control, array offset: 0x30, array step: 0x80
Clock group access control, array offset: 0x4030, array step: 0x80
GPR access control, array offset: 0x4810, array step: 0x20
Clock source access control, array offset: 0x501C, array step: 0x20
LPCG access control, array offset: 0x601C, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN |
Clock group access control, array offset: 0x4030, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN |
GPR access control, array offset: 0x4810, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN |
Clock source access control, array offset: 0x501C, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN |
LPCG access control, array offset: 0x601C, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN |
Observe access control, array offset: 0x30, array step: 0x80
| __IO uint32_t CCM_OBS_Type::AUTHEN |
Observe access control, array offset: 0x30, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN |
Clock root access control, array offset: 0x30, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN |
Clock group access control, array offset: 0x4030, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN |
GPR access control, array offset: 0x4810, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN |
Clock source access control, array offset: 0x501C, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN |
LPCG access control, array offset: 0x601C, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN |
Observe access control, array offset: 0x30, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_CLR |
Clock root access control, array offset: 0x38, array step: 0x80
| __IO uint32_t CCM_Type::AUTHEN_CLR |
Clock root access control, array offset: 0x38, array step: 0x80
Clock group access control, array offset: 0x4038, array step: 0x80
GPR access control, array offset: 0x4818, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN_CLR |
Clock group access control, array offset: 0x4038, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_CLR |
GPR access control, array offset: 0x4818, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN_CLR |
Observe access control, array offset: 0x38, array step: 0x80
| __IO uint32_t CCM_OBS_Type::AUTHEN_CLR |
Observe access control, array offset: 0x38, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_CLR |
Clock root access control, array offset: 0x38, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_CLR |
Clock group access control, array offset: 0x4038, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_CLR |
GPR access control, array offset: 0x4818, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN_CLR |
Observe access control, array offset: 0x38, array step: 0x80
| __IO uint32_t SRC_Type::AUTHEN_DISPLAY |
Slice Authentication Register, offset: 0x220
| __IO uint32_t SRC_Type::AUTHEN_M4CORE |
Slice Authentication Register, offset: 0x280
| __IO uint32_t SRC_Type::AUTHEN_M4DEBUG |
Slice Authentication Register, offset: 0x2C0
| __IO uint32_t SRC_Type::AUTHEN_M7CORE |
Slice Authentication Register, offset: 0x2A0
| __IO uint32_t SRC_Type::AUTHEN_M7DEBUG |
Slice Authentication Register, offset: 0x2E0
| __IO uint32_t SRC_Type::AUTHEN_MEGA |
Slice Authentication Register, offset: 0x200
| __IO uint32_t CCM_Type::AUTHEN_SET |
Clock root access control, array offset: 0x34, array step: 0x80
Clock group access control, array offset: 0x4034, array step: 0x80
GPR access control, array offset: 0x4814, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN_SET |
Clock root access control, array offset: 0x34, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_SET |
Clock group access control, array offset: 0x4034, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_SET |
GPR access control, array offset: 0x4814, array step: 0x20
| __IO uint32_t CCM_OBS_Type::AUTHEN_SET |
Observe access control, array offset: 0x34, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_SET |
Observe access control, array offset: 0x34, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_SET |
Clock root access control, array offset: 0x34, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_SET |
Clock group access control, array offset: 0x4034, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_SET |
GPR access control, array offset: 0x4814, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN_SET |
Observe access control, array offset: 0x34, array step: 0x80
| __IO uint32_t CCM_Type::AUTHEN_TOG |
Clock root access control, array offset: 0x3C, array step: 0x80
Clock group access control, array offset: 0x403C, array step: 0x80
GPR access control, array offset: 0x481C, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN_TOG |
Clock root access control, array offset: 0x3C, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_TOG |
Clock group access control, array offset: 0x403C, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_TOG |
GPR access control, array offset: 0x481C, array step: 0x20
| __IO uint32_t CCM_OBS_Type::AUTHEN_TOG |
Observe access control, array offset: 0x3C, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_TOG |
Observe access control, array offset: 0x3C, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_TOG |
Clock root access control, array offset: 0x3C, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_TOG |
Clock group access control, array offset: 0x403C, array step: 0x80
| __IO uint32_t { ... } ::AUTHEN_TOG |
GPR access control, array offset: 0x481C, array step: 0x20
| __IO uint32_t { ... } ::AUTHEN_TOG |
Observe access control, array offset: 0x3C, array step: 0x80
| __IO uint32_t SRC_Type::AUTHEN_USBPHY1 |
Slice Authentication Register, offset: 0x300
| __IO uint32_t SRC_Type::AUTHEN_USBPHY2 |
Slice Authentication Register, offset: 0x320
| __IO uint32_t SRC_Type::AUTHEN_WAKEUP |
Slice Authentication Register, offset: 0x240
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::AUTO_PD_EN |
AUTO_PD_EN, offset: 0x3C
| __IO uint32_t USDHC_Type::AUTOCMD12_ERR_STATUS |
Auto CMD12 Error Status, offset: 0x3C
| __IO uint32_t ANADIG_PMU_Type::BANDGAP_ENABLE_SP |
BANDGAP_ENABLE_SP_REGISTER, offset: 0x6F0
| __IO uint32_t ANADIG_PMU_Type::BANDGAP_STBY_EN_SP |
BANDGAP_STBY_EN_SP_REGISTER, offset: 0x730
| __IO uint32_t TSC_Type::BASIC_SETTING |
Basic Setting, offset: 0x0
| __IO uint32_t LPUART_Type::BAUD |
LPUART Baud Rate Register, offset: 0x10
| __IO uint16_t AOI_Type::BFCRT01 |
Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4
| __IO uint16_t { ... } ::BFCRT01 |
Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4
| __IO uint16_t { ... } ::BFCRT01 |
Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4
| __IO uint16_t { ... } ::BFCRT01 |
Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4
| __IO uint16_t AOI_Type::BFCRT23 |
Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4
| __IO uint16_t { ... } ::BFCRT23 |
Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4
| __IO uint16_t { ... } ::BFCRT23 |
Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4
| __IO uint16_t { ... } ::BFCRT23 |
Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4
| __IO uint32_t EMVSIM_Type::BGT_VAL |
Block Guard Time Value Register, offset: 0x40
| __I uint32_t MIPI_CSI2RX_Type::BIT_ERR |
ECC and CRC Error Status Register, offset: 0x108
| __IO uint32_t OCOTP_Type::BIT_LOCK |
BIT_LOCK Register, offset: 0x150
| __IO uint16_t { ... } ::BITER_ELINKNO |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t DMA_Type::BITER_ELINKNO |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKNO |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKNO |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKYES |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t DMA_Type::BITER_ELINKYES |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKYES |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKYES |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20
| __IO uint32_t USDHC_Type::BLK_ATT |
Block Attributes, offset: 0x4
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::BLLP_MODE |
BLLP_MODE, offset: 0x34
| __IO uint32_t LCDIF_Type::BM_ERROR_STAT |
Bus Master Error Status Register, offset: 0x190
| __IO uint32_t SEMC_Type::BMCR0 |
Bus (AXI) Master Control Register 0, offset: 0x8
| __IO uint32_t SEMC_Type::BMCR1 |
Bus (AXI) Master Control Register 1, offset: 0xC
| __IO uint32_t PGMC_BPC_Type::BPC_AUTHEN_CTRL |
BPC Authentication Control, offset: 0x4
| __IO uint32_t PGMC_BPC_Type::BPC_FLAG |
BPC flag, offset: 0x2C
| __IO uint32_t PGMC_BPC_Type::BPC_MODE |
BPC Mode, offset: 0x10
| __IO uint32_t PGMC_BPC_Type::BPC_POWER_CTRL |
BPC power control, offset: 0x14
| __IO uint32_t PGMC_BPC_Type::BPC_SSAR_RESTORE_CTRL |
BPC SSAR restore control, offset: 0x44
| __IO uint32_t PGMC_BPC_Type::BPC_SSAR_SAVE_CTRL |
BPC SSAR save control, offset: 0x40
| __IO uint32_t SEMC_Type::BR |
Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4
Base Register 0..Base Register 8, array offset: 0x10, array step: 0x4
| __IO uint32_t SEMC_Type::BR10 |
Base Register 10, offset: 0x104
| __IO uint32_t SEMC_Type::BR11 |
Base Register 11, offset: 0x108
| __IO uint32_t SEMC_Type::BR9 |
Base Register 9, offset: 0x100
| __IO uint32_t USB_Type::BURSTSIZE |
Programmable Burst Size, offset: 0x160
| __IO uint32_t EMVSIM_Type::BWT_VAL |
Block Wait Time Value Register, offset: 0x3C
| __IO uint32_t CMP_Type::C0 |
CMP Control Register 0, offset: 0x8
| __IO uint32_t CMP_Type::C1 |
CMP Control Register 1, offset: 0xC
| __IO uint32_t CMP_Type::C2 |
CMP Control Register 2, offset: 0x10
| __IO uint32_t CMP_Type::C3 |
CMP Control Register 3, offset: 0x14
| __IO uint32_t MMCAU_Type::CA[9] |
General Purpose Register, array offset: 0x8, array step: 0x4
| __IO uint32_t MMCAU_Type::CAA |
Accumulator, offset: 0x4
| __I uint32_t CAAM_Type::CAAMVID_LS |
CAAM Version ID Register, least-significant half, offset: 0xFFC
| __I uint32_t CAAM_Type::CAAMVID_LS_DC01 |
CAAM Version ID Register, least-significant half, offset: 0x80FFC
| __I uint32_t CAAM_Type::CAAMVID_LS_JR |
CAAM Version ID Register, least-significant half, array offset: 0x10FFC, array step: 0x10000
| __I uint32_t { ... } ::CAAMVID_LS_JR |
CAAM Version ID Register, least-significant half, array offset: 0x10FFC, array step: 0x10000
| __I uint32_t { ... } ::CAAMVID_LS_JR |
CAAM Version ID Register, least-significant half, array offset: 0x10FFC, array step: 0x10000
| __I uint32_t CAAM_Type::CAAMVID_LS_RTIC |
CAAM Version ID Register, least-significant half, offset: 0x60FFC
| __I uint32_t CAAM_Type::CAAMVID_LS_TRAD |
CAAM Version ID Register, least-significant half, offset: 0xBFC
| __I uint32_t CAAM_Type::CAAMVID_MS |
CAAM Version ID Register, most-significant half, offset: 0xFF8
| __I uint32_t CAAM_Type::CAAMVID_MS_DC01 |
CAAM Version ID Register, most-significant half, offset: 0x80FF8
| __I uint32_t CAAM_Type::CAAMVID_MS_JR |
CAAM Version ID Register, most-significant half, array offset: 0x10FF8, array step: 0x10000
| __I uint32_t { ... } ::CAAMVID_MS_JR |
CAAM Version ID Register, most-significant half, array offset: 0x10FF8, array step: 0x10000
| __I uint32_t { ... } ::CAAMVID_MS_JR |
CAAM Version ID Register, most-significant half, array offset: 0x10FF8, array step: 0x10000
| __I uint32_t CAAM_Type::CAAMVID_MS_RTIC |
CAAM Version ID Register, most-significant half, offset: 0x60FF8
| __I uint32_t CAAM_Type::CAAMVID_MS_TRAD |
CAAM Version ID Register, most-significant half, offset: 0xBF8
| __IO uint32_t CCM_Type::CACRR |
CCM Arm Clock Root Register, offset: 0x10
| __IO uint32_t ADC_Type::CAL |
Calibration value register, offset: 0x58
| __IO uint32_t DCP_Type::CAPABILITY0 |
DCP capability 0 register, offset: 0x30
| __I uint32_t DCP_Type::CAPABILITY1 |
DCP capability 1 register, offset: 0x40
| __I uint8_t USB_Type::CAPLENGTH |
Capability Registers Length, offset: 0x100
| __IO uint16_t TMR_Type::CAPT |
Timer Channel Capture Register, array offset: 0x4, array step: 0x20
| __IO uint16_t { ... } ::CAPT |
Timer Channel Capture Register, array offset: 0x4, array step: 0x20
| __IO uint16_t { ... } ::CAPT |
Timer Channel Capture Register, array offset: 0x4, array step: 0x20
| __IO uint16_t { ... } ::CAPT |
Timer Channel Capture Register, array offset: 0x4, array step: 0x20
| __IO uint16_t { ... } ::CAPTCOMPA |
Capture Compare A Register, array offset: 0x36, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCOMPA |
Capture Compare A Register, array offset: 0x36, array step: 0x60
| __IO uint16_t { ... } ::CAPTCOMPA |
Capture Compare A Register, array offset: 0x36, array step: 0x60
| __IO uint16_t { ... } ::CAPTCOMPA |
Capture Compare A Register, array offset: 0x36, array step: 0x60
| __IO uint16_t { ... } ::CAPTCOMPB |
Capture Compare B Register, array offset: 0x3A, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCOMPB |
Capture Compare B Register, array offset: 0x3A, array step: 0x60
| __IO uint16_t { ... } ::CAPTCOMPB |
Capture Compare B Register, array offset: 0x3A, array step: 0x60
| __IO uint16_t { ... } ::CAPTCOMPB |
Capture Compare B Register, array offset: 0x3A, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCOMPX |
Capture Compare X Register, array offset: 0x3E, array step: 0x60
| __IO uint16_t { ... } ::CAPTCOMPX |
Capture Compare X Register, array offset: 0x3E, array step: 0x60
| __IO uint16_t { ... } ::CAPTCOMPX |
Capture Compare X Register, array offset: 0x3E, array step: 0x60
| __IO uint16_t { ... } ::CAPTCOMPX |
Capture Compare X Register, array offset: 0x3E, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCTRLA |
Capture Control A Register, array offset: 0x34, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLA |
Capture Control A Register, array offset: 0x34, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLA |
Capture Control A Register, array offset: 0x34, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLA |
Capture Control A Register, array offset: 0x34, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLB |
Capture Control B Register, array offset: 0x38, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCTRLB |
Capture Control B Register, array offset: 0x38, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLB |
Capture Control B Register, array offset: 0x38, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLB |
Capture Control B Register, array offset: 0x38, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCTRLX |
Capture Control X Register, array offset: 0x3C, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLX |
Capture Control X Register, array offset: 0x3C, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLX |
Capture Control X Register, array offset: 0x3C, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLX |
Capture Control X Register, array offset: 0x3C, array step: 0x60
| __IO uint32_t MMCAU_Type::CASR |
Status Register, offset: 0x0
| __IO uint32_t CCM_Type::CBCDR |
CCM Bus Clock Divider Register, offset: 0x14
| __IO uint32_t CCM_Type::CBCMR |
CCM Bus Clock Multiplexer Register, offset: 0x18
| __IO uint32_t CAN_Type::CBT |
CAN Bit Timing register, offset: 0x50
| __IO uint32_t CAAM_Type::CC1AADSZR |
CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C
| __IO uint32_t { ... } ::CC1AADSZR |
CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C
| __IO uint32_t { ... } ::CC1AADSZR |
CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C
| __IO uint32_t CAAM_Type::CC1CTXR[16] |
CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4
| __IO uint32_t { ... } ::CC1CTXR[16] |
CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4
| __IO uint32_t { ... } ::CC1CTXR[16] |
CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4
| __IO uint64_t { ... } ::CC1DSR |
CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C
| __IO uint64_t CAAM_Type::CC1DSR |
CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C
| __IO uint64_t { ... } ::CC1DSR |
CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C
| __IO uint32_t { ... } ::CC1ICVSR |
CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C
| __IO uint32_t CAAM_Type::CC1ICVSR |
CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C
| __IO uint32_t { ... } ::CC1ICVSR |
CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C
| __IO uint32_t CAAM_Type::CC1IVSZR |
CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C
| __IO uint32_t { ... } ::CC1IVSZR |
CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C
| __IO uint32_t { ... } ::CC1IVSZR |
CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C
| __IO uint32_t { ... } ::CC1KR[8] |
CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4
| __IO uint32_t CAAM_Type::CC1KR[8] |
CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4
| __IO uint32_t { ... } ::CC1KR[8] |
CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4
| __IO uint32_t CAAM_Type::CC1KSR |
CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C
| __IO uint32_t { ... } ::CC1KSR |
CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C
| __IO uint32_t { ... } ::CC1KSR |
CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C
| __IO uint32_t { ... } ::CC1MR |
CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms, array offset: 0x80004, array step: 0xE3C
| __IO uint32_t CAAM_Type::CC1MR |
CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms, array offset: 0x80004, array step: 0xE3C
| __IO uint32_t { ... } ::CC1MR |
CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms, array offset: 0x80004, array step: 0xE3C
| __IO uint32_t { ... } ::CC1MR_PK |
CCB 0 Class 1 Mode Register Format for Public Key Algorithms, array offset: 0x80004, array step: 0xE3C
| __IO uint32_t CAAM_Type::CC1MR_PK |
CCB 0 Class 1 Mode Register Format for Public Key Algorithms, array offset: 0x80004, array step: 0xE3C
| __IO uint32_t { ... } ::CC1MR_PK |
CCB 0 Class 1 Mode Register Format for Public Key Algorithms, array offset: 0x80004, array step: 0xE3C
| __IO uint32_t { ... } ::CC1MR_RNG |
CCB 0 Class 1 Mode Register Format for RNG4, array offset: 0x80004, array step: 0xE3C
| __IO uint32_t CAAM_Type::CC1MR_RNG |
CCB 0 Class 1 Mode Register Format for RNG4, array offset: 0x80004, array step: 0xE3C
| __IO uint32_t { ... } ::CC1MR_RNG |
CCB 0 Class 1 Mode Register Format for RNG4, array offset: 0x80004, array step: 0xE3C
| __IO uint32_t CAAM_Type::CC2CTXR[18] |
CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4
| __IO uint32_t { ... } ::CC2CTXR[18] |
CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4
| __IO uint32_t { ... } ::CC2CTXR[18] |
CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4
| __IO uint64_t CAAM_Type::CC2DSR |
CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C
| __IO uint64_t { ... } ::CC2DSR |
CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C
| __IO uint64_t { ... } ::CC2DSR |
CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C
| __IO uint32_t CAAM_Type::CC2ICVSZR |
CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C
| __IO uint32_t { ... } ::CC2ICVSZR |
CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C
| __IO uint32_t { ... } ::CC2ICVSZR |
CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C
| __IO uint32_t CAAM_Type::CC2KEYR[32] |
CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4
| __IO uint32_t { ... } ::CC2KEYR[32] |
CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4
| __IO uint32_t { ... } ::CC2KEYR[32] |
CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4
| __IO uint32_t { ... } ::CC2KSR |
CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C
| __IO uint32_t CAAM_Type::CC2KSR |
CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C
| __IO uint32_t { ... } ::CC2KSR |
CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C
| __IO uint32_t { ... } ::CC2MR |
CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C
| __IO uint32_t CAAM_Type::CC2MR |
CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C
| __IO uint32_t { ... } ::CC2MR |
CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C
| __I uint32_t CAAM_Type::CCBVID |
CHA Cluster Block Version ID Register, offset: 0xFE4
| __I uint32_t CAAM_Type::CCBVID_DC01 |
CHA Cluster Block Version ID Register, offset: 0x80FE4
| __I uint32_t CAAM_Type::CCBVID_JR |
CHA Cluster Block Version ID Register, array offset: 0x10FE4, array step: 0x10000
| __I uint32_t { ... } ::CCBVID_JR |
CHA Cluster Block Version ID Register, array offset: 0x10FE4, array step: 0x10000
| __I uint32_t { ... } ::CCBVID_JR |
CHA Cluster Block Version ID Register, array offset: 0x10FE4, array step: 0x10000
| __I uint32_t CAAM_Type::CCBVID_RTIC |
CHA Cluster Block Version ID Register, offset: 0x60FE4
| __O uint32_t { ... } ::CCCTRL |
CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C
| __O uint32_t CAAM_Type::CCCTRL |
CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C
| __O uint32_t { ... } ::CCCTRL |
CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C
| __IO uint32_t CCM_Type::CCGR0 |
CCM Clock Gating Register 0, offset: 0x68
| __IO uint32_t CCM_Type::CCGR1 |
CCM Clock Gating Register 1, offset: 0x6C
| __IO uint32_t CCM_Type::CCGR2 |
CCM Clock Gating Register 2, offset: 0x70
| __IO uint32_t CCM_Type::CCGR3 |
CCM Clock Gating Register 3, offset: 0x74
| __IO uint32_t CCM_Type::CCGR4 |
CCM Clock Gating Register 4, offset: 0x78
| __IO uint32_t CCM_Type::CCGR5 |
CCM Clock Gating Register 5, offset: 0x7C
| __IO uint32_t CCM_Type::CCGR6 |
CCM Clock Gating Register 6, offset: 0x80
| __IO uint32_t CCM_Type::CCOSR |
CCM Clock Output Source Register, offset: 0x60
| __IO uint32_t CCM_Type::CCR |
CCM Control Register, offset: 0x0
| __IO uint32_t LPSPI_Type::CCR |
Clock Configuration Register, offset: 0x40
Clock Configuration, offset: 0x40
| __IO uint32_t CCM_Type::CCSR |
CCM Clock Switcher Register, offset: 0xC
| __I uint32_t { ... } ::CCSTA_LS |
CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C
| __I uint32_t CAAM_Type::CCSTA_LS |
CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C
| __I uint32_t { ... } ::CCSTA_LS |
CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C
| __I uint32_t { ... } ::CCSTA_MS |
CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C
| __I uint32_t CAAM_Type::CCSTA_MS |
CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C
| __I uint32_t { ... } ::CCSTA_MS |
CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C
| __O uint32_t { ... } ::CCWR |
CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C
| __O uint32_t CAAM_Type::CCWR |
CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C
| __O uint32_t { ... } ::CCWR |
CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C
| __IO uint32_t CCM_Type::CDCDR |
CCM D1 Clock Divider Register, offset: 0x30
| __I uint32_t CCM_Type::CDHIPR |
CCM Divider Handshake In-Process Register, offset: 0x48
| __O uint8_t DMA_Type::CDNE |
Clear DONE Status Bit, offset: 0x1C
| __O uint8_t DMA_Type::CEEI |
Clear Enable Error Interrupt, offset: 0x18
| __O uint8_t DMA_Type::CERQ |
Clear Enable Request, offset: 0x1A
| __O uint8_t DMA_Type::CERR |
Clear Error, offset: 0x1E
| __IO uint32_t ADC_Type::CFG |
Configuration register, offset: 0x44
LPADC Configuration Register, offset: 0x20
| __IO uint32_t PUF_Type::CFG |
PUF Configuration Register, offset: 0x10C
| __IO uint32_t OCOTP_Type::CFG0 |
Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410
| __IO uint32_t OCOTP_Type::CFG1 |
Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420
| __IO uint32_t OCOTP_Type::CFG2 |
Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430
| __IO uint32_t OCOTP_Type::CFG3 |
Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440
| __IO uint32_t OCOTP_Type::CFG4 |
Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450
| __IO uint32_t OCOTP_Type::CFG5 |
Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460
| __IO uint32_t OCOTP_Type::CFG6 |
Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470
| __IO uint32_t DSI_HOST_Type::CFG_AUTOINSERT_EOTP |
CFG_AUTOINSERT_ETOP, offset: 0x14
| __IO uint32_t DSI_HOST_Type::CFG_BTA_H_TO_COUNT |
CFG_BTA_H_TO_COUNT, offset: 0x24
| __IO uint32_t MIPI_CSI2RX_Type::CFG_DISABLE_DATA_LANES |
Disable Data Lane Register, offset: 0x104
| __IO uint32_t MIPI_CSI2RX_Type::CFG_DISABLE_PAYLOAD_0 |
Disable Payload 0 Register, offset: 0x12C
| __IO uint32_t MIPI_CSI2RX_Type::CFG_DISABLE_PAYLOAD_1 |
Disable Payload 1 Register, offset: 0x130
| __IO uint32_t DSI_HOST_Type::CFG_EXTRA_CMDS_AFTER_EOTP |
CFG_EXTRA_CMDS_AFTER_ETOP, offset: 0x18
| __IO uint32_t DSI_HOST_Type::CFG_HTX_TO_COUNT |
CFG_HTX_TO_COUNT, offset: 0x1C
| __IO uint32_t MIPI_CSI2RX_Type::CFG_IGNORE_VC |
Ignore Virtual Channel Register, offset: 0x180
| __IO uint32_t DSI_HOST_Type::CFG_LRX_H_TO_COUNT |
CFG_LRX_H_TO_COUNT, offset: 0x20
| __IO uint32_t DSI_HOST_Type::CFG_NONCONTINUOUS_CLK |
CFG_NONCONTINUOUS_CLK, offset: 0x4
| __IO uint32_t DSI_HOST_Type::CFG_NUM_LANES |
CFG_NUM_LANES, offset: 0x0
| __IO uint32_t MIPI_CSI2RX_Type::CFG_NUM_LANES |
Lane Configuration Register, offset: 0x100
| __I uint32_t DSI_HOST_Type::CFG_STATUS_OUT |
CFG_STATUS_OUT, offset: 0x2C
| __IO uint32_t DSI_HOST_Type::CFG_T_POST |
CFG_T_POST, offset: 0xC
| __IO uint32_t DSI_HOST_Type::CFG_T_PRE |
CFG_T_PRE, offset: 0x8
| __IO uint32_t DSI_HOST_Type::CFG_TWAKEUP |
CFG_TWAKEUP, offset: 0x28
| __IO uint32_t DSI_HOST_Type::CFG_TX_GAP |
CFG_TX_GAP, offset: 0x10
| __IO uint32_t MIPI_CSI2RX_Type::CFG_VID_HSYNC |
HSYNC Configuration Register, offset: 0x194
| __IO uint32_t MIPI_CSI2RX_Type::CFG_VID_HSYNC_BP |
End of HSYNC Delay Control Register, offset: 0x198
| __IO uint32_t MIPI_CSI2RX_Type::CFG_VID_HSYNC_FP |
Start of HSYNC Delay control Register, offset: 0x190
| __IO uint32_t MIPI_CSI2RX_Type::CFG_VID_P_FIFO_SEND_LEVEL |
FIFO Send Level Configuration Register, offset: 0x188
| __IO uint32_t MIPI_CSI2RX_Type::CFG_VID_VC |
Virtual Channel value Register, offset: 0x184
| __IO uint32_t MIPI_CSI2RX_Type::CFG_VID_VSYNC |
VSYNC Configuration Register, offset: 0x18C
| __IO uint32_t LPSPI_Type::CFGR0 |
Configuration Register 0, offset: 0x20
Configuration 0, offset: 0x20
| __IO uint32_t LPSPI_Type::CFGR1 |
Configuration Register 1, offset: 0x24
Configuration 1, offset: 0x24
| __I uint32_t CAAM_Type::CFIFOSTA |
CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C
| __I uint32_t { ... } ::CFIFOSTA |
CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C
| __I uint32_t { ... } ::CFIFOSTA |
CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C
| __IO uint32_t CCM_Type::CGPR |
CCM General Purpose Register, offset: 0x64
| __IO uint32_t DCP_Type::CH0CMDPTR |
DCP channel 0 command pointer address register, offset: 0x100
| __IO uint32_t DCP_Type::CH0OPTS |
DCP channel 0 options register, offset: 0x130
| __IO uint32_t DCP_Type::CH0OPTS_CLR |
DCP channel 0 options register, offset: 0x138
| __IO uint32_t DCP_Type::CH0OPTS_SET |
DCP channel 0 options register, offset: 0x134
| __IO uint32_t DCP_Type::CH0OPTS_TOG |
DCP channel 0 options register, offset: 0x13C
| __IO uint32_t DCP_Type::CH0SEMA |
DCP channel 0 semaphore register, offset: 0x110
| __IO uint32_t DCP_Type::CH0STAT |
DCP channel 0 status register, offset: 0x120
| __IO uint32_t DCP_Type::CH0STAT_CLR |
DCP channel 0 status register, offset: 0x128
| __IO uint32_t DCP_Type::CH0STAT_SET |
DCP channel 0 status register, offset: 0x124
| __IO uint32_t DCP_Type::CH0STAT_TOG |
DCP channel 0 status register, offset: 0x12C
| __IO uint32_t DCP_Type::CH1CMDPTR |
DCP channel 1 command pointer address register, offset: 0x140
| __IO uint32_t DCP_Type::CH1OPTS |
DCP channel 1 options register, offset: 0x170
| __IO uint32_t DCP_Type::CH1OPTS_CLR |
DCP channel 1 options register, offset: 0x178
| __IO uint32_t DCP_Type::CH1OPTS_SET |
DCP channel 1 options register, offset: 0x174
| __IO uint32_t DCP_Type::CH1OPTS_TOG |
DCP channel 1 options register, offset: 0x17C
| __IO uint32_t DCP_Type::CH1SEMA |
DCP channel 1 semaphore register, offset: 0x150
| __IO uint32_t DCP_Type::CH1STAT |
DCP channel 1 status register, offset: 0x160
| __IO uint32_t DCP_Type::CH1STAT_CLR |
DCP channel 1 status register, offset: 0x168
| __IO uint32_t DCP_Type::CH1STAT_SET |
DCP channel 1 status register, offset: 0x164
| __IO uint32_t DCP_Type::CH1STAT_TOG |
DCP channel 1 status register, offset: 0x16C
| __IO uint32_t DCP_Type::CH2CMDPTR |
DCP channel 2 command pointer address register, offset: 0x180
| __IO uint32_t DCP_Type::CH2OPTS |
DCP channel 2 options register, offset: 0x1B0
| __IO uint32_t DCP_Type::CH2OPTS_CLR |
DCP channel 2 options register, offset: 0x1B8
| __IO uint32_t DCP_Type::CH2OPTS_SET |
DCP channel 2 options register, offset: 0x1B4
| __IO uint32_t DCP_Type::CH2OPTS_TOG |
DCP channel 2 options register, offset: 0x1BC
| __IO uint32_t DCP_Type::CH2SEMA |
DCP channel 2 semaphore register, offset: 0x190
| __IO uint32_t DCP_Type::CH2STAT |
DCP channel 2 status register, offset: 0x1A0
| __IO uint32_t DCP_Type::CH2STAT_CLR |
DCP channel 2 status register, offset: 0x1A8
| __IO uint32_t DCP_Type::CH2STAT_SET |
DCP channel 2 status register, offset: 0x1A4
| __IO uint32_t DCP_Type::CH2STAT_TOG |
DCP channel 2 status register, offset: 0x1AC
| __IO uint32_t DCP_Type::CH3CMDPTR |
DCP channel 3 command pointer address register, offset: 0x1C0
| __IO uint32_t DCP_Type::CH3OPTS |
DCP channel 3 options register, offset: 0x1F0
| __IO uint32_t DCP_Type::CH3OPTS_CLR |
DCP channel 3 options register, offset: 0x1F8
| __IO uint32_t DCP_Type::CH3OPTS_SET |
DCP channel 3 options register, offset: 0x1F4
| __IO uint32_t DCP_Type::CH3OPTS_TOG |
DCP channel 3 options register, offset: 0x1FC
| __IO uint32_t DCP_Type::CH3SEMA |
DCP channel 3 semaphore register, offset: 0x1D0
| __IO uint32_t DCP_Type::CH3STAT |
DCP channel 3 status register, offset: 0x1E0
| __IO uint32_t DCP_Type::CH3STAT_CLR |
DCP channel 3 status register, offset: 0x1E8
| __IO uint32_t DCP_Type::CH3STAT_SET |
DCP channel 3 status register, offset: 0x1E4
| __IO uint32_t DCP_Type::CH3STAT_TOG |
DCP channel 3 status register, offset: 0x1EC
| __IO uint32_t DCP_Type::CHANNELCTRL |
DCP channel control register, offset: 0x20
| __IO uint32_t DCP_Type::CHANNELCTRL_CLR |
DCP channel control register, offset: 0x28
| __IO uint32_t DCP_Type::CHANNELCTRL_SET |
DCP channel control register, offset: 0x24
| __IO uint32_t DCP_Type::CHANNELCTRL_TOG |
DCP channel control register, offset: 0x2C
| __I uint32_t CAAM_Type::CHANUM_LS |
CHA Number Register, least-significant half, offset: 0xFF4
| __I uint32_t CAAM_Type::CHANUM_LS_DC01 |
CHA Number Register, least-significant half, offset: 0x80FF4
| __I uint32_t { ... } ::CHANUM_LS_JR |
CHA Number Register, least-significant half, array offset: 0x10FF4, array step: 0x10000
| __I uint32_t CAAM_Type::CHANUM_LS_JR |
CHA Number Register, least-significant half, array offset: 0x10FF4, array step: 0x10000
| __I uint32_t { ... } ::CHANUM_LS_JR |
CHA Number Register, least-significant half, array offset: 0x10FF4, array step: 0x10000
| __I uint32_t CAAM_Type::CHANUM_LS_RTIC |
CHA Number Register, least-significant half, offset: 0x60FF4
| __I uint32_t CAAM_Type::CHANUM_MS |
CHA Number Register, most-significant half, offset: 0xFF0
| __I uint32_t CAAM_Type::CHANUM_MS_DC01 |
CHA Number Register, most-significant half, offset: 0x80FF0
| __I uint32_t CAAM_Type::CHANUM_MS_JR |
CHA Number Register, most-significant half, array offset: 0x10FF0, array step: 0x10000
| __I uint32_t { ... } ::CHANUM_MS_JR |
CHA Number Register, most-significant half, array offset: 0x10FF0, array step: 0x10000
| __I uint32_t { ... } ::CHANUM_MS_JR |
CHA Number Register, most-significant half, array offset: 0x10FF0, array step: 0x10000
| __I uint32_t CAAM_Type::CHANUM_MS_RTIC |
CHA Number Register, most-significant half, offset: 0x60FF0
| __I uint32_t CAAM_Type::CHAVID_LS |
CHA Version ID Register, least-significant half, offset: 0xFEC
| __I uint32_t CAAM_Type::CHAVID_LS_DC01 |
CHA Version ID Register, least-significant half, offset: 0x80FEC
| __I uint32_t CAAM_Type::CHAVID_LS_JR |
CHA Version ID Register, least-significant half, array offset: 0x10FEC, array step: 0x10000
| __I uint32_t { ... } ::CHAVID_LS_JR |
CHA Version ID Register, least-significant half, array offset: 0x10FEC, array step: 0x10000
| __I uint32_t { ... } ::CHAVID_LS_JR |
CHA Version ID Register, least-significant half, array offset: 0x10FEC, array step: 0x10000
| __I uint32_t CAAM_Type::CHAVID_LS_RTIC |
CHA Version ID Register, least-significant half, offset: 0x60FEC
| __I uint32_t CAAM_Type::CHAVID_MS |
CHA Version ID Register, most-significant half, offset: 0xFE8
| __I uint32_t CAAM_Type::CHAVID_MS_DC01 |
CHA Version ID Register, most-significant half, offset: 0x80FE8
| __I uint32_t CAAM_Type::CHAVID_MS_JR |
CHA Version ID Register, most-significant half, array offset: 0x10FE8, array step: 0x10000
| __I uint32_t { ... } ::CHAVID_MS_JR |
CHA Version ID Register, most-significant half, array offset: 0x10FE8, array step: 0x10000
| __I uint32_t { ... } ::CHAVID_MS_JR |
CHA Version ID Register, most-significant half, array offset: 0x10FE8, array step: 0x10000
| __I uint32_t CAAM_Type::CHAVID_MS_RTIC |
CHA Version ID Register, most-significant half, offset: 0x60FE8
| __IO uint32_t DMAMUX_Type::CHCFG |
Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4
| __IO uint32_t { ... } ::CHRG_DETECT |
USB Charger Detect Register, array offset: 0x1B0, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::CHRG_DETECT |
USB Charger Detect Register, array offset: 0x1B0, array step: 0x60
| __IO uint32_t { ... } ::CHRG_DETECT_CLR |
USB Charger Detect Register, array offset: 0x1B8, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::CHRG_DETECT_CLR |
USB Charger Detect Register, array offset: 0x1B8, array step: 0x60
| __IO uint32_t { ... } ::CHRG_DETECT_SET |
USB Charger Detect Register, array offset: 0x1B4, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::CHRG_DETECT_SET |
USB Charger Detect Register, array offset: 0x1B4, array step: 0x60
| __I uint32_t { ... } ::CHRG_DETECT_STAT |
USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60
| __I uint32_t USB_ANALOG_Type::CHRG_DETECT_STAT |
USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60
| __IO uint32_t { ... } ::CHRG_DETECT_TOG |
USB Charger Detect Register, array offset: 0x1BC, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::CHRG_DETECT_TOG |
USB Charger Detect Register, array offset: 0x1BC, array step: 0x60
| __IO uint32_t { ... } ::CICTL |
CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C
| __IO uint32_t CAAM_Type::CICTL |
CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C
| __IO uint32_t { ... } ::CICTL |
CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C
| __O uint32_t CAAM_Type::CIFIFO |
CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C
| __O uint32_t { ... } ::CIFIFO |
CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C
| __O uint32_t { ... } ::CIFIFO |
CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C
| __IO uint32_t CCM_Type::CIMR |
CCM Interrupt Mask Register, offset: 0x5C
| __O uint8_t DMA_Type::CINT |
Clear Interrupt Request, offset: 0x1F
| __IO uint32_t CCM_Type::CISR |
CCM Interrupt Status Register, offset: 0x58
| __IO uint16_t DMA_Type::CITER_ELINKNO |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKNO |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKNO |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKNO |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKYES |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t DMA_Type::CITER_ELINKYES |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKYES |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKYES |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20
| __IO uint32_t USDHC_Type::CLK_TUNE_CTRL_STATUS |
CLK Tuning Control and Status, offset: 0x68
| __IO uint32_t EMVSIM_Type::CLKCFG |
Clock Configuration Register, offset: 0x8
| __IO uint8_t EWM_Type::CLKCTRL |
Clock Control Register, offset: 0x4
| __IO uint8_t EWM_Type::CLKPRESCALER |
Clock Prescaler Register, offset: 0x5
| __IO uint32_t USBHSDCD_Type::CLOCK |
Clock register, offset: 0x4
| __IO uint32_t CCM_Type::CLPCR |
CCM Low Power Control Register, offset: 0x54
| __IO uint32_t AUDIO_PLL_Type::CLR |
Fractional PLL Control Register, offset: 0x8
Fractional PLL Spread Spectrum Control Register, offset: 0x18
Fractional PLL Numerator Control Register, offset: 0x28
Fractional PLL Denominator Control Register, offset: 0x38
| __IO uint32_t { ... } ::CLR |
Fractional PLL Control Register, offset: 0x8
| __IO uint32_t { ... } ::CLR |
Fractional PLL Spread Spectrum Control Register, offset: 0x18
| __IO uint32_t { ... } ::CLR |
Fractional PLL Numerator Control Register, offset: 0x28
| __IO uint32_t { ... } ::CLR |
Fractional PLL Denominator Control Register, offset: 0x38
| __IO uint32_t CCM_Type::CLR |
General Purpose Register, array offset: 0x4808, array step: 0x20
| __IO uint32_t { ... } ::CLR |
General Purpose Register, array offset: 0x4808, array step: 0x20
| __IO uint32_t ETHERNET_PLL_Type::CLR |
Fractional PLL Control Register, offset: 0x8
Fractional PLL Spread Spectrum Control Register, offset: 0x18
Fractional PLL Numerator Control Register, offset: 0x28
Fractional PLL Denominator Control Register, offset: 0x38
| __IO uint32_t { ... } ::CLR |
Fractional PLL Control Register, offset: 0x8
| __IO uint32_t { ... } ::CLR |
Fractional PLL Spread Spectrum Control Register, offset: 0x18
| __IO uint32_t { ... } ::CLR |
Fractional PLL Numerator Control Register, offset: 0x28
| __IO uint32_t { ... } ::CLR |
Fractional PLL Denominator Control Register, offset: 0x38
| __IO uint32_t OSC_RC_400M_Type::CLR |
Control Register 0, offset: 0x8
Control Register 1, offset: 0x18
Control Register 2, offset: 0x28
Control Register 3, offset: 0x38
| __IO uint32_t { ... } ::CLR |
Control Register 0, offset: 0x8
| __IO uint32_t { ... } ::CLR |
Control Register 1, offset: 0x18
| __IO uint32_t { ... } ::CLR |
Control Register 2, offset: 0x28
| __IO uint32_t { ... } ::CLR |
Control Register 3, offset: 0x38
| __I uint32_t { ... } ::CLR |
Status Register 0, offset: 0x58
| __I uint32_t OSC_RC_400M_Type::CLR |
Status Register 0, offset: 0x58
Status Register 1, offset: 0x68
Status Register 2, offset: 0x78
| __I uint32_t { ... } ::CLR |
Status Register 1, offset: 0x68
| __I uint32_t { ... } ::CLR |
Status Register 2, offset: 0x78
| __IO uint32_t { ... } ::CLR |
Analog Control Register CTRL0, offset: 0x8
| __IO uint32_t PHY_LDO_Type::CLR |
Analog Control Register CTRL0, offset: 0x8
| __I uint32_t { ... } ::CLR |
Analog Status Register STAT0, offset: 0x58
| __I uint32_t PHY_LDO_Type::CLR |
Analog Status Register STAT0, offset: 0x58
| __IO uint32_t VIDEO_MUX_Type::CLR |
Video mux Control Register, offset: 0x8
Pixel Link Master(PLM) Control Register, offset: 0x28
YUV420 Control Register, offset: 0x38
Data Disable Register, offset: 0x58
MIPI DSI Control Register, offset: 0x78
| __IO uint32_t { ... } ::CLR |
Video mux Control Register, offset: 0x8
| __IO uint32_t { ... } ::CLR |
Pixel Link Master(PLM) Control Register, offset: 0x28
| __IO uint32_t { ... } ::CLR |
YUV420 Control Register, offset: 0x38
| __IO uint32_t { ... } ::CLR |
Data Disable Register, offset: 0x58
| __IO uint32_t { ... } ::CLR |
MIPI DSI Control Register, offset: 0x78
| __IO uint32_t VIDEO_PLL_Type::CLR |
Fractional PLL Control Register, offset: 0x8
Fractional PLL Spread Spectrum Control Register, offset: 0x18
Fractional PLL Numerator Control Register, offset: 0x28
Fractional PLL Denominator Control Register, offset: 0x38
| __IO uint32_t { ... } ::CLR |
Fractional PLL Control Register, offset: 0x8
| __IO uint32_t { ... } ::CLR |
Fractional PLL Spread Spectrum Control Register, offset: 0x18
| __IO uint32_t { ... } ::CLR |
Fractional PLL Numerator Control Register, offset: 0x28
| __IO uint32_t { ... } ::CLR |
Fractional PLL Denominator Control Register, offset: 0x38
| __IO uint32_t VMBANDGAP_Type::CLR |
Analog Control Register CTRL0, offset: 0x8
| __IO uint32_t { ... } ::CLR |
Analog Control Register CTRL0, offset: 0x8
| __I uint32_t VMBANDGAP_Type::CLR |
Analog Status Register STAT0, offset: 0x58
| __I uint32_t { ... } ::CLR |
Analog Status Register STAT0, offset: 0x58
| __IO uint32_t { ... } ::CLR |
Fractional PLL Control Register, offset: 0x8
| __IO uint32_t { ... } ::CLR |
Fractional PLL Spread Spectrum Control Register, offset: 0x18
| __IO uint32_t { ... } ::CLR |
Fractional PLL Numerator Control Register, offset: 0x28
| __IO uint32_t { ... } ::CLR |
Fractional PLL Denominator Control Register, offset: 0x38
| __IO uint32_t { ... } ::CLR |
General Purpose Register, array offset: 0x4808, array step: 0x20
| __IO uint32_t { ... } ::CLR |
Fractional PLL Control Register, offset: 0x8
| __IO uint32_t { ... } ::CLR |
Fractional PLL Spread Spectrum Control Register, offset: 0x18
| __IO uint32_t { ... } ::CLR |
Fractional PLL Numerator Control Register, offset: 0x28
| __IO uint32_t { ... } ::CLR |
Fractional PLL Denominator Control Register, offset: 0x38
| __IO uint32_t { ... } ::CLR |
Control Register 0, offset: 0x8
| __IO uint32_t { ... } ::CLR |
Control Register 1, offset: 0x18
| __IO uint32_t { ... } ::CLR |
Control Register 2, offset: 0x28
| __IO uint32_t { ... } ::CLR |
Control Register 3, offset: 0x38
| __I uint32_t { ... } ::CLR |
Status Register 0, offset: 0x58
| __I uint32_t { ... } ::CLR |
Status Register 1, offset: 0x68
| __I uint32_t { ... } ::CLR |
Status Register 2, offset: 0x78
| __IO uint32_t { ... } ::CLR |
Analog Control Register CTRL0, offset: 0x8
| __I uint32_t { ... } ::CLR |
Analog Status Register STAT0, offset: 0x58
| __IO uint32_t { ... } ::CLR |
Video mux Control Register, offset: 0x8
| __IO uint32_t { ... } ::CLR |
Pixel Link Master(PLM) Control Register, offset: 0x28
| __IO uint32_t { ... } ::CLR |
YUV420 Control Register, offset: 0x38
| __IO uint32_t { ... } ::CLR |
Data Disable Register, offset: 0x58
| __IO uint32_t { ... } ::CLR |
MIPI DSI Control Register, offset: 0x78
| __IO uint32_t { ... } ::CLR |
Fractional PLL Control Register, offset: 0x8
| __IO uint32_t { ... } ::CLR |
Fractional PLL Spread Spectrum Control Register, offset: 0x18
| __IO uint32_t { ... } ::CLR |
Fractional PLL Numerator Control Register, offset: 0x28
| __IO uint32_t { ... } ::CLR |
Fractional PLL Denominator Control Register, offset: 0x38
| __IO uint32_t { ... } ::CLR |
Analog Control Register CTRL0, offset: 0x8
| __I uint32_t { ... } ::CLR |
Analog Status Register STAT0, offset: 0x58
| __IO uint32_t LCDIFV2_Type::CLUT_LOAD |
LCDIFv2 CLUT load Register, offset: 0x400
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::CM |
CM, offset: 0x28
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_AUTHEN_CTRL |
CM Authentication Control, offset: 0x4
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_INT_CTRL |
CM Interrupt Control, offset: 0x8
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_IRQ_WAKEUP_MASK |
CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask, array offset: 0x100, array step: 0x4
| __I uint32_t GPC_CPU_MODE_CTRL_Type::CM_IRQ_WAKEUP_STAT |
CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status, array offset: 0x150, array step: 0x4
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_MISC |
Miscellaneous, offset: 0xC
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_MODE_CTRL |
CPU mode control, offset: 0x10
| __I uint32_t GPC_CPU_MODE_CTRL_Type::CM_MODE_STAT |
CM CPU mode Status, offset: 0x14
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_NON_IRQ_WAKEUP_MASK |
CM non-irq wakeup mask, offset: 0x140
| __I uint32_t GPC_CPU_MODE_CTRL_Type::CM_NON_IRQ_WAKEUP_STAT |
CM non-irq wakeup status, offset: 0x190
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_RUN_MODE_MAPPING |
CM Run Mode Setpoint Allowed, offset: 0x310
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_ISO_CTRL |
CM sleep isolation control, offset: 0x218
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_LPCG_CTRL |
CM sleep LPCG control, offset: 0x208
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_PLL_CTRL |
CM sleep PLL control, offset: 0x210
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_POWER_CTRL |
CM sleep power control, offset: 0x228
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_RESET_CTRL |
CM sleep reset control, offset: 0x220
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_SSAR_CTRL |
CM sleep SSAR control, offset: 0x200
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SP_CTRL |
CM Setpoint Control, offset: 0x300
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SP_MAPPING |
CM Setpoint 0 Mapping..CM Setpoint 15 Mapping, array offset: 0x320, array step: 0x4
| __I uint32_t GPC_CPU_MODE_CTRL_Type::CM_SP_STAT |
CM Setpoint Status, offset: 0x304
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_STBY_CTRL |
CM standby control, offset: 0x380
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_STOP_MODE_MAPPING |
CM Stop Mode Setpoint Allowed, offset: 0x318
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SUSPEND_MODE_MAPPING |
CM Suspend Mode Setpoint Allowed, offset: 0x31C
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAIT_MODE_MAPPING |
CM Wait Mode Setpoint Allowed, offset: 0x314
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_ISO_CTRL |
CM wakeup isolation control, offset: 0x2A0
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_LPCG_CTRL |
CM wakeup LPCG control, offset: 0x2B0
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_PLL_CTRL |
CM wakeup PLL control, offset: 0x2A8
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_POWER_CTRL |
CM wakeup power control, offset: 0x290
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_RESET_CTRL |
CM wakeup reset control, offset: 0x298
| __IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_SSAR_CTRL |
CM wakeup SSAR control, offset: 0x2B8
| __IO uint32_t USDHC_Type::CMD_ARG |
Command Argument, offset: 0x8
| __I uint32_t USDHC_Type::CMD_RSP0 |
Command Response0, offset: 0x10
| __I uint32_t USDHC_Type::CMD_RSP1 |
Command Response1, offset: 0x14
| __I uint32_t USDHC_Type::CMD_RSP2 |
Command Response2, offset: 0x18
| __I uint32_t USDHC_Type::CMD_RSP3 |
Command Response3, offset: 0x1C
| __IO uint32_t USDHC_Type::CMD_XFR_TYP |
Command Transfer Type, offset: 0xC
| __IO uint32_t { ... } ::CMDH |
LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8
| __IO uint32_t ADC_Type::CMDH |
LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8
| __IO uint32_t { ... } ::CMDH |
LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8
| __IO uint32_t ADC_Type::CMDL |
LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8
| __IO uint32_t { ... } ::CMDL |
LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8
| __IO uint32_t { ... } ::CMDL |
LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8
| __IO uint32_t CCM_Type::CMEOR |
CCM Module Enable Overide Register, offset: 0x88
| __IO uint8_t EWM_Type::CMPH |
Compare High Register, offset: 0x3
| __IO uint8_t EWM_Type::CMPL |
Compare Low Register, offset: 0x2
| __IO uint16_t { ... } ::CMPLD1 |
Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20
| __IO uint16_t TMR_Type::CMPLD1 |
Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20
| __IO uint16_t { ... } ::CMPLD1 |
Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20
| __IO uint16_t { ... } ::CMPLD1 |
Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20
| __IO uint16_t { ... } ::CMPLD2 |
Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20
| __IO uint16_t TMR_Type::CMPLD2 |
Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20
| __IO uint16_t { ... } ::CMPLD2 |
Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20
| __IO uint16_t { ... } ::CMPLD2 |
Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::CN |
CN, offset: 0x24
| __O uint32_t CAAM_Type::CNFIFO |
CCB 0 iNformation FIFO When STYPE != 10b, array offset: 0x807D0, array step: 0xE3C
| __O uint32_t { ... } ::CNFIFO |
CCB 0 iNformation FIFO When STYPE != 10b, array offset: 0x807D0, array step: 0xE3C
| __O uint32_t { ... } ::CNFIFO |
CCB 0 iNformation FIFO When STYPE != 10b, array offset: 0x807D0, array step: 0xE3C
| __O uint32_t { ... } ::CNFIFO_2 |
CCB 0 iNformation FIFO When STYPE == 10b, array offset: 0x807D0, array step: 0xE3C
| __O uint32_t CAAM_Type::CNFIFO_2 |
CCB 0 iNformation FIFO When STYPE == 10b, array offset: 0x807D0, array step: 0xE3C
| __O uint32_t { ... } ::CNFIFO_2 |
CCB 0 iNformation FIFO When STYPE == 10b, array offset: 0x807D0, array step: 0xE3C
| __I uint32_t GPT_Type::CNT |
GPT Counter Register, offset: 0x24
| __I uint16_t PWM_Type::CNT |
Counter Register, array offset: 0x0, array step: 0x60
| __I uint16_t { ... } ::CNT |
Counter Register, array offset: 0x0, array step: 0x60
| __IO uint32_t RTWDOG_Type::CNT |
Watchdog Counter Register, offset: 0x4
| __I uint16_t { ... } ::CNT |
Counter Register, array offset: 0x0, array step: 0x60
| __I uint16_t { ... } ::CNT |
Counter Register, array offset: 0x0, array step: 0x60
| __IO uint32_t GPC_Type::CNTR |
GPC Interface control register, offset: 0x0
| __IO uint16_t TMR_Type::CNTR |
Timer Channel Counter Register, array offset: 0xA, array step: 0x20
| __IO uint16_t { ... } ::CNTR |
Timer Channel Counter Register, array offset: 0xA, array step: 0x20
| __IO uint16_t { ... } ::CNTR |
Timer Channel Counter Register, array offset: 0xA, array step: 0x20
| __IO uint16_t { ... } ::CNTR |
Timer Channel Counter Register, array offset: 0xA, array step: 0x20
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::CO |
CO, offset: 0x2C
| __O uint32_t PUF_Type::CODEINPUT |
PUF Code Input Register, offset: 0x44
| __I uint32_t PUF_Type::CODEOUTPUT |
PUF Code Output Register, offset: 0x48
| __I uint64_t { ... } ::COFIFO |
CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C
| __I uint64_t CAAM_Type::COFIFO |
CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C
| __I uint64_t { ... } ::COFIFO |
CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C
| __IO uint16_t { ... } ::COMP1 |
Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20
| __IO uint16_t TMR_Type::COMP1 |
Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20
| __IO uint16_t { ... } ::COMP1 |
Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20
| __IO uint16_t { ... } ::COMP1 |
Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20
| __IO uint16_t TMR_Type::COMP2 |
Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20
| __IO uint16_t { ... } ::COMP2 |
Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20
| __IO uint16_t { ... } ::COMP2 |
Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20
| __IO uint16_t { ... } ::COMP2 |
Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20
| __I uint32_t CCM_Type::CONFIG |
Clock root configuration, array offset: 0x2C, array step: 0x80
Clock group configuration, array offset: 0x402C, array step: 0x80
Clock source configuration, array offset: 0x5018, array step: 0x20
LPCG configuration, array offset: 0x6018, array step: 0x20
| __I uint32_t { ... } ::CONFIG |
Clock root configuration, array offset: 0x2C, array step: 0x80
| __I uint32_t { ... } ::CONFIG |
Clock group configuration, array offset: 0x402C, array step: 0x80
| __I uint32_t { ... } ::CONFIG |
Clock source configuration, array offset: 0x5018, array step: 0x20
| __I uint32_t { ... } ::CONFIG |
LPCG configuration, array offset: 0x6018, array step: 0x20
| __I uint32_t { ... } ::CONFIG |
Clock root configuration, array offset: 0x2C, array step: 0x80
| __I uint32_t { ... } ::CONFIG |
Clock group configuration, array offset: 0x402C, array step: 0x80
| __I uint32_t { ... } ::CONFIG |
Clock source configuration, array offset: 0x5018, array step: 0x20
| __I uint32_t { ... } ::CONFIG |
LPCG configuration, array offset: 0x6018, array step: 0x20
| __I uint32_t USB_Type::CONFIGFLAG |
Configure Flag Register, offset: 0x180
| __IO uint32_t DCP_Type::CONTEXT |
DCP context buffer pointer, offset: 0x50
| __IO uint32_t { ... } ::CONTROL |
Clock root control, array offset: 0x0, array step: 0x80
| __IO uint32_t CCM_Type::CONTROL |
Clock root control, array offset: 0x0, array step: 0x80
Clock group control, array offset: 0x4000, array step: 0x80
| __IO uint32_t { ... } ::CONTROL |
Clock group control, array offset: 0x4000, array step: 0x80
| __IO uint32_t { ... } ::CONTROL |
Observe control, array offset: 0x0, array step: 0x80
| __IO uint32_t CCM_OBS_Type::CONTROL |
Observe control, array offset: 0x0, array step: 0x80
| __IO uint32_t CDOG_Type::CONTROL |
Control, offset: 0x0
| __IO uint32_t USBHSDCD_Type::CONTROL |
Control register, offset: 0x0
| __IO uint32_t { ... } ::CONTROL |
Clock root control, array offset: 0x0, array step: 0x80
| __IO uint32_t { ... } ::CONTROL |
Clock group control, array offset: 0x4000, array step: 0x80
| __IO uint32_t { ... } ::CONTROL |
Observe control, array offset: 0x0, array step: 0x80
| __IO uint32_t CCM_Type::CONTROL_CLR |
Clock root control, array offset: 0x8, array step: 0x80
Clock group control, array offset: 0x4008, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_CLR |
Clock root control, array offset: 0x8, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_CLR |
Clock group control, array offset: 0x4008, array step: 0x80
| __IO uint32_t CCM_OBS_Type::CONTROL_CLR |
Observe control, array offset: 0x8, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_CLR |
Observe control, array offset: 0x8, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_CLR |
Clock root control, array offset: 0x8, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_CLR |
Clock group control, array offset: 0x4008, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_CLR |
Observe control, array offset: 0x8, array step: 0x80
| __IO uint32_t CCM_Type::CONTROL_SET |
Clock root control, array offset: 0x4, array step: 0x80
Clock group control, array offset: 0x4004, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_SET |
Clock root control, array offset: 0x4, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_SET |
Clock group control, array offset: 0x4004, array step: 0x80
| __IO uint32_t CCM_OBS_Type::CONTROL_SET |
Observe control, array offset: 0x4, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_SET |
Observe control, array offset: 0x4, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_SET |
Clock root control, array offset: 0x4, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_SET |
Clock group control, array offset: 0x4004, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_SET |
Observe control, array offset: 0x4, array step: 0x80
| __IO uint32_t CCM_Type::CONTROL_TOG |
Clock root control, array offset: 0xC, array step: 0x80
Clock group control, array offset: 0x400C, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_TOG |
Clock root control, array offset: 0xC, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_TOG |
Clock group control, array offset: 0x400C, array step: 0x80
| __IO uint32_t CCM_OBS_Type::CONTROL_TOG |
Observe control, array offset: 0xC, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_TOG |
Observe control, array offset: 0xC, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_TOG |
Clock root control, array offset: 0xC, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_TOG |
Clock group control, array offset: 0x400C, array step: 0x80
| __IO uint32_t { ... } ::CONTROL_TOG |
Observe control, array offset: 0xC, array step: 0x80
| __IO uint32_t PGMC_CPC_Type::CPC_AUTHEN_CTRL |
CPC Authentication Control, offset: 0x4
| __IO uint32_t PGMC_CPC_Type::CPC_CACHE_CM_CTRL |
CPC cache CPU mode control, offset: 0x44
| __IO uint32_t PGMC_CPC_Type::CPC_CACHE_MODE |
CPC Cache Mode, offset: 0x40
| __IO uint32_t PGMC_CPC_Type::CPC_CACHE_SP_CTRL_0 |
CPC cache Setpoint control 0, offset: 0x48
| __IO uint32_t PGMC_CPC_Type::CPC_CACHE_SP_CTRL_1 |
CPC cache Setpoint control 1, offset: 0x4C
| __IO uint32_t PGMC_CPC_Type::CPC_CORE_MODE |
CPC Core Mode, offset: 0x10
| __IO uint32_t PGMC_CPC_Type::CPC_CORE_POWER_CTRL |
CPC core power control, offset: 0x14
| __IO uint32_t PGMC_CPC_Type::CPC_FLAG |
CPC flag, offset: 0x2C
| __IO uint32_t PGMC_CPC_Type::CPC_LMEM_CM_CTRL |
CPC local memory CPU mode control, offset: 0xC4
| __IO uint32_t PGMC_CPC_Type::CPC_LMEM_MODE |
CPC local memory Mode, offset: 0xC0
| __IO uint32_t PGMC_CPC_Type::CPC_LMEM_SP_CTRL_0 |
CPC local memory Setpoint control 0, offset: 0xC8
| __IO uint32_t PGMC_CPC_Type::CPC_LMEM_SP_CTRL_1 |
CPC local memory Setpoint control 1, offset: 0xCC
| __IO uint16_t SEMA4_Type::CPINE |
Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8
| __IO uint16_t { ... } ::CPINE |
Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8
| __IO uint16_t { ... } ::CPINE |
Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8
| __IO uint32_t { ... } ::CPKASZR |
PKHA A Size Register, array offset: 0x80084, array step: 0xE3C
| __IO uint32_t CAAM_Type::CPKASZR |
PKHA A Size Register, array offset: 0x80084, array step: 0xE3C
| __IO uint32_t { ... } ::CPKASZR |
PKHA A Size Register, array offset: 0x80084, array step: 0xE3C
| __IO uint32_t { ... } ::CPKBSZR |
PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C
| __IO uint32_t CAAM_Type::CPKBSZR |
PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C
| __IO uint32_t { ... } ::CPKBSZR |
PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C
| __IO uint32_t CAAM_Type::CPKESZR |
PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C
| __IO uint32_t { ... } ::CPKESZR |
PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C
| __IO uint32_t { ... } ::CPKESZR |
PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C
| __IO uint32_t { ... } ::CPKNSZR |
PKHA N Size Register, array offset: 0x80094, array step: 0xE3C
| __IO uint32_t CAAM_Type::CPKNSZR |
PKHA N Size Register, array offset: 0x80094, array step: 0xE3C
| __IO uint32_t { ... } ::CPKNSZR |
PKHA N Size Register, array offset: 0x80094, array step: 0xE3C
| __I uint16_t { ... } ::CPNTF |
Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8
| __I uint16_t SEMA4_Type::CPNTF |
Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8
| __I uint16_t { ... } ::CPNTF |
Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8
| __IO uint32_t PGC_Type::CPU_CTRL |
PGC CPU Control Register, offset: 0x2A0
| __IO uint32_t PGC_Type::CPU_PDNSCR |
PGC CPU Pull Down Sequence Control Register, offset: 0x2A8
| __IO uint32_t PGC_Type::CPU_PUPSCR |
PGC CPU Power Up Sequence Control Register, offset: 0x2A4
| __IO uint32_t PGC_Type::CPU_SR |
PGC CPU Power Gating Controller Status Register, offset: 0x2AC
| __IO uint32_t DMA_Type::CR |
Control, offset: 0x0
| __IO uint32_t GPT_Type::CR |
GPT Control Register, offset: 0x0
| __IO uint32_t LPSPI_Type::CR |
Control Register, offset: 0x10
Control, offset: 0x10
| __IO uint32_t CSI_Type::CR |
CSI Control Register, array offset: 0x54, array step: 0x4
| __IO uint32_t DAC_Type::CR |
DAC Status and Control Register, offset: 0xC
| __IO uint32_t MCM_Type::CR |
Control Register, offset: 0xC
| __IO uint32_t MU_Type::CR |
Processor B Control Register, offset: 0x24
Processor A Control Register, offset: 0x24
| __IO uint32_t OTFAD_Type::CR |
Control Register, offset: 0xC00
| __IO uint8_t CMP_Type::CR0 |
CMP Control Register 0, offset: 0x0
| __IO uint8_t CMP_Type::CR1 |
CMP Control Register 1, offset: 0x1
| __IO uint32_t CSI_Type::CR1 |
CSI Control Register 1, offset: 0x0
| __IO uint32_t CSI_Type::CR18 |
CSI Control Register 18, offset: 0x48
| __IO uint32_t CSI_Type::CR19 |
CSI Control Register 19, offset: 0x4C
| __IO uint32_t CSI_Type::CR2 |
CSI Control Register 2, offset: 0x4
| __IO uint32_t DAC_Type::CR2 |
DAC Status and Control Register 2, offset: 0x14
| __IO uint32_t CSI_Type::CR20 |
CSI Control Register 20, offset: 0x50
| __IO uint32_t CSI_Type::CR3 |
CSI Control Register 3, offset: 0x8
| __IO uint32_t LCDIF_Type::CRC_STAT |
CRC Status Register, offset: 0x1A0
| __I uint32_t CAN_Type::CRCR |
CRC Register, offset: 0x44
CRC register, offset: 0x44
| __I uint32_t CAAM_Type::CRNR_LS |
CHA Revision Number Register, least-significant half, offset: 0xFA4
| __I uint32_t CAAM_Type::CRNR_LS_DC01 |
CHA Revision Number Register, least-significant half, offset: 0x80FA4
| __I uint32_t CAAM_Type::CRNR_LS_JR |
CHA Revision Number Register, least-significant half, array offset: 0x10FA4, array step: 0x10000
| __I uint32_t { ... } ::CRNR_LS_JR |
CHA Revision Number Register, least-significant half, array offset: 0x10FA4, array step: 0x10000
| __I uint32_t { ... } ::CRNR_LS_JR |
CHA Revision Number Register, least-significant half, array offset: 0x10FA4, array step: 0x10000
| __I uint32_t CAAM_Type::CRNR_LS_RTIC |
CHA Revision Number Register, least-significant half, offset: 0x60FA4
| __I uint32_t CAAM_Type::CRNR_MS |
CHA Revision Number Register, most-significant half, offset: 0xFA0
| __I uint32_t CAAM_Type::CRNR_MS_DC01 |
CHA Revision Number Register, most-significant half, offset: 0x80FA0
| __I uint32_t { ... } ::CRNR_MS_JR |
CHA Revision Number Register, most-significant half, array offset: 0x10FA0, array step: 0x10000
| __I uint32_t CAAM_Type::CRNR_MS_JR |
CHA Revision Number Register, most-significant half, array offset: 0x10FA0, array step: 0x10000
| __I uint32_t { ... } ::CRNR_MS_JR |
CHA Revision Number Register, most-significant half, array offset: 0x10FA0, array step: 0x10000
| __I uint32_t CAAM_Type::CRNR_MS_RTIC |
CHA Revision Number Register, most-significant half, offset: 0x60FA0
| __IO uint32_t CAN_Type::CS |
Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10
Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18
Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x280, array step: 0x18
Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28
Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x280, array step: 0x28
Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48
Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x280, array step: 0x48
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10
| __IO uint32_t RTWDOG_Type::CS |
Watchdog Control and Status Register, offset: 0x0
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x280, array step: 0x18
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x280, array step: 0x28
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x280, array step: 0x48
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x280, array step: 0x18
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x280, array step: 0x28
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x280, array step: 0x48
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10
| __IO uint32_t CCM_Type::CS1CDR |
CCM Clock Divider Register, offset: 0x28
| __IO uint32_t CCM_Type::CS2CDR |
CCM Clock Divider Register, offset: 0x2C
| __IO uint32_t PXP_Type::CSC1_COEF0 |
Color Space Conversion Coefficient Register 0, offset: 0x1A0
| __IO uint32_t PXP_Type::CSC1_COEF1 |
Color Space Conversion Coefficient Register 1, offset: 0x1B0
| __IO uint32_t PXP_Type::CSC1_COEF2 |
Color Space Conversion Coefficient Register 2, offset: 0x1C0
| __IO uint32_t { ... } ::CSC_COEF0 |
Color Space Conversion Coefficient Register 0, array offset: 0x218, array step: 0x40, this item is not available for all array instances
| __IO uint32_t LCDIFV2_Type::CSC_COEF0 |
Color Space Conversion Coefficient Register 0, array offset: 0x218, array step: 0x40, this item is not available for all array instances
| __IO uint32_t { ... } ::CSC_COEF0 |
Color Space Conversion Coefficient Register 0, array offset: 0x218, array step: 0x40, this item is not available for all array instances
| __IO uint32_t LCDIFV2_Type::CSC_COEF1 |
Color Space Conversion Coefficient Register 1, array offset: 0x21C, array step: 0x40, this item is not available for all array instances
| __IO uint32_t { ... } ::CSC_COEF1 |
Color Space Conversion Coefficient Register 1, array offset: 0x21C, array step: 0x40, this item is not available for all array instances
| __IO uint32_t { ... } ::CSC_COEF1 |
Color Space Conversion Coefficient Register 1, array offset: 0x21C, array step: 0x40, this item is not available for all array instances
| __IO uint32_t { ... } ::CSC_COEF2 |
Color Space Conversion Coefficient Register 2, array offset: 0x220, array step: 0x40, this item is not available for all array instances
| __IO uint32_t LCDIFV2_Type::CSC_COEF2 |
Color Space Conversion Coefficient Register 2, array offset: 0x220, array step: 0x40, this item is not available for all array instances
| __IO uint32_t { ... } ::CSC_COEF2 |
Color Space Conversion Coefficient Register 2, array offset: 0x220, array step: 0x40, this item is not available for all array instances
| __IO uint32_t CCM_Type::CSCDR1 |
CCM Serial Clock Divider Register 1, offset: 0x24
| __IO uint32_t CCM_Type::CSCDR2 |
CCM Serial Clock Divider Register 2, offset: 0x38
| __IO uint32_t CCM_Type::CSCDR3 |
CCM Serial Clock Divider Register 3, offset: 0x3C
| __IO uint32_t CCM_Type::CSCMR1 |
CCM Serial Clock Multiplexer Register 1, offset: 0x1C
| __IO uint32_t CCM_Type::CSCMR2 |
CCM Serial Clock Multiplexer Register 2, offset: 0x20
| __IO uint16_t TMR_Type::CSCTRL |
Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20
| __IO uint16_t { ... } ::CSCTRL |
Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20
| __IO uint16_t { ... } ::CSCTRL |
Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20
| __IO uint16_t { ... } ::CSCTRL |
Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20
| __IO uint32_t CSU_Type::CSL[32] |
Config security level register, array offset: 0x0, array step: 0x4
| __I uint32_t CCM_Type::CSR |
CCM Status Register, offset: 0x8
| __IO uint16_t { ... } ::CSR |
TCD Control and Status, array offset: 0x101C, array step: 0x20
| __IO uint16_t DMA_Type::CSR |
TCD Control and Status, array offset: 0x101C, array step: 0x20
| __IO uint16_t { ... } ::CSR |
TCD Control and Status, array offset: 0x101C, array step: 0x20
| __IO uint16_t { ... } ::CSR |
TCD Control and Status, array offset: 0x101C, array step: 0x20
| __I uint32_t CAAM_Type::CSTA |
CAAM Status Register, offset: 0xFD4
| __I uint32_t CAAM_Type::CSTA_DC01 |
CAAM Status Register, offset: 0x80FD4
| __I uint32_t { ... } ::CSTA_JR |
CAAM Status Register, array offset: 0x10FD4, array step: 0x10000
| __I uint32_t CAAM_Type::CSTA_JR |
CAAM Status Register, array offset: 0x10FD4, array step: 0x10000
| __I uint32_t { ... } ::CSTA_JR |
CAAM Status Register, array offset: 0x10FD4, array step: 0x10000
| __I uint32_t CAAM_Type::CSTA_RTIC |
CAAM Status Register, offset: 0x60FD4
| __I uint32_t CAAM_Type::CTPR_LS |
Compile Time Parameters Register, least-significant half, offset: 0xFAC
| __I uint32_t CAAM_Type::CTPR_LS_DC01 |
Compile Time Parameters Register, least-significant half, offset: 0x80FAC
| __I uint32_t { ... } ::CTPR_LS_JR |
Compile Time Parameters Register, least-significant half, array offset: 0x10FAC, array step: 0x10000
| __I uint32_t CAAM_Type::CTPR_LS_JR |
Compile Time Parameters Register, least-significant half, array offset: 0x10FAC, array step: 0x10000
| __I uint32_t { ... } ::CTPR_LS_JR |
Compile Time Parameters Register, least-significant half, array offset: 0x10FAC, array step: 0x10000
| __I uint32_t CAAM_Type::CTPR_LS_RTIC |
Compile Time Parameters Register, least-significant half, offset: 0x60FAC
| __I uint32_t CAAM_Type::CTPR_MS |
Compile Time Parameters Register, most-significant half, offset: 0xFA8
| __I uint32_t CAAM_Type::CTPR_MS_DC01 |
Compile Time Parameters Register, most-significant half, offset: 0x80FA8
| __I uint32_t { ... } ::CTPR_MS_JR |
Compile Time Parameters Register, most-significant half, array offset: 0x10FA8, array step: 0x10000
| __I uint32_t CAAM_Type::CTPR_MS_JR |
Compile Time Parameters Register, most-significant half, array offset: 0x10FA8, array step: 0x10000
| __I uint32_t { ... } ::CTPR_MS_JR |
Compile Time Parameters Register, most-significant half, array offset: 0x10FA8, array step: 0x10000
| __I uint32_t CAAM_Type::CTPR_MS_RTIC |
Compile Time Parameters Register, most-significant half, offset: 0x60FA8
| __IO uint32_t OTFAD_Type::CTR[2] |
AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4
| __IO uint32_t { ... } ::CTR[2] |
AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4
| __IO uint32_t { ... } ::CTR[2] |
AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4
| __O uint32_t BEE_Type::CTR_NONCE0_W0 |
NONCE00 Register, offset: 0x20
| __O uint32_t BEE_Type::CTR_NONCE0_W1 |
NONCE01 Register, offset: 0x24
| __O uint32_t BEE_Type::CTR_NONCE0_W2 |
NONCE02 Register, offset: 0x28
| __O uint32_t BEE_Type::CTR_NONCE0_W3 |
NONCE03 Register, offset: 0x2C
| __O uint32_t BEE_Type::CTR_NONCE1_W0 |
NONCE10 Register, offset: 0x30
| __O uint32_t BEE_Type::CTR_NONCE1_W1 |
NONCE11 Register, offset: 0x34
| __O uint32_t BEE_Type::CTR_NONCE1_W2 |
NONCE12 Register, offset: 0x38
| __O uint32_t BEE_Type::CTR_NONCE1_W3 |
NONCE13 Register, offset: 0x3C
| __IO uint32_t ADC_ETC_Type::CTRL |
ADC_ETC Global Control Register, offset: 0x0
| __IO uint32_t BEE_Type::CTRL |
Control Register, offset: 0x0
| __IO uint32_t DCP_Type::CTRL |
DCP control register 0, offset: 0x0
| __IO uint16_t ENC_Type::CTRL |
Control Register, offset: 0x0
| __IO uint8_t EWM_Type::CTRL |
Control Register, offset: 0x0
| __IO uint32_t FLEXIO_Type::CTRL |
FlexIO Control Register, offset: 0x8
| __IO uint32_t LCDIF_Type::CTRL |
LCDIF General Control Register, offset: 0x0
| __IO uint32_t LPUART_Type::CTRL |
LPUART Control Register, offset: 0x18
| __IO uint32_t OCOTP_Type::CTRL |
OTP Controller Control and Status Register, offset: 0x0
| __IO uint16_t PWM_Type::CTRL |
Control Register, array offset: 0x6, array step: 0x60
| __IO uint16_t { ... } ::CTRL |
Control Register, array offset: 0x6, array step: 0x60
| __IO uint32_t PXP_Type::CTRL |
Control Register 0, offset: 0x0
| __IO uint16_t { ... } ::CTRL |
Timer Channel Control Register, array offset: 0xC, array step: 0x20
| __IO uint16_t TMR_Type::CTRL |
Timer Channel Control Register, array offset: 0xC, array step: 0x20
| __IO uint32_t USBPHY_Type::CTRL |
USB PHY General Control Register, offset: 0x30
| __IO uint32_t ADC_Type::CTRL |
LPADC Control Register, offset: 0x10
| __IO uint32_t EMVSIM_Type::CTRL |
Control Register, offset: 0x10
| __IO uint32_t LCDIFV2_Type::CTRL |
LCDIFv2 display control Register, offset: 0x0
| __IO uint32_t PUF_Type::CTRL |
PUF Control Register, offset: 0x0
| __IO uint16_t { ... } ::CTRL |
Control Register, array offset: 0x6, array step: 0x60
| __IO uint32_t SRAM_Type::CTRL |
Control Register, offset: 0x3000
| __IO uint32_t SSARC_LP_Type::CTRL |
Control Register, offset: 0x200
| __IO uint16_t { ... } ::CTRL |
Timer Channel Control Register, array offset: 0xC, array step: 0x20
| __IO uint16_t { ... } ::CTRL |
Control Register, array offset: 0x6, array step: 0x60
| __IO uint16_t { ... } ::CTRL |
Timer Channel Control Register, array offset: 0xC, array step: 0x20
| __IO uint16_t XBARA_Type::CTRL0 |
Crossbar A Control Register 0, offset: 0x84
Crossbar A Control Register 0, offset: 0xB0
| __IO uint32_t DCDC_Type::CTRL0 |
DCDC Control Register 0, offset: 0x0
| __IO uint32_t TMPSNS_Type::CTRL0 |
Temperature Sensor Control Register 0, offset: 0x0
| __IO uint32_t TMPSNS_Type::CTRL0_CLR |
Temperature Sensor Control Register 0, offset: 0x8
| __IO uint32_t TMPSNS_Type::CTRL0_SET |
Temperature Sensor Control Register 0, offset: 0x4
| __IO uint32_t TMPSNS_Type::CTRL0_TOG |
Temperature Sensor Control Register 0, offset: 0xC
| __IO uint32_t CAN_Type::CTRL1 |
Control 1 Register, offset: 0x4
Control 1 register, offset: 0x4
| __IO uint32_t LCDIF_Type::CTRL1 |
LCDIF General Control1 Register, offset: 0x10
| __IO uint16_t XBARA_Type::CTRL1 |
Crossbar A Control Register 1, offset: 0x86
Crossbar A Control Register 1, offset: 0xB2
| __IO uint32_t DCDC_Type::CTRL1 |
DCDC Control Register 1, offset: 0x4
| __IO uint32_t TMPSNS_Type::CTRL1 |
Temperature Sensor Control Register 1, offset: 0x10
| __IO uint32_t USBNC_Type::CTRL1 |
USB OTG Control 1 Register, offset: 0x0
| __IO uint32_t LCDIF_Type::CTRL1_CLR |
LCDIF General Control1 Register, offset: 0x18
| __IO uint32_t TMPSNS_Type::CTRL1_CLR |
Temperature Sensor Control Register 1, offset: 0x18
| __IO uint32_t LCDIF_Type::CTRL1_SET |
LCDIF General Control1 Register, offset: 0x14
| __IO uint32_t TMPSNS_Type::CTRL1_SET |
Temperature Sensor Control Register 1, offset: 0x14
| __IO uint32_t LCDIF_Type::CTRL1_TOG |
LCDIF General Control1 Register, offset: 0x1C
| __IO uint32_t TMPSNS_Type::CTRL1_TOG |
Temperature Sensor Control Register 1, offset: 0x1C
| __IO uint32_t CAN_Type::CTRL2 |
Control 2 Register, offset: 0x34
Control 2 register, offset: 0x34
| __IO uint16_t ENC_Type::CTRL2 |
Control 2 Register, offset: 0x1E
| __IO uint32_t LCDIF_Type::CTRL2 |
LCDIF General Control2 Register, offset: 0x20
| __IO uint16_t PWM_Type::CTRL2 |
Control 2 Register, array offset: 0x4, array step: 0x60
| __IO uint16_t { ... } ::CTRL2 |
Control 2 Register, array offset: 0x4, array step: 0x60
| __IO uint16_t { ... } ::CTRL2 |
Control 2 Register, array offset: 0x4, array step: 0x60
| __IO uint32_t USBNC_Type::CTRL2 |
USB OTG Control 2 Register, offset: 0x4
| __IO uint16_t { ... } ::CTRL2 |
Control 2 Register, array offset: 0x4, array step: 0x60
| __IO uint32_t LCDIF_Type::CTRL2_CLR |
LCDIF General Control2 Register, offset: 0x28
| __IO uint32_t LCDIF_Type::CTRL2_SET |
LCDIF General Control2 Register, offset: 0x24
| __IO uint32_t LCDIF_Type::CTRL2_TOG |
LCDIF General Control2 Register, offset: 0x2C
| __IO uint16_t ENC_Type::CTRL3 |
Control 3 Register, offset: 0x32
| __IO uint32_t PDM_Type::CTRL_1 |
PDM Control register 1, offset: 0x0
| __IO uint32_t PDM_Type::CTRL_2 |
PDM Control register 2, offset: 0x4
| __IO uint32_t DCP_Type::CTRL_CLR |
DCP control register 0, offset: 0x8
| __IO uint32_t LCDIF_Type::CTRL_CLR |
LCDIF General Control Register, offset: 0x8
| __IO uint32_t OCOTP_Type::CTRL_CLR |
OTP Controller Control and Status Register, offset: 0x8
| __IO uint32_t PXP_Type::CTRL_CLR |
Control Register 0, offset: 0x8
| __IO uint32_t USBPHY_Type::CTRL_CLR |
USB PHY General Control Register, offset: 0x38
| __IO uint32_t LCDIFV2_Type::CTRL_CLR |
LCDIFv2 display control Register, offset: 0x8
| __IO uint32_t SRC_Type::CTRL_DISPLAY |
Slice Control Register, offset: 0x224
| __IO uint32_t SRC_Type::CTRL_M4CORE |
Slice Control Register, offset: 0x284
| __IO uint32_t SRC_Type::CTRL_M4DEBUG |
Slice Control Register, offset: 0x2C4
| __IO uint32_t SRC_Type::CTRL_M7CORE |
Slice Control Register, offset: 0x2A4
| __IO uint32_t SRC_Type::CTRL_M7DEBUG |
Slice Control Register, offset: 0x2E4
| __IO uint32_t SRC_Type::CTRL_MEGA |
Slice Control Register, offset: 0x204
| __IO uint32_t DCP_Type::CTRL_SET |
DCP control register 0, offset: 0x4
| __IO uint32_t LCDIF_Type::CTRL_SET |
LCDIF General Control Register, offset: 0x4
| __IO uint32_t OCOTP_Type::CTRL_SET |
OTP Controller Control and Status Register, offset: 0x4
| __IO uint32_t PXP_Type::CTRL_SET |
Control Register 0, offset: 0x4
| __IO uint32_t USBPHY_Type::CTRL_SET |
USB PHY General Control Register, offset: 0x34
| __IO uint32_t LCDIFV2_Type::CTRL_SET |
LCDIFv2 display control Register, offset: 0x4
| __IO uint32_t DCP_Type::CTRL_TOG |
DCP control register 0, offset: 0xC
| __IO uint32_t LCDIF_Type::CTRL_TOG |
LCDIF General Control Register, offset: 0xC
| __IO uint32_t OCOTP_Type::CTRL_TOG |
OTP Controller Control and Status Register, offset: 0xC
| __IO uint32_t PXP_Type::CTRL_TOG |
Control Register 0, offset: 0xC
| __IO uint32_t USBPHY_Type::CTRL_TOG |
USB PHY General Control Register, offset: 0x3C
| __IO uint32_t LCDIFV2_Type::CTRL_TOG |
LCDIFv2 display control Register, offset: 0xC
| __IO uint32_t SRC_Type::CTRL_USBPHY1 |
Slice Control Register, offset: 0x304
| __IO uint32_t SRC_Type::CTRL_USBPHY2 |
Slice Control Register, offset: 0x324
| __IO uint32_t SRC_Type::CTRL_WAKEUP |
Slice Control Register, offset: 0x244
| __IO uint32_t LCDIFV2_Type::CTRLDESCL1 |
Control Descriptor Layer 1 Register, array offset: 0x200, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL1 |
Control Descriptor Layer 1 Register, array offset: 0x200, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL1 |
Control Descriptor Layer 1 Register, array offset: 0x200, array step: 0x40
| __IO uint32_t LCDIFV2_Type::CTRLDESCL2 |
Control Descriptor Layer 2 Register, array offset: 0x204, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL2 |
Control Descriptor Layer 2 Register, array offset: 0x204, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL2 |
Control Descriptor Layer 2 Register, array offset: 0x204, array step: 0x40
| __IO uint32_t LCDIFV2_Type::CTRLDESCL3 |
Control Descriptor Layer 3 Register, array offset: 0x208, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL3 |
Control Descriptor Layer 3 Register, array offset: 0x208, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL3 |
Control Descriptor Layer 3 Register, array offset: 0x208, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL4 |
Control Descriptor Layer 4 Register, array offset: 0x20C, array step: 0x40
| __IO uint32_t LCDIFV2_Type::CTRLDESCL4 |
Control Descriptor Layer 4 Register, array offset: 0x20C, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL4 |
Control Descriptor Layer 4 Register, array offset: 0x20C, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL5 |
Control Descriptor Layer 5 Register, array offset: 0x210, array step: 0x40
| __IO uint32_t LCDIFV2_Type::CTRLDESCL5 |
Control Descriptor Layer 5 Register, array offset: 0x210, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL5 |
Control Descriptor Layer 5 Register, array offset: 0x210, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL6 |
Control Descriptor Layer 6 Register, array offset: 0x214, array step: 0x40
| __IO uint32_t LCDIFV2_Type::CTRLDESCL6 |
Control Descriptor Layer 6 Register, array offset: 0x214, array step: 0x40
| __IO uint32_t { ... } ::CTRLDESCL6 |
Control Descriptor Layer 6 Register, array offset: 0x214, array step: 0x40
| __IO uint32_t LCDIF_Type::CUR_BUF |
LCD Interface Current Buffer Address Register, offset: 0x40
| __IO uint32_t ADC_Type::CV |
Compare value register, offset: 0x50
Compare Value Register, array offset: 0x200, array step: 0x4
| __I uint32_t PIT_Type::CVAL |
Current Timer Value Register, array offset: 0x104, array step: 0x10
| __I uint32_t { ... } ::CVAL |
Current Timer Value Register, array offset: 0x104, array step: 0x10
| __I uint32_t { ... } ::CVAL |
Current Timer Value Register, array offset: 0x104, array step: 0x10
| __I uint32_t { ... } ::CVAL |
Current Timer Value Register, array offset: 0x104, array step: 0x10
| __I uint16_t PWM_Type::CVAL0 |
Capture Value 0 Register, array offset: 0x40, array step: 0x60
| __I uint16_t { ... } ::CVAL0 |
Capture Value 0 Register, array offset: 0x40, array step: 0x60
| __I uint16_t { ... } ::CVAL0 |
Capture Value 0 Register, array offset: 0x40, array step: 0x60
| __I uint16_t { ... } ::CVAL0 |
Capture Value 0 Register, array offset: 0x40, array step: 0x60
| __I uint16_t { ... } ::CVAL0CYC |
Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60
| __I uint16_t PWM_Type::CVAL0CYC |
Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60
| __I uint16_t { ... } ::CVAL0CYC |
Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60
| __I uint16_t { ... } ::CVAL0CYC |
Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60
| __I uint16_t { ... } ::CVAL1 |
Capture Value 1 Register, array offset: 0x44, array step: 0x60
| __I uint16_t PWM_Type::CVAL1 |
Capture Value 1 Register, array offset: 0x44, array step: 0x60
| __I uint16_t { ... } ::CVAL1 |
Capture Value 1 Register, array offset: 0x44, array step: 0x60
| __I uint16_t { ... } ::CVAL1 |
Capture Value 1 Register, array offset: 0x44, array step: 0x60
| __I uint16_t PWM_Type::CVAL1CYC |
Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60
| __I uint16_t { ... } ::CVAL1CYC |
Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60
| __I uint16_t { ... } ::CVAL1CYC |
Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60
| __I uint16_t { ... } ::CVAL1CYC |
Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60
| __I uint16_t PWM_Type::CVAL2 |
Capture Value 2 Register, array offset: 0x48, array step: 0x60
| __I uint16_t { ... } ::CVAL2 |
Capture Value 2 Register, array offset: 0x48, array step: 0x60
| __I uint16_t { ... } ::CVAL2 |
Capture Value 2 Register, array offset: 0x48, array step: 0x60
| __I uint16_t { ... } ::CVAL2 |
Capture Value 2 Register, array offset: 0x48, array step: 0x60
| __I uint16_t PWM_Type::CVAL2CYC |
Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60
| __I uint16_t { ... } ::CVAL2CYC |
Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60
| __I uint16_t { ... } ::CVAL2CYC |
Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60
| __I uint16_t { ... } ::CVAL2CYC |
Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60
| __I uint16_t PWM_Type::CVAL3 |
Capture Value 3 Register, array offset: 0x4C, array step: 0x60
| __I uint16_t { ... } ::CVAL3 |
Capture Value 3 Register, array offset: 0x4C, array step: 0x60
| __I uint16_t { ... } ::CVAL3 |
Capture Value 3 Register, array offset: 0x4C, array step: 0x60
| __I uint16_t { ... } ::CVAL3 |
Capture Value 3 Register, array offset: 0x4C, array step: 0x60
| __I uint16_t PWM_Type::CVAL3CYC |
Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60
| __I uint16_t { ... } ::CVAL3CYC |
Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60
| __I uint16_t { ... } ::CVAL3CYC |
Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60
| __I uint16_t { ... } ::CVAL3CYC |
Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60
| __I uint16_t PWM_Type::CVAL4 |
Capture Value 4 Register, array offset: 0x50, array step: 0x60
| __I uint16_t { ... } ::CVAL4 |
Capture Value 4 Register, array offset: 0x50, array step: 0x60
| __I uint16_t { ... } ::CVAL4 |
Capture Value 4 Register, array offset: 0x50, array step: 0x60
| __I uint16_t { ... } ::CVAL4 |
Capture Value 4 Register, array offset: 0x50, array step: 0x60
| __I uint16_t { ... } ::CVAL4CYC |
Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60
| __I uint16_t PWM_Type::CVAL4CYC |
Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60
| __I uint16_t { ... } ::CVAL4CYC |
Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60
| __I uint16_t { ... } ::CVAL4CYC |
Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60
| __I uint16_t PWM_Type::CVAL5 |
Capture Value 5 Register, array offset: 0x54, array step: 0x60
| __I uint16_t { ... } ::CVAL5 |
Capture Value 5 Register, array offset: 0x54, array step: 0x60
| __I uint16_t { ... } ::CVAL5 |
Capture Value 5 Register, array offset: 0x54, array step: 0x60
| __I uint16_t { ... } ::CVAL5 |
Capture Value 5 Register, array offset: 0x54, array step: 0x60
| __I uint16_t PWM_Type::CVAL5CYC |
Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60
| __I uint16_t { ... } ::CVAL5CYC |
Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60
| __I uint16_t { ... } ::CVAL5CYC |
Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60
| __I uint16_t { ... } ::CVAL5CYC |
Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60
| __IO uint32_t EMVSIM_Type::CWT_VAL |
Character Wait Time Value Register, offset: 0x38
| __I uint32_t FLEXRAM_Type::D0TCM_ECC_MULTI_ERROR_ADDR |
D0TCM multi-bit ECC Error Address Register, offset: 0x6C
| __I uint32_t FLEXRAM_Type::D0TCM_ECC_MULTI_ERROR_DATA |
D0TCM multi-bit ECC Error Data Register, offset: 0x70
| __I uint32_t FLEXRAM_Type::D0TCM_ECC_MULTI_ERROR_INFO |
D0TCM multi-bit ECC Error Information Register, offset: 0x68
| __I uint32_t FLEXRAM_Type::D0TCM_ECC_SINGLE_ERROR_ADDR |
D0TCM single-bit ECC Error Address Register, offset: 0x60
| __I uint32_t FLEXRAM_Type::D0TCM_ECC_SINGLE_ERROR_DATA |
D0TCM single-bit ECC Error Data Register, offset: 0x64
| __I uint32_t FLEXRAM_Type::D0TCM_ECC_SINGLE_ERROR_INFO |
D0TCM single-bit ECC Error Information Register, offset: 0x5C
| __I uint32_t FLEXRAM_Type::D1TCM_ECC_MULTI_ERROR_ADDR |
D1TCM multi-bit ECC Error Address Register, offset: 0x84
| __I uint32_t FLEXRAM_Type::D1TCM_ECC_MULTI_ERROR_DATA |
D1TCM multi-bit ECC Error Data Register, offset: 0x88
| __I uint32_t FLEXRAM_Type::D1TCM_ECC_MULTI_ERROR_INFO |
D1TCM multi-bit ECC Error Information Register, offset: 0x80
| __I uint32_t FLEXRAM_Type::D1TCM_ECC_SINGLE_ERROR_ADDR |
D1TCM single-bit ECC Error Address Register, offset: 0x78
| __I uint32_t FLEXRAM_Type::D1TCM_ECC_SINGLE_ERROR_DATA |
D1TCM single-bit ECC Error Data Register, offset: 0x7C
| __I uint32_t FLEXRAM_Type::D1TCM_ECC_SINGLE_ERROR_INFO |
D1TCM single-bit ECC Error Information Register, offset: 0x74
| __IO uint8_t CMP_Type::DACCR |
DAC Control Register, offset: 0x4
| __IO uint32_t DMA_Type::DADDR |
TCD Destination Address, array offset: 0x1010, array step: 0x20
| __IO uint32_t { ... } ::DADDR |
TCD Destination Address, array offset: 0x1010, array step: 0x20
| __IO uint32_t { ... } ::DADDR |
TCD Destination Address, array offset: 0x1010, array step: 0x20
| __IO uint32_t { ... } ::DADDR |
TCD Destination Address, array offset: 0x1010, array step: 0x20
| __IO uint32_t CAAM_Type::DAR |
DECO Availability Register, offset: 0x120
| __IO uint32_t LPUART_Type::DATA |
LPUART Data Register, offset: 0x1C
| __IO uint32_t OCOTP_Type::DATA |
OTP Controller Write Data Register, offset: 0x20
| __O uint32_t DAC_Type::DATA |
DAC Data Register, offset: 0x8
| __IO uint32_t USDHC_Type::DATA_BUFF_ACC_PORT |
Data Buffer Access Port, offset: 0x20
| __I uint32_t PDM_Type::DATACH |
PDM Output Result Register, array offset: 0x24, array step: 0x4
| __I uint32_t CAN_Type::DBG1 |
Debug 1 register, offset: 0x58
| __I uint32_t CAN_Type::DBG2 |
Debug 2 register, offset: 0x5C
| __I uint32_t DCP_Type::DBGDATA |
DCP debug data register, offset: 0x410
| __IO uint32_t DCP_Type::DBGSELECT |
DCP debug select register, offset: 0x400
| __IO uint32_t SEMC_Type::DBICR0 |
DBI-B control register 0, offset: 0x80
DBI-B Control Register 0, offset: 0x80
| __IO uint32_t SEMC_Type::DBICR1 |
DBI-B control register 1, offset: 0x84
DBI-B Control Register 1, offset: 0x84
| __IO uint32_t SEMC_Type::DBICR2 |
DBI-B Control Register 2, offset: 0x88
| __IO uint32_t PDM_Type::DC_CTRL |
PDM DC Remover Control register, offset: 0x64
| __I uint32_t USB_Type::DCCPARAMS |
Device Controller Capability Parameters, offset: 0x124
| __IO uint32_t SEMC_Type::DCCR |
Delay Chain Control Register, offset: 0x150
| __IO uint8_t DMA_Type::DCHPRI0 |
Channel Priority, offset: 0x103
| __IO uint8_t DMA_Type::DCHPRI1 |
Channel Priority, offset: 0x102
| __IO uint8_t DMA_Type::DCHPRI10 |
Channel Priority, offset: 0x109
| __IO uint8_t DMA_Type::DCHPRI11 |
Channel Priority, offset: 0x108
| __IO uint8_t DMA_Type::DCHPRI12 |
Channel Priority, offset: 0x10F
| __IO uint8_t DMA_Type::DCHPRI13 |
Channel Priority, offset: 0x10E
| __IO uint8_t DMA_Type::DCHPRI14 |
Channel Priority, offset: 0x10D
| __IO uint8_t DMA_Type::DCHPRI15 |
Channel Priority, offset: 0x10C
| __IO uint8_t DMA_Type::DCHPRI16 |
Channel Priority, offset: 0x113
| __IO uint8_t DMA_Type::DCHPRI17 |
Channel Priority, offset: 0x112
| __IO uint8_t DMA_Type::DCHPRI18 |
Channel Priority, offset: 0x111
| __IO uint8_t DMA_Type::DCHPRI19 |
Channel Priority, offset: 0x110
| __IO uint8_t DMA_Type::DCHPRI2 |
Channel Priority, offset: 0x101
| __IO uint8_t DMA_Type::DCHPRI20 |
Channel Priority, offset: 0x117
| __IO uint8_t DMA_Type::DCHPRI21 |
Channel Priority, offset: 0x116
| __IO uint8_t DMA_Type::DCHPRI22 |
Channel Priority, offset: 0x115
| __IO uint8_t DMA_Type::DCHPRI23 |
Channel Priority, offset: 0x114
| __IO uint8_t DMA_Type::DCHPRI24 |
Channel Priority, offset: 0x11B
| __IO uint8_t DMA_Type::DCHPRI25 |
Channel Priority, offset: 0x11A
| __IO uint8_t DMA_Type::DCHPRI26 |
Channel Priority, offset: 0x119
| __IO uint8_t DMA_Type::DCHPRI27 |
Channel Priority, offset: 0x118
| __IO uint8_t DMA_Type::DCHPRI28 |
Channel Priority, offset: 0x11F
| __IO uint8_t DMA_Type::DCHPRI29 |
Channel Priority, offset: 0x11E
| __IO uint8_t DMA_Type::DCHPRI3 |
Channel Priority, offset: 0x100
| __IO uint8_t DMA_Type::DCHPRI30 |
Channel Priority, offset: 0x11D
| __IO uint8_t DMA_Type::DCHPRI31 |
Channel Priority, offset: 0x11C
| __IO uint8_t DMA_Type::DCHPRI4 |
Channel Priority, offset: 0x107
| __IO uint8_t DMA_Type::DCHPRI5 |
Channel Priority, offset: 0x106
| __IO uint8_t DMA_Type::DCHPRI6 |
Channel Priority, offset: 0x105
| __IO uint8_t DMA_Type::DCHPRI7 |
Channel Priority, offset: 0x104
| __IO uint8_t DMA_Type::DCHPRI8 |
Channel Priority, offset: 0x10B
| __IO uint8_t DMA_Type::DCHPRI9 |
Channel Priority, offset: 0x10A
| __IO uint32_t DCIC_Type::DCICC |
DCIC Control Register, offset: 0x0
| __IO uint32_t DCIC_Type::DCICIC |
DCIC Interrupt Control Register, offset: 0x4
| __IO uint32_t DCIC_Type::DCICRC |
DCIC ROI Config Register, array offset: 0x10, array step: 0x10
| __IO uint32_t { ... } ::DCICRC |
DCIC ROI Config Register, array offset: 0x10, array step: 0x10
| __IO uint32_t { ... } ::DCICRC |
DCIC ROI Config Register, array offset: 0x10, array step: 0x10
| __I uint32_t { ... } ::DCICRCS |
DCIC ROI Calculated Signature Register, array offset: 0x1C, array step: 0x10
| __I uint32_t DCIC_Type::DCICRCS |
DCIC ROI Calculated Signature Register, array offset: 0x1C, array step: 0x10
| __I uint32_t { ... } ::DCICRCS |
DCIC ROI Calculated Signature Register, array offset: 0x1C, array step: 0x10
| __IO uint32_t DCIC_Type::DCICRRS |
DCIC ROI Reference Signature Register, array offset: 0x18, array step: 0x10
| __IO uint32_t { ... } ::DCICRRS |
DCIC ROI Reference Signature Register, array offset: 0x18, array step: 0x10
| __IO uint32_t { ... } ::DCICRRS |
DCIC ROI Reference Signature Register, array offset: 0x18, array step: 0x10
| __IO uint32_t DCIC_Type::DCICRS |
DCIC ROI Size Register, array offset: 0x14, array step: 0x10
| __IO uint32_t { ... } ::DCICRS |
DCIC ROI Size Register, array offset: 0x14, array step: 0x10
| __IO uint32_t { ... } ::DCICRS |
DCIC ROI Size Register, array offset: 0x14, array step: 0x10
| __IO uint32_t DCIC_Type::DCICS |
DCIC Status Register, offset: 0x8
| __I uint16_t USB_Type::DCIVERSION |
Device Controller Interface Version, offset: 0x120
| __I uint64_t CAAM_Type::DDAR |
DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C
| __I uint64_t { ... } ::DDAR |
DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C
| __I uint64_t { ... } ::DDAR |
DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C
| __I uint32_t { ... } ::DDDR |
DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C
| __I uint32_t CAAM_Type::DDDR |
DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C
| __I uint32_t { ... } ::DDDR |
DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C
| __I uint32_t CAAM_Type::DDDR_LS |
DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C
| __I uint32_t { ... } ::DDDR_LS |
DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C
| __I uint32_t { ... } ::DDDR_LS |
DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C
| __I uint32_t CAAM_Type::DDDR_MS |
DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C
| __I uint32_t { ... } ::DDDR_MS |
DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C
| __I uint32_t { ... } ::DDDR_MS |
DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C
| __IO uint32_t { ... } ::DDESB[64] |
DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4
| __IO uint32_t CAAM_Type::DDESB[64] |
DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4
| __IO uint32_t { ... } ::DDESB[64] |
DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4
| __I uint64_t { ... } ::DDJP |
DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C
| __I uint64_t CAAM_Type::DDJP |
DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C
| __I uint64_t { ... } ::DDJP |
DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C
| __I uint32_t { ... } ::DDJR |
DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C
| __I uint32_t CAAM_Type::DDJR |
DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C
| __I uint32_t { ... } ::DDJR |
DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C
| __IO uint32_t ADC_Type::DE |
DMA Enable Register, offset: 0x1C
| __I uint32_t USBPHY_Type::DEBUG0_STATUS |
UTMI Debug Status Register 0, offset: 0x60
| __IO uint32_t USBPHY_Type::DEBUG1 |
UTMI Debug Status Register 1, offset: 0x70
| __IO uint32_t USBPHY_Type::DEBUG1_CLR |
UTMI Debug Status Register 1, offset: 0x78
| __IO uint32_t USBPHY_Type::DEBUG1_SET |
UTMI Debug Status Register 1, offset: 0x74
| __IO uint32_t USBPHY_Type::DEBUG1_TOG |
UTMI Debug Status Register 1, offset: 0x7C
| __IO uint32_t USBPHY_Type::DEBUG_CLR |
USB PHY Debug Register, offset: 0x58
| __IO uint32_t TSC_Type::DEBUG_MODE |
Debug Mode Register, offset: 0x70
| __IO uint32_t TSC_Type::DEBUG_MODE2 |
Debug Mode Register 2, offset: 0x80
| __IO uint32_t USBPHY_Type::DEBUG_SET |
USB PHY Debug Register, offset: 0x54
| __IO uint32_t USBPHY_Type::DEBUG_TOG |
USB PHY Debug Register, offset: 0x5C
| __IO uint32_t CAAM_Type::DEBUGCTL |
Debug Control Register, offset: 0x58
| __IO uint32_t USBPHY_Type::DEBUGr |
USB PHY Debug Register, offset: 0x50, 'r' suffix has been added to avoid clash with DEBUG symbolic constant
| __IO uint32_t CAAM_Type::DECODID_LS |
DECO0 DID Register - least significant half, array offset: 0xA4, array step: 0x8
| __IO uint32_t { ... } ::DECODID_LS |
DECO0 DID Register - least significant half, array offset: 0xA4, array step: 0x8
| __IO uint32_t { ... } ::DECODID_LS |
DECO0 DID Register - least significant half, array offset: 0xA4, array step: 0x8
| __IO uint32_t { ... } ::DECODID_MS |
DECO0 DID Register - most significant half, array offset: 0xA0, array step: 0x8
| __IO uint32_t CAAM_Type::DECODID_MS |
DECO0 DID Register - most significant half, array offset: 0xA0, array step: 0x8
| __IO uint32_t { ... } ::DECODID_MS |
DECO0 DID Register - most significant half, array offset: 0xA0, array step: 0x8
| __IO uint32_t CAAM_Type::DECORR |
DECO Request Register, offset: 0x9C
| __IO uint32_t CAAM_Type::DECORSR |
DECO Request Source Register, offset: 0x94
| __IO uint32_t LPSPI_Type::DER |
DMA Enable Register, offset: 0x1C
DMA Enable, offset: 0x1C
| __IO uint32_t { ... } ::DESC_ADDR_DOWN |
Descriptor Address Down 0 Register..Descriptor Address Down 15 Register, array offset: 0xC, array step: 0x20
| __IO uint32_t SSARC_LP_Type::DESC_ADDR_DOWN |
Descriptor Address Down 0 Register..Descriptor Address Down 15 Register, array offset: 0xC, array step: 0x20
| __IO uint32_t { ... } ::DESC_ADDR_DOWN |
Descriptor Address Down 0 Register..Descriptor Address Down 15 Register, array offset: 0xC, array step: 0x20
| __IO uint32_t { ... } ::DESC_ADDR_UP |
Descriptor Address Up 0 Register..Descriptor Address Up 15 Register, array offset: 0x8, array step: 0x20
| __IO uint32_t SSARC_LP_Type::DESC_ADDR_UP |
Descriptor Address Up 0 Register..Descriptor Address Up 15 Register, array offset: 0x8, array step: 0x20
| __IO uint32_t { ... } ::DESC_ADDR_UP |
Descriptor Address Up 0 Register..Descriptor Address Up 15 Register, array offset: 0x8, array step: 0x20
| __IO uint32_t { ... } ::DESC_CTRL0 |
Descriptor Control0 0 Register..Descriptor Control0 15 Register, array offset: 0x0, array step: 0x20
| __IO uint32_t SSARC_LP_Type::DESC_CTRL0 |
Descriptor Control0 0 Register..Descriptor Control0 15 Register, array offset: 0x0, array step: 0x20
| __IO uint32_t { ... } ::DESC_CTRL0 |
Descriptor Control0 0 Register..Descriptor Control0 15 Register, array offset: 0x0, array step: 0x20
| __IO uint32_t { ... } ::DESC_CTRL1 |
Descriptor Control1 0 Register..Descriptor Control1 15 Register, array offset: 0x4, array step: 0x20
| __IO uint32_t SSARC_LP_Type::DESC_CTRL1 |
Descriptor Control1 0 Register..Descriptor Control1 15 Register, array offset: 0x4, array step: 0x20
| __IO uint32_t { ... } ::DESC_CTRL1 |
Descriptor Control1 0 Register..Descriptor Control1 15 Register, array offset: 0x4, array step: 0x20
| __IO uint32_t { ... } ::DEVICEADDR |
Device Address, offset: 0x154
| __IO uint32_t USB_Type::DEVICEADDR |
Device Address, offset: 0x154
| __IO uint32_t { ... } ::DEVICEADDR |
Device Address, offset: 0x154
| __IO uint32_t { ... } ::DEVICEADDR |
Device Address, offset: 0x154
| __IO uint32_t { ... } ::DGTR_0 |
DECO0 Gather Table Register 0 Word 0, array offset: 0x80880, array step: index*0xE3C, index2*0x10
| __IO uint32_t CAAM_Type::DGTR_0 |
DECO0 Gather Table Register 0 Word 0, array offset: 0x80880, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DGTR_0 |
DECO0 Gather Table Register 0 Word 0, array offset: 0x80880, array step: index*0xE3C, index2*0x10
| __IO uint32_t CAAM_Type::DGTR_1 |
DECO0 Gather Table Register 0 Word 1, array offset: 0x80884, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DGTR_1 |
DECO0 Gather Table Register 0 Word 1, array offset: 0x80884, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DGTR_1 |
DECO0 Gather Table Register 0 Word 1, array offset: 0x80884, array step: index*0xE3C, index2*0x10
| __IO uint32_t CAAM_Type::DGTR_2 |
DECO0 Gather Table Register 0 Word 2, array offset: 0x80888, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DGTR_2 |
DECO0 Gather Table Register 0 Word 2, array offset: 0x80888, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DGTR_2 |
DECO0 Gather Table Register 0 Word 2, array offset: 0x80888, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DGTR_3 |
DECO0 Gather Table Register 0 Word 3, array offset: 0x8088C, array step: index*0xE3C, index2*0x10
| __IO uint32_t CAAM_Type::DGTR_3 |
DECO0 Gather Table Register 0 Word 3, array offset: 0x8088C, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DGTR_3 |
DECO0 Gather Table Register 0 Word 3, array offset: 0x8088C, array step: index*0xE3C, index2*0x10
| __I uint32_t USB_ANALOG_Type::DIGPROG |
Chip Silicon Version, offset: 0x260
| __IO uint32_t CCM_Type::DIRECT |
Clock source direct control, array offset: 0x5000, array step: 0x20
LPCG direct control, array offset: 0x6000, array step: 0x20
| __IO uint32_t { ... } ::DIRECT |
Clock source direct control, array offset: 0x5000, array step: 0x20
| __IO uint32_t { ... } ::DIRECT |
LPCG direct control, array offset: 0x6000, array step: 0x20
| __IO uint32_t { ... } ::DIRECT |
Clock source direct control, array offset: 0x5000, array step: 0x20
| __IO uint32_t { ... } ::DIRECT |
LPCG direct control, array offset: 0x6000, array step: 0x20
| __IO uint16_t { ... } ::DISMAP[1] |
Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2
| __IO uint16_t { ... } ::DISMAP[1] |
Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2
| __IO uint16_t { ... } ::DISMAP[2] |
Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2
| __IO uint16_t PWM_Type::DISMAP[1] |
Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2
Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2
| __IO uint32_t LCDIFV2_Type::DISP_PARA |
Display Parameter Register, offset: 0x10
| __IO uint32_t LCDIFV2_Type::DISP_SIZE |
Display Size Register, offset: 0x14
| __IO uint32_t EMVSIM_Type::DIVISOR |
Baud Rate Divisor Register, offset: 0xC
| __I uint32_t CAAM_Type::DJQCR_LS |
DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C
| __I uint32_t { ... } ::DJQCR_LS |
DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C
| __I uint32_t { ... } ::DJQCR_LS |
DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C
| __IO uint32_t { ... } ::DJQCR_MS |
DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C
| __IO uint32_t CAAM_Type::DJQCR_MS |
DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C
| __IO uint32_t { ... } ::DJQCR_MS |
DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C
| __IO int32_t { ... } ::DLAST_SGA |
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
| __IO int32_t DMA_Type::DLAST_SGA |
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
| __IO int32_t { ... } ::DLAST_SGA |
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
| __IO int32_t { ... } ::DLAST_SGA |
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
| __IO uint32_t USDHC_Type::DLL_CTRL |
DLL (Delay Line) Control, offset: 0x60
| __I uint32_t USDHC_Type::DLL_STATUS |
DLL Status, offset: 0x64
| __IO uint32_t FLEXSPI_Type::DLLCR |
DLL Control Register 0, array offset: 0xC0, array step: 0x4
| __IO uint32_t SEMC_Type::DLLCR |
DLL Control Register, offset: 0x34
| __IO uint16_t { ... } ::DMA |
Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20
| __IO uint16_t TMR_Type::DMA |
Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20
| __IO uint16_t { ... } ::DMA |
Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20
| __IO uint16_t { ... } ::DMA |
Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20
| __I uint32_t CAAM_Type::DMA0_AID_ENB |
DMA0 AXI ID Enable Register, offset: 0x250
| __IO uint32_t CAAM_Type::DMA0_ARD_LAT |
DMA0 Read Timing Check Latency Register, offset: 0x26C
| __IO uint64_t CAAM_Type::DMA0_ARD_TC |
DMA0 AXI Read Timing Check Register, offset: 0x260
| __IO uint32_t CAAM_Type::DMA0_AWR_LAT |
DMA0 Write Timing Check Latency Register, offset: 0x27C
| __IO uint64_t CAAM_Type::DMA0_AWR_TC |
DMA0 AXI Write Timing Check Register, offset: 0x270
| __I uint32_t { ... } ::DMA_AIDL_MAP_LS |
DMA0_AIDL_MAP_LS, array offset: 0x244, array step: 0x10
| __I uint32_t CAAM_Type::DMA_AIDL_MAP_LS |
DMA0_AIDL_MAP_LS, array offset: 0x244, array step: 0x10
| __I uint32_t { ... } ::DMA_AIDL_MAP_LS |
DMA0_AIDL_MAP_LS, array offset: 0x244, array step: 0x10
| __I uint32_t { ... } ::DMA_AIDL_MAP_MS |
DMA0_AIDL_MAP_MS, array offset: 0x240, array step: 0x10
| __I uint32_t CAAM_Type::DMA_AIDL_MAP_MS |
DMA0_AIDL_MAP_MS, array offset: 0x240, array step: 0x10
| __I uint32_t { ... } ::DMA_AIDL_MAP_MS |
DMA0_AIDL_MAP_MS, array offset: 0x240, array step: 0x10
| __I uint32_t { ... } ::DMA_AIDM_MAP_LS |
DMA0_AIDM_MAP_LS, array offset: 0x24C, array step: 0x10
| __I uint32_t CAAM_Type::DMA_AIDM_MAP_LS |
DMA0_AIDM_MAP_LS, array offset: 0x24C, array step: 0x10
| __I uint32_t { ... } ::DMA_AIDM_MAP_LS |
DMA0_AIDM_MAP_LS, array offset: 0x24C, array step: 0x10
| __I uint32_t { ... } ::DMA_AIDM_MAP_MS |
DMA0_AIDM_MAP_MS, array offset: 0x248, array step: 0x10
| __I uint32_t CAAM_Type::DMA_AIDM_MAP_MS |
DMA0_AIDM_MAP_MS, array offset: 0x248, array step: 0x10
| __I uint32_t { ... } ::DMA_AIDM_MAP_MS |
DMA0_AIDM_MAP_MS, array offset: 0x248, array step: 0x10
| __IO uint32_t ADC_ETC_Type::DMA_CTRL |
ETC DMA control Register, offset: 0xC
| __I uint32_t CAAM_Type::DMA_STA |
DMA Status Register, offset: 0x50C
| __I uint32_t CAAM_Type::DMA_X_AID_11_8_MAP |
DMA_X_AID_11_8_MAP, offset: 0x51C
| __I uint32_t CAAM_Type::DMA_X_AID_15_0_EN |
DMA_X AXI ID Map Enable Register, offset: 0x524
| __I uint32_t CAAM_Type::DMA_X_AID_15_12_MAP |
DMA_X_AID_15_12_MAP, offset: 0x518
| __I uint32_t CAAM_Type::DMA_X_AID_3_0_MAP |
DMA_X_AID_3_0_MAP, offset: 0x514
| __I uint32_t CAAM_Type::DMA_X_AID_7_4_MAP |
DMA_X_AID_7_4_MAP, offset: 0x510
| __IO uint32_t CAAM_Type::DMA_X_ARTC_CTL |
DMA_X AXI Read Timing Check Control Register, offset: 0x530
| __IO uint32_t CAAM_Type::DMA_X_ARTC_LAT |
DMA_X Read Timing Check Latency Register, offset: 0x53C
| __IO uint32_t CAAM_Type::DMA_X_ARTC_LC |
DMA_X AXI Read Timing Check Late Count Register, offset: 0x534
| __IO uint32_t CAAM_Type::DMA_X_ARTC_SC |
DMA_X AXI Read Timing Check Sample Count Register, offset: 0x538
| __IO uint32_t CAAM_Type::DMA_X_AWTC_CTL |
DMA_X AXI Write Timing Check Control Register, offset: 0x540
| __IO uint32_t CAAM_Type::DMA_X_AWTC_LAT |
DMA_X Write Timing Check Latency Register, offset: 0x54C
| __IO uint32_t CAAM_Type::DMA_X_AWTC_LC |
DMA_X AXI Write Timing Check Late Count Register, offset: 0x544
| __IO uint32_t CAAM_Type::DMA_X_AWTC_SC |
DMA_X AXI Write Timing Check Sample Count Register, offset: 0x548
| __IO uint32_t ENET_Type::DMACFG |
DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4
| __IO uint16_t PWM_Type::DMAEN |
DMA Enable Register, array offset: 0x28, array step: 0x60
| __IO uint16_t { ... } ::DMAEN |
DMA Enable Register, array offset: 0x28, array step: 0x60
| __IO uint16_t { ... } ::DMAEN |
DMA Enable Register, array offset: 0x28, array step: 0x60
| __IO uint16_t { ... } ::DMAEN |
DMA Enable Register, array offset: 0x28, array step: 0x60
| __IO uint32_t CSI_Type::DMASA_FB1 |
CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28
| __IO uint32_t CSI_Type::DMASA_FB2 |
CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C
| __IO uint32_t CSI_Type::DMASA_STATFIFO |
CSI DMA Start Address Register - for STATFIFO, offset: 0x20
| __IO uint32_t CSI_Type::DMATS_STATFIFO |
CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24
| __IO uint32_t LPSPI_Type::DMR0 |
Data Match Register 0, offset: 0x30
Data Match 0, offset: 0x30
| __IO uint32_t LPSPI_Type::DMR1 |
Data Match Register 1, offset: 0x34
Data Match 1, offset: 0x34
| __IO uint32_t { ... } ::DMTH_LS |
DECO0 Math Register 0_LS..DECO0 Math Register 3_LS, array offset: 0x80844, array step: index*0xE3C, index2*0x8
| __IO uint32_t CAAM_Type::DMTH_LS |
DECO0 Math Register 0_LS..DECO0 Math Register 3_LS, array offset: 0x80844, array step: index*0xE3C, index2*0x8
| __IO uint32_t { ... } ::DMTH_LS |
DECO0 Math Register 0_LS..DECO0 Math Register 3_LS, array offset: 0x80844, array step: index*0xE3C, index2*0x8
| __IO uint32_t { ... } ::DMTH_MS |
DECO0 Math Register 0_MS..DECO0 Math Register 3_MS, array offset: 0x80840, array step: index*0xE3C, index2*0x8
| __IO uint32_t CAAM_Type::DMTH_MS |
DECO0 Math Register 0_MS..DECO0 Math Register 3_MS, array offset: 0x80840, array step: index*0xE3C, index2*0x8
| __IO uint32_t { ... } ::DMTH_MS |
DECO0 Math Register 0_MS..DECO0 Math Register 3_MS, array offset: 0x80840, array step: index*0xE3C, index2*0x8
| __I uint32_t CAAM_Type::DODIDSR |
DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C
| __I uint32_t { ... } ::DODIDSR |
DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C
| __I uint32_t { ... } ::DODIDSR |
DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C
| __IO uint16_t { ... } ::DOFF |
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
| __IO uint16_t DMA_Type::DOFF |
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
| __IO uint16_t { ... } ::DOFF |
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
| __IO uint16_t { ... } ::DOFF |
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
| __IO uint32_t SRC_Type::DOMAIN_DISPLAY |
Slice Domain Config Register, offset: 0x22C
| __IO uint32_t SRC_Type::DOMAIN_M4CORE |
Slice Domain Config Register, offset: 0x28C
| __IO uint32_t SRC_Type::DOMAIN_M4DEBUG |
Slice Domain Config Register, offset: 0x2CC
| __IO uint32_t SRC_Type::DOMAIN_M7CORE |
Slice Domain Config Register, offset: 0x2AC
| __IO uint32_t SRC_Type::DOMAIN_M7DEBUG |
Slice Domain Config Register, offset: 0x2EC
| __IO uint32_t SRC_Type::DOMAIN_MEGA |
Slice Domain Config Register, offset: 0x20C
| __IO uint32_t SRC_Type::DOMAIN_USBPHY1 |
Slice Domain Config Register, offset: 0x30C
| __IO uint32_t SRC_Type::DOMAIN_USBPHY2 |
Slice Domain Config Register, offset: 0x32C
| __IO uint32_t SRC_Type::DOMAIN_WAKEUP |
Slice Domain Config Register, offset: 0x24C
| __IO uint32_t CCM_Type::DOMAINr |
| __IO uint32_t { ... } ::DOMAINr |
Clock source domain control, array offset: 0x5004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h
| __IO uint32_t { ... } ::DOMAINr |
LPCG domain control, array offset: 0x6004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h
| __IO uint32_t { ... } ::DOMAINr |
Clock source domain control, array offset: 0x5004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h
| __IO uint32_t { ... } ::DOMAINr |
LPCG domain control, array offset: 0x6004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h
| __IO uint32_t ADC_ETC_Type::DONE0_1_IRQ |
ETC DONE0 and DONE1 IRQ State Register, offset: 0x4
| __IO uint32_t ADC_ETC_Type::DONE2_3_ERR_IRQ |
ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8
ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register, offset: 0x8
| __I uint32_t CAAM_Type::DOPSTA_LS |
DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C
| __I uint32_t { ... } ::DOPSTA_LS |
DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C
| __I uint32_t { ... } ::DOPSTA_LS |
DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C
| __I uint32_t { ... } ::DOPSTA_MS |
DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C
| __I uint32_t CAAM_Type::DOPSTA_MS |
DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C
| __I uint32_t { ... } ::DOPSTA_MS |
DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C
| __O uint32_t IEE_Type::DPAMS |
AES Mask Generation Seed, offset: 0xC
| __I uint32_t CAAM_Type::DPDIDSR |
DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C
| __I uint32_t { ... } ::DPDIDSR |
DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C
| __I uint32_t { ... } ::DPDIDSR |
DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C
| __IO uint32_t CAAM_Type::DPOVRD |
Protocol Override Register, array offset: 0x80E30, array step: 0xE3C
| __IO uint32_t { ... } ::DPOVRD |
Protocol Override Register, array offset: 0x80E30, array step: 0xE3C
| __IO uint32_t { ... } ::DPOVRD |
Protocol Override Register, array offset: 0x80E30, array step: 0xE3C
| __IO uint32_t GPIO_Type::DR |
GPIO data register, offset: 0x0
| __O uint32_t GPIO_Type::DR_CLEAR |
GPIO data register CLEAR, offset: 0x88
| __O uint32_t GPIO_Type::DR_SET |
GPIO data register SET, offset: 0x84
| __O uint32_t GPIO_Type::DR_TOGGLE |
GPIO data register TOGGLE, offset: 0x8C
| __O uint32_t CAAM_Type::DRR |
DECO Reset Register, offset: 0x124
| __IO uint32_t USDHC_Type::DS_ADDR |
DMA System Address, offset: 0x0
| __I uint64_t { ... } ::DSDP |
DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C
| __I uint64_t CAAM_Type::DSDP |
DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C
| __I uint64_t { ... } ::DSDP |
DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C
| __IO uint32_t CAAM_Type::DSTR_0 |
DECO0 Scatter Table Register 0 Word 0, array offset: 0x80900, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DSTR_0 |
DECO0 Scatter Table Register 0 Word 0, array offset: 0x80900, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DSTR_0 |
DECO0 Scatter Table Register 0 Word 0, array offset: 0x80900, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DSTR_1 |
DECO0 Scatter Table Register 0 Word 1, array offset: 0x80904, array step: index*0xE3C, index2*0x10
| __IO uint32_t CAAM_Type::DSTR_1 |
DECO0 Scatter Table Register 0 Word 1, array offset: 0x80904, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DSTR_1 |
DECO0 Scatter Table Register 0 Word 1, array offset: 0x80904, array step: index*0xE3C, index2*0x10
| __IO uint32_t CAAM_Type::DSTR_2 |
DECO0 Scatter Table Register 0 Word 2, array offset: 0x80908, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DSTR_2 |
DECO0 Scatter Table Register 0 Word 2, array offset: 0x80908, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DSTR_2 |
DECO0 Scatter Table Register 0 Word 2, array offset: 0x80908, array step: index*0xE3C, index2*0x10
| __IO uint32_t CAAM_Type::DSTR_3 |
DECO0 Scatter Table Register 0 Word 3, array offset: 0x8090C, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DSTR_3 |
DECO0 Scatter Table Register 0 Word 3, array offset: 0x8090C, array step: index*0xE3C, index2*0x10
| __IO uint32_t { ... } ::DSTR_3 |
DECO0 Scatter Table Register 0 Word 3, array offset: 0x8090C, array step: index*0xE3C, index2*0x10
| __IO uint32_t FLEXRAM_Type::DTCM_MAGIC_ADDR |
DTCM Magic Address Register, offset: 0x8
| __IO uint16_t { ... } ::DTCNT0 |
Deadtime Count Register 0, array offset: 0x30, array step: 0x60
| __IO uint16_t PWM_Type::DTCNT0 |
Deadtime Count Register 0, array offset: 0x30, array step: 0x60
| __IO uint16_t { ... } ::DTCNT0 |
Deadtime Count Register 0, array offset: 0x30, array step: 0x60
| __IO uint16_t { ... } ::DTCNT0 |
Deadtime Count Register 0, array offset: 0x30, array step: 0x60
| __IO uint16_t { ... } ::DTCNT1 |
Deadtime Count Register 1, array offset: 0x32, array step: 0x60
| __IO uint16_t PWM_Type::DTCNT1 |
Deadtime Count Register 1, array offset: 0x32, array step: 0x60
| __IO uint16_t { ... } ::DTCNT1 |
Deadtime Count Register 1, array offset: 0x32, array step: 0x60
| __IO uint16_t { ... } ::DTCNT1 |
Deadtime Count Register 1, array offset: 0x32, array step: 0x60
| __IO uint16_t PWM_Type::DTSRCSEL |
PWM Source Select Register, offset: 0x186
| __IO uint32_t DMA_Type::EARS |
Enable Asynchronous Request in Stop, offset: 0x44
| __IO uint32_t XECC_Type::ECC_BASE_ADDR0 |
ECC Region 0 Base Address, offset: 0x3C
| __IO uint32_t XECC_Type::ECC_BASE_ADDR1 |
ECC Region 1 Base Address, offset: 0x44
| __IO uint32_t XECC_Type::ECC_BASE_ADDR2 |
ECC Region 2 Base Address, offset: 0x4C
| __IO uint32_t XECC_Type::ECC_BASE_ADDR3 |
ECC Region 3 Base Address, offset: 0x54
| __IO uint32_t XECC_Type::ECC_CTRL |
ECC Control Register, offset: 0x0
| __IO uint32_t XECC_Type::ECC_END_ADDR0 |
ECC Region 0 End Address, offset: 0x40
| __IO uint32_t XECC_Type::ECC_END_ADDR1 |
ECC Region 1 End Address, offset: 0x48
| __IO uint32_t XECC_Type::ECC_END_ADDR2 |
ECC Region 2 End Address, offset: 0x50
| __IO uint32_t XECC_Type::ECC_END_ADDR3 |
ECC Region 3 End Address, offset: 0x58
| __IO uint32_t CAN_Type::ECR |
Error Counter Register, offset: 0x1C
Error Counter, offset: 0x1C
| __IO uint32_t ENET_Type::ECR |
Ethernet Control Register, offset: 0x24
| __IO uint32_t GPIO_Type::EDGE_SEL |
GPIO edge select register, offset: 0x1C
| __IO uint32_t DMA_Type::EEI |
Enable Error Interrupt, offset: 0x14
| __IO uint32_t ENET_Type::EIMR |
Interrupt Mask Register, offset: 0x8
| __IO uint32_t ENET_Type::EIR |
Interrupt Event Register, offset: 0x4
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::ENABLE_MULT_PKTS |
ENABLE_MULT_PKTS, offset: 0x28
| __IO uint16_t { ... } ::ENBL |
Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances
| __IO uint16_t TMR_Type::ENBL |
Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances
| __IO uint16_t { ... } ::ENBL |
Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances
| __IO uint16_t { ... } ::ENBL |
Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances
| __IO uint32_t USB_Type::ENDPTCOMPLETE |
Endpoint Complete, offset: 0x1BC
| __IO uint32_t USB_Type::ENDPTCTRL |
Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4
| __IO uint32_t USB_Type::ENDPTCTRL0 |
Endpoint Control0, offset: 0x1C0
| __IO uint32_t USB_Type::ENDPTFLUSH |
Endpoint Flush, offset: 0x1B4
| __IO uint32_t USB_Type::ENDPTLISTADDR |
Endpoint List Address, offset: 0x158
| __IO uint32_t { ... } ::ENDPTLISTADDR |
Endpoint List Address, offset: 0x158
| __IO uint32_t { ... } ::ENDPTLISTADDR |
Endpoint List Address, offset: 0x158
| __IO uint32_t { ... } ::ENDPTLISTADDR |
Endpoint List Address, offset: 0x158
| __IO uint32_t USB_Type::ENDPTNAK |
Endpoint NAK, offset: 0x178
| __IO uint32_t USB_Type::ENDPTNAKEN |
Endpoint NAK Enable, offset: 0x17C
| __IO uint32_t USB_Type::ENDPTPRIME |
Endpoint Prime, offset: 0x1B0
| __IO uint32_t USB_Type::ENDPTSETUPSTAT |
Endpoint Setup Status, offset: 0x1AC
| __I uint32_t USB_Type::ENDPTSTAT |
Endpoint Status, offset: 0x1B8
| __I uint32_t TRNG_Type::ENT[16] |
Entropy Read Register, array offset: 0x40, array step: 0x4
| __IO uint32_t DMA_Type::ERQ |
Enable Request, offset: 0xC
| __IO uint32_t DMA_Type::ERR |
Error, offset: 0x2C
| __IO uint32_t XECC_Type::ERR_DATA_INJ |
Error Injection On Write Data, offset: 0x10
| __IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH0 |
Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data, offset: 0x10
| __IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH1 |
Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data, offset: 0x1C
| __IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH2 |
Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data, offset: 0x28
| __IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH3 |
Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data, offset: 0x34
| __IO uint32_t MECC_Type::ERR_DATA_INJ_LOW0 |
Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data, offset: 0xC
| __IO uint32_t MECC_Type::ERR_DATA_INJ_LOW1 |
Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data, offset: 0x18
| __IO uint32_t MECC_Type::ERR_DATA_INJ_LOW2 |
Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data, offset: 0x24
| __IO uint32_t MECC_Type::ERR_DATA_INJ_LOW3 |
Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data, offset: 0x30
| __IO uint32_t XECC_Type::ERR_ECC_INJ |
Error Injection On ECC Code of Write Data, offset: 0x14
| __IO uint32_t MECC_Type::ERR_ECC_INJ0 |
Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data, offset: 0x14
| __IO uint32_t MECC_Type::ERR_ECC_INJ1 |
Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data, offset: 0x20
| __IO uint32_t MECC_Type::ERR_ECC_INJ2 |
Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data, offset: 0x2C
| __IO uint32_t MECC_Type::ERR_ECC_INJ3 |
Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data, offset: 0x38
| __IO uint32_t MECC_Type::ERR_SIG_EN |
Error Interrupt Enable Register, offset: 0x8
| __IO uint32_t XECC_Type::ERR_SIG_EN |
Error Interrupt Enable Register, offset: 0xC
| __IO uint32_t MECC_Type::ERR_STAT_EN |
Error Interrupt Status Enable Register, offset: 0x4
| __IO uint32_t XECC_Type::ERR_STAT_EN |
Error Interrupt Status Enable Register, offset: 0x8
| __IO uint32_t MECC_Type::ERR_STATUS |
Error Interrupt Status Register, offset: 0x0
| __IO uint32_t XECC_Type::ERR_STATUS |
Error Interrupt Status Register, offset: 0x4
| __IO uint32_t CAN_Type::ERRIAR |
Error Injection Address register, offset: 0xAE4
| __IO uint32_t CAN_Type::ERRIDPR |
Error Injection Data Pattern register, offset: 0xAE8
| __IO uint32_t CAN_Type::ERRIPPR |
Error Injection Parity Pattern register, offset: 0xAEC
| __IO uint32_t CAN_Type::ERRSR |
Error Status register, offset: 0xAFC
| __I uint32_t DMA_Type::ES |
Error Status, offset: 0x4
| __IO uint32_t CAN_Type::ESR1 |
Error and Status 1 Register, offset: 0x20
Error and Status 1 register, offset: 0x20
| __I uint32_t CAN_Type::ESR2 |
Error and Status 2 Register, offset: 0x38
Error and Status 2 register, offset: 0x38
| __I uint32_t CAAM_Type::FADID |
Fault Address DID Register, offset: 0xFC8
| __I uint32_t CAAM_Type::FADID_DC01 |
Fault Address DID Register, offset: 0x80FC8
| __I uint32_t { ... } ::FADID_JR |
Fault Address DID Register, array offset: 0x10FC8, array step: 0x10000
| __I uint32_t CAAM_Type::FADID_JR |
Fault Address DID Register, array offset: 0x10FC8, array step: 0x10000
| __I uint32_t { ... } ::FADID_JR |
Fault Address DID Register, array offset: 0x10FC8, array step: 0x10000
| __I uint32_t CAAM_Type::FADID_RTIC |
Fault Address DID Register, offset: 0x60FC8
| __I uint32_t CAAM_Type::FADR |
Fault Address Detail Register, offset: 0xFCC
| __I uint32_t MCM_Type::FADR |
Fault address register, offset: 0x20
| __I uint32_t CAAM_Type::FADR_DC01 |
Fault Address Detail Register, offset: 0x80FCC
| __I uint32_t { ... } ::FADR_JR |
Fault Address Detail Register, array offset: 0x10FCC, array step: 0x10000
| __I uint32_t CAAM_Type::FADR_JR |
Fault Address Detail Register, array offset: 0x10FCC, array step: 0x10000
| __I uint32_t { ... } ::FADR_JR |
Fault Address Detail Register, array offset: 0x10FCC, array step: 0x10000
| __I uint32_t CAAM_Type::FADR_RTIC |
Fault Address Detail Register, offset: 0x60FCC
| __I uint64_t CAAM_Type::FAR |
Fault Address Register, offset: 0xFC0
| __I uint64_t CAAM_Type::FAR_DC01 |
Fault Address Register, offset: 0x80FC0
| __I uint64_t { ... } ::FAR_JR |
Fault Address Register, array offset: 0x10FC0, array step: 0x10000
| __I uint64_t CAAM_Type::FAR_JR |
Fault Address Register, array offset: 0x10FC0, array step: 0x10000
| __I uint64_t { ... } ::FAR_JR |
Fault Address Register, array offset: 0x10FC0, array step: 0x10000
| __I uint64_t CAAM_Type::FAR_RTIC |
Fault Address Register, offset: 0x60FC0
| __I uint32_t MCM_Type::FATR |
Fault attributes register, offset: 0x24
| __IO uint32_t CSI_Type::FBUF_PARA |
CSI Frame Buffer Parameter Register, offset: 0x30
| __IO uint32_t LPSPI_Type::FCR |
The FIFO Control register contains the RXWATER and TXWATER control fields., offset: 0x58
FIFO Control, offset: 0x58
| __IO uint16_t PWM_Type::FCTRL |
Fault Control Register, offset: 0x18C
| __IO uint32_t ADC_Type::FCTRL |
LPADC FIFO Control Register, offset: 0x30
| __IO uint16_t PWM_Type::FCTRL2 |
Fault Control 2 Register, offset: 0x194
| __IO uint32_t CAN_Type::FDCBT |
CAN FD Bit Timing register, offset: 0xC04
| __I uint32_t CAN_Type::FDCRC |
CAN FD CRC register, offset: 0xC08
| __IO uint32_t CAN_Type::FDCTRL |
CAN FD Control register, offset: 0xC00
| __I uint32_t MCM_Type::FDR |
Fault data register, offset: 0x28
| __IO uint16_t PWM_Type::FFILT |
Fault Filter Register, offset: 0x190
| __IO uint32_t LPUART_Type::FIFO |
LPUART FIFO Register, offset: 0x28
| __IO uint32_t PDM_Type::FIFO_CTRL |
PDM FIFO Control register, offset: 0x10
| __IO uint32_t PDM_Type::FIFO_STAT |
PDM FIFO Status register, offset: 0x14
| __IO uint16_t ENC_Type::FILT |
Input Filter Register, offset: 0x2
| __IO uint16_t { ... } ::FILT |
Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20
| __IO uint16_t TMR_Type::FILT |
Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20
| __IO uint16_t { ... } ::FILT |
Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20
| __IO uint16_t { ... } ::FILT |
Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20
| __IO uint32_t CDOG_Type::FLAGS |
Flags, offset: 0x18
| __IO uint32_t FLEXRAM_Type::FLEXRAM_CTRL |
FlexRAM feature Control register, offset: 0x108
| __IO uint32_t TSC_Type::FLOW_CONTROL |
Flow Control, offset: 0x20
| __IO uint32_t FLEXSPI_Type::FLSHCR0 |
Flash Control Register 0, array offset: 0x60, array step: 0x4
| __IO uint32_t FLEXSPI_Type::FLSHCR1 |
Flash Control Register 1, array offset: 0x70, array step: 0x4
| __IO uint32_t FLEXSPI_Type::FLSHCR2 |
Flash Control Register 2, array offset: 0x80, array step: 0x4
| __IO uint32_t FLEXSPI_Type::FLSHCR4 |
Flash Control Register 4, offset: 0x94
| __O uint32_t USDHC_Type::FORCE_EVENT |
Force Event, offset: 0x50
| __IO uint8_t CMP_Type::FPR |
CMP Filter Period Register, offset: 0x2
| __IO uint16_t { ... } ::FRACVAL1 |
Fractional Value Register 1, array offset: 0xC, array step: 0x60
| __IO uint16_t PWM_Type::FRACVAL1 |
Fractional Value Register 1, array offset: 0xC, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL1 |
Fractional Value Register 1, array offset: 0xC, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL1 |
Fractional Value Register 1, array offset: 0xC, array step: 0x60
| __IO uint16_t PWM_Type::FRACVAL2 |
Fractional Value Register 2, array offset: 0x10, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL2 |
Fractional Value Register 2, array offset: 0x10, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL2 |
Fractional Value Register 2, array offset: 0x10, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL2 |
Fractional Value Register 2, array offset: 0x10, array step: 0x60
| __IO uint16_t PWM_Type::FRACVAL3 |
Fractional Value Register 3, array offset: 0x14, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL3 |
Fractional Value Register 3, array offset: 0x14, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL3 |
Fractional Value Register 3, array offset: 0x14, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL3 |
Fractional Value Register 3, array offset: 0x14, array step: 0x60
| __IO uint16_t PWM_Type::FRACVAL4 |
Fractional Value Register 4, array offset: 0x18, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL4 |
Fractional Value Register 4, array offset: 0x18, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL4 |
Fractional Value Register 4, array offset: 0x18, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL4 |
Fractional Value Register 4, array offset: 0x18, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL5 |
Fractional Value Register 5, array offset: 0x1C, array step: 0x60
| __IO uint16_t PWM_Type::FRACVAL5 |
Fractional Value Register 5, array offset: 0x1C, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL5 |
Fractional Value Register 5, array offset: 0x1C, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL5 |
Fractional Value Register 5, array offset: 0x1C, array step: 0x60
| __IO uint16_t { ... } ::FRCTRL |
Fractional Control Register, array offset: 0x20, array step: 0x60
| __IO uint16_t PWM_Type::FRCTRL |
Fractional Control Register, array offset: 0x20, array step: 0x60
| __IO uint16_t { ... } ::FRCTRL |
Fractional Control Register, array offset: 0x20, array step: 0x60
| __IO uint16_t { ... } ::FRCTRL |
Fractional Control Register, array offset: 0x20, array step: 0x60
| __I uint32_t CCM_OBS_Type::FREQUENCY_CURRENT |
Current frequency detected, array offset: 0x40, array step: 0x80
| __I uint32_t { ... } ::FREQUENCY_CURRENT |
Current frequency detected, array offset: 0x40, array step: 0x80
| __I uint32_t { ... } ::FREQUENCY_CURRENT |
Current frequency detected, array offset: 0x40, array step: 0x80
| __I uint32_t { ... } ::FREQUENCY_MAX |
Maximum frequency detected, array offset: 0x48, array step: 0x80
| __I uint32_t CCM_OBS_Type::FREQUENCY_MAX |
Maximum frequency detected, array offset: 0x48, array step: 0x80
| __I uint32_t { ... } ::FREQUENCY_MAX |
Maximum frequency detected, array offset: 0x48, array step: 0x80
| __I uint32_t { ... } ::FREQUENCY_MIN |
Minimum frequency detected, array offset: 0x44, array step: 0x80
| __I uint32_t CCM_OBS_Type::FREQUENCY_MIN |
Minimum frequency detected, array offset: 0x44, array step: 0x80
| __I uint32_t { ... } ::FREQUENCY_MIN |
Minimum frequency detected, array offset: 0x44, array step: 0x80
| __IO uint32_t USB_Type::FRINDEX |
USB Frame Index, offset: 0x14C
| __I uint32_t TRNG_Type::FRQCNT |
Frequency Count Register, offset: 0x1C
| __I uint32_t { ... } ::FRQCNT |
Frequency Count Register, offset: 0x1C
| __IO uint32_t TRNG_Type::FRQMAX |
Frequency Count Maximum Limit Register, offset: 0x1C
| __IO uint32_t { ... } ::FRQMAX |
Frequency Count Maximum Limit Register, offset: 0x1C
| __IO uint32_t TRNG_Type::FRQMIN |
Frequency Count Minimum Limit Register, offset: 0x18
| __I uint32_t LPSPI_Type::FSR |
FIFO Status Register, offset: 0x5C
FIFO Status, offset: 0x5C
| __IO uint16_t PWM_Type::FSTS |
Fault Status Register, offset: 0x18E
| __IO uint32_t ENET_Type::FTRL |
Frame Truncation Length, offset: 0x1B0
| __IO uint16_t PWM_Type::FTST |
Fault Test Register, offset: 0x192
| __I uint32_t { ... } ::FUSE |
Value of fuse word 0..Value of fuse word 143, array offset: 0x800, array step: 0x10
| __I uint32_t OCOTP_Type::FUSE |
Value of fuse word 0..Value of fuse word 143, array offset: 0x800, array step: 0x10
| __I uint32_t { ... } ::FUSE |
Value of fuse word 0..Value of fuse word 143, array offset: 0x800, array step: 0x10
| __IO uint32_t ENET_Type::GALR |
Descriptor Group Lower Address Register, offset: 0x124
| __IO uint8_t SEMA4_Type::GATE |
Semaphores Gate n Register, array offset: 0x0, array step: 0x1
| __IO uint8_t RDC_SEMAPHORE_Type::GATE |
Gate Register, array offset: 0x0, array step: 0x1
| __IO uint32_t ENET_Type::GAUR |
Descriptor Group Upper Address Register, offset: 0x120
| __IO uint32_t ADC_Type::GC |
General control register, offset: 0x48
| __IO uint32_t IEE_Type::GCFG |
IEE Global Configuration, offset: 0x0
| __IO uint32_t GPIO_Type::GDIR |
GPIO direction register, offset: 0x4
| __IO uint32_t CAN_Type::GFWR |
Glitch Filter Width Registers, offset: 0x9E0
| __IO uint32_t CAN_WRAPPER_Type::GFWR |
Glitch Filter Width Register, offset: 0x9E0
| __IO uint32_t LPUART_Type::GLOBAL |
LPUART Global Register, offset: 0x8
| __IO uint32_t OCOTP_Type::GP1 |
Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660
| __IO uint32_t OCOTP_Type::GP2 |
Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670
| __IO uint32_t OCOTP_Type::GP3 |
Value of OTP Bank4 Word4 (MAC Address), offset: 0x640
| __IO uint32_t EMVSIM_Type::GPCNT0_VAL |
General Purpose Counter 0 Timeout Value Register, offset: 0x44
| __IO uint32_t EMVSIM_Type::GPCNT1_VAL |
General Purpose Counter 1 Timeout Value, offset: 0x48
| __IO uint32_t SRC_Type::GPR |
SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4
SRC General Purpose Register, array offset: 0x14, array step: 0x4
| __IO uint32_t IOMUXC_SNVS_GPR_Type::GPR |
GPR0 General Purpose Register, array offset: 0x0, array step: 0x4
| __IO uint32_t IOMUXC_GPR_Type::GPR0 |
GPR0 General Purpose Register, offset: 0x0
| uint32_t IOMUXC_SNVS_GPR_Type::GPR0 |
GPR0 General Purpose Register, offset: 0x0
| __IO uint32_t IOMUXC_GPR_Type::GPR0 |
GPR0 General Purpose Register, offset: 0x0
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR0 |
GPR0 General Purpose Register, offset: 0x0
| __IO uint32_t IOMUXC_GPR_Type::GPR1 |
GPR1 General Purpose Register, offset: 0x4
| uint32_t IOMUXC_SNVS_GPR_Type::GPR1 |
GPR1 General Purpose Register, offset: 0x4
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR1 |
GPR1 General Purpose Register, offset: 0x4
| __IO uint32_t IOMUXC_GPR_Type::GPR10 |
GPR10 General Purpose Register, offset: 0x28
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR10 |
GPR10 General Purpose Register, offset: 0x28
| __IO uint32_t IOMUXC_GPR_Type::GPR11 |
GPR11 General Purpose Register, offset: 0x2C
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR11 |
GPR11 General Purpose Register, offset: 0x2C
| __IO uint32_t IOMUXC_GPR_Type::GPR12 |
GPR12 General Purpose Register, offset: 0x30
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR12 |
GPR12 General Purpose Register, offset: 0x30
| __IO uint32_t IOMUXC_GPR_Type::GPR13 |
GPR13 General Purpose Register, offset: 0x34
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR13 |
GPR13 General Purpose Register, offset: 0x34
| __IO uint32_t IOMUXC_GPR_Type::GPR14 |
GPR14 General Purpose Register, offset: 0x38
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR14 |
GPR14 General Purpose Register, offset: 0x38
| __IO uint32_t IOMUXC_GPR_Type::GPR15 |
GPR15 General Purpose Register, offset: 0x3C
| __IO uint32_t IOMUXC_GPR_Type::GPR15 |
GPR15 General Purpose Register, offset: 0x3C
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR15 |
GPR15 General Purpose Register, offset: 0x3C
| __IO uint32_t IOMUXC_GPR_Type::GPR16 |
GPR16 General Purpose Register, offset: 0x40
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR16 |
GPR16 General Purpose Register, offset: 0x40
| __IO uint32_t IOMUXC_GPR_Type::GPR17 |
GPR17 General Purpose Register, offset: 0x44
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR17 |
GPR17 General Purpose Register, offset: 0x44
| __IO uint32_t IOMUXC_GPR_Type::GPR18 |
GPR18 General Purpose Register, offset: 0x48
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR18 |
GPR18 General Purpose Register, offset: 0x48
| __IO uint32_t IOMUXC_GPR_Type::GPR19 |
GPR19 General Purpose Register, offset: 0x4C
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR19 |
GPR19 General Purpose Register, offset: 0x4C
| __IO uint32_t IOMUXC_GPR_Type::GPR2 |
GPR2 General Purpose Register, offset: 0x8
| uint32_t IOMUXC_SNVS_GPR_Type::GPR2 |
GPR2 General Purpose Register, offset: 0x8
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR2 |
GPR2 General Purpose Register, offset: 0x8
| __IO uint32_t IOMUXC_GPR_Type::GPR20 |
GPR20 General Purpose Register, offset: 0x50
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR20 |
GPR20 General Purpose Register, offset: 0x50
| __IO uint32_t IOMUXC_GPR_Type::GPR21 |
GPR21 General Purpose Register, offset: 0x54
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR21 |
GPR21 General Purpose Register, offset: 0x54
| __IO uint32_t IOMUXC_GPR_Type::GPR22 |
GPR22 General Purpose Register, offset: 0x58
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR22 |
GPR22 General Purpose Register, offset: 0x58
| __IO uint32_t IOMUXC_GPR_Type::GPR23 |
GPR23 General Purpose Register, offset: 0x5C
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR23 |
GPR23 General Purpose Register, offset: 0x5C
| __IO uint32_t IOMUXC_GPR_Type::GPR24 |
GPR24 General Purpose Register, offset: 0x60
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR24 |
GPR24 General Purpose Register, offset: 0x60
| __IO uint32_t IOMUXC_GPR_Type::GPR25 |
GPR25 General Purpose Register, offset: 0x64
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR25 |
GPR25 General Purpose Register, offset: 0x64
| __IO uint32_t IOMUXC_GPR_Type::GPR26 |
GPR26 General Purpose Register, offset: 0x68
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR26 |
GPR26 General Purpose Register, offset: 0x68
| __IO uint32_t IOMUXC_GPR_Type::GPR27 |
GPR27 General Purpose Register, offset: 0x6C
| __IO uint32_t IOMUXC_GPR_Type::GPR28 |
GPR28 General Purpose Register, offset: 0x70
| __IO uint32_t IOMUXC_GPR_Type::GPR29 |
GPR29 General Purpose Register, offset: 0x74
| __IO uint32_t IOMUXC_GPR_Type::GPR3 |
GPR3 General Purpose Register, offset: 0xC
| __IO uint32_t IOMUXC_SNVS_GPR_Type::GPR3 |
GPR3 General Purpose Register, offset: 0xC
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR3 |
GPR3 General Purpose Register, offset: 0xC
| __IO uint32_t IOMUXC_GPR_Type::GPR30 |
GPR30 General Purpose Register, offset: 0x78
| __IO uint32_t IOMUXC_GPR_Type::GPR31 |
GPR31 General Purpose Register, offset: 0x7C
| __IO uint32_t IOMUXC_GPR_Type::GPR32 |
GPR32 General Purpose Register, offset: 0x80
| __IO uint32_t IOMUXC_SNVS_GPR_Type::GPR32 |
GPR32 General Purpose Register, offset: 0x80
| __IO uint32_t IOMUXC_GPR_Type::GPR33 |
GPR33 General Purpose Register, offset: 0x84
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR33 |
GPR33 General Purpose Register, offset: 0x84
| __IO uint32_t IOMUXC_SNVS_GPR_Type::GPR33 |
GPR33 General Purpose Register, offset: 0x84
| __IO uint32_t IOMUXC_GPR_Type::GPR34 |
GPR34 General Purpose Register, offset: 0x88
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR34 |
GPR34 General Purpose Register, offset: 0x88
| __IO uint32_t IOMUXC_SNVS_GPR_Type::GPR34 |
GPR34 General Purpose Register, offset: 0x88
| __IO uint32_t IOMUXC_GPR_Type::GPR35 |
GPR35 General Purpose Register, offset: 0x8C
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR35 |
GPR35 General Purpose Register, offset: 0x8C
| __IO uint32_t IOMUXC_SNVS_GPR_Type::GPR35 |
GPR35 General Purpose Register, offset: 0x8C
| __IO uint32_t IOMUXC_GPR_Type::GPR36 |
GPR36 General Purpose Register, offset: 0x90
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR36 |
GPR36 General Purpose Register, offset: 0x90
| __IO uint32_t IOMUXC_SNVS_GPR_Type::GPR36 |
GPR36 General Purpose Register, offset: 0x90
| __IO uint32_t IOMUXC_GPR_Type::GPR37 |
GPR37 General Purpose Register, offset: 0x94
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR37 |
GPR37 General Purpose Register, offset: 0x94
| __IO uint32_t IOMUXC_SNVS_GPR_Type::GPR37 |
GPR37 General Purpose Register, offset: 0x94
| __IO uint32_t IOMUXC_GPR_Type::GPR38 |
GPR38 General Purpose Register, offset: 0x98
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR38 |
GPR38 General Purpose Register, offset: 0x98
| __IO uint32_t IOMUXC_GPR_Type::GPR39 |
GPR39 General Purpose Register, offset: 0x9C
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR39 |
GPR39 General Purpose Register, offset: 0x9C
| __IO uint32_t IOMUXC_GPR_Type::GPR4 |
GPR4 General Purpose Register, offset: 0x10
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR4 |
GPR4 General Purpose Register, offset: 0x10
| __IO uint32_t IOMUXC_GPR_Type::GPR40 |
GPR40 General Purpose Register, offset: 0xA0
| __I uint32_t IOMUXC_LPSR_GPR_Type::GPR40 |
GPR40 General Purpose Register, offset: 0xA0
| __IO uint32_t IOMUXC_GPR_Type::GPR41 |
GPR41 General Purpose Register, offset: 0xA4
| __I uint32_t IOMUXC_LPSR_GPR_Type::GPR41 |
GPR41 General Purpose Register, offset: 0xA4
| __IO uint32_t IOMUXC_GPR_Type::GPR42 |
GPR42 General Purpose Register, offset: 0xA8
| __IO uint32_t IOMUXC_GPR_Type::GPR43 |
GPR43 General Purpose Register, offset: 0xAC
| __IO uint32_t IOMUXC_GPR_Type::GPR44 |
GPR44 General Purpose Register, offset: 0xB0
| __IO uint32_t IOMUXC_GPR_Type::GPR45 |
GPR45 General Purpose Register, offset: 0xB4
| __IO uint32_t IOMUXC_GPR_Type::GPR46 |
GPR46 General Purpose Register, offset: 0xB8
| __IO uint32_t IOMUXC_GPR_Type::GPR47 |
GPR47 General Purpose Register, offset: 0xBC
| __IO uint32_t IOMUXC_GPR_Type::GPR48 |
GPR48 General Purpose Register, offset: 0xC0
| __IO uint32_t IOMUXC_GPR_Type::GPR49 |
GPR49 General Purpose Register, offset: 0xC4
| __IO uint32_t IOMUXC_GPR_Type::GPR5 |
GPR5 General Purpose Register, offset: 0x14
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR5 |
GPR5 General Purpose Register, offset: 0x14
| __IO uint32_t IOMUXC_GPR_Type::GPR50 |
GPR50 General Purpose Register, offset: 0xC8
| __IO uint32_t IOMUXC_GPR_Type::GPR51 |
GPR51 General Purpose Register, offset: 0xCC
| __IO uint32_t IOMUXC_GPR_Type::GPR52 |
GPR52 General Purpose Register, offset: 0xD0
| __IO uint32_t IOMUXC_GPR_Type::GPR53 |
GPR53 General Purpose Register, offset: 0xD4
| __IO uint32_t IOMUXC_GPR_Type::GPR54 |
GPR54 General Purpose Register, offset: 0xD8
| __IO uint32_t IOMUXC_GPR_Type::GPR55 |
GPR55 General Purpose Register, offset: 0xDC
| __IO uint32_t IOMUXC_GPR_Type::GPR59 |
GPR59 General Purpose Register, offset: 0xEC
| __IO uint32_t IOMUXC_GPR_Type::GPR6 |
GPR6 General Purpose Register, offset: 0x18
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR6 |
GPR6 General Purpose Register, offset: 0x18
| __IO uint32_t IOMUXC_GPR_Type::GPR62 |
GPR62 General Purpose Register, offset: 0xF8
| __I uint32_t IOMUXC_GPR_Type::GPR63 |
GPR63 General Purpose Register, offset: 0xFC
| __IO uint32_t IOMUXC_GPR_Type::GPR64 |
GPR64 General Purpose Register, offset: 0x100
| __IO uint32_t IOMUXC_GPR_Type::GPR65 |
GPR65 General Purpose Register, offset: 0x104
| __IO uint32_t IOMUXC_GPR_Type::GPR66 |
GPR66 General Purpose Register, offset: 0x108
| __IO uint32_t IOMUXC_GPR_Type::GPR67 |
GPR67 General Purpose Register, offset: 0x10C
| __IO uint32_t IOMUXC_GPR_Type::GPR68 |
GPR68 General Purpose Register, offset: 0x110
| __IO uint32_t IOMUXC_GPR_Type::GPR69 |
GPR69 General Purpose Register, offset: 0x114
| __IO uint32_t IOMUXC_GPR_Type::GPR7 |
GPR7 General Purpose Register, offset: 0x1C
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR7 |
GPR7 General Purpose Register, offset: 0x1C
| __IO uint32_t IOMUXC_GPR_Type::GPR70 |
GPR70 General Purpose Register, offset: 0x118
| __IO uint32_t IOMUXC_GPR_Type::GPR71 |
GPR71 General Purpose Register, offset: 0x11C
| __IO uint32_t IOMUXC_GPR_Type::GPR72 |
GPR72 General Purpose Register, offset: 0x120
| __IO uint32_t IOMUXC_GPR_Type::GPR73 |
GPR73 General Purpose Register, offset: 0x124
| __IO uint32_t IOMUXC_GPR_Type::GPR74 |
GPR74 General Purpose Register, offset: 0x128
| __I uint32_t IOMUXC_GPR_Type::GPR75 |
GPR75 General Purpose Register, offset: 0x12C
| __I uint32_t IOMUXC_GPR_Type::GPR76 |
GPR76 General Purpose Register, offset: 0x130
| __IO uint32_t IOMUXC_GPR_Type::GPR8 |
GPR8 General Purpose Register, offset: 0x20
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR8 |
GPR8 General Purpose Register, offset: 0x20
| __IO uint32_t IOMUXC_GPR_Type::GPR9 |
GPR9 General Purpose Register, offset: 0x24
| __IO uint32_t IOMUXC_GPR_Type::GPR9 |
GPR9 General Purpose Register, offset: 0x24
| __IO uint32_t IOMUXC_LPSR_GPR_Type::GPR9 |
GPR9 General Purpose Register, offset: 0x24
| __IO uint32_t CCM_Type::GPR_PRIVATE1 |
General Purpose Register, offset: 0x4C20
| __IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN |
GPR access control, offset: 0x4C30
| __IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN_CLR |
GPR access control, offset: 0x4C38
| __IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN_SET |
GPR access control, offset: 0x4C34
| __IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN_TOG |
GPR access control, offset: 0x4C3C
| __IO uint32_t CCM_Type::GPR_PRIVATE1_CLR |
General Purpose Register, offset: 0x4C28
| __IO uint32_t CCM_Type::GPR_PRIVATE1_SET |
General Purpose Register, offset: 0x4C24
| __IO uint32_t CCM_Type::GPR_PRIVATE1_TOG |
General Purpose Register, offset: 0x4C2C
| __IO uint32_t CCM_Type::GPR_PRIVATE2 |
General Purpose Register, offset: 0x4C40
| __IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN |
GPR access control, offset: 0x4C50
| __IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN_CLR |
GPR access control, offset: 0x4C58
| __IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN_SET |
GPR access control, offset: 0x4C54
| __IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN_TOG |
GPR access control, offset: 0x4C5C
| __IO uint32_t CCM_Type::GPR_PRIVATE2_CLR |
General Purpose Register, offset: 0x4C48
| __IO uint32_t CCM_Type::GPR_PRIVATE2_SET |
General Purpose Register, offset: 0x4C44
| __IO uint32_t CCM_Type::GPR_PRIVATE2_TOG |
General Purpose Register, offset: 0x4C4C
| __IO uint32_t CCM_Type::GPR_PRIVATE3 |
General Purpose Register, offset: 0x4C60
| __IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN |
GPR access control, offset: 0x4C70
| __IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN_CLR |
GPR access control, offset: 0x4C78
| __IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN_SET |
GPR access control, offset: 0x4C74
| __IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN_TOG |
GPR access control, offset: 0x4C7C
| __IO uint32_t CCM_Type::GPR_PRIVATE3_CLR |
General Purpose Register, offset: 0x4C68
| __IO uint32_t CCM_Type::GPR_PRIVATE3_SET |
General Purpose Register, offset: 0x4C64
| __IO uint32_t CCM_Type::GPR_PRIVATE3_TOG |
General Purpose Register, offset: 0x4C6C
| __IO uint32_t CCM_Type::GPR_PRIVATE4 |
General Purpose Register, offset: 0x4C80
| __IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN |
GPR access control, offset: 0x4C90
| __IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN_CLR |
GPR access control, offset: 0x4C98
| __IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN_SET |
GPR access control, offset: 0x4C94
| __IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN_TOG |
GPR access control, offset: 0x4C9C
| __IO uint32_t CCM_Type::GPR_PRIVATE4_CLR |
General Purpose Register, offset: 0x4C88
| __IO uint32_t CCM_Type::GPR_PRIVATE4_SET |
General Purpose Register, offset: 0x4C84
| __IO uint32_t CCM_Type::GPR_PRIVATE4_TOG |
General Purpose Register, offset: 0x4C8C
| __IO uint32_t CCM_Type::GPR_PRIVATE5 |
General Purpose Register, offset: 0x4CA0
| __IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN |
GPR access control, offset: 0x4CB0
| __IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN_CLR |
GPR access control, offset: 0x4CB8
| __IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN_SET |
GPR access control, offset: 0x4CB4
| __IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN_TOG |
GPR access control, offset: 0x4CBC
| __IO uint32_t CCM_Type::GPR_PRIVATE5_CLR |
General Purpose Register, offset: 0x4CA8
| __IO uint32_t CCM_Type::GPR_PRIVATE5_SET |
General Purpose Register, offset: 0x4CA4
| __IO uint32_t CCM_Type::GPR_PRIVATE5_TOG |
General Purpose Register, offset: 0x4CAC
| __IO uint32_t CCM_Type::GPR_PRIVATE6 |
General Purpose Register, offset: 0x4CC0
| __IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN |
GPR access control, offset: 0x4CD0
| __IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN_CLR |
GPR access control, offset: 0x4CD8
| __IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN_SET |
GPR access control, offset: 0x4CD4
| __IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN_TOG |
GPR access control, offset: 0x4CDC
| __IO uint32_t CCM_Type::GPR_PRIVATE6_CLR |
General Purpose Register, offset: 0x4CC8
| __IO uint32_t CCM_Type::GPR_PRIVATE6_SET |
General Purpose Register, offset: 0x4CC4
| __IO uint32_t CCM_Type::GPR_PRIVATE6_TOG |
General Purpose Register, offset: 0x4CCC
| __IO uint32_t CCM_Type::GPR_PRIVATE7 |
General Purpose Register, offset: 0x4CE0
| __IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN |
GPR access control, offset: 0x4CF0
| __IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN_CLR |
GPR access control, offset: 0x4CF8
| __IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN_SET |
GPR access control, offset: 0x4CF4
| __IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN_TOG |
GPR access control, offset: 0x4CFC
| __IO uint32_t CCM_Type::GPR_PRIVATE7_CLR |
General Purpose Register, offset: 0x4CE8
| __IO uint32_t CCM_Type::GPR_PRIVATE7_SET |
General Purpose Register, offset: 0x4CE4
| __IO uint32_t CCM_Type::GPR_PRIVATE7_TOG |
General Purpose Register, offset: 0x4CEC
| __IO uint32_t CCM_Type::GPR_SHARED |
General Purpose Register, array offset: 0x4800, array step: 0x20
| __IO uint32_t { ... } ::GPR_SHARED |
General Purpose Register, array offset: 0x4800, array step: 0x20
| __IO uint32_t { ... } ::GPR_SHARED |
General Purpose Register, array offset: 0x4800, array step: 0x20
| __IO uint32_t USB_Type::GPTIMER0CTRL |
General Purpose Timer #0 Controller, offset: 0x84
| __IO uint32_t USB_Type::GPTIMER0LD |
General Purpose Timer #0 Load, offset: 0x80
| __IO uint32_t USB_Type::GPTIMER1CTRL |
General Purpose Timer #1 Controller, offset: 0x8C
| __IO uint32_t USB_Type::GPTIMER1LD |
General Purpose Timer #1 Load, offset: 0x88
| __IO uint32_t ADC_Type::GS |
General status register, offset: 0x4C
| __IO uint32_t FLEXSPI_Type::HADDREND |
HADDR REMAP END ADDR, offset: 0x424
| __IO uint32_t FLEXSPI_Type::HADDROFFSET |
HADDR REMAP OFFSET, offset: 0x428
| __IO uint32_t FLEXSPI_Type::HADDRSTART |
HADDR REMAP START ADDR, offset: 0x420
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::HBP |
HBP, offset: 0x20
| __IO uint32_t ADC_Type::HC[8] |
Control register for hardware triggers, array offset: 0x0, array step: 0x4
| __I uint32_t USB_Type::HCCPARAMS |
Host Controller Capability Parameters, offset: 0x108
| __I uint16_t USB_Type::HCIVERSION |
Host Controller Interface Version, offset: 0x102
| __I uint32_t USB_Type::HCSPARAMS |
Host Controller Structural Parameters, offset: 0x104
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::HFP |
HFP, offset: 0x1C
| __IO uint32_t FLEXSPI_Type::HMSTRCR |
AHB Master ID 0 Control Register..AHB Master ID 7 Control Register, array offset: 0x400, array step: 0x4
| __IO uint16_t { ... } ::HOLD |
Timer Channel Hold Register, array offset: 0x8, array step: 0x20
| __IO uint16_t TMR_Type::HOLD |
Timer Channel Hold Register, array offset: 0x8, array step: 0x20
| __IO uint16_t { ... } ::HOLD |
Timer Channel Hold Register, array offset: 0x8, array step: 0x20
| __IO uint16_t { ... } ::HOLD |
Timer Channel Hold Register, array offset: 0x8, array step: 0x20
| __IO uint32_t USDHC_Type::HOST_CTRL_CAP |
Host Controller Capabilities, offset: 0x40
| __IO uint32_t CSU_Type::HP0 |
HP0 register, offset: 0x200
| __IO uint32_t SSARC_LP_Type::HP_TIMEOUT |
HP Timeout Register, offset: 0x20C
| __IO uint32_t SNVS_Type::HPCOMR |
SNVS_HP Command Register, offset: 0x4
| __IO uint32_t CSU_Type::HPCONTROL0 |
HPCONTROL0 register, offset: 0x358
| __IO uint32_t SNVS_Type::HPCR |
SNVS_HP Control Register, offset: 0x8
| __IO uint32_t SNVS_Type::HPHACIVR |
SNVS_HP High Assurance Counter IV Register, offset: 0x1C
| __I uint32_t SNVS_Type::HPHACR |
SNVS_HP High Assurance Counter Register, offset: 0x20
| __IO uint32_t SNVS_Type::HPLR |
SNVS_HP Lock Register, offset: 0x0
| __IO uint32_t SNVS_Type::HPRTCLR |
SNVS_HP Real Time Counter LSB Register, offset: 0x28
| __IO uint32_t SNVS_Type::HPRTCMR |
SNVS_HP Real Time Counter MSB Register, offset: 0x24
| __IO uint32_t SNVS_Type::HPSICR |
SNVS_HP Security Interrupt Control Register, offset: 0xC
| __IO uint32_t SNVS_Type::HPSR |
SNVS_HP Status Register, offset: 0x14
| __IO uint32_t SNVS_Type::HPSVCR |
SNVS_HP Security Violation Control Register, offset: 0x10
| __IO uint32_t SNVS_Type::HPSVSR |
SNVS_HP Security Violation Status Register, offset: 0x18
| __IO uint32_t SNVS_Type::HPTALR |
SNVS_HP Time Alarm LSB Register, offset: 0x30
| __IO uint32_t SNVS_Type::HPTAMR |
SNVS_HP Time Alarm MSB Register, offset: 0x2C
| __I uint32_t SNVS_Type::HPVIDR1 |
SNVS_HP Version ID Register 1, offset: 0xBF8
| __I uint32_t SNVS_Type::HPVIDR2 |
SNVS_HP Version ID Register 2, offset: 0xBFC
| __I uint32_t DMA_Type::HRS |
Hardware Request Status, offset: 0x34
| __I uint32_t ADC_Type::HS |
Status register for HW triggers, offset: 0x20
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::HSA |
HSA, offset: 0x24
| __IO uint32_t USBNC_Type::HSIC_CTRL |
USB Host HSIC Control Register, offset: 0x10
| __IO uint32_t LCDIFV2_Type::HSYN_PARA |
Horizontal Sync Parameter Register, offset: 0x18
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::HSYNC_POLARITY |
HSYNC_POLARITY, offset: 0x14
| __I uint64_t CAAM_Type::HT_JD_ADDR |
Holding Tank 0 Job Descriptor Address, array offset: 0xC00, array step: 0x20
| __I uint64_t { ... } ::HT_JD_ADDR |
Holding Tank 0 Job Descriptor Address, array offset: 0xC00, array step: 0x20
| __I uint64_t { ... } ::HT_JD_ADDR |
Holding Tank 0 Job Descriptor Address, array offset: 0xC00, array step: 0x20
| __I uint32_t CAAM_Type::HT_JQ_CTRL_LS |
Holding Tank 0 Job Queue Control, least-significant half, array offset: 0xC14, array step: 0x20
| __I uint32_t { ... } ::HT_JQ_CTRL_LS |
Holding Tank 0 Job Queue Control, least-significant half, array offset: 0xC14, array step: 0x20
| __I uint32_t { ... } ::HT_JQ_CTRL_LS |
Holding Tank 0 Job Queue Control, least-significant half, array offset: 0xC14, array step: 0x20
| __I uint32_t CAAM_Type::HT_JQ_CTRL_MS |
Holding Tank 0 Job Queue Control, most-significant half, array offset: 0xC10, array step: 0x20
| __I uint32_t { ... } ::HT_JQ_CTRL_MS |
Holding Tank 0 Job Queue Control, most-significant half, array offset: 0xC10, array step: 0x20
| __I uint32_t { ... } ::HT_JQ_CTRL_MS |
Holding Tank 0 Job Queue Control, most-significant half, array offset: 0xC10, array step: 0x20
| __I uint64_t CAAM_Type::HT_SD_ADDR |
Holding Tank 0 Shared Descriptor Address, array offset: 0xC08, array step: 0x20
| __I uint64_t { ... } ::HT_SD_ADDR |
Holding Tank 0 Shared Descriptor Address, array offset: 0xC08, array step: 0x20
| __I uint64_t { ... } ::HT_SD_ADDR |
Holding Tank 0 Shared Descriptor Address, array offset: 0xC08, array step: 0x20
| __I uint32_t CAAM_Type::HT_STATUS |
Holding Tank Status, array offset: 0xC1C, array step: 0x20
| __I uint32_t { ... } ::HT_STATUS |
Holding Tank Status, array offset: 0xC1C, array step: 0x20
| __I uint32_t { ... } ::HT_STATUS |
Holding Tank Status, array offset: 0xC1C, array step: 0x20
| __I uint32_t SSARC_LP_Type::HW_GROUP_PENDING |
Hardware Request Pending Register, offset: 0x21C
| __I uint32_t USB_Type::HWDEVICE |
Device Hardware Parameters, offset: 0xC
| __I uint32_t USB_Type::HWGENERAL |
Hardware General, offset: 0x4
| __I uint32_t USB_Type::HWHOST |
Host Hardware Parameters, offset: 0x8
| __I uint32_t USB_Type::HWRXBUF |
RX Buffer Hardware Parameters, offset: 0x14
| __I uint32_t USB_Type::HWTXBUF |
TX Buffer Hardware Parameters, offset: 0x10
| __IO uint32_t ENET_Type::IALR |
Descriptor Individual Lower Address Register, offset: 0x11C
| __IO uint32_t ENET_Type::IAUR |
Descriptor Individual Upper Address Register, offset: 0x118
| __I uint32_t GPT_Type::ICR |
GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4
GPT Input Capture Register, array offset: 0x1C, array step: 0x4
| __IO uint32_t GPIO_Type::ICR1 |
GPIO interrupt configuration register1, offset: 0xC
| __IO uint32_t GPIO_Type::ICR2 |
GPIO interrupt configuration register2, offset: 0x10
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10
| __IO uint32_t CAN_Type::ID |
Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10
Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18
Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x284, array step: 0x18
Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28
Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x284, array step: 0x28
Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48
Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x284, array step: 0x48
| __I uint32_t USB_Type::ID |
Identification register, offset: 0x0
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x284, array step: 0x18
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x284, array step: 0x28
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x284, array step: 0x48
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x284, array step: 0x18
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x284, array step: 0x28
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x284, array step: 0x48
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10
| __IO uint32_t PUF_Type::IDXBLK |
PUF Index Block Key Output, offset: 0x20C
| __IO uint32_t PUF_Type::IDXBLK_DP |
PUF Index Block Key Output, offset: 0x210
| __I uint32_t PUF_Type::IDXBLK_SHIFT |
PUF Key Manager Shift Status, offset: 0x258
| __I uint32_t PUF_Type::IDXBLK_STATUS |
PUF Index Block Setting Status Register, offset: 0x254
| __IO uint32_t ADC_Type::IE |
Interrupt Enable Register, offset: 0x18
| __IO uint32_t KEY_MANAGER_Type::IEE_KEY_CTRL |
CSR IEE Key Control, offset: 0x20
| __I uint32_t ENET_Type::IEEE_R_ALIGN |
Frames Received with Alignment Error Statistic Register, offset: 0x2D4
| __I uint32_t ENET_Type::IEEE_R_CRC |
Frames Received with CRC Error Statistic Register, offset: 0x2D0
| __I uint32_t ENET_Type::IEEE_R_DROP |
Frames not Counted Correctly Statistic Register, offset: 0x2C8
| __I uint32_t ENET_Type::IEEE_R_FDXFC |
Flow Control Pause Frames Received Statistic Register, offset: 0x2DC
| __I uint32_t ENET_Type::IEEE_R_FRAME_OK |
Frames Received OK Statistic Register, offset: 0x2CC
| __I uint32_t ENET_Type::IEEE_R_MACERR |
Receive FIFO Overflow Count Statistic Register, offset: 0x2D8
| __I uint32_t ENET_Type::IEEE_R_OCTETS_OK |
Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0
| __I uint32_t ENET_Type::IEEE_T_1COL |
Frames Transmitted with Single Collision Statistic Register, offset: 0x250
| __I uint32_t ENET_Type::IEEE_T_CSERR |
Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268
| __I uint32_t ENET_Type::IEEE_T_DEF |
Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258
| uint32_t ENET_Type::IEEE_T_DROP |
Reserved Statistic Register, offset: 0x248
| __I uint32_t ENET_Type::IEEE_T_EXCOL |
Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260
| __I uint32_t ENET_Type::IEEE_T_FDXFC |
Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270
| __I uint32_t ENET_Type::IEEE_T_FRAME_OK |
Frames Transmitted OK Statistic Register, offset: 0x24C
| __I uint32_t ENET_Type::IEEE_T_LCOL |
Frames Transmitted with Late Collision Statistic Register, offset: 0x25C
| __I uint32_t ENET_Type::IEEE_T_MACERR |
Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264
| __I uint32_t ENET_Type::IEEE_T_MCOL |
Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254
| __I uint32_t ENET_Type::IEEE_T_OCTETS_OK |
Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274
| __I uint32_t ENET_Type::IEEE_T_SQE |
Reserved Statistic Register, offset: 0x26C
| __IO uint32_t LPSPI_Type::IER |
Interrupt Enable Register, offset: 0x18
Interrupt Enable, offset: 0x18
| __IO uint32_t CAN_Type::IFLAG1 |
Interrupt Flags 1 Register, offset: 0x30
Interrupt Flags 1 register, offset: 0x30
| __IO uint32_t CAN_Type::IFLAG2 |
Interrupt Flags 2 Register, offset: 0x2C
Interrupt Flags 2 register, offset: 0x2C
| __IO uint32_t PUF_Type::IFSTAT |
PUF Interface Status Register, offset: 0xDC
| __IO uint32_t CSI_Type::IMAG_PARA |
CSI Image Parameter Register, offset: 0x34
| __IO uint32_t CAN_Type::IMASK1 |
Interrupt Masks 1 Register, offset: 0x28
Interrupt Masks 1 register, offset: 0x28
| __IO uint32_t CAN_Type::IMASK2 |
Interrupt Masks 2 Register, offset: 0x24
Interrupt Masks 2 register, offset: 0x24
| __I uint16_t ENC_Type::IMR |
Input Monitor Register, offset: 0x1A
| __IO uint32_t GPC_Type::IMR[4] |
IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4
| __IO uint32_t GPIO_Type::IMR |
GPIO interrupt mask register, offset: 0x14
| __IO uint32_t GPC_Type::IMR5 |
IRQ masking register 5, offset: 0x34
| __IO uint16_t { ... } ::INIT |
Initial Count Register, array offset: 0x2, array step: 0x60
| __IO uint16_t PWM_Type::INIT |
Initial Count Register, array offset: 0x2, array step: 0x60
| __IO uint16_t { ... } ::INIT |
Initial Count Register, array offset: 0x2, array step: 0x60
| __IO uint16_t { ... } ::INIT |
Initial Count Register, array offset: 0x2, array step: 0x60
| __IO uint32_t CDOG_Type::INSTRUCTION_TIMER |
Instruction Timer, offset: 0x8
| __IO uint32_t DMA_Type::INT |
Interrupt Request, offset: 0x24
| __IO uint32_t TRNG_Type::INT_CTRL |
Interrupt Control Register, offset: 0xA4
| __IO uint32_t TSC_Type::INT_EN |
Interrupt Enable, offset: 0x40
| __IO uint32_t { ... } ::INT_ENABLE |
Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1, array offset: 0x24, array step: 0x10
| __IO uint32_t LCDIFV2_Type::INT_ENABLE |
Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1, array offset: 0x24, array step: 0x10
| __IO uint32_t { ... } ::INT_ENABLE |
Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1, array offset: 0x24, array step: 0x10
| __IO uint32_t TRNG_Type::INT_MASK |
Mask Register, offset: 0xA8
| __IO uint32_t EMVSIM_Type::INT_MASK |
Interrupt Mask Register, offset: 0x14
| __IO uint32_t FLEXRAM_Type::INT_SIG_EN |
Interrupt Enable Register, offset: 0x18
| __IO uint32_t TSC_Type::INT_SIG_EN |
Interrupt Signal Enable, offset: 0x50
| __IO uint32_t USDHC_Type::INT_SIGNAL_EN |
Interrupt Signal Enable, offset: 0x38
| __IO uint32_t FLEXRAM_Type::INT_STAT_EN |
Interrupt Status Enable Register, offset: 0x14
| __IO uint32_t FLEXRAM_Type::INT_STATUS |
Interrupt Status Register, offset: 0x10
| __I uint32_t TRNG_Type::INT_STATUS |
Interrupt Status Register, offset: 0xAC
| __IO uint32_t TSC_Type::INT_STATUS |
Intterrupt Status, offset: 0x60
| __IO uint32_t USDHC_Type::INT_STATUS |
Interrupt Status, offset: 0x30
| __IO uint32_t { ... } ::INT_STATUS |
Interrupt Status Register for domain 0..Interrupt Status Register for domain 1, array offset: 0x20, array step: 0x10
| __IO uint32_t LCDIFV2_Type::INT_STATUS |
Interrupt Status Register for domain 0..Interrupt Status Register for domain 1, array offset: 0x20, array step: 0x10
| __IO uint32_t SSARC_LP_Type::INT_STATUS |
Interrupt Status Register, offset: 0x204
| __IO uint32_t { ... } ::INT_STATUS |
Interrupt Status Register for domain 0..Interrupt Status Register for domain 1, array offset: 0x20, array step: 0x10
| __IO uint32_t USDHC_Type::INT_STATUS_EN |
Interrupt Status Enable, offset: 0x34
| __IO uint32_t RDC_Type::INTCTRL |
Interrupt and Control, offset: 0x28
| __IO uint32_t FLEXSPI_Type::INTEN |
Interrupt Enable Register, offset: 0x10
| __IO uint16_t PWM_Type::INTEN |
Interrupt Enable Register, array offset: 0x26, array step: 0x60
| __IO uint16_t { ... } ::INTEN |
Interrupt Enable Register, array offset: 0x26, array step: 0x60
| __IO uint32_t SEMC_Type::INTEN |
Interrupt Enable Register, offset: 0x38
| __IO uint32_t PUF_Type::INTEN |
PUF Interrupt Enable, offset: 0x100
| __IO uint16_t { ... } ::INTEN |
Interrupt Enable Register, array offset: 0x26, array step: 0x60
| __IO uint16_t { ... } ::INTEN |
Interrupt Enable Register, array offset: 0x26, array step: 0x60
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::INTERFACE_COLOR_CODING |
INTERFACE_COLOR_CODING, offset: 0x8
| __IO uint32_t FLEXSPI_Type::INTR |
Interrupt Register, offset: 0x14
| __IO uint32_t SEMC_Type::INTR |
Interrupt Enable Register, offset: 0x3C
Interrupt Register, offset: 0x3C
| __IO uint32_t PUF_Type::INTSTAT |
PUF Interrupt Status, offset: 0x104
| __IO uint32_t RDC_Type::INTSTAT |
Interrupt Status, offset: 0x2C
| __IO uint32_t SEMC_Type::IOCR |
IO Mux Control Register, offset: 0x4
IO MUX Control Register, offset: 0x4
| __IO uint32_t FLEXSPI_Type::IPCMD |
IP Command Register, offset: 0xB0
| __IO uint32_t SEMC_Type::IPCMD |
IP Command register, offset: 0x9C
IP Command Register, offset: 0x9C
| __IO uint32_t FLEXSPI_Type::IPCR0 |
IP Control Register 0, offset: 0xA0
| __IO uint32_t SEMC_Type::IPCR0 |
IP Command control register 0, offset: 0x90
IP Command Control Register 0, offset: 0x90
| __IO uint32_t FLEXSPI_Type::IPCR1 |
IP Control Register 1, offset: 0xA4
| __IO uint32_t SEMC_Type::IPCR1 |
IP Command control register 1, offset: 0x94
IP Command Control Register 1, offset: 0x94
| __IO uint32_t SEMC_Type::IPCR2 |
IP Command control register 2, offset: 0x98
IP Command Control Register 2, offset: 0x98
| __I uint32_t SEMC_Type::IPRXDAT |
RX DATA register (for IP Command), offset: 0xB0
RX DATA Register, offset: 0xB0
| __IO uint32_t FLEXSPI_Type::IPRXFCR |
IP RX FIFO Control Register, offset: 0xB8
| __I uint32_t FLEXSPI_Type::IPRXFSTS |
IP RX FIFO Status Register, offset: 0xF0
| __IO uint32_t FLEXSPI_Type::IPSNSZEND0 |
IPS nonsecure region End address of region 0, offset: 0x434
| __IO uint32_t FLEXSPI_Type::IPSNSZEND1 |
IPS nonsecure region End address of region 1, offset: 0x43C
| __IO uint32_t FLEXSPI_Type::IPSNSZSTART0 |
IPS nonsecure region Start address of region 0, offset: 0x430
| __IO uint32_t FLEXSPI_Type::IPSNSZSTART1 |
IPS nonsecure region Start address of region 1, offset: 0x438
| __IO uint32_t SEMC_Type::IPTXDAT |
TX DATA register (for IP Command), offset: 0xA0
TX DATA Register, offset: 0xA0
| __IO uint32_t FLEXSPI_Type::IPTXFCR |
IP TX FIFO Control Register, offset: 0xBC
| __I uint32_t FLEXSPI_Type::IPTXFSTS |
IP TX FIFO Status Register, offset: 0xF4
| __IO uint32_t GPT_Type::IR |
GPT Interrupt Register, offset: 0xC
| __IO uint64_t { ... } ::IRBAR_JR |
Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3, array offset: 0x10000, array step: 0x10000
| __IO uint64_t CAAM_Type::IRBAR_JR |
Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3, array offset: 0x10000, array step: 0x10000
| __IO uint64_t { ... } ::IRBAR_JR |
Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3, array offset: 0x10000, array step: 0x10000
| __IO uint32_t { ... } ::IRJAR_JR |
Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3, array offset: 0x1001C, array step: 0x10000
| __IO uint32_t CAAM_Type::IRJAR_JR |
Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3, array offset: 0x1001C, array step: 0x10000
| __IO uint32_t { ... } ::IRJAR_JR |
Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3, array offset: 0x1001C, array step: 0x10000
| __IO uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_MASK |
IRQ_MASK, offset: 0x28
| __IO uint32_t MIPI_CSI2RX_Type::IRQ_MASK |
IRQ Mask Setting Register, offset: 0x110
| __IO uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_MASK2 |
IRQ_MASK2, offset: 0x2C
| __I uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_STATUS |
IRQ_STATUS, offset: 0x20
| __I uint32_t MIPI_CSI2RX_Type::IRQ_STATUS |
IRQ Status Register, offset: 0x10C
| __I uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_STATUS2 |
IRQ_STATUS2, offset: 0x24
| __IO uint32_t CAAM_Type::IRRIR_JR |
Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3, array offset: 0x1005C, array step: 0x10000
| __IO uint32_t { ... } ::IRRIR_JR |
Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3, array offset: 0x1005C, array step: 0x10000
| __IO uint32_t { ... } ::IRRIR_JR |
Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3, array offset: 0x1005C, array step: 0x10000
| __IO uint32_t CAAM_Type::IRSAR_JR |
Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3, array offset: 0x10014, array step: 0x10000
| __IO uint32_t { ... } ::IRSAR_JR |
Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3, array offset: 0x10014, array step: 0x10000
| __IO uint32_t { ... } ::IRSAR_JR |
Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3, array offset: 0x10014, array step: 0x10000
| __IO uint32_t { ... } ::IRSR_JR |
Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3, array offset: 0x1000C, array step: 0x10000
| __IO uint32_t CAAM_Type::IRSR_JR |
Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3, array offset: 0x1000C, array step: 0x10000
| __IO uint32_t { ... } ::IRSR_JR |
Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3, array offset: 0x1000C, array step: 0x10000
| __IO uint32_t CM7_MCM_Type::ISCR |
Interrupt Status and Control Register, offset: 0x10
| __IO uint32_t MCM_Type::ISCR |
Interrupt Status and Control Register, offset: 0x10
| __I uint32_t GPC_Type::ISR[4] |
IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4
| __IO uint32_t GPIO_Type::ISR |
GPIO interrupt status register, offset: 0x18
| __I uint32_t GPC_Type::ISR5 |
IRQ status resister 5, offset: 0x38
| __I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_ADDR |
ITCM multi-bit ECC Error Address Register, offset: 0x50
| __I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_DATA_LSB |
ITCM multi-bit ECC Error Data Register, offset: 0x54
| __I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_DATA_MSB |
ITCM multi-bit ECC Error Data Register, offset: 0x58
| __I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_INFO |
ITCM multi-bit ECC Error Information Register, offset: 0x4C
| __I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_ADDR |
ITCM single-bit ECC Error Address Register, offset: 0x40
| __I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_DATA_LSB |
ITCM single-bit ECC Error Data Register, offset: 0x44
| __I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_DATA_MSB |
ITCM single-bit ECC Error Data Register, offset: 0x48
| __I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_INFO |
ITCM single-bit ECC Error Information Register, offset: 0x3C
| __IO uint32_t FLEXRAM_Type::ITCM_MAGIC_ADDR |
ITCM Magic Address Register, offset: 0xC
| __IO uint32_t CAAM_Type::JDKEKR |
Job Descriptor Key Encryption Key Register, array offset: 0x400, array step: 0x4
| __IO uint32_t CAAM_Type::JQ_DEBUG_SEL |
Job Queue Debug Select Register, offset: 0xC24
| __I uint64_t { ... } ::JRAAA[4] |
Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register, array offset: 0x10800, array step: index*0x10000, index2*0x8
| __I uint64_t CAAM_Type::JRAAA[4] |
Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register, array offset: 0x10800, array step: index*0x10000, index2*0x8
| __I uint64_t { ... } ::JRAAA[4] |
Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register, array offset: 0x10800, array step: index*0x10000, index2*0x8
| __I uint32_t CAAM_Type::JRAAV |
Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register, array offset: 0x10704, array step: 0x10000
| __I uint32_t { ... } ::JRAAV |
Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register, array offset: 0x10704, array step: 0x10000
| __I uint32_t { ... } ::JRAAV |
Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register, array offset: 0x10704, array step: 0x10000
| __IO uint32_t { ... } ::JRCFGR_JR_LS |
Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half, array offset: 0x10054, array step: 0x10000
| __IO uint32_t CAAM_Type::JRCFGR_JR_LS |
Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half, array offset: 0x10054, array step: 0x10000
| __IO uint32_t { ... } ::JRCFGR_JR_LS |
Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half, array offset: 0x10054, array step: 0x10000
| __IO uint32_t { ... } ::JRCFGR_JR_MS |
Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half, array offset: 0x10050, array step: 0x10000
| __IO uint32_t CAAM_Type::JRCFGR_JR_MS |
Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half, array offset: 0x10050, array step: 0x10000
| __IO uint32_t { ... } ::JRCFGR_JR_MS |
Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half, array offset: 0x10050, array step: 0x10000
| __O uint32_t { ... } ::JRCR_JR |
Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3, array offset: 0x1006C, array step: 0x10000
| __O uint32_t CAAM_Type::JRCR_JR |
Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3, array offset: 0x1006C, array step: 0x10000
| __O uint32_t { ... } ::JRCR_JR |
Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3, array offset: 0x1006C, array step: 0x10000
| __IO uint32_t { ... } ::JRDID_LS |
Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half, array offset: 0x14, array step: 0x8
| __IO uint32_t CAAM_Type::JRDID_LS |
Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half, array offset: 0x14, array step: 0x8
| __IO uint32_t { ... } ::JRDID_LS |
Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half, array offset: 0x14, array step: 0x8
| __IO uint32_t CAAM_Type::JRDID_MS |
Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half, array offset: 0x10, array step: 0x8
| __IO uint32_t { ... } ::JRDID_MS |
Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half, array offset: 0x10, array step: 0x8
| __IO uint32_t { ... } ::JRDID_MS |
Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half, array offset: 0x10, array step: 0x8
| __IO uint32_t { ... } ::JRINTR_JR |
Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3, array offset: 0x1004C, array step: 0x10000
| __IO uint32_t CAAM_Type::JRINTR_JR |
Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3, array offset: 0x1004C, array step: 0x10000
| __IO uint32_t { ... } ::JRINTR_JR |
Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3, array offset: 0x1004C, array step: 0x10000
| __I uint64_t CAAM_Type::JRJDDA |
Job Ring Job-Done Descriptor Address 0 Register, array offset: 0xE00, array step: 0x8
| __I uint32_t CAAM_Type::JRJDJIF |
Job Ring Job-Done Job ID FIFO, offset: 0xDC4
| __I uint32_t CAAM_Type::JRJDJIFBC |
Job Ring Job-Done Job ID FIFO BC, offset: 0xDC0
| __I uint32_t CAAM_Type::JRJDS1 |
Job Ring Job-Done Source 1, offset: 0xDE4
| __I uint32_t CAAM_Type::JRJIDU_LS |
Job Ring Job IDs in Use Register, least-significant half, offset: 0xDBC
| __IO uint32_t { ... } ::JRSMVBAR |
Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register, array offset: 0x184, array step: 0x8
| __IO uint32_t CAAM_Type::JRSMVBAR |
Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register, array offset: 0x184, array step: 0x8
| __IO uint32_t { ... } ::JRSMVBAR |
Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register, array offset: 0x184, array step: 0x8
| __I uint32_t { ... } ::JRSTAR_JR |
Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3, array offset: 0x10044, array step: 0x10000
| __I uint32_t CAAM_Type::JRSTAR_JR |
Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3, array offset: 0x10044, array step: 0x10000
| __I uint32_t { ... } ::JRSTAR_JR |
Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3, array offset: 0x10044, array step: 0x10000
| __IO uint32_t CAAM_Type::JRSTARTR |
Job Ring Start Register, offset: 0x5C
| __IO uint16_t KPP_Type::KDDR |
Keypad Data Direction Register, offset: 0x4
| __IO uint32_t DCP_Type::KEY |
DCP key index, offset: 0x60
| __IO uint32_t OTFAD_Type::KEY[4] |
AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4
| __IO uint32_t { ... } ::KEY[4] |
AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4
| __IO uint32_t { ... } ::KEY[4] |
AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4
| __IO uint32_t DCP_Type::KEYDATA |
DCP key data, offset: 0x70
| __IO uint32_t PUF_Type::KEYENABLE |
PUF Key Manager Enable, offset: 0x204
| __IO uint32_t PUF_Type::KEYINDEX |
PUF Key Index Register, offset: 0x4
| __O uint32_t PUF_Type::KEYINPUT |
PUF Key Input Register, offset: 0x40
| __IO uint32_t PUF_Type::KEYLOCK |
PUF Key Manager Lock, offset: 0x200
| __IO uint32_t PUF_Type::KEYMASK |
PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable, array offset: 0x214, array step: 0x4
| __I uint32_t PUF_Type::KEYOUTINDEX |
PUF Key Output Index Register, offset: 0x60
| __I uint32_t PUF_Type::KEYOUTPUT |
PUF Key Output Register, offset: 0x64
| __IO uint32_t PUF_Type::KEYRESET |
PUF Key Manager Reset, offset: 0x208
| __IO uint32_t PUF_Type::KEYSIZE |
PUF Key Size Register, offset: 0x8
| __IO uint16_t KPP_Type::KPCR |
Keypad Control Register, offset: 0x0
| __IO uint16_t KPP_Type::KPDR |
Keypad Data Register, offset: 0x6
| __IO uint16_t KPP_Type::KPSR |
Keypad Status Register, offset: 0x2
| __I uint16_t ENC_Type::LASTEDGE |
Last Edge Time Register, offset: 0x28
| __I uint16_t ENC_Type::LASTEDGEH |
Last Edge Time Hold Register, offset: 0x2A
| __IO uint16_t ENC_Type::LCOMP |
Lower Position Compare Register, offset: 0x26
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_BYPASS_EN_SP |
LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER, offset: 0x640
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_ENABLE_SP |
LDO_LPSR_ANA_ENABLE_SP_REGISTER, offset: 0x610
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_LP_MODE_SP |
LDO_LPSR_ANA_LP_MODE_SP_REGISTER, offset: 0x620
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_STBY_EN_SP |
LDO_LPSR_ANA_STBY_EN_SP_REGISTER, offset: 0x650
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_TRACKING_EN_SP |
LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER, offset: 0x630
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_BYPASS_EN_SP |
LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER, offset: 0x6D0
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_ENABLE_SP |
LDO_LPSR_DIG_ENABLE_SP_REGISTER, offset: 0x660
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_LP_MODE_SP |
LDO_LPSR_DIG_LP_MODE_SP_REGISTER, offset: 0x6B0
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_STBY_EN_SP |
LDO_LPSR_DIG_STBY_EN_SP_REGISTER, offset: 0x6E0
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRACKING_EN_SP |
LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER, offset: 0x6C0
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP0 |
LDO_LPSR_DIG_TRG_SP0_REGISTER, offset: 0x670
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP1 |
LDO_LPSR_DIG_TRG_SP1_REGISTER, offset: 0x680
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP2 |
LDO_LPSR_DIG_TRG_SP2_REGISTER, offset: 0x690
| __IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP3 |
LDO_LPSR_DIG_TRG_SP3_REGISTER, offset: 0x6A0
| __IO uint32_t ANADIG_PMU_Type::LDO_PLL_ENABLE_SP |
LDO_PLL_ENABLE_SP_REGISTER, offset: 0x600
| __IO uint32_t PIT_Type::LDVAL |
Timer Load Value Register, array offset: 0x100, array step: 0x10
| __IO uint32_t { ... } ::LDVAL |
Timer Load Value Register, array offset: 0x100, array step: 0x10
| __IO uint32_t { ... } ::LDVAL |
Timer Load Value Register, array offset: 0x100, array step: 0x10
| __IO uint32_t { ... } ::LDVAL |
Timer Load Value Register, array offset: 0x100, array step: 0x10
| __IO uint16_t ENC_Type::LINIT |
Lower Initialization Register, offset: 0x18
| __IO uint32_t MCM_Type::LMDR[4] |
Local Memory Descriptor Register, array offset: 0x400, array step: 0x4
| __I uint32_t MCM_Type::LMFAR |
LMEM Fault Address Register, offset: 0x490
| __IO uint32_t MCM_Type::LMFATR |
LMEM Fault Attribute Register, offset: 0x494
| __I uint32_t MCM_Type::LMFDHR |
LMEM Fault Data High Register, offset: 0x4A0
| __I uint32_t MCM_Type::LMFDLR |
LMEM Fault Data Low Register, offset: 0x4A4
| __IO uint16_t ENC_Type::LMOD |
Lower Modulus Register, offset: 0x22
| __IO uint32_t MCM_Type::LMPECR |
LMEM Parity & ECC Control Register, offset: 0x480
| __IO uint32_t MCM_Type::LMPEIR |
LMEM Parity & ECC Interrupt Register, offset: 0x488
| __IO uint16_t { ... } ::LOAD |
Timer Channel Load Register, array offset: 0x6, array step: 0x20
| __IO uint16_t TMR_Type::LOAD |
Timer Channel Load Register, array offset: 0x6, array step: 0x20
| __IO uint16_t { ... } ::LOAD |
Timer Channel Load Register, array offset: 0x6, array step: 0x20
| __IO uint16_t { ... } ::LOAD |
Timer Channel Load Register, array offset: 0x6, array step: 0x20
| __IO uint32_t OCOTP_Type::LOCK |
Value of OTP Bank0 Word0 (Lock controls), offset: 0x400
| __I uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::LOCK |
LOCK, offset: 0x30
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::LOCK_BYP |
LOCK_BYP, offset: 0x34
| __I uint32_t OCOTP_Type::LOCKED0 |
OTP Controller Program Locked Status 0 Register, offset: 0x600
| __I uint32_t OCOTP_Type::LOCKED1 |
OTP Controller Program Locked Status 1 Register, offset: 0x610
| __I uint32_t OCOTP_Type::LOCKED2 |
OTP Controller Program Locked Status 2 Register, offset: 0x620
| __I uint32_t OCOTP_Type::LOCKED3 |
OTP Controller Program Locked Status 3 Register, offset: 0x630
| __I uint32_t OCOTP_Type::LOCKED4 |
OTP Controller Program Locked Status 4 Register, offset: 0x640
| __IO uint32_t { ... } ::LOOPBACK |
USB Loopback Test Register, array offset: 0x1E0, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::LOOPBACK |
USB Loopback Test Register, array offset: 0x1E0, array step: 0x60
| __IO uint32_t { ... } ::LOOPBACK_CLR |
USB Loopback Test Register, array offset: 0x1E8, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::LOOPBACK_CLR |
USB Loopback Test Register, array offset: 0x1E8, array step: 0x60
| __IO uint32_t { ... } ::LOOPBACK_SET |
USB Loopback Test Register, array offset: 0x1E4, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::LOOPBACK_SET |
USB Loopback Test Register, array offset: 0x1E4, array step: 0x60
| __IO uint32_t { ... } ::LOOPBACK_TOG |
USB Loopback Test Register, array offset: 0x1EC, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::LOOPBACK_TOG |
USB Loopback Test Register, array offset: 0x1EC, array step: 0x60
| __IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL |
XTAL OSC (LP) Control Register, offset: 0x270
| __IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_CLR |
XTAL OSC (LP) Control Register, offset: 0x278
| __IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_SET |
XTAL OSC (LP) Control Register, offset: 0x274
| __IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_TOG |
XTAL OSC (LP) Control Register, offset: 0x27C
| __IO uint32_t SNVS_Type::LPATCLKR |
SNVS_LP Active Tamper Clock Control Register, offset: 0xE4
| __O uint32_t SNVS_Type::LPATCR |
SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register, array offset: 0xC0, array step: 0x4
| __IO uint32_t SNVS_Type::LPATCTLR |
SNVS_LP Active Tamper Control Register, offset: 0xE0
| __IO uint32_t SNVS_Type::LPATRC1R |
SNVS_LP Active Tamper Routing Control 1 Register, offset: 0xE8
| __IO uint32_t SNVS_Type::LPATRC2R |
SNVS_LP Active Tamper Routing Control 2 Register, offset: 0xEC
| __IO uint32_t SNVS_Type::LPCR |
SNVS_LP Control Register, offset: 0x38
| __IO uint32_t SNVS_Type::LPGPR |
SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4
SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4
| __IO uint32_t SNVS_Type::LPGPR0_LEGACY_ALIAS |
SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68
| __IO uint32_t SNVS_Type::LPGPR_ALIAS |
SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4
| __IO uint32_t SNVS_Type::LPLR |
SNVS_LP Lock Register, offset: 0x34
| __IO uint32_t SNVS_Type::LPLVDR |
SNVS_LP Digital Low-Voltage Detector Register, offset: 0x64
| __IO uint32_t SNVS_Type::LPMKCR |
SNVS_LP Master Key Control Register, offset: 0x3C
| __IO uint16_t ENC_Type::LPOS |
Lower Position Counter Register, offset: 0x10
| __I uint16_t ENC_Type::LPOSH |
Lower Position Hold Register, offset: 0x14
| __IO uint32_t SNVS_Type::LPSECR |
SNVS_LP Security Events Configuration Register, offset: 0x48
| __IO uint32_t SNVS_Type::LPSMCLR |
SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60
| __IO uint32_t SNVS_Type::LPSMCMR |
SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C
| __IO uint32_t SNVS_Type::LPSR |
SNVS_LP Status Register, offset: 0x4C
| __I uint32_t ANADIG_PMU_Type::LPSR_1P8_LDO_OTP_TRIM_VALUE |
LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER, offset: 0x7D0
| __IO uint32_t SNVS_Type::LPSRTCLR |
SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54
| __IO uint32_t SNVS_Type::LPSRTCMR |
SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50
| __IO uint32_t SNVS_Type::LPSVCR |
SNVS_LP Security Violation Control Register, offset: 0x40
| __IO uint32_t SNVS_Type::LPTAR |
SNVS_LP Time Alarm Register, offset: 0x58
| __IO uint32_t SNVS_Type::LPTDC2R |
SNVS_LP Tamper Detectors Config 2 Register, offset: 0xA0
| __IO uint32_t SNVS_Type::LPTDCR |
SNVS_LP Tamper Detect Configuration Register, offset: 0x48
| __IO uint32_t SNVS_Type::LPTDSR |
SNVS_LP Tamper Detectors Status Register, offset: 0xA4
| __IO uint32_t SNVS_Type::LPTGF1CR |
SNVS_LP Tamper Glitch Filter 1 Configuration Register, offset: 0xA8
| __IO uint32_t SNVS_Type::LPTGF2CR |
SNVS_LP Tamper Glitch Filter 2 Configuration Register, offset: 0xAC
| __IO uint32_t SNVS_Type::LPTGFCR |
SNVS_LP Tamper Glitch Filters Configuration Register, offset: 0x44
| __IO uint32_t SNVS_Type::LPZMKR |
SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4
| __I uint32_t PIT_Type::LTMR64H |
PIT Upper Lifetime Timer Register, offset: 0xE0
| __I uint32_t PIT_Type::LTMR64L |
PIT Lower Lifetime Timer Register, offset: 0xE4
| __IO uint32_t FLEXSPI_Type::LUT |
LUT 0..LUT 63, array offset: 0x200, array step: 0x4
| __IO uint32_t LCDIF_Type::LUT0_ADDR |
Lookup Table 0 Index Register, offset: 0xB10
| __IO uint32_t LCDIF_Type::LUT0_DATA |
Lookup Table 0 Data Register, offset: 0xB20
| __IO uint32_t LCDIF_Type::LUT1_ADDR |
Lookup Table 1 Index Register, offset: 0xB30
| __IO uint32_t LCDIF_Type::LUT1_DATA |
Lookup Table 1 Data Register, offset: 0xB40
| __IO uint32_t LCDIF_Type::LUT_CTRL |
Look Up Table Control Register, offset: 0xB00
| __IO uint32_t FLEXSPI_Type::LUTCR |
LUT Control Register, offset: 0x1C
| __IO uint32_t FLEXSPI_Type::LUTKEY |
LUT Key Register, offset: 0x18
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::M_PRG_HS_PREPARE |
M_PRG_HS_PREPARE, offset: 0x4
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::M_PRG_HS_TRAIL |
M_PRG_HS_TRAIL, offset: 0x14
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::M_PRG_HS_ZERO |
M_PRG_HS_ZERO, offset: 0xC
| __IO uint32_t OCOTP_Type::MAC0 |
Value of OTP Bank4 Word2 (MAC Address), offset: 0x620
| __IO uint32_t OCOTP_Type::MAC1 |
Value of OTP Bank4 Word3 (MAC Address), offset: 0x630
| __IO uint16_t PWM_Type::MASK |
Mask Register, offset: 0x182
| __IO uint32_t KEY_MANAGER_Type::MASTER_KEY_CTRL |
CSR Master Key Control Register, offset: 0x0
| __IO uint32_t LPUART_Type::MATCH |
LPUART Match Address Register, offset: 0x20
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::MC_PRG_HS_PREPARE |
MC_PRG_HS_PREPARE, offset: 0x8
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::MC_PRG_HS_TRAIL |
MC_PRG_HS_TRAIL, offset: 0x18
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::MC_PRG_HS_ZERO |
MC_PRG_HS_ZERO, offset: 0x10
| __IO uint32_t LPI2C_Type::MCCR0 |
Master Clock Configuration Register 0, offset: 0x48
Master Clock Configuration 0, offset: 0x48
| __IO uint32_t LPI2C_Type::MCCR1 |
Master Clock Configuration Register 1, offset: 0x50
Master Clock Configuration 1, offset: 0x50
| __IO uint32_t CAAM_Type::MCFGR |
Master Configuration Register, offset: 0x4
| __IO uint32_t LPI2C_Type::MCFGR0 |
Master Configuration Register 0, offset: 0x20
Master Configuration 0, offset: 0x20
| __IO uint32_t LPI2C_Type::MCFGR1 |
Master Configuration Register 1, offset: 0x24
Master Configuration 1, offset: 0x24
| __IO uint32_t LPI2C_Type::MCFGR2 |
Master Configuration Register 2, offset: 0x28
Master Configuration 2, offset: 0x28
| __IO uint32_t LPI2C_Type::MCFGR3 |
Master Configuration Register 3, offset: 0x2C
Master Configuration 3, offset: 0x2C
| __IO uint32_t CAN_Type::MCR |
Module Configuration Register, offset: 0x0
Module Configuration register, offset: 0x0
| __IO uint32_t LPI2C_Type::MCR |
Master Control Register, offset: 0x10
Master Control, offset: 0x10
| __IO uint32_t PIT_Type::MCR |
PIT Module Control Register, offset: 0x0
| __IO uint32_t SEMC_Type::MCR |
Module Control Register, offset: 0x0
| __IO uint32_t XRDC2_Type::MCR |
Module Control Register, offset: 0x0
| __IO uint32_t FLEXSPI_Type::MCR0 |
Module Control Register 0, offset: 0x0
| __IO uint32_t FLEXSPI_Type::MCR1 |
Module Control Register 1, offset: 0x4
| __IO uint32_t FLEXSPI_Type::MCR2 |
Module Control Register 2, offset: 0x8
| __IO uint32_t TRNG_Type::MCTL |
Miscellaneous Control Register, offset: 0x0
| __IO uint16_t PWM_Type::MCTRL |
Master Control Register, offset: 0x188
| __IO uint16_t PWM_Type::MCTRL2 |
Master Control 2 Register, offset: 0x18A
| __IO uint32_t RDC_Type::MDA |
Master Domain Assignment, array offset: 0x200, array step: 0x4
| __IO uint32_t { ... } ::MDAC_MDA_W0 |
Master Domain Assignment, array offset: 0x2000, array step: index*0x100, index2*0x8
| __IO uint32_t XRDC2_Type::MDAC_MDA_W0 |
Master Domain Assignment, array offset: 0x2000, array step: index*0x100, index2*0x8
| __IO uint32_t { ... } ::MDAC_MDA_W0 |
Master Domain Assignment, array offset: 0x2000, array step: index*0x100, index2*0x8
| __IO uint32_t { ... } ::MDAC_MDA_W1 |
Master Domain Assignment, array offset: 0x2004, array step: index*0x100, index2*0x8
| __IO uint32_t XRDC2_Type::MDAC_MDA_W1 |
Master Domain Assignment, array offset: 0x2004, array step: index*0x100, index2*0x8
| __IO uint32_t { ... } ::MDAC_MDA_W1 |
Master Domain Assignment, array offset: 0x2004, array step: index*0x100, index2*0x8
| __IO uint32_t LPI2C_Type::MDER |
Master DMA Enable Register, offset: 0x1C
Master DMA Enable, offset: 0x1C
| __IO uint32_t LPI2C_Type::MDMR |
Master Data Match Register, offset: 0x40
Master Data Match, offset: 0x40
| __I uint32_t TSC_Type::MEASEURE_VALUE |
Measure Value, offset: 0x30
| __IO uint32_t CAN_Type::MECR |
Memory Error Control register, offset: 0xAE0
| __IO uint32_t PGC_Type::MEGA_CTRL |
PGC Mega Control Register, offset: 0x220
| __IO uint32_t PGC_Type::MEGA_PDNSCR |
PGC Mega Pull Down Sequence Control Register, offset: 0x228
| __IO uint32_t PGC_Type::MEGA_PUPSCR |
PGC Mega Power Up Sequence Control Register, offset: 0x224
| __IO uint32_t PGC_Type::MEGA_SR |
PGC Mega Power Gating Controller Status Register, offset: 0x22C
| __IO uint32_t OCOTP_Type::MEM0 |
Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480
| __IO uint32_t OCOTP_Type::MEM1 |
Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490
| __IO uint32_t OCOTP_Type::MEM2 |
Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0
| __IO uint32_t OCOTP_Type::MEM3 |
Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0
| __IO uint32_t OCOTP_Type::MEM4 |
Value of OTP Bank 1 Word 4 (Memory Related Info.), offset: 0x4C0
| __I uint32_t MCM_Type::MEMCFG |
Memory configuration, offset: 0x4
| __IO uint32_t LPI2C_Type::MFCR |
Master FIFO Control Register, offset: 0x58
Master FIFO Control, offset: 0x58
| __I uint32_t LPI2C_Type::MFSR |
Master FIFO Status Register, offset: 0x5C
Master FIFO Status, offset: 0x5C
| __IO uint32_t ENET_Type::MIBC |
MIB Control Register, offset: 0x64
| __IO uint32_t LPI2C_Type::MIER |
Master Interrupt Enable Register, offset: 0x18
Master Interrupt Enable, offset: 0x18
| __IO uint32_t PGMC_MIF_Type::MIF_AUTHEN_CTRL |
MIF Authentication Control, offset: 0x4
| __IO uint32_t PGMC_MIF_Type::MIF_MLPL_ARR_PDN |
MIF MLPL control of array power down, offset: 0x60
| __IO uint32_t PGMC_MIF_Type::MIF_MLPL_HS |
MIF MLPL control of HS, offset: 0x40
| __IO uint32_t PGMC_MIF_Type::MIF_MLPL_IG |
MIF MLPL control of IG, offset: 0x20
| __IO uint32_t PGMC_MIF_Type::MIF_MLPL_INITN |
MIF MLPL control of INITN, offset: 0x80
| __IO uint32_t PGMC_MIF_Type::MIF_MLPL_ISO |
MIF MLPL control of isolation enable, offset: 0xB0
| __IO uint32_t PGMC_MIF_Type::MIF_MLPL_LS |
MIF MLPL control of LS, offset: 0x30
| __IO uint32_t PGMC_MIF_Type::MIF_MLPL_PER_PDN |
MIF MLPL control of peripheral power down, offset: 0x70
| __IO uint32_t PGMC_MIF_Type::MIF_MLPL_SLEEP |
MIF MLPL control of SLEEP, offset: 0x10
| __IO uint32_t PGMC_MIF_Type::MIF_MLPL_STDBY |
MIF MLPL control of STDBY, offset: 0x50
| __IO uint32_t USB_ANALOG_Type::MISC |
USB Misc Register, array offset: 0x1F0, array step: 0x60
| __IO uint32_t { ... } ::MISC |
USB Misc Register, array offset: 0x1F0, array step: 0x60
| __IO uint32_t CCM_ANALOG_Type::MISC0 |
Miscellaneous Register 0, offset: 0x150
| __IO uint32_t PMU_Type::MISC0 |
Miscellaneous Register 0, offset: 0x150
| __IO uint32_t XTALOSC24M_Type::MISC0 |
Miscellaneous Register 0, offset: 0x150
| __IO uint32_t CCM_ANALOG_Type::MISC0_CLR |
Miscellaneous Register 0, offset: 0x158
| __IO uint32_t PMU_Type::MISC0_CLR |
Miscellaneous Register 0, offset: 0x158
| __IO uint32_t XTALOSC24M_Type::MISC0_CLR |
Miscellaneous Register 0, offset: 0x158
| __IO uint32_t CCM_ANALOG_Type::MISC0_SET |
Miscellaneous Register 0, offset: 0x154
| __IO uint32_t PMU_Type::MISC0_SET |
Miscellaneous Register 0, offset: 0x154
| __IO uint32_t XTALOSC24M_Type::MISC0_SET |
Miscellaneous Register 0, offset: 0x154
| __IO uint32_t CCM_ANALOG_Type::MISC0_TOG |
Miscellaneous Register 0, offset: 0x15C
| __IO uint32_t PMU_Type::MISC0_TOG |
Miscellaneous Register 0, offset: 0x15C
| __IO uint32_t XTALOSC24M_Type::MISC0_TOG |
Miscellaneous Register 0, offset: 0x15C
| __IO uint32_t CCM_ANALOG_Type::MISC1 |
Miscellaneous Register 1, offset: 0x160
| __IO uint32_t PMU_Type::MISC1 |
Miscellaneous Register 1, offset: 0x160
| __IO uint32_t CCM_ANALOG_Type::MISC1_CLR |
Miscellaneous Register 1, offset: 0x168
| __IO uint32_t PMU_Type::MISC1_CLR |
Miscellaneous Register 1, offset: 0x168
| __IO uint32_t CCM_ANALOG_Type::MISC1_SET |
Miscellaneous Register 1, offset: 0x164
| __IO uint32_t PMU_Type::MISC1_SET |
Miscellaneous Register 1, offset: 0x164
| __IO uint32_t CCM_ANALOG_Type::MISC1_TOG |
Miscellaneous Register 1, offset: 0x16C
| __IO uint32_t PMU_Type::MISC1_TOG |
Miscellaneous Register 1, offset: 0x16C
| __IO uint32_t CCM_ANALOG_Type::MISC2 |
Miscellaneous Register 2, offset: 0x170
| __IO uint32_t PMU_Type::MISC2 |
Miscellaneous Control Register, offset: 0x170
| __IO uint32_t CCM_ANALOG_Type::MISC2_CLR |
Miscellaneous Register 2, offset: 0x178
| __IO uint32_t PMU_Type::MISC2_CLR |
Miscellaneous Control Register, offset: 0x178
| __IO uint32_t CCM_ANALOG_Type::MISC2_SET |
Miscellaneous Register 2, offset: 0x174
| __IO uint32_t PMU_Type::MISC2_SET |
Miscellaneous Control Register, offset: 0x174
| __IO uint32_t CCM_ANALOG_Type::MISC2_TOG |
Miscellaneous Register 2, offset: 0x17C
| __IO uint32_t PMU_Type::MISC2_TOG |
Miscellaneous Control Register, offset: 0x17C
| __IO uint32_t USB_ANALOG_Type::MISC_CLR |
USB Misc Register, array offset: 0x1F8, array step: 0x60
| __IO uint32_t { ... } ::MISC_CLR |
USB Misc Register, array offset: 0x1F8, array step: 0x60
| __IO uint32_t OCOTP_Type::MISC_CONF0 |
Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0
| __IO uint32_t OCOTP_Type::MISC_CONF1 |
Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0
| __I uint32_t ANADIG_MISC_Type::MISC_DIFPROG |
Chip Silicon Version Register, offset: 0x800
| __IO uint32_t USB_ANALOG_Type::MISC_SET |
USB Misc Register, array offset: 0x1F4, array step: 0x60
| __IO uint32_t { ... } ::MISC_SET |
USB Misc Register, array offset: 0x1F4, array step: 0x60
| __IO uint32_t { ... } ::MISC_TOG |
USB Misc Register, array offset: 0x1FC, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::MISC_TOG |
USB Misc Register, array offset: 0x1FC, array step: 0x60
| __I uint32_t FLEXSPI_Type::MISCCR4 |
Misc Control Register 4, offset: 0xD0
| __I uint32_t FLEXSPI_Type::MISCCR5 |
Misc Control Register 5, offset: 0xD4
| __I uint32_t FLEXSPI_Type::MISCCR6 |
Misc Control Register 6, offset: 0xD8
| __I uint32_t FLEXSPI_Type::MISCCR7 |
Misc Control Register 7, offset: 0xDC
| __IO uint32_t USDHC_Type::MIX_CTRL |
Mixer Control, offset: 0x48
| __IO uint32_t USDHC_Type::MMC_BOOT |
MMC Boot, offset: 0xC4
| __IO uint32_t ENET_Type::MMFR |
MII Management Frame Register, offset: 0x40
| __IO uint32_t LPUART_Type::MODIR |
LPUART Modem IrDA Register, offset: 0x24
| __I uint32_t CAAM_Type::MPECC |
Manufacturing Protection ECC Register, offset: 0x3F8
| __IO uint8_t CAAM_Type::MPMR |
Manufacturing Protection Message Register, array offset: 0x380, array step: 0x1
| __IO uint8_t CAAM_Type::MPPKR |
Manufacturing Protection Private Key Register, array offset: 0x300, array step: 0x1
| __IO uint32_t AIPSTZ_Type::MPR |
Master Priviledge Registers, offset: 0x0
| __I uint8_t CAAM_Type::MPTESTR |
Manufacturing Protection Test Register, array offset: 0x3C0, array step: 0x1
| __IO uint32_t ENET_Type::MRBR |
Maximum Receive Buffer Size Register - Ring 0, offset: 0x188
| __IO uint32_t ENET_Type::MRBR1 |
Maximum Receive Buffer Size Register - Ring 1, offset: 0x168
| __IO uint32_t ENET_Type::MRBR2 |
Maximum Receive Buffer Size Register - Ring 2, offset: 0x174
| __IO uint32_t RDC_Type::MRC |
Memory Region Control, array offset: 0x808, array step: 0x10
| __IO uint32_t { ... } ::MRC |
Memory Region Control, array offset: 0x808, array step: 0x10
| __IO uint32_t { ... } ::MRC |
Memory Region Control, array offset: 0x808, array step: 0x10
| __IO uint32_t { ... } ::MRC_MRGD_W0 |
Memory Region Descriptor, array offset: 0x8000, array step: index*0x400, index2*0x20
| __IO uint32_t XRDC2_Type::MRC_MRGD_W0 |
Memory Region Descriptor, array offset: 0x8000, array step: index*0x400, index2*0x20
| __IO uint32_t { ... } ::MRC_MRGD_W0 |
Memory Region Descriptor, array offset: 0x8000, array step: index*0x400, index2*0x20
| __IO uint32_t XRDC2_Type::MRC_MRGD_W1 |
Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20
| __IO uint32_t { ... } ::MRC_MRGD_W1 |
Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20
| __IO uint32_t { ... } ::MRC_MRGD_W1 |
Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20
| __IO uint32_t { ... } ::MRC_MRGD_W2 |
Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20
| __IO uint32_t XRDC2_Type::MRC_MRGD_W2 |
Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20
| __IO uint32_t { ... } ::MRC_MRGD_W2 |
Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20
| __IO uint32_t { ... } ::MRC_MRGD_W3 |
Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20
| __IO uint32_t XRDC2_Type::MRC_MRGD_W3 |
Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20
| __IO uint32_t { ... } ::MRC_MRGD_W3 |
Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20
| __IO uint32_t { ... } ::MRC_MRGD_W5 |
Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20
| __IO uint32_t XRDC2_Type::MRC_MRGD_W5 |
Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20
| __IO uint32_t { ... } ::MRC_MRGD_W5 |
Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20
| __IO uint32_t XRDC2_Type::MRC_MRGD_W6 |
Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20
| __IO uint32_t { ... } ::MRC_MRGD_W6 |
Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20
| __IO uint32_t { ... } ::MRC_MRGD_W6 |
Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20
| __I uint32_t LPI2C_Type::MRDR |
Master Receive Data Register, offset: 0x70
Master Receive Data, offset: 0x70
| __IO uint32_t RDC_Type::MREA |
Memory Region End Address, array offset: 0x804, array step: 0x10
| __IO uint32_t { ... } ::MREA |
Memory Region End Address, array offset: 0x804, array step: 0x10
| __IO uint32_t { ... } ::MREA |
Memory Region End Address, array offset: 0x804, array step: 0x10
| __IO uint32_t RDC_Type::MRSA |
Memory Region Start Address, array offset: 0x800, array step: 0x10
| __IO uint32_t { ... } ::MRSA |
Memory Region Start Address, array offset: 0x800, array step: 0x10
| __IO uint32_t { ... } ::MRSA |
Memory Region Start Address, array offset: 0x800, array step: 0x10
| __IO uint32_t RDC_Type::MRVS |
Memory Region Violation Status, array offset: 0x80C, array step: 0x10
| __IO uint32_t { ... } ::MRVS |
Memory Region Violation Status, array offset: 0x80C, array step: 0x10
| __IO uint32_t { ... } ::MRVS |
Memory Region Violation Status, array offset: 0x80C, array step: 0x10
| __IO uint32_t XRDC2_Type::MSC_MSAC_W0 |
Memory Slot Access Control, array offset: 0x1000, array step: 0x8
| __IO uint32_t { ... } ::MSC_MSAC_W0 |
Memory Slot Access Control, array offset: 0x1000, array step: 0x8
| __IO uint32_t { ... } ::MSC_MSAC_W0 |
Memory Slot Access Control, array offset: 0x1000, array step: 0x8
| __IO uint32_t { ... } ::MSC_MSAC_W1 |
Memory Slot Access Control, array offset: 0x1004, array step: 0x8
| __IO uint32_t XRDC2_Type::MSC_MSAC_W1 |
Memory Slot Access Control, array offset: 0x1004, array step: 0x8
| __IO uint32_t { ... } ::MSC_MSAC_W1 |
Memory Slot Access Control, array offset: 0x1004, array step: 0x8
| __IO uint32_t ENET_Type::MSCR |
MII Speed Control Register, offset: 0x44
| __IO uint32_t LPI2C_Type::MSR |
Master Status Register, offset: 0x14
Master Status, offset: 0x14
| __O uint32_t LPI2C_Type::MTDR |
Master Transmit Data Register, offset: 0x60
Master Transmit Data, offset: 0x60
| __I uint32_t XECC_Type::MULTI_ERR_ADDR |
Multiple Error Address, offset: 0x2C
| __I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC0 |
Multiple Error Address And ECC code On OCRAM Bank0, offset: 0x8C
| __I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC1 |
Multiple Error Address And ECC code On OCRAM Bank1, offset: 0x98
| __I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC2 |
Multiple Error Address And ECC code On OCRAM Bank2, offset: 0xA4
| __I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC3 |
Multiple Error Address And ECC code On OCRAM Bank3, offset: 0xB0
| __I uint32_t XECC_Type::MULTI_ERR_BIT_FIELD |
Multiple Error Bit Field, offset: 0x38
| __I uint32_t XECC_Type::MULTI_ERR_DATA |
Multiple Error Read Data, offset: 0x30
| __I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH0 |
HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x94
| __I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH1 |
HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0xA0
| __I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH2 |
HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xAC
| __I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH3 |
HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB8
| __I uint32_t MECC_Type::MULTI_ERR_DATA_LOW0 |
LOW 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x90
| __I uint32_t MECC_Type::MULTI_ERR_DATA_LOW1 |
LOW 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0x9C
| __I uint32_t MECC_Type::MULTI_ERR_DATA_LOW2 |
LOW 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xA8
| __I uint32_t MECC_Type::MULTI_ERR_DATA_LOW3 |
LOW 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB4
| __I uint32_t XECC_Type::MULTI_ERR_ECC |
Multiple Error ECC code, offset: 0x34
| __IO uint8_t CMP_Type::MUXCR |
MUX Control Register, offset: 0x5
| __IO uint32_t SEMC_Type::NANDCR0 |
NAND control register 0, offset: 0x50
NAND Control Register 0, offset: 0x50
| __IO uint32_t SEMC_Type::NANDCR1 |
NAND control register 1, offset: 0x54
NAND Control Register 1, offset: 0x54
| __IO uint32_t SEMC_Type::NANDCR2 |
NAND control register 2, offset: 0x58
NAND Control Register 2, offset: 0x58
| __IO uint32_t SEMC_Type::NANDCR3 |
NAND control register 3, offset: 0x5C
NAND Control Register 3, offset: 0x5C
| __IO uint32_t DMA_Type::NBYTES_MLNO |
TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLNO |
TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLNO |
TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLNO |
TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t DMA_Type::NBYTES_MLOFFNO |
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFNO |
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFNO |
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFNO |
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t DMA_Type::NBYTES_MLOFFYES |
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFYES |
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFYES |
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFYES |
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t PXP_Type::NEXT |
Next Frame Pointer, offset: 0x400
| __IO uint32_t LCDIF_Type::NEXT_BUF |
LCD Interface Next Buffer Address Register, offset: 0x50
| __IO uint32_t SEMC_Type::NORCR0 |
NOR control register 0, offset: 0x60
NOR Control Register 0, offset: 0x60
| __IO uint32_t SEMC_Type::NORCR1 |
NOR control register 1, offset: 0x64
NOR Control Register 1, offset: 0x64
| __IO uint32_t SEMC_Type::NORCR2 |
NOR control register 2, offset: 0x68
NOR Control Register 2, offset: 0x68
| __IO uint32_t SEMC_Type::NORCR3 |
NOR control register 3, offset: 0x6C
NOR Control Register 3, offset: 0x6C
| __IO uint32_t SEMC_Type::NORCR3 |
NOR Control Register 3, offset: 0x6C
| __IO uint32_t GPT_Type::OCR |
GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4
GPT Output Compare Register, array offset: 0x10, array step: 0x4
| __I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_ADDR |
OCRAM multi-bit ECC Error Address Register, offset: 0x30
| __I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_DATA_LSB |
OCRAM multi-bit ECC Error Data Register, offset: 0x34
| __I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_DATA_MSB |
OCRAM multi-bit ECC Error Data Register, offset: 0x38
| __I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_INFO |
OCRAM multi-bit ECC Error Information Register, offset: 0x2C
| __I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_ADDR |
OCRAM single-bit ECC Error Address Register, offset: 0x20
| __I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_DATA_LSB |
OCRAM single-bit ECC Error Data Register, offset: 0x24
| __I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_DATA_MSB |
OCRAM single-bit ECC Error Data Register, offset: 0x28
| __I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_INFO |
OCRAM single-bit ECC Error Information Register, offset: 0x1C
| __IO uint32_t FLEXRAM_Type::OCRAM_MAGIC_ADDR |
OCRAM Magic Address Register, offset: 0x4
| __I uint32_t FLEXRAM_Type::OCRAM_PIPELINE_STATUS |
OCRAM Pipeline Status register, offset: 0x10C
| __IO uint16_t { ... } ::OCTRL |
Output Control Register, array offset: 0x22, array step: 0x60
| __IO uint16_t PWM_Type::OCTRL |
Output Control Register, array offset: 0x22, array step: 0x60
| __IO uint16_t { ... } ::OCTRL |
Output Control Register, array offset: 0x22, array step: 0x60
| __IO uint16_t { ... } ::OCTRL |
Output Control Register, array offset: 0x22, array step: 0x60
| __IO uint32_t ADC_Type::OFS |
Offset correction value register, offset: 0x54
| __IO uint32_t AIPSTZ_Type::OPACR |
Off-Platform Peripheral Access Control Registers, offset: 0x40
| __IO uint32_t AIPSTZ_Type::OPACR1 |
Off-Platform Peripheral Access Control Registers, offset: 0x44
| __IO uint32_t AIPSTZ_Type::OPACR2 |
Off-Platform Peripheral Access Control Registers, offset: 0x48
| __IO uint32_t AIPSTZ_Type::OPACR3 |
Off-Platform Peripheral Access Control Registers, offset: 0x4C
| __IO uint32_t AIPSTZ_Type::OPACR4 |
Off-Platform Peripheral Access Control Registers, offset: 0x50
| __IO uint32_t ENET_Type::OPD |
Opcode/Pause Duration Register, offset: 0xEC
| __IO uint64_t { ... } ::ORBAR_JR |
Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3, array offset: 0x10020, array step: 0x10000
| __IO uint64_t CAAM_Type::ORBAR_JR |
Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3, array offset: 0x10020, array step: 0x10000
| __IO uint64_t { ... } ::ORBAR_JR |
Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3, array offset: 0x10020, array step: 0x10000
| __IO uint32_t { ... } ::ORJRR_JR |
Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3, array offset: 0x10034, array step: 0x10000
| __IO uint32_t CAAM_Type::ORJRR_JR |
Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3, array offset: 0x10034, array step: 0x10000
| __IO uint32_t { ... } ::ORJRR_JR |
Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3, array offset: 0x10034, array step: 0x10000
| __IO uint32_t { ... } ::ORSFR_JR |
Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3, array offset: 0x1003C, array step: 0x10000
| __IO uint32_t CAAM_Type::ORSFR_JR |
Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3, array offset: 0x1003C, array step: 0x10000
| __IO uint32_t { ... } ::ORSFR_JR |
Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3, array offset: 0x1003C, array step: 0x10000
| __IO uint32_t { ... } ::ORSR_JR |
Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3, array offset: 0x1002C, array step: 0x10000
| __IO uint32_t CAAM_Type::ORSR_JR |
Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3, array offset: 0x1002C, array step: 0x10000
| __IO uint32_t { ... } ::ORSR_JR |
Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3, array offset: 0x1002C, array step: 0x10000
| __IO uint32_t { ... } ::ORWIR_JR |
Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3, array offset: 0x10064, array step: 0x10000
| __IO uint32_t CAAM_Type::ORWIR_JR |
Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3, array offset: 0x10064, array step: 0x10000
| __IO uint32_t { ... } ::ORWIR_JR |
Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3, array offset: 0x10064, array step: 0x10000
| __IO uint32_t ANADIG_OSC_Type::OSC_16M_CTRL |
16MHz RCOSC Control Register, offset: 0xC0
| __IO uint32_t ANADIG_OSC_Type::OSC_24M_CTRL |
24MHz OSC Control Register, offset: 0x20
| __I uint32_t ANADIG_OSC_Type::OSC_400M_CTRL0 |
400MHz RCOSC Control0 Register, offset: 0x40
| __IO uint32_t ANADIG_OSC_Type::OSC_400M_CTRL1 |
400MHz RCOSC Control1 Register, offset: 0x50
| __IO uint32_t ANADIG_OSC_Type::OSC_400M_CTRL2 |
400MHz RCOSC Control2 Register, offset: 0x60
| __IO uint32_t ANADIG_OSC_Type::OSC_48M_CTRL |
48MHz RCOSC Control Register, offset: 0x10
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG0 |
XTAL OSC Configuration 0 Register, offset: 0x2A0
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_CLR |
XTAL OSC Configuration 0 Register, offset: 0x2A8
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_SET |
XTAL OSC Configuration 0 Register, offset: 0x2A4
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_TOG |
XTAL OSC Configuration 0 Register, offset: 0x2AC
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG1 |
XTAL OSC Configuration 1 Register, offset: 0x2B0
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_CLR |
XTAL OSC Configuration 1 Register, offset: 0x2B8
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_SET |
XTAL OSC Configuration 1 Register, offset: 0x2B4
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_TOG |
XTAL OSC Configuration 1 Register, offset: 0x2BC
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG2 |
XTAL OSC Configuration 2 Register, offset: 0x2C0
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_CLR |
XTAL OSC Configuration 2 Register, offset: 0x2C8
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_SET |
XTAL OSC Configuration 2 Register, offset: 0x2C4
| __IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_TOG |
XTAL OSC Configuration 2 Register, offset: 0x2CC
| __IO uint32_t KEY_MANAGER_Type::OTFAD1_KEY_CTRL |
CSR OTFAD-1 Key Control, offset: 0x10
| __IO uint32_t KEY_MANAGER_Type::OTFAD2_KEY_CTRL |
CSR OTFAD-2 Key Control, offset: 0x18
| __IO uint32_t USB_Type::OTGSC |
On-The-Go Status & control, offset: 0x1A4
| __IO uint32_t PXP_Type::OUT_AS_LRC |
Alpha Surface Lower Right Coordinate, offset: 0xA0
| __IO uint32_t PXP_Type::OUT_AS_ULC |
Alpha Surface Upper Left Coordinate, offset: 0x90
| __IO uint32_t PXP_Type::OUT_BUF |
Output Frame Buffer Pointer, offset: 0x30
| __IO uint32_t PXP_Type::OUT_BUF2 |
Output Frame Buffer Pointer #2, offset: 0x40
| __IO uint32_t PXP_Type::OUT_CTRL |
Output Buffer Control Register, offset: 0x20
| __IO uint32_t PXP_Type::OUT_CTRL_CLR |
Output Buffer Control Register, offset: 0x28
| __IO uint32_t PXP_Type::OUT_CTRL_SET |
Output Buffer Control Register, offset: 0x24
| __IO uint32_t PXP_Type::OUT_CTRL_TOG |
Output Buffer Control Register, offset: 0x2C
| __IO uint32_t PXP_Type::OUT_LRC |
Output Surface Lower Right Coordinate, offset: 0x60
| __IO uint32_t PXP_Type::OUT_PITCH |
Output Buffer Pitch, offset: 0x50
| __IO uint32_t PXP_Type::OUT_PS_LRC |
Processed Surface Lower Right Coordinate, offset: 0x80
| __IO uint32_t PXP_Type::OUT_PS_ULC |
Processed Surface Upper Left Coordinate, offset: 0x70
| __IO uint32_t OCOTP_Type::OUT_STATUS |
8K OTP Memory STATUS Register, offset: 0x90
| __IO uint32_t OCOTP_Type::OUT_STATUS_CLR |
8K OTP Memory STATUS Register, offset: 0x98
| __IO uint32_t OCOTP_Type::OUT_STATUS_SET |
8K OTP Memory STATUS Register, offset: 0x94
| __IO uint32_t OCOTP_Type::OUT_STATUS_TOG |
8K OTP Memory STATUS Register, offset: 0x9C
| __IO uint16_t PWM_Type::OUTEN |
Output Enable Register, offset: 0x180
| __IO uint32_t XRDC2_Type::PAC_PDAC_W0 |
Peripheral Domain Access Control, array offset: 0x4000, array step: index*0x800, index2*0x8
| __IO uint32_t { ... } ::PAC_PDAC_W0 |
Peripheral Domain Access Control, array offset: 0x4000, array step: index*0x800, index2*0x8
| __IO uint32_t { ... } ::PAC_PDAC_W0 |
Peripheral Domain Access Control, array offset: 0x4000, array step: index*0x800, index2*0x8
| __IO uint32_t { ... } ::PAC_PDAC_W1 |
Peripheral Domain Access Control, array offset: 0x4004, array step: index*0x800, index2*0x8
| __IO uint32_t XRDC2_Type::PAC_PDAC_W1 |
Peripheral Domain Access Control, array offset: 0x4004, array step: index*0x800, index2*0x8
| __IO uint32_t { ... } ::PAC_PDAC_W1 |
Peripheral Domain Access Control, array offset: 0x4004, array step: index*0x800, index2*0x8
| __I uint32_t DCP_Type::PACKET0 |
DCP work packet 0 status register, offset: 0x80
| __I uint32_t DCP_Type::PACKET1 |
DCP work packet 1 status register, offset: 0x90
| __I uint32_t DCP_Type::PACKET2 |
DCP work packet 2 status register, offset: 0xA0
| __I uint32_t DCP_Type::PACKET3 |
DCP work packet 3 status register, offset: 0xB0
| __I uint32_t DCP_Type::PACKET4 |
DCP work packet 4 status register, offset: 0xC0
| __I uint32_t DCP_Type::PACKET5 |
DCP work packet 5 status register, offset: 0xD0
| __I uint32_t DCP_Type::PACKET6 |
DCP work packet 6 status register, offset: 0xE0
| __IO uint32_t CAAM_Type::PAGE0_SDID |
Page 0 SDID Register, offset: 0x8
| __IO uint32_t DCP_Type::PAGETABLE |
DCP page table register, offset: 0x420
| __IO uint32_t ENET_Type::PALR |
Physical Address Lower Register, offset: 0xE4
| __I uint32_t FLEXIO_Type::PARAM |
Parameter Register, offset: 0x4
| __I uint32_t I2S_Type::PARAM |
Parameter Register, offset: 0x4
Parameter, offset: 0x4
| __I uint32_t LPI2C_Type::PARAM |
Parameter Register, offset: 0x4
Parameter, offset: 0x4
| __I uint32_t LPSPI_Type::PARAM |
Parameter Register, offset: 0x4
Parameter, offset: 0x4
| __I uint32_t LPUART_Type::PARAM |
Parameter Register, offset: 0x4
| __I uint32_t ADC_Type::PARAM |
Parameter Register, offset: 0x4
| __I uint32_t CMP_Type::PARAM |
Parameter Register, offset: 0x4
| __I uint32_t DAC_Type::PARAM |
Parameter Register, offset: 0x4
| __I uint32_t EMVSIM_Type::PARAM |
Parameter Register, offset: 0x4
| __IO uint32_t ENET_Type::PAUR |
Physical Address Upper Register, offset: 0xE8
| __IO uint32_t ADC_Type::PAUSE |
LPADC Pause Register, offset: 0x24
| __IO uint32_t CAAM_Type::PBSL |
Peak Bandwidth Smoothing Limit Register, offset: 0x220
| __IO uint32_t IEE_Type::PC_BLK_DEC |
Performance Counter, Number of AES Block Decryptions, offset: 0x44
| __IO uint32_t IEE_Type::PC_BLK_ENC |
Performance Counter, Number of AES Block Encryptions, offset: 0x40
| __IO uint32_t IEE_Type::PC_M_LT |
Performance Counter, AES Master Latency Threshold, offset: 0x24
| __IO uint32_t IEE_Type::PC_M_MBR |
Performance Counter, Number of AXI Master Merge Buffer Read Transactions, offset: 0x64
| __IO uint32_t IEE_Type::PC_MR_TBC_L |
Performance Counter, Lower Master Read Transactions Byte Count, offset: 0x84
| __IO uint32_t IEE_Type::PC_MR_TBC_U |
Performance Counter, Upper Master Read Transactions Byte Count, offset: 0x80
| __IO uint32_t IEE_Type::PC_MR_TLAT_L |
Performance Counter, Lower Master Read Latency Count, offset: 0xB4
| __IO uint32_t IEE_Type::PC_MR_TLAT_U |
Performance Counter, Upper Master Read Latency Count, offset: 0xB0
| __IO uint32_t IEE_Type::PC_MR_TLGTT |
Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold, offset: 0x98
| __IO uint32_t IEE_Type::PC_MR_TRANS |
Performance Counter, Number of AXI Master Read Transactions, offset: 0x58
| __IO uint32_t IEE_Type::PC_MW_TBC_L |
Performance Counter, Lower Master Write Transactions Byte Count, offset: 0x8C
| __IO uint32_t IEE_Type::PC_MW_TBC_U |
Performance Counter, Upper Master Write Transactions Byte Count, offset: 0x88
| __IO uint32_t IEE_Type::PC_MW_TLAT_L |
Performance Counter, Lower Master Write Latency Count, offset: 0xBC
| __IO uint32_t IEE_Type::PC_MW_TLAT_U |
Performance Counter, Upper Master Write Latency Count, offset: 0xB8
| __IO uint32_t IEE_Type::PC_MW_TLGTT |
Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold, offset: 0x9C
| __IO uint32_t IEE_Type::PC_MW_TRANS |
Performance Counter, Number of AXI Master Write Transactions, offset: 0x5C
| __IO uint32_t IEE_Type::PC_S_LT |
Performance Counter, AES Slave Latency Threshold Value, offset: 0x20
| __IO uint32_t IEE_Type::PC_SR_TBC_L |
Performance Counter, Lower Slave Read Transactions Byte Count, offset: 0x74
| __IO uint32_t IEE_Type::PC_SR_TBC_U |
Performance Counter, Upper Slave Read Transactions Byte Count, offset: 0x70
| __IO uint32_t IEE_Type::PC_SR_TLAT_L |
Performance Counter, Lower Slave Read Latency Count, offset: 0xA4
| __IO uint32_t IEE_Type::PC_SR_TLAT_U |
Performance Counter, Upper Slave Read Latency Count, offset: 0xA0
| __IO uint32_t IEE_Type::PC_SR_TLGTT |
Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold, offset: 0x90
| __IO uint32_t IEE_Type::PC_SR_TNRT_L |
Performance Counter, Lower Slave Read Total Non-Responding Time, offset: 0xC4
| __IO uint32_t IEE_Type::PC_SR_TNRT_U |
Performance Counter, Upper Slave Read Total Non-Responding Time, offset: 0xC0
| __IO uint32_t IEE_Type::PC_SR_TRANS |
Performance Counter, Number of AXI Slave Read Transactions, offset: 0x50
| __IO uint32_t IEE_Type::PC_SW_TBC_L |
Performance Counter, Lower Slave Write Transactions Byte Count, offset: 0x7C
| __IO uint32_t IEE_Type::PC_SW_TBC_U |
Performance Counter, Upper Slave Write Transactions Byte Count, offset: 0x78
| __IO uint32_t IEE_Type::PC_SW_TLAT_L |
Performance Counter, Lower Slave Write Latency Count, offset: 0xAC
| __IO uint32_t IEE_Type::PC_SW_TLAT_U |
Performance Counter, Upper Slave Write Latency Count, offset: 0xA8
| __IO uint32_t IEE_Type::PC_SW_TLGTT |
Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold, offset: 0x94
| __IO uint32_t IEE_Type::PC_SW_TNRT_L |
Performance Counter, Lower Slave Write Total Non-Responding Time, offset: 0xCC
| __IO uint32_t IEE_Type::PC_SW_TNRT_U |
Performance Counter, Upper Slave Write Total Non-Responding Time, offset: 0xC8
| __IO uint32_t IEE_Type::PC_SW_TRANS |
Performance Counter, Number of AXI Slave Write Transactions, offset: 0x54
| __IO uint32_t LMEM_Type::PCCCR |
PC bus Cache control register, offset: 0x0
| __IO uint32_t LMEM_Type::PCCCVR |
PC bus Cache read/write value register, offset: 0xC
| __IO uint32_t LMEM_Type::PCCLCR |
PC bus Cache line control register, offset: 0x4
| __IO uint32_t LMEM_Type::PCCSAR |
PC bus Cache search address register, offset: 0x8
| __IO uint32_t EMVSIM_Type::PCSR |
Port Control and Status Register, offset: 0x28
| __I uint16_t MCM_Type::PCT |
Processor core type, offset: 0x2
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::PD_PLL |
PD_PLL, offset: 0x1C
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::PD_TX |
PD_TX, offset: 0x0
| __IO uint32_t RDC_Type::PDAP |
Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4
| __IO uint32_t LCDIFV2_Type::PDI_PARA |
Parallel Data Interface Parameter Register, offset: 0x40
| __IO uint32_t OCOTP_Type::PDN |
OTP Controller PDN Register, offset: 0x10
| __I uint32_t MECC_Type::PENDING_STAT |
Pending Status, offset: 0x104
| __IO uint32_t USB_Type::PERIODICLISTBASE |
Frame List Base Address, offset: 0x154
| __IO uint32_t { ... } ::PERIODICLISTBASE |
Frame List Base Address, offset: 0x154
| __IO uint32_t { ... } ::PERIODICLISTBASE |
Frame List Base Address, offset: 0x154
| __IO uint32_t { ... } ::PERIODICLISTBASE |
Frame List Base Address, offset: 0x154
| __IO uint32_t CDOG_Type::PERSISTENT |
Persistent Data Storage, offset: 0x1C
| __IO uint32_t CCM_ANALOG_Type::PFD_480 |
480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0
| __IO uint32_t CCM_ANALOG_Type::PFD_480_CLR |
480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8
| __IO uint32_t CCM_ANALOG_Type::PFD_480_SET |
480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4
| __IO uint32_t CCM_ANALOG_Type::PFD_480_TOG |
480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC
| __IO uint32_t CCM_ANALOG_Type::PFD_528 |
528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100
| __IO uint32_t CCM_ANALOG_Type::PFD_528_CLR |
528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108
| __IO uint32_t CCM_ANALOG_Type::PFD_528_SET |
528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104
| __IO uint32_t CCM_ANALOG_Type::PFD_528_TOG |
528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C
| __IO uint32_t { ... } ::PIGEON_0 |
Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40
| __IO uint32_t LCDIF_Type::PIGEON_0 |
Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40
| __IO uint32_t { ... } ::PIGEON_0 |
Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40
| __IO uint32_t { ... } ::PIGEON_0 |
Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40
| __IO uint32_t LCDIF_Type::PIGEON_1 |
Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40
| __IO uint32_t { ... } ::PIGEON_1 |
Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40
| __IO uint32_t { ... } ::PIGEON_1 |
Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40
| __IO uint32_t { ... } ::PIGEON_1 |
Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40
| __IO uint32_t LCDIF_Type::PIGEON_2 |
Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40
| __IO uint32_t { ... } ::PIGEON_2 |
Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40
| __IO uint32_t { ... } ::PIGEON_2 |
Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40
| __IO uint32_t { ... } ::PIGEON_2 |
Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40
| __IO uint32_t LCDIF_Type::PIGEONCTRL0 |
LCDIF Pigeon Mode Control0 Register, offset: 0x380
| __IO uint32_t LCDIF_Type::PIGEONCTRL0_CLR |
LCDIF Pigeon Mode Control0 Register, offset: 0x388
| __IO uint32_t LCDIF_Type::PIGEONCTRL0_SET |
LCDIF Pigeon Mode Control0 Register, offset: 0x384
| __IO uint32_t LCDIF_Type::PIGEONCTRL0_TOG |
LCDIF Pigeon Mode Control0 Register, offset: 0x38C
| __IO uint32_t LCDIF_Type::PIGEONCTRL1 |
LCDIF Pigeon Mode Control1 Register, offset: 0x390
| __IO uint32_t LCDIF_Type::PIGEONCTRL1_CLR |
LCDIF Pigeon Mode Control1 Register, offset: 0x398
| __IO uint32_t LCDIF_Type::PIGEONCTRL1_SET |
LCDIF Pigeon Mode Control1 Register, offset: 0x394
| __IO uint32_t LCDIF_Type::PIGEONCTRL1_TOG |
LCDIF Pigeon Mode Control1 Register, offset: 0x39C
| __IO uint32_t LCDIF_Type::PIGEONCTRL2 |
LCDIF Pigeon Mode Control2 Register, offset: 0x3A0
| __IO uint32_t LCDIF_Type::PIGEONCTRL2_CLR |
LCDIF Pigeon Mode Control2 Register, offset: 0x3A8
| __IO uint32_t LCDIF_Type::PIGEONCTRL2_SET |
LCDIF Pigeon Mode Control2 Register, offset: 0x3A4
| __IO uint32_t LCDIF_Type::PIGEONCTRL2_TOG |
LCDIF Pigeon Mode Control2 Register, offset: 0x3AC
| __I uint32_t FLEXIO_Type::PIN |
Pin State Register, offset: 0xC
| __IO uint32_t LPUART_Type::PINCFG |
LPUART Pin Configuration Register, offset: 0xC
| __IO uint32_t MECC_Type::PIPE_ECC_EN |
OCRAM Pipeline And ECC Enable, offset: 0x100
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::PIXEL_FIFO_SEND_LEVEL |
PIXEL_FIFO_SEND_LEVEL, offset: 0x4
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::PIXEL_FORMAT |
PIXEL_FORMAT, offset: 0xC
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::PIXEL_PAYLOAD_SIZE |
PEXEL_PAYLOAD_SIZE, offset: 0x0
| __I uint32_t TRNG_Type::PKRCNT10 |
Statistical Check Poker Count 1 and 0 Register, offset: 0x80
| __I uint32_t TRNG_Type::PKRCNT32 |
Statistical Check Poker Count 3 and 2 Register, offset: 0x84
| __I uint32_t TRNG_Type::PKRCNT54 |
Statistical Check Poker Count 5 and 4 Register, offset: 0x88
| __I uint32_t TRNG_Type::PKRCNT76 |
Statistical Check Poker Count 7 and 6 Register, offset: 0x8C
| __I uint32_t TRNG_Type::PKRCNT98 |
Statistical Check Poker Count 9 and 8 Register, offset: 0x90
| __I uint32_t TRNG_Type::PKRCNTBA |
Statistical Check Poker Count B and A Register, offset: 0x94
| __I uint32_t TRNG_Type::PKRCNTDC |
Statistical Check Poker Count D and C Register, offset: 0x98
| __I uint32_t TRNG_Type::PKRCNTFE |
Statistical Check Poker Count F and E Register, offset: 0x9C
| __IO uint32_t { ... } ::PKRMAX |
Poker Maximum Limit Register, offset: 0xC
| __IO uint32_t TRNG_Type::PKRMAX |
Poker Maximum Limit Register, offset: 0xC
| __IO uint32_t TRNG_Type::PKRRNG |
Poker Range Register, offset: 0x8
| __I uint32_t { ... } ::PKRSQ |
Poker Square Calculation Result Register, offset: 0xC
| __I uint32_t TRNG_Type::PKRSQ |
Poker Square Calculation Result Register, offset: 0xC
| __IO uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_CONTROL |
PKT_CONTROL, offset: 0x4
| __I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_FIFO_RD_LEVEL |
PKT_FIFO_RD_LEVEL, offset: 0x14
| __I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_FIFO_WR_LEVEL |
PKT_FIFO_WR_LEVEL, offset: 0x10
| __I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_RX_PAYLOAD |
PKT_RX_PAYLOAD, offset: 0x18
| __I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_RX_PKT_HEADER |
PKT_RX_PKT_HEADER, offset: 0x1C
| __I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_STATUS |
PKT_STATUS, offset: 0xC
| __I uint16_t MCM_Type::PLAMC |
Crossbar Switch (AXBS) Master Configuration, offset: 0xA
| __I uint16_t MCM_Type::PLASC |
Crossbar Switch (AXBS) Slave Configuration, offset: 0x8
| __IO uint32_t CCM_ANALOG_Type::PLL_ARM |
Analog ARM PLL control Register, offset: 0x0
| __IO uint32_t CCM_ANALOG_Type::PLL_ARM_CLR |
Analog ARM PLL control Register, offset: 0x8
| __IO uint32_t CCM_ANALOG_Type::PLL_ARM_SET |
Analog ARM PLL control Register, offset: 0x4
| __IO uint32_t CCM_ANALOG_Type::PLL_ARM_TOG |
Analog ARM PLL control Register, offset: 0xC
| __IO uint32_t CCM_ANALOG_Type::PLL_AUDIO |
Analog Audio PLL control Register, offset: 0x70
| __IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_CLR |
Analog Audio PLL control Register, offset: 0x78
| __IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_CTRL |
PLL_AUDIO_CTRL_REGISTER, offset: 0x300
| __IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_DENOM |
Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90
| __IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_DENOMINATOR |
PLL_AUDIO_DENOMINATOR_REGISTER, offset: 0x320
| __IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_DIV_SELECT |
PLL_AUDIO_DIV_SELECT_REGISTER, offset: 0x340
| __IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_NUM |
Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80
| __IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_NUMERATOR |
PLL_AUDIO_NUMERATOR_REGISTER, offset: 0x330
| __IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_SET |
Analog Audio PLL control Register, offset: 0x74
| __IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_SS |
PLL_AUDIO_SS_REGISTER, offset: 0x310
| __IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_TOG |
Analog Audio PLL control Register, offset: 0x7C
| __IO uint32_t CCM_ANALOG_Type::PLL_ENET |
Analog ENET PLL Control Register, offset: 0xE0
| __IO uint32_t CCM_ANALOG_Type::PLL_ENET_CLR |
Analog ENET PLL Control Register, offset: 0xE8
| __IO uint32_t CCM_ANALOG_Type::PLL_ENET_SET |
Analog ENET PLL Control Register, offset: 0xE4
| __IO uint32_t CCM_ANALOG_Type::PLL_ENET_TOG |
Analog ENET PLL Control Register, offset: 0xEC
| __IO uint32_t ANADIG_PMU_Type::PLL_LDO_STBY_EN_SP |
PLL_LDO_STBY_EN_SP_REGISTER, offset: 0x740
| __IO uint32_t USBPHY_Type::PLL_SIC |
USB PHY PLL Control/Status Register, offset: 0xA0
| __IO uint32_t USBPHY_Type::PLL_SIC_CLR |
USB PHY PLL Control/Status Register, offset: 0xA8
| __IO uint32_t USBPHY_Type::PLL_SIC_SET |
USB PHY PLL Control/Status Register, offset: 0xA4
| __IO uint32_t USBPHY_Type::PLL_SIC_TOG |
USB PHY PLL Control/Status Register, offset: 0xAC
| __IO uint32_t CCM_ANALOG_Type::PLL_SYS |
Analog System PLL Control Register, offset: 0x30
| __IO uint32_t CCM_ANALOG_Type::PLL_SYS_CLR |
Analog System PLL Control Register, offset: 0x38
| __IO uint32_t CCM_ANALOG_Type::PLL_SYS_DENOM |
Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60
| __IO uint32_t CCM_ANALOG_Type::PLL_SYS_NUM |
Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50
| __IO uint32_t CCM_ANALOG_Type::PLL_SYS_SET |
Analog System PLL Control Register, offset: 0x34
| __IO uint32_t CCM_ANALOG_Type::PLL_SYS_SS |
528MHz System PLL Spread Spectrum Register, offset: 0x40
| __IO uint32_t CCM_ANALOG_Type::PLL_SYS_TOG |
Analog System PLL Control Register, offset: 0x3C
| __IO uint32_t CCM_ANALOG_Type::PLL_USB1 |
Analog USB1 480MHz PLL Control Register, offset: 0x10
| __IO uint32_t CCM_ANALOG_Type::PLL_USB1_CLR |
Analog USB1 480MHz PLL Control Register, offset: 0x18
| __IO uint32_t CCM_ANALOG_Type::PLL_USB1_SET |
Analog USB1 480MHz PLL Control Register, offset: 0x14
| __IO uint32_t CCM_ANALOG_Type::PLL_USB1_TOG |
Analog USB1 480MHz PLL Control Register, offset: 0x1C
| __IO uint32_t CCM_ANALOG_Type::PLL_USB2 |
Analog USB2 480MHz PLL Control Register, offset: 0x20
| __IO uint32_t CCM_ANALOG_Type::PLL_USB2_CLR |
Analog USB2 480MHz PLL Control Register, offset: 0x28
| __IO uint32_t CCM_ANALOG_Type::PLL_USB2_SET |
Analog USB2 480MHz PLL Control Register, offset: 0x24
| __IO uint32_t CCM_ANALOG_Type::PLL_USB2_TOG |
Analog USB2 480MHz PLL Control Register, offset: 0x2C
| __IO uint32_t CCM_ANALOG_Type::PLL_VIDEO |
Analog Video PLL control Register, offset: 0xA0
| __IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_CLR |
Analog Video PLL control Register, offset: 0xA8
| __IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_CTRL |
PLL_VIDEO_CTRL_REGISTER, offset: 0x350
| __IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_DENOM |
Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0
| __IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_DENOMINATOR |
PLL_VIDEO_DENOMINATOR_REGISTER, offset: 0x370
| __IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_DIV_SELECT |
PLL_VIDEO_DIV_SELECT_REGISTER, offset: 0x390
| __IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_NUM |
Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0
| __IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_NUMERATOR |
PLL_VIDEO_NUMERATOR_REGISTER, offset: 0x380
| __IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_SET |
Analog Video PLL control Register, offset: 0xA4
| __IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_SS |
PLL_VIDEO_SS_REGISTER, offset: 0x360
| __IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_TOG |
Analog Video PLL control Register, offset: 0xAC
| __I uint16_t MCM_Type::PLREV |
SoC-defined platform revision, offset: 0x0
| __IO uint32_t ANADIG_PMU_Type::PMU_BIAS_CTRL |
PMU_BIAS_CTRL_REGISTER, offset: 0x550
| __IO uint32_t ANADIG_PMU_Type::PMU_BIAS_CTRL2 |
PMU_BIAS_CTRL2_REGISTER, offset: 0x560
| __IO uint32_t ANADIG_LDO_SNVS_Type::PMU_LDO_LPSR_ANA |
PMU_LDO_LPSR_ANA_REGISTER, offset: 0x510
| __IO uint32_t ANADIG_LDO_SNVS_Type::PMU_LDO_LPSR_DIG |
PMU_LDO_LPSR_DIG_REGISTER, offset: 0x530
| __IO uint32_t ANADIG_LDO_SNVS_Type::PMU_LDO_LPSR_DIG_2 |
PMU_LDO_LPSR_DIG_2_REGISTER, offset: 0x520
| __IO uint32_t ANADIG_PMU_Type::PMU_LDO_PLL |
PMU_LDO_PLL_REGISTER, offset: 0x500
| __IO uint32_t ANADIG_LDO_SNVS_DIG_Type::PMU_LDO_SNVS_DIG |
PMU_LDO_SNVS_DIG_REGISTER, offset: 0x540
| __IO uint32_t ANADIG_PMU_Type::PMU_POWER_DETECT_CTRL |
PMU_POWER_DETECT_CTRL_REGISTER, offset: 0x580
| __IO uint32_t ANADIG_PMU_Type::PMU_REF_CTRL |
PMU_REF_CTRL_REGISTER, offset: 0x570
| __IO uint32_t PXP_Type::PORTER_DUFF_CTRL |
PXP Alpha Engine A Control Register., offset: 0x440
| __IO uint32_t USB_Type::PORTSC1 |
Port Status & Control, offset: 0x184
| __IO uint16_t ENC_Type::POSD |
Position Difference Counter Register, offset: 0x6
| __I uint16_t ENC_Type::POSDH |
Position Difference Hold Register, offset: 0x8
| __I uint16_t ENC_Type::POSDPER |
Position Difference Period Counter Register, offset: 0x2C
| __I uint16_t ENC_Type::POSDPERBFR |
Position Difference Period Buffer Register, offset: 0x2E
| __I uint16_t ENC_Type::POSDPERH |
Position Difference Period Hold Register, offset: 0x30
| __IO uint32_t PXP_Type::POWER |
PXP Power Control Register, offset: 0x320
| __IO uint32_t PGMC_PPC_Type::PPC_AUTHEN_CTRL |
PPC Authentication Control, offset: 0x4
| __IO uint32_t PGMC_PPC_Type::PPC_MODE |
PPC Mode, offset: 0x10
| __IO uint32_t PGMC_PPC_Type::PPC_STBY_CM_CTRL |
PPC standby CPU mode control, offset: 0x14
| __IO uint32_t PGMC_PPC_Type::PPC_STBY_SP_CTRL |
PPC standby Setpoint control, offset: 0x18
| __I uint32_t MIPI_CSI2RX_Type::PPI_ERRCONTROL |
ErrControl Status Register, offset: 0x128
| __I uint32_t MIPI_CSI2RX_Type::PPI_ERRESC |
ErrEsc Status Register, offset: 0x120
| __I uint32_t MIPI_CSI2RX_Type::PPI_ERRSOT_HS |
ERRSot HS Status Register, offset: 0x118
| __I uint32_t MIPI_CSI2RX_Type::PPI_ERRSOTSYNC_HS |
ErrSotSync HS Status Register, offset: 0x11C
| __I uint32_t MIPI_CSI2RX_Type::PPI_ERRSYNCESC |
ErrSyncEsc Status Register, offset: 0x124
| __IO uint32_t GPT_Type::PR |
GPT Prescaler Register, offset: 0x4
| __IO uint32_t TSC_Type::PRE_CHARGE_TIME |
Pre-charge Time, offset: 0x10
| __I uint32_t USDHC_Type::PRES_STATE |
Present State, offset: 0x24
| __IO uint32_t USDHC_Type::PROT_CTRL |
Protocol Control, offset: 0x28
| __IO uint32_t PXP_Type::PS_BACKGROUND |
PS Background Color, offset: 0x100
| __IO uint32_t PXP_Type::PS_BUF |
PS Input Buffer Address, offset: 0xC0
| __IO uint32_t PXP_Type::PS_CLRKEYHIGH |
PS Color Key High, offset: 0x140
| __IO uint32_t PXP_Type::PS_CLRKEYLOW |
PS Color Key Low, offset: 0x130
| __IO uint32_t PXP_Type::PS_CTRL |
Processed Surface (PS) Control Register, offset: 0xB0
| __IO uint32_t PXP_Type::PS_CTRL_CLR |
Processed Surface (PS) Control Register, offset: 0xB8
| __IO uint32_t PXP_Type::PS_CTRL_SET |
Processed Surface (PS) Control Register, offset: 0xB4
| __IO uint32_t PXP_Type::PS_CTRL_TOG |
Processed Surface (PS) Control Register, offset: 0xBC
| __IO uint32_t PXP_Type::PS_OFFSET |
PS Scale Offset Register, offset: 0x120
| __IO uint32_t PXP_Type::PS_PITCH |
Processed Surface Pitch, offset: 0xF0
| __IO uint32_t PXP_Type::PS_SCALE |
PS Scale Factor Register, offset: 0x110
| __IO uint32_t PXP_Type::PS_UBUF |
PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0
| __IO uint32_t PXP_Type::PS_VBUF |
PS V/Cr Input Buffer Address, offset: 0xE0
| __IO uint32_t LMEM_Type::PSCCR |
PS bus Cache control register, offset: 0x800
| __IO uint32_t LMEM_Type::PSCCVR |
PS bus Cache read/write value register, offset: 0x80C
| __IO uint32_t LMEM_Type::PSCLCR |
PS bus Cache line control register, offset: 0x804
| __IO uint32_t LMEM_Type::PSCSAR |
PS bus Cache search address register, offset: 0x808
| __I uint32_t GPIO_Type::PSR |
GPIO pad status register, offset: 0x8
| __I uint32_t DAC_Type::PTR |
DAC FIFO Pointer Register, offset: 0x10
| __IO uint32_t KEY_MANAGER_Type::PUF_KEY_CTRL |
CSR PUF Key Control, offset: 0x30
| __IO uint32_t USBPHY_Type::PWD |
USB PHY Power-Down Register, offset: 0x0
| __IO uint32_t USBPHY_Type::PWD_CLR |
USB PHY Power-Down Register, offset: 0x8
| __IO uint32_t USBPHY_Type::PWD_SET |
USB PHY Power-Down Register, offset: 0x4
| __IO uint32_t USBPHY_Type::PWD_TOG |
USB PHY Power-Down Register, offset: 0xC
| __IO uint32_t PUF_Type::PWRCTRL |
PUF Power Control Of RAM, offset: 0x108
| __I uint32_t CAAM_Type::PX_SDID_JR |
Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10
| __I uint32_t { ... } ::PX_SDID_JR |
Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10
| __I uint32_t { ... } ::PX_SDID_JR |
Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10
| __I uint32_t CAAM_Type::PX_SDID_PG0 |
Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10
| __I uint32_t { ... } ::PX_SDID_PG0 |
Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10
| __I uint32_t { ... } ::PX_SDID_PG0 |
Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10
| __IO uint32_t CAAM_Type::PX_SMAG1_JR |
Secure Memory Access Group Registers, array offset: 0x10A0C, array step: index*0x10000, index2*0x10
| __IO uint32_t { ... } ::PX_SMAG1_JR |
Secure Memory Access Group Registers, array offset: 0x10A0C, array step: index*0x10000, index2*0x10
| __IO uint32_t { ... } ::PX_SMAG1_JR |
Secure Memory Access Group Registers, array offset: 0x10A0C, array step: index*0x10000, index2*0x10
| __IO uint32_t CAAM_Type::PX_SMAG1_PG0 |
Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10
| __IO uint32_t { ... } ::PX_SMAG1_PG0 |
Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10
| __IO uint32_t { ... } ::PX_SMAG1_PG0 |
Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10
| __IO uint32_t CAAM_Type::PX_SMAG2_JR |
Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10
| __IO uint32_t { ... } ::PX_SMAG2_JR |
Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10
| __IO uint32_t { ... } ::PX_SMAG2_JR |
Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10
| __IO uint32_t { ... } ::PX_SMAG2_PG0 |
Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10
| __IO uint32_t CAAM_Type::PX_SMAG2_PG0 |
Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10
| __IO uint32_t { ... } ::PX_SMAG2_PG0 |
Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10
| __IO uint32_t { ... } ::PX_SMAPR_JR |
Secure Memory Access Permissions register, array offset: 0x10A04, array step: index*0x10000, index2*0x10
| __IO uint32_t CAAM_Type::PX_SMAPR_JR |
Secure Memory Access Permissions register, array offset: 0x10A04, array step: index*0x10000, index2*0x10
| __IO uint32_t { ... } ::PX_SMAPR_JR |
Secure Memory Access Permissions register, array offset: 0x10A04, array step: index*0x10000, index2*0x10
| __IO uint32_t { ... } ::PX_SMAPR_PG0 |
Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10
| __IO uint32_t CAAM_Type::PX_SMAPR_PG0 |
Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10
| __IO uint32_t { ... } ::PX_SMAPR_PG0 |
Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10
| __IO uint32_t ENET_Type::QOS |
QOS Scheme, offset: 0x1F0
| __I uint32_t ADC_Type::R[8] |
Data result register for HW triggers, array offset: 0x24, array step: 0x4
| __IO uint32_t ENET_Type::RACC |
Receive Accelerator Function Configuration, offset: 0x1C4
| __IO uint32_t ENET_Type::RAEM |
Receive FIFO Almost Empty Threshold, offset: 0x198
| __IO uint32_t ENET_Type::RAFL |
Receive FIFO Almost Full Threshold, offset: 0x19C
| __IO uint32_t TMPSNS_Type::RANGE0 |
Temperature Sensor Range Register 0, offset: 0x20
| __IO uint32_t TMPSNS_Type::RANGE0_CLR |
Temperature Sensor Range Register 0, offset: 0x28
| __IO uint32_t TMPSNS_Type::RANGE0_SET |
Temperature Sensor Range Register 0, offset: 0x24
| __IO uint32_t TMPSNS_Type::RANGE0_TOG |
Temperature Sensor Range Register 0, offset: 0x2C
| __IO uint32_t TMPSNS_Type::RANGE1 |
Temperature Sensor Range Register 1, offset: 0x30
| __IO uint32_t TMPSNS_Type::RANGE1_CLR |
Temperature Sensor Range Register 1, offset: 0x38
| __IO uint32_t TMPSNS_Type::RANGE1_SET |
Temperature Sensor Range Register 1, offset: 0x34
| __IO uint32_t TMPSNS_Type::RANGE1_TOG |
Temperature Sensor Range Register 1, offset: 0x3C
| __IO uint32_t PDM_Type::RANGE_CTRL |
PDM Range Control register, offset: 0x74
| __IO uint32_t PDM_Type::RANGE_STAT |
PDM Range Status register, offset: 0x7C
| __IO uint32_t ANADIG_PMU_Type::RBB_LPSR_CONFIGURE |
RBB_LPSR_CONFIGURE_REGISTER, offset: 0x790
| __IO uint32_t ANADIG_PMU_Type::RBB_LPSR_ENABLE_SP |
RBB_LPSR_ENABLE_SP_REGISTER, offset: 0x720
| __IO uint32_t ANADIG_PMU_Type::RBB_LPSR_STBY_EN_SP |
RBB_LPSR_STBY_EN_SP_REGISTER, offset: 0x770
| __IO uint32_t ANADIG_PMU_Type::RBB_SOC_CONFIGURE |
RBB_SOC_CONFIGURE_REGISTER, offset: 0x7A0
| __IO uint32_t ANADIG_PMU_Type::RBB_SOC_ENABLE_SP |
RBB_SOC_ENABLE_SP_REGISTER, offset: 0x710
| __IO uint32_t ANADIG_PMU_Type::RBB_SOC_STBY_EN_SP |
RBB_SOC_STBY_EN_SP_REGISTER, offset: 0x760
| __IO uint32_t CAAM_Type::RCMD |
RTIC Command Register, offset: 0x6000C
| __IO uint32_t ENET_Type::RCMR |
Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4
| __IO uint32_t ENET_Type::RCR |
Receive Control Register, offset: 0x84
| __IO uint32_t I2S_Type::RCR1 |
SAI Receive Configuration 1 Register, offset: 0x8C
Receive Configuration 1, offset: 0x8C
| __IO uint32_t I2S_Type::RCR2 |
SAI Receive Configuration 2 Register, offset: 0x90
Receive Configuration 2, offset: 0x90
| __IO uint32_t I2S_Type::RCR3 |
SAI Receive Configuration 3 Register, offset: 0x94
Receive Configuration 3, offset: 0x94
| __IO uint32_t I2S_Type::RCR4 |
SAI Receive Configuration 4 Register, offset: 0x98
Receive Configuration 4, offset: 0x98
| __IO uint32_t I2S_Type::RCR5 |
SAI Receive Configuration 5 Register, offset: 0x9C
Receive Configuration 5, offset: 0x9C
| __IO uint32_t I2S_Type::RCSR |
SAI Receive Control Register, offset: 0x88
Receive Control, offset: 0x88
| __IO uint32_t CAAM_Type::RCTL |
RTIC Control Register, offset: 0x60014
| __IO uint32_t ENET_Type::RDAR |
Receive Descriptor Active Register - Ring 0, offset: 0x10
| __IO uint32_t ENET_Type::RDAR1 |
Receive Descriptor Active Register - Ring 1, offset: 0x1E0
| __IO uint32_t ENET_Type::RDAR2 |
Receive Descriptor Active Register - Ring 2, offset: 0x1E8
| __O uint32_t CAAM_Type::RDHBUF |
RNG DRNG Hash Buffer Register, offset: 0x6E8
| __IO uint32_t CAAM_Type::RDHCNTL |
RNG DRNG Hash Control Register, offset: 0x6E0
| __I uint32_t CAAM_Type::RDHDIG |
RNG DRNG Hash Digest Register, offset: 0x6E4
| __I uint32_t CAAM_Type::RDINT0 |
RNG DRNG State Handle 0 Reseed Interval Register, offset: 0x6D0
| __I uint32_t CAAM_Type::RDINT1 |
RNG DRNG State Handle 1 Reseed Interval Register, offset: 0x6D4
| __I uint32_t I2S_Type::RDR |
SAI Receive Data Register, array offset: 0xA0, array step: 0x4
Receive Data, array offset: 0xA0, array step: 0x4
| __I uint32_t LPSPI_Type::RDR |
Receive Data Register, offset: 0x74
Receive Data, offset: 0x74
| __IO uint32_t ENET_Type::RDSR |
Receive Descriptor Ring 0 Start Register, offset: 0x180
| __IO uint32_t ENET_Type::RDSR1 |
Receive Descriptor Ring 1 Start Register, offset: 0x160
| __IO uint32_t ENET_Type::RDSR2 |
Receive Descriptor Ring 2 Start Register, offset: 0x16C
| __I uint32_t CAAM_Type::RDSTA |
RNG DRNG Status Register, offset: 0x6C0
| __IO uint32_t OCOTP_Type::READ_CTRL |
OTP Controller Write Data Register, offset: 0x30
OTP Controller Read Control Register, offset: 0x30
| __IO uint32_t OCOTP_Type::READ_FUSE_DATA |
OTP Controller Read Data Register, offset: 0x40
OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register, array offset: 0x100, array step: 0x10
| __IO uint32_t { ... } ::READ_FUSE_DATA |
OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register, array offset: 0x100, array step: 0x10
| __IO uint32_t { ... } ::READ_FUSE_DATA |
OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register, array offset: 0x100, array step: 0x10
| __I uint32_t ANADIG_PMU_Type::REFTOP_OTP_TRIM_VALUE |
REFTOP_OTP_TRIM_VALUE_REGISTER, offset: 0x7B0
| __IO uint32_t DCDC_Type::REG0 |
DCDC Register 0, offset: 0x0
DCDC Register 0, offset: 0x8
| __IO uint32_t DCDC_Type::REG1 |
DCDC Register 1, offset: 0x4
DCDC Register 1, offset: 0xC
| __IO uint32_t DCDC_Type::REG10 |
DCDC Register 10, offset: 0x34
| __IO uint32_t DCDC_Type::REG11 |
DCDC Register 11, offset: 0x38
| __IO uint32_t DCDC_Type::REG12 |
DCDC Register 12, offset: 0x3C
| __IO uint32_t DCDC_Type::REG13 |
DCDC Register 13, offset: 0x40
| __IO uint32_t DCDC_Type::REG14 |
DCDC Register 14, offset: 0x44
| __IO uint32_t DCDC_Type::REG15 |
DCDC Register 15, offset: 0x48
| __IO uint32_t DCDC_Type::REG16 |
DCDC Register 16, offset: 0x4C
| __IO uint32_t DCDC_Type::REG17 |
DCDC Register 17, offset: 0x50
| __IO uint32_t DCDC_Type::REG18 |
DCDC Register 18, offset: 0x54
| __IO uint32_t DCDC_Type::REG19 |
DCDC Register 19, offset: 0x58
| __IO uint32_t DCDC_Type::REG2 |
DCDC Register 2, offset: 0x8
DCDC Register 2, offset: 0x10
| __IO uint32_t DCDC_Type::REG20 |
DCDC Register 20, offset: 0x5C
| __IO uint32_t DCDC_Type::REG21 |
DCDC Register 21, offset: 0x60
| __IO uint32_t DCDC_Type::REG22 |
DCDC Register 22, offset: 0x64
| __IO uint32_t DCDC_Type::REG23 |
DCDC Register 23, offset: 0x68
| __IO uint32_t DCDC_Type::REG24 |
DCDC Register 24, offset: 0x6C
| __IO uint32_t DCDC_Type::REG3 |
DCDC Register 3, offset: 0xC
DCDC Register 3, offset: 0x14
| __IO uint32_t DCDC_Type::REG4 |
DCDC Register 4, offset: 0x18
| __IO uint32_t DCDC_Type::REG5 |
DCDC Register 5, offset: 0x1C
| __IO uint32_t DCDC_Type::REG6 |
DCDC Register 6, offset: 0x20
| __IO uint32_t DCDC_Type::REG7 |
DCDC Register 7, offset: 0x24
| __IO uint32_t DCDC_Type::REG7P |
DCDC Register 7 plus, offset: 0x28
| __IO uint32_t DCDC_Type::REG8 |
DCDC Register 8, offset: 0x2C
| __IO uint32_t DCDC_Type::REG9 |
DCDC Register 9, offset: 0x30
| __IO uint32_t PMU_Type::REG_1P1 |
Regulator 1P1 Register, offset: 0x110
| __IO uint32_t PMU_Type::REG_1P1_CLR |
Regulator 1P1 Register, offset: 0x118
| __IO uint32_t PMU_Type::REG_1P1_SET |
Regulator 1P1 Register, offset: 0x114
| __IO uint32_t PMU_Type::REG_1P1_TOG |
Regulator 1P1 Register, offset: 0x11C
| __IO uint32_t PMU_Type::REG_2P5 |
Regulator 2P5 Register, offset: 0x130
| __IO uint32_t PMU_Type::REG_2P5_CLR |
Regulator 2P5 Register, offset: 0x138
| __IO uint32_t PMU_Type::REG_2P5_SET |
Regulator 2P5 Register, offset: 0x134
| __IO uint32_t PMU_Type::REG_2P5_TOG |
Regulator 2P5 Register, offset: 0x13C
| __IO uint32_t PMU_Type::REG_3P0 |
Regulator 3P0 Register, offset: 0x120
| __IO uint32_t PMU_Type::REG_3P0_CLR |
Regulator 3P0 Register, offset: 0x128
| __IO uint32_t PMU_Type::REG_3P0_SET |
Regulator 3P0 Register, offset: 0x124
| __IO uint32_t PMU_Type::REG_3P0_TOG |
Regulator 3P0 Register, offset: 0x12C
| __IO uint32_t PMU_Type::REG_CORE |
Digital Regulator Core Register, offset: 0x140
| __IO uint32_t PMU_Type::REG_CORE_CLR |
Digital Regulator Core Register, offset: 0x148
| __IO uint32_t PMU_Type::REG_CORE_SET |
Digital Regulator Core Register, offset: 0x144
| __IO uint32_t PMU_Type::REG_CORE_TOG |
Digital Regulator Core Register, offset: 0x14C
| __IO uint32_t IEE_Type::REGATTR |
IEE Region 0 Attribute Register...IEE Region 7 Attribute Register., array offset: 0x100, array step: 0x100
| __IO uint32_t { ... } ::REGATTR |
IEE Region 0 Attribute Register...IEE Region 7 Attribute Register., array offset: 0x100, array step: 0x100
| __IO uint32_t { ... } ::REGATTR |
IEE Region 0 Attribute Register...IEE Region 7 Attribute Register., array offset: 0x100, array step: 0x100
| __IO uint32_t IEE_APC_Type::REGION0_BOT_ADDR |
Start address of IEE region (n), offset: 0x4
| __IO uint32_t IEE_APC_Type::REGION0_RDC_D0 |
Region control of core domain 0 for region (n), offset: 0x8
| __IO uint32_t IEE_APC_Type::REGION0_RDC_D1 |
Region control of core domain 1 for region (n), offset: 0xC
| __IO uint32_t IEE_APC_Type::REGION0_TOP_ADDR |
End address of IEE region (n), offset: 0x0
| __IO uint32_t BEE_Type::REGION1_BOT |
Region1 Bottom Address Register, offset: 0x44
| __IO uint32_t IEE_APC_Type::REGION1_BOT_ADDR |
Start address of IEE region (n), offset: 0x14
| __IO uint32_t IEE_APC_Type::REGION1_RDC_D0 |
Region control of core domain 0 for region (n), offset: 0x18
| __IO uint32_t IEE_APC_Type::REGION1_RDC_D1 |
Region control of core domain 1 for region (n), offset: 0x1C
| __IO uint32_t BEE_Type::REGION1_TOP |
Region1 Top Address Register, offset: 0x40
| __IO uint32_t IEE_APC_Type::REGION1_TOP_ADDR |
End address of IEE region (n), offset: 0x10
| __IO uint32_t IEE_APC_Type::REGION2_BOT_ADDR |
Start address of IEE region (n), offset: 0x24
| __IO uint32_t IEE_APC_Type::REGION2_RDC_D0 |
Region control of core domain 0 for region (n), offset: 0x28
| __IO uint32_t IEE_APC_Type::REGION2_RDC_D1 |
Region control of core domain 1 for region (n), offset: 0x2C
| __IO uint32_t IEE_APC_Type::REGION2_TOP_ADDR |
End address of IEE region (n), offset: 0x20
| __IO uint32_t IEE_APC_Type::REGION3_BOT_ADDR |
Start address of IEE region (n), offset: 0x34
| __IO uint32_t IEE_APC_Type::REGION3_RDC_D0 |
Region control of core domain 0 for region (n), offset: 0x38
| __IO uint32_t IEE_APC_Type::REGION3_RDC_D1 |
Region control of core domain 1 for region (n), offset: 0x3C
| __IO uint32_t IEE_APC_Type::REGION3_TOP_ADDR |
End address of IEE region (n), offset: 0x30
| __IO uint32_t IEE_APC_Type::REGION4_BOT_ADDR |
Start address of IEE region (n), offset: 0x44
| __IO uint32_t IEE_APC_Type::REGION4_RDC_D0 |
Region control of core domain 0 for region (n), offset: 0x48
| __IO uint32_t IEE_APC_Type::REGION4_RDC_D1 |
Region control of core domain 1 for region (n), offset: 0x4C
| __IO uint32_t IEE_APC_Type::REGION4_TOP_ADDR |
End address of IEE region (n), offset: 0x40
| __IO uint32_t IEE_APC_Type::REGION5_BOT_ADDR |
Start address of IEE region (n), offset: 0x54
| __IO uint32_t IEE_APC_Type::REGION5_RDC_D0 |
Region control of core domain 0 for region (n), offset: 0x58
| __IO uint32_t IEE_APC_Type::REGION5_RDC_D1 |
Region control of core domain 1 for region (n), offset: 0x5C
| __IO uint32_t IEE_APC_Type::REGION5_TOP_ADDR |
End address of IEE region (n), offset: 0x50
| __IO uint32_t IEE_APC_Type::REGION6_BOT_ADDR |
Start address of IEE region (n), offset: 0x64
| __IO uint32_t IEE_APC_Type::REGION6_RDC_D0 |
Region control of core domain 0 for region (n), offset: 0x68
| __IO uint32_t IEE_APC_Type::REGION6_RDC_D1 |
Region control of core domain 1 for region (n), offset: 0x6C
| __IO uint32_t IEE_APC_Type::REGION6_TOP_ADDR |
End address of IEE region (n), offset: 0x60
| __IO uint32_t IEE_APC_Type::REGION7_BOT_ADDR |
Start address of IEE region (n), offset: 0x74
| __IO uint32_t IEE_APC_Type::REGION7_RDC_D0 |
Region control of core domain 0 for region (n), offset: 0x78
| __IO uint32_t IEE_APC_Type::REGION7_RDC_D1 |
Region control of core domain 1 for region (n), offset: 0x7C
| __IO uint32_t IEE_APC_Type::REGION7_TOP_ADDR |
End address of IEE region (n), offset: 0x70
| __O uint32_t { ... } ::REGKEY1[8] |
IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register, array offset: 0x140, array step: index*0x100, index2*0x4
| __O uint32_t IEE_Type::REGKEY1[8] |
IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register, array offset: 0x140, array step: index*0x100, index2*0x4
| __O uint32_t { ... } ::REGKEY1[8] |
IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register, array offset: 0x140, array step: index*0x100, index2*0x4
| __O uint32_t { ... } ::REGKEY2[8] |
IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register, array offset: 0x180, array step: index*0x100, index2*0x4
| __O uint32_t IEE_Type::REGKEY2[8] |
IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register, array offset: 0x180, array step: index*0x100, index2*0x4
| __O uint32_t { ... } ::REGKEY2[8] |
IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register, array offset: 0x180, array step: index*0x100, index2*0x4
| __IO uint32_t { ... } ::REGPO |
IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register, array offset: 0x108, array step: 0x100
| __IO uint32_t IEE_Type::REGPO |
IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register, array offset: 0x108, array step: 0x100
| __IO uint32_t { ... } ::REGPO |
IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register, array offset: 0x108, array step: 0x100
| __IO uint32_t CAAM_Type::REIE |
Recoverable Error Interrupt Enable, offset: 0xB04
| __I uint32_t CAAM_Type::REIF |
Recoverable Error Interrupt Force, offset: 0xB08
| __IO uint32_t CAAM_Type::REIH |
Recoverable Error Interrupt Halt, offset: 0xB0C
| __I uint32_t CAAM_Type::REIR0JR |
Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3, array offset: 0x10E00, array step: 0x10000
| __I uint32_t { ... } ::REIR0JR |
Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3, array offset: 0x10E00, array step: 0x10000
| __I uint32_t { ... } ::REIR0JR |
Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3, array offset: 0x10E00, array step: 0x10000
| __I uint32_t CAAM_Type::REIR0RTIC |
Recoverable Error Interrupt Record 0 for RTIC, offset: 0x60E00
| __I uint64_t CAAM_Type::REIR2JR |
Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3, array offset: 0x10E08, array step: 0x10000
| __I uint64_t { ... } ::REIR2JR |
Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3, array offset: 0x10E08, array step: 0x10000
| __I uint64_t { ... } ::REIR2JR |
Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3, array offset: 0x10E08, array step: 0x10000
| __I uint64_t CAAM_Type::REIR2RTIC |
Recoverable Error Interrupt Record 2 for RTIC, offset: 0x60E08
| __I uint32_t { ... } ::REIR4JR |
Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3, array offset: 0x10E10, array step: 0x10000
| __I uint32_t CAAM_Type::REIR4JR |
Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3, array offset: 0x10E10, array step: 0x10000
| __I uint32_t { ... } ::REIR4JR |
Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3, array offset: 0x10E10, array step: 0x10000
| __I uint32_t CAAM_Type::REIR4RTIC |
Recoverable Error Interrupt Record 4 for RTIC, offset: 0x60E10
| __I uint32_t CAAM_Type::REIR5JR |
Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3, array offset: 0x10E14, array step: 0x10000
| __I uint32_t { ... } ::REIR5JR |
Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3, array offset: 0x10E14, array step: 0x10000
| __I uint32_t { ... } ::REIR5JR |
Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3, array offset: 0x10E14, array step: 0x10000
| __I uint32_t CAAM_Type::REIR5RTIC |
Recoverable Error Interrupt Record 5 for RTIC, offset: 0x60E14
| __IO uint32_t CAAM_Type::REIS |
Recoverable Error Interrupt Status, offset: 0xB00
| __IO uint32_t CDOG_Type::RELOAD |
Instruction Timer reload, offset: 0x4
| __IO uint32_t CAAM_Type::REND |
RTIC Endian Register, offset: 0x60034
| __I uint32_t CAN_Type::RERRAR |
Error Report Address register, offset: 0xAF0
| __I uint32_t CAN_Type::RERRDR |
Error Report Data register, offset: 0xAF4
| __I uint32_t CAN_Type::RERRSYNR |
Error Report Syndrome register, offset: 0xAF8
| __I uint32_t ADC_Type::RESFIFO |
LPADC Data Result FIFO Register, offset: 0x300
| __O uint32_t CDOG_Type::RESTART |
RESTART Command, offset: 0x28
| __IO uint16_t ENC_Type::REV |
Revolution Counter Register, offset: 0xA
| __I uint16_t ENC_Type::REVH |
Revolution Hold Register, offset: 0xC
| __I uint32_t FLEXSPI_Type::RFDR |
IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4
| __I uint32_t CSI_Type::RFIFO |
CSI RX FIFO Register, offset: 0x10
| __I uint32_t I2S_Type::RFR |
SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4
Receive FIFO, array offset: 0xC0, array step: 0x4
| __IO uint32_t LCDIF_Type::RGB_ADJUST |
RGB Color Range Adjust, offset: 0x2A0
| __IO uint32_t LCDIF_Type::RGB_ADJUST_CLR |
RGB Color Range Adjust, offset: 0x2A8
| __IO uint32_t LCDIF_Type::RGB_ADJUST_SET |
RGB Color Range Adjust, offset: 0x2A4
| __IO uint32_t LCDIF_Type::RGB_ADJUST_TOG |
RGB Color Range Adjust, offset: 0x2AC
| __IO uint32_t { ... } ::RGD_W0 |
AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40
| __IO uint32_t OTFAD_Type::RGD_W0 |
AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40
| __IO uint32_t { ... } ::RGD_W0 |
AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40
| __IO uint32_t { ... } ::RGD_W1 |
AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40
| __IO uint32_t OTFAD_Type::RGD_W1 |
AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40
| __IO uint32_t { ... } ::RGD_W1 |
AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40
| __IO uint64_t { ... } ::RMA |
RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register, array offset: 0x60100, array step: index*0x20, index2*0x10
| __IO uint64_t CAAM_Type::RMA |
RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register, array offset: 0x60100, array step: index*0x20, index2*0x10
| __IO uint64_t { ... } ::RMA |
RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register, array offset: 0x60100, array step: index*0x20, index2*0x10
| __IO uint32_t CAAM_Type::RMD |
RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31, array offset: 0x60200, array step: index*0x100, index2*0x80, index3*0x4
| __IO uint32_t { ... } ::RML |
RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register, array offset: 0x6010C, array step: index*0x20, index2*0x10
| __IO uint32_t CAAM_Type::RML |
RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register, array offset: 0x6010C, array step: index*0x20, index2*0x10
| __IO uint32_t { ... } ::RML |
RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register, array offset: 0x6010C, array step: index*0x20, index2*0x10
| __I uint32_t ENET_Type::RMON_R_BC_PKT |
Rx Broadcast Packets Statistic Register, offset: 0x288
| __I uint32_t ENET_Type::RMON_R_CRC_ALIGN |
Rx Packets with CRC/Align Error Statistic Register, offset: 0x290
| __I uint32_t ENET_Type::RMON_R_FRAG |
Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C
| __I uint32_t ENET_Type::RMON_R_JAB |
Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0
| __I uint32_t ENET_Type::RMON_R_MC_PKT |
Rx Multicast Packets Statistic Register, offset: 0x28C
| __I uint32_t ENET_Type::RMON_R_OCTETS |
Rx Octets Statistic Register, offset: 0x2C4
| __I uint32_t ENET_Type::RMON_R_OVERSIZE |
Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298
| __I uint32_t ENET_Type::RMON_R_P1024TO2047 |
Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC
| __I uint32_t ENET_Type::RMON_R_P128TO255 |
Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0
| __I uint32_t ENET_Type::RMON_R_P256TO511 |
Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4
| __I uint32_t ENET_Type::RMON_R_P512TO1023 |
Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8
| __I uint32_t ENET_Type::RMON_R_P64 |
Rx 64-Byte Packets Statistic Register, offset: 0x2A8
| __I uint32_t ENET_Type::RMON_R_P65TO127 |
Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC
| __I uint32_t ENET_Type::RMON_R_P_GTE2048 |
Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0
| __I uint32_t ENET_Type::RMON_R_PACKETS |
Rx Packet Count Statistic Register, offset: 0x284
| __I uint32_t ENET_Type::RMON_R_UNDERSIZE |
Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294
| __I uint32_t ENET_Type::RMON_T_BC_PKT |
Tx Broadcast Packets Statistic Register, offset: 0x208
| __I uint32_t ENET_Type::RMON_T_COL |
Tx Collision Count Statistic Register, offset: 0x224
| __I uint32_t ENET_Type::RMON_T_CRC_ALIGN |
Tx Packets with CRC/Align Error Statistic Register, offset: 0x210
| __I uint32_t ENET_Type::RMON_T_FRAG |
Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C
| __I uint32_t ENET_Type::RMON_T_JAB |
Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220
| __I uint32_t ENET_Type::RMON_T_MC_PKT |
Tx Multicast Packets Statistic Register, offset: 0x20C
| __I uint32_t ENET_Type::RMON_T_OCTETS |
Tx Octets Statistic Register, offset: 0x244
| __I uint32_t ENET_Type::RMON_T_OVERSIZE |
Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218
| __I uint32_t ENET_Type::RMON_T_P1024TO2047 |
Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C
| __I uint32_t ENET_Type::RMON_T_P128TO255 |
Tx 128- to 255-byte Packets Statistic Register, offset: 0x230
| __I uint32_t ENET_Type::RMON_T_P256TO511 |
Tx 256- to 511-byte Packets Statistic Register, offset: 0x234
| __I uint32_t ENET_Type::RMON_T_P512TO1023 |
Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238
| __I uint32_t ENET_Type::RMON_T_P64 |
Tx 64-Byte Packets Statistic Register, offset: 0x228
| __I uint32_t ENET_Type::RMON_T_P65TO127 |
Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C
| __I uint32_t ENET_Type::RMON_T_P_GTE2048 |
Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240
| __I uint32_t ENET_Type::RMON_T_PACKETS |
Tx Packet Count Statistic Register, offset: 0x204
| __I uint32_t ENET_Type::RMON_T_UNDERSIZE |
Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214
| __IO uint32_t I2S_Type::RMR |
SAI Receive Mask Register, offset: 0xE0
Receive Mask, offset: 0xE0
| __IO uint32_t ROMC_Type::ROMPATCHA[16] |
ROMC Address Registers, array offset: 0x100, array step: 0x4
| __IO uint32_t ROMC_Type::ROMPATCHCNTL |
ROMC Control Register, offset: 0xF4
| __IO uint32_t ROMC_Type::ROMPATCHD[8] |
ROMC Data Registers, array offset: 0xD4, array step: 0x4
| uint32_t ROMC_Type::ROMPATCHENH |
ROMC Enable Register High, offset: 0xF8
| __IO uint32_t ROMC_Type::ROMPATCHENL |
ROMC Enable Register Low, offset: 0xFC
| __IO uint32_t ROMC_Type::ROMPATCHSR |
ROMC Status Register, offset: 0x208
| __I uint32_t MU_Type::RR |
Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array step: 0x4
Processor A Receive Register 0..Processor A Receive Register 3, array offset: 0x10, array step: 0x4
| __IO uint32_t ENET_Type::RSEM |
Receive FIFO Section Empty Threshold, offset: 0x194
| __IO uint32_t ENET_Type::RSFL |
Receive FIFO Section Full Threshold, offset: 0x190
| __I uint32_t LPSPI_Type::RSR |
Receive Status Register, offset: 0x70
Receive Status, offset: 0x70
| __I uint32_t CAAM_Type::RSTA |
RTIC Status Register, offset: 0x60004
| __IO uint16_t SEMA4_Type::RSTGT |
Semaphores (Secure) Reset Gate n, offset: 0x100
| __IO uint16_t { ... } ::RSTGT_R |
Reset Gate Read, offset: 0x42
| __IO uint16_t RDC_SEMAPHORE_Type::RSTGT_R |
Reset Gate Read, offset: 0x42
| __IO uint16_t { ... } ::RSTGT_R |
Reset Gate Read, offset: 0x42
| __IO uint16_t { ... } ::RSTGT_W |
Reset Gate Write, offset: 0x42
| __IO uint16_t RDC_SEMAPHORE_Type::RSTGT_W |
Reset Gate Write, offset: 0x42
| __IO uint16_t { ... } ::RSTGT_W |
Reset Gate Write, offset: 0x42
| __IO uint16_t SEMA4_Type::RSTNTF |
Semaphores (Secure) Reset IRQ Notification, offset: 0x104
| __I uint32_t CAAM_Type::RTENT |
RNG TRNG Entropy Read Register, array offset: 0x640, array step: 0x4
| __I uint32_t CAAM_Type::RTFRQCNT |
RNG TRNG Frequency Count Register, offset: 0x61C
| __I uint32_t { ... } ::RTFRQCNT |
RNG TRNG Frequency Count Register, offset: 0x61C
| __I uint32_t { ... } ::RTFRQCNT |
RNG TRNG Frequency Count Register, offset: 0x61C
| __IO uint32_t CAAM_Type::RTFRQMAX |
RNG TRNG Frequency Count Maximum Limit Register, offset: 0x61C
| __IO uint32_t { ... } ::RTFRQMAX |
RNG TRNG Frequency Count Maximum Limit Register, offset: 0x61C
| __IO uint32_t { ... } ::RTFRQMAX |
RNG TRNG Frequency Count Maximum Limit Register, offset: 0x61C
| __IO uint32_t CAAM_Type::RTFRQMIN |
RNG TRNG Frequency Count Minimum Limit Register, offset: 0x618
| __IO uint32_t CAAM_Type::RTHR |
RTIC Throttle Register, offset: 0x6001C
| __IO uint32_t CAAM_Type::RTIC_DID |
RTIC DID Register for Block A..RTIC DID Register for Block D, array offset: 0x64, array step: 0x8
| __IO uint32_t { ... } ::RTIC_DID |
RTIC DID Register for Block A..RTIC DID Register for Block D, array offset: 0x64, array step: 0x8
| __IO uint32_t { ... } ::RTIC_DID |
RTIC DID Register for Block A..RTIC DID Register for Block D, array offset: 0x64, array step: 0x8
| __IO uint32_t CAAM_Type::RTIC_OWN |
RTIC OWN Register, offset: 0x60
| __IO uint32_t CAAM_Type::RTMCTL |
RNG TRNG Miscellaneous Control Register, offset: 0x600
| __I uint32_t CAAM_Type::RTPKRCNT10 |
RNG TRNG Statistical Check Poker Count 1 and 0 Register, offset: 0x680
| __I uint32_t CAAM_Type::RTPKRCNT32 |
RNG TRNG Statistical Check Poker Count 3 and 2 Register, offset: 0x684
| __I uint32_t CAAM_Type::RTPKRCNT54 |
RNG TRNG Statistical Check Poker Count 5 and 4 Register, offset: 0x688
| __I uint32_t CAAM_Type::RTPKRCNT76 |
RNG TRNG Statistical Check Poker Count 7 and 6 Register, offset: 0x68C
| __I uint32_t CAAM_Type::RTPKRCNT98 |
RNG TRNG Statistical Check Poker Count 9 and 8 Register, offset: 0x690
| __I uint32_t CAAM_Type::RTPKRCNTBA |
RNG TRNG Statistical Check Poker Count B and A Register, offset: 0x694
| __I uint32_t CAAM_Type::RTPKRCNTDC |
RNG TRNG Statistical Check Poker Count D and C Register, offset: 0x698
| __I uint32_t CAAM_Type::RTPKRCNTFE |
RNG TRNG Statistical Check Poker Count F and E Register, offset: 0x69C
| __IO uint32_t CAAM_Type::RTPKRMAX |
RNG TRNG Poker Maximum Limit Register, offset: 0x60C
| __IO uint32_t { ... } ::RTPKRMAX |
RNG TRNG Poker Maximum Limit Register, offset: 0x60C
| __IO uint32_t { ... } ::RTPKRMAX |
RNG TRNG Poker Maximum Limit Register, offset: 0x60C
| __IO uint32_t CAAM_Type::RTPKRRNG |
RNG TRNG Poker Range Register, offset: 0x608
| __I uint32_t CAAM_Type::RTPKRSQ |
RNG TRNG Poker Square Calculation Result Register, offset: 0x60C
| __I uint32_t { ... } ::RTPKRSQ |
RNG TRNG Poker Square Calculation Result Register, offset: 0x60C
| __I uint32_t { ... } ::RTPKRSQ |
RNG TRNG Poker Square Calculation Result Register, offset: 0x60C
| __IO uint32_t CAAM_Type::RTSBLIM |
RNG TRNG Sparse Bit Limit Register, offset: 0x614
| __IO uint32_t { ... } ::RTSBLIM |
RNG TRNG Sparse Bit Limit Register, offset: 0x614
| __IO uint32_t { ... } ::RTSBLIM |
RNG TRNG Sparse Bit Limit Register, offset: 0x614
| __I uint32_t { ... } ::RTSCMC |
RNG TRNG Statistical Check Monobit Count Register, offset: 0x620
| __I uint32_t CAAM_Type::RTSCMC |
RNG TRNG Statistical Check Monobit Count Register, offset: 0x620
| __I uint32_t { ... } ::RTSCMC |
RNG TRNG Statistical Check Monobit Count Register, offset: 0x620
| __IO uint32_t CAAM_Type::RTSCMISC |
RNG TRNG Statistical Check Miscellaneous Register, offset: 0x604
| __IO uint32_t { ... } ::RTSCML |
RNG TRNG Statistical Check Monobit Limit Register, offset: 0x620
| __IO uint32_t CAAM_Type::RTSCML |
RNG TRNG Statistical Check Monobit Limit Register, offset: 0x620
| __IO uint32_t { ... } ::RTSCML |
RNG TRNG Statistical Check Monobit Limit Register, offset: 0x620
| __I uint32_t { ... } ::RTSCR1C |
RNG TRNG Statistical Check Run Length 1 Count Register, offset: 0x624
| __I uint32_t CAAM_Type::RTSCR1C |
RNG TRNG Statistical Check Run Length 1 Count Register, offset: 0x624
| __I uint32_t { ... } ::RTSCR1C |
RNG TRNG Statistical Check Run Length 1 Count Register, offset: 0x624
| __IO uint32_t CAAM_Type::RTSCR1L |
RNG TRNG Statistical Check Run Length 1 Limit Register, offset: 0x624
| __IO uint32_t { ... } ::RTSCR1L |
RNG TRNG Statistical Check Run Length 1 Limit Register, offset: 0x624
| __IO uint32_t { ... } ::RTSCR1L |
RNG TRNG Statistical Check Run Length 1 Limit Register, offset: 0x624
| __I uint32_t CAAM_Type::RTSCR2C |
RNG TRNG Statistical Check Run Length 2 Count Register, offset: 0x628
| __I uint32_t { ... } ::RTSCR2C |
RNG TRNG Statistical Check Run Length 2 Count Register, offset: 0x628
| __I uint32_t { ... } ::RTSCR2C |
RNG TRNG Statistical Check Run Length 2 Count Register, offset: 0x628
| __IO uint32_t CAAM_Type::RTSCR2L |
RNG TRNG Statistical Check Run Length 2 Limit Register, offset: 0x628
| __IO uint32_t { ... } ::RTSCR2L |
RNG TRNG Statistical Check Run Length 2 Limit Register, offset: 0x628
| __IO uint32_t { ... } ::RTSCR2L |
RNG TRNG Statistical Check Run Length 2 Limit Register, offset: 0x628
| __I uint32_t CAAM_Type::RTSCR3C |
RNG TRNG Statistical Check Run Length 3 Count Register, offset: 0x62C
| __I uint32_t { ... } ::RTSCR3C |
RNG TRNG Statistical Check Run Length 3 Count Register, offset: 0x62C
| __I uint32_t { ... } ::RTSCR3C |
RNG TRNG Statistical Check Run Length 3 Count Register, offset: 0x62C
| __IO uint32_t { ... } ::RTSCR3L |
RNG TRNG Statistical Check Run Length 3 Limit Register, offset: 0x62C
| __IO uint32_t CAAM_Type::RTSCR3L |
RNG TRNG Statistical Check Run Length 3 Limit Register, offset: 0x62C
| __IO uint32_t { ... } ::RTSCR3L |
RNG TRNG Statistical Check Run Length 3 Limit Register, offset: 0x62C
| __I uint32_t CAAM_Type::RTSCR4C |
RNG TRNG Statistical Check Run Length 4 Count Register, offset: 0x630
| __I uint32_t { ... } ::RTSCR4C |
RNG TRNG Statistical Check Run Length 4 Count Register, offset: 0x630
| __I uint32_t { ... } ::RTSCR4C |
RNG TRNG Statistical Check Run Length 4 Count Register, offset: 0x630
| __IO uint32_t CAAM_Type::RTSCR4L |
RNG TRNG Statistical Check Run Length 4 Limit Register, offset: 0x630
| __IO uint32_t { ... } ::RTSCR4L |
RNG TRNG Statistical Check Run Length 4 Limit Register, offset: 0x630
| __IO uint32_t { ... } ::RTSCR4L |
RNG TRNG Statistical Check Run Length 4 Limit Register, offset: 0x630
| __I uint32_t CAAM_Type::RTSCR5C |
RNG TRNG Statistical Check Run Length 5 Count Register, offset: 0x634
| __I uint32_t { ... } ::RTSCR5C |
RNG TRNG Statistical Check Run Length 5 Count Register, offset: 0x634
| __I uint32_t { ... } ::RTSCR5C |
RNG TRNG Statistical Check Run Length 5 Count Register, offset: 0x634
| __IO uint32_t { ... } ::RTSCR5L |
RNG TRNG Statistical Check Run Length 5 Limit Register, offset: 0x634
| __IO uint32_t CAAM_Type::RTSCR5L |
RNG TRNG Statistical Check Run Length 5 Limit Register, offset: 0x634
| __IO uint32_t { ... } ::RTSCR5L |
RNG TRNG Statistical Check Run Length 5 Limit Register, offset: 0x634
| __I uint32_t CAAM_Type::RTSCR6PC |
RNG TRNG Statistical Check Run Length 6+ Count Register, offset: 0x638
| __I uint32_t { ... } ::RTSCR6PC |
RNG TRNG Statistical Check Run Length 6+ Count Register, offset: 0x638
| __I uint32_t { ... } ::RTSCR6PC |
RNG TRNG Statistical Check Run Length 6+ Count Register, offset: 0x638
| __IO uint32_t CAAM_Type::RTSCR6PL |
RNG TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x638
| __IO uint32_t { ... } ::RTSCR6PL |
RNG TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x638
| __IO uint32_t { ... } ::RTSCR6PL |
RNG TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x638
| __IO uint32_t CAAM_Type::RTSDCTL |
RNG TRNG Seed Control Register, offset: 0x610
| __I uint32_t CAAM_Type::RTSTATUS |
RNG TRNG Status Register, offset: 0x63C
| __I uint32_t CAAM_Type::RTTOTSAM |
RNG TRNG Total Samples Register, offset: 0x614
| __I uint32_t { ... } ::RTTOTSAM |
RNG TRNG Total Samples Register, offset: 0x614
| __I uint32_t { ... } ::RTTOTSAM |
RNG TRNG Total Samples Register, offset: 0x614
| __I uint32_t CAAM_Type::RVID |
RTIC Version ID Register, offset: 0xFE0
| __I uint32_t CAAM_Type::RVID_DC01 |
RTIC Version ID Register, offset: 0x80FE0
| __I uint32_t { ... } ::RVID_JR |
RTIC Version ID Register, array offset: 0x10FE0, array step: 0x10000
| __I uint32_t CAAM_Type::RVID_JR |
RTIC Version ID Register, array offset: 0x10FE0, array step: 0x10000
| __I uint32_t { ... } ::RVID_JR |
RTIC Version ID Register, array offset: 0x10FE0, array step: 0x10000
| __I uint32_t CAAM_Type::RVID_RTIC |
RTIC Version ID Register, offset: 0x60FE0
| __IO uint32_t AUDIO_PLL_Type::RW |
Fractional PLL Control Register, offset: 0x0
Fractional PLL Spread Spectrum Control Register, offset: 0x10
Fractional PLL Numerator Control Register, offset: 0x20
Fractional PLL Denominator Control Register, offset: 0x30
| __IO uint32_t { ... } ::RW |
Fractional PLL Control Register, offset: 0x0
| __IO uint32_t { ... } ::RW |
Fractional PLL Spread Spectrum Control Register, offset: 0x10
| __IO uint32_t { ... } ::RW |
Fractional PLL Numerator Control Register, offset: 0x20
| __IO uint32_t { ... } ::RW |
Fractional PLL Denominator Control Register, offset: 0x30
| __IO uint32_t { ... } ::RW |
Fractional PLL Control Register, offset: 0x0
| __IO uint32_t ETHERNET_PLL_Type::RW |
Fractional PLL Control Register, offset: 0x0
Fractional PLL Spread Spectrum Control Register, offset: 0x10
Fractional PLL Numerator Control Register, offset: 0x20
Fractional PLL Denominator Control Register, offset: 0x30
| __IO uint32_t { ... } ::RW |
Fractional PLL Spread Spectrum Control Register, offset: 0x10
| __IO uint32_t { ... } ::RW |
Fractional PLL Numerator Control Register, offset: 0x20
| __IO uint32_t { ... } ::RW |
Fractional PLL Denominator Control Register, offset: 0x30
| __IO uint32_t OSC_RC_400M_Type::RW |
Control Register 0, offset: 0x0
Control Register 1, offset: 0x10
Control Register 2, offset: 0x20
Control Register 3, offset: 0x30
| __IO uint32_t { ... } ::RW |
Control Register 0, offset: 0x0
| __IO uint32_t { ... } ::RW |
Control Register 1, offset: 0x10
| __IO uint32_t { ... } ::RW |
Control Register 2, offset: 0x20
| __IO uint32_t { ... } ::RW |
Control Register 3, offset: 0x30
| __I uint32_t { ... } ::RW |
Status Register 0, offset: 0x50
| __I uint32_t OSC_RC_400M_Type::RW |
Status Register 0, offset: 0x50
Status Register 1, offset: 0x60
Status Register 2, offset: 0x70
| __I uint32_t { ... } ::RW |
Status Register 1, offset: 0x60
| __I uint32_t { ... } ::RW |
Status Register 2, offset: 0x70
| __IO uint32_t { ... } ::RW |
Analog Control Register CTRL0, offset: 0x0
| __IO uint32_t PHY_LDO_Type::RW |
Analog Control Register CTRL0, offset: 0x0
| __I uint32_t PHY_LDO_Type::RW |
Analog Status Register STAT0, offset: 0x50
| __I uint32_t { ... } ::RW |
Analog Status Register STAT0, offset: 0x50
| __IO uint32_t VIDEO_MUX_Type::RW |
Video mux Control Register, offset: 0x0
Pixel Link Master(PLM) Control Register, offset: 0x20
YUV420 Control Register, offset: 0x30
Data Disable Register, offset: 0x50
MIPI DSI Control Register, offset: 0x70
| __IO uint32_t { ... } ::RW |
Video mux Control Register, offset: 0x0
| __IO uint32_t { ... } ::RW |
Pixel Link Master(PLM) Control Register, offset: 0x20
| __IO uint32_t { ... } ::RW |
YUV420 Control Register, offset: 0x30
| __IO uint32_t { ... } ::RW |
Data Disable Register, offset: 0x50
| __IO uint32_t { ... } ::RW |
MIPI DSI Control Register, offset: 0x70
| __IO uint32_t VIDEO_PLL_Type::RW |
Fractional PLL Control Register, offset: 0x0
Fractional PLL Spread Spectrum Control Register, offset: 0x10
Fractional PLL Numerator Control Register, offset: 0x20
Fractional PLL Denominator Control Register, offset: 0x30
| __IO uint32_t { ... } ::RW |
Fractional PLL Control Register, offset: 0x0
| __IO uint32_t { ... } ::RW |
Fractional PLL Spread Spectrum Control Register, offset: 0x10
| __IO uint32_t { ... } ::RW |
Fractional PLL Numerator Control Register, offset: 0x20
| __IO uint32_t { ... } ::RW |
Fractional PLL Denominator Control Register, offset: 0x30
| __IO uint32_t { ... } ::RW |
Analog Control Register CTRL0, offset: 0x0
| __IO uint32_t VMBANDGAP_Type::RW |
Analog Control Register CTRL0, offset: 0x0
| __I uint32_t { ... } ::RW |
Analog Status Register STAT0, offset: 0x50
| __I uint32_t VMBANDGAP_Type::RW |
Analog Status Register STAT0, offset: 0x50
| __IO uint32_t { ... } ::RW |
Fractional PLL Control Register, offset: 0x0
| __IO uint32_t { ... } ::RW |
Fractional PLL Spread Spectrum Control Register, offset: 0x10
| __IO uint32_t { ... } ::RW |
Fractional PLL Numerator Control Register, offset: 0x20
| __IO uint32_t { ... } ::RW |
Fractional PLL Denominator Control Register, offset: 0x30
| __IO uint32_t { ... } ::RW |
Fractional PLL Control Register, offset: 0x0
| __IO uint32_t { ... } ::RW |
Fractional PLL Spread Spectrum Control Register, offset: 0x10
| __IO uint32_t { ... } ::RW |
Fractional PLL Numerator Control Register, offset: 0x20
| __IO uint32_t { ... } ::RW |
Fractional PLL Denominator Control Register, offset: 0x30
| __IO uint32_t { ... } ::RW |
Control Register 0, offset: 0x0
| __IO uint32_t { ... } ::RW |
Control Register 1, offset: 0x10
| __IO uint32_t { ... } ::RW |
Control Register 2, offset: 0x20
| __IO uint32_t { ... } ::RW |
Control Register 3, offset: 0x30
| __I uint32_t { ... } ::RW |
Status Register 0, offset: 0x50
| __I uint32_t { ... } ::RW |
Status Register 1, offset: 0x60
| __I uint32_t { ... } ::RW |
Status Register 2, offset: 0x70
| __IO uint32_t { ... } ::RW |
Analog Control Register CTRL0, offset: 0x0
| __I uint32_t { ... } ::RW |
Analog Status Register STAT0, offset: 0x50
| __IO uint32_t { ... } ::RW |
Video mux Control Register, offset: 0x0
| __IO uint32_t { ... } ::RW |
Pixel Link Master(PLM) Control Register, offset: 0x20
| __IO uint32_t { ... } ::RW |
YUV420 Control Register, offset: 0x30
| __IO uint32_t { ... } ::RW |
Data Disable Register, offset: 0x50
| __IO uint32_t { ... } ::RW |
MIPI DSI Control Register, offset: 0x70
| __IO uint32_t { ... } ::RW |
Fractional PLL Control Register, offset: 0x0
| __IO uint32_t { ... } ::RW |
Fractional PLL Spread Spectrum Control Register, offset: 0x10
| __IO uint32_t { ... } ::RW |
Fractional PLL Numerator Control Register, offset: 0x20
| __IO uint32_t { ... } ::RW |
Fractional PLL Denominator Control Register, offset: 0x30
| __IO uint32_t { ... } ::RW |
Analog Control Register CTRL0, offset: 0x0
| __I uint32_t { ... } ::RW |
Analog Status Register STAT0, offset: 0x50
| __IO uint64_t CAAM_Type::RWDOG |
RTIC Watchdog Timer, offset: 0x60028
| __IO uint32_t USBPHY_Type::RX |
USB PHY Receiver Control Register, offset: 0x20
| __IO uint32_t CAN_Type::RX14MASK |
Rx Buffer 14 Mask Register, offset: 0x14
Rx 14 Mask register, offset: 0x14
| __IO uint32_t CAN_Type::RX15MASK |
Rx Buffer 15 Mask Register, offset: 0x18
Rx 15 Mask register, offset: 0x18
| __I uint32_t EMVSIM_Type::RX_BUF |
Receive Data Read Buffer, offset: 0x2C
| __IO uint32_t USBPHY_Type::RX_CLR |
USB PHY Receiver Control Register, offset: 0x28
| __I uint32_t DSI_HOST_Type::RX_ERROR_STATUS |
RX_ERROR_STATUS, offset: 0x30
| __IO uint32_t USBPHY_Type::RX_SET |
USB PHY Receiver Control Register, offset: 0x24
| __IO uint32_t EMVSIM_Type::RX_STATUS |
Receive Status Register, offset: 0x20
| __IO uint32_t EMVSIM_Type::RX_THD |
Receiver Threshold Register, offset: 0x18
| __IO uint32_t USBPHY_Type::RX_TOG |
USB PHY Receiver Control Register, offset: 0x2C
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::RXCDRP |
RXCDRP, offset: 0x44
| __IO uint32_t CSI_Type::RXCNT |
CSI RX Count Register, offset: 0x14
| __IO uint32_t CAN_Type::RXFGMASK |
Rx FIFO Global Mask Register, offset: 0x48
Rx FIFO Global Mask register, offset: 0x48
| __I uint32_t CAN_Type::RXFIR |
Rx FIFO Information Register, offset: 0x4C
Rx FIFO Information register, offset: 0x4C
| __IO uint32_t ENET_Type::RXIC |
Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4
| __IO uint32_t CAN_Type::RXIMR |
Rx Individual Mask Registers, array offset: 0x880, array step: 0x4
Rx Individual Mask registers, array offset: 0x880, array step: 0x4
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::RXLPRP |
RXLPRP, offset: 0x40
| __IO uint32_t CAN_Type::RXMGMASK |
Rx Mailboxes Global Mask Register, offset: 0x10
Rx Mailboxes Global Mask register, offset: 0x10
| __IO uint32_t CSU_Type::SA |
Secure access register, offset: 0x218
| __IO uint32_t DMA_Type::SADDR |
TCD Source Address, array offset: 0x1000, array step: 0x20
| __IO uint32_t { ... } ::SADDR |
TCD Source Address, array offset: 0x1000, array step: 0x20
| __IO uint32_t { ... } ::SADDR |
TCD Source Address, array offset: 0x1000, array step: 0x20
| __IO uint32_t { ... } ::SADDR |
TCD Source Address, array offset: 0x1000, array step: 0x20
| __IO uint32_t LPI2C_Type::SAMR |
Slave Address Match Register, offset: 0x140
Slave Address Match, offset: 0x140
| __I uint32_t LPI2C_Type::SASR |
Slave Address Status Register, offset: 0x150
Slave Address Status, offset: 0x150
| __IO uint32_t { ... } ::SBLIM |
Sparse Bit Limit Register, offset: 0x14
| __IO uint32_t TRNG_Type::SBLIM |
Sparse Bit Limit Register, offset: 0x14
| __I uint32_t SRC_Type::SBMR1 |
SRC Boot Mode Register 1, offset: 0x4
SRC Boot Mode Register 1, offset: 0x8
| __I uint32_t SRC_Type::SBMR2 |
SRC Boot Mode Register 2, offset: 0x1C
SRC Boot Mode Register 2, offset: 0xC
| __IO uint32_t USB_Type::SBUSCFG |
System Bus Config, offset: 0x90
| __IO uint32_t CAAM_Type::SCFGR |
Security Configuration Register, offset: 0xC
| __IO uint32_t LPI2C_Type::SCFGR1 |
Slave Configuration Register 1, offset: 0x124
Slave Configuration 1, offset: 0x124
| __IO uint32_t LPI2C_Type::SCFGR2 |
Slave Configuration Register 2, offset: 0x128
Slave Configuration 2, offset: 0x128
| __I uint32_t TRNG_Type::SCMC |
Statistical Check Monobit Count Register, offset: 0x20
| __I uint32_t { ... } ::SCMC |
Statistical Check Monobit Count Register, offset: 0x20
| __IO uint32_t TRNG_Type::SCMISC |
Statistical Check Miscellaneous Register, offset: 0x4
| __IO uint32_t TRNG_Type::SCML |
Statistical Check Monobit Limit Register, offset: 0x20
| __IO uint32_t { ... } ::SCML |
Statistical Check Monobit Limit Register, offset: 0x20
| __IO uint8_t CMP_Type::SCR |
CMP Status and Control Register, offset: 0x3
| __IO uint32_t LPI2C_Type::SCR |
Slave Control Register, offset: 0x110
Slave Control, offset: 0x110
| __IO uint32_t SPDIF_Type::SCR |
SPDIF Configuration Register, offset: 0x0
| __IO uint32_t SRC_Type::SCR |
SRC Control Register, offset: 0x0
| __I uint32_t TRNG_Type::SCR1C |
Statistical Check Run Length 1 Count Register, offset: 0x24
| __I uint32_t { ... } ::SCR1C |
Statistical Check Run Length 1 Count Register, offset: 0x24
| __IO uint32_t TRNG_Type::SCR1L |
Statistical Check Run Length 1 Limit Register, offset: 0x24
| __IO uint32_t { ... } ::SCR1L |
Statistical Check Run Length 1 Limit Register, offset: 0x24
| __I uint32_t TRNG_Type::SCR2C |
Statistical Check Run Length 2 Count Register, offset: 0x28
| __I uint32_t { ... } ::SCR2C |
Statistical Check Run Length 2 Count Register, offset: 0x28
| __IO uint32_t TRNG_Type::SCR2L |
Statistical Check Run Length 2 Limit Register, offset: 0x28
| __IO uint32_t { ... } ::SCR2L |
Statistical Check Run Length 2 Limit Register, offset: 0x28
| __I uint32_t { ... } ::SCR3C |
Statistical Check Run Length 3 Count Register, offset: 0x2C
| __I uint32_t TRNG_Type::SCR3C |
Statistical Check Run Length 3 Count Register, offset: 0x2C
| __IO uint32_t { ... } ::SCR3L |
Statistical Check Run Length 3 Limit Register, offset: 0x2C
| __IO uint32_t TRNG_Type::SCR3L |
Statistical Check Run Length 3 Limit Register, offset: 0x2C
| __I uint32_t TRNG_Type::SCR4C |
Statistical Check Run Length 4 Count Register, offset: 0x30
| __I uint32_t { ... } ::SCR4C |
Statistical Check Run Length 4 Count Register, offset: 0x30
| __IO uint32_t TRNG_Type::SCR4L |
Statistical Check Run Length 4 Limit Register, offset: 0x30
| __IO uint32_t { ... } ::SCR4L |
Statistical Check Run Length 4 Limit Register, offset: 0x30
| __I uint32_t { ... } ::SCR5C |
Statistical Check Run Length 5 Count Register, offset: 0x34
| __I uint32_t TRNG_Type::SCR5C |
Statistical Check Run Length 5 Count Register, offset: 0x34
| __IO uint32_t { ... } ::SCR5L |
Statistical Check Run Length 5 Limit Register, offset: 0x34
| __IO uint32_t TRNG_Type::SCR5L |
Statistical Check Run Length 5 Limit Register, offset: 0x34
| __I uint32_t TRNG_Type::SCR6PC |
Statistical Check Run Length 6+ Count Register, offset: 0x38
| __I uint32_t { ... } ::SCR6PC |
Statistical Check Run Length 6+ Count Register, offset: 0x38
| __IO uint32_t TRNG_Type::SCR6PL |
Statistical Check Run Length 6+ Limit Register, offset: 0x38
| __IO uint32_t { ... } ::SCR6PL |
Statistical Check Run Length 6+ Limit Register, offset: 0x38
| __IO uint32_t OCOTP_Type::SCS |
Software Controllable Signals Register, offset: 0x60
| __IO uint32_t OCOTP_Type::SCS_CLR |
Software Controllable Signals Register, offset: 0x68
| __IO uint32_t OCOTP_Type::SCS_SET |
Software Controllable Signals Register, offset: 0x64
| __IO uint32_t OCOTP_Type::SCS_TOG |
Software Controllable Signals Register, offset: 0x6C
| __IO uint16_t { ... } ::SCTRL |
Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20
| __IO uint16_t TMR_Type::SCTRL |
Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20
| __IO uint16_t { ... } ::SCTRL |
Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20
| __IO uint16_t { ... } ::SCTRL |
Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20
| __IO uint32_t TRNG_Type::SDCTL |
Seed Control Register, offset: 0x10
| __IO uint32_t LPI2C_Type::SDER |
Slave DMA Enable Register, offset: 0x11C
Slave DMA Enable, offset: 0x11C
| __IO uint32_t SEMC_Type::SDRAMCR0 |
SDRAM control register 0, offset: 0x40
SDRAM Control Register 0, offset: 0x40
| __IO uint32_t SEMC_Type::SDRAMCR1 |
SDRAM control register 1, offset: 0x44
SDRAM Control Register 1, offset: 0x44
| __IO uint32_t SEMC_Type::SDRAMCR2 |
SDRAM control register 2, offset: 0x48
SDRAM Control Register 2, offset: 0x48
| __IO uint32_t SEMC_Type::SDRAMCR3 |
SDRAM control register 3, offset: 0x4C
SDRAM Control Register 3, offset: 0x4C
| __IO uint32_t TRNG_Type::SEC_CFG |
Security Configuration Register, offset: 0xA0
| __O uint32_t CDOG_Type::SECURE_COUNTER |
Secure Counter, offset: 0xC
| __O uint8_t DMA_Type::SEEI |
Set Enable Error Interrupt, offset: 0x19
| __IO uint16_t XBARA_Type::SEL0 |
Crossbar A Select Register 0, offset: 0x0
| __IO uint16_t XBARB_Type::SEL0 |
Crossbar B Select Register 0, offset: 0x0
| __IO uint16_t XBARA_Type::SEL1 |
Crossbar A Select Register 1, offset: 0x2
| __IO uint16_t XBARB_Type::SEL1 |
Crossbar B Select Register 1, offset: 0x2
| __IO uint16_t XBARA_Type::SEL10 |
Crossbar A Select Register 10, offset: 0x14
| __IO uint16_t XBARA_Type::SEL11 |
Crossbar A Select Register 11, offset: 0x16
| __IO uint16_t XBARA_Type::SEL12 |
Crossbar A Select Register 12, offset: 0x18
| __IO uint16_t XBARA_Type::SEL13 |
Crossbar A Select Register 13, offset: 0x1A
| __IO uint16_t XBARA_Type::SEL14 |
Crossbar A Select Register 14, offset: 0x1C
| __IO uint16_t XBARA_Type::SEL15 |
Crossbar A Select Register 15, offset: 0x1E
| __IO uint16_t XBARA_Type::SEL16 |
Crossbar A Select Register 16, offset: 0x20
| __IO uint16_t XBARA_Type::SEL17 |
Crossbar A Select Register 17, offset: 0x22
| __IO uint16_t XBARA_Type::SEL18 |
Crossbar A Select Register 18, offset: 0x24
| __IO uint16_t XBARA_Type::SEL19 |
Crossbar A Select Register 19, offset: 0x26
| __IO uint16_t XBARA_Type::SEL2 |
Crossbar A Select Register 2, offset: 0x4
| __IO uint16_t XBARB_Type::SEL2 |
Crossbar B Select Register 2, offset: 0x4
| __IO uint16_t XBARA_Type::SEL20 |
Crossbar A Select Register 20, offset: 0x28
| __IO uint16_t XBARA_Type::SEL21 |
Crossbar A Select Register 21, offset: 0x2A
| __IO uint16_t XBARA_Type::SEL22 |
Crossbar A Select Register 22, offset: 0x2C
| __IO uint16_t XBARA_Type::SEL23 |
Crossbar A Select Register 23, offset: 0x2E
| __IO uint16_t XBARA_Type::SEL24 |
Crossbar A Select Register 24, offset: 0x30
| __IO uint16_t XBARA_Type::SEL25 |
Crossbar A Select Register 25, offset: 0x32
| __IO uint16_t XBARA_Type::SEL26 |
Crossbar A Select Register 26, offset: 0x34
| __IO uint16_t XBARA_Type::SEL27 |
Crossbar A Select Register 27, offset: 0x36
| __IO uint16_t XBARA_Type::SEL28 |
Crossbar A Select Register 28, offset: 0x38
| __IO uint16_t XBARA_Type::SEL29 |
Crossbar A Select Register 29, offset: 0x3A
| __IO uint16_t XBARA_Type::SEL3 |
Crossbar A Select Register 3, offset: 0x6
| __IO uint16_t XBARB_Type::SEL3 |
Crossbar B Select Register 3, offset: 0x6
| __IO uint16_t XBARA_Type::SEL30 |
Crossbar A Select Register 30, offset: 0x3C
| __IO uint16_t XBARA_Type::SEL31 |
Crossbar A Select Register 31, offset: 0x3E
| __IO uint16_t XBARA_Type::SEL32 |
Crossbar A Select Register 32, offset: 0x40
| __IO uint16_t XBARA_Type::SEL33 |
Crossbar A Select Register 33, offset: 0x42
| __IO uint16_t XBARA_Type::SEL34 |
Crossbar A Select Register 34, offset: 0x44
| __IO uint16_t XBARA_Type::SEL35 |
Crossbar A Select Register 35, offset: 0x46
| __IO uint16_t XBARA_Type::SEL36 |
Crossbar A Select Register 36, offset: 0x48
| __IO uint16_t XBARA_Type::SEL37 |
Crossbar A Select Register 37, offset: 0x4A
| __IO uint16_t XBARA_Type::SEL38 |
Crossbar A Select Register 38, offset: 0x4C
| __IO uint16_t XBARA_Type::SEL39 |
Crossbar A Select Register 39, offset: 0x4E
| __IO uint16_t XBARA_Type::SEL4 |
Crossbar A Select Register 4, offset: 0x8
| __IO uint16_t XBARB_Type::SEL4 |
Crossbar B Select Register 4, offset: 0x8
| __IO uint16_t XBARA_Type::SEL40 |
Crossbar A Select Register 40, offset: 0x50
| __IO uint16_t XBARA_Type::SEL41 |
Crossbar A Select Register 41, offset: 0x52
| __IO uint16_t XBARA_Type::SEL42 |
Crossbar A Select Register 42, offset: 0x54
| __IO uint16_t XBARA_Type::SEL43 |
Crossbar A Select Register 43, offset: 0x56
| __IO uint16_t XBARA_Type::SEL44 |
Crossbar A Select Register 44, offset: 0x58
| __IO uint16_t XBARA_Type::SEL45 |
Crossbar A Select Register 45, offset: 0x5A
| __IO uint16_t XBARA_Type::SEL46 |
Crossbar A Select Register 46, offset: 0x5C
| __IO uint16_t XBARA_Type::SEL47 |
Crossbar A Select Register 47, offset: 0x5E
| __IO uint16_t XBARA_Type::SEL48 |
Crossbar A Select Register 48, offset: 0x60
| __IO uint16_t XBARA_Type::SEL49 |
Crossbar A Select Register 49, offset: 0x62
| __IO uint16_t XBARA_Type::SEL5 |
Crossbar A Select Register 5, offset: 0xA
| __IO uint16_t XBARB_Type::SEL5 |
Crossbar B Select Register 5, offset: 0xA
| __IO uint16_t XBARA_Type::SEL50 |
Crossbar A Select Register 50, offset: 0x64
| __IO uint16_t XBARA_Type::SEL51 |
Crossbar A Select Register 51, offset: 0x66
| __IO uint16_t XBARA_Type::SEL52 |
Crossbar A Select Register 52, offset: 0x68
| __IO uint16_t XBARA_Type::SEL53 |
Crossbar A Select Register 53, offset: 0x6A
| __IO uint16_t XBARA_Type::SEL54 |
Crossbar A Select Register 54, offset: 0x6C
| __IO uint16_t XBARA_Type::SEL55 |
Crossbar A Select Register 55, offset: 0x6E
| __IO uint16_t XBARA_Type::SEL56 |
Crossbar A Select Register 56, offset: 0x70
| __IO uint16_t XBARA_Type::SEL57 |
Crossbar A Select Register 57, offset: 0x72
| __IO uint16_t XBARA_Type::SEL58 |
Crossbar A Select Register 58, offset: 0x74
| __IO uint16_t XBARA_Type::SEL59 |
Crossbar A Select Register 59, offset: 0x76
| __IO uint16_t XBARA_Type::SEL6 |
Crossbar A Select Register 6, offset: 0xC
| __IO uint16_t XBARB_Type::SEL6 |
Crossbar B Select Register 6, offset: 0xC
| __IO uint16_t XBARA_Type::SEL60 |
Crossbar A Select Register 60, offset: 0x78
| __IO uint16_t XBARA_Type::SEL61 |
Crossbar A Select Register 61, offset: 0x7A
| __IO uint16_t XBARA_Type::SEL62 |
Crossbar A Select Register 62, offset: 0x7C
| __IO uint16_t XBARA_Type::SEL63 |
Crossbar A Select Register 63, offset: 0x7E
| __IO uint16_t XBARA_Type::SEL64 |
Crossbar A Select Register 64, offset: 0x80
| __IO uint16_t XBARA_Type::SEL65 |
Crossbar A Select Register 65, offset: 0x82
| __IO uint16_t XBARA_Type::SEL66 |
Crossbar A Select Register 66, offset: 0x84
| __IO uint16_t XBARA_Type::SEL67 |
Crossbar A Select Register 67, offset: 0x86
| __IO uint16_t XBARA_Type::SEL68 |
Crossbar A Select Register 68, offset: 0x88
| __IO uint16_t XBARA_Type::SEL69 |
Crossbar A Select Register 69, offset: 0x8A
| __IO uint16_t XBARA_Type::SEL7 |
Crossbar A Select Register 7, offset: 0xE
| __IO uint16_t XBARB_Type::SEL7 |
Crossbar B Select Register 7, offset: 0xE
| __IO uint16_t XBARA_Type::SEL70 |
Crossbar A Select Register 70, offset: 0x8C
| __IO uint16_t XBARA_Type::SEL71 |
Crossbar A Select Register 71, offset: 0x8E
| __IO uint16_t XBARA_Type::SEL72 |
Crossbar A Select Register 72, offset: 0x90
| __IO uint16_t XBARA_Type::SEL73 |
Crossbar A Select Register 73, offset: 0x92
| __IO uint16_t XBARA_Type::SEL74 |
Crossbar A Select Register 74, offset: 0x94
| __IO uint16_t XBARA_Type::SEL75 |
Crossbar A Select Register 75, offset: 0x96
| __IO uint16_t XBARA_Type::SEL76 |
Crossbar A Select Register 76, offset: 0x98
| __IO uint16_t XBARA_Type::SEL77 |
Crossbar A Select Register 77, offset: 0x9A
| __IO uint16_t XBARA_Type::SEL78 |
Crossbar A Select Register 78, offset: 0x9C
| __IO uint16_t XBARA_Type::SEL79 |
Crossbar A Select Register 79, offset: 0x9E
| __IO uint16_t XBARA_Type::SEL8 |
Crossbar A Select Register 8, offset: 0x10
| __IO uint16_t XBARA_Type::SEL80 |
Crossbar A Select Register 80, offset: 0xA0
| __IO uint16_t XBARA_Type::SEL81 |
Crossbar A Select Register 81, offset: 0xA2
| __IO uint16_t XBARA_Type::SEL82 |
Crossbar A Select Register 82, offset: 0xA4
| __IO uint16_t XBARA_Type::SEL83 |
Crossbar A Select Register 83, offset: 0xA6
| __IO uint16_t XBARA_Type::SEL84 |
Crossbar A Select Register 84, offset: 0xA8
| __IO uint16_t XBARA_Type::SEL85 |
Crossbar A Select Register 85, offset: 0xAA
| __IO uint16_t XBARA_Type::SEL86 |
Crossbar A Select Register 86, offset: 0xAC
| __IO uint16_t XBARA_Type::SEL87 |
Crossbar A Select Register 87, offset: 0xAE
| __IO uint16_t XBARA_Type::SEL9 |
Crossbar A Select Register 9, offset: 0x12
| __IO uint32_t IOMUXC_Type::SELECT_INPUT |
ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR_INOUT23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4
FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register, array offset: 0x498, array step: 0x4
| __IO uint32_t IOMUXC_LPSR_Type::SELECT_INPUT |
CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register, array offset: 0x80, array step: 0x4
| __IO uint32_t DSI_HOST_APB_PKT_IF_Type::SEND_PACKET |
SEND_PACKET, offset: 0x8
| __O uint8_t DMA_Type::SERQ |
Set Enable Request, offset: 0x1B
| __O uint8_t EWM_Type::SERV |
Service Register, offset: 0x1
| __IO uint32_t { ... } ::SET |
Fractional PLL Control Register, offset: 0x4
| __IO uint32_t AUDIO_PLL_Type::SET |
Fractional PLL Control Register, offset: 0x4
Fractional PLL Spread Spectrum Control Register, offset: 0x14
Fractional PLL Numerator Control Register, offset: 0x24
Fractional PLL Denominator Control Register, offset: 0x34
| __IO uint32_t { ... } ::SET |
Fractional PLL Spread Spectrum Control Register, offset: 0x14
| __IO uint32_t { ... } ::SET |
Fractional PLL Numerator Control Register, offset: 0x24
| __IO uint32_t { ... } ::SET |
Fractional PLL Denominator Control Register, offset: 0x34
| __IO uint32_t CCM_Type::SET |
General Purpose Register, array offset: 0x4804, array step: 0x20
| __IO uint32_t { ... } ::SET |
General Purpose Register, array offset: 0x4804, array step: 0x20
| __IO uint32_t ETHERNET_PLL_Type::SET |
Fractional PLL Control Register, offset: 0x4
Fractional PLL Spread Spectrum Control Register, offset: 0x14
Fractional PLL Numerator Control Register, offset: 0x24
Fractional PLL Denominator Control Register, offset: 0x34
| __IO uint32_t { ... } ::SET |
Fractional PLL Control Register, offset: 0x4
| __IO uint32_t { ... } ::SET |
Fractional PLL Spread Spectrum Control Register, offset: 0x14
| __IO uint32_t { ... } ::SET |
Fractional PLL Numerator Control Register, offset: 0x24
| __IO uint32_t { ... } ::SET |
Fractional PLL Denominator Control Register, offset: 0x34
| __IO uint32_t { ... } ::SET |
Control Register 0, offset: 0x4
| __IO uint32_t OSC_RC_400M_Type::SET |
Control Register 0, offset: 0x4
Control Register 1, offset: 0x14
Control Register 2, offset: 0x24
Control Register 3, offset: 0x34
| __IO uint32_t { ... } ::SET |
Control Register 1, offset: 0x14
| __IO uint32_t { ... } ::SET |
Control Register 2, offset: 0x24
| __IO uint32_t { ... } ::SET |
Control Register 3, offset: 0x34
| __I uint32_t { ... } ::SET |
Status Register 0, offset: 0x54
| __I uint32_t OSC_RC_400M_Type::SET |
Status Register 0, offset: 0x54
Status Register 1, offset: 0x64
Status Register 2, offset: 0x74
| __I uint32_t { ... } ::SET |
Status Register 1, offset: 0x64
| __I uint32_t { ... } ::SET |
Status Register 2, offset: 0x74
| __IO uint32_t { ... } ::SET |
Analog Control Register CTRL0, offset: 0x4
| __IO uint32_t PHY_LDO_Type::SET |
Analog Control Register CTRL0, offset: 0x4
| __I uint32_t { ... } ::SET |
Analog Status Register STAT0, offset: 0x54
| __I uint32_t PHY_LDO_Type::SET |
Analog Status Register STAT0, offset: 0x54
| __IO uint32_t { ... } ::SET |
Video mux Control Register, offset: 0x4
| __IO uint32_t VIDEO_MUX_Type::SET |
Video mux Control Register, offset: 0x4
Pixel Link Master(PLM) Control Register, offset: 0x24
YUV420 Control Register, offset: 0x34
Data Disable Register, offset: 0x54
MIPI DSI Control Register, offset: 0x74
| __IO uint32_t { ... } ::SET |
Pixel Link Master(PLM) Control Register, offset: 0x24
| __IO uint32_t { ... } ::SET |
YUV420 Control Register, offset: 0x34
| __IO uint32_t { ... } ::SET |
Data Disable Register, offset: 0x54
| __IO uint32_t { ... } ::SET |
MIPI DSI Control Register, offset: 0x74
| __IO uint32_t VIDEO_PLL_Type::SET |
Fractional PLL Control Register, offset: 0x4
Fractional PLL Spread Spectrum Control Register, offset: 0x14
Fractional PLL Numerator Control Register, offset: 0x24
Fractional PLL Denominator Control Register, offset: 0x34
| __IO uint32_t { ... } ::SET |
Fractional PLL Control Register, offset: 0x4
| __IO uint32_t { ... } ::SET |
Fractional PLL Spread Spectrum Control Register, offset: 0x14
| __IO uint32_t { ... } ::SET |
Fractional PLL Numerator Control Register, offset: 0x24
| __IO uint32_t { ... } ::SET |
Fractional PLL Denominator Control Register, offset: 0x34
| __IO uint32_t { ... } ::SET |
Analog Control Register CTRL0, offset: 0x4
| __IO uint32_t VMBANDGAP_Type::SET |
Analog Control Register CTRL0, offset: 0x4
| __I uint32_t { ... } ::SET |
Analog Status Register STAT0, offset: 0x54
| __I uint32_t VMBANDGAP_Type::SET |
Analog Status Register STAT0, offset: 0x54
| __IO uint32_t { ... } ::SET |
Fractional PLL Control Register, offset: 0x4
| __IO uint32_t { ... } ::SET |
Fractional PLL Spread Spectrum Control Register, offset: 0x14
| __IO uint32_t { ... } ::SET |
Fractional PLL Numerator Control Register, offset: 0x24
| __IO uint32_t { ... } ::SET |
Fractional PLL Denominator Control Register, offset: 0x34
| __IO uint32_t { ... } ::SET |
General Purpose Register, array offset: 0x4804, array step: 0x20
| __IO uint32_t { ... } ::SET |
Fractional PLL Control Register, offset: 0x4
| __IO uint32_t { ... } ::SET |
Fractional PLL Spread Spectrum Control Register, offset: 0x14
| __IO uint32_t { ... } ::SET |
Fractional PLL Numerator Control Register, offset: 0x24
| __IO uint32_t { ... } ::SET |
Fractional PLL Denominator Control Register, offset: 0x34
| __IO uint32_t { ... } ::SET |
Control Register 0, offset: 0x4
| __IO uint32_t { ... } ::SET |
Control Register 1, offset: 0x14
| __IO uint32_t { ... } ::SET |
Control Register 2, offset: 0x24
| __IO uint32_t { ... } ::SET |
Control Register 3, offset: 0x34
| __I uint32_t { ... } ::SET |
Status Register 0, offset: 0x54
| __I uint32_t { ... } ::SET |
Status Register 1, offset: 0x64
| __I uint32_t { ... } ::SET |
Status Register 2, offset: 0x74
| __IO uint32_t { ... } ::SET |
Analog Control Register CTRL0, offset: 0x4
| __I uint32_t { ... } ::SET |
Analog Status Register STAT0, offset: 0x54
| __IO uint32_t { ... } ::SET |
Video mux Control Register, offset: 0x4
| __IO uint32_t { ... } ::SET |
Pixel Link Master(PLM) Control Register, offset: 0x24
| __IO uint32_t { ... } ::SET |
YUV420 Control Register, offset: 0x34
| __IO uint32_t { ... } ::SET |
Data Disable Register, offset: 0x54
| __IO uint32_t { ... } ::SET |
MIPI DSI Control Register, offset: 0x74
| __IO uint32_t { ... } ::SET |
Fractional PLL Control Register, offset: 0x4
| __IO uint32_t { ... } ::SET |
Fractional PLL Spread Spectrum Control Register, offset: 0x14
| __IO uint32_t { ... } ::SET |
Fractional PLL Numerator Control Register, offset: 0x24
| __IO uint32_t { ... } ::SET |
Fractional PLL Denominator Control Register, offset: 0x34
| __IO uint32_t { ... } ::SET |
Analog Control Register CTRL0, offset: 0x4
| __I uint32_t { ... } ::SET |
Analog Status Register STAT0, offset: 0x54
| __IO uint32_t CCM_Type::SETPOINT |
Setpoint setting, array offset: 0x40, array step: index*0x80, index2*0x4
Setpoint setting, array offset: 0x4040, array step: index*0x80, index2*0x4
Clock source Setpoint setting, array offset: 0x5008, array step: 0x20
LPCG Setpoint setting, array offset: 0x6008, array step: 0x20
| __IO uint32_t { ... } ::SETPOINT[16] |
Setpoint setting, array offset: 0x40, array step: index*0x80, index2*0x4
| __IO uint32_t { ... } ::SETPOINT[16] |
Setpoint setting, array offset: 0x4040, array step: index*0x80, index2*0x4
| __IO uint32_t { ... } ::SETPOINT |
Clock source Setpoint setting, array offset: 0x5008, array step: 0x20
| __IO uint32_t { ... } ::SETPOINT |
LPCG Setpoint setting, array offset: 0x6008, array step: 0x20
| __IO uint32_t { ... } ::SETPOINT[16] |
Setpoint setting, array offset: 0x40, array step: index*0x80, index2*0x4
| __IO uint32_t { ... } ::SETPOINT[16] |
Setpoint setting, array offset: 0x4040, array step: index*0x80, index2*0x4
| __IO uint32_t { ... } ::SETPOINT |
Clock source Setpoint setting, array offset: 0x5008, array step: 0x20
| __IO uint32_t { ... } ::SETPOINT |
LPCG Setpoint setting, array offset: 0x6008, array step: 0x20
| __IO uint32_t SRC_Type::SETPOINT_DISPLAY |
Slice Setpoint Config Register, offset: 0x228
| __IO uint32_t SRC_Type::SETPOINT_M4CORE |
Slice Setpoint Config Register, offset: 0x288
| __IO uint32_t SRC_Type::SETPOINT_M4DEBUG |
Slice Setpoint Config Register, offset: 0x2C8
| __IO uint32_t SRC_Type::SETPOINT_M7CORE |
Slice Setpoint Config Register, offset: 0x2A8
| __IO uint32_t SRC_Type::SETPOINT_M7DEBUG |
Slice Setpoint Config Register, offset: 0x2E8
| __IO uint32_t SRC_Type::SETPOINT_MEGA |
Slice Setpoint Config Register, offset: 0x208
| __IO uint32_t SRC_Type::SETPOINT_USBPHY1 |
Slice Setpoint Config Register, offset: 0x308
| __IO uint32_t SRC_Type::SETPOINT_USBPHY2 |
Slice Setpoint Config Register, offset: 0x328
| __IO uint32_t SRC_Type::SETPOINT_WAKEUP |
Slice Setpoint Config Register, offset: 0x248
| __IO uint32_t FLEXIO_Type::SHIFTBUF |
Shifter Buffer N Register, array offset: 0x200, array step: 0x4
| __IO uint32_t FLEXIO_Type::SHIFTBUFBBS |
Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4
| __IO uint32_t FLEXIO_Type::SHIFTBUFBIS |
Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4
| __IO uint32_t FLEXIO_Type::SHIFTBUFBYS |
Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4
| __IO uint32_t FLEXIO_Type::SHIFTBUFEOS |
Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4
| __IO uint32_t FLEXIO_Type::SHIFTBUFHWS |
Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4
| __IO uint32_t FLEXIO_Type::SHIFTBUFNBS |
Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4
| __IO uint32_t FLEXIO_Type::SHIFTBUFNIS |
Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4
| __IO uint32_t FLEXIO_Type::SHIFTBUFOES |
Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4
| __IO uint32_t FLEXIO_Type::SHIFTCFG |
Shifter Configuration N Register, array offset: 0x100, array step: 0x4
| __IO uint32_t FLEXIO_Type::SHIFTCTL |
Shifter Control N Register, array offset: 0x80, array step: 0x4
| __IO uint32_t FLEXIO_Type::SHIFTEIEN |
Shifter Error Interrupt Enable, offset: 0x24
| __IO uint32_t FLEXIO_Type::SHIFTERR |
Shifter Error Register, offset: 0x14
| __IO uint32_t FLEXIO_Type::SHIFTSDEN |
Shifter Status DMA Enable, offset: 0x30
| __IO uint32_t FLEXIO_Type::SHIFTSIEN |
Shifter Status Interrupt Enable, offset: 0x20
| __IO uint32_t FLEXIO_Type::SHIFTSTAT |
Shifter Status Register, offset: 0x10
| __IO uint32_t FLEXIO_Type::SHIFTSTATE |
Shifter State Register, offset: 0x40
| __O uint32_t SPDIF_Type::SIC |
InterruptClear Register, offset: 0x10
| __O uint32_t { ... } ::SIC |
InterruptClear Register, offset: 0x10
| __O uint32_t { ... } ::SIC |
InterruptClear Register, offset: 0x10
| __O uint32_t { ... } ::SIC |
InterruptClear Register, offset: 0x10
| __IO uint32_t SPDIF_Type::SIE |
InterruptEn Register, offset: 0xC
| __IO uint32_t LPI2C_Type::SIER |
Slave Interrupt Enable Register, offset: 0x118
Slave Interrupt Enable, offset: 0x118
| __IO uint32_t USBHSDCD_Type::SIGNAL_OVERRIDE |
Signal Override Register, offset: 0xC
| __IO uint32_t CAAM_Type::SIL |
Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C
| __IO uint32_t { ... } ::SIL |
Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C
| __IO uint32_t { ... } ::SIL |
Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C
| __I uint32_t XECC_Type::SINGLE_ERR_ADDR |
Single Error Address, offset: 0x18
| __I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC0 |
Single Error Address And ECC code On OCRAM Bank0, offset: 0x3C
| __I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC1 |
Single Error Address And ECC code On OCRAM Bank1, offset: 0x50
| __I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC2 |
Single Error Address And ECC code On OCRAM Bank2, offset: 0x64
| __I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC3 |
Single Error Address And ECC code On OCRAM Bank3, offset: 0x78
| __I uint32_t XECC_Type::SINGLE_ERR_BIT_FIELD |
Single Error Bit Field, offset: 0x28
| __I uint32_t XECC_Type::SINGLE_ERR_DATA |
Single Error Read Data, offset: 0x1C
| __I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH0 |
HIGH 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x44
| __I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH1 |
HIGH 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x58
| __I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH2 |
HIGH 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x6C
| __I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH3 |
HIGH 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x80
| __I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW0 |
LOW 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x40
| __I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW1 |
LOW 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x54
| __I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW2 |
LOW 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x68
| __I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW3 |
LOW 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x7C
| __I uint32_t XECC_Type::SINGLE_ERR_ECC |
Single Error ECC Code, offset: 0x20
| __I uint32_t XECC_Type::SINGLE_ERR_POS |
Single Error Bit Position, offset: 0x24
| __I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH0 |
HIGH Single Error Bit Position On OCRAM Bank0, offset: 0x4C
| __I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH1 |
HIGH Single Error Bit Position On OCRAM Bank1, offset: 0x60
| __I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH2 |
HIGH Single Error Bit Position On OCRAM Bank2, offset: 0x74
| __I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH3 |
HIGH Single Error Bit Position On OCRAM Bank3, offset: 0x88
| __I uint32_t MECC_Type::SINGLE_ERR_POS_LOW0 |
LOW Single Error Bit Position On OCRAM Bank0, offset: 0x48
| __I uint32_t MECC_Type::SINGLE_ERR_POS_LOW1 |
LOW Single Error Bit Position On OCRAM Bank1, offset: 0x5C
| __I uint32_t MECC_Type::SINGLE_ERR_POS_LOW2 |
LOW Single Error Bit Position On OCRAM Bank2, offset: 0x70
| __I uint32_t MECC_Type::SINGLE_ERR_POS_LOW3 |
LOW Single Error Bit Position On OCRAM Bank3, offset: 0x84
| __I uint32_t { ... } ::SIS |
InterruptStat Register, offset: 0x10
| __I uint32_t SPDIF_Type::SIS |
InterruptStat Register, offset: 0x10
| __I uint32_t { ... } ::SIS |
InterruptStat Register, offset: 0x10
| __I uint32_t { ... } ::SIS |
InterruptStat Register, offset: 0x10
| __IO uint32_t OCOTP_Type::SJC_RESP0 |
Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600
| __IO uint32_t OCOTP_Type::SJC_RESP1 |
Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610
| __IO uint64_t CAAM_Type::SKNR |
Secure Key Nonce Register, offset: 0x4E0
| __IO int32_t DMA_Type::SLAST |
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
| __IO int32_t { ... } ::SLAST |
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
| __IO int32_t { ... } ::SLAST |
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
| __IO int32_t { ... } ::SLAST |
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
| __IO uint32_t KEY_MANAGER_Type::SLOT0_CTRL |
Slot 0 Control, offset: 0x400
| __IO uint32_t KEY_MANAGER_Type::SLOT1_CTRL |
Slot1 Control, offset: 0x404
| __IO uint32_t KEY_MANAGER_Type::SLOT2_CTRL |
Slot2 Control, offset: 0x408
| __IO uint32_t KEY_MANAGER_Type::SLOT3_CTRL |
Slot3 Control, offset: 0x40C
| __IO uint32_t KEY_MANAGER_Type::SLOT4_CTRL |
Slot 4 Control, offset: 0x410
| __IO uint32_t { ... } ::SLOT_CTRL |
Slot Control Register, array offset: 0x0, array step: 0x10
| __IO uint32_t IPS_DOMAIN_Type::SLOT_CTRL |
Slot Control Register, array offset: 0x0, array step: 0x10
| __IO uint32_t { ... } ::SLOT_CTRL |
Slot Control Register, array offset: 0x0, array step: 0x10
| __O uint32_t { ... } ::SMCR_JR |
Secure Memory Command Register, array offset: 0x10BE4, array step: 0x10000
| __O uint32_t CAAM_Type::SMCR_JR |
Secure Memory Command Register, array offset: 0x10BE4, array step: 0x10000
| __O uint32_t { ... } ::SMCR_JR |
Secure Memory Command Register, array offset: 0x10BE4, array step: 0x10000
| __O uint32_t CAAM_Type::SMCR_PG0 |
Secure Memory Command Register, offset: 0xBE4
| __I uint32_t { ... } ::SMCSR_JR |
Secure Memory Command Status Register, array offset: 0x10BEC, array step: 0x10000
| __I uint32_t CAAM_Type::SMCSR_JR |
Secure Memory Command Status Register, array offset: 0x10BEC, array step: 0x10000
| __I uint32_t { ... } ::SMCSR_JR |
Secure Memory Command Status Register, array offset: 0x10BEC, array step: 0x10000
| __I uint32_t CAAM_Type::SMCSR_PG0 |
Secure Memory Command Status Register, offset: 0xBEC
| __I uint32_t CAAM_Type::SMPO |
Secure Memory Partition Owners Register, offset: 0xFBC
| __I uint32_t { ... } ::SMPO_JR |
Secure Memory Partition Owners Register, array offset: 0x10FBC, array step: 0x10000
| __I uint32_t CAAM_Type::SMPO_JR |
Secure Memory Partition Owners Register, array offset: 0x10FBC, array step: 0x10000
| __I uint32_t { ... } ::SMPO_JR |
Secure Memory Partition Owners Register, array offset: 0x10FBC, array step: 0x10000
| __I uint32_t CAAM_Type::SMSTA |
Secure Memory Status Register, offset: 0xFB4
| __I uint32_t CAAM_Type::SMSTA_DC01 |
Secure Memory Status Register, offset: 0x80FB4
| __I uint32_t CAAM_Type::SMSTA_JR |
Secure Memory Status Register, array offset: 0x10FB4, array step: 0x10000
| __I uint32_t { ... } ::SMSTA_JR |
Secure Memory Status Register, array offset: 0x10FB4, array step: 0x10000
| __I uint32_t { ... } ::SMSTA_JR |
Secure Memory Status Register, array offset: 0x10FB4, array step: 0x10000
| __I uint32_t CAAM_Type::SMSTA_RTIC |
Secure Memory Status Register, offset: 0x60FB4
| __I uint32_t CAAM_Type::SMVID_LS |
Secure Memory Version ID Register, least-significant half, offset: 0xFDC
| __I uint32_t CAAM_Type::SMVID_LS_DC01 |
Secure Memory Version ID Register, least-significant half, offset: 0x80FDC
| __I uint32_t CAAM_Type::SMVID_LS_JR |
Secure Memory Version ID Register, least-significant half, array offset: 0x10FDC, array step: 0x10000
| __I uint32_t { ... } ::SMVID_LS_JR |
Secure Memory Version ID Register, least-significant half, array offset: 0x10FDC, array step: 0x10000
| __I uint32_t { ... } ::SMVID_LS_JR |
Secure Memory Version ID Register, least-significant half, array offset: 0x10FDC, array step: 0x10000
| __I uint32_t CAAM_Type::SMVID_LS_RTIC |
Secure Memory Version ID Register, least-significant half, offset: 0x60FDC
| __I uint32_t CAAM_Type::SMVID_MS |
Secure Memory Version ID Register, most-significant half, offset: 0xFD8
| __I uint32_t CAAM_Type::SMVID_MS_DC01 |
Secure Memory Version ID Register, most-significant half, offset: 0x80FD8
| __I uint32_t CAAM_Type::SMVID_MS_JR |
Secure Memory Version ID Register, most-significant half, array offset: 0x10FD8, array step: 0x10000
| __I uint32_t { ... } ::SMVID_MS_JR |
Secure Memory Version ID Register, most-significant half, array offset: 0x10FD8, array step: 0x10000
| __I uint32_t { ... } ::SMVID_MS_JR |
Secure Memory Version ID Register, most-significant half, array offset: 0x10FD8, array step: 0x10000
| __I uint32_t CAAM_Type::SMVID_MS_RTIC |
Secure Memory Version ID Register, most-significant half, offset: 0x60FD8
| __IO uint32_t CAAM_Type::SMWPJRR |
Secure Memory Write Protect Job Ring Register, array offset: 0xBD0, array step: 0x4
| __IO uint16_t { ... } ::SOFF |
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
| __IO uint16_t DMA_Type::SOFF |
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
| __IO uint16_t { ... } ::SOFF |
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
| __IO uint16_t { ... } ::SOFF |
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
| __IO uint32_t { ... } ::SOL |
Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C
| __IO uint32_t CAAM_Type::SOL |
Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C
| __IO uint32_t { ... } ::SOL |
Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_AUTHEN_CTRL |
SP Authentication Control, offset: 0x4
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BG_PLDO_OFF_CTRL |
SP bandgap and PLL_LDO off control, offset: 0x190
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BG_PLDO_ON_CTRL |
SP bandgap and PLL_LDO on control, offset: 0x220
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BIAS_OFF_CTRL |
SP bias off control, offset: 0x180
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BIAS_ON_CTRL |
SP bias on control, offset: 0x230
| __I uint32_t GPC_SET_POINT_CTRL_Type::SP_CPU_REQ |
CPU SP Request, offset: 0x10
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_DCDC_DOWN_CTRL |
SP DCDC down control, offset: 0x1B0
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_DCDC_UP_CTRL |
SP DCDC up control, offset: 0x200
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_GROUP_DOWN_CTRL |
SP group down control, offset: 0x120
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_GROUP_UP_CTRL |
SP group up control, offset: 0x290
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_INT_CTRL |
SP Interrupt Control, offset: 0x8
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ISO_OFF_CTRL |
SP ISO off control, offset: 0x260
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ISO_ON_CTRL |
SP ISO on control, offset: 0x150
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LDO_POST_CTRL |
SP LDO post control, offset: 0x210
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LDO_PRE_CTRL |
SP LDO pre control, offset: 0x1A0
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LPCG_OFF_CTRL |
SP LPCG off control, offset: 0x110
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LPCG_ON_CTRL |
SP LPCG on control, offset: 0x2A0
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PLL_OFF_CTRL |
SP PLL off control, offset: 0x140
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PLL_ON_CTRL |
SP PLL on control, offset: 0x270
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_POWER_OFF_CTRL |
SP power off control, offset: 0x170
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_POWER_ON_CTRL |
SP power on control, offset: 0x240
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PRIORITY_0_7 |
SP0~7 Priority, offset: 0x40
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PRIORITY_8_15 |
SP8~15 Priority, offset: 0x44
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_RESET_EARLY_CTRL |
SP reset early control, offset: 0x160
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_RESET_LATE_CTRL |
SP reset late control, offset: 0x250
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ROOT_DOWN_CTRL |
SP root down control, offset: 0x130
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ROOT_UP_CTRL |
SP root up control, offset: 0x280
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ROSC_CTRL |
SP ROSC Control, offset: 0x1C
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_SSAR_RESTORE_CTRL |
SP SSAR restore control, offset: 0x2B0
| __IO uint32_t GPC_SET_POINT_CTRL_Type::SP_SSAR_SAVE_CTRL |
SP SSAR save control, offset: 0x100
| __I uint32_t GPC_SET_POINT_CTRL_Type::SP_SYS_STAT |
SP System Status, offset: 0x14
| __IO uint32_t CSI_Type::SR |
CSI Status Register, offset: 0x18
| __IO uint32_t GPT_Type::SR |
GPT Status Register, offset: 0x8
| __IO uint32_t LPSPI_Type::SR |
Status Register, offset: 0x14
Status, offset: 0x14
| __IO uint32_t MU_Type::SR |
Processor B Status Register, offset: 0x20
Processor A Status Register, offset: 0x20
| __IO uint32_t OTFAD_Type::SR |
Status Register, offset: 0xC04
| __I uint32_t XRDC2_Type::SR |
Status Register, offset: 0x4
| __IO uint32_t { ... } ::SRAM0 |
Description Address Register, array offset: 0x0, array step: 0x10
| __IO uint32_t SSARC_HP_Type::SRAM0 |
Description Address Register, array offset: 0x0, array step: 0x10
| __IO uint32_t { ... } ::SRAM0 |
Description Address Register, array offset: 0x0, array step: 0x10
| __IO uint32_t { ... } ::SRAM1 |
Description Data Register, array offset: 0x4, array step: 0x10
| __IO uint32_t SSARC_HP_Type::SRAM1 |
Description Data Register, array offset: 0x4, array step: 0x10
| __IO uint32_t { ... } ::SRAM1 |
Description Data Register, array offset: 0x4, array step: 0x10
| __IO uint32_t { ... } ::SRAM2 |
Description Control Register, array offset: 0x8, array step: 0x10
| __IO uint32_t SSARC_HP_Type::SRAM2 |
Description Control Register, array offset: 0x8, array step: 0x10
| __IO uint32_t { ... } ::SRAM2 |
Description Control Register, array offset: 0x8, array step: 0x10
| __IO uint32_t SEMC_Type::SRAMCR0 |
SRAM control register 0, offset: 0x70
SRAM Control Register 0, offset: 0x70
| __IO uint32_t SEMC_Type::SRAMCR1 |
SRAM control register 1, offset: 0x74
SRAM Control Register 1, offset: 0x74
| __IO uint32_t SEMC_Type::SRAMCR2 |
SRAM control register 2, offset: 0x78
SRAM Control Register 2, offset: 0x78
| uint32_t SEMC_Type::SRAMCR3 |
SRAM control register 3, offset: 0x7C
SRAM Control Register 3, offset: 0x7C
| __IO uint32_t SEMC_Type::SRAMCR4 |
SRAM Control Register 4, offset: 0x120
| __IO uint32_t SEMC_Type::SRAMCR5 |
SRAM Control Register 5, offset: 0x124
| __IO uint32_t SEMC_Type::SRAMCR6 |
SRAM Control Register 6, offset: 0x128
| __IO uint32_t SPDIF_Type::SRCD |
CDText Control Register, offset: 0x4
| __I uint32_t SPDIF_Type::SRCSH |
SPDIFRxCChannel_h Register, offset: 0x1C
| __I uint32_t SPDIF_Type::SRCSL |
SPDIFRxCChannel_l Register, offset: 0x20
| __I uint32_t LPI2C_Type::SRDR |
Slave Receive Data Register, offset: 0x170
Slave Receive Data, offset: 0x170
| __I uint32_t SPDIF_Type::SRFM |
FreqMeas Register, offset: 0x44
| __IO uint32_t OCOTP_Type::SRK0 |
Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580
| __IO uint32_t OCOTP_Type::SRK1 |
Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590
| __IO uint32_t OCOTP_Type::SRK2 |
Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0
| __IO uint32_t OCOTP_Type::SRK3 |
Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0
| __IO uint32_t OCOTP_Type::SRK4 |
Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0
| __IO uint32_t OCOTP_Type::SRK5 |
Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0
| __IO uint32_t OCOTP_Type::SRK6 |
Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0
| __IO uint32_t OCOTP_Type::SRK7 |
Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0
| __IO uint32_t OCOTP_Type::SRK_REVOKE |
Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0
| __I uint32_t SPDIF_Type::SRL |
SPDIFRxLeft Register, offset: 0x14
| __IO uint32_t SRC_Type::SRMR |
SRC Reset Mode Register, offset: 0x4
| __IO uint32_t SPDIF_Type::SRPC |
PhaseConfig Register, offset: 0x8
| __I uint32_t SPDIF_Type::SRQ |
QchannelRx Register, offset: 0x28
| __I uint32_t SPDIF_Type::SRR |
SPDIFRxRight Register, offset: 0x18
| __IO uint32_t SRC_Type::SRSR |
SRC Reset Status Register, offset: 0x8
SRC Reset Status Register, offset: 0x10
| __I uint32_t SPDIF_Type::SRU |
UchannelRx Register, offset: 0x24
| __IO uint32_t LPI2C_Type::SSR |
Slave Status Register, offset: 0x114
Slave Status, offset: 0x114
| __O uint8_t DMA_Type::SSRT |
Set START Bit, offset: 0x1D
| __I uint32_t IEE_Type::STA |
IEE Status, offset: 0x4
| __IO uint32_t LPI2C_Type::STAR |
Slave Transmit ACK Register, offset: 0x154
Slave Transmit ACK, offset: 0x154
| __O uint32_t CDOG_Type::START |
START Command, offset: 0x20
| __IO uint32_t DCP_Type::STAT |
DCP status register, offset: 0x10
| __I uint32_t LCDIF_Type::STAT |
LCD Interface Status Register, offset: 0x1B0
| __IO uint32_t LPUART_Type::STAT |
LPUART Status Register, offset: 0x14
| __IO uint32_t PXP_Type::STAT |
Status Register, offset: 0x10
| __IO uint32_t ADC_Type::STAT |
LPADC Status Register, offset: 0x14
| __IO uint32_t PDM_Type::STAT |
PDM Status register, offset: 0x8
| __I uint32_t PUF_Type::STAT |
PUF Status Register, offset: 0x20
| __IO uint32_t RDC_Type::STAT |
Status, offset: 0x24
| __IO uint32_t DCP_Type::STAT_CLR |
DCP status register, offset: 0x18
| __IO uint32_t PXP_Type::STAT_CLR |
Status Register, offset: 0x18
| __IO uint32_t SRC_Type::STAT_DISPLAY |
Slice Status Register, offset: 0x230
| __IO uint32_t SRC_Type::STAT_M4CORE |
Slice Status Register, offset: 0x290
| __IO uint32_t SRC_Type::STAT_M4DEBUG |
Slice Status Register, offset: 0x2D0
| __IO uint32_t SRC_Type::STAT_M7CORE |
Slice Status Register, offset: 0x2B0
| __IO uint32_t SRC_Type::STAT_M7DEBUG |
Slice Status Register, offset: 0x2F0
| __IO uint32_t SRC_Type::STAT_MEGA |
Slice Status Register, offset: 0x210
| __IO uint32_t DCP_Type::STAT_SET |
DCP status register, offset: 0x14
| __IO uint32_t PXP_Type::STAT_SET |
Status Register, offset: 0x14
| __IO uint32_t DCP_Type::STAT_TOG |
DCP status register, offset: 0x1C
| __IO uint32_t PXP_Type::STAT_TOG |
Status Register, offset: 0x1C
| __IO uint32_t SRC_Type::STAT_USBPHY1 |
Slice Status Register, offset: 0x310
| __IO uint32_t SRC_Type::STAT_USBPHY2 |
Slice Status Register, offset: 0x330
| __IO uint32_t SRC_Type::STAT_WAKEUP |
Slice Status Register, offset: 0x250
| __I uint32_t CSI_Type::STATFIFO |
CSI Statistic FIFO Register, offset: 0xC
| __IO uint32_t BEE_Type::STATUS |
Status Register, offset: 0x1C
| __I uint32_t TRNG_Type::STATUS |
Status Register, offset: 0x3C
| __IO uint32_t USBPHY_Type::STATUS |
USB PHY Status Register, offset: 0x40
| __I uint32_t CDOG_Type::STATUS |
Status 1, offset: 0x10
| __I uint32_t USBHSDCD_Type::STATUS |
Status register, offset: 0x8
| __I uint32_t CCM_Type::STATUS0 |
Clock root working status, array offset: 0x20, array step: 0x80
Clock source working status, array offset: 0x5010, array step: 0x20
LPCG working status, array offset: 0x6010, array step: 0x20
| __I uint32_t { ... } ::STATUS0 |
Clock root working status, array offset: 0x20, array step: 0x80
| __IO uint32_t { ... } ::STATUS0 |
Clock group working status, array offset: 0x4020, array step: 0x80
| __IO uint32_t CCM_Type::STATUS0 |
Clock group working status, array offset: 0x4020, array step: 0x80
| __I uint32_t { ... } ::STATUS0 |
Clock source working status, array offset: 0x5010, array step: 0x20
| __I uint32_t { ... } ::STATUS0 |
LPCG working status, array offset: 0x6010, array step: 0x20
| __I uint32_t { ... } ::STATUS0 |
Observe status, array offset: 0x20, array step: 0x80
| __I uint32_t CCM_OBS_Type::STATUS0 |
Observe status, array offset: 0x20, array step: 0x80
| __IO uint32_t TMPSNS_Type::STATUS0 |
Temperature Sensor Status Register 0, offset: 0x50
| __I uint32_t { ... } ::STATUS0 |
Clock root working status, array offset: 0x20, array step: 0x80
| __IO uint32_t { ... } ::STATUS0 |
Clock group working status, array offset: 0x4020, array step: 0x80
| __I uint32_t { ... } ::STATUS0 |
Clock source working status, array offset: 0x5010, array step: 0x20
| __I uint32_t { ... } ::STATUS0 |
LPCG working status, array offset: 0x6010, array step: 0x20
| __I uint32_t { ... } ::STATUS0 |
Observe status, array offset: 0x20, array step: 0x80
| __I uint32_t { ... } ::STATUS1 |
Clock root low power status, array offset: 0x24, array step: 0x80
| __I uint32_t CCM_Type::STATUS1 |
Clock root low power status, array offset: 0x24, array step: 0x80
Clock group low power/extend status, array offset: 0x4024, array step: 0x80
Clock source low power status, array offset: 0x5014, array step: 0x20
LPCG low power status, array offset: 0x6014, array step: 0x20
| __I uint32_t { ... } ::STATUS1 |
Clock group low power/extend status, array offset: 0x4024, array step: 0x80
| __I uint32_t { ... } ::STATUS1 |
Clock source low power status, array offset: 0x5014, array step: 0x20
| __I uint32_t { ... } ::STATUS1 |
LPCG low power status, array offset: 0x6014, array step: 0x20
| __I uint32_t { ... } ::STATUS1 |
Clock root low power status, array offset: 0x24, array step: 0x80
| __I uint32_t { ... } ::STATUS1 |
Clock group low power/extend status, array offset: 0x4024, array step: 0x80
| __I uint32_t { ... } ::STATUS1 |
Clock source low power status, array offset: 0x5014, array step: 0x20
| __I uint32_t { ... } ::STATUS1 |
LPCG low power status, array offset: 0x6014, array step: 0x20
| __I uint32_t CDOG_Type::STATUS2 |
Status 2, offset: 0x14
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_AUTHEN_CTRL |
Standby Authentication Control, offset: 0x4
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_BANDGAP_IN_CTRL |
STBY bandgap_in control, offset: 0x128
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_BANDGAP_OUT_CTRL |
STBY bandgap out control, offset: 0x230
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_BIAS_IN_CTRL |
STBY bias_in control, offset: 0x110
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_BIAS_OUT_CTRL |
STBY bias out control, offset: 0x240
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_DCDC_IN_CTRL |
STBY dcdc_in control, offset: 0x140
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_DCDC_OUT_CTRL |
STBY DCDC out control, offset: 0x210
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_LDO_IN_CTRL |
STBY ldo_in control, offset: 0x130
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_LDO_OUT_CTRL |
STBY LDO out control, offset: 0x220
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_LPCG_IN_CTRL |
STBY lpcg_in control, offset: 0xF0
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_LPCG_OUT_CTRL |
STBY LPCG out control, offset: 0x260
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_MISC |
STBY Misc, offset: 0xC
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_PLDO_IN_CTRL |
STBY pldo_in control, offset: 0x120
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_PLDO_OUT_CTRL |
STBY pldo out control, offset: 0x238
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_PLL_IN_CTRL |
STBY pll_in control, offset: 0x100
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_PLL_OUT_CTRL |
STBY PLL out control, offset: 0x250
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_PMIC_IN_CTRL |
STBY PMIC in control, offset: 0x150
| __IO uint32_t GPC_STBY_CTRL_Type::STBY_PMIC_OUT_CTRL |
STBY PMIC out control, offset: 0x200
| __IO uint32_t SPDIF_Type::STC |
SPDIFTxClk Register, offset: 0x50
| __IO uint32_t SPDIF_Type::STCSCH |
SPDIFTxCChannelCons_h Register, offset: 0x34
| __IO uint32_t SPDIF_Type::STCSCL |
SPDIFTxCChannelCons_l Register, offset: 0x38
| __O uint32_t LPI2C_Type::STDR |
Slave Transmit Data Register, offset: 0x160
Slave Transmit Data, offset: 0x160
| __O uint32_t SPDIF_Type::STL |
SPDIFTxLeft Register, offset: 0x2C
| __O uint32_t CDOG_Type::STOP |
STOP Command, offset: 0x24
| __O uint32_t SPDIF_Type::STR |
SPDIFTxRight Register, offset: 0x30
| __IO uint32_t USDHC_Type::STROBE_DLL_CTRL |
Strobe DLL control, offset: 0x70
| __I uint32_t USDHC_Type::STROBE_DLL_STATUS |
Strobe DLL status, offset: 0x74
| __IO uint16_t PWM_Type::STS |
Status Register, array offset: 0x24, array step: 0x60
| __IO uint16_t { ... } ::STS |
Status Register, array offset: 0x24, array step: 0x60
| __IO uint16_t { ... } ::STS |
Status Register, array offset: 0x24, array step: 0x60
| __IO uint16_t { ... } ::STS |
Status Register, array offset: 0x24, array step: 0x60
| __I uint32_t FLEXSPI_Type::STS0 |
Status Register 0, offset: 0xE0
| __I uint32_t SEMC_Type::STS0 |
Status register 0, offset: 0xC0
Status Register 0, offset: 0xC0
| __I uint32_t FLEXSPI_Type::STS1 |
Status Register 1, offset: 0xE4
| uint32_t SEMC_Type::STS1 |
Status register 1, offset: 0xC4
Status Register 1, offset: 0xC4
| uint32_t SEMC_Type::STS10 |
Status register 10, offset: 0xE8
Status Register 10, offset: 0xE8
| uint32_t SEMC_Type::STS11 |
Status register 11, offset: 0xEC
Status Register 11, offset: 0xEC
| __I uint32_t SEMC_Type::STS12 |
Status register 12, offset: 0xF0
Status Register 12, offset: 0xF0
| __I uint32_t SEMC_Type::STS13 |
Status register 13, offset: 0xF4
Status Register 13, offset: 0xF4
| __I uint32_t SEMC_Type::STS13 |
Status Register 13, offset: 0xF4
| uint32_t SEMC_Type::STS14 |
Status register 14, offset: 0xF8
Status Register 14, offset: 0xF8
| uint32_t SEMC_Type::STS15 |
Status register 15, offset: 0xFC
Status Register 15, offset: 0xFC
| __I uint32_t FLEXSPI_Type::STS2 |
Status Register 2, offset: 0xE8
| __I uint32_t SEMC_Type::STS2 |
Status register 2, offset: 0xC8
Status Register 2, offset: 0xC8
| uint32_t SEMC_Type::STS3 |
Status register 3, offset: 0xCC
Status Register 3, offset: 0xCC
| uint32_t SEMC_Type::STS4 |
Status register 4, offset: 0xD0
Status Register 4, offset: 0xD0
| uint32_t SEMC_Type::STS5 |
Status register 5, offset: 0xD4
Status Register 5, offset: 0xD4
| uint32_t SEMC_Type::STS6 |
Status register 6, offset: 0xD8
Status Register 6, offset: 0xD8
| uint32_t SEMC_Type::STS7 |
Status register 7, offset: 0xDC
Status Register 7, offset: 0xDC
| uint32_t SEMC_Type::STS8 |
Status register 8, offset: 0xE0
Status Register 8, offset: 0xE0
| uint32_t SEMC_Type::STS9 |
Status register 9, offset: 0xE4
Status Register 9, offset: 0xE4
| __O uint32_t CDOG_Type::SUB |
SUB Command, offset: 0x3C
| __O uint32_t CDOG_Type::SUB1 |
SUB1 Command, offset: 0x40
| __O uint32_t CDOG_Type::SUB16 |
SUB16 Command, offset: 0x44
| __O uint32_t CDOG_Type::SUB256 |
SUB256 Command, offset: 0x48
| __IO uint32_t OCOTP_Type::SW_GP1 |
Value of OTP Bank5 Word0 (SW GP1), offset: 0x680
| __IO uint32_t OCOTP_Type::SW_GP20 |
Value of OTP Bank5 Word1 (SW GP2), offset: 0x690
| __IO uint32_t OCOTP_Type::SW_GP21 |
Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0
| __IO uint32_t OCOTP_Type::SW_GP22 |
Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0
| __IO uint32_t OCOTP_Type::SW_GP23 |
Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0
| __I uint32_t SSARC_LP_Type::SW_GROUP_PENDING |
Software Request Pending Register, offset: 0x220
| __IO uint32_t OCOTP_Type::SW_LOCK |
SW_LOCK Register, offset: 0x140
| __IO uint32_t IOMUXC_Type::SW_MUX_CTL_PAD |
SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4
SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register, array offset: 0x10, array step: 0x4
| __IO uint32_t IOMUXC_LPSR_Type::SW_MUX_CTL_PAD |
SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register, array offset: 0x0, array step: 0x4
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG |
SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register, offset: 0xC
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG |
SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register, offset: 0x10
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG |
SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register, offset: 0x14
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG |
SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register, offset: 0x18
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG |
SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register, offset: 0x1C
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG |
SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register, offset: 0x20
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG |
SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register, offset: 0x24
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG |
SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register, offset: 0x28
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG |
SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register, offset: 0x2C
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG |
SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register, offset: 0x30
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_ON_REQ |
SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG |
SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register, offset: 0x4
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_STBY_REQ |
SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x8
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG |
SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register, offset: 0x8
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_WAKEUP |
SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register, offset: 0x0
| __IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_WAKEUP_DIG |
SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register, offset: 0x0
| __IO uint32_t IOMUXC_Type::SW_PAD_CTL_PAD |
SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4
SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register, array offset: 0x254, array step: 0x4
| __IO uint32_t IOMUXC_LPSR_Type::SW_PAD_CTL_PAD |
SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register, array offset: 0x40, array step: 0x4
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG |
SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register, offset: 0x4C
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG |
SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register, offset: 0x50
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG |
SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register, offset: 0x54
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG |
SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register, offset: 0x58
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG |
SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register, offset: 0x5C
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG |
SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register, offset: 0x60
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG |
SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register, offset: 0x64
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG |
SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register, offset: 0x68
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG |
SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register, offset: 0x6C
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG |
SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register, offset: 0x70
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_ONOFF |
SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_ONOFF_DIG |
SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register, offset: 0x3C
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_ON_REQ |
SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG |
SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register, offset: 0x44
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_STBY_REQ |
SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register, offset: 0x20
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG |
SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register, offset: 0x48
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_POR_B |
SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_POR_B_DIG |
SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register, offset: 0x38
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_TEST_MODE |
SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_TEST_MODE_DIG |
SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register, offset: 0x34
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_WAKEUP |
SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register, offset: 0x18
| __IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_WAKEUP_DIG |
SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register, offset: 0x40
| __IO uint32_t OCOTP_Type::SW_STICKY |
Sticky bit Register, offset: 0x50
| __IO uint16_t PWM_Type::SWCOUT |
Software Controlled Output Register, offset: 0x184
| __O uint32_t ADC_Type::SWTRIG |
Software Trigger Register, offset: 0x34
| __IO uint32_t USDHC_Type::SYS_CTRL |
System Control, offset: 0x2C
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL1_CTRL |
SYS_PLL1_CTRL_REGISTER, offset: 0x2C0
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL1_DENOMINATOR |
SYS_PLL1_DENOMINATOR_REGISTER, offset: 0x2D0
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL1_DIV_SELECT |
SYS_PLL1_DIV_SELECT_REGISTER, offset: 0x2F0
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL1_NUMERATOR |
SYS_PLL1_NUMERATOR_REGISTER, offset: 0x2E0
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL1_SS |
SYS_PLL1_SS_REGISTER, offset: 0x2B0
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL2_CTRL |
SYS_PLL2_CTRL_REGISTER, offset: 0x240
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL2_MFD |
SYS_PLL2_MFD_REGISTER, offset: 0x2A0
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL2_PFD |
SYS_PLL2_PFD_REGISTER, offset: 0x270
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL2_SS |
SYS_PLL2_SS_REGISTER, offset: 0x260
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL2_UPDATE |
SYS_PLL2_UPDATE_REGISTER, offset: 0x250
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL3_CTRL |
SYS_PLL3_CTRL_REGISTER, offset: 0x210
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL3_PFD |
SYS_PLL3_PFD_REGISTER, offset: 0x230
| __IO uint32_t ANADIG_PLL_Type::SYS_PLL3_UPDATE |
SYS_PLL3_UPDATE_REGISTER, offset: 0x220
| __IO uint32_t ENET_Type::TACC |
Transmit Accelerator Function Configuration, offset: 0x1C0
| __IO uint32_t ENET_Type::TAEM |
Transmit FIFO Almost Empty Threshold, offset: 0x1A4
| __IO uint32_t ENET_Type::TAFL |
Transmit FIFO Almost Full Threshold, offset: 0x1A8
| __IO uint32_t { ... } ::TCCR |
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8
| __IO uint32_t ENET_Type::TCCR |
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8
| __IO uint32_t { ... } ::TCCR |
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8
| __IO uint32_t { ... } ::TCCR |
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8
| __IO uint32_t FLEXRAM_Type::TCM_CTRL |
TCM CRTL Register, offset: 0x0
| __IO uint32_t ENET_Type::TCR |
Transmit Control Register, offset: 0xC4
| __IO uint32_t LPSPI_Type::TCR |
Transmit Command Register, offset: 0x60
Transmit Command, offset: 0x60
| __IO uint32_t I2S_Type::TCR1 |
SAI Transmit Configuration 1 Register, offset: 0xC
Transmit Configuration 1, offset: 0xC
| __IO uint32_t I2S_Type::TCR2 |
SAI Transmit Configuration 2 Register, offset: 0x10
Transmit Configuration 2, offset: 0x10
| __IO uint32_t I2S_Type::TCR3 |
SAI Transmit Configuration 3 Register, offset: 0x14
Transmit Configuration 3, offset: 0x14
| __IO uint32_t I2S_Type::TCR4 |
SAI Transmit Configuration 4 Register, offset: 0x18
Transmit Configuration 4, offset: 0x18
| __IO uint32_t I2S_Type::TCR5 |
SAI Transmit Configuration 5 Register, offset: 0x1C
Transmit Configuration 5, offset: 0x1C
| __IO uint32_t ENET_Type::TCSR |
Timer Control Status Register, array offset: 0x608, array step: 0x8
| __IO uint32_t { ... } ::TCSR |
Timer Control Status Register, array offset: 0x608, array step: 0x8
| __IO uint32_t I2S_Type::TCSR |
SAI Transmit Control Register, offset: 0x8
Transmit Control, offset: 0x8
| __IO uint32_t { ... } ::TCSR |
Timer Control Status Register, array offset: 0x608, array step: 0x8
| __IO uint32_t { ... } ::TCSR |
Timer Control Status Register, array offset: 0x608, array step: 0x8
| __IO uint32_t { ... } ::TCTRL |
Timer Control Register, array offset: 0x108, array step: 0x10
| __IO uint32_t PIT_Type::TCTRL |
Timer Control Register, array offset: 0x108, array step: 0x10
| __IO uint16_t PWM_Type::TCTRL |
Output Trigger Control Register, array offset: 0x2A, array step: 0x60
| __IO uint16_t { ... } ::TCTRL |
Output Trigger Control Register, array offset: 0x2A, array step: 0x60
| __IO uint32_t ADC_Type::TCTRL |
Trigger Control Register, array offset: 0xC0, array step: 0x4
| __IO uint32_t { ... } ::TCTRL |
Timer Control Register, array offset: 0x108, array step: 0x10
| __IO uint16_t { ... } ::TCTRL |
Output Trigger Control Register, array offset: 0x2A, array step: 0x60
| __IO uint32_t { ... } ::TCTRL |
Timer Control Register, array offset: 0x108, array step: 0x10
| __IO uint16_t { ... } ::TCTRL |
Output Trigger Control Register, array offset: 0x2A, array step: 0x60
| __IO uint32_t ENET_Type::TDAR |
Transmit Descriptor Active Register - Ring 0, offset: 0x14
| __IO uint32_t ENET_Type::TDAR1 |
Transmit Descriptor Active Register - Ring 1, offset: 0x1E4
| __IO uint32_t ENET_Type::TDAR2 |
Transmit Descriptor Active Register - Ring 2, offset: 0x1EC
| __IO uint32_t CAAM_Type::TDKEKR |
Trusted Descriptor Key Encryption Key Register, array offset: 0x420, array step: 0x4
| __O uint32_t I2S_Type::TDR |
SAI Transmit Data Register, array offset: 0x20, array step: 0x4
Transmit Data, array offset: 0x20, array step: 0x4
| __O uint32_t LPSPI_Type::TDR |
Transmit Data Register, offset: 0x64
Transmit Data, offset: 0x64
| __IO uint32_t CAAM_Type::TDSKR |
Trusted Descriptor Signing Key Register, array offset: 0x440, array step: 0x4
| __IO uint32_t ENET_Type::TDSR |
Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184
| __IO uint32_t ENET_Type::TDSR1 |
Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164
| __IO uint32_t ENET_Type::TDSR2 |
Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170
| __IO uint32_t TEMPMON_Type::TEMPSENSE0 |
Tempsensor Control Register 0, offset: 0x180
| __IO uint32_t TEMPMON_Type::TEMPSENSE0_CLR |
Tempsensor Control Register 0, offset: 0x188
| __IO uint32_t TEMPMON_Type::TEMPSENSE0_SET |
Tempsensor Control Register 0, offset: 0x184
| __IO uint32_t TEMPMON_Type::TEMPSENSE0_TOG |
Tempsensor Control Register 0, offset: 0x18C
| __IO uint32_t TEMPMON_Type::TEMPSENSE1 |
Tempsensor Control Register 1, offset: 0x190
| __IO uint32_t TEMPMON_Type::TEMPSENSE1_CLR |
Tempsensor Control Register 1, offset: 0x198
| __IO uint32_t TEMPMON_Type::TEMPSENSE1_SET |
Tempsensor Control Register 1, offset: 0x194
| __IO uint32_t TEMPMON_Type::TEMPSENSE1_TOG |
Tempsensor Control Register 1, offset: 0x19C
| __IO uint32_t TEMPMON_Type::TEMPSENSE2 |
Tempsensor Control Register 2, offset: 0x290
| __IO uint32_t TEMPMON_Type::TEMPSENSE2_CLR |
Tempsensor Control Register 2, offset: 0x298
| __IO uint32_t TEMPMON_Type::TEMPSENSE2_SET |
Tempsensor Control Register 2, offset: 0x294
| __IO uint32_t TEMPMON_Type::TEMPSENSE2_TOG |
Tempsensor Control Register 2, offset: 0x29C
| __IO uint32_t ANADIG_TEMPSENSOR_Type::TEMPSENSOR |
Tempsensor Register, offset: 0x400
| __I uint32_t ANADIG_TEMPSENSOR_Type::TEMPSNS_OTP_TRIM_VALUE |
TEMPSNS_OTP_TRIM_VALUE_REGISTER, offset: 0x430
| __O uint32_t FLEXSPI_Type::TFDR |
IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4
| __IO uint32_t PIT_Type::TFLG |
Timer Flag Register, array offset: 0x10C, array step: 0x10
| __IO uint32_t { ... } ::TFLG |
Timer Flag Register, array offset: 0x10C, array step: 0x10
| __IO uint32_t { ... } ::TFLG |
Timer Flag Register, array offset: 0x10C, array step: 0x10
| __IO uint32_t { ... } ::TFLG |
Timer Flag Register, array offset: 0x10C, array step: 0x10
| __I uint32_t I2S_Type::TFR |
SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4
Transmit FIFO, array offset: 0x40, array step: 0x4
| __IO uint32_t ENET_Type::TFWR |
Transmit FIFO Watermark Register, offset: 0x144
| __IO uint32_t ENET_Type::TGSR |
Timer Global Status Register, offset: 0x604
| __IO uint32_t LCDIF_Type::THRES |
LCDIF Threshold Register, offset: 0x200
| __IO uint32_t FLEXIO_Type::TIMCFG |
Timer Configuration N Register, array offset: 0x480, array step: 0x4
| __IO uint32_t FLEXIO_Type::TIMCMP |
Timer Compare N Register, array offset: 0x500, array step: 0x4
| __IO uint32_t FLEXIO_Type::TIMCTL |
Timer Control N Register, array offset: 0x400, array step: 0x4
| __IO uint32_t CAN_Type::TIMER |
Free Running Timer Register, offset: 0x8
Free Running Timer, offset: 0x8
| __IO uint32_t USBHSDCD_Type::TIMER0 |
TIMER0 register, offset: 0x10
| __IO uint32_t USBHSDCD_Type::TIMER1 |
TIMER1 register, offset: 0x14
| __IO uint32_t USBHSDCD_Type::TIMER2_BC11 |
TIMER2_BC11 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC11 |
TIMER2_BC11 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC11 |
TIMER2_BC11 register, offset: 0x18
| __IO uint32_t USBHSDCD_Type::TIMER2_BC12 |
TIMER2_BC12 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC12 |
TIMER2_BC12 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC12 |
TIMER2_BC12 register, offset: 0x18
| __IO uint32_t FLEXIO_Type::TIMERSDEN |
Timer Status DMA Enable, offset: 0x38
| __IO uint32_t FLEXIO_Type::TIMIEN |
Timer Interrupt Enable Register, offset: 0x28
| __IO uint32_t OCOTP_Type::TIMING |
OTP Controller Timing Register, offset: 0x10
| __IO uint32_t OCOTP_Type::TIMING2 |
OTP Controller Timing Register 2, offset: 0x100
| __IO uint32_t FLEXIO_Type::TIMSTAT |
Timer Status Register, offset: 0x18
| __IO uint32_t ENET_Type::TIPG |
Transmit Inter-Packet Gap, offset: 0x1AC
| __IO uint32_t I2S_Type::TMR |
SAI Transmit Mask Register, offset: 0x60
Transmit Mask, offset: 0x60
| __IO uint32_t AUDIO_PLL_Type::TOG |
Fractional PLL Control Register, offset: 0xC
Fractional PLL Spread Spectrum Control Register, offset: 0x1C
Fractional PLL Numerator Control Register, offset: 0x2C
Fractional PLL Denominator Control Register, offset: 0x3C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Control Register, offset: 0xC
| __IO uint32_t { ... } ::TOG |
Fractional PLL Spread Spectrum Control Register, offset: 0x1C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Numerator Control Register, offset: 0x2C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Denominator Control Register, offset: 0x3C
| __IO uint32_t { ... } ::TOG |
General Purpose Register, array offset: 0x480C, array step: 0x20
| __IO uint32_t CCM_Type::TOG |
General Purpose Register, array offset: 0x480C, array step: 0x20
| __IO uint32_t { ... } ::TOG |
Fractional PLL Control Register, offset: 0xC
| __IO uint32_t ETHERNET_PLL_Type::TOG |
Fractional PLL Control Register, offset: 0xC
Fractional PLL Spread Spectrum Control Register, offset: 0x1C
Fractional PLL Numerator Control Register, offset: 0x2C
Fractional PLL Denominator Control Register, offset: 0x3C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Spread Spectrum Control Register, offset: 0x1C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Numerator Control Register, offset: 0x2C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Denominator Control Register, offset: 0x3C
| __IO uint32_t OSC_RC_400M_Type::TOG |
Control Register 0, offset: 0xC
Control Register 1, offset: 0x1C
Control Register 2, offset: 0x2C
Control Register 3, offset: 0x3C
| __IO uint32_t { ... } ::TOG |
Control Register 0, offset: 0xC
| __IO uint32_t { ... } ::TOG |
Control Register 1, offset: 0x1C
| __IO uint32_t { ... } ::TOG |
Control Register 2, offset: 0x2C
| __IO uint32_t { ... } ::TOG |
Control Register 3, offset: 0x3C
| __I uint32_t OSC_RC_400M_Type::TOG |
Status Register 0, offset: 0x5C
Status Register 1, offset: 0x6C
Status Register 2, offset: 0x7C
| __I uint32_t { ... } ::TOG |
Status Register 0, offset: 0x5C
| __I uint32_t { ... } ::TOG |
Status Register 1, offset: 0x6C
| __I uint32_t { ... } ::TOG |
Status Register 2, offset: 0x7C
| __IO uint32_t { ... } ::TOG |
Analog Control Register CTRL0, offset: 0xC
| __IO uint32_t PHY_LDO_Type::TOG |
Analog Control Register CTRL0, offset: 0xC
| __I uint32_t PHY_LDO_Type::TOG |
Analog Status Register STAT0, offset: 0x5C
| __I uint32_t { ... } ::TOG |
Analog Status Register STAT0, offset: 0x5C
| __IO uint32_t VIDEO_MUX_Type::TOG |
Video mux Control Register, offset: 0xC
Pixel Link Master(PLM) Control Register, offset: 0x2C
YUV420 Control Register, offset: 0x3C
Data Disable Register, offset: 0x5C
MIPI DSI Control Register, offset: 0x7C
| __IO uint32_t { ... } ::TOG |
Video mux Control Register, offset: 0xC
| __IO uint32_t { ... } ::TOG |
Pixel Link Master(PLM) Control Register, offset: 0x2C
| __IO uint32_t { ... } ::TOG |
YUV420 Control Register, offset: 0x3C
| __IO uint32_t { ... } ::TOG |
Data Disable Register, offset: 0x5C
| __IO uint32_t { ... } ::TOG |
MIPI DSI Control Register, offset: 0x7C
| __IO uint32_t VIDEO_PLL_Type::TOG |
Fractional PLL Control Register, offset: 0xC
Fractional PLL Spread Spectrum Control Register, offset: 0x1C
Fractional PLL Numerator Control Register, offset: 0x2C
Fractional PLL Denominator Control Register, offset: 0x3C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Control Register, offset: 0xC
| __IO uint32_t { ... } ::TOG |
Fractional PLL Spread Spectrum Control Register, offset: 0x1C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Numerator Control Register, offset: 0x2C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Denominator Control Register, offset: 0x3C
| __IO uint32_t { ... } ::TOG |
Analog Control Register CTRL0, offset: 0xC
| __IO uint32_t VMBANDGAP_Type::TOG |
Analog Control Register CTRL0, offset: 0xC
| __I uint32_t VMBANDGAP_Type::TOG |
Analog Status Register STAT0, offset: 0x5C
| __I uint32_t { ... } ::TOG |
Analog Status Register STAT0, offset: 0x5C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Control Register, offset: 0xC
| __IO uint32_t { ... } ::TOG |
Fractional PLL Spread Spectrum Control Register, offset: 0x1C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Numerator Control Register, offset: 0x2C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Denominator Control Register, offset: 0x3C
| __IO uint32_t { ... } ::TOG |
General Purpose Register, array offset: 0x480C, array step: 0x20
| __IO uint32_t { ... } ::TOG |
Fractional PLL Control Register, offset: 0xC
| __IO uint32_t { ... } ::TOG |
Fractional PLL Spread Spectrum Control Register, offset: 0x1C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Numerator Control Register, offset: 0x2C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Denominator Control Register, offset: 0x3C
| __IO uint32_t { ... } ::TOG |
Control Register 0, offset: 0xC
| __IO uint32_t { ... } ::TOG |
Control Register 1, offset: 0x1C
| __IO uint32_t { ... } ::TOG |
Control Register 2, offset: 0x2C
| __IO uint32_t { ... } ::TOG |
Control Register 3, offset: 0x3C
| __I uint32_t { ... } ::TOG |
Status Register 0, offset: 0x5C
| __I uint32_t { ... } ::TOG |
Status Register 1, offset: 0x6C
| __I uint32_t { ... } ::TOG |
Status Register 2, offset: 0x7C
| __IO uint32_t { ... } ::TOG |
Analog Control Register CTRL0, offset: 0xC
| __I uint32_t { ... } ::TOG |
Analog Status Register STAT0, offset: 0x5C
| __IO uint32_t { ... } ::TOG |
Video mux Control Register, offset: 0xC
| __IO uint32_t { ... } ::TOG |
Pixel Link Master(PLM) Control Register, offset: 0x2C
| __IO uint32_t { ... } ::TOG |
YUV420 Control Register, offset: 0x3C
| __IO uint32_t { ... } ::TOG |
Data Disable Register, offset: 0x5C
| __IO uint32_t { ... } ::TOG |
MIPI DSI Control Register, offset: 0x7C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Control Register, offset: 0xC
| __IO uint32_t { ... } ::TOG |
Fractional PLL Spread Spectrum Control Register, offset: 0x1C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Numerator Control Register, offset: 0x2C
| __IO uint32_t { ... } ::TOG |
Fractional PLL Denominator Control Register, offset: 0x3C
| __IO uint32_t { ... } ::TOG |
Analog Control Register CTRL0, offset: 0xC
| __I uint32_t { ... } ::TOG |
Analog Status Register STAT0, offset: 0x5C
| __I uint32_t TRNG_Type::TOTSAM |
Total Samples Register, offset: 0x14
| __I uint32_t { ... } ::TOTSAM |
Total Samples Register, offset: 0x14
| __IO uint32_t RTWDOG_Type::TOVAL |
Watchdog Timeout Value Register, offset: 0x8
| __IO uint32_t MU_Type::TR |
Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array step: 0x4
Processor A Transmit Register 0..Processor A Transmit Register 3, array offset: 0x0, array step: 0x4
| __IO uint32_t LCDIF_Type::TRANSFER_COUNT |
LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30
| __IO uint32_t { ... } ::TRIGn_CHAIN_1_0 |
ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28
| __IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_1_0 |
ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CHAIN_1_0 |
ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CHAIN_1_0 |
ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CHAIN_3_2 |
ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28
| __IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_3_2 |
ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CHAIN_3_2 |
ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CHAIN_3_2 |
ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28
| __IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_5_4 |
ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CHAIN_5_4 |
ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CHAIN_5_4 |
ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CHAIN_5_4 |
ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28
| __IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_7_6 |
ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CHAIN_7_6 |
ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CHAIN_7_6 |
ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CHAIN_7_6 |
ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_COUNTER |
ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28
| __IO uint32_t ADC_ETC_Type::TRIGn_COUNTER |
ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_COUNTER |
ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_COUNTER |
ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28
| __IO uint32_t ADC_ETC_Type::TRIGn_CTRL |
ETC_TRIG Control Register, array offset: 0x10, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CTRL |
ETC_TRIG Control Register, array offset: 0x10, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CTRL |
ETC_TRIG Control Register, array offset: 0x10, array step: 0x28
| __IO uint32_t { ... } ::TRIGn_CTRL |
ETC_TRIG Control Register, array offset: 0x10, array step: 0x28
| __I uint32_t ADC_ETC_Type::TRIGn_RESULT_1_0 |
ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_1_0 |
ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_1_0 |
ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_1_0 |
ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28
| __I uint32_t ADC_ETC_Type::TRIGn_RESULT_3_2 |
ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_3_2 |
ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_3_2 |
ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_3_2 |
ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28
| __I uint32_t ADC_ETC_Type::TRIGn_RESULT_5_4 |
ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_5_4 |
ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_5_4 |
ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_5_4 |
ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28
| __I uint32_t ADC_ETC_Type::TRIGn_RESULT_7_6 |
ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_7_6 |
ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_7_6 |
ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28
| __I uint32_t { ... } ::TRIGn_RESULT_7_6 |
ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28
| __IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN |
USB PHY Trim Override Enable Register, offset: 0x130
| __IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_CLR |
USB PHY Trim Override Enable Register, offset: 0x138
| __IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_SET |
USB PHY Trim Override Enable Register, offset: 0x134
| __IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_TOG |
USB PHY Trim Override Enable Register, offset: 0x13C
| __IO uint32_t ENET_Type::TSEM |
Transmit FIFO Section Empty Threshold, offset: 0x1A0
| __IO uint16_t ENC_Type::TST |
Test Register, offset: 0x1C
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::TST |
TST, offset: 0x20
| __IO uint32_t IEE_Type::TSTMD |
IEE Test Mode Register, offset: 0x8
| __IO uint32_t USDHC_Type::TUNING_CTRL |
Tuning Control, offset: 0xCC
| __IO uint32_t USBPHY_Type::TX |
USB PHY Transmitter Control Register, offset: 0x10
| __O uint32_t EMVSIM_Type::TX_BUF |
Transmit Data Buffer, offset: 0x30
| __IO uint32_t USBPHY_Type::TX_CLR |
USB PHY Transmitter Control Register, offset: 0x18
| __IO uint32_t EMVSIM_Type::TX_GETU |
Transmitter Guard ETU Value Register, offset: 0x34
| __IO uint32_t DSI_HOST_APB_PKT_IF_Type::TX_PAYLOAD |
TX_PAYLOAD, offset: 0x0
| __IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::TX_RCAL |
TX_RCAL, offset: 0x38
| __IO uint32_t USBPHY_Type::TX_SET |
USB PHY Transmitter Control Register, offset: 0x14
| __IO uint32_t EMVSIM_Type::TX_STATUS |
Transmitter Status Register, offset: 0x24
| __IO uint32_t EMVSIM_Type::TX_THD |
Transmitter Threshold Register, offset: 0x1C
| __IO uint32_t USBPHY_Type::TX_TOG |
USB PHY Transmitter Control Register, offset: 0x1C
| __IO uint32_t USB_Type::TXFILLTUNING |
TX FIFO Fill Tuning, offset: 0x164
| __IO uint32_t ENET_Type::TXIC |
Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4
| __IO uint16_t ENC_Type::UCOMP |
Upper Position Compare Register, offset: 0x24
| __IO uint16_t ENC_Type::UINIT |
Upper Initialization Register, offset: 0x16
| __I uint32_t MIPI_CSI2RX_Type::ULPS_STATUS |
Ultra Low Power State (ULPS) Status Register, offset: 0x114
| __IO uint16_t ENC_Type::UMOD |
Upper Modulus Register, offset: 0x20
| __IO uint16_t ENC_Type::UPOS |
Upper Position Counter Register, offset: 0xE
| __I uint16_t ENC_Type::UPOSH |
Upper Position Hold Register, offset: 0x12
| __I uint32_t USBPHY_Type::USB1_CHRG_DET_STAT |
USB PHY Charger Detect Status Register, offset: 0xF0
| __IO uint32_t USBPHY_Type::USB1_CHRG_DETECT |
USB PHY Charger Detect Control Register, offset: 0xE0
| __IO uint32_t USBPHY_Type::USB1_CHRG_DETECT_CLR |
USB PHY Charger Detect Control Register, offset: 0xE8
| __IO uint32_t USBPHY_Type::USB1_CHRG_DETECT_SET |
USB PHY Charger Detect Control Register, offset: 0xE4
| __IO uint32_t USBPHY_Type::USB1_CHRG_DETECT_TOG |
USB PHY Charger Detect Control Register, offset: 0xEC
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK |
USB PHY Loopback Control/Status Register, offset: 0x110
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_CLR |
USB PHY Loopback Control/Status Register, offset: 0x118
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT |
USB PHY Loopback Packet Number Select Register, offset: 0x120
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_CLR |
USB PHY Loopback Packet Number Select Register, offset: 0x128
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_SET |
USB PHY Loopback Packet Number Select Register, offset: 0x124
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_TOG |
USB PHY Loopback Packet Number Select Register, offset: 0x12C
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_SET |
USB PHY Loopback Control/Status Register, offset: 0x114
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_TOG |
USB PHY Loopback Control/Status Register, offset: 0x11C
| __I uint32_t USBPHY_Type::USB1_VBUS_DET_STAT |
USB PHY VBUS Detector Status Register, offset: 0xD0
| __IO uint32_t USBPHY_Type::USB1_VBUS_DETECT |
USB PHY VBUS Detect Control Register, offset: 0xC0
| __IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_CLR |
USB PHY VBUS Detect Control Register, offset: 0xC8
| __IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_SET |
USB PHY VBUS Detect Control Register, offset: 0xC4
| __IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_TOG |
USB PHY VBUS Detect Control Register, offset: 0xCC
| __IO uint32_t USBNC_Type::USB_OTGn_CTRL |
USB OTG1 Control Register..USB OTG2 Control Register, offset: 0x800
| __IO uint32_t USBNC_Type::USB_OTGn_PHY_CTRL_0 |
OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register, offset: 0x818
| __IO uint32_t USB_Type::USBCMD |
USB Command Register, offset: 0x140
| __IO uint32_t USB_Type::USBINTR |
Interrupt Enable Register, offset: 0x148
| __IO uint32_t USB_Type::USBMODE |
USB Device Mode, offset: 0x1A8
| __IO uint32_t USB_Type::USBSTS |
USB Status Register, offset: 0x144
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::USE_NULL_PKT_BLLP |
USE_NULL_PKT_BLLP, offset: 0x38
| __IO uint32_t CAAM_Type::UVSIL |
Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C
| __IO uint32_t { ... } ::UVSIL |
Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C
| __IO uint32_t { ... } ::UVSIL |
Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C
| __IO uint32_t CAAM_Type::UVSOL |
Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C
| __IO uint32_t { ... } ::UVSOL |
Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C
| __IO uint32_t { ... } ::UVSOL |
Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::VACTIVE |
VACTIVE, offset: 0x3C
| __IO uint32_t PDM_Type::VAD0_CTRL_1 |
Voice Activity Detector 0 Control register, offset: 0x90
| __IO uint32_t PDM_Type::VAD0_CTRL_2 |
Voice Activity Detector 0 Control register, offset: 0x94
| __IO uint32_t PDM_Type::VAD0_NCONFIG |
Voice Activity Detector 0 Noise Configuration, offset: 0xA0
| __I uint32_t PDM_Type::VAD0_NDATA |
Voice Activity Detector 0 Noise Data, offset: 0xA4
| __IO uint32_t PDM_Type::VAD0_SCONFIG |
Voice Activity Detector 0 Signal Configuration, offset: 0x9C
| __IO uint32_t PDM_Type::VAD0_STAT |
Voice Activity Detector 0 Status register, offset: 0x98
| __IO uint32_t PDM_Type::VAD0_ZCD |
Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8
| __IO uint16_t PWM_Type::VAL0 |
Value Register 0, array offset: 0xA, array step: 0x60
| __IO uint16_t { ... } ::VAL0 |
Value Register 0, array offset: 0xA, array step: 0x60
| __IO uint16_t { ... } ::VAL0 |
Value Register 0, array offset: 0xA, array step: 0x60
| __IO uint16_t { ... } ::VAL0 |
Value Register 0, array offset: 0xA, array step: 0x60
| __IO uint16_t PWM_Type::VAL1 |
Value Register 1, array offset: 0xE, array step: 0x60
| __IO uint16_t { ... } ::VAL1 |
Value Register 1, array offset: 0xE, array step: 0x60
| __IO uint16_t { ... } ::VAL1 |
Value Register 1, array offset: 0xE, array step: 0x60
| __IO uint16_t { ... } ::VAL1 |
Value Register 1, array offset: 0xE, array step: 0x60
| __IO uint16_t PWM_Type::VAL2 |
Value Register 2, array offset: 0x12, array step: 0x60
| __IO uint16_t { ... } ::VAL2 |
Value Register 2, array offset: 0x12, array step: 0x60
| __IO uint16_t { ... } ::VAL2 |
Value Register 2, array offset: 0x12, array step: 0x60
| __IO uint16_t { ... } ::VAL2 |
Value Register 2, array offset: 0x12, array step: 0x60
| __IO uint16_t PWM_Type::VAL3 |
Value Register 3, array offset: 0x16, array step: 0x60
| __IO uint16_t { ... } ::VAL3 |
Value Register 3, array offset: 0x16, array step: 0x60
| __IO uint16_t { ... } ::VAL3 |
Value Register 3, array offset: 0x16, array step: 0x60
| __IO uint16_t { ... } ::VAL3 |
Value Register 3, array offset: 0x16, array step: 0x60
| __IO uint16_t PWM_Type::VAL4 |
Value Register 4, array offset: 0x1A, array step: 0x60
| __IO uint16_t { ... } ::VAL4 |
Value Register 4, array offset: 0x1A, array step: 0x60
| __IO uint16_t { ... } ::VAL4 |
Value Register 4, array offset: 0x1A, array step: 0x60
| __IO uint16_t { ... } ::VAL4 |
Value Register 4, array offset: 0x1A, array step: 0x60
| __IO uint16_t PWM_Type::VAL5 |
Value Register 5, array offset: 0x1E, array step: 0x60
| __IO uint16_t { ... } ::VAL5 |
Value Register 5, array offset: 0x1E, array step: 0x60
| __IO uint16_t { ... } ::VAL5 |
Value Register 5, array offset: 0x1E, array step: 0x60
| __IO uint16_t { ... } ::VAL5 |
Value Register 5, array offset: 0x1E, array step: 0x60
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::VBP |
VBP, offset: 0x2C
| __IO uint32_t { ... } ::VBUS_DETECT |
USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::VBUS_DETECT |
USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60
| __IO uint32_t { ... } ::VBUS_DETECT_CLR |
USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::VBUS_DETECT_CLR |
USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60
| __IO uint32_t { ... } ::VBUS_DETECT_SET |
USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::VBUS_DETECT_SET |
USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60
| __I uint32_t { ... } ::VBUS_DETECT_STAT |
USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60
| __I uint32_t USB_ANALOG_Type::VBUS_DETECT_STAT |
USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60
| __IO uint32_t { ... } ::VBUS_DETECT_TOG |
USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60
| __IO uint32_t USB_ANALOG_Type::VBUS_DETECT_TOG |
USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60
| __IO uint32_t LCDIF_Type::VDCTRL0 |
LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70
| __IO uint32_t LCDIF_Type::VDCTRL0_CLR |
LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78
| __IO uint32_t LCDIF_Type::VDCTRL0_SET |
LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74
| __IO uint32_t LCDIF_Type::VDCTRL0_TOG |
LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C
| __IO uint32_t LCDIF_Type::VDCTRL1 |
LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80
| __IO uint32_t LCDIF_Type::VDCTRL2 |
LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90
| __IO uint32_t LCDIF_Type::VDCTRL3 |
LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0
| __IO uint32_t LCDIF_Type::VDCTRL4 |
LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0
| __IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI400M_CTRL |
VDDLPSR_AI400M_CTRL_REGISTER, offset: 0x920
| __I uint32_t ANADIG_MISC_Type::VDDLPSR_AI400M_RDATA |
VDDLPSR_AI400M_RDATA_REGISTER, offset: 0x940
| __IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI400M_WDATA |
VDDLPSR_AI400M_WDATA_REGISTER, offset: 0x930
| __IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI_CTRL |
VDDSOC_AI_CTRL_REGISTER, offset: 0x8E0
| __I uint32_t ANADIG_MISC_Type::VDDLPSR_AI_RDATA_REFTOP |
VDDLPSR_AI_RDATA_REFTOP_REGISTER, offset: 0x900
| __I uint32_t ANADIG_MISC_Type::VDDLPSR_AI_RDATA_TMPSNS |
VDDLPSR_AI_RDATA_TMPSNS_REGISTER, offset: 0x910
| __IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI_WDATA |
VDDLPSR_AI_WDATA_REGISTER, offset: 0x8F0
| __IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_CTRL_1G |
VDDSOC2PLL_AI_CTRL_1G_REGISTER, offset: 0x850
| __IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_CTRL_AUDIO |
VDDSOC_AI_CTRL_AUDIO_REGISTER, offset: 0x880
| __IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_CTRL_VIDEO |
VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER, offset: 0x8B0
| __I uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_RDATA_1G |
VDDSOC2PLL_AI_RDATA_1G_REGISTER, offset: 0x870
| __I uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_RDATA_AUDIO |
VDDSOC2PLL_AI_RDATA_REGISTER, offset: 0x8A0
| __I uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_RDATA_VIDEO |
VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER, offset: 0x8D0
| __IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_WDATA_1G |
VDDSOC2PLL_AI_WDATA_1G_REGISTER, offset: 0x860
| __IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_WDATA_AUDIO |
VDDSOC_AI_WDATA_AUDIO_REGISTER, offset: 0x890
| __IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_WDATA_VIDEO |
VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER, offset: 0x8C0
| __IO uint32_t ANADIG_MISC_Type::VDDSOC_AI_CTRL |
VDDSOC_AI_CTRL_REGISTER, offset: 0x820
| __I uint32_t ANADIG_MISC_Type::VDDSOC_AI_RDATA |
VDDSOC_AI_RDATA_REGISTER, offset: 0x840
| __IO uint32_t ANADIG_MISC_Type::VDDSOC_AI_WDATA |
VDDSOC_AI_WDATA_REGISTER, offset: 0x830
| __IO uint32_t USDHC_Type::VEND_SPEC |
Vendor Specific Register, offset: 0xC0
| __IO uint32_t USDHC_Type::VEND_SPEC2 |
Vendor Specific 2 Register, offset: 0xC8
| __I uint32_t EMVSIM_Type::VER_ID |
Version ID Register, offset: 0x0
| __I uint32_t FLEXIO_Type::VERID |
Version ID Register, offset: 0x0
| __I uint32_t I2S_Type::VERID |
Version ID Register, offset: 0x0
Version ID, offset: 0x0
| __I uint32_t LPI2C_Type::VERID |
Version ID Register, offset: 0x0
Version ID, offset: 0x0
| __I uint32_t LPSPI_Type::VERID |
Version ID Register, offset: 0x0
Version ID, offset: 0x0
| __I uint32_t LPUART_Type::VERID |
Version ID Register, offset: 0x0
| __I uint32_t ADC_Type::VERID |
Version ID Register, offset: 0x0
| __I uint32_t CMP_Type::VERID |
Version ID Register, offset: 0x0
| __I uint32_t DAC_Type::VERID |
Version Identifier Register, offset: 0x0
| __I uint32_t DCP_Type::VERSION |
DCP version register, offset: 0x430
| __I uint32_t OCOTP_Type::VERSION |
OTP Controller Version Register, offset: 0x90
OTP Controller Version Register, offset: 0xB0
| __I uint32_t USBPHY_Type::VERSION |
UTMI RTL Version, offset: 0x80
| __I uint32_t PUF_Type::VERSION |
PUF Version Register, offset: 0xFC
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::VFP |
VFP, offset: 0x30
| __I uint32_t TRNG_Type::VID1 |
Version ID Register (MS), offset: 0xF0
| __I uint32_t TRNG_Type::VID2 |
Version ID Register (LS), offset: 0xF4
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::VIDEO_MODE |
VIDEO_MODE, offset: 0x18
| __I uint32_t IEE_Type::VIDR1 |
IEE Version ID Register 1, offset: 0xF0
| __I uint32_t RDC_Type::VIR |
Version Information, offset: 0x0
| __IO uint32_t CAAM_Type::VSIL |
Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C
| __IO uint32_t { ... } ::VSIL |
Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C
| __IO uint32_t { ... } ::VSIL |
Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C
| __IO uint32_t CAAM_Type::VSOL |
Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C
| __IO uint32_t { ... } ::VSOL |
Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C
| __IO uint32_t { ... } ::VSOL |
Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C
| __IO uint32_t LCDIFV2_Type::VSYN_PARA |
Vertical Sync Parameter Register, offset: 0x1C
| __IO uint32_t DSI_HOST_DPI_INTFC_Type::VSYNC_POLARITY |
VSYNC_POLARITY, offset: 0x10
| __IO uint32_t LPUART_Type::WATER |
LPUART Watermark Register, offset: 0x2C
| __IO uint16_t WDOG_Type::WCR |
Watchdog Control Register, offset: 0x0
| __IO uint16_t WDOG_Type::WICR |
Watchdog Interrupt Control Register, offset: 0x6
| __IO uint32_t RTWDOG_Type::WIN |
Watchdog Window Register, offset: 0xC
| __IO uint16_t WDOG_Type::WMCR |
Watchdog Miscellaneous Control Register, offset: 0x8
| __IO uint32_t { ... } ::WORD[16] |
Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4
| __IO uint32_t { ... } ::WORD[16] |
Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x288, array step: index*0x48, index2*0x4
| __IO uint32_t { ... } ::WORD[16] |
Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4
| __IO uint32_t { ... } ::WORD[16] |
Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x288, array step: index*0x48, index2*0x4
| __IO uint32_t { ... } ::WORD[2] |
Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4
| __IO uint32_t CAN_Type::WORD[16] |
Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4
Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4
Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x288, array step: index*0x18, index2*0x4
Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4
Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x288, array step: index*0x28, index2*0x4
Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4
Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x288, array step: index*0x48, index2*0x4
| __IO uint32_t { ... } ::WORD[2] |
Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4
| __IO uint32_t { ... } ::WORD[4] |
Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4
| __IO uint32_t { ... } ::WORD[4] |
Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x288, array step: index*0x18, index2*0x4
| __IO uint32_t { ... } ::WORD[4] |
Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4
| __IO uint32_t { ... } ::WORD[4] |
Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x288, array step: index*0x18, index2*0x4
| __IO uint32_t { ... } ::WORD[8] |
Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4
| __IO uint32_t { ... } ::WORD[8] |
Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x288, array step: index*0x28, index2*0x4
| __IO uint32_t { ... } ::WORD[8] |
Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4
| __IO uint32_t { ... } ::WORD[8] |
Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x288, array step: index*0x28, index2*0x4
| __IO uint32_t { ... } ::WORD0 |
Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10
| __IO uint32_t CAN_Type::WORD0 |
Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10
| __IO uint32_t { ... } ::WORD0 |
Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10
| __IO uint32_t { ... } ::WORD0 |
Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10
| __IO uint32_t { ... } ::WORD1 |
Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10
| __IO uint32_t CAN_Type::WORD1 |
Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10
| __IO uint32_t { ... } ::WORD1 |
Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10
| __IO uint32_t { ... } ::WORD1 |
Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10
| __I uint16_t WDOG_Type::WRSR |
Watchdog Reset Status Register, offset: 0x4
| __IO uint16_t WDOG_Type::WSR |
Watchdog Service Register, offset: 0x2
| __IO uint32_t USDHC_Type::WTMK_LVL |
Watermark Level, offset: 0x44
| __IO uint16_t ENC_Type::WTR |
Watchdog Timeout Register, offset: 0x4
1.9.4