RTEMS 6.1-rc1
Macros
SNVS Register Masks
Mapping Information » Iomuxc_pads » Device Peripheral Access Layer » SNVS Peripheral Access Layer

Macros

#define SNVS_LPZMKR_COUNT   (8U)
 
#define SNVS_LPGPR_ALIAS_COUNT   (4U)
 
#define SNVS_LPGPR_COUNT   (8U)
 
#define SNVS_LPZMKR_COUNT   (8U)
 
#define SNVS_LPGPR_ALIAS_COUNT   (4U)
 
#define SNVS_LPATCR_COUNT   (5U)
 
#define SNVS_LPGPR_COUNT   (4U)
 
#define SNVS_LPZMKR_COUNT   (8U)
 
#define SNVS_LPGPR_ALIAS_COUNT   (4U)
 
#define SNVS_LPATCR_COUNT   (5U)
 
#define SNVS_LPGPR_COUNT   (4U)
 

HPLR - SNVS_HP Lock Register

#define SNVS_HPLR_ZMK_WSL_MASK   (0x1U)
 
#define SNVS_HPLR_ZMK_WSL_SHIFT   (0U)
 
#define SNVS_HPLR_ZMK_WSL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
 
#define SNVS_HPLR_ZMK_RSL_MASK   (0x2U)
 
#define SNVS_HPLR_ZMK_RSL_SHIFT   (1U)
 
#define SNVS_HPLR_ZMK_RSL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
 
#define SNVS_HPLR_SRTC_SL_MASK   (0x4U)
 
#define SNVS_HPLR_SRTC_SL_SHIFT   (2U)
 
#define SNVS_HPLR_SRTC_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
 
#define SNVS_HPLR_LPCALB_SL_MASK   (0x8U)
 
#define SNVS_HPLR_LPCALB_SL_SHIFT   (3U)
 
#define SNVS_HPLR_LPCALB_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
 
#define SNVS_HPLR_MC_SL_MASK   (0x10U)
 
#define SNVS_HPLR_MC_SL_SHIFT   (4U)
 
#define SNVS_HPLR_MC_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
 
#define SNVS_HPLR_GPR_SL_MASK   (0x20U)
 
#define SNVS_HPLR_GPR_SL_SHIFT   (5U)
 
#define SNVS_HPLR_GPR_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
 
#define SNVS_HPLR_LPSVCR_SL_MASK   (0x40U)
 
#define SNVS_HPLR_LPSVCR_SL_SHIFT   (6U)
 
#define SNVS_HPLR_LPSVCR_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
 
#define SNVS_HPLR_LPSECR_SL_MASK   (0x100U)
 
#define SNVS_HPLR_LPSECR_SL_SHIFT   (8U)
 
#define SNVS_HPLR_LPSECR_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)
 
#define SNVS_HPLR_MKS_SL_MASK   (0x200U)
 
#define SNVS_HPLR_MKS_SL_SHIFT   (9U)
 
#define SNVS_HPLR_MKS_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
 
#define SNVS_HPLR_HPSVCR_L_MASK   (0x10000U)
 
#define SNVS_HPLR_HPSVCR_L_SHIFT   (16U)
 
#define SNVS_HPLR_HPSVCR_L(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
 
#define SNVS_HPLR_HPSICR_L_MASK   (0x20000U)
 
#define SNVS_HPLR_HPSICR_L_SHIFT   (17U)
 
#define SNVS_HPLR_HPSICR_L(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
 
#define SNVS_HPLR_HAC_L_MASK   (0x40000U)
 
#define SNVS_HPLR_HAC_L_SHIFT   (18U)
 
#define SNVS_HPLR_HAC_L(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
 

HPCOMR - SNVS_HP Command Register

#define SNVS_HPCOMR_SSM_ST_MASK   (0x1U)
 
#define SNVS_HPCOMR_SSM_ST_SHIFT   (0U)
 
#define SNVS_HPCOMR_SSM_ST(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
 
#define SNVS_HPCOMR_SSM_ST_DIS_MASK   (0x2U)
 
#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT   (1U)
 
#define SNVS_HPCOMR_SSM_ST_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
 
#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK   (0x4U)
 
#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT   (2U)
 
#define SNVS_HPCOMR_SSM_SFNS_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
 
#define SNVS_HPCOMR_LP_SWR_MASK   (0x10U)
 
#define SNVS_HPCOMR_LP_SWR_SHIFT   (4U)
 
#define SNVS_HPCOMR_LP_SWR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
 
#define SNVS_HPCOMR_LP_SWR_DIS_MASK   (0x20U)
 
#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT   (5U)
 
#define SNVS_HPCOMR_LP_SWR_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
 
#define SNVS_HPCOMR_SW_SV_MASK   (0x100U)
 
#define SNVS_HPCOMR_SW_SV_SHIFT   (8U)
 
#define SNVS_HPCOMR_SW_SV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
 
#define SNVS_HPCOMR_SW_FSV_MASK   (0x200U)
 
#define SNVS_HPCOMR_SW_FSV_SHIFT   (9U)
 
#define SNVS_HPCOMR_SW_FSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
 
#define SNVS_HPCOMR_SW_LPSV_MASK   (0x400U)
 
#define SNVS_HPCOMR_SW_LPSV_SHIFT   (10U)
 
#define SNVS_HPCOMR_SW_LPSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
 
#define SNVS_HPCOMR_PROG_ZMK_MASK   (0x1000U)
 
#define SNVS_HPCOMR_PROG_ZMK_SHIFT   (12U)
 
#define SNVS_HPCOMR_PROG_ZMK(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
 
#define SNVS_HPCOMR_MKS_EN_MASK   (0x2000U)
 
#define SNVS_HPCOMR_MKS_EN_SHIFT   (13U)
 
#define SNVS_HPCOMR_MKS_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
 
#define SNVS_HPCOMR_HAC_EN_MASK   (0x10000U)
 
#define SNVS_HPCOMR_HAC_EN_SHIFT   (16U)
 
#define SNVS_HPCOMR_HAC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
 
#define SNVS_HPCOMR_HAC_LOAD_MASK   (0x20000U)
 
#define SNVS_HPCOMR_HAC_LOAD_SHIFT   (17U)
 
#define SNVS_HPCOMR_HAC_LOAD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
 
#define SNVS_HPCOMR_HAC_CLEAR_MASK   (0x40000U)
 
#define SNVS_HPCOMR_HAC_CLEAR_SHIFT   (18U)
 
#define SNVS_HPCOMR_HAC_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
 
#define SNVS_HPCOMR_HAC_STOP_MASK   (0x80000U)
 
#define SNVS_HPCOMR_HAC_STOP_SHIFT   (19U)
 
#define SNVS_HPCOMR_HAC_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
 
#define SNVS_HPCOMR_NPSWA_EN_MASK   (0x80000000U)
 
#define SNVS_HPCOMR_NPSWA_EN_SHIFT   (31U)
 
#define SNVS_HPCOMR_NPSWA_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
 

HPCR - SNVS_HP Control Register

#define SNVS_HPCR_RTC_EN_MASK   (0x1U)
 
#define SNVS_HPCR_RTC_EN_SHIFT   (0U)
 
#define SNVS_HPCR_RTC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
 
#define SNVS_HPCR_HPTA_EN_MASK   (0x2U)
 
#define SNVS_HPCR_HPTA_EN_SHIFT   (1U)
 
#define SNVS_HPCR_HPTA_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
 
#define SNVS_HPCR_DIS_PI_MASK   (0x4U)
 
#define SNVS_HPCR_DIS_PI_SHIFT   (2U)
 
#define SNVS_HPCR_DIS_PI(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
 
#define SNVS_HPCR_PI_EN_MASK   (0x8U)
 
#define SNVS_HPCR_PI_EN_SHIFT   (3U)
 
#define SNVS_HPCR_PI_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
 
#define SNVS_HPCR_PI_FREQ_MASK   (0xF0U)
 
#define SNVS_HPCR_PI_FREQ_SHIFT   (4U)
 
#define SNVS_HPCR_PI_FREQ(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
 
#define SNVS_HPCR_HPCALB_EN_MASK   (0x100U)
 
#define SNVS_HPCR_HPCALB_EN_SHIFT   (8U)
 
#define SNVS_HPCR_HPCALB_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
 
#define SNVS_HPCR_HPCALB_VAL_MASK   (0x7C00U)
 
#define SNVS_HPCR_HPCALB_VAL_SHIFT   (10U)
 
#define SNVS_HPCR_HPCALB_VAL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
 
#define SNVS_HPCR_HP_TS_MASK   (0x10000U)
 
#define SNVS_HPCR_HP_TS_SHIFT   (16U)
 
#define SNVS_HPCR_HP_TS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
 
#define SNVS_HPCR_BTN_CONFIG_MASK   (0x7000000U)
 
#define SNVS_HPCR_BTN_CONFIG_SHIFT   (24U)
 
#define SNVS_HPCR_BTN_CONFIG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
 
#define SNVS_HPCR_BTN_MASK_MASK   (0x8000000U)
 
#define SNVS_HPCR_BTN_MASK_SHIFT   (27U)
 
#define SNVS_HPCR_BTN_MASK(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
 

HPSICR - SNVS_HP Security Interrupt Control Register

#define SNVS_HPSICR_SV0_EN_MASK   (0x1U)
 
#define SNVS_HPSICR_SV0_EN_SHIFT   (0U)
 
#define SNVS_HPSICR_SV0_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
 
#define SNVS_HPSICR_SV1_EN_MASK   (0x2U)
 
#define SNVS_HPSICR_SV1_EN_SHIFT   (1U)
 
#define SNVS_HPSICR_SV1_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
 
#define SNVS_HPSICR_SV2_EN_MASK   (0x4U)
 
#define SNVS_HPSICR_SV2_EN_SHIFT   (2U)
 
#define SNVS_HPSICR_SV2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
 
#define SNVS_HPSICR_SV3_EN_MASK   (0x8U)
 
#define SNVS_HPSICR_SV3_EN_SHIFT   (3U)
 
#define SNVS_HPSICR_SV3_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
 
#define SNVS_HPSICR_SV4_EN_MASK   (0x10U)
 
#define SNVS_HPSICR_SV4_EN_SHIFT   (4U)
 
#define SNVS_HPSICR_SV4_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
 
#define SNVS_HPSICR_SV5_EN_MASK   (0x20U)
 
#define SNVS_HPSICR_SV5_EN_SHIFT   (5U)
 
#define SNVS_HPSICR_SV5_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
 
#define SNVS_HPSICR_LPSVI_EN_MASK   (0x80000000U)
 
#define SNVS_HPSICR_LPSVI_EN_SHIFT   (31U)
 
#define SNVS_HPSICR_LPSVI_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
 

HPSVCR - SNVS_HP Security Violation Control Register

#define SNVS_HPSVCR_SV0_CFG_MASK   (0x1U)
 
#define SNVS_HPSVCR_SV0_CFG_SHIFT   (0U)
 
#define SNVS_HPSVCR_SV0_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
 
#define SNVS_HPSVCR_SV1_CFG_MASK   (0x2U)
 
#define SNVS_HPSVCR_SV1_CFG_SHIFT   (1U)
 
#define SNVS_HPSVCR_SV1_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
 
#define SNVS_HPSVCR_SV2_CFG_MASK   (0x4U)
 
#define SNVS_HPSVCR_SV2_CFG_SHIFT   (2U)
 
#define SNVS_HPSVCR_SV2_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
 
#define SNVS_HPSVCR_SV3_CFG_MASK   (0x8U)
 
#define SNVS_HPSVCR_SV3_CFG_SHIFT   (3U)
 
#define SNVS_HPSVCR_SV3_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
 
#define SNVS_HPSVCR_SV4_CFG_MASK   (0x10U)
 
#define SNVS_HPSVCR_SV4_CFG_SHIFT   (4U)
 
#define SNVS_HPSVCR_SV4_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
 
#define SNVS_HPSVCR_SV5_CFG_MASK   (0x60U)
 
#define SNVS_HPSVCR_SV5_CFG_SHIFT   (5U)
 
#define SNVS_HPSVCR_SV5_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
 
#define SNVS_HPSVCR_LPSV_CFG_MASK   (0xC0000000U)
 
#define SNVS_HPSVCR_LPSV_CFG_SHIFT   (30U)
 
#define SNVS_HPSVCR_LPSV_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
 

HPSR - SNVS_HP Status Register

#define SNVS_HPSR_HPTA_MASK   (0x1U)
 
#define SNVS_HPSR_HPTA_SHIFT   (0U)
 
#define SNVS_HPSR_HPTA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
 
#define SNVS_HPSR_PI_MASK   (0x2U)
 
#define SNVS_HPSR_PI_SHIFT   (1U)
 
#define SNVS_HPSR_PI(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
 
#define SNVS_HPSR_LPDIS_MASK   (0x10U)
 
#define SNVS_HPSR_LPDIS_SHIFT   (4U)
 
#define SNVS_HPSR_LPDIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
 
#define SNVS_HPSR_BTN_MASK   (0x40U)
 
#define SNVS_HPSR_BTN_SHIFT   (6U)
 
#define SNVS_HPSR_BTN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
 
#define SNVS_HPSR_BI_MASK   (0x80U)
 
#define SNVS_HPSR_BI_SHIFT   (7U)
 
#define SNVS_HPSR_BI(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
 
#define SNVS_HPSR_SSM_STATE_MASK   (0xF00U)
 
#define SNVS_HPSR_SSM_STATE_SHIFT   (8U)
 
#define SNVS_HPSR_SSM_STATE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
 
#define SNVS_HPSR_SYS_SECURITY_CFG_MASK   (0x7000U)
 
#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT   (12U)
 
#define SNVS_HPSR_SYS_SECURITY_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)
 
#define SNVS_HPSR_SYS_SECURE_BOOT_MASK   (0x8000U)
 
#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT   (15U)
 
#define SNVS_HPSR_SYS_SECURE_BOOT(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)
 
#define SNVS_HPSR_OTPMK_SYNDROME_MASK   (0x1FF0000U)
 
#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT   (16U)
 
#define SNVS_HPSR_OTPMK_SYNDROME(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
 
#define SNVS_HPSR_OTPMK_ZERO_MASK   (0x8000000U)
 
#define SNVS_HPSR_OTPMK_ZERO_SHIFT   (27U)
 
#define SNVS_HPSR_OTPMK_ZERO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
 
#define SNVS_HPSR_ZMK_ZERO_MASK   (0x80000000U)
 
#define SNVS_HPSR_ZMK_ZERO_SHIFT   (31U)
 
#define SNVS_HPSR_ZMK_ZERO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
 

HPSVSR - SNVS_HP Security Violation Status Register

#define SNVS_HPSVSR_SV0_MASK   (0x1U)
 
#define SNVS_HPSVSR_SV0_SHIFT   (0U)
 
#define SNVS_HPSVSR_SV0(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
 
#define SNVS_HPSVSR_SV1_MASK   (0x2U)
 
#define SNVS_HPSVSR_SV1_SHIFT   (1U)
 
#define SNVS_HPSVSR_SV1(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
 
#define SNVS_HPSVSR_SV2_MASK   (0x4U)
 
#define SNVS_HPSVSR_SV2_SHIFT   (2U)
 
#define SNVS_HPSVSR_SV2(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
 
#define SNVS_HPSVSR_SV3_MASK   (0x8U)
 
#define SNVS_HPSVSR_SV3_SHIFT   (3U)
 
#define SNVS_HPSVSR_SV3(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
 
#define SNVS_HPSVSR_SV4_MASK   (0x10U)
 
#define SNVS_HPSVSR_SV4_SHIFT   (4U)
 
#define SNVS_HPSVSR_SV4(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
 
#define SNVS_HPSVSR_SV5_MASK   (0x20U)
 
#define SNVS_HPSVSR_SV5_SHIFT   (5U)
 
#define SNVS_HPSVSR_SV5(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
 
#define SNVS_HPSVSR_SW_SV_MASK   (0x2000U)
 
#define SNVS_HPSVSR_SW_SV_SHIFT   (13U)
 
#define SNVS_HPSVSR_SW_SV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
 
#define SNVS_HPSVSR_SW_FSV_MASK   (0x4000U)
 
#define SNVS_HPSVSR_SW_FSV_SHIFT   (14U)
 
#define SNVS_HPSVSR_SW_FSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
 
#define SNVS_HPSVSR_SW_LPSV_MASK   (0x8000U)
 
#define SNVS_HPSVSR_SW_LPSV_SHIFT   (15U)
 
#define SNVS_HPSVSR_SW_LPSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
 
#define SNVS_HPSVSR_ZMK_SYNDROME_MASK   (0x1FF0000U)
 
#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT   (16U)
 
#define SNVS_HPSVSR_ZMK_SYNDROME(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
 
#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK   (0x8000000U)
 
#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT   (27U)
 
#define SNVS_HPSVSR_ZMK_ECC_FAIL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
 
#define SNVS_HPSVSR_LP_SEC_VIO_MASK   (0x80000000U)
 
#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT   (31U)
 
#define SNVS_HPSVSR_LP_SEC_VIO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
 

HPHACIVR - SNVS_HP High Assurance Counter IV Register

#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT   (0U)
 
#define SNVS_HPHACIVR_HAC_COUNTER_IV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
 

HPHACR - SNVS_HP High Assurance Counter Register

#define SNVS_HPHACR_HAC_COUNTER_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPHACR_HAC_COUNTER_SHIFT   (0U)
 
#define SNVS_HPHACR_HAC_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
 

HPRTCMR - SNVS_HP Real Time Counter MSB Register

#define SNVS_HPRTCMR_RTC_MASK   (0x7FFFU)
 
#define SNVS_HPRTCMR_RTC_SHIFT   (0U)
 
#define SNVS_HPRTCMR_RTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
 

HPRTCLR - SNVS_HP Real Time Counter LSB Register

#define SNVS_HPRTCLR_RTC_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPRTCLR_RTC_SHIFT   (0U)
 
#define SNVS_HPRTCLR_RTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
 

HPTAMR - SNVS_HP Time Alarm MSB Register

#define SNVS_HPTAMR_HPTA_MS_MASK   (0x7FFFU)
 
#define SNVS_HPTAMR_HPTA_MS_SHIFT   (0U)
 
#define SNVS_HPTAMR_HPTA_MS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
 

HPTALR - SNVS_HP Time Alarm LSB Register

#define SNVS_HPTALR_HPTA_LS_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPTALR_HPTA_LS_SHIFT   (0U)
 
#define SNVS_HPTALR_HPTA_LS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
 

LPLR - SNVS_LP Lock Register

#define SNVS_LPLR_ZMK_WHL_MASK   (0x1U)
 
#define SNVS_LPLR_ZMK_WHL_SHIFT   (0U)
 
#define SNVS_LPLR_ZMK_WHL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
 
#define SNVS_LPLR_ZMK_RHL_MASK   (0x2U)
 
#define SNVS_LPLR_ZMK_RHL_SHIFT   (1U)
 
#define SNVS_LPLR_ZMK_RHL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
 
#define SNVS_LPLR_SRTC_HL_MASK   (0x4U)
 
#define SNVS_LPLR_SRTC_HL_SHIFT   (2U)
 
#define SNVS_LPLR_SRTC_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
 
#define SNVS_LPLR_LPCALB_HL_MASK   (0x8U)
 
#define SNVS_LPLR_LPCALB_HL_SHIFT   (3U)
 
#define SNVS_LPLR_LPCALB_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
 
#define SNVS_LPLR_MC_HL_MASK   (0x10U)
 
#define SNVS_LPLR_MC_HL_SHIFT   (4U)
 
#define SNVS_LPLR_MC_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
 
#define SNVS_LPLR_GPR_HL_MASK   (0x20U)
 
#define SNVS_LPLR_GPR_HL_SHIFT   (5U)
 
#define SNVS_LPLR_GPR_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
 
#define SNVS_LPLR_LPSVCR_HL_MASK   (0x40U)
 
#define SNVS_LPLR_LPSVCR_HL_SHIFT   (6U)
 
#define SNVS_LPLR_LPSVCR_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
 
#define SNVS_LPLR_LPSECR_HL_MASK   (0x100U)
 
#define SNVS_LPLR_LPSECR_HL_SHIFT   (8U)
 
#define SNVS_LPLR_LPSECR_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)
 
#define SNVS_LPLR_MKS_HL_MASK   (0x200U)
 
#define SNVS_LPLR_MKS_HL_SHIFT   (9U)
 
#define SNVS_LPLR_MKS_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
 

LPCR - SNVS_LP Control Register

#define SNVS_LPCR_SRTC_ENV_MASK   (0x1U)
 
#define SNVS_LPCR_SRTC_ENV_SHIFT   (0U)
 
#define SNVS_LPCR_SRTC_ENV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
 
#define SNVS_LPCR_LPTA_EN_MASK   (0x2U)
 
#define SNVS_LPCR_LPTA_EN_SHIFT   (1U)
 
#define SNVS_LPCR_LPTA_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
 
#define SNVS_LPCR_MC_ENV_MASK   (0x4U)
 
#define SNVS_LPCR_MC_ENV_SHIFT   (2U)
 
#define SNVS_LPCR_MC_ENV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
 
#define SNVS_LPCR_LPWUI_EN_MASK   (0x8U)
 
#define SNVS_LPCR_LPWUI_EN_SHIFT   (3U)
 
#define SNVS_LPCR_LPWUI_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
 
#define SNVS_LPCR_SRTC_INV_EN_MASK   (0x10U)
 
#define SNVS_LPCR_SRTC_INV_EN_SHIFT   (4U)
 
#define SNVS_LPCR_SRTC_INV_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
 
#define SNVS_LPCR_DP_EN_MASK   (0x20U)
 
#define SNVS_LPCR_DP_EN_SHIFT   (5U)
 
#define SNVS_LPCR_DP_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
 
#define SNVS_LPCR_TOP_MASK   (0x40U)
 
#define SNVS_LPCR_TOP_SHIFT   (6U)
 
#define SNVS_LPCR_TOP(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
 
#define SNVS_LPCR_LVD_EN_MASK   (0x80U)
 
#define SNVS_LPCR_LVD_EN_SHIFT   (7U)
 
#define SNVS_LPCR_LVD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK)
 
#define SNVS_LPCR_LPCALB_EN_MASK   (0x100U)
 
#define SNVS_LPCR_LPCALB_EN_SHIFT   (8U)
 
#define SNVS_LPCR_LPCALB_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
 
#define SNVS_LPCR_LPCALB_VAL_MASK   (0x7C00U)
 
#define SNVS_LPCR_LPCALB_VAL_SHIFT   (10U)
 
#define SNVS_LPCR_LPCALB_VAL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
 
#define SNVS_LPCR_BTN_PRESS_TIME_MASK   (0x30000U)
 
#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT   (16U)
 
#define SNVS_LPCR_BTN_PRESS_TIME(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
 
#define SNVS_LPCR_DEBOUNCE_MASK   (0xC0000U)
 
#define SNVS_LPCR_DEBOUNCE_SHIFT   (18U)
 
#define SNVS_LPCR_DEBOUNCE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
 
#define SNVS_LPCR_ON_TIME_MASK   (0x300000U)
 
#define SNVS_LPCR_ON_TIME_SHIFT   (20U)
 
#define SNVS_LPCR_ON_TIME(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
 
#define SNVS_LPCR_PK_EN_MASK   (0x400000U)
 
#define SNVS_LPCR_PK_EN_SHIFT   (22U)
 
#define SNVS_LPCR_PK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
 
#define SNVS_LPCR_PK_OVERRIDE_MASK   (0x800000U)
 
#define SNVS_LPCR_PK_OVERRIDE_SHIFT   (23U)
 
#define SNVS_LPCR_PK_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
 
#define SNVS_LPCR_GPR_Z_DIS_MASK   (0x1000000U)
 
#define SNVS_LPCR_GPR_Z_DIS_SHIFT   (24U)
 
#define SNVS_LPCR_GPR_Z_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
 

LPMKCR - SNVS_LP Master Key Control Register

#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK   (0x3U)
 
#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT   (0U)
 
#define SNVS_LPMKCR_MASTER_KEY_SEL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
 
#define SNVS_LPMKCR_ZMK_HWP_MASK   (0x4U)
 
#define SNVS_LPMKCR_ZMK_HWP_SHIFT   (2U)
 
#define SNVS_LPMKCR_ZMK_HWP(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
 
#define SNVS_LPMKCR_ZMK_VAL_MASK   (0x8U)
 
#define SNVS_LPMKCR_ZMK_VAL_SHIFT   (3U)
 
#define SNVS_LPMKCR_ZMK_VAL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
 
#define SNVS_LPMKCR_ZMK_ECC_EN_MASK   (0x10U)
 
#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT   (4U)
 
#define SNVS_LPMKCR_ZMK_ECC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
 
#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK   (0xFF80U)
 
#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT   (7U)
 
#define SNVS_LPMKCR_ZMK_ECC_VALUE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
 

LPSVCR - SNVS_LP Security Violation Control Register

#define SNVS_LPSVCR_SV0_EN_MASK   (0x1U)
 
#define SNVS_LPSVCR_SV0_EN_SHIFT   (0U)
 
#define SNVS_LPSVCR_SV0_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
 
#define SNVS_LPSVCR_SV1_EN_MASK   (0x2U)
 
#define SNVS_LPSVCR_SV1_EN_SHIFT   (1U)
 
#define SNVS_LPSVCR_SV1_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
 
#define SNVS_LPSVCR_SV2_EN_MASK   (0x4U)
 
#define SNVS_LPSVCR_SV2_EN_SHIFT   (2U)
 
#define SNVS_LPSVCR_SV2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
 
#define SNVS_LPSVCR_SV3_EN_MASK   (0x8U)
 
#define SNVS_LPSVCR_SV3_EN_SHIFT   (3U)
 
#define SNVS_LPSVCR_SV3_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
 
#define SNVS_LPSVCR_SV4_EN_MASK   (0x10U)
 
#define SNVS_LPSVCR_SV4_EN_SHIFT   (4U)
 
#define SNVS_LPSVCR_SV4_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
 
#define SNVS_LPSVCR_SV5_EN_MASK   (0x20U)
 
#define SNVS_LPSVCR_SV5_EN_SHIFT   (5U)
 
#define SNVS_LPSVCR_SV5_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
 

LPSECR - SNVS_LP Security Events Configuration Register

#define SNVS_LPSECR_SRTCR_EN_MASK   (0x2U)
 
#define SNVS_LPSECR_SRTCR_EN_SHIFT   (1U)
 
#define SNVS_LPSECR_SRTCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_SRTCR_EN_SHIFT)) & SNVS_LPSECR_SRTCR_EN_MASK)
 
#define SNVS_LPSECR_MCR_EN_MASK   (0x4U)
 
#define SNVS_LPSECR_MCR_EN_SHIFT   (2U)
 
#define SNVS_LPSECR_MCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_MCR_EN_SHIFT)) & SNVS_LPSECR_MCR_EN_MASK)
 
#define SNVS_LPSECR_PFD_OBSERV_MASK   (0x4000U)
 
#define SNVS_LPSECR_PFD_OBSERV_SHIFT   (14U)
 
#define SNVS_LPSECR_PFD_OBSERV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_PFD_OBSERV_SHIFT)) & SNVS_LPSECR_PFD_OBSERV_MASK)
 
#define SNVS_LPSECR_POR_OBSERV_MASK   (0x8000U)
 
#define SNVS_LPSECR_POR_OBSERV_SHIFT   (15U)
 
#define SNVS_LPSECR_POR_OBSERV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_POR_OBSERV_SHIFT)) & SNVS_LPSECR_POR_OBSERV_MASK)
 
#define SNVS_LPSECR_LTDC_MASK   (0x70000U)
 
#define SNVS_LPSECR_LTDC_SHIFT   (16U)
 
#define SNVS_LPSECR_LTDC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_LTDC_SHIFT)) & SNVS_LPSECR_LTDC_MASK)
 
#define SNVS_LPSECR_HTDC_MASK   (0x700000U)
 
#define SNVS_LPSECR_HTDC_SHIFT   (20U)
 
#define SNVS_LPSECR_HTDC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_HTDC_SHIFT)) & SNVS_LPSECR_HTDC_MASK)
 
#define SNVS_LPSECR_VRC_MASK   (0x7000000U)
 
#define SNVS_LPSECR_VRC_SHIFT   (24U)
 
#define SNVS_LPSECR_VRC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_VRC_SHIFT)) & SNVS_LPSECR_VRC_MASK)
 
#define SNVS_LPSECR_OSCB_MASK   (0x10000000U)
 
#define SNVS_LPSECR_OSCB_SHIFT   (28U)
 
#define SNVS_LPSECR_OSCB(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_OSCB_SHIFT)) & SNVS_LPSECR_OSCB_MASK)
 

LPSR - SNVS_LP Status Register

#define SNVS_LPSR_LPTA_MASK   (0x1U)
 
#define SNVS_LPSR_LPTA_SHIFT   (0U)
 
#define SNVS_LPSR_LPTA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
 
#define SNVS_LPSR_SRTCR_MASK   (0x2U)
 
#define SNVS_LPSR_SRTCR_SHIFT   (1U)
 
#define SNVS_LPSR_SRTCR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
 
#define SNVS_LPSR_MCR_MASK   (0x4U)
 
#define SNVS_LPSR_MCR_SHIFT   (2U)
 
#define SNVS_LPSR_MCR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
 
#define SNVS_LPSR_LVD_MASK   (0x8U)
 
#define SNVS_LPSR_LVD_SHIFT   (3U)
 
#define SNVS_LPSR_LVD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)
 
#define SNVS_LPSR_ESVD_MASK   (0x10000U)
 
#define SNVS_LPSR_ESVD_SHIFT   (16U)
 
#define SNVS_LPSR_ESVD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
 
#define SNVS_LPSR_EO_MASK   (0x20000U)
 
#define SNVS_LPSR_EO_SHIFT   (17U)
 
#define SNVS_LPSR_EO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
 
#define SNVS_LPSR_SPOF_MASK   (0x40000U)
 
#define SNVS_LPSR_SPOF_SHIFT   (18U)
 
#define SNVS_LPSR_SPOF(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
 
#define SNVS_LPSR_SPON_MASK   (0x80000U)
 
#define SNVS_LPSR_SPON_SHIFT   (19U)
 
#define SNVS_LPSR_SPON(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPON_SHIFT)) & SNVS_LPSR_SPON_MASK)
 
#define SNVS_LPSR_LPNS_MASK   (0x40000000U)
 
#define SNVS_LPSR_LPNS_SHIFT   (30U)
 
#define SNVS_LPSR_LPNS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
 
#define SNVS_LPSR_LPS_MASK   (0x80000000U)
 
#define SNVS_LPSR_LPS_SHIFT   (31U)
 
#define SNVS_LPSR_LPS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
 

LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register

#define SNVS_LPSRTCMR_SRTC_MASK   (0x7FFFU)
 
#define SNVS_LPSRTCMR_SRTC_SHIFT   (0U)
 
#define SNVS_LPSRTCMR_SRTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
 

LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register

#define SNVS_LPSRTCLR_SRTC_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPSRTCLR_SRTC_SHIFT   (0U)
 
#define SNVS_LPSRTCLR_SRTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
 

LPTAR - SNVS_LP Time Alarm Register

#define SNVS_LPTAR_LPTA_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPTAR_LPTA_SHIFT   (0U)
 
#define SNVS_LPTAR_LPTA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
 

LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register

#define SNVS_LPSMCMR_MON_COUNTER_MASK   (0xFFFFU)
 
#define SNVS_LPSMCMR_MON_COUNTER_SHIFT   (0U)
 
#define SNVS_LPSMCMR_MON_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
 
#define SNVS_LPSMCMR_MC_ERA_BITS_MASK   (0xFFFF0000U)
 
#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT   (16U)
 
#define SNVS_LPSMCMR_MC_ERA_BITS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
 

LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register

#define SNVS_LPSMCLR_MON_COUNTER_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPSMCLR_MON_COUNTER_SHIFT   (0U)
 
#define SNVS_LPSMCLR_MON_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
 

LPLVDR - SNVS_LP Digital Low-Voltage Detector Register

#define SNVS_LPLVDR_LVD_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPLVDR_LVD_SHIFT   (0U)
 
#define SNVS_LPLVDR_LVD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK)
 

LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias)

#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT   (0U)
 
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
 

LPZMKR - SNVS_LP Zeroizable Master Key Register

#define SNVS_LPZMKR_ZMK_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPZMKR_ZMK_SHIFT   (0U)
 
#define SNVS_LPZMKR_ZMK(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
 

LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3

#define SNVS_LPGPR_ALIAS_GPR_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPGPR_ALIAS_GPR_SHIFT   (0U)
 
#define SNVS_LPGPR_ALIAS_GPR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
 

LPGPR - SNVS_LP General Purpose Registers 0 .. 7

#define SNVS_LPGPR_GPR_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPGPR_GPR_SHIFT   (0U)
 
#define SNVS_LPGPR_GPR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
 

HPVIDR1 - SNVS_HP Version ID Register 1

#define SNVS_HPVIDR1_MINOR_REV_MASK   (0xFFU)
 
#define SNVS_HPVIDR1_MINOR_REV_SHIFT   (0U)
 
#define SNVS_HPVIDR1_MINOR_REV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
 
#define SNVS_HPVIDR1_MAJOR_REV_MASK   (0xFF00U)
 
#define SNVS_HPVIDR1_MAJOR_REV_SHIFT   (8U)
 
#define SNVS_HPVIDR1_MAJOR_REV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
 
#define SNVS_HPVIDR1_IP_ID_MASK   (0xFFFF0000U)
 
#define SNVS_HPVIDR1_IP_ID_SHIFT   (16U)
 
#define SNVS_HPVIDR1_IP_ID(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
 

HPVIDR2 - SNVS_HP Version ID Register 2

#define SNVS_HPVIDR2_CONFIG_OPT_MASK   (0xFFU)
 
#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT   (0U)
 
#define SNVS_HPVIDR2_CONFIG_OPT(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
 
#define SNVS_HPVIDR2_ECO_REV_MASK   (0xFF00U)
 
#define SNVS_HPVIDR2_ECO_REV_SHIFT   (8U)
 
#define SNVS_HPVIDR2_ECO_REV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
 
#define SNVS_HPVIDR2_INTG_OPT_MASK   (0xFF0000U)
 
#define SNVS_HPVIDR2_INTG_OPT_SHIFT   (16U)
 
#define SNVS_HPVIDR2_INTG_OPT(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
 
#define SNVS_HPVIDR2_IP_ERA_MASK   (0xFF000000U)
 
#define SNVS_HPVIDR2_IP_ERA_SHIFT   (24U)
 
#define SNVS_HPVIDR2_IP_ERA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
 

HPLR - SNVS_HP Lock Register

#define SNVS_HPLR_ZMK_WSL_MASK   (0x1U)
 
#define SNVS_HPLR_ZMK_WSL_SHIFT   (0U)
 
#define SNVS_HPLR_ZMK_WSL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
 
#define SNVS_HPLR_ZMK_RSL_MASK   (0x2U)
 
#define SNVS_HPLR_ZMK_RSL_SHIFT   (1U)
 
#define SNVS_HPLR_ZMK_RSL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
 
#define SNVS_HPLR_SRTC_SL_MASK   (0x4U)
 
#define SNVS_HPLR_SRTC_SL_SHIFT   (2U)
 
#define SNVS_HPLR_SRTC_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
 
#define SNVS_HPLR_LPCALB_SL_MASK   (0x8U)
 
#define SNVS_HPLR_LPCALB_SL_SHIFT   (3U)
 
#define SNVS_HPLR_LPCALB_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
 
#define SNVS_HPLR_MC_SL_MASK   (0x10U)
 
#define SNVS_HPLR_MC_SL_SHIFT   (4U)
 
#define SNVS_HPLR_MC_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
 
#define SNVS_HPLR_GPR_SL_MASK   (0x20U)
 
#define SNVS_HPLR_GPR_SL_SHIFT   (5U)
 
#define SNVS_HPLR_GPR_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
 
#define SNVS_HPLR_LPSVCR_SL_MASK   (0x40U)
 
#define SNVS_HPLR_LPSVCR_SL_SHIFT   (6U)
 
#define SNVS_HPLR_LPSVCR_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
 
#define SNVS_HPLR_LPTGFCR_SL_MASK   (0x80U)
 
#define SNVS_HPLR_LPTGFCR_SL_SHIFT   (7U)
 
#define SNVS_HPLR_LPTGFCR_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK)
 
#define SNVS_HPLR_LPSECR_SL_MASK   (0x100U)
 
#define SNVS_HPLR_LPSECR_SL_SHIFT   (8U)
 
#define SNVS_HPLR_LPSECR_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)
 
#define SNVS_HPLR_MKS_SL_MASK   (0x200U)
 
#define SNVS_HPLR_MKS_SL_SHIFT   (9U)
 
#define SNVS_HPLR_MKS_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
 
#define SNVS_HPLR_HPSVCR_L_MASK   (0x10000U)
 
#define SNVS_HPLR_HPSVCR_L_SHIFT   (16U)
 
#define SNVS_HPLR_HPSVCR_L(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
 
#define SNVS_HPLR_HPSICR_L_MASK   (0x20000U)
 
#define SNVS_HPLR_HPSICR_L_SHIFT   (17U)
 
#define SNVS_HPLR_HPSICR_L(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
 
#define SNVS_HPLR_HAC_L_MASK   (0x40000U)
 
#define SNVS_HPLR_HAC_L_SHIFT   (18U)
 
#define SNVS_HPLR_HAC_L(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
 
#define SNVS_HPLR_AT1_SL_MASK   (0x1000000U)
 
#define SNVS_HPLR_AT1_SL_SHIFT   (24U)
 
#define SNVS_HPLR_AT1_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT1_SL_SHIFT)) & SNVS_HPLR_AT1_SL_MASK)
 
#define SNVS_HPLR_AT2_SL_MASK   (0x2000000U)
 
#define SNVS_HPLR_AT2_SL_SHIFT   (25U)
 
#define SNVS_HPLR_AT2_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT2_SL_SHIFT)) & SNVS_HPLR_AT2_SL_MASK)
 
#define SNVS_HPLR_AT3_SL_MASK   (0x4000000U)
 
#define SNVS_HPLR_AT3_SL_SHIFT   (26U)
 
#define SNVS_HPLR_AT3_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT3_SL_SHIFT)) & SNVS_HPLR_AT3_SL_MASK)
 
#define SNVS_HPLR_AT4_SL_MASK   (0x8000000U)
 
#define SNVS_HPLR_AT4_SL_SHIFT   (27U)
 
#define SNVS_HPLR_AT4_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT4_SL_SHIFT)) & SNVS_HPLR_AT4_SL_MASK)
 
#define SNVS_HPLR_AT5_SL_MASK   (0x10000000U)
 
#define SNVS_HPLR_AT5_SL_SHIFT   (28U)
 
#define SNVS_HPLR_AT5_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT5_SL_SHIFT)) & SNVS_HPLR_AT5_SL_MASK)
 

HPCOMR - SNVS_HP Command Register

#define SNVS_HPCOMR_SSM_ST_MASK   (0x1U)
 
#define SNVS_HPCOMR_SSM_ST_SHIFT   (0U)
 
#define SNVS_HPCOMR_SSM_ST(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
 
#define SNVS_HPCOMR_SSM_ST_DIS_MASK   (0x2U)
 
#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT   (1U)
 
#define SNVS_HPCOMR_SSM_ST_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
 
#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK   (0x4U)
 
#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT   (2U)
 
#define SNVS_HPCOMR_SSM_SFNS_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
 
#define SNVS_HPCOMR_LP_SWR_MASK   (0x10U)
 
#define SNVS_HPCOMR_LP_SWR_SHIFT   (4U)
 
#define SNVS_HPCOMR_LP_SWR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
 
#define SNVS_HPCOMR_LP_SWR_DIS_MASK   (0x20U)
 
#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT   (5U)
 
#define SNVS_HPCOMR_LP_SWR_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
 
#define SNVS_HPCOMR_SW_SV_MASK   (0x100U)
 
#define SNVS_HPCOMR_SW_SV_SHIFT   (8U)
 
#define SNVS_HPCOMR_SW_SV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
 
#define SNVS_HPCOMR_SW_FSV_MASK   (0x200U)
 
#define SNVS_HPCOMR_SW_FSV_SHIFT   (9U)
 
#define SNVS_HPCOMR_SW_FSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
 
#define SNVS_HPCOMR_SW_LPSV_MASK   (0x400U)
 
#define SNVS_HPCOMR_SW_LPSV_SHIFT   (10U)
 
#define SNVS_HPCOMR_SW_LPSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
 
#define SNVS_HPCOMR_PROG_ZMK_MASK   (0x1000U)
 
#define SNVS_HPCOMR_PROG_ZMK_SHIFT   (12U)
 
#define SNVS_HPCOMR_PROG_ZMK(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
 
#define SNVS_HPCOMR_MKS_EN_MASK   (0x2000U)
 
#define SNVS_HPCOMR_MKS_EN_SHIFT   (13U)
 
#define SNVS_HPCOMR_MKS_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
 
#define SNVS_HPCOMR_HAC_EN_MASK   (0x10000U)
 
#define SNVS_HPCOMR_HAC_EN_SHIFT   (16U)
 
#define SNVS_HPCOMR_HAC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
 
#define SNVS_HPCOMR_HAC_LOAD_MASK   (0x20000U)
 
#define SNVS_HPCOMR_HAC_LOAD_SHIFT   (17U)
 
#define SNVS_HPCOMR_HAC_LOAD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
 
#define SNVS_HPCOMR_HAC_CLEAR_MASK   (0x40000U)
 
#define SNVS_HPCOMR_HAC_CLEAR_SHIFT   (18U)
 
#define SNVS_HPCOMR_HAC_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
 
#define SNVS_HPCOMR_HAC_STOP_MASK   (0x80000U)
 
#define SNVS_HPCOMR_HAC_STOP_SHIFT   (19U)
 
#define SNVS_HPCOMR_HAC_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
 
#define SNVS_HPCOMR_NPSWA_EN_MASK   (0x80000000U)
 
#define SNVS_HPCOMR_NPSWA_EN_SHIFT   (31U)
 
#define SNVS_HPCOMR_NPSWA_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
 

HPCR - SNVS_HP Control Register

#define SNVS_HPCR_RTC_EN_MASK   (0x1U)
 
#define SNVS_HPCR_RTC_EN_SHIFT   (0U)
 
#define SNVS_HPCR_RTC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
 
#define SNVS_HPCR_HPTA_EN_MASK   (0x2U)
 
#define SNVS_HPCR_HPTA_EN_SHIFT   (1U)
 
#define SNVS_HPCR_HPTA_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
 
#define SNVS_HPCR_DIS_PI_MASK   (0x4U)
 
#define SNVS_HPCR_DIS_PI_SHIFT   (2U)
 
#define SNVS_HPCR_DIS_PI(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
 
#define SNVS_HPCR_PI_EN_MASK   (0x8U)
 
#define SNVS_HPCR_PI_EN_SHIFT   (3U)
 
#define SNVS_HPCR_PI_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
 
#define SNVS_HPCR_PI_FREQ_MASK   (0xF0U)
 
#define SNVS_HPCR_PI_FREQ_SHIFT   (4U)
 
#define SNVS_HPCR_PI_FREQ(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
 
#define SNVS_HPCR_HPCALB_EN_MASK   (0x100U)
 
#define SNVS_HPCR_HPCALB_EN_SHIFT   (8U)
 
#define SNVS_HPCR_HPCALB_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
 
#define SNVS_HPCR_HPCALB_VAL_MASK   (0x7C00U)
 
#define SNVS_HPCR_HPCALB_VAL_SHIFT   (10U)
 
#define SNVS_HPCR_HPCALB_VAL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
 
#define SNVS_HPCR_HP_TS_MASK   (0x10000U)
 
#define SNVS_HPCR_HP_TS_SHIFT   (16U)
 
#define SNVS_HPCR_HP_TS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
 
#define SNVS_HPCR_BTN_CONFIG_MASK   (0x7000000U)
 
#define SNVS_HPCR_BTN_CONFIG_SHIFT   (24U)
 
#define SNVS_HPCR_BTN_CONFIG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
 
#define SNVS_HPCR_BTN_MASK_MASK   (0x8000000U)
 
#define SNVS_HPCR_BTN_MASK_SHIFT   (27U)
 
#define SNVS_HPCR_BTN_MASK(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
 

HPSICR - SNVS_HP Security Interrupt Control Register

#define SNVS_HPSICR_CAAM_EN_MASK   (0x1U)
 
#define SNVS_HPSICR_CAAM_EN_SHIFT   (0U)
 
#define SNVS_HPSICR_CAAM_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_CAAM_EN_SHIFT)) & SNVS_HPSICR_CAAM_EN_MASK)
 
#define SNVS_HPSICR_JTAGC_EN_MASK   (0x2U)
 
#define SNVS_HPSICR_JTAGC_EN_SHIFT   (1U)
 
#define SNVS_HPSICR_JTAGC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_JTAGC_EN_SHIFT)) & SNVS_HPSICR_JTAGC_EN_MASK)
 
#define SNVS_HPSICR_WDOG2_EN_MASK   (0x4U)
 
#define SNVS_HPSICR_WDOG2_EN_SHIFT   (2U)
 
#define SNVS_HPSICR_WDOG2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_WDOG2_EN_SHIFT)) & SNVS_HPSICR_WDOG2_EN_MASK)
 
#define SNVS_HPSICR_SRC_EN_MASK   (0x10U)
 
#define SNVS_HPSICR_SRC_EN_SHIFT   (4U)
 
#define SNVS_HPSICR_SRC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SRC_EN_SHIFT)) & SNVS_HPSICR_SRC_EN_MASK)
 
#define SNVS_HPSICR_OCOTP_EN_MASK   (0x20U)
 
#define SNVS_HPSICR_OCOTP_EN_SHIFT   (5U)
 
#define SNVS_HPSICR_OCOTP_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_OCOTP_EN_SHIFT)) & SNVS_HPSICR_OCOTP_EN_MASK)
 
#define SNVS_HPSICR_LPSVI_EN_MASK   (0x80000000U)
 
#define SNVS_HPSICR_LPSVI_EN_SHIFT   (31U)
 
#define SNVS_HPSICR_LPSVI_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
 

HPSVCR - SNVS_HP Security Violation Control Register

#define SNVS_HPSVCR_CAAM_CFG_MASK   (0x1U)
 
#define SNVS_HPSVCR_CAAM_CFG_SHIFT   (0U)
 
#define SNVS_HPSVCR_CAAM_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_CAAM_CFG_SHIFT)) & SNVS_HPSVCR_CAAM_CFG_MASK)
 
#define SNVS_HPSVCR_JTAGC_CFG_MASK   (0x2U)
 
#define SNVS_HPSVCR_JTAGC_CFG_SHIFT   (1U)
 
#define SNVS_HPSVCR_JTAGC_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_JTAGC_CFG_SHIFT)) & SNVS_HPSVCR_JTAGC_CFG_MASK)
 
#define SNVS_HPSVCR_WDOG2_CFG_MASK   (0x4U)
 
#define SNVS_HPSVCR_WDOG2_CFG_SHIFT   (2U)
 
#define SNVS_HPSVCR_WDOG2_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
 
#define SNVS_HPSVCR_SRC_CFG_MASK   (0x10U)
 
#define SNVS_HPSVCR_SRC_CFG_SHIFT   (4U)
 
#define SNVS_HPSVCR_SRC_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SRC_CFG_SHIFT)) & SNVS_HPSVCR_SRC_CFG_MASK)
 
#define SNVS_HPSVCR_OCOTP_CFG_MASK   (0x60U)
 
#define SNVS_HPSVCR_OCOTP_CFG_SHIFT   (5U)
 
#define SNVS_HPSVCR_OCOTP_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_OCOTP_CFG_SHIFT)) & SNVS_HPSVCR_OCOTP_CFG_MASK)
 
#define SNVS_HPSVCR_LPSV_CFG_MASK   (0xC0000000U)
 
#define SNVS_HPSVCR_LPSV_CFG_SHIFT   (30U)
 
#define SNVS_HPSVCR_LPSV_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
 

HPSR - SNVS_HP Status Register

#define SNVS_HPSR_HPTA_MASK   (0x1U)
 
#define SNVS_HPSR_HPTA_SHIFT   (0U)
 
#define SNVS_HPSR_HPTA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
 
#define SNVS_HPSR_PI_MASK   (0x2U)
 
#define SNVS_HPSR_PI_SHIFT   (1U)
 
#define SNVS_HPSR_PI(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
 
#define SNVS_HPSR_LPDIS_MASK   (0x10U)
 
#define SNVS_HPSR_LPDIS_SHIFT   (4U)
 
#define SNVS_HPSR_LPDIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
 
#define SNVS_HPSR_BTN_MASK   (0x40U)
 
#define SNVS_HPSR_BTN_SHIFT   (6U)
 
#define SNVS_HPSR_BTN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
 
#define SNVS_HPSR_BI_MASK   (0x80U)
 
#define SNVS_HPSR_BI_SHIFT   (7U)
 
#define SNVS_HPSR_BI(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
 
#define SNVS_HPSR_SSM_STATE_MASK   (0xF00U)
 
#define SNVS_HPSR_SSM_STATE_SHIFT   (8U)
 
#define SNVS_HPSR_SSM_STATE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
 
#define SNVS_HPSR_SYS_SECURITY_CFG_MASK   (0x7000U)
 
#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT   (12U)
 
#define SNVS_HPSR_SYS_SECURITY_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)
 
#define SNVS_HPSR_SYS_SECURE_BOOT_MASK   (0x8000U)
 
#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT   (15U)
 
#define SNVS_HPSR_SYS_SECURE_BOOT(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)
 
#define SNVS_HPSR_OTPMK_ZERO_MASK   (0x8000000U)
 
#define SNVS_HPSR_OTPMK_ZERO_SHIFT   (27U)
 
#define SNVS_HPSR_OTPMK_ZERO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
 
#define SNVS_HPSR_ZMK_ZERO_MASK   (0x80000000U)
 
#define SNVS_HPSR_ZMK_ZERO_SHIFT   (31U)
 
#define SNVS_HPSR_ZMK_ZERO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
 

HPSVSR - SNVS_HP Security Violation Status Register

#define SNVS_HPSVSR_CAAM_MASK   (0x1U)
 
#define SNVS_HPSVSR_CAAM_SHIFT   (0U)
 
#define SNVS_HPSVSR_CAAM(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_CAAM_SHIFT)) & SNVS_HPSVSR_CAAM_MASK)
 
#define SNVS_HPSVSR_JTAGC_MASK   (0x2U)
 
#define SNVS_HPSVSR_JTAGC_SHIFT   (1U)
 
#define SNVS_HPSVSR_JTAGC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_JTAGC_SHIFT)) & SNVS_HPSVSR_JTAGC_MASK)
 
#define SNVS_HPSVSR_WDOG2_MASK   (0x4U)
 
#define SNVS_HPSVSR_WDOG2_SHIFT   (2U)
 
#define SNVS_HPSVSR_WDOG2(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_WDOG2_SHIFT)) & SNVS_HPSVSR_WDOG2_MASK)
 
#define SNVS_HPSVSR_SRC_MASK   (0x10U)
 
#define SNVS_HPSVSR_SRC_SHIFT   (4U)
 
#define SNVS_HPSVSR_SRC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SRC_SHIFT)) & SNVS_HPSVSR_SRC_MASK)
 
#define SNVS_HPSVSR_OCOTP_MASK   (0x20U)
 
#define SNVS_HPSVSR_OCOTP_SHIFT   (5U)
 
#define SNVS_HPSVSR_OCOTP(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_OCOTP_SHIFT)) & SNVS_HPSVSR_OCOTP_MASK)
 
#define SNVS_HPSVSR_SW_SV_MASK   (0x2000U)
 
#define SNVS_HPSVSR_SW_SV_SHIFT   (13U)
 
#define SNVS_HPSVSR_SW_SV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
 
#define SNVS_HPSVSR_SW_FSV_MASK   (0x4000U)
 
#define SNVS_HPSVSR_SW_FSV_SHIFT   (14U)
 
#define SNVS_HPSVSR_SW_FSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
 
#define SNVS_HPSVSR_SW_LPSV_MASK   (0x8000U)
 
#define SNVS_HPSVSR_SW_LPSV_SHIFT   (15U)
 
#define SNVS_HPSVSR_SW_LPSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
 
#define SNVS_HPSVSR_ZMK_SYNDROME_MASK   (0x1FF0000U)
 
#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT   (16U)
 
#define SNVS_HPSVSR_ZMK_SYNDROME(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
 
#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK   (0x8000000U)
 
#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT   (27U)
 
#define SNVS_HPSVSR_ZMK_ECC_FAIL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
 
#define SNVS_HPSVSR_LP_SEC_VIO_MASK   (0x80000000U)
 
#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT   (31U)
 
#define SNVS_HPSVSR_LP_SEC_VIO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
 

HPHACIVR - SNVS_HP High Assurance Counter IV Register

#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT   (0U)
 
#define SNVS_HPHACIVR_HAC_COUNTER_IV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
 

HPHACR - SNVS_HP High Assurance Counter Register

#define SNVS_HPHACR_HAC_COUNTER_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPHACR_HAC_COUNTER_SHIFT   (0U)
 
#define SNVS_HPHACR_HAC_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
 

HPRTCMR - SNVS_HP Real Time Counter MSB Register

#define SNVS_HPRTCMR_RTC_MASK   (0x7FFFU)
 
#define SNVS_HPRTCMR_RTC_SHIFT   (0U)
 
#define SNVS_HPRTCMR_RTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
 

HPRTCLR - SNVS_HP Real Time Counter LSB Register

#define SNVS_HPRTCLR_RTC_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPRTCLR_RTC_SHIFT   (0U)
 
#define SNVS_HPRTCLR_RTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
 

HPTAMR - SNVS_HP Time Alarm MSB Register

#define SNVS_HPTAMR_HPTA_MS_MASK   (0x7FFFU)
 
#define SNVS_HPTAMR_HPTA_MS_SHIFT   (0U)
 
#define SNVS_HPTAMR_HPTA_MS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
 

HPTALR - SNVS_HP Time Alarm LSB Register

#define SNVS_HPTALR_HPTA_LS_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPTALR_HPTA_LS_SHIFT   (0U)
 
#define SNVS_HPTALR_HPTA_LS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
 

LPLR - SNVS_LP Lock Register

#define SNVS_LPLR_ZMK_WHL_MASK   (0x1U)
 
#define SNVS_LPLR_ZMK_WHL_SHIFT   (0U)
 
#define SNVS_LPLR_ZMK_WHL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
 
#define SNVS_LPLR_ZMK_RHL_MASK   (0x2U)
 
#define SNVS_LPLR_ZMK_RHL_SHIFT   (1U)
 
#define SNVS_LPLR_ZMK_RHL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
 
#define SNVS_LPLR_SRTC_HL_MASK   (0x4U)
 
#define SNVS_LPLR_SRTC_HL_SHIFT   (2U)
 
#define SNVS_LPLR_SRTC_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
 
#define SNVS_LPLR_LPCALB_HL_MASK   (0x8U)
 
#define SNVS_LPLR_LPCALB_HL_SHIFT   (3U)
 
#define SNVS_LPLR_LPCALB_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
 
#define SNVS_LPLR_MC_HL_MASK   (0x10U)
 
#define SNVS_LPLR_MC_HL_SHIFT   (4U)
 
#define SNVS_LPLR_MC_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
 
#define SNVS_LPLR_GPR_HL_MASK   (0x20U)
 
#define SNVS_LPLR_GPR_HL_SHIFT   (5U)
 
#define SNVS_LPLR_GPR_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
 
#define SNVS_LPLR_LPSVCR_HL_MASK   (0x40U)
 
#define SNVS_LPLR_LPSVCR_HL_SHIFT   (6U)
 
#define SNVS_LPLR_LPSVCR_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
 
#define SNVS_LPLR_LPTGFCR_HL_MASK   (0x80U)
 
#define SNVS_LPLR_LPTGFCR_HL_SHIFT   (7U)
 
#define SNVS_LPLR_LPTGFCR_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK)
 
#define SNVS_LPLR_LPSECR_HL_MASK   (0x100U)
 
#define SNVS_LPLR_LPSECR_HL_SHIFT   (8U)
 
#define SNVS_LPLR_LPSECR_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)
 
#define SNVS_LPLR_MKS_HL_MASK   (0x200U)
 
#define SNVS_LPLR_MKS_HL_SHIFT   (9U)
 
#define SNVS_LPLR_MKS_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
 
#define SNVS_LPLR_AT1_HL_MASK   (0x1000000U)
 
#define SNVS_LPLR_AT1_HL_SHIFT   (24U)
 
#define SNVS_LPLR_AT1_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT1_HL_SHIFT)) & SNVS_LPLR_AT1_HL_MASK)
 
#define SNVS_LPLR_AT2_HL_MASK   (0x2000000U)
 
#define SNVS_LPLR_AT2_HL_SHIFT   (25U)
 
#define SNVS_LPLR_AT2_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT2_HL_SHIFT)) & SNVS_LPLR_AT2_HL_MASK)
 
#define SNVS_LPLR_AT3_HL_MASK   (0x4000000U)
 
#define SNVS_LPLR_AT3_HL_SHIFT   (26U)
 
#define SNVS_LPLR_AT3_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT3_HL_SHIFT)) & SNVS_LPLR_AT3_HL_MASK)
 
#define SNVS_LPLR_AT4_HL_MASK   (0x8000000U)
 
#define SNVS_LPLR_AT4_HL_SHIFT   (27U)
 
#define SNVS_LPLR_AT4_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT4_HL_SHIFT)) & SNVS_LPLR_AT4_HL_MASK)
 
#define SNVS_LPLR_AT5_HL_MASK   (0x10000000U)
 
#define SNVS_LPLR_AT5_HL_SHIFT   (28U)
 
#define SNVS_LPLR_AT5_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT5_HL_SHIFT)) & SNVS_LPLR_AT5_HL_MASK)
 

LPCR - SNVS_LP Control Register

#define SNVS_LPCR_SRTC_ENV_MASK   (0x1U)
 
#define SNVS_LPCR_SRTC_ENV_SHIFT   (0U)
 
#define SNVS_LPCR_SRTC_ENV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
 
#define SNVS_LPCR_LPTA_EN_MASK   (0x2U)
 
#define SNVS_LPCR_LPTA_EN_SHIFT   (1U)
 
#define SNVS_LPCR_LPTA_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
 
#define SNVS_LPCR_MC_ENV_MASK   (0x4U)
 
#define SNVS_LPCR_MC_ENV_SHIFT   (2U)
 
#define SNVS_LPCR_MC_ENV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
 
#define SNVS_LPCR_LPWUI_EN_MASK   (0x8U)
 
#define SNVS_LPCR_LPWUI_EN_SHIFT   (3U)
 
#define SNVS_LPCR_LPWUI_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
 
#define SNVS_LPCR_SRTC_INV_EN_MASK   (0x10U)
 
#define SNVS_LPCR_SRTC_INV_EN_SHIFT   (4U)
 
#define SNVS_LPCR_SRTC_INV_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
 
#define SNVS_LPCR_DP_EN_MASK   (0x20U)
 
#define SNVS_LPCR_DP_EN_SHIFT   (5U)
 
#define SNVS_LPCR_DP_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
 
#define SNVS_LPCR_TOP_MASK   (0x40U)
 
#define SNVS_LPCR_TOP_SHIFT   (6U)
 
#define SNVS_LPCR_TOP(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
 
#define SNVS_LPCR_LVD_EN_MASK   (0x80U)
 
#define SNVS_LPCR_LVD_EN_SHIFT   (7U)
 
#define SNVS_LPCR_LVD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK)
 
#define SNVS_LPCR_LPCALB_EN_MASK   (0x100U)
 
#define SNVS_LPCR_LPCALB_EN_SHIFT   (8U)
 
#define SNVS_LPCR_LPCALB_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
 
#define SNVS_LPCR_LPCALB_VAL_MASK   (0x7C00U)
 
#define SNVS_LPCR_LPCALB_VAL_SHIFT   (10U)
 
#define SNVS_LPCR_LPCALB_VAL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
 
#define SNVS_LPCR_BTN_PRESS_TIME_MASK   (0x30000U)
 
#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT   (16U)
 
#define SNVS_LPCR_BTN_PRESS_TIME(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
 
#define SNVS_LPCR_DEBOUNCE_MASK   (0xC0000U)
 
#define SNVS_LPCR_DEBOUNCE_SHIFT   (18U)
 
#define SNVS_LPCR_DEBOUNCE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
 
#define SNVS_LPCR_ON_TIME_MASK   (0x300000U)
 
#define SNVS_LPCR_ON_TIME_SHIFT   (20U)
 
#define SNVS_LPCR_ON_TIME(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
 
#define SNVS_LPCR_PK_EN_MASK   (0x400000U)
 
#define SNVS_LPCR_PK_EN_SHIFT   (22U)
 
#define SNVS_LPCR_PK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
 
#define SNVS_LPCR_PK_OVERRIDE_MASK   (0x800000U)
 
#define SNVS_LPCR_PK_OVERRIDE_SHIFT   (23U)
 
#define SNVS_LPCR_PK_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
 
#define SNVS_LPCR_GPR_Z_DIS_MASK   (0x1000000U)
 
#define SNVS_LPCR_GPR_Z_DIS_SHIFT   (24U)
 
#define SNVS_LPCR_GPR_Z_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
 

LPMKCR - SNVS_LP Master Key Control Register

#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK   (0x3U)
 
#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT   (0U)
 
#define SNVS_LPMKCR_MASTER_KEY_SEL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
 
#define SNVS_LPMKCR_ZMK_HWP_MASK   (0x4U)
 
#define SNVS_LPMKCR_ZMK_HWP_SHIFT   (2U)
 
#define SNVS_LPMKCR_ZMK_HWP(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
 
#define SNVS_LPMKCR_ZMK_VAL_MASK   (0x8U)
 
#define SNVS_LPMKCR_ZMK_VAL_SHIFT   (3U)
 
#define SNVS_LPMKCR_ZMK_VAL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
 
#define SNVS_LPMKCR_ZMK_ECC_EN_MASK   (0x10U)
 
#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT   (4U)
 
#define SNVS_LPMKCR_ZMK_ECC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
 
#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK   (0xFF80U)
 
#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT   (7U)
 
#define SNVS_LPMKCR_ZMK_ECC_VALUE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
 

LPSVCR - SNVS_LP Security Violation Control Register

#define SNVS_LPSVCR_CAAM_EN_MASK   (0x1U)
 
#define SNVS_LPSVCR_CAAM_EN_SHIFT   (0U)
 
#define SNVS_LPSVCR_CAAM_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_CAAM_EN_SHIFT)) & SNVS_LPSVCR_CAAM_EN_MASK)
 
#define SNVS_LPSVCR_JTAGC_EN_MASK   (0x2U)
 
#define SNVS_LPSVCR_JTAGC_EN_SHIFT   (1U)
 
#define SNVS_LPSVCR_JTAGC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_JTAGC_EN_SHIFT)) & SNVS_LPSVCR_JTAGC_EN_MASK)
 
#define SNVS_LPSVCR_WDOG2_EN_MASK   (0x4U)
 
#define SNVS_LPSVCR_WDOG2_EN_SHIFT   (2U)
 
#define SNVS_LPSVCR_WDOG2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_WDOG2_EN_SHIFT)) & SNVS_LPSVCR_WDOG2_EN_MASK)
 
#define SNVS_LPSVCR_SRC_EN_MASK   (0x10U)
 
#define SNVS_LPSVCR_SRC_EN_SHIFT   (4U)
 
#define SNVS_LPSVCR_SRC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SRC_EN_SHIFT)) & SNVS_LPSVCR_SRC_EN_MASK)
 
#define SNVS_LPSVCR_OCOTP_EN_MASK   (0x20U)
 
#define SNVS_LPSVCR_OCOTP_EN_SHIFT   (5U)
 
#define SNVS_LPSVCR_OCOTP_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_OCOTP_EN_SHIFT)) & SNVS_LPSVCR_OCOTP_EN_MASK)
 

LPTGFCR - SNVS_LP Tamper Glitch Filters Configuration Register

#define SNVS_LPTGFCR_WMTGF_MASK   (0x1FU)
 
#define SNVS_LPTGFCR_WMTGF_SHIFT   (0U)
 
#define SNVS_LPTGFCR_WMTGF(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_SHIFT)) & SNVS_LPTGFCR_WMTGF_MASK)
 
#define SNVS_LPTGFCR_WMTGF_EN_MASK   (0x80U)
 
#define SNVS_LPTGFCR_WMTGF_EN_SHIFT   (7U)
 
#define SNVS_LPTGFCR_WMTGF_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK)
 
#define SNVS_LPTGFCR_ETGF1_MASK   (0x7F0000U)
 
#define SNVS_LPTGFCR_ETGF1_SHIFT   (16U)
 
#define SNVS_LPTGFCR_ETGF1(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_SHIFT)) & SNVS_LPTGFCR_ETGF1_MASK)
 
#define SNVS_LPTGFCR_ETGF1_EN_MASK   (0x800000U)
 
#define SNVS_LPTGFCR_ETGF1_EN_SHIFT   (23U)
 
#define SNVS_LPTGFCR_ETGF1_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK)
 
#define SNVS_LPTGFCR_ETGF2_MASK   (0x7F000000U)
 
#define SNVS_LPTGFCR_ETGF2_SHIFT   (24U)
 
#define SNVS_LPTGFCR_ETGF2(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_SHIFT)) & SNVS_LPTGFCR_ETGF2_MASK)
 
#define SNVS_LPTGFCR_ETGF2_EN_MASK   (0x80000000U)
 
#define SNVS_LPTGFCR_ETGF2_EN_SHIFT   (31U)
 
#define SNVS_LPTGFCR_ETGF2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_EN_SHIFT)) & SNVS_LPTGFCR_ETGF2_EN_MASK)
 

LPTDCR - SNVS_LP Tamper Detect Configuration Register

#define SNVS_LPTDCR_SRTCR_EN_MASK   (0x2U)
 
#define SNVS_LPTDCR_SRTCR_EN_SHIFT   (1U)
 
#define SNVS_LPTDCR_SRTCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
 
#define SNVS_LPTDCR_MCR_EN_MASK   (0x4U)
 
#define SNVS_LPTDCR_MCR_EN_SHIFT   (2U)
 
#define SNVS_LPTDCR_MCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
 
#define SNVS_LPTDCR_CT_EN_MASK   (0x10U)
 
#define SNVS_LPTDCR_CT_EN_SHIFT   (4U)
 
#define SNVS_LPTDCR_CT_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK)
 
#define SNVS_LPTDCR_TT_EN_MASK   (0x20U)
 
#define SNVS_LPTDCR_TT_EN_SHIFT   (5U)
 
#define SNVS_LPTDCR_TT_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK)
 
#define SNVS_LPTDCR_VT_EN_MASK   (0x40U)
 
#define SNVS_LPTDCR_VT_EN_SHIFT   (6U)
 
#define SNVS_LPTDCR_VT_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK)
 
#define SNVS_LPTDCR_WMT1_EN_MASK   (0x80U)
 
#define SNVS_LPTDCR_WMT1_EN_SHIFT   (7U)
 
#define SNVS_LPTDCR_WMT1_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK)
 
#define SNVS_LPTDCR_WMT2_EN_MASK   (0x100U)
 
#define SNVS_LPTDCR_WMT2_EN_SHIFT   (8U)
 
#define SNVS_LPTDCR_WMT2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK)
 
#define SNVS_LPTDCR_ET1_EN_MASK   (0x200U)
 
#define SNVS_LPTDCR_ET1_EN_SHIFT   (9U)
 
#define SNVS_LPTDCR_ET1_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
 
#define SNVS_LPTDCR_ET2_EN_MASK   (0x400U)
 
#define SNVS_LPTDCR_ET2_EN_SHIFT   (10U)
 
#define SNVS_LPTDCR_ET2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK)
 
#define SNVS_LPTDCR_ET1P_MASK   (0x800U)
 
#define SNVS_LPTDCR_ET1P_SHIFT   (11U)
 
#define SNVS_LPTDCR_ET1P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
 
#define SNVS_LPTDCR_ET2P_MASK   (0x1000U)
 
#define SNVS_LPTDCR_ET2P_SHIFT   (12U)
 
#define SNVS_LPTDCR_ET2P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK)
 
#define SNVS_LPTDCR_PFD_OBSERV_MASK   (0x4000U)
 
#define SNVS_LPTDCR_PFD_OBSERV_SHIFT   (14U)
 
#define SNVS_LPTDCR_PFD_OBSERV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
 
#define SNVS_LPTDCR_POR_OBSERV_MASK   (0x8000U)
 
#define SNVS_LPTDCR_POR_OBSERV_SHIFT   (15U)
 
#define SNVS_LPTDCR_POR_OBSERV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
 
#define SNVS_LPTDCR_LTDC_MASK   (0x70000U)
 
#define SNVS_LPTDCR_LTDC_SHIFT   (16U)
 
#define SNVS_LPTDCR_LTDC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_LTDC_SHIFT)) & SNVS_LPTDCR_LTDC_MASK)
 
#define SNVS_LPTDCR_HTDC_MASK   (0x700000U)
 
#define SNVS_LPTDCR_HTDC_SHIFT   (20U)
 
#define SNVS_LPTDCR_HTDC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_HTDC_SHIFT)) & SNVS_LPTDCR_HTDC_MASK)
 
#define SNVS_LPTDCR_VRC_MASK   (0x7000000U)
 
#define SNVS_LPTDCR_VRC_SHIFT   (24U)
 
#define SNVS_LPTDCR_VRC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VRC_SHIFT)) & SNVS_LPTDCR_VRC_MASK)
 
#define SNVS_LPTDCR_OSCB_MASK   (0x10000000U)
 
#define SNVS_LPTDCR_OSCB_SHIFT   (28U)
 
#define SNVS_LPTDCR_OSCB(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
 

LPSR - SNVS_LP Status Register

#define SNVS_LPSR_LPTA_MASK   (0x1U)
 
#define SNVS_LPSR_LPTA_SHIFT   (0U)
 
#define SNVS_LPSR_LPTA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
 
#define SNVS_LPSR_SRTCR_MASK   (0x2U)
 
#define SNVS_LPSR_SRTCR_SHIFT   (1U)
 
#define SNVS_LPSR_SRTCR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
 
#define SNVS_LPSR_MCR_MASK   (0x4U)
 
#define SNVS_LPSR_MCR_SHIFT   (2U)
 
#define SNVS_LPSR_MCR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
 
#define SNVS_LPSR_LVD_MASK   (0x8U)
 
#define SNVS_LPSR_LVD_SHIFT   (3U)
 
#define SNVS_LPSR_LVD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)
 
#define SNVS_LPSR_CTD_MASK   (0x10U)
 
#define SNVS_LPSR_CTD_SHIFT   (4U)
 
#define SNVS_LPSR_CTD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK)
 
#define SNVS_LPSR_TTD_MASK   (0x20U)
 
#define SNVS_LPSR_TTD_SHIFT   (5U)
 
#define SNVS_LPSR_TTD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK)
 
#define SNVS_LPSR_VTD_MASK   (0x40U)
 
#define SNVS_LPSR_VTD_SHIFT   (6U)
 
#define SNVS_LPSR_VTD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
 
#define SNVS_LPSR_WMT1D_MASK   (0x80U)
 
#define SNVS_LPSR_WMT1D_SHIFT   (7U)
 
#define SNVS_LPSR_WMT1D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK)
 
#define SNVS_LPSR_WMT2D_MASK   (0x100U)
 
#define SNVS_LPSR_WMT2D_SHIFT   (8U)
 
#define SNVS_LPSR_WMT2D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK)
 
#define SNVS_LPSR_ET1D_MASK   (0x200U)
 
#define SNVS_LPSR_ET1D_SHIFT   (9U)
 
#define SNVS_LPSR_ET1D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
 
#define SNVS_LPSR_ET2D_MASK   (0x400U)
 
#define SNVS_LPSR_ET2D_SHIFT   (10U)
 
#define SNVS_LPSR_ET2D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
 
#define SNVS_LPSR_ESVD_MASK   (0x10000U)
 
#define SNVS_LPSR_ESVD_SHIFT   (16U)
 
#define SNVS_LPSR_ESVD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
 
#define SNVS_LPSR_EO_MASK   (0x20000U)
 
#define SNVS_LPSR_EO_SHIFT   (17U)
 
#define SNVS_LPSR_EO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
 
#define SNVS_LPSR_SPOF_MASK   (0x40000U)
 
#define SNVS_LPSR_SPOF_SHIFT   (18U)
 
#define SNVS_LPSR_SPOF(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
 
#define SNVS_LPSR_LPNS_MASK   (0x40000000U)
 
#define SNVS_LPSR_LPNS_SHIFT   (30U)
 
#define SNVS_LPSR_LPNS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
 
#define SNVS_LPSR_LPS_MASK   (0x80000000U)
 
#define SNVS_LPSR_LPS_SHIFT   (31U)
 
#define SNVS_LPSR_LPS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
 

LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register

#define SNVS_LPSRTCMR_SRTC_MASK   (0x7FFFU)
 
#define SNVS_LPSRTCMR_SRTC_SHIFT   (0U)
 
#define SNVS_LPSRTCMR_SRTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
 

LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register

#define SNVS_LPSRTCLR_SRTC_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPSRTCLR_SRTC_SHIFT   (0U)
 
#define SNVS_LPSRTCLR_SRTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
 

LPTAR - SNVS_LP Time Alarm Register

#define SNVS_LPTAR_LPTA_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPTAR_LPTA_SHIFT   (0U)
 
#define SNVS_LPTAR_LPTA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
 

LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register

#define SNVS_LPSMCMR_MON_COUNTER_MASK   (0xFFFFU)
 
#define SNVS_LPSMCMR_MON_COUNTER_SHIFT   (0U)
 
#define SNVS_LPSMCMR_MON_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
 
#define SNVS_LPSMCMR_MC_ERA_BITS_MASK   (0xFFFF0000U)
 
#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT   (16U)
 
#define SNVS_LPSMCMR_MC_ERA_BITS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
 

LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register

#define SNVS_LPSMCLR_MON_COUNTER_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPSMCLR_MON_COUNTER_SHIFT   (0U)
 
#define SNVS_LPSMCLR_MON_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
 

LPLVDR - SNVS_LP Digital Low-Voltage Detector Register

#define SNVS_LPLVDR_LVD_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPLVDR_LVD_SHIFT   (0U)
 
#define SNVS_LPLVDR_LVD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK)
 

LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias)

#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT   (0U)
 
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
 

LPZMKR - SNVS_LP Zeroizable Master Key Register

#define SNVS_LPZMKR_ZMK_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPZMKR_ZMK_SHIFT   (0U)
 
#define SNVS_LPZMKR_ZMK(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
 

LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3

#define SNVS_LPGPR_ALIAS_GPR_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPGPR_ALIAS_GPR_SHIFT   (0U)
 
#define SNVS_LPGPR_ALIAS_GPR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
 

LPTDC2R - SNVS_LP Tamper Detectors Config 2 Register

#define SNVS_LPTDC2R_ET3_EN_MASK   (0x1U)
 
#define SNVS_LPTDC2R_ET3_EN_SHIFT   (0U)
 
#define SNVS_LPTDC2R_ET3_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK)
 
#define SNVS_LPTDC2R_ET4_EN_MASK   (0x2U)
 
#define SNVS_LPTDC2R_ET4_EN_SHIFT   (1U)
 
#define SNVS_LPTDC2R_ET4_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK)
 
#define SNVS_LPTDC2R_ET5_EN_MASK   (0x4U)
 
#define SNVS_LPTDC2R_ET5_EN_SHIFT   (2U)
 
#define SNVS_LPTDC2R_ET5_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK)
 
#define SNVS_LPTDC2R_ET6_EN_MASK   (0x8U)
 
#define SNVS_LPTDC2R_ET6_EN_SHIFT   (3U)
 
#define SNVS_LPTDC2R_ET6_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK)
 
#define SNVS_LPTDC2R_ET7_EN_MASK   (0x10U)
 
#define SNVS_LPTDC2R_ET7_EN_SHIFT   (4U)
 
#define SNVS_LPTDC2R_ET7_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK)
 
#define SNVS_LPTDC2R_ET8_EN_MASK   (0x20U)
 
#define SNVS_LPTDC2R_ET8_EN_SHIFT   (5U)
 
#define SNVS_LPTDC2R_ET8_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK)
 
#define SNVS_LPTDC2R_ET9_EN_MASK   (0x40U)
 
#define SNVS_LPTDC2R_ET9_EN_SHIFT   (6U)
 
#define SNVS_LPTDC2R_ET9_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK)
 
#define SNVS_LPTDC2R_ET10_EN_MASK   (0x80U)
 
#define SNVS_LPTDC2R_ET10_EN_SHIFT   (7U)
 
#define SNVS_LPTDC2R_ET10_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK)
 
#define SNVS_LPTDC2R_ET3P_MASK   (0x10000U)
 
#define SNVS_LPTDC2R_ET3P_SHIFT   (16U)
 
#define SNVS_LPTDC2R_ET3P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK)
 
#define SNVS_LPTDC2R_ET4P_MASK   (0x20000U)
 
#define SNVS_LPTDC2R_ET4P_SHIFT   (17U)
 
#define SNVS_LPTDC2R_ET4P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK)
 
#define SNVS_LPTDC2R_ET5P_MASK   (0x40000U)
 
#define SNVS_LPTDC2R_ET5P_SHIFT   (18U)
 
#define SNVS_LPTDC2R_ET5P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK)
 
#define SNVS_LPTDC2R_ET6P_MASK   (0x80000U)
 
#define SNVS_LPTDC2R_ET6P_SHIFT   (19U)
 
#define SNVS_LPTDC2R_ET6P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK)
 
#define SNVS_LPTDC2R_ET7P_MASK   (0x100000U)
 
#define SNVS_LPTDC2R_ET7P_SHIFT   (20U)
 
#define SNVS_LPTDC2R_ET7P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK)
 
#define SNVS_LPTDC2R_ET8P_MASK   (0x200000U)
 
#define SNVS_LPTDC2R_ET8P_SHIFT   (21U)
 
#define SNVS_LPTDC2R_ET8P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK)
 
#define SNVS_LPTDC2R_ET9P_MASK   (0x400000U)
 
#define SNVS_LPTDC2R_ET9P_SHIFT   (22U)
 
#define SNVS_LPTDC2R_ET9P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK)
 
#define SNVS_LPTDC2R_ET10P_MASK   (0x800000U)
 
#define SNVS_LPTDC2R_ET10P_SHIFT   (23U)
 
#define SNVS_LPTDC2R_ET10P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10P_SHIFT)) & SNVS_LPTDC2R_ET10P_MASK)
 

LPTDSR - SNVS_LP Tamper Detectors Status Register

#define SNVS_LPTDSR_ET3D_MASK   (0x1U)
 
#define SNVS_LPTDSR_ET3D_SHIFT   (0U)
 
#define SNVS_LPTDSR_ET3D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK)
 
#define SNVS_LPTDSR_ET4D_MASK   (0x2U)
 
#define SNVS_LPTDSR_ET4D_SHIFT   (1U)
 
#define SNVS_LPTDSR_ET4D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK)
 
#define SNVS_LPTDSR_ET5D_MASK   (0x4U)
 
#define SNVS_LPTDSR_ET5D_SHIFT   (2U)
 
#define SNVS_LPTDSR_ET5D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK)
 
#define SNVS_LPTDSR_ET6D_MASK   (0x8U)
 
#define SNVS_LPTDSR_ET6D_SHIFT   (3U)
 
#define SNVS_LPTDSR_ET6D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK)
 
#define SNVS_LPTDSR_ET7D_MASK   (0x10U)
 
#define SNVS_LPTDSR_ET7D_SHIFT   (4U)
 
#define SNVS_LPTDSR_ET7D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK)
 
#define SNVS_LPTDSR_ET8D_MASK   (0x20U)
 
#define SNVS_LPTDSR_ET8D_SHIFT   (5U)
 
#define SNVS_LPTDSR_ET8D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK)
 
#define SNVS_LPTDSR_ET9D_MASK   (0x40U)
 
#define SNVS_LPTDSR_ET9D_SHIFT   (6U)
 
#define SNVS_LPTDSR_ET9D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK)
 
#define SNVS_LPTDSR_ET10D_MASK   (0x80U)
 
#define SNVS_LPTDSR_ET10D_SHIFT   (7U)
 
#define SNVS_LPTDSR_ET10D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET10D_SHIFT)) & SNVS_LPTDSR_ET10D_MASK)
 

LPTGF1CR - SNVS_LP Tamper Glitch Filter 1 Configuration Register

#define SNVS_LPTGF1CR_ETGF3_MASK   (0x7FU)
 
#define SNVS_LPTGF1CR_ETGF3_SHIFT   (0U)
 
#define SNVS_LPTGF1CR_ETGF3(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_SHIFT)) & SNVS_LPTGF1CR_ETGF3_MASK)
 
#define SNVS_LPTGF1CR_ETGF3_EN_MASK   (0x80U)
 
#define SNVS_LPTGF1CR_ETGF3_EN_SHIFT   (7U)
 
#define SNVS_LPTGF1CR_ETGF3_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK)
 
#define SNVS_LPTGF1CR_ETGF4_MASK   (0x7F00U)
 
#define SNVS_LPTGF1CR_ETGF4_SHIFT   (8U)
 
#define SNVS_LPTGF1CR_ETGF4(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_SHIFT)) & SNVS_LPTGF1CR_ETGF4_MASK)
 
#define SNVS_LPTGF1CR_ETGF4_EN_MASK   (0x8000U)
 
#define SNVS_LPTGF1CR_ETGF4_EN_SHIFT   (15U)
 
#define SNVS_LPTGF1CR_ETGF4_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK)
 
#define SNVS_LPTGF1CR_ETGF5_MASK   (0x7F0000U)
 
#define SNVS_LPTGF1CR_ETGF5_SHIFT   (16U)
 
#define SNVS_LPTGF1CR_ETGF5(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_SHIFT)) & SNVS_LPTGF1CR_ETGF5_MASK)
 
#define SNVS_LPTGF1CR_ETGF5_EN_MASK   (0x800000U)
 
#define SNVS_LPTGF1CR_ETGF5_EN_SHIFT   (23U)
 
#define SNVS_LPTGF1CR_ETGF5_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK)
 
#define SNVS_LPTGF1CR_ETGF6_MASK   (0x7F000000U)
 
#define SNVS_LPTGF1CR_ETGF6_SHIFT   (24U)
 
#define SNVS_LPTGF1CR_ETGF6(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_SHIFT)) & SNVS_LPTGF1CR_ETGF6_MASK)
 
#define SNVS_LPTGF1CR_ETGF6_EN_MASK   (0x80000000U)
 
#define SNVS_LPTGF1CR_ETGF6_EN_SHIFT   (31U)
 
#define SNVS_LPTGF1CR_ETGF6_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF6_EN_MASK)
 

LPTGF2CR - SNVS_LP Tamper Glitch Filter 2 Configuration Register

#define SNVS_LPTGF2CR_ETGF7_MASK   (0x7FU)
 
#define SNVS_LPTGF2CR_ETGF7_SHIFT   (0U)
 
#define SNVS_LPTGF2CR_ETGF7(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_SHIFT)) & SNVS_LPTGF2CR_ETGF7_MASK)
 
#define SNVS_LPTGF2CR_ETGF7_EN_MASK   (0x80U)
 
#define SNVS_LPTGF2CR_ETGF7_EN_SHIFT   (7U)
 
#define SNVS_LPTGF2CR_ETGF7_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK)
 
#define SNVS_LPTGF2CR_ETGF8_MASK   (0x7F00U)
 
#define SNVS_LPTGF2CR_ETGF8_SHIFT   (8U)
 
#define SNVS_LPTGF2CR_ETGF8(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_SHIFT)) & SNVS_LPTGF2CR_ETGF8_MASK)
 
#define SNVS_LPTGF2CR_ETGF8_EN_MASK   (0x8000U)
 
#define SNVS_LPTGF2CR_ETGF8_EN_SHIFT   (15U)
 
#define SNVS_LPTGF2CR_ETGF8_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK)
 
#define SNVS_LPTGF2CR_ETGF9_MASK   (0x7F0000U)
 
#define SNVS_LPTGF2CR_ETGF9_SHIFT   (16U)
 
#define SNVS_LPTGF2CR_ETGF9(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_SHIFT)) & SNVS_LPTGF2CR_ETGF9_MASK)
 
#define SNVS_LPTGF2CR_ETGF9_EN_MASK   (0x800000U)
 
#define SNVS_LPTGF2CR_ETGF9_EN_SHIFT   (23U)
 
#define SNVS_LPTGF2CR_ETGF9_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK)
 
#define SNVS_LPTGF2CR_ETGF10_MASK   (0x7F000000U)
 
#define SNVS_LPTGF2CR_ETGF10_SHIFT   (24U)
 
#define SNVS_LPTGF2CR_ETGF10(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_SHIFT)) & SNVS_LPTGF2CR_ETGF10_MASK)
 
#define SNVS_LPTGF2CR_ETGF10_EN_MASK   (0x80000000U)
 
#define SNVS_LPTGF2CR_ETGF10_EN_SHIFT   (31U)
 
#define SNVS_LPTGF2CR_ETGF10_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF10_EN_MASK)
 

LPATCR - SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register

#define SNVS_LPATCR_Seed_MASK   (0xFFFFU)
 
#define SNVS_LPATCR_Seed_SHIFT   (0U)
 
#define SNVS_LPATCR_Seed(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Seed_SHIFT)) & SNVS_LPATCR_Seed_MASK)
 
#define SNVS_LPATCR_Polynomial_MASK   (0xFFFF0000U)
 
#define SNVS_LPATCR_Polynomial_SHIFT   (16U)
 
#define SNVS_LPATCR_Polynomial(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Polynomial_SHIFT)) & SNVS_LPATCR_Polynomial_MASK)
 

LPATCTLR - SNVS_LP Active Tamper Control Register

#define SNVS_LPATCTLR_AT1_EN_MASK   (0x1U)
 
#define SNVS_LPATCTLR_AT1_EN_SHIFT   (0U)
 
#define SNVS_LPATCTLR_AT1_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_EN_SHIFT)) & SNVS_LPATCTLR_AT1_EN_MASK)
 
#define SNVS_LPATCTLR_AT2_EN_MASK   (0x2U)
 
#define SNVS_LPATCTLR_AT2_EN_SHIFT   (1U)
 
#define SNVS_LPATCTLR_AT2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_EN_SHIFT)) & SNVS_LPATCTLR_AT2_EN_MASK)
 
#define SNVS_LPATCTLR_AT3_EN_MASK   (0x4U)
 
#define SNVS_LPATCTLR_AT3_EN_SHIFT   (2U)
 
#define SNVS_LPATCTLR_AT3_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_EN_SHIFT)) & SNVS_LPATCTLR_AT3_EN_MASK)
 
#define SNVS_LPATCTLR_AT4_EN_MASK   (0x8U)
 
#define SNVS_LPATCTLR_AT4_EN_SHIFT   (3U)
 
#define SNVS_LPATCTLR_AT4_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_EN_SHIFT)) & SNVS_LPATCTLR_AT4_EN_MASK)
 
#define SNVS_LPATCTLR_AT5_EN_MASK   (0x10U)
 
#define SNVS_LPATCTLR_AT5_EN_SHIFT   (4U)
 
#define SNVS_LPATCTLR_AT5_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_EN_SHIFT)) & SNVS_LPATCTLR_AT5_EN_MASK)
 
#define SNVS_LPATCTLR_AT1_PAD_EN_MASK   (0x10000U)
 
#define SNVS_LPATCTLR_AT1_PAD_EN_SHIFT   (16U)
 
#define SNVS_LPATCTLR_AT1_PAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT1_PAD_EN_MASK)
 
#define SNVS_LPATCTLR_AT2_PAD_EN_MASK   (0x20000U)
 
#define SNVS_LPATCTLR_AT2_PAD_EN_SHIFT   (17U)
 
#define SNVS_LPATCTLR_AT2_PAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT2_PAD_EN_MASK)
 
#define SNVS_LPATCTLR_AT3_PAD_EN_MASK   (0x40000U)
 
#define SNVS_LPATCTLR_AT3_PAD_EN_SHIFT   (18U)
 
#define SNVS_LPATCTLR_AT3_PAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT3_PAD_EN_MASK)
 
#define SNVS_LPATCTLR_AT4_PAD_EN_MASK   (0x80000U)
 
#define SNVS_LPATCTLR_AT4_PAD_EN_SHIFT   (19U)
 
#define SNVS_LPATCTLR_AT4_PAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT4_PAD_EN_MASK)
 
#define SNVS_LPATCTLR_AT5_PAD_EN_MASK   (0x100000U)
 
#define SNVS_LPATCTLR_AT5_PAD_EN_SHIFT   (20U)
 
#define SNVS_LPATCTLR_AT5_PAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT5_PAD_EN_MASK)
 

LPATCLKR - SNVS_LP Active Tamper Clock Control Register

#define SNVS_LPATCLKR_AT1_CLK_CTL_MASK   (0x3U)
 
#define SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT   (0U)
 
#define SNVS_LPATCLKR_AT1_CLK_CTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT1_CLK_CTL_MASK)
 
#define SNVS_LPATCLKR_AT2_CLK_CTL_MASK   (0x30U)
 
#define SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT   (4U)
 
#define SNVS_LPATCLKR_AT2_CLK_CTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT2_CLK_CTL_MASK)
 
#define SNVS_LPATCLKR_AT3_CLK_CTL_MASK   (0x300U)
 
#define SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT   (8U)
 
#define SNVS_LPATCLKR_AT3_CLK_CTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT3_CLK_CTL_MASK)
 
#define SNVS_LPATCLKR_AT4_CLK_CTL_MASK   (0x3000U)
 
#define SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT   (12U)
 
#define SNVS_LPATCLKR_AT4_CLK_CTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT4_CLK_CTL_MASK)
 
#define SNVS_LPATCLKR_AT5_CLK_CTL_MASK   (0x30000U)
 
#define SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT   (16U)
 
#define SNVS_LPATCLKR_AT5_CLK_CTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT5_CLK_CTL_MASK)
 

LPATRC1R - SNVS_LP Active Tamper Routing Control 1 Register

#define SNVS_LPATRC1R_ET1RCTL_MASK   (0x7U)
 
#define SNVS_LPATRC1R_ET1RCTL_SHIFT   (0U)
 
#define SNVS_LPATRC1R_ET1RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET1RCTL_SHIFT)) & SNVS_LPATRC1R_ET1RCTL_MASK)
 
#define SNVS_LPATRC1R_ET2RCTL_MASK   (0x70U)
 
#define SNVS_LPATRC1R_ET2RCTL_SHIFT   (4U)
 
#define SNVS_LPATRC1R_ET2RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET2RCTL_SHIFT)) & SNVS_LPATRC1R_ET2RCTL_MASK)
 
#define SNVS_LPATRC1R_ET3RCTL_MASK   (0x700U)
 
#define SNVS_LPATRC1R_ET3RCTL_SHIFT   (8U)
 
#define SNVS_LPATRC1R_ET3RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET3RCTL_SHIFT)) & SNVS_LPATRC1R_ET3RCTL_MASK)
 
#define SNVS_LPATRC1R_ET4RCTL_MASK   (0x7000U)
 
#define SNVS_LPATRC1R_ET4RCTL_SHIFT   (12U)
 
#define SNVS_LPATRC1R_ET4RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET4RCTL_SHIFT)) & SNVS_LPATRC1R_ET4RCTL_MASK)
 
#define SNVS_LPATRC1R_ET5RCTL_MASK   (0x70000U)
 
#define SNVS_LPATRC1R_ET5RCTL_SHIFT   (16U)
 
#define SNVS_LPATRC1R_ET5RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET5RCTL_SHIFT)) & SNVS_LPATRC1R_ET5RCTL_MASK)
 
#define SNVS_LPATRC1R_ET6RCTL_MASK   (0x700000U)
 
#define SNVS_LPATRC1R_ET6RCTL_SHIFT   (20U)
 
#define SNVS_LPATRC1R_ET6RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET6RCTL_SHIFT)) & SNVS_LPATRC1R_ET6RCTL_MASK)
 
#define SNVS_LPATRC1R_ET7RCTL_MASK   (0x7000000U)
 
#define SNVS_LPATRC1R_ET7RCTL_SHIFT   (24U)
 
#define SNVS_LPATRC1R_ET7RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET7RCTL_SHIFT)) & SNVS_LPATRC1R_ET7RCTL_MASK)
 
#define SNVS_LPATRC1R_ET8RCTL_MASK   (0x70000000U)
 
#define SNVS_LPATRC1R_ET8RCTL_SHIFT   (28U)
 
#define SNVS_LPATRC1R_ET8RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET8RCTL_SHIFT)) & SNVS_LPATRC1R_ET8RCTL_MASK)
 

LPATRC2R - SNVS_LP Active Tamper Routing Control 2 Register

#define SNVS_LPATRC2R_ET9RCTL_MASK   (0x7U)
 
#define SNVS_LPATRC2R_ET9RCTL_SHIFT   (0U)
 
#define SNVS_LPATRC2R_ET9RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET9RCTL_SHIFT)) & SNVS_LPATRC2R_ET9RCTL_MASK)
 
#define SNVS_LPATRC2R_ET10RCTL_MASK   (0x70U)
 
#define SNVS_LPATRC2R_ET10RCTL_SHIFT   (4U)
 
#define SNVS_LPATRC2R_ET10RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET10RCTL_SHIFT)) & SNVS_LPATRC2R_ET10RCTL_MASK)
 

LPGPR - SNVS_LP General Purpose Registers 0 .. 3

#define SNVS_LPGPR_GPR_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPGPR_GPR_SHIFT   (0U)
 
#define SNVS_LPGPR_GPR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
 

HPVIDR1 - SNVS_HP Version ID Register 1

#define SNVS_HPVIDR1_MINOR_REV_MASK   (0xFFU)
 
#define SNVS_HPVIDR1_MINOR_REV_SHIFT   (0U)
 
#define SNVS_HPVIDR1_MINOR_REV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
 
#define SNVS_HPVIDR1_MAJOR_REV_MASK   (0xFF00U)
 
#define SNVS_HPVIDR1_MAJOR_REV_SHIFT   (8U)
 
#define SNVS_HPVIDR1_MAJOR_REV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
 
#define SNVS_HPVIDR1_IP_ID_MASK   (0xFFFF0000U)
 
#define SNVS_HPVIDR1_IP_ID_SHIFT   (16U)
 
#define SNVS_HPVIDR1_IP_ID(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
 

HPVIDR2 - SNVS_HP Version ID Register 2

#define SNVS_HPVIDR2_ECO_REV_MASK   (0xFF00U)
 
#define SNVS_HPVIDR2_ECO_REV_SHIFT   (8U)
 
#define SNVS_HPVIDR2_ECO_REV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
 
#define SNVS_HPVIDR2_IP_ERA_MASK   (0xFF000000U)
 
#define SNVS_HPVIDR2_IP_ERA_SHIFT   (24U)
 
#define SNVS_HPVIDR2_IP_ERA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
 

HPLR - SNVS_HP Lock Register

#define SNVS_HPLR_ZMK_WSL_MASK   (0x1U)
 
#define SNVS_HPLR_ZMK_WSL_SHIFT   (0U)
 
#define SNVS_HPLR_ZMK_WSL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
 
#define SNVS_HPLR_ZMK_RSL_MASK   (0x2U)
 
#define SNVS_HPLR_ZMK_RSL_SHIFT   (1U)
 
#define SNVS_HPLR_ZMK_RSL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
 
#define SNVS_HPLR_SRTC_SL_MASK   (0x4U)
 
#define SNVS_HPLR_SRTC_SL_SHIFT   (2U)
 
#define SNVS_HPLR_SRTC_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
 
#define SNVS_HPLR_LPCALB_SL_MASK   (0x8U)
 
#define SNVS_HPLR_LPCALB_SL_SHIFT   (3U)
 
#define SNVS_HPLR_LPCALB_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
 
#define SNVS_HPLR_MC_SL_MASK   (0x10U)
 
#define SNVS_HPLR_MC_SL_SHIFT   (4U)
 
#define SNVS_HPLR_MC_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
 
#define SNVS_HPLR_GPR_SL_MASK   (0x20U)
 
#define SNVS_HPLR_GPR_SL_SHIFT   (5U)
 
#define SNVS_HPLR_GPR_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
 
#define SNVS_HPLR_LPSVCR_SL_MASK   (0x40U)
 
#define SNVS_HPLR_LPSVCR_SL_SHIFT   (6U)
 
#define SNVS_HPLR_LPSVCR_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
 
#define SNVS_HPLR_LPTGFCR_SL_MASK   (0x80U)
 
#define SNVS_HPLR_LPTGFCR_SL_SHIFT   (7U)
 
#define SNVS_HPLR_LPTGFCR_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK)
 
#define SNVS_HPLR_LPSECR_SL_MASK   (0x100U)
 
#define SNVS_HPLR_LPSECR_SL_SHIFT   (8U)
 
#define SNVS_HPLR_LPSECR_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)
 
#define SNVS_HPLR_MKS_SL_MASK   (0x200U)
 
#define SNVS_HPLR_MKS_SL_SHIFT   (9U)
 
#define SNVS_HPLR_MKS_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
 
#define SNVS_HPLR_HPSVCR_L_MASK   (0x10000U)
 
#define SNVS_HPLR_HPSVCR_L_SHIFT   (16U)
 
#define SNVS_HPLR_HPSVCR_L(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
 
#define SNVS_HPLR_HPSICR_L_MASK   (0x20000U)
 
#define SNVS_HPLR_HPSICR_L_SHIFT   (17U)
 
#define SNVS_HPLR_HPSICR_L(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
 
#define SNVS_HPLR_HAC_L_MASK   (0x40000U)
 
#define SNVS_HPLR_HAC_L_SHIFT   (18U)
 
#define SNVS_HPLR_HAC_L(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
 
#define SNVS_HPLR_AT1_SL_MASK   (0x1000000U)
 
#define SNVS_HPLR_AT1_SL_SHIFT   (24U)
 
#define SNVS_HPLR_AT1_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT1_SL_SHIFT)) & SNVS_HPLR_AT1_SL_MASK)
 
#define SNVS_HPLR_AT2_SL_MASK   (0x2000000U)
 
#define SNVS_HPLR_AT2_SL_SHIFT   (25U)
 
#define SNVS_HPLR_AT2_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT2_SL_SHIFT)) & SNVS_HPLR_AT2_SL_MASK)
 
#define SNVS_HPLR_AT3_SL_MASK   (0x4000000U)
 
#define SNVS_HPLR_AT3_SL_SHIFT   (26U)
 
#define SNVS_HPLR_AT3_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT3_SL_SHIFT)) & SNVS_HPLR_AT3_SL_MASK)
 
#define SNVS_HPLR_AT4_SL_MASK   (0x8000000U)
 
#define SNVS_HPLR_AT4_SL_SHIFT   (27U)
 
#define SNVS_HPLR_AT4_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT4_SL_SHIFT)) & SNVS_HPLR_AT4_SL_MASK)
 
#define SNVS_HPLR_AT5_SL_MASK   (0x10000000U)
 
#define SNVS_HPLR_AT5_SL_SHIFT   (28U)
 
#define SNVS_HPLR_AT5_SL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT5_SL_SHIFT)) & SNVS_HPLR_AT5_SL_MASK)
 

HPCOMR - SNVS_HP Command Register

#define SNVS_HPCOMR_SSM_ST_MASK   (0x1U)
 
#define SNVS_HPCOMR_SSM_ST_SHIFT   (0U)
 
#define SNVS_HPCOMR_SSM_ST(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
 
#define SNVS_HPCOMR_SSM_ST_DIS_MASK   (0x2U)
 
#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT   (1U)
 
#define SNVS_HPCOMR_SSM_ST_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
 
#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK   (0x4U)
 
#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT   (2U)
 
#define SNVS_HPCOMR_SSM_SFNS_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
 
#define SNVS_HPCOMR_LP_SWR_MASK   (0x10U)
 
#define SNVS_HPCOMR_LP_SWR_SHIFT   (4U)
 
#define SNVS_HPCOMR_LP_SWR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
 
#define SNVS_HPCOMR_LP_SWR_DIS_MASK   (0x20U)
 
#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT   (5U)
 
#define SNVS_HPCOMR_LP_SWR_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
 
#define SNVS_HPCOMR_SW_SV_MASK   (0x100U)
 
#define SNVS_HPCOMR_SW_SV_SHIFT   (8U)
 
#define SNVS_HPCOMR_SW_SV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
 
#define SNVS_HPCOMR_SW_FSV_MASK   (0x200U)
 
#define SNVS_HPCOMR_SW_FSV_SHIFT   (9U)
 
#define SNVS_HPCOMR_SW_FSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
 
#define SNVS_HPCOMR_SW_LPSV_MASK   (0x400U)
 
#define SNVS_HPCOMR_SW_LPSV_SHIFT   (10U)
 
#define SNVS_HPCOMR_SW_LPSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
 
#define SNVS_HPCOMR_PROG_ZMK_MASK   (0x1000U)
 
#define SNVS_HPCOMR_PROG_ZMK_SHIFT   (12U)
 
#define SNVS_HPCOMR_PROG_ZMK(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
 
#define SNVS_HPCOMR_MKS_EN_MASK   (0x2000U)
 
#define SNVS_HPCOMR_MKS_EN_SHIFT   (13U)
 
#define SNVS_HPCOMR_MKS_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
 
#define SNVS_HPCOMR_HAC_EN_MASK   (0x10000U)
 
#define SNVS_HPCOMR_HAC_EN_SHIFT   (16U)
 
#define SNVS_HPCOMR_HAC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
 
#define SNVS_HPCOMR_HAC_LOAD_MASK   (0x20000U)
 
#define SNVS_HPCOMR_HAC_LOAD_SHIFT   (17U)
 
#define SNVS_HPCOMR_HAC_LOAD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
 
#define SNVS_HPCOMR_HAC_CLEAR_MASK   (0x40000U)
 
#define SNVS_HPCOMR_HAC_CLEAR_SHIFT   (18U)
 
#define SNVS_HPCOMR_HAC_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
 
#define SNVS_HPCOMR_HAC_STOP_MASK   (0x80000U)
 
#define SNVS_HPCOMR_HAC_STOP_SHIFT   (19U)
 
#define SNVS_HPCOMR_HAC_STOP(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
 
#define SNVS_HPCOMR_NPSWA_EN_MASK   (0x80000000U)
 
#define SNVS_HPCOMR_NPSWA_EN_SHIFT   (31U)
 
#define SNVS_HPCOMR_NPSWA_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
 

HPCR - SNVS_HP Control Register

#define SNVS_HPCR_RTC_EN_MASK   (0x1U)
 
#define SNVS_HPCR_RTC_EN_SHIFT   (0U)
 
#define SNVS_HPCR_RTC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
 
#define SNVS_HPCR_HPTA_EN_MASK   (0x2U)
 
#define SNVS_HPCR_HPTA_EN_SHIFT   (1U)
 
#define SNVS_HPCR_HPTA_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
 
#define SNVS_HPCR_DIS_PI_MASK   (0x4U)
 
#define SNVS_HPCR_DIS_PI_SHIFT   (2U)
 
#define SNVS_HPCR_DIS_PI(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
 
#define SNVS_HPCR_PI_EN_MASK   (0x8U)
 
#define SNVS_HPCR_PI_EN_SHIFT   (3U)
 
#define SNVS_HPCR_PI_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
 
#define SNVS_HPCR_PI_FREQ_MASK   (0xF0U)
 
#define SNVS_HPCR_PI_FREQ_SHIFT   (4U)
 
#define SNVS_HPCR_PI_FREQ(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
 
#define SNVS_HPCR_HPCALB_EN_MASK   (0x100U)
 
#define SNVS_HPCR_HPCALB_EN_SHIFT   (8U)
 
#define SNVS_HPCR_HPCALB_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
 
#define SNVS_HPCR_HPCALB_VAL_MASK   (0x7C00U)
 
#define SNVS_HPCR_HPCALB_VAL_SHIFT   (10U)
 
#define SNVS_HPCR_HPCALB_VAL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
 
#define SNVS_HPCR_HP_TS_MASK   (0x10000U)
 
#define SNVS_HPCR_HP_TS_SHIFT   (16U)
 
#define SNVS_HPCR_HP_TS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
 
#define SNVS_HPCR_BTN_CONFIG_MASK   (0x7000000U)
 
#define SNVS_HPCR_BTN_CONFIG_SHIFT   (24U)
 
#define SNVS_HPCR_BTN_CONFIG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
 
#define SNVS_HPCR_BTN_MASK_MASK   (0x8000000U)
 
#define SNVS_HPCR_BTN_MASK_SHIFT   (27U)
 
#define SNVS_HPCR_BTN_MASK(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
 

HPSICR - SNVS_HP Security Interrupt Control Register

#define SNVS_HPSICR_CAAM_EN_MASK   (0x1U)
 
#define SNVS_HPSICR_CAAM_EN_SHIFT   (0U)
 
#define SNVS_HPSICR_CAAM_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_CAAM_EN_SHIFT)) & SNVS_HPSICR_CAAM_EN_MASK)
 
#define SNVS_HPSICR_JTAGC_EN_MASK   (0x2U)
 
#define SNVS_HPSICR_JTAGC_EN_SHIFT   (1U)
 
#define SNVS_HPSICR_JTAGC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_JTAGC_EN_SHIFT)) & SNVS_HPSICR_JTAGC_EN_MASK)
 
#define SNVS_HPSICR_WDOG2_EN_MASK   (0x4U)
 
#define SNVS_HPSICR_WDOG2_EN_SHIFT   (2U)
 
#define SNVS_HPSICR_WDOG2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_WDOG2_EN_SHIFT)) & SNVS_HPSICR_WDOG2_EN_MASK)
 
#define SNVS_HPSICR_SRC_EN_MASK   (0x10U)
 
#define SNVS_HPSICR_SRC_EN_SHIFT   (4U)
 
#define SNVS_HPSICR_SRC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SRC_EN_SHIFT)) & SNVS_HPSICR_SRC_EN_MASK)
 
#define SNVS_HPSICR_OCOTP_EN_MASK   (0x20U)
 
#define SNVS_HPSICR_OCOTP_EN_SHIFT   (5U)
 
#define SNVS_HPSICR_OCOTP_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_OCOTP_EN_SHIFT)) & SNVS_HPSICR_OCOTP_EN_MASK)
 
#define SNVS_HPSICR_LPSVI_EN_MASK   (0x80000000U)
 
#define SNVS_HPSICR_LPSVI_EN_SHIFT   (31U)
 
#define SNVS_HPSICR_LPSVI_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
 

HPSVCR - SNVS_HP Security Violation Control Register

#define SNVS_HPSVCR_CAAM_CFG_MASK   (0x1U)
 
#define SNVS_HPSVCR_CAAM_CFG_SHIFT   (0U)
 
#define SNVS_HPSVCR_CAAM_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_CAAM_CFG_SHIFT)) & SNVS_HPSVCR_CAAM_CFG_MASK)
 
#define SNVS_HPSVCR_JTAGC_CFG_MASK   (0x2U)
 
#define SNVS_HPSVCR_JTAGC_CFG_SHIFT   (1U)
 
#define SNVS_HPSVCR_JTAGC_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_JTAGC_CFG_SHIFT)) & SNVS_HPSVCR_JTAGC_CFG_MASK)
 
#define SNVS_HPSVCR_WDOG2_CFG_MASK   (0x4U)
 
#define SNVS_HPSVCR_WDOG2_CFG_SHIFT   (2U)
 
#define SNVS_HPSVCR_WDOG2_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
 
#define SNVS_HPSVCR_SRC_CFG_MASK   (0x10U)
 
#define SNVS_HPSVCR_SRC_CFG_SHIFT   (4U)
 
#define SNVS_HPSVCR_SRC_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SRC_CFG_SHIFT)) & SNVS_HPSVCR_SRC_CFG_MASK)
 
#define SNVS_HPSVCR_OCOTP_CFG_MASK   (0x60U)
 
#define SNVS_HPSVCR_OCOTP_CFG_SHIFT   (5U)
 
#define SNVS_HPSVCR_OCOTP_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_OCOTP_CFG_SHIFT)) & SNVS_HPSVCR_OCOTP_CFG_MASK)
 
#define SNVS_HPSVCR_LPSV_CFG_MASK   (0xC0000000U)
 
#define SNVS_HPSVCR_LPSV_CFG_SHIFT   (30U)
 
#define SNVS_HPSVCR_LPSV_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
 

HPSR - SNVS_HP Status Register

#define SNVS_HPSR_HPTA_MASK   (0x1U)
 
#define SNVS_HPSR_HPTA_SHIFT   (0U)
 
#define SNVS_HPSR_HPTA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
 
#define SNVS_HPSR_PI_MASK   (0x2U)
 
#define SNVS_HPSR_PI_SHIFT   (1U)
 
#define SNVS_HPSR_PI(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
 
#define SNVS_HPSR_LPDIS_MASK   (0x10U)
 
#define SNVS_HPSR_LPDIS_SHIFT   (4U)
 
#define SNVS_HPSR_LPDIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
 
#define SNVS_HPSR_BTN_MASK   (0x40U)
 
#define SNVS_HPSR_BTN_SHIFT   (6U)
 
#define SNVS_HPSR_BTN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
 
#define SNVS_HPSR_BI_MASK   (0x80U)
 
#define SNVS_HPSR_BI_SHIFT   (7U)
 
#define SNVS_HPSR_BI(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
 
#define SNVS_HPSR_SSM_STATE_MASK   (0xF00U)
 
#define SNVS_HPSR_SSM_STATE_SHIFT   (8U)
 
#define SNVS_HPSR_SSM_STATE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
 
#define SNVS_HPSR_SYS_SECURITY_CFG_MASK   (0x7000U)
 
#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT   (12U)
 
#define SNVS_HPSR_SYS_SECURITY_CFG(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)
 
#define SNVS_HPSR_SYS_SECURE_BOOT_MASK   (0x8000U)
 
#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT   (15U)
 
#define SNVS_HPSR_SYS_SECURE_BOOT(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)
 
#define SNVS_HPSR_OTPMK_ZERO_MASK   (0x8000000U)
 
#define SNVS_HPSR_OTPMK_ZERO_SHIFT   (27U)
 
#define SNVS_HPSR_OTPMK_ZERO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
 
#define SNVS_HPSR_ZMK_ZERO_MASK   (0x80000000U)
 
#define SNVS_HPSR_ZMK_ZERO_SHIFT   (31U)
 
#define SNVS_HPSR_ZMK_ZERO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
 

HPSVSR - SNVS_HP Security Violation Status Register

#define SNVS_HPSVSR_CAAM_MASK   (0x1U)
 
#define SNVS_HPSVSR_CAAM_SHIFT   (0U)
 
#define SNVS_HPSVSR_CAAM(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_CAAM_SHIFT)) & SNVS_HPSVSR_CAAM_MASK)
 
#define SNVS_HPSVSR_JTAGC_MASK   (0x2U)
 
#define SNVS_HPSVSR_JTAGC_SHIFT   (1U)
 
#define SNVS_HPSVSR_JTAGC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_JTAGC_SHIFT)) & SNVS_HPSVSR_JTAGC_MASK)
 
#define SNVS_HPSVSR_WDOG2_MASK   (0x4U)
 
#define SNVS_HPSVSR_WDOG2_SHIFT   (2U)
 
#define SNVS_HPSVSR_WDOG2(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_WDOG2_SHIFT)) & SNVS_HPSVSR_WDOG2_MASK)
 
#define SNVS_HPSVSR_SRC_MASK   (0x10U)
 
#define SNVS_HPSVSR_SRC_SHIFT   (4U)
 
#define SNVS_HPSVSR_SRC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SRC_SHIFT)) & SNVS_HPSVSR_SRC_MASK)
 
#define SNVS_HPSVSR_OCOTP_MASK   (0x20U)
 
#define SNVS_HPSVSR_OCOTP_SHIFT   (5U)
 
#define SNVS_HPSVSR_OCOTP(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_OCOTP_SHIFT)) & SNVS_HPSVSR_OCOTP_MASK)
 
#define SNVS_HPSVSR_SW_SV_MASK   (0x2000U)
 
#define SNVS_HPSVSR_SW_SV_SHIFT   (13U)
 
#define SNVS_HPSVSR_SW_SV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
 
#define SNVS_HPSVSR_SW_FSV_MASK   (0x4000U)
 
#define SNVS_HPSVSR_SW_FSV_SHIFT   (14U)
 
#define SNVS_HPSVSR_SW_FSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
 
#define SNVS_HPSVSR_SW_LPSV_MASK   (0x8000U)
 
#define SNVS_HPSVSR_SW_LPSV_SHIFT   (15U)
 
#define SNVS_HPSVSR_SW_LPSV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
 
#define SNVS_HPSVSR_ZMK_SYNDROME_MASK   (0x1FF0000U)
 
#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT   (16U)
 
#define SNVS_HPSVSR_ZMK_SYNDROME(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
 
#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK   (0x8000000U)
 
#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT   (27U)
 
#define SNVS_HPSVSR_ZMK_ECC_FAIL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
 
#define SNVS_HPSVSR_LP_SEC_VIO_MASK   (0x80000000U)
 
#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT   (31U)
 
#define SNVS_HPSVSR_LP_SEC_VIO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
 

HPHACIVR - SNVS_HP High Assurance Counter IV Register

#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT   (0U)
 
#define SNVS_HPHACIVR_HAC_COUNTER_IV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
 

HPHACR - SNVS_HP High Assurance Counter Register

#define SNVS_HPHACR_HAC_COUNTER_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPHACR_HAC_COUNTER_SHIFT   (0U)
 
#define SNVS_HPHACR_HAC_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
 

HPRTCMR - SNVS_HP Real Time Counter MSB Register

#define SNVS_HPRTCMR_RTC_MASK   (0x7FFFU)
 
#define SNVS_HPRTCMR_RTC_SHIFT   (0U)
 
#define SNVS_HPRTCMR_RTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
 

HPRTCLR - SNVS_HP Real Time Counter LSB Register

#define SNVS_HPRTCLR_RTC_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPRTCLR_RTC_SHIFT   (0U)
 
#define SNVS_HPRTCLR_RTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
 

HPTAMR - SNVS_HP Time Alarm MSB Register

#define SNVS_HPTAMR_HPTA_MS_MASK   (0x7FFFU)
 
#define SNVS_HPTAMR_HPTA_MS_SHIFT   (0U)
 
#define SNVS_HPTAMR_HPTA_MS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
 

HPTALR - SNVS_HP Time Alarm LSB Register

#define SNVS_HPTALR_HPTA_LS_MASK   (0xFFFFFFFFU)
 
#define SNVS_HPTALR_HPTA_LS_SHIFT   (0U)
 
#define SNVS_HPTALR_HPTA_LS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
 

LPLR - SNVS_LP Lock Register

#define SNVS_LPLR_ZMK_WHL_MASK   (0x1U)
 
#define SNVS_LPLR_ZMK_WHL_SHIFT   (0U)
 
#define SNVS_LPLR_ZMK_WHL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
 
#define SNVS_LPLR_ZMK_RHL_MASK   (0x2U)
 
#define SNVS_LPLR_ZMK_RHL_SHIFT   (1U)
 
#define SNVS_LPLR_ZMK_RHL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
 
#define SNVS_LPLR_SRTC_HL_MASK   (0x4U)
 
#define SNVS_LPLR_SRTC_HL_SHIFT   (2U)
 
#define SNVS_LPLR_SRTC_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
 
#define SNVS_LPLR_LPCALB_HL_MASK   (0x8U)
 
#define SNVS_LPLR_LPCALB_HL_SHIFT   (3U)
 
#define SNVS_LPLR_LPCALB_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
 
#define SNVS_LPLR_MC_HL_MASK   (0x10U)
 
#define SNVS_LPLR_MC_HL_SHIFT   (4U)
 
#define SNVS_LPLR_MC_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
 
#define SNVS_LPLR_GPR_HL_MASK   (0x20U)
 
#define SNVS_LPLR_GPR_HL_SHIFT   (5U)
 
#define SNVS_LPLR_GPR_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
 
#define SNVS_LPLR_LPSVCR_HL_MASK   (0x40U)
 
#define SNVS_LPLR_LPSVCR_HL_SHIFT   (6U)
 
#define SNVS_LPLR_LPSVCR_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
 
#define SNVS_LPLR_LPTGFCR_HL_MASK   (0x80U)
 
#define SNVS_LPLR_LPTGFCR_HL_SHIFT   (7U)
 
#define SNVS_LPLR_LPTGFCR_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK)
 
#define SNVS_LPLR_LPSECR_HL_MASK   (0x100U)
 
#define SNVS_LPLR_LPSECR_HL_SHIFT   (8U)
 
#define SNVS_LPLR_LPSECR_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)
 
#define SNVS_LPLR_MKS_HL_MASK   (0x200U)
 
#define SNVS_LPLR_MKS_HL_SHIFT   (9U)
 
#define SNVS_LPLR_MKS_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
 
#define SNVS_LPLR_AT1_HL_MASK   (0x1000000U)
 
#define SNVS_LPLR_AT1_HL_SHIFT   (24U)
 
#define SNVS_LPLR_AT1_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT1_HL_SHIFT)) & SNVS_LPLR_AT1_HL_MASK)
 
#define SNVS_LPLR_AT2_HL_MASK   (0x2000000U)
 
#define SNVS_LPLR_AT2_HL_SHIFT   (25U)
 
#define SNVS_LPLR_AT2_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT2_HL_SHIFT)) & SNVS_LPLR_AT2_HL_MASK)
 
#define SNVS_LPLR_AT3_HL_MASK   (0x4000000U)
 
#define SNVS_LPLR_AT3_HL_SHIFT   (26U)
 
#define SNVS_LPLR_AT3_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT3_HL_SHIFT)) & SNVS_LPLR_AT3_HL_MASK)
 
#define SNVS_LPLR_AT4_HL_MASK   (0x8000000U)
 
#define SNVS_LPLR_AT4_HL_SHIFT   (27U)
 
#define SNVS_LPLR_AT4_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT4_HL_SHIFT)) & SNVS_LPLR_AT4_HL_MASK)
 
#define SNVS_LPLR_AT5_HL_MASK   (0x10000000U)
 
#define SNVS_LPLR_AT5_HL_SHIFT   (28U)
 
#define SNVS_LPLR_AT5_HL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT5_HL_SHIFT)) & SNVS_LPLR_AT5_HL_MASK)
 

LPCR - SNVS_LP Control Register

#define SNVS_LPCR_SRTC_ENV_MASK   (0x1U)
 
#define SNVS_LPCR_SRTC_ENV_SHIFT   (0U)
 
#define SNVS_LPCR_SRTC_ENV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
 
#define SNVS_LPCR_LPTA_EN_MASK   (0x2U)
 
#define SNVS_LPCR_LPTA_EN_SHIFT   (1U)
 
#define SNVS_LPCR_LPTA_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
 
#define SNVS_LPCR_MC_ENV_MASK   (0x4U)
 
#define SNVS_LPCR_MC_ENV_SHIFT   (2U)
 
#define SNVS_LPCR_MC_ENV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
 
#define SNVS_LPCR_LPWUI_EN_MASK   (0x8U)
 
#define SNVS_LPCR_LPWUI_EN_SHIFT   (3U)
 
#define SNVS_LPCR_LPWUI_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
 
#define SNVS_LPCR_SRTC_INV_EN_MASK   (0x10U)
 
#define SNVS_LPCR_SRTC_INV_EN_SHIFT   (4U)
 
#define SNVS_LPCR_SRTC_INV_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
 
#define SNVS_LPCR_DP_EN_MASK   (0x20U)
 
#define SNVS_LPCR_DP_EN_SHIFT   (5U)
 
#define SNVS_LPCR_DP_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
 
#define SNVS_LPCR_TOP_MASK   (0x40U)
 
#define SNVS_LPCR_TOP_SHIFT   (6U)
 
#define SNVS_LPCR_TOP(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
 
#define SNVS_LPCR_LVD_EN_MASK   (0x80U)
 
#define SNVS_LPCR_LVD_EN_SHIFT   (7U)
 
#define SNVS_LPCR_LVD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK)
 
#define SNVS_LPCR_LPCALB_EN_MASK   (0x100U)
 
#define SNVS_LPCR_LPCALB_EN_SHIFT   (8U)
 
#define SNVS_LPCR_LPCALB_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
 
#define SNVS_LPCR_LPCALB_VAL_MASK   (0x7C00U)
 
#define SNVS_LPCR_LPCALB_VAL_SHIFT   (10U)
 
#define SNVS_LPCR_LPCALB_VAL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
 
#define SNVS_LPCR_BTN_PRESS_TIME_MASK   (0x30000U)
 
#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT   (16U)
 
#define SNVS_LPCR_BTN_PRESS_TIME(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
 
#define SNVS_LPCR_DEBOUNCE_MASK   (0xC0000U)
 
#define SNVS_LPCR_DEBOUNCE_SHIFT   (18U)
 
#define SNVS_LPCR_DEBOUNCE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
 
#define SNVS_LPCR_ON_TIME_MASK   (0x300000U)
 
#define SNVS_LPCR_ON_TIME_SHIFT   (20U)
 
#define SNVS_LPCR_ON_TIME(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
 
#define SNVS_LPCR_PK_EN_MASK   (0x400000U)
 
#define SNVS_LPCR_PK_EN_SHIFT   (22U)
 
#define SNVS_LPCR_PK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
 
#define SNVS_LPCR_PK_OVERRIDE_MASK   (0x800000U)
 
#define SNVS_LPCR_PK_OVERRIDE_SHIFT   (23U)
 
#define SNVS_LPCR_PK_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
 
#define SNVS_LPCR_GPR_Z_DIS_MASK   (0x1000000U)
 
#define SNVS_LPCR_GPR_Z_DIS_SHIFT   (24U)
 
#define SNVS_LPCR_GPR_Z_DIS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
 

LPMKCR - SNVS_LP Master Key Control Register

#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK   (0x3U)
 
#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT   (0U)
 
#define SNVS_LPMKCR_MASTER_KEY_SEL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
 
#define SNVS_LPMKCR_ZMK_HWP_MASK   (0x4U)
 
#define SNVS_LPMKCR_ZMK_HWP_SHIFT   (2U)
 
#define SNVS_LPMKCR_ZMK_HWP(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
 
#define SNVS_LPMKCR_ZMK_VAL_MASK   (0x8U)
 
#define SNVS_LPMKCR_ZMK_VAL_SHIFT   (3U)
 
#define SNVS_LPMKCR_ZMK_VAL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
 
#define SNVS_LPMKCR_ZMK_ECC_EN_MASK   (0x10U)
 
#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT   (4U)
 
#define SNVS_LPMKCR_ZMK_ECC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
 
#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK   (0xFF80U)
 
#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT   (7U)
 
#define SNVS_LPMKCR_ZMK_ECC_VALUE(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
 

LPSVCR - SNVS_LP Security Violation Control Register

#define SNVS_LPSVCR_CAAM_EN_MASK   (0x1U)
 
#define SNVS_LPSVCR_CAAM_EN_SHIFT   (0U)
 
#define SNVS_LPSVCR_CAAM_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_CAAM_EN_SHIFT)) & SNVS_LPSVCR_CAAM_EN_MASK)
 
#define SNVS_LPSVCR_JTAGC_EN_MASK   (0x2U)
 
#define SNVS_LPSVCR_JTAGC_EN_SHIFT   (1U)
 
#define SNVS_LPSVCR_JTAGC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_JTAGC_EN_SHIFT)) & SNVS_LPSVCR_JTAGC_EN_MASK)
 
#define SNVS_LPSVCR_WDOG2_EN_MASK   (0x4U)
 
#define SNVS_LPSVCR_WDOG2_EN_SHIFT   (2U)
 
#define SNVS_LPSVCR_WDOG2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_WDOG2_EN_SHIFT)) & SNVS_LPSVCR_WDOG2_EN_MASK)
 
#define SNVS_LPSVCR_SRC_EN_MASK   (0x10U)
 
#define SNVS_LPSVCR_SRC_EN_SHIFT   (4U)
 
#define SNVS_LPSVCR_SRC_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SRC_EN_SHIFT)) & SNVS_LPSVCR_SRC_EN_MASK)
 
#define SNVS_LPSVCR_OCOTP_EN_MASK   (0x20U)
 
#define SNVS_LPSVCR_OCOTP_EN_SHIFT   (5U)
 
#define SNVS_LPSVCR_OCOTP_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_OCOTP_EN_SHIFT)) & SNVS_LPSVCR_OCOTP_EN_MASK)
 

LPTGFCR - SNVS_LP Tamper Glitch Filters Configuration Register

#define SNVS_LPTGFCR_WMTGF_MASK   (0x1FU)
 
#define SNVS_LPTGFCR_WMTGF_SHIFT   (0U)
 
#define SNVS_LPTGFCR_WMTGF(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_SHIFT)) & SNVS_LPTGFCR_WMTGF_MASK)
 
#define SNVS_LPTGFCR_WMTGF_EN_MASK   (0x80U)
 
#define SNVS_LPTGFCR_WMTGF_EN_SHIFT   (7U)
 
#define SNVS_LPTGFCR_WMTGF_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK)
 
#define SNVS_LPTGFCR_ETGF1_MASK   (0x7F0000U)
 
#define SNVS_LPTGFCR_ETGF1_SHIFT   (16U)
 
#define SNVS_LPTGFCR_ETGF1(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_SHIFT)) & SNVS_LPTGFCR_ETGF1_MASK)
 
#define SNVS_LPTGFCR_ETGF1_EN_MASK   (0x800000U)
 
#define SNVS_LPTGFCR_ETGF1_EN_SHIFT   (23U)
 
#define SNVS_LPTGFCR_ETGF1_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK)
 
#define SNVS_LPTGFCR_ETGF2_MASK   (0x7F000000U)
 
#define SNVS_LPTGFCR_ETGF2_SHIFT   (24U)
 
#define SNVS_LPTGFCR_ETGF2(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_SHIFT)) & SNVS_LPTGFCR_ETGF2_MASK)
 
#define SNVS_LPTGFCR_ETGF2_EN_MASK   (0x80000000U)
 
#define SNVS_LPTGFCR_ETGF2_EN_SHIFT   (31U)
 
#define SNVS_LPTGFCR_ETGF2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_EN_SHIFT)) & SNVS_LPTGFCR_ETGF2_EN_MASK)
 

LPTDCR - SNVS_LP Tamper Detect Configuration Register

#define SNVS_LPTDCR_SRTCR_EN_MASK   (0x2U)
 
#define SNVS_LPTDCR_SRTCR_EN_SHIFT   (1U)
 
#define SNVS_LPTDCR_SRTCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
 
#define SNVS_LPTDCR_MCR_EN_MASK   (0x4U)
 
#define SNVS_LPTDCR_MCR_EN_SHIFT   (2U)
 
#define SNVS_LPTDCR_MCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
 
#define SNVS_LPTDCR_CT_EN_MASK   (0x10U)
 
#define SNVS_LPTDCR_CT_EN_SHIFT   (4U)
 
#define SNVS_LPTDCR_CT_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK)
 
#define SNVS_LPTDCR_TT_EN_MASK   (0x20U)
 
#define SNVS_LPTDCR_TT_EN_SHIFT   (5U)
 
#define SNVS_LPTDCR_TT_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK)
 
#define SNVS_LPTDCR_VT_EN_MASK   (0x40U)
 
#define SNVS_LPTDCR_VT_EN_SHIFT   (6U)
 
#define SNVS_LPTDCR_VT_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK)
 
#define SNVS_LPTDCR_WMT1_EN_MASK   (0x80U)
 
#define SNVS_LPTDCR_WMT1_EN_SHIFT   (7U)
 
#define SNVS_LPTDCR_WMT1_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK)
 
#define SNVS_LPTDCR_WMT2_EN_MASK   (0x100U)
 
#define SNVS_LPTDCR_WMT2_EN_SHIFT   (8U)
 
#define SNVS_LPTDCR_WMT2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK)
 
#define SNVS_LPTDCR_ET1_EN_MASK   (0x200U)
 
#define SNVS_LPTDCR_ET1_EN_SHIFT   (9U)
 
#define SNVS_LPTDCR_ET1_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
 
#define SNVS_LPTDCR_ET2_EN_MASK   (0x400U)
 
#define SNVS_LPTDCR_ET2_EN_SHIFT   (10U)
 
#define SNVS_LPTDCR_ET2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK)
 
#define SNVS_LPTDCR_ET1P_MASK   (0x800U)
 
#define SNVS_LPTDCR_ET1P_SHIFT   (11U)
 
#define SNVS_LPTDCR_ET1P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
 
#define SNVS_LPTDCR_ET2P_MASK   (0x1000U)
 
#define SNVS_LPTDCR_ET2P_SHIFT   (12U)
 
#define SNVS_LPTDCR_ET2P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK)
 
#define SNVS_LPTDCR_PFD_OBSERV_MASK   (0x4000U)
 
#define SNVS_LPTDCR_PFD_OBSERV_SHIFT   (14U)
 
#define SNVS_LPTDCR_PFD_OBSERV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
 
#define SNVS_LPTDCR_POR_OBSERV_MASK   (0x8000U)
 
#define SNVS_LPTDCR_POR_OBSERV_SHIFT   (15U)
 
#define SNVS_LPTDCR_POR_OBSERV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
 
#define SNVS_LPTDCR_LTDC_MASK   (0x70000U)
 
#define SNVS_LPTDCR_LTDC_SHIFT   (16U)
 
#define SNVS_LPTDCR_LTDC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_LTDC_SHIFT)) & SNVS_LPTDCR_LTDC_MASK)
 
#define SNVS_LPTDCR_HTDC_MASK   (0x700000U)
 
#define SNVS_LPTDCR_HTDC_SHIFT   (20U)
 
#define SNVS_LPTDCR_HTDC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_HTDC_SHIFT)) & SNVS_LPTDCR_HTDC_MASK)
 
#define SNVS_LPTDCR_VRC_MASK   (0x7000000U)
 
#define SNVS_LPTDCR_VRC_SHIFT   (24U)
 
#define SNVS_LPTDCR_VRC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VRC_SHIFT)) & SNVS_LPTDCR_VRC_MASK)
 
#define SNVS_LPTDCR_OSCB_MASK   (0x10000000U)
 
#define SNVS_LPTDCR_OSCB_SHIFT   (28U)
 
#define SNVS_LPTDCR_OSCB(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
 

LPSR - SNVS_LP Status Register

#define SNVS_LPSR_LPTA_MASK   (0x1U)
 
#define SNVS_LPSR_LPTA_SHIFT   (0U)
 
#define SNVS_LPSR_LPTA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
 
#define SNVS_LPSR_SRTCR_MASK   (0x2U)
 
#define SNVS_LPSR_SRTCR_SHIFT   (1U)
 
#define SNVS_LPSR_SRTCR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
 
#define SNVS_LPSR_MCR_MASK   (0x4U)
 
#define SNVS_LPSR_MCR_SHIFT   (2U)
 
#define SNVS_LPSR_MCR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
 
#define SNVS_LPSR_LVD_MASK   (0x8U)
 
#define SNVS_LPSR_LVD_SHIFT   (3U)
 
#define SNVS_LPSR_LVD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)
 
#define SNVS_LPSR_CTD_MASK   (0x10U)
 
#define SNVS_LPSR_CTD_SHIFT   (4U)
 
#define SNVS_LPSR_CTD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK)
 
#define SNVS_LPSR_TTD_MASK   (0x20U)
 
#define SNVS_LPSR_TTD_SHIFT   (5U)
 
#define SNVS_LPSR_TTD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK)
 
#define SNVS_LPSR_VTD_MASK   (0x40U)
 
#define SNVS_LPSR_VTD_SHIFT   (6U)
 
#define SNVS_LPSR_VTD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
 
#define SNVS_LPSR_WMT1D_MASK   (0x80U)
 
#define SNVS_LPSR_WMT1D_SHIFT   (7U)
 
#define SNVS_LPSR_WMT1D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK)
 
#define SNVS_LPSR_WMT2D_MASK   (0x100U)
 
#define SNVS_LPSR_WMT2D_SHIFT   (8U)
 
#define SNVS_LPSR_WMT2D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK)
 
#define SNVS_LPSR_ET1D_MASK   (0x200U)
 
#define SNVS_LPSR_ET1D_SHIFT   (9U)
 
#define SNVS_LPSR_ET1D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
 
#define SNVS_LPSR_ET2D_MASK   (0x400U)
 
#define SNVS_LPSR_ET2D_SHIFT   (10U)
 
#define SNVS_LPSR_ET2D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
 
#define SNVS_LPSR_ESVD_MASK   (0x10000U)
 
#define SNVS_LPSR_ESVD_SHIFT   (16U)
 
#define SNVS_LPSR_ESVD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
 
#define SNVS_LPSR_EO_MASK   (0x20000U)
 
#define SNVS_LPSR_EO_SHIFT   (17U)
 
#define SNVS_LPSR_EO(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
 
#define SNVS_LPSR_SPOF_MASK   (0x40000U)
 
#define SNVS_LPSR_SPOF_SHIFT   (18U)
 
#define SNVS_LPSR_SPOF(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
 
#define SNVS_LPSR_LPNS_MASK   (0x40000000U)
 
#define SNVS_LPSR_LPNS_SHIFT   (30U)
 
#define SNVS_LPSR_LPNS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
 
#define SNVS_LPSR_LPS_MASK   (0x80000000U)
 
#define SNVS_LPSR_LPS_SHIFT   (31U)
 
#define SNVS_LPSR_LPS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
 

LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register

#define SNVS_LPSRTCMR_SRTC_MASK   (0x7FFFU)
 
#define SNVS_LPSRTCMR_SRTC_SHIFT   (0U)
 
#define SNVS_LPSRTCMR_SRTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
 

LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register

#define SNVS_LPSRTCLR_SRTC_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPSRTCLR_SRTC_SHIFT   (0U)
 
#define SNVS_LPSRTCLR_SRTC(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
 

LPTAR - SNVS_LP Time Alarm Register

#define SNVS_LPTAR_LPTA_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPTAR_LPTA_SHIFT   (0U)
 
#define SNVS_LPTAR_LPTA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
 

LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register

#define SNVS_LPSMCMR_MON_COUNTER_MASK   (0xFFFFU)
 
#define SNVS_LPSMCMR_MON_COUNTER_SHIFT   (0U)
 
#define SNVS_LPSMCMR_MON_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
 
#define SNVS_LPSMCMR_MC_ERA_BITS_MASK   (0xFFFF0000U)
 
#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT   (16U)
 
#define SNVS_LPSMCMR_MC_ERA_BITS(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
 

LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register

#define SNVS_LPSMCLR_MON_COUNTER_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPSMCLR_MON_COUNTER_SHIFT   (0U)
 
#define SNVS_LPSMCLR_MON_COUNTER(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
 

LPLVDR - SNVS_LP Digital Low-Voltage Detector Register

#define SNVS_LPLVDR_LVD_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPLVDR_LVD_SHIFT   (0U)
 
#define SNVS_LPLVDR_LVD(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK)
 

LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias)

#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT   (0U)
 
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
 

LPZMKR - SNVS_LP Zeroizable Master Key Register

#define SNVS_LPZMKR_ZMK_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPZMKR_ZMK_SHIFT   (0U)
 
#define SNVS_LPZMKR_ZMK(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
 

LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3

#define SNVS_LPGPR_ALIAS_GPR_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPGPR_ALIAS_GPR_SHIFT   (0U)
 
#define SNVS_LPGPR_ALIAS_GPR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
 

LPTDC2R - SNVS_LP Tamper Detectors Config 2 Register

#define SNVS_LPTDC2R_ET3_EN_MASK   (0x1U)
 
#define SNVS_LPTDC2R_ET3_EN_SHIFT   (0U)
 
#define SNVS_LPTDC2R_ET3_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK)
 
#define SNVS_LPTDC2R_ET4_EN_MASK   (0x2U)
 
#define SNVS_LPTDC2R_ET4_EN_SHIFT   (1U)
 
#define SNVS_LPTDC2R_ET4_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK)
 
#define SNVS_LPTDC2R_ET5_EN_MASK   (0x4U)
 
#define SNVS_LPTDC2R_ET5_EN_SHIFT   (2U)
 
#define SNVS_LPTDC2R_ET5_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK)
 
#define SNVS_LPTDC2R_ET6_EN_MASK   (0x8U)
 
#define SNVS_LPTDC2R_ET6_EN_SHIFT   (3U)
 
#define SNVS_LPTDC2R_ET6_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK)
 
#define SNVS_LPTDC2R_ET7_EN_MASK   (0x10U)
 
#define SNVS_LPTDC2R_ET7_EN_SHIFT   (4U)
 
#define SNVS_LPTDC2R_ET7_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK)
 
#define SNVS_LPTDC2R_ET8_EN_MASK   (0x20U)
 
#define SNVS_LPTDC2R_ET8_EN_SHIFT   (5U)
 
#define SNVS_LPTDC2R_ET8_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK)
 
#define SNVS_LPTDC2R_ET9_EN_MASK   (0x40U)
 
#define SNVS_LPTDC2R_ET9_EN_SHIFT   (6U)
 
#define SNVS_LPTDC2R_ET9_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK)
 
#define SNVS_LPTDC2R_ET10_EN_MASK   (0x80U)
 
#define SNVS_LPTDC2R_ET10_EN_SHIFT   (7U)
 
#define SNVS_LPTDC2R_ET10_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK)
 
#define SNVS_LPTDC2R_ET3P_MASK   (0x10000U)
 
#define SNVS_LPTDC2R_ET3P_SHIFT   (16U)
 
#define SNVS_LPTDC2R_ET3P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK)
 
#define SNVS_LPTDC2R_ET4P_MASK   (0x20000U)
 
#define SNVS_LPTDC2R_ET4P_SHIFT   (17U)
 
#define SNVS_LPTDC2R_ET4P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK)
 
#define SNVS_LPTDC2R_ET5P_MASK   (0x40000U)
 
#define SNVS_LPTDC2R_ET5P_SHIFT   (18U)
 
#define SNVS_LPTDC2R_ET5P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK)
 
#define SNVS_LPTDC2R_ET6P_MASK   (0x80000U)
 
#define SNVS_LPTDC2R_ET6P_SHIFT   (19U)
 
#define SNVS_LPTDC2R_ET6P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK)
 
#define SNVS_LPTDC2R_ET7P_MASK   (0x100000U)
 
#define SNVS_LPTDC2R_ET7P_SHIFT   (20U)
 
#define SNVS_LPTDC2R_ET7P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK)
 
#define SNVS_LPTDC2R_ET8P_MASK   (0x200000U)
 
#define SNVS_LPTDC2R_ET8P_SHIFT   (21U)
 
#define SNVS_LPTDC2R_ET8P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK)
 
#define SNVS_LPTDC2R_ET9P_MASK   (0x400000U)
 
#define SNVS_LPTDC2R_ET9P_SHIFT   (22U)
 
#define SNVS_LPTDC2R_ET9P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK)
 
#define SNVS_LPTDC2R_ET10P_MASK   (0x800000U)
 
#define SNVS_LPTDC2R_ET10P_SHIFT   (23U)
 
#define SNVS_LPTDC2R_ET10P(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10P_SHIFT)) & SNVS_LPTDC2R_ET10P_MASK)
 

LPTDSR - SNVS_LP Tamper Detectors Status Register

#define SNVS_LPTDSR_ET3D_MASK   (0x1U)
 
#define SNVS_LPTDSR_ET3D_SHIFT   (0U)
 
#define SNVS_LPTDSR_ET3D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK)
 
#define SNVS_LPTDSR_ET4D_MASK   (0x2U)
 
#define SNVS_LPTDSR_ET4D_SHIFT   (1U)
 
#define SNVS_LPTDSR_ET4D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK)
 
#define SNVS_LPTDSR_ET5D_MASK   (0x4U)
 
#define SNVS_LPTDSR_ET5D_SHIFT   (2U)
 
#define SNVS_LPTDSR_ET5D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK)
 
#define SNVS_LPTDSR_ET6D_MASK   (0x8U)
 
#define SNVS_LPTDSR_ET6D_SHIFT   (3U)
 
#define SNVS_LPTDSR_ET6D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK)
 
#define SNVS_LPTDSR_ET7D_MASK   (0x10U)
 
#define SNVS_LPTDSR_ET7D_SHIFT   (4U)
 
#define SNVS_LPTDSR_ET7D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK)
 
#define SNVS_LPTDSR_ET8D_MASK   (0x20U)
 
#define SNVS_LPTDSR_ET8D_SHIFT   (5U)
 
#define SNVS_LPTDSR_ET8D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK)
 
#define SNVS_LPTDSR_ET9D_MASK   (0x40U)
 
#define SNVS_LPTDSR_ET9D_SHIFT   (6U)
 
#define SNVS_LPTDSR_ET9D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK)
 
#define SNVS_LPTDSR_ET10D_MASK   (0x80U)
 
#define SNVS_LPTDSR_ET10D_SHIFT   (7U)
 
#define SNVS_LPTDSR_ET10D(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET10D_SHIFT)) & SNVS_LPTDSR_ET10D_MASK)
 

LPTGF1CR - SNVS_LP Tamper Glitch Filter 1 Configuration Register

#define SNVS_LPTGF1CR_ETGF3_MASK   (0x7FU)
 
#define SNVS_LPTGF1CR_ETGF3_SHIFT   (0U)
 
#define SNVS_LPTGF1CR_ETGF3(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_SHIFT)) & SNVS_LPTGF1CR_ETGF3_MASK)
 
#define SNVS_LPTGF1CR_ETGF3_EN_MASK   (0x80U)
 
#define SNVS_LPTGF1CR_ETGF3_EN_SHIFT   (7U)
 
#define SNVS_LPTGF1CR_ETGF3_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK)
 
#define SNVS_LPTGF1CR_ETGF4_MASK   (0x7F00U)
 
#define SNVS_LPTGF1CR_ETGF4_SHIFT   (8U)
 
#define SNVS_LPTGF1CR_ETGF4(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_SHIFT)) & SNVS_LPTGF1CR_ETGF4_MASK)
 
#define SNVS_LPTGF1CR_ETGF4_EN_MASK   (0x8000U)
 
#define SNVS_LPTGF1CR_ETGF4_EN_SHIFT   (15U)
 
#define SNVS_LPTGF1CR_ETGF4_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK)
 
#define SNVS_LPTGF1CR_ETGF5_MASK   (0x7F0000U)
 
#define SNVS_LPTGF1CR_ETGF5_SHIFT   (16U)
 
#define SNVS_LPTGF1CR_ETGF5(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_SHIFT)) & SNVS_LPTGF1CR_ETGF5_MASK)
 
#define SNVS_LPTGF1CR_ETGF5_EN_MASK   (0x800000U)
 
#define SNVS_LPTGF1CR_ETGF5_EN_SHIFT   (23U)
 
#define SNVS_LPTGF1CR_ETGF5_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK)
 
#define SNVS_LPTGF1CR_ETGF6_MASK   (0x7F000000U)
 
#define SNVS_LPTGF1CR_ETGF6_SHIFT   (24U)
 
#define SNVS_LPTGF1CR_ETGF6(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_SHIFT)) & SNVS_LPTGF1CR_ETGF6_MASK)
 
#define SNVS_LPTGF1CR_ETGF6_EN_MASK   (0x80000000U)
 
#define SNVS_LPTGF1CR_ETGF6_EN_SHIFT   (31U)
 
#define SNVS_LPTGF1CR_ETGF6_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF6_EN_MASK)
 

LPTGF2CR - SNVS_LP Tamper Glitch Filter 2 Configuration Register

#define SNVS_LPTGF2CR_ETGF7_MASK   (0x7FU)
 
#define SNVS_LPTGF2CR_ETGF7_SHIFT   (0U)
 
#define SNVS_LPTGF2CR_ETGF7(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_SHIFT)) & SNVS_LPTGF2CR_ETGF7_MASK)
 
#define SNVS_LPTGF2CR_ETGF7_EN_MASK   (0x80U)
 
#define SNVS_LPTGF2CR_ETGF7_EN_SHIFT   (7U)
 
#define SNVS_LPTGF2CR_ETGF7_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK)
 
#define SNVS_LPTGF2CR_ETGF8_MASK   (0x7F00U)
 
#define SNVS_LPTGF2CR_ETGF8_SHIFT   (8U)
 
#define SNVS_LPTGF2CR_ETGF8(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_SHIFT)) & SNVS_LPTGF2CR_ETGF8_MASK)
 
#define SNVS_LPTGF2CR_ETGF8_EN_MASK   (0x8000U)
 
#define SNVS_LPTGF2CR_ETGF8_EN_SHIFT   (15U)
 
#define SNVS_LPTGF2CR_ETGF8_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK)
 
#define SNVS_LPTGF2CR_ETGF9_MASK   (0x7F0000U)
 
#define SNVS_LPTGF2CR_ETGF9_SHIFT   (16U)
 
#define SNVS_LPTGF2CR_ETGF9(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_SHIFT)) & SNVS_LPTGF2CR_ETGF9_MASK)
 
#define SNVS_LPTGF2CR_ETGF9_EN_MASK   (0x800000U)
 
#define SNVS_LPTGF2CR_ETGF9_EN_SHIFT   (23U)
 
#define SNVS_LPTGF2CR_ETGF9_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK)
 
#define SNVS_LPTGF2CR_ETGF10_MASK   (0x7F000000U)
 
#define SNVS_LPTGF2CR_ETGF10_SHIFT   (24U)
 
#define SNVS_LPTGF2CR_ETGF10(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_SHIFT)) & SNVS_LPTGF2CR_ETGF10_MASK)
 
#define SNVS_LPTGF2CR_ETGF10_EN_MASK   (0x80000000U)
 
#define SNVS_LPTGF2CR_ETGF10_EN_SHIFT   (31U)
 
#define SNVS_LPTGF2CR_ETGF10_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF10_EN_MASK)
 

LPATCR - SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register

#define SNVS_LPATCR_Seed_MASK   (0xFFFFU)
 
#define SNVS_LPATCR_Seed_SHIFT   (0U)
 
#define SNVS_LPATCR_Seed(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Seed_SHIFT)) & SNVS_LPATCR_Seed_MASK)
 
#define SNVS_LPATCR_Polynomial_MASK   (0xFFFF0000U)
 
#define SNVS_LPATCR_Polynomial_SHIFT   (16U)
 
#define SNVS_LPATCR_Polynomial(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Polynomial_SHIFT)) & SNVS_LPATCR_Polynomial_MASK)
 

LPATCTLR - SNVS_LP Active Tamper Control Register

#define SNVS_LPATCTLR_AT1_EN_MASK   (0x1U)
 
#define SNVS_LPATCTLR_AT1_EN_SHIFT   (0U)
 
#define SNVS_LPATCTLR_AT1_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_EN_SHIFT)) & SNVS_LPATCTLR_AT1_EN_MASK)
 
#define SNVS_LPATCTLR_AT2_EN_MASK   (0x2U)
 
#define SNVS_LPATCTLR_AT2_EN_SHIFT   (1U)
 
#define SNVS_LPATCTLR_AT2_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_EN_SHIFT)) & SNVS_LPATCTLR_AT2_EN_MASK)
 
#define SNVS_LPATCTLR_AT3_EN_MASK   (0x4U)
 
#define SNVS_LPATCTLR_AT3_EN_SHIFT   (2U)
 
#define SNVS_LPATCTLR_AT3_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_EN_SHIFT)) & SNVS_LPATCTLR_AT3_EN_MASK)
 
#define SNVS_LPATCTLR_AT4_EN_MASK   (0x8U)
 
#define SNVS_LPATCTLR_AT4_EN_SHIFT   (3U)
 
#define SNVS_LPATCTLR_AT4_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_EN_SHIFT)) & SNVS_LPATCTLR_AT4_EN_MASK)
 
#define SNVS_LPATCTLR_AT5_EN_MASK   (0x10U)
 
#define SNVS_LPATCTLR_AT5_EN_SHIFT   (4U)
 
#define SNVS_LPATCTLR_AT5_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_EN_SHIFT)) & SNVS_LPATCTLR_AT5_EN_MASK)
 
#define SNVS_LPATCTLR_AT1_PAD_EN_MASK   (0x10000U)
 
#define SNVS_LPATCTLR_AT1_PAD_EN_SHIFT   (16U)
 
#define SNVS_LPATCTLR_AT1_PAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT1_PAD_EN_MASK)
 
#define SNVS_LPATCTLR_AT2_PAD_EN_MASK   (0x20000U)
 
#define SNVS_LPATCTLR_AT2_PAD_EN_SHIFT   (17U)
 
#define SNVS_LPATCTLR_AT2_PAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT2_PAD_EN_MASK)
 
#define SNVS_LPATCTLR_AT3_PAD_EN_MASK   (0x40000U)
 
#define SNVS_LPATCTLR_AT3_PAD_EN_SHIFT   (18U)
 
#define SNVS_LPATCTLR_AT3_PAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT3_PAD_EN_MASK)
 
#define SNVS_LPATCTLR_AT4_PAD_EN_MASK   (0x80000U)
 
#define SNVS_LPATCTLR_AT4_PAD_EN_SHIFT   (19U)
 
#define SNVS_LPATCTLR_AT4_PAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT4_PAD_EN_MASK)
 
#define SNVS_LPATCTLR_AT5_PAD_EN_MASK   (0x100000U)
 
#define SNVS_LPATCTLR_AT5_PAD_EN_SHIFT   (20U)
 
#define SNVS_LPATCTLR_AT5_PAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT5_PAD_EN_MASK)
 

LPATCLKR - SNVS_LP Active Tamper Clock Control Register

#define SNVS_LPATCLKR_AT1_CLK_CTL_MASK   (0x3U)
 
#define SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT   (0U)
 
#define SNVS_LPATCLKR_AT1_CLK_CTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT1_CLK_CTL_MASK)
 
#define SNVS_LPATCLKR_AT2_CLK_CTL_MASK   (0x30U)
 
#define SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT   (4U)
 
#define SNVS_LPATCLKR_AT2_CLK_CTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT2_CLK_CTL_MASK)
 
#define SNVS_LPATCLKR_AT3_CLK_CTL_MASK   (0x300U)
 
#define SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT   (8U)
 
#define SNVS_LPATCLKR_AT3_CLK_CTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT3_CLK_CTL_MASK)
 
#define SNVS_LPATCLKR_AT4_CLK_CTL_MASK   (0x3000U)
 
#define SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT   (12U)
 
#define SNVS_LPATCLKR_AT4_CLK_CTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT4_CLK_CTL_MASK)
 
#define SNVS_LPATCLKR_AT5_CLK_CTL_MASK   (0x30000U)
 
#define SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT   (16U)
 
#define SNVS_LPATCLKR_AT5_CLK_CTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT5_CLK_CTL_MASK)
 

LPATRC1R - SNVS_LP Active Tamper Routing Control 1 Register

#define SNVS_LPATRC1R_ET1RCTL_MASK   (0x7U)
 
#define SNVS_LPATRC1R_ET1RCTL_SHIFT   (0U)
 
#define SNVS_LPATRC1R_ET1RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET1RCTL_SHIFT)) & SNVS_LPATRC1R_ET1RCTL_MASK)
 
#define SNVS_LPATRC1R_ET2RCTL_MASK   (0x70U)
 
#define SNVS_LPATRC1R_ET2RCTL_SHIFT   (4U)
 
#define SNVS_LPATRC1R_ET2RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET2RCTL_SHIFT)) & SNVS_LPATRC1R_ET2RCTL_MASK)
 
#define SNVS_LPATRC1R_ET3RCTL_MASK   (0x700U)
 
#define SNVS_LPATRC1R_ET3RCTL_SHIFT   (8U)
 
#define SNVS_LPATRC1R_ET3RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET3RCTL_SHIFT)) & SNVS_LPATRC1R_ET3RCTL_MASK)
 
#define SNVS_LPATRC1R_ET4RCTL_MASK   (0x7000U)
 
#define SNVS_LPATRC1R_ET4RCTL_SHIFT   (12U)
 
#define SNVS_LPATRC1R_ET4RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET4RCTL_SHIFT)) & SNVS_LPATRC1R_ET4RCTL_MASK)
 
#define SNVS_LPATRC1R_ET5RCTL_MASK   (0x70000U)
 
#define SNVS_LPATRC1R_ET5RCTL_SHIFT   (16U)
 
#define SNVS_LPATRC1R_ET5RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET5RCTL_SHIFT)) & SNVS_LPATRC1R_ET5RCTL_MASK)
 
#define SNVS_LPATRC1R_ET6RCTL_MASK   (0x700000U)
 
#define SNVS_LPATRC1R_ET6RCTL_SHIFT   (20U)
 
#define SNVS_LPATRC1R_ET6RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET6RCTL_SHIFT)) & SNVS_LPATRC1R_ET6RCTL_MASK)
 
#define SNVS_LPATRC1R_ET7RCTL_MASK   (0x7000000U)
 
#define SNVS_LPATRC1R_ET7RCTL_SHIFT   (24U)
 
#define SNVS_LPATRC1R_ET7RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET7RCTL_SHIFT)) & SNVS_LPATRC1R_ET7RCTL_MASK)
 
#define SNVS_LPATRC1R_ET8RCTL_MASK   (0x70000000U)
 
#define SNVS_LPATRC1R_ET8RCTL_SHIFT   (28U)
 
#define SNVS_LPATRC1R_ET8RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET8RCTL_SHIFT)) & SNVS_LPATRC1R_ET8RCTL_MASK)
 

LPATRC2R - SNVS_LP Active Tamper Routing Control 2 Register

#define SNVS_LPATRC2R_ET9RCTL_MASK   (0x7U)
 
#define SNVS_LPATRC2R_ET9RCTL_SHIFT   (0U)
 
#define SNVS_LPATRC2R_ET9RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET9RCTL_SHIFT)) & SNVS_LPATRC2R_ET9RCTL_MASK)
 
#define SNVS_LPATRC2R_ET10RCTL_MASK   (0x70U)
 
#define SNVS_LPATRC2R_ET10RCTL_SHIFT   (4U)
 
#define SNVS_LPATRC2R_ET10RCTL(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET10RCTL_SHIFT)) & SNVS_LPATRC2R_ET10RCTL_MASK)
 

LPGPR - SNVS_LP General Purpose Registers 0 .. 3

#define SNVS_LPGPR_GPR_MASK   (0xFFFFFFFFU)
 
#define SNVS_LPGPR_GPR_SHIFT   (0U)
 
#define SNVS_LPGPR_GPR(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
 

HPVIDR1 - SNVS_HP Version ID Register 1

#define SNVS_HPVIDR1_MINOR_REV_MASK   (0xFFU)
 
#define SNVS_HPVIDR1_MINOR_REV_SHIFT   (0U)
 
#define SNVS_HPVIDR1_MINOR_REV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
 
#define SNVS_HPVIDR1_MAJOR_REV_MASK   (0xFF00U)
 
#define SNVS_HPVIDR1_MAJOR_REV_SHIFT   (8U)
 
#define SNVS_HPVIDR1_MAJOR_REV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
 
#define SNVS_HPVIDR1_IP_ID_MASK   (0xFFFF0000U)
 
#define SNVS_HPVIDR1_IP_ID_SHIFT   (16U)
 
#define SNVS_HPVIDR1_IP_ID(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
 

HPVIDR2 - SNVS_HP Version ID Register 2

#define SNVS_HPVIDR2_ECO_REV_MASK   (0xFF00U)
 
#define SNVS_HPVIDR2_ECO_REV_SHIFT   (8U)
 
#define SNVS_HPVIDR2_ECO_REV(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
 
#define SNVS_HPVIDR2_IP_ERA_MASK   (0xFF000000U)
 
#define SNVS_HPVIDR2_IP_ERA_SHIFT   (24U)
 
#define SNVS_HPVIDR2_IP_ERA(x)   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
 

Detailed Description

Macro Definition Documentation

◆ SNVS_HPCOMR_HAC_CLEAR [1/3]

#define SNVS_HPCOMR_HAC_CLEAR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)

HAC_CLEAR 0b0..No Action 0b1..Clear the HAC

◆ SNVS_HPCOMR_HAC_CLEAR [2/3]

#define SNVS_HPCOMR_HAC_CLEAR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)

HAC_CLEAR 0b0..No Action 0b1..Clear the HAC

◆ SNVS_HPCOMR_HAC_CLEAR [3/3]

#define SNVS_HPCOMR_HAC_CLEAR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)

HAC_CLEAR 0b0..No Action 0b1..Clear the HAC

◆ SNVS_HPCOMR_HAC_EN [1/3]

#define SNVS_HPCOMR_HAC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)

HAC_EN 0b0..High Assurance Counter is disabled 0b1..High Assurance Counter is enabled

◆ SNVS_HPCOMR_HAC_EN [2/3]

#define SNVS_HPCOMR_HAC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)

HAC_EN 0b0..High Assurance Counter is disabled 0b1..High Assurance Counter is enabled

◆ SNVS_HPCOMR_HAC_EN [3/3]

#define SNVS_HPCOMR_HAC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)

HAC_EN 0b0..High Assurance Counter is disabled 0b1..High Assurance Counter is enabled

◆ SNVS_HPCOMR_HAC_LOAD [1/3]

#define SNVS_HPCOMR_HAC_LOAD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)

HAC_LOAD 0b0..No Action 0b1..Load the HAC

◆ SNVS_HPCOMR_HAC_LOAD [2/3]

#define SNVS_HPCOMR_HAC_LOAD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)

HAC_LOAD 0b0..No Action 0b1..Load the HAC

◆ SNVS_HPCOMR_HAC_LOAD [3/3]

#define SNVS_HPCOMR_HAC_LOAD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)

HAC_LOAD 0b0..No Action 0b1..Load the HAC

◆ SNVS_HPCOMR_LP_SWR [1/3]

#define SNVS_HPCOMR_LP_SWR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)

LP_SWR 0b0..No Action 0b1..Reset LP section

◆ SNVS_HPCOMR_LP_SWR [2/3]

#define SNVS_HPCOMR_LP_SWR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)

LP_SWR 0b0..No Action 0b1..Reset LP section

◆ SNVS_HPCOMR_LP_SWR [3/3]

#define SNVS_HPCOMR_LP_SWR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)

LP_SWR 0b0..No Action 0b1..Reset LP section

◆ SNVS_HPCOMR_LP_SWR_DIS [1/3]

#define SNVS_HPCOMR_LP_SWR_DIS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)

LP_SWR_DIS 0b0..LP software reset is enabled 0b1..LP software reset is disabled

◆ SNVS_HPCOMR_LP_SWR_DIS [2/3]

#define SNVS_HPCOMR_LP_SWR_DIS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)

LP_SWR_DIS 0b0..LP software reset is enabled 0b1..LP software reset is disabled

◆ SNVS_HPCOMR_LP_SWR_DIS [3/3]

#define SNVS_HPCOMR_LP_SWR_DIS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)

LP_SWR_DIS 0b0..LP software reset is enabled 0b1..LP software reset is disabled

◆ SNVS_HPCOMR_MKS_EN [1/3]

#define SNVS_HPCOMR_MKS_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)

MKS_EN 0b0..OTP master key is selected as an SNVS master key 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR

◆ SNVS_HPCOMR_MKS_EN [2/3]

#define SNVS_HPCOMR_MKS_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)

MKS_EN 0b0..OTP master key is selected as an SNVS master key 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR

◆ SNVS_HPCOMR_MKS_EN [3/3]

#define SNVS_HPCOMR_MKS_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)

MKS_EN 0b0..OTP master key is selected as an SNVS master key 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR

◆ SNVS_HPCOMR_PROG_ZMK [1/3]

#define SNVS_HPCOMR_PROG_ZMK (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)

PROG_ZMK 0b0..No Action 0b1..Activate hardware key programming mechanism

◆ SNVS_HPCOMR_PROG_ZMK [2/3]

#define SNVS_HPCOMR_PROG_ZMK (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)

PROG_ZMK 0b0..No Action 0b1..Activate hardware key programming mechanism

◆ SNVS_HPCOMR_PROG_ZMK [3/3]

#define SNVS_HPCOMR_PROG_ZMK (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)

PROG_ZMK 0b0..No Action 0b1..Activate hardware key programming mechanism

◆ SNVS_HPCOMR_SSM_SFNS_DIS [1/3]

#define SNVS_HPCOMR_SSM_SFNS_DIS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)

SSM_SFNS_DIS 0b0..Soft Fail to Non-Secure State transition is enabled 0b1..Soft Fail to Non-Secure State transition is disabled

◆ SNVS_HPCOMR_SSM_SFNS_DIS [2/3]

#define SNVS_HPCOMR_SSM_SFNS_DIS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)

SSM_SFNS_DIS 0b0..Soft Fail to Non-Secure State transition is enabled 0b1..Soft Fail to Non-Secure State transition is disabled

◆ SNVS_HPCOMR_SSM_SFNS_DIS [3/3]

#define SNVS_HPCOMR_SSM_SFNS_DIS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)

SSM_SFNS_DIS 0b0..Soft Fail to Non-Secure State transition is enabled 0b1..Soft Fail to Non-Secure State transition is disabled

◆ SNVS_HPCOMR_SSM_ST_DIS [1/3]

#define SNVS_HPCOMR_SSM_ST_DIS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)

SSM_ST_DIS 0b0..Secure to Trusted State transition is enabled 0b1..Secure to Trusted State transition is disabled

◆ SNVS_HPCOMR_SSM_ST_DIS [2/3]

#define SNVS_HPCOMR_SSM_ST_DIS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)

SSM_ST_DIS 0b0..Secure to Trusted State transition is enabled 0b1..Secure to Trusted State transition is disabled

◆ SNVS_HPCOMR_SSM_ST_DIS [3/3]

#define SNVS_HPCOMR_SSM_ST_DIS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)

SSM_ST_DIS 0b0..Secure to Trusted State transition is enabled 0b1..Secure to Trusted State transition is disabled

◆ SNVS_HPCR_DIS_PI [1/3]

#define SNVS_HPCR_DIS_PI (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)

DIS_PI 0b0..Periodic interrupt will trigger a functional interrupt 0b1..Disable periodic interrupt in the function interrupt

◆ SNVS_HPCR_DIS_PI [2/3]

#define SNVS_HPCR_DIS_PI (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)

DIS_PI 0b0..Periodic interrupt will trigger a functional interrupt 0b1..Disable periodic interrupt in the function interrupt

◆ SNVS_HPCR_DIS_PI [3/3]

#define SNVS_HPCR_DIS_PI (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)

DIS_PI 0b0..Periodic interrupt will trigger a functional interrupt 0b1..Disable periodic interrupt in the function interrupt

◆ SNVS_HPCR_HP_TS [1/3]

#define SNVS_HPCR_HP_TS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)

HP_TS 0b0..No Action 0b1..Synchronize the HP Time Counter to the LP Time Counter

◆ SNVS_HPCR_HP_TS [2/3]

#define SNVS_HPCR_HP_TS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)

HP_TS 0b0..No Action 0b1..Synchronize the HP Time Counter to the LP Time Counter

◆ SNVS_HPCR_HP_TS [3/3]

#define SNVS_HPCR_HP_TS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)

HP_TS 0b0..No Action 0b1..Synchronize the HP Time Counter to the LP Time Counter

◆ SNVS_HPCR_HPCALB_EN [1/3]

#define SNVS_HPCR_HPCALB_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)

HPCALB_EN 0b0..HP Timer calibration disabled 0b1..HP Timer calibration enabled

◆ SNVS_HPCR_HPCALB_EN [2/3]

#define SNVS_HPCR_HPCALB_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)

HPCALB_EN 0b0..HP Timer calibration disabled 0b1..HP Timer calibration enabled

◆ SNVS_HPCR_HPCALB_EN [3/3]

#define SNVS_HPCR_HPCALB_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)

HPCALB_EN 0b0..HP Timer calibration disabled 0b1..HP Timer calibration enabled

◆ SNVS_HPCR_HPCALB_VAL [1/3]

#define SNVS_HPCR_HPCALB_VAL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)

HPCALB_VAL 0b00000..+0 counts per each 32768 ticks of the counter 0b00001..+1 counts per each 32768 ticks of the counter 0b00010..+2 counts per each 32768 ticks of the counter 0b01111..+15 counts per each 32768 ticks of the counter 0b10000..-16 counts per each 32768 ticks of the counter 0b10001..-15 counts per each 32768 ticks of the counter 0b11110..-2 counts per each 32768 ticks of the counter 0b11111..-1 counts per each 32768 ticks of the counter

◆ SNVS_HPCR_HPCALB_VAL [2/3]

#define SNVS_HPCR_HPCALB_VAL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)

HPCALB_VAL 0b00000..+0 counts per each 32768 ticks of the counter 0b00001..+1 counts per each 32768 ticks of the counter 0b00010..+2 counts per each 32768 ticks of the counter 0b01111..+15 counts per each 32768 ticks of the counter 0b10000..-16 counts per each 32768 ticks of the counter 0b10001..-15 counts per each 32768 ticks of the counter 0b11110..-2 counts per each 32768 ticks of the counter 0b11111..-1 counts per each 32768 ticks of the counter

◆ SNVS_HPCR_HPCALB_VAL [3/3]

#define SNVS_HPCR_HPCALB_VAL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)

HPCALB_VAL 0b00000..+0 counts per each 32768 ticks of the counter 0b00001..+1 counts per each 32768 ticks of the counter 0b00010..+2 counts per each 32768 ticks of the counter 0b01111..+15 counts per each 32768 ticks of the counter 0b10000..-16 counts per each 32768 ticks of the counter 0b10001..-15 counts per each 32768 ticks of the counter 0b11110..-2 counts per each 32768 ticks of the counter 0b11111..-1 counts per each 32768 ticks of the counter

◆ SNVS_HPCR_HPTA_EN [1/3]

#define SNVS_HPCR_HPTA_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)

HPTA_EN 0b0..HP Time Alarm Interrupt is disabled 0b1..HP Time Alarm Interrupt is enabled

◆ SNVS_HPCR_HPTA_EN [2/3]

#define SNVS_HPCR_HPTA_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)

HPTA_EN 0b0..HP Time Alarm Interrupt is disabled 0b1..HP Time Alarm Interrupt is enabled

◆ SNVS_HPCR_HPTA_EN [3/3]

#define SNVS_HPCR_HPTA_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)

HPTA_EN 0b0..HP Time Alarm Interrupt is disabled 0b1..HP Time Alarm Interrupt is enabled

◆ SNVS_HPCR_PI_EN [1/3]

#define SNVS_HPCR_PI_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)

PI_EN 0b0..HP Periodic Interrupt is disabled 0b1..HP Periodic Interrupt is enabled

◆ SNVS_HPCR_PI_EN [2/3]

#define SNVS_HPCR_PI_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)

PI_EN 0b0..HP Periodic Interrupt is disabled 0b1..HP Periodic Interrupt is enabled

◆ SNVS_HPCR_PI_EN [3/3]

#define SNVS_HPCR_PI_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)

PI_EN 0b0..HP Periodic Interrupt is disabled 0b1..HP Periodic Interrupt is enabled

◆ SNVS_HPCR_PI_FREQ [1/3]

#define SNVS_HPCR_PI_FREQ (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)

PI_FREQ 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt

◆ SNVS_HPCR_PI_FREQ [2/3]

#define SNVS_HPCR_PI_FREQ (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)

PI_FREQ 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt

◆ SNVS_HPCR_PI_FREQ [3/3]

#define SNVS_HPCR_PI_FREQ (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)

PI_FREQ 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt

◆ SNVS_HPCR_RTC_EN [1/3]

#define SNVS_HPCR_RTC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)

RTC_EN 0b0..RTC is disabled 0b1..RTC is enabled

◆ SNVS_HPCR_RTC_EN [2/3]

#define SNVS_HPCR_RTC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)

RTC_EN 0b0..RTC is disabled 0b1..RTC is enabled

◆ SNVS_HPCR_RTC_EN [3/3]

#define SNVS_HPCR_RTC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)

RTC_EN 0b0..RTC is disabled 0b1..RTC is enabled

◆ SNVS_HPLR_AT1_SL [1/2]

#define SNVS_HPLR_AT1_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT1_SL_SHIFT)) & SNVS_HPLR_AT1_SL_MASK)

AT1_SL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_HPLR_AT1_SL [2/2]

#define SNVS_HPLR_AT1_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT1_SL_SHIFT)) & SNVS_HPLR_AT1_SL_MASK)

AT1_SL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_HPLR_AT2_SL [1/2]

#define SNVS_HPLR_AT2_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT2_SL_SHIFT)) & SNVS_HPLR_AT2_SL_MASK)

AT2_SL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_HPLR_AT2_SL [2/2]

#define SNVS_HPLR_AT2_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT2_SL_SHIFT)) & SNVS_HPLR_AT2_SL_MASK)

AT2_SL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_HPLR_AT3_SL [1/2]

#define SNVS_HPLR_AT3_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT3_SL_SHIFT)) & SNVS_HPLR_AT3_SL_MASK)

AT3_SL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_HPLR_AT3_SL [2/2]

#define SNVS_HPLR_AT3_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT3_SL_SHIFT)) & SNVS_HPLR_AT3_SL_MASK)

AT3_SL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_HPLR_AT4_SL [1/2]

#define SNVS_HPLR_AT4_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT4_SL_SHIFT)) & SNVS_HPLR_AT4_SL_MASK)

AT4_SL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_HPLR_AT4_SL [2/2]

#define SNVS_HPLR_AT4_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT4_SL_SHIFT)) & SNVS_HPLR_AT4_SL_MASK)

AT4_SL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_HPLR_AT5_SL [1/2]

#define SNVS_HPLR_AT5_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT5_SL_SHIFT)) & SNVS_HPLR_AT5_SL_MASK)

AT5_SL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_HPLR_AT5_SL [2/2]

#define SNVS_HPLR_AT5_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT5_SL_SHIFT)) & SNVS_HPLR_AT5_SL_MASK)

AT5_SL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_HPLR_GPR_SL [1/3]

#define SNVS_HPLR_GPR_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)

GPR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_GPR_SL [2/3]

#define SNVS_HPLR_GPR_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)

GPR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_GPR_SL [3/3]

#define SNVS_HPLR_GPR_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)

GPR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_HAC_L [1/3]

#define SNVS_HPLR_HAC_L (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)

HAC_L 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_HAC_L [2/3]

#define SNVS_HPLR_HAC_L (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)

HAC_L 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_HAC_L [3/3]

#define SNVS_HPLR_HAC_L (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)

HAC_L 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_HPSICR_L [1/3]

#define SNVS_HPLR_HPSICR_L (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)

HPSICR_L 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_HPSICR_L [2/3]

#define SNVS_HPLR_HPSICR_L (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)

HPSICR_L 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_HPSICR_L [3/3]

#define SNVS_HPLR_HPSICR_L (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)

HPSICR_L 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_HPSVCR_L [1/3]

#define SNVS_HPLR_HPSVCR_L (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)

HPSVCR_L 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_HPSVCR_L [2/3]

#define SNVS_HPLR_HPSVCR_L (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)

HPSVCR_L 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_HPSVCR_L [3/3]

#define SNVS_HPLR_HPSVCR_L (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)

HPSVCR_L 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_LPCALB_SL [1/3]

#define SNVS_HPLR_LPCALB_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)

LPCALB_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_LPCALB_SL [2/3]

#define SNVS_HPLR_LPCALB_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)

LPCALB_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_LPCALB_SL [3/3]

#define SNVS_HPLR_LPCALB_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)

LPCALB_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_LPSECR_SL [1/3]

#define SNVS_HPLR_LPSECR_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)

LPSECR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_LPSECR_SL [2/3]

#define SNVS_HPLR_LPSECR_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)

LPSECR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_LPSECR_SL [3/3]

#define SNVS_HPLR_LPSECR_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)

LPSECR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_LPSVCR_SL [1/3]

#define SNVS_HPLR_LPSVCR_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)

LPSVCR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_LPSVCR_SL [2/3]

#define SNVS_HPLR_LPSVCR_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)

LPSVCR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_LPSVCR_SL [3/3]

#define SNVS_HPLR_LPSVCR_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)

LPSVCR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_LPTGFCR_SL [1/2]

#define SNVS_HPLR_LPTGFCR_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK)

LPTGFCR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_LPTGFCR_SL [2/2]

#define SNVS_HPLR_LPTGFCR_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK)

LPTGFCR_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_MC_SL [1/3]

#define SNVS_HPLR_MC_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)

MC_SL 0b0..Write access (increment) is allowed 0b1..Write access (increment) is not allowed

◆ SNVS_HPLR_MC_SL [2/3]

#define SNVS_HPLR_MC_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)

MC_SL 0b0..Write access (increment) is allowed 0b1..Write access (increment) is not allowed

◆ SNVS_HPLR_MC_SL [3/3]

#define SNVS_HPLR_MC_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)

MC_SL 0b0..Write access (increment) is allowed 0b1..Write access (increment) is not allowed

◆ SNVS_HPLR_MKS_SL [1/3]

#define SNVS_HPLR_MKS_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)

MKS_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_MKS_SL [2/3]

#define SNVS_HPLR_MKS_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)

MKS_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_MKS_SL [3/3]

#define SNVS_HPLR_MKS_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)

MKS_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_SRTC_SL [1/3]

#define SNVS_HPLR_SRTC_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)

SRTC_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_SRTC_SL [2/3]

#define SNVS_HPLR_SRTC_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)

SRTC_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_SRTC_SL [3/3]

#define SNVS_HPLR_SRTC_SL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)

SRTC_SL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_ZMK_RSL [1/3]

#define SNVS_HPLR_ZMK_RSL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)

ZMK_RSL 0b0..Read access is allowed (only in software Programming mode) 0b1..Read access is not allowed

◆ SNVS_HPLR_ZMK_RSL [2/3]

#define SNVS_HPLR_ZMK_RSL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)

ZMK_RSL 0b0..Read access is allowed (only in software Programming mode) 0b1..Read access is not allowed

◆ SNVS_HPLR_ZMK_RSL [3/3]

#define SNVS_HPLR_ZMK_RSL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)

ZMK_RSL 0b0..Read access is allowed (only in software Programming mode) 0b1..Read access is not allowed

◆ SNVS_HPLR_ZMK_WSL [1/3]

#define SNVS_HPLR_ZMK_WSL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)

ZMK_WSL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_ZMK_WSL [2/3]

#define SNVS_HPLR_ZMK_WSL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)

ZMK_WSL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPLR_ZMK_WSL [3/3]

#define SNVS_HPLR_ZMK_WSL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)

ZMK_WSL 0b0..Write access is allowed 0b1..Write access is not allowed

◆ SNVS_HPSICR_CAAM_EN [1/2]

#define SNVS_HPSICR_CAAM_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_CAAM_EN_SHIFT)) & SNVS_HPSICR_CAAM_EN_MASK)

CAAM_EN 0b0..CAAM Security Violation Interrupt is Disabled 0b1..CAAM Security Violation Interrupt is Enabled

◆ SNVS_HPSICR_CAAM_EN [2/2]

#define SNVS_HPSICR_CAAM_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_CAAM_EN_SHIFT)) & SNVS_HPSICR_CAAM_EN_MASK)

CAAM_EN 0b0..CAAM Security Violation Interrupt is Disabled 0b1..CAAM Security Violation Interrupt is Enabled

◆ SNVS_HPSICR_JTAGC_EN [1/2]

#define SNVS_HPSICR_JTAGC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_JTAGC_EN_SHIFT)) & SNVS_HPSICR_JTAGC_EN_MASK)

JTAGC_EN 0b0..JTAG Active Interrupt is Disabled 0b1..JTAG Active Interrupt is Enabled

◆ SNVS_HPSICR_JTAGC_EN [2/2]

#define SNVS_HPSICR_JTAGC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_JTAGC_EN_SHIFT)) & SNVS_HPSICR_JTAGC_EN_MASK)

JTAGC_EN 0b0..JTAG Active Interrupt is Disabled 0b1..JTAG Active Interrupt is Enabled

◆ SNVS_HPSICR_LPSVI_EN [1/3]

#define SNVS_HPSICR_LPSVI_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)

LPSVI_EN 0b0..LP Security Violation Interrupt is Disabled 0b1..LP Security Violation Interrupt is Enabled

◆ SNVS_HPSICR_LPSVI_EN [2/3]

#define SNVS_HPSICR_LPSVI_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)

LPSVI_EN 0b0..LP Security Violation Interrupt is Disabled 0b1..LP Security Violation Interrupt is Enabled

◆ SNVS_HPSICR_LPSVI_EN [3/3]

#define SNVS_HPSICR_LPSVI_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)

LPSVI_EN 0b0..LP Security Violation Interrupt is Disabled 0b1..LP Security Violation Interrupt is Enabled

◆ SNVS_HPSICR_OCOTP_EN [1/2]

#define SNVS_HPSICR_OCOTP_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_OCOTP_EN_SHIFT)) & SNVS_HPSICR_OCOTP_EN_MASK)

OCOTP_EN 0b0..OCOTP attack error Interrupt is Disabled 0b1..OCOTP attack error Interrupt is Enabled

◆ SNVS_HPSICR_OCOTP_EN [2/2]

#define SNVS_HPSICR_OCOTP_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_OCOTP_EN_SHIFT)) & SNVS_HPSICR_OCOTP_EN_MASK)

OCOTP_EN 0b0..OCOTP attack error Interrupt is Disabled 0b1..OCOTP attack error Interrupt is Enabled

◆ SNVS_HPSICR_SRC_EN [1/2]

#define SNVS_HPSICR_SRC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SRC_EN_SHIFT)) & SNVS_HPSICR_SRC_EN_MASK)

SRC_EN 0b0..Internal Boot Interrupt is Disabled 0b1..Internal Boot Interrupt is Enabled

◆ SNVS_HPSICR_SRC_EN [2/2]

#define SNVS_HPSICR_SRC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SRC_EN_SHIFT)) & SNVS_HPSICR_SRC_EN_MASK)

SRC_EN 0b0..Internal Boot Interrupt is Disabled 0b1..Internal Boot Interrupt is Enabled

◆ SNVS_HPSICR_SV0_EN

#define SNVS_HPSICR_SV0_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)

SV0_EN 0b0..Security Violation 0 Interrupt is Disabled 0b1..Security Violation 0 Interrupt is Enabled

◆ SNVS_HPSICR_SV1_EN

#define SNVS_HPSICR_SV1_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)

SV1_EN 0b0..Security Violation 1 Interrupt is Disabled 0b1..Security Violation 1 Interrupt is Enabled

◆ SNVS_HPSICR_SV2_EN

#define SNVS_HPSICR_SV2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)

SV2_EN 0b0..Security Violation 2 Interrupt is Disabled 0b1..Security Violation 2 Interrupt is Enabled

◆ SNVS_HPSICR_SV3_EN

#define SNVS_HPSICR_SV3_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)

SV3_EN 0b0..Security Violation 3 Interrupt is Disabled 0b1..Security Violation 3 Interrupt is Enabled

◆ SNVS_HPSICR_SV4_EN

#define SNVS_HPSICR_SV4_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)

SV4_EN 0b0..Security Violation 4 Interrupt is Disabled 0b1..Security Violation 4 Interrupt is Enabled

◆ SNVS_HPSICR_SV5_EN

#define SNVS_HPSICR_SV5_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)

SV5_EN 0b0..Security Violation 5 Interrupt is Disabled 0b1..Security Violation 5 Interrupt is Enabled

◆ SNVS_HPSICR_WDOG2_EN [1/2]

#define SNVS_HPSICR_WDOG2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_WDOG2_EN_SHIFT)) & SNVS_HPSICR_WDOG2_EN_MASK)

WDOG2_EN 0b0..Watchdog 2 Reset Interrupt is Disabled 0b1..Watchdog 2 Reset Interrupt is Enabled

◆ SNVS_HPSICR_WDOG2_EN [2/2]

#define SNVS_HPSICR_WDOG2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_WDOG2_EN_SHIFT)) & SNVS_HPSICR_WDOG2_EN_MASK)

WDOG2_EN 0b0..Watchdog 2 Reset Interrupt is Disabled 0b1..Watchdog 2 Reset Interrupt is Enabled

◆ SNVS_HPSR_HPTA [1/3]

#define SNVS_HPSR_HPTA (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)

HPTA 0b0..No time alarm interrupt occurred. 0b1..A time alarm interrupt occurred.

◆ SNVS_HPSR_HPTA [2/3]

#define SNVS_HPSR_HPTA (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)

HPTA 0b0..No time alarm interrupt occurred. 0b1..A time alarm interrupt occurred.

◆ SNVS_HPSR_HPTA [3/3]

#define SNVS_HPSR_HPTA (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)

HPTA 0b0..No time alarm interrupt occurred. 0b1..A time alarm interrupt occurred.

◆ SNVS_HPSR_OTPMK_ZERO [1/3]

#define SNVS_HPSR_OTPMK_ZERO (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)

OTPMK_ZERO 0b0..The OTPMK is not zero. 0b1..The OTPMK is zero.

◆ SNVS_HPSR_OTPMK_ZERO [2/3]

#define SNVS_HPSR_OTPMK_ZERO (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)

OTPMK_ZERO 0b0..The OTPMK is not zero. 0b1..The OTPMK is zero.

◆ SNVS_HPSR_OTPMK_ZERO [3/3]

#define SNVS_HPSR_OTPMK_ZERO (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)

OTPMK_ZERO 0b0..The OTPMK is not zero. 0b1..The OTPMK is zero.

◆ SNVS_HPSR_PI [1/3]

#define SNVS_HPSR_PI (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)

PI 0b0..No periodic interrupt occurred. 0b1..A periodic interrupt occurred.

◆ SNVS_HPSR_PI [2/3]

#define SNVS_HPSR_PI (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)

PI 0b0..No periodic interrupt occurred. 0b1..A periodic interrupt occurred.

◆ SNVS_HPSR_PI [3/3]

#define SNVS_HPSR_PI (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)

PI 0b0..No periodic interrupt occurred. 0b1..A periodic interrupt occurred.

◆ SNVS_HPSR_SSM_STATE [1/3]

#define SNVS_HPSR_SSM_STATE (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)

SSM_STATE 0b0000..Init 0b0001..Hard Fail 0b0011..Soft Fail 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) 0b1001..Check 0b1011..Non-Secure 0b1101..Trusted 0b1111..Secure

◆ SNVS_HPSR_SSM_STATE [2/3]

#define SNVS_HPSR_SSM_STATE (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)

SSM_STATE 0b0000..Init 0b0001..Hard Fail 0b0011..Soft Fail 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) 0b1001..Check 0b1011..Non-Secure 0b1101..Trusted 0b1111..Secure

◆ SNVS_HPSR_SSM_STATE [3/3]

#define SNVS_HPSR_SSM_STATE (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)

SSM_STATE 0b0000..Init 0b0001..Hard Fail 0b0011..Soft Fail 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) 0b1001..Check 0b1011..Non-Secure 0b1101..Trusted 0b1111..Secure

◆ SNVS_HPSR_SYS_SECURITY_CFG [1/3]

#define SNVS_HPSR_SYS_SECURITY_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)

SYS_SECURITY_CFG 0b000..Fab Configuration - the default configuration of newly fabricated chips 0b001..Open Configuration - the configuration after NXP-programmable fuses have been blown 0b011..Closed Configuration - the configuration after OEM-programmable fuses have been blown 0b111..Field Return Configuration - the configuration of chips that are returned to NXP for analysis

◆ SNVS_HPSR_SYS_SECURITY_CFG [2/3]

#define SNVS_HPSR_SYS_SECURITY_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)

SYS_SECURITY_CFG 0b000..Fab Configuration - the default configuration of newly fabricated chips 0b001..Open Configuration - the configuration after NXP-programmable fuses have been blown 0b011..Closed Configuration - the configuration after OEM-programmable fuses have been blown 0b111..Field Return Configuration - the configuration of chips that are returned to NXP for analysis

◆ SNVS_HPSR_SYS_SECURITY_CFG [3/3]

#define SNVS_HPSR_SYS_SECURITY_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)

SYS_SECURITY_CFG 0b000..Fab Configuration - the default configuration of newly fabricated chips 0b001..Open Configuration - the configuration after NXP-programmable fuses have been blown 0b011..Closed Configuration - the configuration after OEM-programmable fuses have been blown 0b111..Field Return Configuration - the configuration of chips that are returned to NXP for analysis

◆ SNVS_HPSR_ZMK_ZERO [1/3]

#define SNVS_HPSR_ZMK_ZERO (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)

ZMK_ZERO 0b0..The ZMK is not zero. 0b1..The ZMK is zero.

◆ SNVS_HPSR_ZMK_ZERO [2/3]

#define SNVS_HPSR_ZMK_ZERO (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)

ZMK_ZERO 0b0..The ZMK is not zero. 0b1..The ZMK is zero.

◆ SNVS_HPSR_ZMK_ZERO [3/3]

#define SNVS_HPSR_ZMK_ZERO (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)

ZMK_ZERO 0b0..The ZMK is not zero. 0b1..The ZMK is zero.

◆ SNVS_HPSVCR_CAAM_CFG [1/2]

#define SNVS_HPSVCR_CAAM_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_CAAM_CFG_SHIFT)) & SNVS_HPSVCR_CAAM_CFG_MASK)

CAAM_CFG 0b0..CAAM Security Violation is a non-fatal violation 0b1..CAAM Security Violation is a fatal violation

◆ SNVS_HPSVCR_CAAM_CFG [2/2]

#define SNVS_HPSVCR_CAAM_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_CAAM_CFG_SHIFT)) & SNVS_HPSVCR_CAAM_CFG_MASK)

CAAM_CFG 0b0..CAAM Security Violation is a non-fatal violation 0b1..CAAM Security Violation is a fatal violation

◆ SNVS_HPSVCR_JTAGC_CFG [1/2]

#define SNVS_HPSVCR_JTAGC_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_JTAGC_CFG_SHIFT)) & SNVS_HPSVCR_JTAGC_CFG_MASK)

JTAGC_CFG 0b0..JTAG Active is a non-fatal violation 0b1..JTAG Active is a fatal violation

◆ SNVS_HPSVCR_JTAGC_CFG [2/2]

#define SNVS_HPSVCR_JTAGC_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_JTAGC_CFG_SHIFT)) & SNVS_HPSVCR_JTAGC_CFG_MASK)

JTAGC_CFG 0b0..JTAG Active is a non-fatal violation 0b1..JTAG Active is a fatal violation

◆ SNVS_HPSVCR_LPSV_CFG [1/3]

#define SNVS_HPSVCR_LPSV_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)

LPSV_CFG 0b00..LP security violation is disabled 0b01..LP security violation is a non-fatal violation 0b1x..LP security violation is a fatal violation

◆ SNVS_HPSVCR_LPSV_CFG [2/3]

#define SNVS_HPSVCR_LPSV_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)

LPSV_CFG 0b00..LP security violation is disabled 0b01..LP security violation is a non-fatal violation 0b1x..LP security violation is a fatal violation

◆ SNVS_HPSVCR_LPSV_CFG [3/3]

#define SNVS_HPSVCR_LPSV_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)

LPSV_CFG 0b00..LP security violation is disabled 0b01..LP security violation is a non-fatal violation 0b1x..LP security violation is a fatal violation

◆ SNVS_HPSVCR_OCOTP_CFG [1/2]

#define SNVS_HPSVCR_OCOTP_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_OCOTP_CFG_SHIFT)) & SNVS_HPSVCR_OCOTP_CFG_MASK)

OCOTP_CFG 0b00..OCOTP attack error is disabled 0b01..OCOTP attack error is a non-fatal violation 0b1x..OCOTP attack error is a fatal violation

◆ SNVS_HPSVCR_OCOTP_CFG [2/2]

#define SNVS_HPSVCR_OCOTP_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_OCOTP_CFG_SHIFT)) & SNVS_HPSVCR_OCOTP_CFG_MASK)

OCOTP_CFG 0b00..OCOTP attack error is disabled 0b01..OCOTP attack error is a non-fatal violation 0b1x..OCOTP attack error is a fatal violation

◆ SNVS_HPSVCR_SRC_CFG [1/2]

#define SNVS_HPSVCR_SRC_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SRC_CFG_SHIFT)) & SNVS_HPSVCR_SRC_CFG_MASK)

SRC_CFG 0b0..Internal Boot is a non-fatal violation 0b1..Internal Boot is a fatal violation

◆ SNVS_HPSVCR_SRC_CFG [2/2]

#define SNVS_HPSVCR_SRC_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SRC_CFG_SHIFT)) & SNVS_HPSVCR_SRC_CFG_MASK)

SRC_CFG 0b0..Internal Boot is a non-fatal violation 0b1..Internal Boot is a fatal violation

◆ SNVS_HPSVCR_SV0_CFG

#define SNVS_HPSVCR_SV0_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)

SV0_CFG 0b0..Security Violation 0 is a non-fatal violation 0b1..Security Violation 0 is a fatal violation

◆ SNVS_HPSVCR_SV1_CFG

#define SNVS_HPSVCR_SV1_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)

SV1_CFG 0b0..Security Violation 1 is a non-fatal violation 0b1..Security Violation 1 is a fatal violation

◆ SNVS_HPSVCR_SV2_CFG

#define SNVS_HPSVCR_SV2_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)

SV2_CFG 0b0..Security Violation 2 is a non-fatal violation 0b1..Security Violation 2 is a fatal violation

◆ SNVS_HPSVCR_SV3_CFG

#define SNVS_HPSVCR_SV3_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)

SV3_CFG 0b0..Security Violation 3 is a non-fatal violation 0b1..Security Violation 3 is a fatal violation

◆ SNVS_HPSVCR_SV4_CFG

#define SNVS_HPSVCR_SV4_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)

SV4_CFG 0b0..Security Violation 4 is a non-fatal violation 0b1..Security Violation 4 is a fatal violation

◆ SNVS_HPSVCR_SV5_CFG

#define SNVS_HPSVCR_SV5_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)

SV5_CFG 0b00..Security Violation 5 is disabled 0b01..Security Violation 5 is a non-fatal violation 0b1x..Security Violation 5 is a fatal violation

◆ SNVS_HPSVCR_WDOG2_CFG [1/2]

#define SNVS_HPSVCR_WDOG2_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)

WDOG2_CFG 0b0..Watchdog 2 Reset is a non-fatal violation 0b1..Watchdog 2 Reset is a fatal violation

◆ SNVS_HPSVCR_WDOG2_CFG [2/2]

#define SNVS_HPSVCR_WDOG2_CFG (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)

WDOG2_CFG 0b0..Watchdog 2 Reset is a non-fatal violation 0b1..Watchdog 2 Reset is a fatal violation

◆ SNVS_HPSVSR_CAAM [1/2]

#define SNVS_HPSVSR_CAAM (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_CAAM_SHIFT)) & SNVS_HPSVSR_CAAM_MASK)

CAAM 0b0..No CAAM Security Violation security violation was detected. 0b1..CAAM Security Violation security violation was detected.

◆ SNVS_HPSVSR_CAAM [2/2]

#define SNVS_HPSVSR_CAAM (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_CAAM_SHIFT)) & SNVS_HPSVSR_CAAM_MASK)

CAAM 0b0..No CAAM Security Violation security violation was detected. 0b1..CAAM Security Violation security violation was detected.

◆ SNVS_HPSVSR_JTAGC [1/2]

#define SNVS_HPSVSR_JTAGC (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_JTAGC_SHIFT)) & SNVS_HPSVSR_JTAGC_MASK)

JTAGC 0b0..No JTAG Active security violation was detected. 0b1..JTAG Active security violation was detected.

◆ SNVS_HPSVSR_JTAGC [2/2]

#define SNVS_HPSVSR_JTAGC (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_JTAGC_SHIFT)) & SNVS_HPSVSR_JTAGC_MASK)

JTAGC 0b0..No JTAG Active security violation was detected. 0b1..JTAG Active security violation was detected.

◆ SNVS_HPSVSR_OCOTP [1/2]

#define SNVS_HPSVSR_OCOTP (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_OCOTP_SHIFT)) & SNVS_HPSVSR_OCOTP_MASK)

OCOTP 0b0..No OCOTP attack error security violation was detected. 0b1..OCOTP attack error security violation was detected.

◆ SNVS_HPSVSR_OCOTP [2/2]

#define SNVS_HPSVSR_OCOTP (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_OCOTP_SHIFT)) & SNVS_HPSVSR_OCOTP_MASK)

OCOTP 0b0..No OCOTP attack error security violation was detected. 0b1..OCOTP attack error security violation was detected.

◆ SNVS_HPSVSR_SRC [1/2]

#define SNVS_HPSVSR_SRC (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SRC_SHIFT)) & SNVS_HPSVSR_SRC_MASK)

SRC 0b0..No Internal Boot security violation was detected. 0b1..Internal Boot security violation was detected.

◆ SNVS_HPSVSR_SRC [2/2]

#define SNVS_HPSVSR_SRC (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SRC_SHIFT)) & SNVS_HPSVSR_SRC_MASK)

SRC 0b0..No Internal Boot security violation was detected. 0b1..Internal Boot security violation was detected.

◆ SNVS_HPSVSR_SV0

#define SNVS_HPSVSR_SV0 (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)

SV0 0b0..No Security Violation 0 security violation was detected. 0b1..Security Violation 0 security violation was detected.

◆ SNVS_HPSVSR_SV1

#define SNVS_HPSVSR_SV1 (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)

SV1 0b0..No Security Violation 1 security violation was detected. 0b1..Security Violation 1 security violation was detected.

◆ SNVS_HPSVSR_SV2

#define SNVS_HPSVSR_SV2 (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)

SV2 0b0..No Security Violation 2 security violation was detected. 0b1..Security Violation 2 security violation was detected.

◆ SNVS_HPSVSR_SV3

#define SNVS_HPSVSR_SV3 (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)

SV3 0b0..No Security Violation 3 security violation was detected. 0b1..Security Violation 3 security violation was detected.

◆ SNVS_HPSVSR_SV4

#define SNVS_HPSVSR_SV4 (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)

SV4 0b0..No Security Violation 4 security violation was detected. 0b1..Security Violation 4 security violation was detected.

◆ SNVS_HPSVSR_SV5

#define SNVS_HPSVSR_SV5 (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)

SV5 0b0..No Security Violation 5 security violation was detected. 0b1..Security Violation 5 security violation was detected.

◆ SNVS_HPSVSR_WDOG2 [1/2]

#define SNVS_HPSVSR_WDOG2 (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_WDOG2_SHIFT)) & SNVS_HPSVSR_WDOG2_MASK)

WDOG2 0b0..No Watchdog 2 Reset security violation was detected. 0b1..Watchdog 2 Reset security violation was detected.

◆ SNVS_HPSVSR_WDOG2 [2/2]

#define SNVS_HPSVSR_WDOG2 (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_WDOG2_SHIFT)) & SNVS_HPSVSR_WDOG2_MASK)

WDOG2 0b0..No Watchdog 2 Reset security violation was detected. 0b1..Watchdog 2 Reset security violation was detected.

◆ SNVS_HPSVSR_ZMK_ECC_FAIL [1/3]

#define SNVS_HPSVSR_ZMK_ECC_FAIL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)

ZMK_ECC_FAIL 0b0..ZMK ECC Failure was not detected. 0b1..ZMK ECC Failure was detected.

◆ SNVS_HPSVSR_ZMK_ECC_FAIL [2/3]

#define SNVS_HPSVSR_ZMK_ECC_FAIL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)

ZMK_ECC_FAIL 0b0..ZMK ECC Failure was not detected. 0b1..ZMK ECC Failure was detected.

◆ SNVS_HPSVSR_ZMK_ECC_FAIL [3/3]

#define SNVS_HPSVSR_ZMK_ECC_FAIL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)

ZMK_ECC_FAIL 0b0..ZMK ECC Failure was not detected. 0b1..ZMK ECC Failure was detected.

◆ SNVS_LPATCTLR_AT1_EN [1/2]

#define SNVS_LPATCTLR_AT1_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_EN_SHIFT)) & SNVS_LPATCTLR_AT1_EN_MASK)

AT1_EN 0b0..Active Tamper 1 is disabled. 0b1..Active Tamper 1 is enabled.

◆ SNVS_LPATCTLR_AT1_EN [2/2]

#define SNVS_LPATCTLR_AT1_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_EN_SHIFT)) & SNVS_LPATCTLR_AT1_EN_MASK)

AT1_EN 0b0..Active Tamper 1 is disabled. 0b1..Active Tamper 1 is enabled.

◆ SNVS_LPATCTLR_AT1_PAD_EN [1/2]

#define SNVS_LPATCTLR_AT1_PAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT1_PAD_EN_MASK)

AT1_PAD_EN 0b0..Active Tamper 1 is disabled. 0b1..Active Tamper 1 is enabled.

◆ SNVS_LPATCTLR_AT1_PAD_EN [2/2]

#define SNVS_LPATCTLR_AT1_PAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT1_PAD_EN_MASK)

AT1_PAD_EN 0b0..Active Tamper 1 is disabled. 0b1..Active Tamper 1 is enabled.

◆ SNVS_LPATCTLR_AT2_EN [1/2]

#define SNVS_LPATCTLR_AT2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_EN_SHIFT)) & SNVS_LPATCTLR_AT2_EN_MASK)

AT2_EN 0b0..Active Tamper 2 is disabled. 0b1..Active Tamper 2 is enabled.

◆ SNVS_LPATCTLR_AT2_EN [2/2]

#define SNVS_LPATCTLR_AT2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_EN_SHIFT)) & SNVS_LPATCTLR_AT2_EN_MASK)

AT2_EN 0b0..Active Tamper 2 is disabled. 0b1..Active Tamper 2 is enabled.

◆ SNVS_LPATCTLR_AT2_PAD_EN [1/2]

#define SNVS_LPATCTLR_AT2_PAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT2_PAD_EN_MASK)

AT2_PAD_EN 0b0..Active Tamper 2 is disabled. 0b1..Active Tamper 2 is enabled.

◆ SNVS_LPATCTLR_AT2_PAD_EN [2/2]

#define SNVS_LPATCTLR_AT2_PAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT2_PAD_EN_MASK)

AT2_PAD_EN 0b0..Active Tamper 2 is disabled. 0b1..Active Tamper 2 is enabled.

◆ SNVS_LPATCTLR_AT3_EN [1/2]

#define SNVS_LPATCTLR_AT3_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_EN_SHIFT)) & SNVS_LPATCTLR_AT3_EN_MASK)

AT3_EN 0b0..Active Tamper 3 is disabled. 0b1..Active Tamper 3 is enabled.

◆ SNVS_LPATCTLR_AT3_EN [2/2]

#define SNVS_LPATCTLR_AT3_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_EN_SHIFT)) & SNVS_LPATCTLR_AT3_EN_MASK)

AT3_EN 0b0..Active Tamper 3 is disabled. 0b1..Active Tamper 3 is enabled.

◆ SNVS_LPATCTLR_AT3_PAD_EN [1/2]

#define SNVS_LPATCTLR_AT3_PAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT3_PAD_EN_MASK)

AT3_PAD_EN 0b0..Active Tamper 3 is disabled. 0b1..Active Tamper 3 is enabled

◆ SNVS_LPATCTLR_AT3_PAD_EN [2/2]

#define SNVS_LPATCTLR_AT3_PAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT3_PAD_EN_MASK)

AT3_PAD_EN 0b0..Active Tamper 3 is disabled. 0b1..Active Tamper 3 is enabled

◆ SNVS_LPATCTLR_AT4_EN [1/2]

#define SNVS_LPATCTLR_AT4_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_EN_SHIFT)) & SNVS_LPATCTLR_AT4_EN_MASK)

AT4_EN 0b0..Active Tamper 4 is disabled. 0b1..Active Tamper 4 is enabled.

◆ SNVS_LPATCTLR_AT4_EN [2/2]

#define SNVS_LPATCTLR_AT4_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_EN_SHIFT)) & SNVS_LPATCTLR_AT4_EN_MASK)

AT4_EN 0b0..Active Tamper 4 is disabled. 0b1..Active Tamper 4 is enabled.

◆ SNVS_LPATCTLR_AT4_PAD_EN [1/2]

#define SNVS_LPATCTLR_AT4_PAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT4_PAD_EN_MASK)

AT4_PAD_EN 0b0..Active Tamper 4 is disabled. 0b1..Active Tamper 4 is enabled.

◆ SNVS_LPATCTLR_AT4_PAD_EN [2/2]

#define SNVS_LPATCTLR_AT4_PAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT4_PAD_EN_MASK)

AT4_PAD_EN 0b0..Active Tamper 4 is disabled. 0b1..Active Tamper 4 is enabled.

◆ SNVS_LPATCTLR_AT5_EN [1/2]

#define SNVS_LPATCTLR_AT5_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_EN_SHIFT)) & SNVS_LPATCTLR_AT5_EN_MASK)

AT5_EN 0b0..Active Tamper 5 is disabled. 0b1..Active Tamper 5 is enabled.

◆ SNVS_LPATCTLR_AT5_EN [2/2]

#define SNVS_LPATCTLR_AT5_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_EN_SHIFT)) & SNVS_LPATCTLR_AT5_EN_MASK)

AT5_EN 0b0..Active Tamper 5 is disabled. 0b1..Active Tamper 5 is enabled.

◆ SNVS_LPATCTLR_AT5_PAD_EN [1/2]

#define SNVS_LPATCTLR_AT5_PAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT5_PAD_EN_MASK)

AT5_PAD_EN 0b0..Active Tamper 5 is disabled. 0b1..Active Tamper 5 is enabled.

◆ SNVS_LPATCTLR_AT5_PAD_EN [2/2]

#define SNVS_LPATCTLR_AT5_PAD_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT5_PAD_EN_MASK)

AT5_PAD_EN 0b0..Active Tamper 5 is disabled. 0b1..Active Tamper 5 is enabled.

◆ SNVS_LPCR_DP_EN [1/3]

#define SNVS_LPCR_DP_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)

DP_EN 0b0..Smart PMIC enabled. 0b1..Dumb PMIC enabled.

◆ SNVS_LPCR_DP_EN [2/3]

#define SNVS_LPCR_DP_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)

DP_EN 0b0..Smart PMIC enabled. 0b1..Dumb PMIC enabled.

◆ SNVS_LPCR_DP_EN [3/3]

#define SNVS_LPCR_DP_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)

DP_EN 0b0..Smart PMIC enabled. 0b1..Dumb PMIC enabled.

◆ SNVS_LPCR_LPCALB_EN [1/3]

#define SNVS_LPCR_LPCALB_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)

LPCALB_EN 0b0..SRTC Time calibration is disabled. 0b1..SRTC Time calibration is enabled.

◆ SNVS_LPCR_LPCALB_EN [2/3]

#define SNVS_LPCR_LPCALB_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)

LPCALB_EN 0b0..SRTC Time calibration is disabled. 0b1..SRTC Time calibration is enabled.

◆ SNVS_LPCR_LPCALB_EN [3/3]

#define SNVS_LPCR_LPCALB_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)

LPCALB_EN 0b0..SRTC Time calibration is disabled. 0b1..SRTC Time calibration is enabled.

◆ SNVS_LPCR_LPCALB_VAL [1/3]

#define SNVS_LPCR_LPCALB_VAL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)

LPCALB_VAL 0b00000..+0 counts per each 32768 ticks of the counter clock 0b00001..+1 counts per each 32768 ticks of the counter clock 0b00010..+2 counts per each 32768 ticks of the counter clock 0b01111..+15 counts per each 32768 ticks of the counter clock 0b10000..-16 counts per each 32768 ticks of the counter clock 0b10001..-15 counts per each 32768 ticks of the counter clock 0b11110..-2 counts per each 32768 ticks of the counter clock 0b11111..-1 counts per each 32768 ticks of the counter clock

◆ SNVS_LPCR_LPCALB_VAL [2/3]

#define SNVS_LPCR_LPCALB_VAL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)

LPCALB_VAL 0b00000..+0 counts per each 32768 ticks of the counter clock 0b00001..+1 counts per each 32768 ticks of the counter clock 0b00010..+2 counts per each 32768 ticks of the counter clock 0b01111..+15 counts per each 32768 ticks of the counter clock 0b10000..-16 counts per each 32768 ticks of the counter clock 0b10001..-15 counts per each 32768 ticks of the counter clock 0b11110..-2 counts per each 32768 ticks of the counter clock 0b11111..-1 counts per each 32768 ticks of the counter clock

◆ SNVS_LPCR_LPCALB_VAL [3/3]

#define SNVS_LPCR_LPCALB_VAL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)

LPCALB_VAL 0b00000..+0 counts per each 32768 ticks of the counter clock 0b00001..+1 counts per each 32768 ticks of the counter clock 0b00010..+2 counts per each 32768 ticks of the counter clock 0b01111..+15 counts per each 32768 ticks of the counter clock 0b10000..-16 counts per each 32768 ticks of the counter clock 0b10001..-15 counts per each 32768 ticks of the counter clock 0b11110..-2 counts per each 32768 ticks of the counter clock 0b11111..-1 counts per each 32768 ticks of the counter clock

◆ SNVS_LPCR_LPTA_EN [1/3]

#define SNVS_LPCR_LPTA_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)

LPTA_EN 0b0..LP time alarm interrupt is disabled. 0b1..LP time alarm interrupt is enabled.

◆ SNVS_LPCR_LPTA_EN [2/3]

#define SNVS_LPCR_LPTA_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)

LPTA_EN 0b0..LP time alarm interrupt is disabled. 0b1..LP time alarm interrupt is enabled.

◆ SNVS_LPCR_LPTA_EN [3/3]

#define SNVS_LPCR_LPTA_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)

LPTA_EN 0b0..LP time alarm interrupt is disabled. 0b1..LP time alarm interrupt is enabled.

◆ SNVS_LPCR_MC_ENV [1/3]

#define SNVS_LPCR_MC_ENV (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)

MC_ENV 0b0..MC is disabled or invalid. 0b1..MC is enabled and valid.

◆ SNVS_LPCR_MC_ENV [2/3]

#define SNVS_LPCR_MC_ENV (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)

MC_ENV 0b0..MC is disabled or invalid. 0b1..MC is enabled and valid.

◆ SNVS_LPCR_MC_ENV [3/3]

#define SNVS_LPCR_MC_ENV (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)

MC_ENV 0b0..MC is disabled or invalid. 0b1..MC is enabled and valid.

◆ SNVS_LPCR_SRTC_ENV [1/3]

#define SNVS_LPCR_SRTC_ENV (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)

SRTC_ENV 0b0..SRTC is disabled or invalid. 0b1..SRTC is enabled and valid.

◆ SNVS_LPCR_SRTC_ENV [2/3]

#define SNVS_LPCR_SRTC_ENV (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)

SRTC_ENV 0b0..SRTC is disabled or invalid. 0b1..SRTC is enabled and valid.

◆ SNVS_LPCR_SRTC_ENV [3/3]

#define SNVS_LPCR_SRTC_ENV (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)

SRTC_ENV 0b0..SRTC is disabled or invalid. 0b1..SRTC is enabled and valid.

◆ SNVS_LPCR_SRTC_INV_EN [1/3]

#define SNVS_LPCR_SRTC_INV_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)

SRTC_INV_EN 0b0..SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)). 0b1..SRTC is invalidated in the case of security violation.

◆ SNVS_LPCR_SRTC_INV_EN [2/3]

#define SNVS_LPCR_SRTC_INV_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)

SRTC_INV_EN 0b0..SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)). 0b1..SRTC is invalidated in the case of security violation.

◆ SNVS_LPCR_SRTC_INV_EN [3/3]

#define SNVS_LPCR_SRTC_INV_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)

SRTC_INV_EN 0b0..SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)). 0b1..SRTC is invalidated in the case of security violation.

◆ SNVS_LPCR_TOP [1/3]

#define SNVS_LPCR_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)

TOP 0b0..Leave system power on. 0b1..Turn off system power.

◆ SNVS_LPCR_TOP [2/3]

#define SNVS_LPCR_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)

TOP 0b0..Leave system power on. 0b1..Turn off system power.

◆ SNVS_LPCR_TOP [3/3]

#define SNVS_LPCR_TOP (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)

TOP 0b0..Leave system power on. 0b1..Turn off system power.

◆ SNVS_LPLR_AT1_HL [1/2]

#define SNVS_LPLR_AT1_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT1_HL_SHIFT)) & SNVS_LPLR_AT1_HL_MASK)

AT1_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_AT1_HL [2/2]

#define SNVS_LPLR_AT1_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT1_HL_SHIFT)) & SNVS_LPLR_AT1_HL_MASK)

AT1_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_AT2_HL [1/2]

#define SNVS_LPLR_AT2_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT2_HL_SHIFT)) & SNVS_LPLR_AT2_HL_MASK)

AT2_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_AT2_HL [2/2]

#define SNVS_LPLR_AT2_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT2_HL_SHIFT)) & SNVS_LPLR_AT2_HL_MASK)

AT2_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_AT3_HL [1/2]

#define SNVS_LPLR_AT3_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT3_HL_SHIFT)) & SNVS_LPLR_AT3_HL_MASK)

AT3_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_AT3_HL [2/2]

#define SNVS_LPLR_AT3_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT3_HL_SHIFT)) & SNVS_LPLR_AT3_HL_MASK)

AT3_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_AT4_HL [1/2]

#define SNVS_LPLR_AT4_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT4_HL_SHIFT)) & SNVS_LPLR_AT4_HL_MASK)

AT4_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_AT4_HL [2/2]

#define SNVS_LPLR_AT4_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT4_HL_SHIFT)) & SNVS_LPLR_AT4_HL_MASK)

AT4_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_AT5_HL [1/2]

#define SNVS_LPLR_AT5_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT5_HL_SHIFT)) & SNVS_LPLR_AT5_HL_MASK)

AT5_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_AT5_HL [2/2]

#define SNVS_LPLR_AT5_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT5_HL_SHIFT)) & SNVS_LPLR_AT5_HL_MASK)

AT5_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_GPR_HL [1/3]

#define SNVS_LPLR_GPR_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)

GPR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_GPR_HL [2/3]

#define SNVS_LPLR_GPR_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)

GPR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_GPR_HL [3/3]

#define SNVS_LPLR_GPR_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)

GPR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_LPCALB_HL [1/3]

#define SNVS_LPLR_LPCALB_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)

LPCALB_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_LPCALB_HL [2/3]

#define SNVS_LPLR_LPCALB_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)

LPCALB_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_LPCALB_HL [3/3]

#define SNVS_LPLR_LPCALB_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)

LPCALB_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_LPSECR_HL [1/3]

#define SNVS_LPLR_LPSECR_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)

LPSECR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_LPSECR_HL [2/3]

#define SNVS_LPLR_LPSECR_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)

LPSECR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_LPSECR_HL [3/3]

#define SNVS_LPLR_LPSECR_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)

LPSECR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_LPSVCR_HL [1/3]

#define SNVS_LPLR_LPSVCR_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)

LPSVCR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_LPSVCR_HL [2/3]

#define SNVS_LPLR_LPSVCR_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)

LPSVCR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_LPSVCR_HL [3/3]

#define SNVS_LPLR_LPSVCR_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)

LPSVCR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_LPTGFCR_HL [1/2]

#define SNVS_LPLR_LPTGFCR_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK)

LPTGFCR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_LPTGFCR_HL [2/2]

#define SNVS_LPLR_LPTGFCR_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK)

LPTGFCR_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_MC_HL [1/3]

#define SNVS_LPLR_MC_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)

MC_HL 0b0..Write access (increment) is allowed. 0b1..Write access (increment) is not allowed.

◆ SNVS_LPLR_MC_HL [2/3]

#define SNVS_LPLR_MC_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)

MC_HL 0b0..Write access (increment) is allowed. 0b1..Write access (increment) is not allowed.

◆ SNVS_LPLR_MC_HL [3/3]

#define SNVS_LPLR_MC_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)

MC_HL 0b0..Write access (increment) is allowed. 0b1..Write access (increment) is not allowed.

◆ SNVS_LPLR_MKS_HL [1/3]

#define SNVS_LPLR_MKS_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)

MKS_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_MKS_HL [2/3]

#define SNVS_LPLR_MKS_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)

MKS_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_MKS_HL [3/3]

#define SNVS_LPLR_MKS_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)

MKS_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_SRTC_HL [1/3]

#define SNVS_LPLR_SRTC_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)

SRTC_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_SRTC_HL [2/3]

#define SNVS_LPLR_SRTC_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)

SRTC_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_SRTC_HL [3/3]

#define SNVS_LPLR_SRTC_HL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)

SRTC_HL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_ZMK_RHL [1/3]

#define SNVS_LPLR_ZMK_RHL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)

ZMK_RHL 0b0..Read access is allowed (only in software programming mode). 0b1..Read access is not allowed.

◆ SNVS_LPLR_ZMK_RHL [2/3]

#define SNVS_LPLR_ZMK_RHL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)

ZMK_RHL 0b0..Read access is allowed (only in software programming mode). 0b1..Read access is not allowed.

◆ SNVS_LPLR_ZMK_RHL [3/3]

#define SNVS_LPLR_ZMK_RHL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)

ZMK_RHL 0b0..Read access is allowed (only in software programming mode). 0b1..Read access is not allowed.

◆ SNVS_LPLR_ZMK_WHL [1/3]

#define SNVS_LPLR_ZMK_WHL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)

ZMK_WHL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_ZMK_WHL [2/3]

#define SNVS_LPLR_ZMK_WHL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)

ZMK_WHL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPLR_ZMK_WHL [3/3]

#define SNVS_LPLR_ZMK_WHL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)

ZMK_WHL 0b0..Write access is allowed. 0b1..Write access is not allowed.

◆ SNVS_LPMKCR_MASTER_KEY_SEL [1/3]

#define SNVS_LPMKCR_MASTER_KEY_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)

MASTER_KEY_SEL 0b0x..Select one time programmable master key. 0b10..Select zeroizable master key when MKS_EN bit is set . 0b11..Select combined master key when MKS_EN bit is set .

◆ SNVS_LPMKCR_MASTER_KEY_SEL [2/3]

#define SNVS_LPMKCR_MASTER_KEY_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)

MASTER_KEY_SEL 0b0x..Select one time programmable master key. 0b10..Select zeroizable master key when MKS_EN bit is set . 0b11..Select combined master key when MKS_EN bit is set .

◆ SNVS_LPMKCR_MASTER_KEY_SEL [3/3]

#define SNVS_LPMKCR_MASTER_KEY_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)

MASTER_KEY_SEL 0b0x..Select one time programmable master key. 0b10..Select zeroizable master key when MKS_EN bit is set . 0b11..Select combined master key when MKS_EN bit is set .

◆ SNVS_LPMKCR_ZMK_ECC_EN [1/3]

#define SNVS_LPMKCR_ZMK_ECC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)

ZMK_ECC_EN 0b0..ZMK ECC check is disabled. 0b1..ZMK ECC check is enabled.

◆ SNVS_LPMKCR_ZMK_ECC_EN [2/3]

#define SNVS_LPMKCR_ZMK_ECC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)

ZMK_ECC_EN 0b0..ZMK ECC check is disabled. 0b1..ZMK ECC check is enabled.

◆ SNVS_LPMKCR_ZMK_ECC_EN [3/3]

#define SNVS_LPMKCR_ZMK_ECC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)

ZMK_ECC_EN 0b0..ZMK ECC check is disabled. 0b1..ZMK ECC check is enabled.

◆ SNVS_LPMKCR_ZMK_HWP [1/3]

#define SNVS_LPMKCR_ZMK_HWP (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)

ZMK_HWP 0b0..ZMK is in the software programming mode. 0b1..ZMK is in the hardware programming mode.

◆ SNVS_LPMKCR_ZMK_HWP [2/3]

#define SNVS_LPMKCR_ZMK_HWP (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)

ZMK_HWP 0b0..ZMK is in the software programming mode. 0b1..ZMK is in the hardware programming mode.

◆ SNVS_LPMKCR_ZMK_HWP [3/3]

#define SNVS_LPMKCR_ZMK_HWP (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)

ZMK_HWP 0b0..ZMK is in the software programming mode. 0b1..ZMK is in the hardware programming mode.

◆ SNVS_LPMKCR_ZMK_VAL [1/3]

#define SNVS_LPMKCR_ZMK_VAL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)

ZMK_VAL 0b0..ZMK is not valid. 0b1..ZMK is valid.

◆ SNVS_LPMKCR_ZMK_VAL [2/3]

#define SNVS_LPMKCR_ZMK_VAL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)

ZMK_VAL 0b0..ZMK is not valid. 0b1..ZMK is valid.

◆ SNVS_LPMKCR_ZMK_VAL [3/3]

#define SNVS_LPMKCR_ZMK_VAL (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)

ZMK_VAL 0b0..ZMK is not valid. 0b1..ZMK is valid.

◆ SNVS_LPSECR_MCR_EN

#define SNVS_LPSECR_MCR_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_MCR_EN_SHIFT)) & SNVS_LPSECR_MCR_EN_MASK)

MCR_EN 0b0..MC rollover is disabled. 0b1..MC rollover is enabled.

◆ SNVS_LPSECR_OSCB

#define SNVS_LPSECR_OSCB (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_OSCB_SHIFT)) & SNVS_LPSECR_OSCB_MASK)

OSCB 0b0..Normal SRTC clock oscillator not bypassed. 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.

◆ SNVS_LPSECR_SRTCR_EN

#define SNVS_LPSECR_SRTCR_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSECR_SRTCR_EN_SHIFT)) & SNVS_LPSECR_SRTCR_EN_MASK)

SRTCR_EN 0b0..SRTC rollover is disabled. 0b1..SRTC rollover is enabled.

◆ SNVS_LPSR_CTD [1/2]

#define SNVS_LPSR_CTD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK)

CTD 0b0..No clock tamper. 0b1..Clock tamper is detected.

◆ SNVS_LPSR_CTD [2/2]

#define SNVS_LPSR_CTD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK)

CTD 0b0..No clock tamper. 0b1..Clock tamper is detected.

◆ SNVS_LPSR_EO [1/3]

#define SNVS_LPSR_EO (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)

EO 0b0..Emergency off was not detected. 0b1..Emergency off was detected.

◆ SNVS_LPSR_EO [2/3]

#define SNVS_LPSR_EO (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)

EO 0b0..Emergency off was not detected. 0b1..Emergency off was detected.

◆ SNVS_LPSR_EO [3/3]

#define SNVS_LPSR_EO (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)

EO 0b0..Emergency off was not detected. 0b1..Emergency off was detected.

◆ SNVS_LPSR_ESVD [1/3]

#define SNVS_LPSR_ESVD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)

ESVD 0b0..No external security violation. 0b1..External security violation is detected.

◆ SNVS_LPSR_ESVD [2/3]

#define SNVS_LPSR_ESVD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)

ESVD 0b0..No external security violation. 0b1..External security violation is detected.

◆ SNVS_LPSR_ESVD [3/3]

#define SNVS_LPSR_ESVD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)

ESVD 0b0..No external security violation. 0b1..External security violation is detected.

◆ SNVS_LPSR_ET1D [1/2]

#define SNVS_LPSR_ET1D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)

ET1D 0b0..External tampering 1 not detected. 0b1..External tampering 1 detected.

◆ SNVS_LPSR_ET1D [2/2]

#define SNVS_LPSR_ET1D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)

ET1D 0b0..External tampering 1 not detected. 0b1..External tampering 1 detected.

◆ SNVS_LPSR_ET2D [1/2]

#define SNVS_LPSR_ET2D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)

ET2D 0b0..External tampering 2 not detected. 0b1..External tampering 2 detected.

◆ SNVS_LPSR_ET2D [2/2]

#define SNVS_LPSR_ET2D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)

ET2D 0b0..External tampering 2 not detected. 0b1..External tampering 2 detected.

◆ SNVS_LPSR_LPNS [1/3]

#define SNVS_LPSR_LPNS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)

LPNS 0b0..LP section was not programmed in the non-secure state. 0b1..LP section was programmed in the non-secure state.

◆ SNVS_LPSR_LPNS [2/3]

#define SNVS_LPSR_LPNS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)

LPNS 0b0..LP section was not programmed in the non-secure state. 0b1..LP section was programmed in the non-secure state.

◆ SNVS_LPSR_LPNS [3/3]

#define SNVS_LPSR_LPNS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)

LPNS 0b0..LP section was not programmed in the non-secure state. 0b1..LP section was programmed in the non-secure state.

◆ SNVS_LPSR_LPS [1/3]

#define SNVS_LPSR_LPS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)

LPS 0b0..LP section was not programmed in secure or trusted state. 0b1..LP section was programmed in secure or trusted state.

◆ SNVS_LPSR_LPS [2/3]

#define SNVS_LPSR_LPS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)

LPS 0b0..LP section was not programmed in secure or trusted state. 0b1..LP section was programmed in secure or trusted state.

◆ SNVS_LPSR_LPS [3/3]

#define SNVS_LPSR_LPS (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)

LPS 0b0..LP section was not programmed in secure or trusted state. 0b1..LP section was programmed in secure or trusted state.

◆ SNVS_LPSR_LPTA [1/3]

#define SNVS_LPSR_LPTA (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)

LPTA 0b0..No time alarm interrupt occurred. 0b1..A time alarm interrupt occurred.

◆ SNVS_LPSR_LPTA [2/3]

#define SNVS_LPSR_LPTA (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)

LPTA 0b0..No time alarm interrupt occurred. 0b1..A time alarm interrupt occurred.

◆ SNVS_LPSR_LPTA [3/3]

#define SNVS_LPSR_LPTA (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)

LPTA 0b0..No time alarm interrupt occurred. 0b1..A time alarm interrupt occurred.

◆ SNVS_LPSR_LVD [1/3]

#define SNVS_LPSR_LVD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)

LVD 0b0..No low voltage event detected. 0b1..Low voltage event is detected.

◆ SNVS_LPSR_LVD [2/3]

#define SNVS_LPSR_LVD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)

LVD 0b0..No low voltage event detected. 0b1..Low voltage event is detected.

◆ SNVS_LPSR_LVD [3/3]

#define SNVS_LPSR_LVD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)

LVD 0b0..No low voltage event detected. 0b1..Low voltage event is detected.

◆ SNVS_LPSR_MCR [1/3]

#define SNVS_LPSR_MCR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)

MCR 0b0..MC has not reached its maximum value. 0b1..MC has reached its maximum value.

◆ SNVS_LPSR_MCR [2/3]

#define SNVS_LPSR_MCR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)

MCR 0b0..MC has not reached its maximum value. 0b1..MC has reached its maximum value.

◆ SNVS_LPSR_MCR [3/3]

#define SNVS_LPSR_MCR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)

MCR 0b0..MC has not reached its maximum value. 0b1..MC has reached its maximum value.

◆ SNVS_LPSR_SPOF [1/3]

#define SNVS_LPSR_SPOF (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)

SPOF 0b0..Set Power Off was not detected. 0b1..Set Power Off was detected.

◆ SNVS_LPSR_SPOF [2/3]

#define SNVS_LPSR_SPOF (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)

SPOF 0b0..Set Power Off was not detected. 0b1..Set Power Off was detected.

◆ SNVS_LPSR_SPOF [3/3]

#define SNVS_LPSR_SPOF (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)

SPOF 0b0..Set Power Off was not detected. 0b1..Set Power Off was detected.

◆ SNVS_LPSR_SPON

#define SNVS_LPSR_SPON (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPON_SHIFT)) & SNVS_LPSR_SPON_MASK)

SPON 0b0..Set Power On Interrupt was not detected. 0b1..Set Power On Interrupt was detected.

◆ SNVS_LPSR_SRTCR [1/3]

#define SNVS_LPSR_SRTCR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)

SRTCR 0b0..SRTC has not reached its maximum value. 0b1..SRTC has reached its maximum value.

◆ SNVS_LPSR_SRTCR [2/3]

#define SNVS_LPSR_SRTCR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)

SRTCR 0b0..SRTC has not reached its maximum value. 0b1..SRTC has reached its maximum value.

◆ SNVS_LPSR_SRTCR [3/3]

#define SNVS_LPSR_SRTCR (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)

SRTCR 0b0..SRTC has not reached its maximum value. 0b1..SRTC has reached its maximum value.

◆ SNVS_LPSR_TTD [1/2]

#define SNVS_LPSR_TTD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK)

TTD 0b0..No temperature tamper. 0b1..Temperature tamper is detected.

◆ SNVS_LPSR_TTD [2/2]

#define SNVS_LPSR_TTD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK)

TTD 0b0..No temperature tamper. 0b1..Temperature tamper is detected.

◆ SNVS_LPSR_VTD [1/2]

#define SNVS_LPSR_VTD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)

VTD 0b0..Voltage tampering not detected. 0b1..Voltage tampering detected.

◆ SNVS_LPSR_VTD [2/2]

#define SNVS_LPSR_VTD (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)

VTD 0b0..Voltage tampering not detected. 0b1..Voltage tampering detected.

◆ SNVS_LPSR_WMT1D [1/2]

#define SNVS_LPSR_WMT1D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK)

WMT1D 0b0..Wire-mesh tampering 1 not detected. 0b1..Wire-mesh tampering 1 detected.

◆ SNVS_LPSR_WMT1D [2/2]

#define SNVS_LPSR_WMT1D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK)

WMT1D 0b0..Wire-mesh tampering 1 not detected. 0b1..Wire-mesh tampering 1 detected.

◆ SNVS_LPSR_WMT2D [1/2]

#define SNVS_LPSR_WMT2D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK)

WMT2D 0b0..Wire-mesh tampering 2 not detected. 0b1..Wire-mesh tampering 2 detected.

◆ SNVS_LPSR_WMT2D [2/2]

#define SNVS_LPSR_WMT2D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK)

WMT2D 0b0..Wire-mesh tampering 2 not detected. 0b1..Wire-mesh tampering 2 detected.

◆ SNVS_LPSVCR_CAAM_EN [1/2]

#define SNVS_LPSVCR_CAAM_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_CAAM_EN_SHIFT)) & SNVS_LPSVCR_CAAM_EN_MASK)

CAAM_EN 0b0..CAAM Security Violation is disabled in the LP domain. 0b1..CAAM Security Violation is enabled in the LP domain.

◆ SNVS_LPSVCR_CAAM_EN [2/2]

#define SNVS_LPSVCR_CAAM_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_CAAM_EN_SHIFT)) & SNVS_LPSVCR_CAAM_EN_MASK)

CAAM_EN 0b0..CAAM Security Violation is disabled in the LP domain. 0b1..CAAM Security Violation is enabled in the LP domain.

◆ SNVS_LPSVCR_JTAGC_EN [1/2]

#define SNVS_LPSVCR_JTAGC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_JTAGC_EN_SHIFT)) & SNVS_LPSVCR_JTAGC_EN_MASK)

JTAGC_EN 0b0..JTAG Active is disabled in the LP domain. 0b1..JTAG Active is enabled in the LP domain.

◆ SNVS_LPSVCR_JTAGC_EN [2/2]

#define SNVS_LPSVCR_JTAGC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_JTAGC_EN_SHIFT)) & SNVS_LPSVCR_JTAGC_EN_MASK)

JTAGC_EN 0b0..JTAG Active is disabled in the LP domain. 0b1..JTAG Active is enabled in the LP domain.

◆ SNVS_LPSVCR_OCOTP_EN [1/2]

#define SNVS_LPSVCR_OCOTP_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_OCOTP_EN_SHIFT)) & SNVS_LPSVCR_OCOTP_EN_MASK)

OCOTP_EN 0b0..OCOTP attack error is disabled in the LP domain. 0b1..OCOTP attack error is enabled in the LP domain.

◆ SNVS_LPSVCR_OCOTP_EN [2/2]

#define SNVS_LPSVCR_OCOTP_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_OCOTP_EN_SHIFT)) & SNVS_LPSVCR_OCOTP_EN_MASK)

OCOTP_EN 0b0..OCOTP attack error is disabled in the LP domain. 0b1..OCOTP attack error is enabled in the LP domain.

◆ SNVS_LPSVCR_SRC_EN [1/2]

#define SNVS_LPSVCR_SRC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SRC_EN_SHIFT)) & SNVS_LPSVCR_SRC_EN_MASK)

SRC_EN 0b0..Internal Boot is disabled in the LP domain. 0b1..Internal Boot is enabled in the LP domain.

◆ SNVS_LPSVCR_SRC_EN [2/2]

#define SNVS_LPSVCR_SRC_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SRC_EN_SHIFT)) & SNVS_LPSVCR_SRC_EN_MASK)

SRC_EN 0b0..Internal Boot is disabled in the LP domain. 0b1..Internal Boot is enabled in the LP domain.

◆ SNVS_LPSVCR_SV0_EN

#define SNVS_LPSVCR_SV0_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)

SV0_EN 0b0..Security Violation 0 is disabled in the LP domain. 0b1..Security Violation 0 is enabled in the LP domain.

◆ SNVS_LPSVCR_SV1_EN

#define SNVS_LPSVCR_SV1_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)

SV1_EN 0b0..Security Violation 1 is disabled in the LP domain. 0b1..Security Violation 1 is enabled in the LP domain.

◆ SNVS_LPSVCR_SV2_EN

#define SNVS_LPSVCR_SV2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)

SV2_EN 0b0..Security Violation 2 is disabled in the LP domain. 0b1..Security Violation 2 is enabled in the LP domain.

◆ SNVS_LPSVCR_SV3_EN

#define SNVS_LPSVCR_SV3_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)

SV3_EN 0b0..Security Violation 3 is disabled in the LP domain. 0b1..Security Violation 3 is enabled in the LP domain.

◆ SNVS_LPSVCR_SV4_EN

#define SNVS_LPSVCR_SV4_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)

SV4_EN 0b0..Security Violation 4 is disabled in the LP domain. 0b1..Security Violation 4 is enabled in the LP domain.

◆ SNVS_LPSVCR_SV5_EN

#define SNVS_LPSVCR_SV5_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)

SV5_EN 0b0..Security Violation 5 is disabled in the LP domain. 0b1..Security Violation 5 is enabled in the LP domain.

◆ SNVS_LPSVCR_WDOG2_EN [1/2]

#define SNVS_LPSVCR_WDOG2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_WDOG2_EN_SHIFT)) & SNVS_LPSVCR_WDOG2_EN_MASK)

WDOG2_EN 0b0..Watchdog 2 Reset is disabled in the LP domain. 0b1..Watchdog 2 Reset is enabled in the LP domain.

◆ SNVS_LPSVCR_WDOG2_EN [2/2]

#define SNVS_LPSVCR_WDOG2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_WDOG2_EN_SHIFT)) & SNVS_LPSVCR_WDOG2_EN_MASK)

WDOG2_EN 0b0..Watchdog 2 Reset is disabled in the LP domain. 0b1..Watchdog 2 Reset is enabled in the LP domain.

◆ SNVS_LPTDC2R_ET10_EN [1/2]

#define SNVS_LPTDC2R_ET10_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK)

ET10_EN 0b0..External tamper 10 is disabled. 0b1..External tamper 10 is enabled.

◆ SNVS_LPTDC2R_ET10_EN [2/2]

#define SNVS_LPTDC2R_ET10_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK)

ET10_EN 0b0..External tamper 10 is disabled. 0b1..External tamper 10 is enabled.

◆ SNVS_LPTDC2R_ET10P [1/2]

#define SNVS_LPTDC2R_ET10P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10P_SHIFT)) & SNVS_LPTDC2R_ET10P_MASK)

ET10P 0b0..External tamper 10 is active low. 0b1..External tamper 10 is active high.

◆ SNVS_LPTDC2R_ET10P [2/2]

#define SNVS_LPTDC2R_ET10P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10P_SHIFT)) & SNVS_LPTDC2R_ET10P_MASK)

ET10P 0b0..External tamper 10 is active low. 0b1..External tamper 10 is active high.

◆ SNVS_LPTDC2R_ET3_EN [1/2]

#define SNVS_LPTDC2R_ET3_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK)

ET3_EN 0b0..External tamper 3 is disabled. 0b1..External tamper 3 is enabled.

◆ SNVS_LPTDC2R_ET3_EN [2/2]

#define SNVS_LPTDC2R_ET3_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK)

ET3_EN 0b0..External tamper 3 is disabled. 0b1..External tamper 3 is enabled.

◆ SNVS_LPTDC2R_ET3P [1/2]

#define SNVS_LPTDC2R_ET3P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK)

ET3P 0b0..External tamper 3 active low. 0b1..External tamper 3 active high.

◆ SNVS_LPTDC2R_ET3P [2/2]

#define SNVS_LPTDC2R_ET3P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK)

ET3P 0b0..External tamper 3 active low. 0b1..External tamper 3 active high.

◆ SNVS_LPTDC2R_ET4_EN [1/2]

#define SNVS_LPTDC2R_ET4_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK)

ET4_EN 0b0..External tamper 4 is disabled. 0b1..External tamper 4 is enabled.

◆ SNVS_LPTDC2R_ET4_EN [2/2]

#define SNVS_LPTDC2R_ET4_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK)

ET4_EN 0b0..External tamper 4 is disabled. 0b1..External tamper 4 is enabled.

◆ SNVS_LPTDC2R_ET4P [1/2]

#define SNVS_LPTDC2R_ET4P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK)

ET4P 0b0..External tamper 4 is active low. 0b1..External tamper 4 is active high.

◆ SNVS_LPTDC2R_ET4P [2/2]

#define SNVS_LPTDC2R_ET4P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK)

ET4P 0b0..External tamper 4 is active low. 0b1..External tamper 4 is active high.

◆ SNVS_LPTDC2R_ET5_EN [1/2]

#define SNVS_LPTDC2R_ET5_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK)

ET5_EN 0b0..External tamper 5 is disabled. 0b1..External tamper 5 is enabled.

◆ SNVS_LPTDC2R_ET5_EN [2/2]

#define SNVS_LPTDC2R_ET5_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK)

ET5_EN 0b0..External tamper 5 is disabled. 0b1..External tamper 5 is enabled.

◆ SNVS_LPTDC2R_ET5P [1/2]

#define SNVS_LPTDC2R_ET5P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK)

ET5P 0b0..External tamper 5 is active low. 0b1..External tamper 5 is active high.

◆ SNVS_LPTDC2R_ET5P [2/2]

#define SNVS_LPTDC2R_ET5P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK)

ET5P 0b0..External tamper 5 is active low. 0b1..External tamper 5 is active high.

◆ SNVS_LPTDC2R_ET6_EN [1/2]

#define SNVS_LPTDC2R_ET6_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK)

ET6_EN 0b0..External tamper 6 is disabled. 0b1..External tamper 6 is enabled.

◆ SNVS_LPTDC2R_ET6_EN [2/2]

#define SNVS_LPTDC2R_ET6_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK)

ET6_EN 0b0..External tamper 6 is disabled. 0b1..External tamper 6 is enabled.

◆ SNVS_LPTDC2R_ET6P [1/2]

#define SNVS_LPTDC2R_ET6P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK)

ET6P 0b0..External tamper 6 is active low. 0b1..External tamper 6 is active high.

◆ SNVS_LPTDC2R_ET6P [2/2]

#define SNVS_LPTDC2R_ET6P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK)

ET6P 0b0..External tamper 6 is active low. 0b1..External tamper 6 is active high.

◆ SNVS_LPTDC2R_ET7_EN [1/2]

#define SNVS_LPTDC2R_ET7_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK)

ET7_EN 0b0..External tamper 7 is disabled. 0b1..External tamper 7 is enabled.

◆ SNVS_LPTDC2R_ET7_EN [2/2]

#define SNVS_LPTDC2R_ET7_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK)

ET7_EN 0b0..External tamper 7 is disabled. 0b1..External tamper 7 is enabled.

◆ SNVS_LPTDC2R_ET7P [1/2]

#define SNVS_LPTDC2R_ET7P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK)

ET7P 0b0..External tamper 7 is active low. 0b1..External tamper 7 is active high.

◆ SNVS_LPTDC2R_ET7P [2/2]

#define SNVS_LPTDC2R_ET7P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK)

ET7P 0b0..External tamper 7 is active low. 0b1..External tamper 7 is active high.

◆ SNVS_LPTDC2R_ET8_EN [1/2]

#define SNVS_LPTDC2R_ET8_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK)

ET8_EN 0b0..External tamper 8 is disabled. 0b1..External tamper 8 is enabled.

◆ SNVS_LPTDC2R_ET8_EN [2/2]

#define SNVS_LPTDC2R_ET8_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK)

ET8_EN 0b0..External tamper 8 is disabled. 0b1..External tamper 8 is enabled.

◆ SNVS_LPTDC2R_ET8P [1/2]

#define SNVS_LPTDC2R_ET8P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK)

ET8P 0b0..External tamper 8 is active low. 0b1..External tamper 8 is active high.

◆ SNVS_LPTDC2R_ET8P [2/2]

#define SNVS_LPTDC2R_ET8P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK)

ET8P 0b0..External tamper 8 is active low. 0b1..External tamper 8 is active high.

◆ SNVS_LPTDC2R_ET9_EN [1/2]

#define SNVS_LPTDC2R_ET9_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK)

ET9_EN 0b0..External tamper 9 is disabled. 0b1..External tamper 9 is enabled.

◆ SNVS_LPTDC2R_ET9_EN [2/2]

#define SNVS_LPTDC2R_ET9_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK)

ET9_EN 0b0..External tamper 9 is disabled. 0b1..External tamper 9 is enabled.

◆ SNVS_LPTDC2R_ET9P [1/2]

#define SNVS_LPTDC2R_ET9P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK)

ET9P 0b0..External tamper 9 is active low. 0b1..External tamper 9 is active high.

◆ SNVS_LPTDC2R_ET9P [2/2]

#define SNVS_LPTDC2R_ET9P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK)

ET9P 0b0..External tamper 9 is active low. 0b1..External tamper 9 is active high.

◆ SNVS_LPTDCR_CT_EN [1/2]

#define SNVS_LPTDCR_CT_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK)

CT_EN 0b0..Clock tamper is disabled. 0b1..Clock tamper is enabled.

◆ SNVS_LPTDCR_CT_EN [2/2]

#define SNVS_LPTDCR_CT_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK)

CT_EN 0b0..Clock tamper is disabled. 0b1..Clock tamper is enabled.

◆ SNVS_LPTDCR_ET1_EN [1/2]

#define SNVS_LPTDCR_ET1_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)

ET1_EN 0b0..External tamper 1 is disabled. 0b1..External tamper 1 is enabled.

◆ SNVS_LPTDCR_ET1_EN [2/2]

#define SNVS_LPTDCR_ET1_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)

ET1_EN 0b0..External tamper 1 is disabled. 0b1..External tamper 1 is enabled.

◆ SNVS_LPTDCR_ET1P [1/2]

#define SNVS_LPTDCR_ET1P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)

ET1P 0b0..External tamper 1 is active low. 0b1..External tamper 1 is active high.

◆ SNVS_LPTDCR_ET1P [2/2]

#define SNVS_LPTDCR_ET1P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)

ET1P 0b0..External tamper 1 is active low. 0b1..External tamper 1 is active high.

◆ SNVS_LPTDCR_ET2_EN [1/2]

#define SNVS_LPTDCR_ET2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK)

ET2_EN 0b0..External tamper 2 is disabled. 0b1..External tamper 2 is enabled.

◆ SNVS_LPTDCR_ET2_EN [2/2]

#define SNVS_LPTDCR_ET2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK)

ET2_EN 0b0..External tamper 2 is disabled. 0b1..External tamper 2 is enabled.

◆ SNVS_LPTDCR_ET2P [1/2]

#define SNVS_LPTDCR_ET2P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK)

ET2P 0b0..External tamper 2 is active low. 0b1..External tamper 2 is active high.

◆ SNVS_LPTDCR_ET2P [2/2]

#define SNVS_LPTDCR_ET2P (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK)

ET2P 0b0..External tamper 2 is active low. 0b1..External tamper 2 is active high.

◆ SNVS_LPTDCR_MCR_EN [1/2]

#define SNVS_LPTDCR_MCR_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)

MCR_EN 0b0..MC rollover is disabled. 0b1..MC rollover is enabled.

◆ SNVS_LPTDCR_MCR_EN [2/2]

#define SNVS_LPTDCR_MCR_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)

MCR_EN 0b0..MC rollover is disabled. 0b1..MC rollover is enabled.

◆ SNVS_LPTDCR_OSCB [1/2]

#define SNVS_LPTDCR_OSCB (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)

OSCB 0b0..Normal SRTC clock oscillator not bypassed. 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.

◆ SNVS_LPTDCR_OSCB [2/2]

#define SNVS_LPTDCR_OSCB (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)

OSCB 0b0..Normal SRTC clock oscillator not bypassed. 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.

◆ SNVS_LPTDCR_SRTCR_EN [1/2]

#define SNVS_LPTDCR_SRTCR_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)

SRTCR_EN 0b0..SRTC rollover is disabled. 0b1..SRTC rollover is enabled.

◆ SNVS_LPTDCR_SRTCR_EN [2/2]

#define SNVS_LPTDCR_SRTCR_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)

SRTCR_EN 0b0..SRTC rollover is disabled. 0b1..SRTC rollover is enabled.

◆ SNVS_LPTDCR_TT_EN [1/2]

#define SNVS_LPTDCR_TT_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK)

TT_EN 0b0..Temperature tamper is disabled. 0b1..Temperature tamper is enabled.

◆ SNVS_LPTDCR_TT_EN [2/2]

#define SNVS_LPTDCR_TT_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK)

TT_EN 0b0..Temperature tamper is disabled. 0b1..Temperature tamper is enabled.

◆ SNVS_LPTDCR_VT_EN [1/2]

#define SNVS_LPTDCR_VT_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK)

VT_EN 0b0..Voltage tamper is disabled. 0b1..Voltage tamper is enabled.

◆ SNVS_LPTDCR_VT_EN [2/2]

#define SNVS_LPTDCR_VT_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK)

VT_EN 0b0..Voltage tamper is disabled. 0b1..Voltage tamper is enabled.

◆ SNVS_LPTDCR_WMT1_EN [1/2]

#define SNVS_LPTDCR_WMT1_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK)

WMT1_EN 0b0..Wire-mesh tamper 1 is disabled. 0b1..Wire-mesh tamper 1 is enabled.

◆ SNVS_LPTDCR_WMT1_EN [2/2]

#define SNVS_LPTDCR_WMT1_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK)

WMT1_EN 0b0..Wire-mesh tamper 1 is disabled. 0b1..Wire-mesh tamper 1 is enabled.

◆ SNVS_LPTDCR_WMT2_EN [1/2]

#define SNVS_LPTDCR_WMT2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK)

WMT2_EN 0b0..Wire-mesh tamper 2 is disabled. 0b1..Wire-mesh tamper 2 is enabled.

◆ SNVS_LPTDCR_WMT2_EN [2/2]

#define SNVS_LPTDCR_WMT2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK)

WMT2_EN 0b0..Wire-mesh tamper 2 is disabled. 0b1..Wire-mesh tamper 2 is enabled.

◆ SNVS_LPTDSR_ET10D [1/2]

#define SNVS_LPTDSR_ET10D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET10D_SHIFT)) & SNVS_LPTDSR_ET10D_MASK)

ET10D 0b0..External tamper 10 is not detected. 0b1..External tamper 10 is detected.

◆ SNVS_LPTDSR_ET10D [2/2]

#define SNVS_LPTDSR_ET10D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET10D_SHIFT)) & SNVS_LPTDSR_ET10D_MASK)

ET10D 0b0..External tamper 10 is not detected. 0b1..External tamper 10 is detected.

◆ SNVS_LPTDSR_ET3D [1/2]

#define SNVS_LPTDSR_ET3D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK)

ET3D 0b0..External tamper 3 is not detected. 0b1..External tamper 3 is detected.

◆ SNVS_LPTDSR_ET3D [2/2]

#define SNVS_LPTDSR_ET3D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK)

ET3D 0b0..External tamper 3 is not detected. 0b1..External tamper 3 is detected.

◆ SNVS_LPTDSR_ET4D [1/2]

#define SNVS_LPTDSR_ET4D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK)

ET4D 0b0..External tamper 4 is not detected. 0b1..External tamper 4 is detected.

◆ SNVS_LPTDSR_ET4D [2/2]

#define SNVS_LPTDSR_ET4D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK)

ET4D 0b0..External tamper 4 is not detected. 0b1..External tamper 4 is detected.

◆ SNVS_LPTDSR_ET5D [1/2]

#define SNVS_LPTDSR_ET5D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK)

ET5D 0b0..External tamper 5 is not detected. 0b1..External tamper 5 is detected.

◆ SNVS_LPTDSR_ET5D [2/2]

#define SNVS_LPTDSR_ET5D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK)

ET5D 0b0..External tamper 5 is not detected. 0b1..External tamper 5 is detected.

◆ SNVS_LPTDSR_ET6D [1/2]

#define SNVS_LPTDSR_ET6D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK)

ET6D 0b0..External tamper 6 is not detected. 0b1..External tamper 6 is detected.

◆ SNVS_LPTDSR_ET6D [2/2]

#define SNVS_LPTDSR_ET6D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK)

ET6D 0b0..External tamper 6 is not detected. 0b1..External tamper 6 is detected.

◆ SNVS_LPTDSR_ET7D [1/2]

#define SNVS_LPTDSR_ET7D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK)

ET7D 0b0..External tamper 7 is not detected. 0b1..External tamper 7 is detected.

◆ SNVS_LPTDSR_ET7D [2/2]

#define SNVS_LPTDSR_ET7D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK)

ET7D 0b0..External tamper 7 is not detected. 0b1..External tamper 7 is detected.

◆ SNVS_LPTDSR_ET8D [1/2]

#define SNVS_LPTDSR_ET8D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK)

ET8D 0b0..External tamper 8 is not detected. 0b1..External tamper 8 is detected.

◆ SNVS_LPTDSR_ET8D [2/2]

#define SNVS_LPTDSR_ET8D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK)

ET8D 0b0..External tamper 8 is not detected. 0b1..External tamper 8 is detected.

◆ SNVS_LPTDSR_ET9D [1/2]

#define SNVS_LPTDSR_ET9D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK)

ET9D 0b0..External tamper 9 is not detected. 0b1..External tamper 9 is detected.

◆ SNVS_LPTDSR_ET9D [2/2]

#define SNVS_LPTDSR_ET9D (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK)

ET9D 0b0..External tamper 9 is not detected. 0b1..External tamper 9 is detected.

◆ SNVS_LPTGF1CR_ETGF3_EN [1/2]

#define SNVS_LPTGF1CR_ETGF3_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK)

ETGF3_EN 0b0..External tamper glitch filter 3 is bypassed. 0b1..External tamper glitch filter 3 is enabled.

◆ SNVS_LPTGF1CR_ETGF3_EN [2/2]

#define SNVS_LPTGF1CR_ETGF3_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK)

ETGF3_EN 0b0..External tamper glitch filter 3 is bypassed. 0b1..External tamper glitch filter 3 is enabled.

◆ SNVS_LPTGF1CR_ETGF4_EN [1/2]

#define SNVS_LPTGF1CR_ETGF4_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK)

ETGF4_EN 0b0..External tamper glitch filter 4 is bypassed. 0b1..External tamper glitch filter 4 is enabled.

◆ SNVS_LPTGF1CR_ETGF4_EN [2/2]

#define SNVS_LPTGF1CR_ETGF4_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK)

ETGF4_EN 0b0..External tamper glitch filter 4 is bypassed. 0b1..External tamper glitch filter 4 is enabled.

◆ SNVS_LPTGF1CR_ETGF5_EN [1/2]

#define SNVS_LPTGF1CR_ETGF5_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK)

ETGF5_EN 0b0..External tamper glitch filter 5 is bypassed. 0b1..External tamper glitch filter 5 is enabled.

◆ SNVS_LPTGF1CR_ETGF5_EN [2/2]

#define SNVS_LPTGF1CR_ETGF5_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK)

ETGF5_EN 0b0..External tamper glitch filter 5 is bypassed. 0b1..External tamper glitch filter 5 is enabled.

◆ SNVS_LPTGF1CR_ETGF6_EN [1/2]

#define SNVS_LPTGF1CR_ETGF6_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF6_EN_MASK)

ETGF6_EN 0b0..External tamper glitch filter 6 is bypassed. 0b1..External tamper glitch filter 6 is enabled.

◆ SNVS_LPTGF1CR_ETGF6_EN [2/2]

#define SNVS_LPTGF1CR_ETGF6_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF6_EN_MASK)

ETGF6_EN 0b0..External tamper glitch filter 6 is bypassed. 0b1..External tamper glitch filter 6 is enabled.

◆ SNVS_LPTGF2CR_ETGF10_EN [1/2]

#define SNVS_LPTGF2CR_ETGF10_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF10_EN_MASK)

ETGF10_EN 0b0..External tamper glitch filter 10 is bypassed. 0b1..External tamper glitch filter 10 is enabled.

◆ SNVS_LPTGF2CR_ETGF10_EN [2/2]

#define SNVS_LPTGF2CR_ETGF10_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF10_EN_MASK)

ETGF10_EN 0b0..External tamper glitch filter 10 is bypassed. 0b1..External tamper glitch filter 10 is enabled.

◆ SNVS_LPTGF2CR_ETGF7_EN [1/2]

#define SNVS_LPTGF2CR_ETGF7_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK)

ETGF7_EN 0b0..External tamper glitch filter 7 is bypassed. 0b1..External tamper glitch filter 7 is enabled.

◆ SNVS_LPTGF2CR_ETGF7_EN [2/2]

#define SNVS_LPTGF2CR_ETGF7_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK)

ETGF7_EN 0b0..External tamper glitch filter 7 is bypassed. 0b1..External tamper glitch filter 7 is enabled.

◆ SNVS_LPTGF2CR_ETGF8_EN [1/2]

#define SNVS_LPTGF2CR_ETGF8_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK)

ETGF8_EN 0b0..External tamper glitch filter 8 is bypassed. 0b1..External tamper glitch filter 8 is enabled.

◆ SNVS_LPTGF2CR_ETGF8_EN [2/2]

#define SNVS_LPTGF2CR_ETGF8_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK)

ETGF8_EN 0b0..External tamper glitch filter 8 is bypassed. 0b1..External tamper glitch filter 8 is enabled.

◆ SNVS_LPTGF2CR_ETGF9_EN [1/2]

#define SNVS_LPTGF2CR_ETGF9_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK)

ETGF9_EN 0b0..External tamper glitch filter 9 is bypassed. 0b1..External tamper glitch filter 9 is enabled.

◆ SNVS_LPTGF2CR_ETGF9_EN [2/2]

#define SNVS_LPTGF2CR_ETGF9_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK)

ETGF9_EN 0b0..External tamper glitch filter 9 is bypassed. 0b1..External tamper glitch filter 9 is enabled.

◆ SNVS_LPTGFCR_ETGF1_EN [1/2]

#define SNVS_LPTGFCR_ETGF1_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK)

ETGF1_EN 0b0..External tamper glitch filter 1 is bypassed. 0b1..External tamper glitch filter 1 is enabled.

◆ SNVS_LPTGFCR_ETGF1_EN [2/2]

#define SNVS_LPTGFCR_ETGF1_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK)

ETGF1_EN 0b0..External tamper glitch filter 1 is bypassed. 0b1..External tamper glitch filter 1 is enabled.

◆ SNVS_LPTGFCR_ETGF2_EN [1/2]

#define SNVS_LPTGFCR_ETGF2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_EN_SHIFT)) & SNVS_LPTGFCR_ETGF2_EN_MASK)

ETGF2_EN 0b0..External tamper glitch filter 2 is bypassed. 0b1..External tamper glitch filter 2 is enabled.

◆ SNVS_LPTGFCR_ETGF2_EN [2/2]

#define SNVS_LPTGFCR_ETGF2_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_EN_SHIFT)) & SNVS_LPTGFCR_ETGF2_EN_MASK)

ETGF2_EN 0b0..External tamper glitch filter 2 is bypassed. 0b1..External tamper glitch filter 2 is enabled.

◆ SNVS_LPTGFCR_WMTGF_EN [1/2]

#define SNVS_LPTGFCR_WMTGF_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK)

WMTGF_EN 0b0..Wire-mesh tamper glitch filter is bypassed. 0b1..Wire-mesh tamper glitch filter is enabled.

◆ SNVS_LPTGFCR_WMTGF_EN [2/2]

#define SNVS_LPTGFCR_WMTGF_EN (   x)    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK)

WMTGF_EN 0b0..Wire-mesh tamper glitch filter is bypassed. 0b1..Wire-mesh tamper glitch filter is enabled.

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