CTRL - Control Register 0
#define	PXP_CTRL_ENABLE_MASK (0x1U)

#define	PXP_CTRL_ENABLE_SHIFT (0U)

#define	PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)

#define	PXP_CTRL_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)

#define	PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_ROTATE_MASK (0x300U)

#define	PXP_CTRL_ROTATE_SHIFT (8U)

#define	PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)

#define	PXP_CTRL_HFLIP_MASK (0x400U)

#define	PXP_CTRL_HFLIP_SHIFT (10U)

#define	PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)

#define	PXP_CTRL_VFLIP_MASK (0x800U)

#define	PXP_CTRL_VFLIP_SHIFT (11U)

#define	PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)

#define	PXP_CTRL_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)

#define	PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)

#define	PXP_CTRL_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)

#define	PXP_CTRL_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)

#define	PXP_CTRL_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_SFTRST_SHIFT (31U)

#define	PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)

CTRL_SET - Control Register 0
#define	PXP_CTRL_SET_ENABLE_MASK (0x1U)

#define	PXP_CTRL_SET_ENABLE_SHIFT (0U)

#define	PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)

#define	PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)

#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_SET_ROTATE_MASK (0x300U)

#define	PXP_CTRL_SET_ROTATE_SHIFT (8U)

#define	PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)

#define	PXP_CTRL_SET_HFLIP_MASK (0x400U)

#define	PXP_CTRL_SET_HFLIP_SHIFT (10U)

#define	PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)

#define	PXP_CTRL_SET_VFLIP_MASK (0x800U)

#define	PXP_CTRL_SET_VFLIP_SHIFT (11U)

#define	PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)

#define	PXP_CTRL_SET_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_SET_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)

#define	PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)

#define	PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)

#define	PXP_CTRL_SET_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_SET_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)

#define	PXP_CTRL_SET_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_SET_SFTRST_SHIFT (31U)

#define	PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)

CTRL_CLR - Control Register 0
#define	PXP_CTRL_CLR_ENABLE_MASK (0x1U)

#define	PXP_CTRL_CLR_ENABLE_SHIFT (0U)

#define	PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)

#define	PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)

#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_CLR_ROTATE_MASK (0x300U)

#define	PXP_CTRL_CLR_ROTATE_SHIFT (8U)

#define	PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)

#define	PXP_CTRL_CLR_HFLIP_MASK (0x400U)

#define	PXP_CTRL_CLR_HFLIP_SHIFT (10U)

#define	PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)

#define	PXP_CTRL_CLR_VFLIP_MASK (0x800U)

#define	PXP_CTRL_CLR_VFLIP_SHIFT (11U)

#define	PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)

#define	PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_CLR_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)

#define	PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)

#define	PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)

#define	PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_CLR_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)

#define	PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_CLR_SFTRST_SHIFT (31U)

#define	PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)

CTRL_TOG - Control Register 0
#define	PXP_CTRL_TOG_ENABLE_MASK (0x1U)

#define	PXP_CTRL_TOG_ENABLE_SHIFT (0U)

#define	PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)

#define	PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)

#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_TOG_ROTATE_MASK (0x300U)

#define	PXP_CTRL_TOG_ROTATE_SHIFT (8U)

#define	PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)

#define	PXP_CTRL_TOG_HFLIP_MASK (0x400U)

#define	PXP_CTRL_TOG_HFLIP_SHIFT (10U)

#define	PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)

#define	PXP_CTRL_TOG_VFLIP_MASK (0x800U)

#define	PXP_CTRL_TOG_VFLIP_SHIFT (11U)

#define	PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)

#define	PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_TOG_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)

#define	PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)

#define	PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)

#define	PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_TOG_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)

#define	PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_TOG_SFTRST_SHIFT (31U)

#define	PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)

STAT - Status Register
#define	PXP_STAT_IRQ_MASK (0x1U)

#define	PXP_STAT_IRQ_SHIFT (0U)

#define	PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)

#define	PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)

#define	PXP_STAT_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)

#define	PXP_STAT_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)

#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_BLOCKY_SHIFT (16U)

#define	PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)

#define	PXP_STAT_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_BLOCKX_SHIFT (24U)

#define	PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)

STAT_SET - Status Register
#define	PXP_STAT_SET_IRQ_MASK (0x1U)

#define	PXP_STAT_SET_IRQ_SHIFT (0U)

#define	PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)

#define	PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)

#define	PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)

#define	PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)

#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_SET_BLOCKY_SHIFT (16U)

#define	PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)

#define	PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_SET_BLOCKX_SHIFT (24U)

#define	PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)

STAT_CLR - Status Register
#define	PXP_STAT_CLR_IRQ_MASK (0x1U)

#define	PXP_STAT_CLR_IRQ_SHIFT (0U)

#define	PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)

#define	PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)

#define	PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)

#define	PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)

#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_CLR_BLOCKY_SHIFT (16U)

#define	PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)

#define	PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_CLR_BLOCKX_SHIFT (24U)

#define	PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)

STAT_TOG - Status Register
#define	PXP_STAT_TOG_IRQ_MASK (0x1U)

#define	PXP_STAT_TOG_IRQ_SHIFT (0U)

#define	PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)

#define	PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)

#define	PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)

#define	PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)

#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_TOG_BLOCKY_SHIFT (16U)

#define	PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)

#define	PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_TOG_BLOCKX_SHIFT (24U)

#define	PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)

OUT_CTRL - Output Buffer Control Register
#define	PXP_OUT_CTRL_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)

#define	PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)

OUT_CTRL_SET - Output Buffer Control Register
#define	PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)

#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)

OUT_CTRL_CLR - Output Buffer Control Register
#define	PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)

#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)

OUT_CTRL_TOG - Output Buffer Control Register
#define	PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)

#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)

OUT_BUF - Output Frame Buffer Pointer
#define	PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_OUT_BUF_ADDR_SHIFT (0U)

#define	PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)

OUT_BUF2 - Output Frame Buffer Pointer #2
#define	PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_OUT_BUF2_ADDR_SHIFT (0U)

#define	PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)

OUT_PITCH - Output Buffer Pitch
#define	PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)

#define	PXP_OUT_PITCH_PITCH_SHIFT (0U)

#define	PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)

OUT_LRC - Output Surface Lower Right Coordinate
#define	PXP_OUT_LRC_Y_MASK (0x3FFFU)

#define	PXP_OUT_LRC_Y_SHIFT (0U)

#define	PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)

#define	PXP_OUT_LRC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_LRC_X_SHIFT (16U)

#define	PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)

OUT_PS_ULC - Processed Surface Upper Left Coordinate
#define	PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)

#define	PXP_OUT_PS_ULC_Y_SHIFT (0U)

#define	PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)

#define	PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_PS_ULC_X_SHIFT (16U)

#define	PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)

OUT_PS_LRC - Processed Surface Lower Right Coordinate
#define	PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)

#define	PXP_OUT_PS_LRC_Y_SHIFT (0U)

#define	PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)

#define	PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_PS_LRC_X_SHIFT (16U)

#define	PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)

OUT_AS_ULC - Alpha Surface Upper Left Coordinate
#define	PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)

#define	PXP_OUT_AS_ULC_Y_SHIFT (0U)

#define	PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)

#define	PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_AS_ULC_X_SHIFT (16U)

#define	PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)

OUT_AS_LRC - Alpha Surface Lower Right Coordinate
#define	PXP_OUT_AS_LRC_Y_MASK (0x3FFFU)

#define	PXP_OUT_AS_LRC_Y_SHIFT (0U)

#define	PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)

#define	PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_AS_LRC_X_SHIFT (16U)

#define	PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)

PS_CTRL - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)

#define	PXP_PS_CTRL_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)

#define	PXP_PS_CTRL_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)

#define	PXP_PS_CTRL_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)

PS_CTRL_SET - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)

#define	PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)

#define	PXP_PS_CTRL_SET_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_SET_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)

#define	PXP_PS_CTRL_SET_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_SET_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)

PS_CTRL_CLR - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)

#define	PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)

#define	PXP_PS_CTRL_CLR_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_CLR_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)

#define	PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_CLR_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)

PS_CTRL_TOG - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)

#define	PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)

#define	PXP_PS_CTRL_TOG_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_TOG_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)

#define	PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_TOG_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)

PS_BUF - PS Input Buffer Address
#define	PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_PS_BUF_ADDR_SHIFT (0U)

#define	PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)

PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address
#define	PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_PS_UBUF_ADDR_SHIFT (0U)

#define	PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)

PS_VBUF - PS V/Cr Input Buffer Address
#define	PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_PS_VBUF_ADDR_SHIFT (0U)

#define	PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)

PS_PITCH - Processed Surface Pitch
#define	PXP_PS_PITCH_PITCH_MASK (0xFFFFU)

#define	PXP_PS_PITCH_PITCH_SHIFT (0U)

#define	PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)

PS_BACKGROUND - PS Background Color
#define	PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)

#define	PXP_PS_BACKGROUND_COLOR_SHIFT (0U)

#define	PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)

PS_SCALE - PS Scale Factor Register
#define	PXP_PS_SCALE_XSCALE_MASK (0x7FFFU)

#define	PXP_PS_SCALE_XSCALE_SHIFT (0U)

#define	PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)

#define	PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)

#define	PXP_PS_SCALE_YSCALE_SHIFT (16U)

#define	PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)

PS_OFFSET - PS Scale Offset Register
#define	PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)

#define	PXP_PS_OFFSET_XOFFSET_SHIFT (0U)

#define	PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)

#define	PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)

#define	PXP_PS_OFFSET_YOFFSET_SHIFT (16U)

#define	PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)

PS_CLRKEYLOW - PS Color Key Low
#define	PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)

#define	PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)

#define	PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)

PS_CLRKEYHIGH - PS Color Key High
#define	PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)

#define	PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)

#define	PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)

AS_CTRL - Alpha Surface Control
#define	PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)

#define	PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)

#define	PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)

#define	PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)

#define	PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)

#define	PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)

#define	PXP_AS_CTRL_FORMAT_MASK (0xF0U)

#define	PXP_AS_CTRL_FORMAT_SHIFT (4U)

#define	PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)

#define	PXP_AS_CTRL_ALPHA_MASK (0xFF00U)

#define	PXP_AS_CTRL_ALPHA_SHIFT (8U)

#define	PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)

#define	PXP_AS_CTRL_ROP_MASK (0xF0000U)

#define	PXP_AS_CTRL_ROP_SHIFT (16U)

#define	PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)

#define	PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)

#define	PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)

#define	PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)

AS_BUF - Alpha Surface Buffer Pointer
#define	PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_AS_BUF_ADDR_SHIFT (0U)

#define	PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)

AS_PITCH - Alpha Surface Pitch
#define	PXP_AS_PITCH_PITCH_MASK (0xFFFFU)

#define	PXP_AS_PITCH_PITCH_SHIFT (0U)

#define	PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)

AS_CLRKEYLOW - Overlay Color Key Low
#define	PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)

#define	PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)

#define	PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)

AS_CLRKEYHIGH - Overlay Color Key High
#define	PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)

#define	PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)

#define	PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)

CSC1_COEF0 - Color Space Conversion Coefficient Register 0
#define	PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)

#define	PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)

#define	PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)

#define	PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)

#define	PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)

#define	PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)

#define	PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)

#define	PXP_CSC1_COEF0_C0_SHIFT (18U)

#define	PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)

#define	PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)

#define	PXP_CSC1_COEF0_BYPASS_SHIFT (30U)

#define	PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)

#define	PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)

#define	PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)

#define	PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)

CSC1_COEF1 - Color Space Conversion Coefficient Register 1
#define	PXP_CSC1_COEF1_C4_MASK (0x7FFU)

#define	PXP_CSC1_COEF1_C4_SHIFT (0U)

#define	PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)

#define	PXP_CSC1_COEF1_C1_MASK (0x7FF0000U)

#define	PXP_CSC1_COEF1_C1_SHIFT (16U)

#define	PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)

CSC1_COEF2 - Color Space Conversion Coefficient Register 2
#define	PXP_CSC1_COEF2_C3_MASK (0x7FFU)

#define	PXP_CSC1_COEF2_C3_SHIFT (0U)

#define	PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)

#define	PXP_CSC1_COEF2_C2_MASK (0x7FF0000U)

#define	PXP_CSC1_COEF2_C2_SHIFT (16U)

#define	PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)

POWER - PXP Power Control Register
#define	PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)

#define	PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)

#define	PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)

#define	PXP_POWER_CTRL_MASK (0xFFFFF000U)

#define	PXP_POWER_CTRL_SHIFT (12U)

#define	PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK)

NEXT - Next Frame Pointer
#define	PXP_NEXT_ENABLED_MASK (0x1U)

#define	PXP_NEXT_ENABLED_SHIFT (0U)

#define	PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)

#define	PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)

#define	PXP_NEXT_POINTER_SHIFT (2U)

#define	PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)

PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register.
#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)

#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)

#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)

#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)

#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)

#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)

#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)

#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)

#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)

#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)

#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)

#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)

#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)

#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)

#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)

CTRL - Control Register 0
#define	PXP_CTRL_ENABLE_MASK (0x1U)

#define	PXP_CTRL_ENABLE_SHIFT (0U)

#define	PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)

#define	PXP_CTRL_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)

#define	PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_ROTATE_MASK (0x300U)

#define	PXP_CTRL_ROTATE_SHIFT (8U)

#define	PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)

#define	PXP_CTRL_HFLIP_MASK (0x400U)

#define	PXP_CTRL_HFLIP_SHIFT (10U)

#define	PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)

#define	PXP_CTRL_VFLIP_MASK (0x800U)

#define	PXP_CTRL_VFLIP_SHIFT (11U)

#define	PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)

#define	PXP_CTRL_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)

#define	PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)

#define	PXP_CTRL_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)

#define	PXP_CTRL_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)

#define	PXP_CTRL_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_SFTRST_SHIFT (31U)

#define	PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)

CTRL_SET - Control Register 0
#define	PXP_CTRL_SET_ENABLE_MASK (0x1U)

#define	PXP_CTRL_SET_ENABLE_SHIFT (0U)

#define	PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)

#define	PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)

#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_SET_ROTATE_MASK (0x300U)

#define	PXP_CTRL_SET_ROTATE_SHIFT (8U)

#define	PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)

#define	PXP_CTRL_SET_HFLIP_MASK (0x400U)

#define	PXP_CTRL_SET_HFLIP_SHIFT (10U)

#define	PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)

#define	PXP_CTRL_SET_VFLIP_MASK (0x800U)

#define	PXP_CTRL_SET_VFLIP_SHIFT (11U)

#define	PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)

#define	PXP_CTRL_SET_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_SET_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)

#define	PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)

#define	PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)

#define	PXP_CTRL_SET_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_SET_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)

#define	PXP_CTRL_SET_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_SET_SFTRST_SHIFT (31U)

#define	PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)

CTRL_CLR - Control Register 0
#define	PXP_CTRL_CLR_ENABLE_MASK (0x1U)

#define	PXP_CTRL_CLR_ENABLE_SHIFT (0U)

#define	PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)

#define	PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)

#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_CLR_ROTATE_MASK (0x300U)

#define	PXP_CTRL_CLR_ROTATE_SHIFT (8U)

#define	PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)

#define	PXP_CTRL_CLR_HFLIP_MASK (0x400U)

#define	PXP_CTRL_CLR_HFLIP_SHIFT (10U)

#define	PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)

#define	PXP_CTRL_CLR_VFLIP_MASK (0x800U)

#define	PXP_CTRL_CLR_VFLIP_SHIFT (11U)

#define	PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)

#define	PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_CLR_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)

#define	PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)

#define	PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)

#define	PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_CLR_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)

#define	PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_CLR_SFTRST_SHIFT (31U)

#define	PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)

CTRL_TOG - Control Register 0
#define	PXP_CTRL_TOG_ENABLE_MASK (0x1U)

#define	PXP_CTRL_TOG_ENABLE_SHIFT (0U)

#define	PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)

#define	PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)

#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_TOG_ROTATE_MASK (0x300U)

#define	PXP_CTRL_TOG_ROTATE_SHIFT (8U)

#define	PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)

#define	PXP_CTRL_TOG_HFLIP_MASK (0x400U)

#define	PXP_CTRL_TOG_HFLIP_SHIFT (10U)

#define	PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)

#define	PXP_CTRL_TOG_VFLIP_MASK (0x800U)

#define	PXP_CTRL_TOG_VFLIP_SHIFT (11U)

#define	PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)

#define	PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_TOG_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)

#define	PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)

#define	PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)

#define	PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_TOG_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)

#define	PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_TOG_SFTRST_SHIFT (31U)

#define	PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)

STAT - Status Register
#define	PXP_STAT_IRQ_MASK (0x1U)

#define	PXP_STAT_IRQ_SHIFT (0U)

#define	PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)

#define	PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)

#define	PXP_STAT_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)

#define	PXP_STAT_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)

#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_BLOCKY_SHIFT (16U)

#define	PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)

#define	PXP_STAT_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_BLOCKX_SHIFT (24U)

#define	PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)

STAT_SET - Status Register
#define	PXP_STAT_SET_IRQ_MASK (0x1U)

#define	PXP_STAT_SET_IRQ_SHIFT (0U)

#define	PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)

#define	PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)

#define	PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)

#define	PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)

#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_SET_BLOCKY_SHIFT (16U)

#define	PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)

#define	PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_SET_BLOCKX_SHIFT (24U)

#define	PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)

STAT_CLR - Status Register
#define	PXP_STAT_CLR_IRQ_MASK (0x1U)

#define	PXP_STAT_CLR_IRQ_SHIFT (0U)

#define	PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)

#define	PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)

#define	PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)

#define	PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)

#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_CLR_BLOCKY_SHIFT (16U)

#define	PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)

#define	PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_CLR_BLOCKX_SHIFT (24U)

#define	PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)

STAT_TOG - Status Register
#define	PXP_STAT_TOG_IRQ_MASK (0x1U)

#define	PXP_STAT_TOG_IRQ_SHIFT (0U)

#define	PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)

#define	PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)

#define	PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)

#define	PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)

#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_TOG_BLOCKY_SHIFT (16U)

#define	PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)

#define	PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_TOG_BLOCKX_SHIFT (24U)

#define	PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)

OUT_CTRL - Output Buffer Control Register
#define	PXP_OUT_CTRL_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)

#define	PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)

OUT_CTRL_SET - Output Buffer Control Register
#define	PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)

#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)

OUT_CTRL_CLR - Output Buffer Control Register
#define	PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)

#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)

OUT_CTRL_TOG - Output Buffer Control Register
#define	PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)

#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)

OUT_BUF - Output Frame Buffer Pointer
#define	PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_OUT_BUF_ADDR_SHIFT (0U)

#define	PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)

OUT_BUF2 - Output Frame Buffer Pointer #2
#define	PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_OUT_BUF2_ADDR_SHIFT (0U)

#define	PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)

OUT_PITCH - Output Buffer Pitch
#define	PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)

#define	PXP_OUT_PITCH_PITCH_SHIFT (0U)

#define	PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)

OUT_LRC - Output Surface Lower Right Coordinate
#define	PXP_OUT_LRC_Y_MASK (0x3FFFU)

#define	PXP_OUT_LRC_Y_SHIFT (0U)

#define	PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)

#define	PXP_OUT_LRC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_LRC_X_SHIFT (16U)

#define	PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)

OUT_PS_ULC - Processed Surface Upper Left Coordinate
#define	PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)

#define	PXP_OUT_PS_ULC_Y_SHIFT (0U)

#define	PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)

#define	PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_PS_ULC_X_SHIFT (16U)

#define	PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)

OUT_PS_LRC - Processed Surface Lower Right Coordinate
#define	PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)

#define	PXP_OUT_PS_LRC_Y_SHIFT (0U)

#define	PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)

#define	PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_PS_LRC_X_SHIFT (16U)

#define	PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)

OUT_AS_ULC - Alpha Surface Upper Left Coordinate
#define	PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)

#define	PXP_OUT_AS_ULC_Y_SHIFT (0U)

#define	PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)

#define	PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_AS_ULC_X_SHIFT (16U)

#define	PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)

OUT_AS_LRC - Alpha Surface Lower Right Coordinate
#define	PXP_OUT_AS_LRC_Y_MASK (0x3FFFU)

#define	PXP_OUT_AS_LRC_Y_SHIFT (0U)

#define	PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)

#define	PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_AS_LRC_X_SHIFT (16U)

#define	PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)

PS_CTRL - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)

#define	PXP_PS_CTRL_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)

#define	PXP_PS_CTRL_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)

#define	PXP_PS_CTRL_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)

PS_CTRL_SET - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)

#define	PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)

#define	PXP_PS_CTRL_SET_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_SET_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)

#define	PXP_PS_CTRL_SET_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_SET_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)

PS_CTRL_CLR - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)

#define	PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)

#define	PXP_PS_CTRL_CLR_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_CLR_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)

#define	PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_CLR_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)

PS_CTRL_TOG - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)

#define	PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)

#define	PXP_PS_CTRL_TOG_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_TOG_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)

#define	PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_TOG_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)

PS_BUF - PS Input Buffer Address
#define	PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_PS_BUF_ADDR_SHIFT (0U)

#define	PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)

PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address
#define	PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_PS_UBUF_ADDR_SHIFT (0U)

#define	PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)

PS_VBUF - PS V/Cr Input Buffer Address
#define	PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_PS_VBUF_ADDR_SHIFT (0U)

#define	PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)

PS_PITCH - Processed Surface Pitch
#define	PXP_PS_PITCH_PITCH_MASK (0xFFFFU)

#define	PXP_PS_PITCH_PITCH_SHIFT (0U)

#define	PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)

PS_BACKGROUND - PS Background Color
#define	PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)

#define	PXP_PS_BACKGROUND_COLOR_SHIFT (0U)

#define	PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)

PS_SCALE - PS Scale Factor Register
#define	PXP_PS_SCALE_XSCALE_MASK (0x7FFFU)

#define	PXP_PS_SCALE_XSCALE_SHIFT (0U)

#define	PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)

#define	PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)

#define	PXP_PS_SCALE_YSCALE_SHIFT (16U)

#define	PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)

PS_OFFSET - PS Scale Offset Register
#define	PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)

#define	PXP_PS_OFFSET_XOFFSET_SHIFT (0U)

#define	PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)

#define	PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)

#define	PXP_PS_OFFSET_YOFFSET_SHIFT (16U)

#define	PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)

PS_CLRKEYLOW - PS Color Key Low
#define	PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)

#define	PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)

#define	PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)

PS_CLRKEYHIGH - PS Color Key High
#define	PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)

#define	PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)

#define	PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)

AS_CTRL - Alpha Surface Control
#define	PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)

#define	PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)

#define	PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)

#define	PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)

#define	PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)

#define	PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)

#define	PXP_AS_CTRL_FORMAT_MASK (0xF0U)

#define	PXP_AS_CTRL_FORMAT_SHIFT (4U)

#define	PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)

#define	PXP_AS_CTRL_ALPHA_MASK (0xFF00U)

#define	PXP_AS_CTRL_ALPHA_SHIFT (8U)

#define	PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)

#define	PXP_AS_CTRL_ROP_MASK (0xF0000U)

#define	PXP_AS_CTRL_ROP_SHIFT (16U)

#define	PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)

#define	PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)

#define	PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)

#define	PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)

AS_BUF - Alpha Surface Buffer Pointer
#define	PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_AS_BUF_ADDR_SHIFT (0U)

#define	PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)

AS_PITCH - Alpha Surface Pitch
#define	PXP_AS_PITCH_PITCH_MASK (0xFFFFU)

#define	PXP_AS_PITCH_PITCH_SHIFT (0U)

#define	PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)

AS_CLRKEYLOW - Overlay Color Key Low
#define	PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)

#define	PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)

#define	PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)

AS_CLRKEYHIGH - Overlay Color Key High
#define	PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)

#define	PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)

#define	PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)

CSC1_COEF0 - Color Space Conversion Coefficient Register 0
#define	PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)

#define	PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)

#define	PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)

#define	PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)

#define	PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)

#define	PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)

#define	PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)

#define	PXP_CSC1_COEF0_C0_SHIFT (18U)

#define	PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)

#define	PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)

#define	PXP_CSC1_COEF0_BYPASS_SHIFT (30U)

#define	PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)

#define	PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)

#define	PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)

#define	PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)

CSC1_COEF1 - Color Space Conversion Coefficient Register 1
#define	PXP_CSC1_COEF1_C4_MASK (0x7FFU)

#define	PXP_CSC1_COEF1_C4_SHIFT (0U)

#define	PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)

#define	PXP_CSC1_COEF1_C1_MASK (0x7FF0000U)

#define	PXP_CSC1_COEF1_C1_SHIFT (16U)

#define	PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)

CSC1_COEF2 - Color Space Conversion Coefficient Register 2
#define	PXP_CSC1_COEF2_C3_MASK (0x7FFU)

#define	PXP_CSC1_COEF2_C3_SHIFT (0U)

#define	PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)

#define	PXP_CSC1_COEF2_C2_MASK (0x7FF0000U)

#define	PXP_CSC1_COEF2_C2_SHIFT (16U)

#define	PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)

POWER - PXP Power Control Register
#define	PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)

#define	PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)

#define	PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)

NEXT - Next Frame Pointer
#define	PXP_NEXT_ENABLED_MASK (0x1U)

#define	PXP_NEXT_ENABLED_SHIFT (0U)

#define	PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)

#define	PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)

#define	PXP_NEXT_POINTER_SHIFT (2U)

#define	PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)

PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register.
#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)

#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)

#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)

#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)

#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)

#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)

#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)

#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)

#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)

#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)

#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)

#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)

#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)

#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)

#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)

CTRL - Control Register 0
#define	PXP_CTRL_ENABLE_MASK (0x1U)

#define	PXP_CTRL_ENABLE_SHIFT (0U)

#define	PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)

#define	PXP_CTRL_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)

#define	PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_ROTATE_MASK (0x300U)

#define	PXP_CTRL_ROTATE_SHIFT (8U)

#define	PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)

#define	PXP_CTRL_HFLIP_MASK (0x400U)

#define	PXP_CTRL_HFLIP_SHIFT (10U)

#define	PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)

#define	PXP_CTRL_VFLIP_MASK (0x800U)

#define	PXP_CTRL_VFLIP_SHIFT (11U)

#define	PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)

#define	PXP_CTRL_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)

#define	PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)

#define	PXP_CTRL_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)

#define	PXP_CTRL_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)

#define	PXP_CTRL_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_SFTRST_SHIFT (31U)

#define	PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)

CTRL_SET - Control Register 0
#define	PXP_CTRL_SET_ENABLE_MASK (0x1U)

#define	PXP_CTRL_SET_ENABLE_SHIFT (0U)

#define	PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)

#define	PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)

#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_SET_ROTATE_MASK (0x300U)

#define	PXP_CTRL_SET_ROTATE_SHIFT (8U)

#define	PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)

#define	PXP_CTRL_SET_HFLIP_MASK (0x400U)

#define	PXP_CTRL_SET_HFLIP_SHIFT (10U)

#define	PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)

#define	PXP_CTRL_SET_VFLIP_MASK (0x800U)

#define	PXP_CTRL_SET_VFLIP_SHIFT (11U)

#define	PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)

#define	PXP_CTRL_SET_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_SET_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)

#define	PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)

#define	PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)

#define	PXP_CTRL_SET_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_SET_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)

#define	PXP_CTRL_SET_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_SET_SFTRST_SHIFT (31U)

#define	PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)

CTRL_CLR - Control Register 0
#define	PXP_CTRL_CLR_ENABLE_MASK (0x1U)

#define	PXP_CTRL_CLR_ENABLE_SHIFT (0U)

#define	PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)

#define	PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)

#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_CLR_ROTATE_MASK (0x300U)

#define	PXP_CTRL_CLR_ROTATE_SHIFT (8U)

#define	PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)

#define	PXP_CTRL_CLR_HFLIP_MASK (0x400U)

#define	PXP_CTRL_CLR_HFLIP_SHIFT (10U)

#define	PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)

#define	PXP_CTRL_CLR_VFLIP_MASK (0x800U)

#define	PXP_CTRL_CLR_VFLIP_SHIFT (11U)

#define	PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)

#define	PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_CLR_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)

#define	PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)

#define	PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)

#define	PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_CLR_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)

#define	PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_CLR_SFTRST_SHIFT (31U)

#define	PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)

CTRL_TOG - Control Register 0
#define	PXP_CTRL_TOG_ENABLE_MASK (0x1U)

#define	PXP_CTRL_TOG_ENABLE_SHIFT (0U)

#define	PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)

#define	PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)

#define	PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)

#define	PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)

#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)

#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)

#define	PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)

#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)

#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)

#define	PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)

#define	PXP_CTRL_TOG_ROTATE_MASK (0x300U)

#define	PXP_CTRL_TOG_ROTATE_SHIFT (8U)

#define	PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)

#define	PXP_CTRL_TOG_HFLIP_MASK (0x400U)

#define	PXP_CTRL_TOG_HFLIP_SHIFT (10U)

#define	PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)

#define	PXP_CTRL_TOG_VFLIP_MASK (0x800U)

#define	PXP_CTRL_TOG_VFLIP_SHIFT (11U)

#define	PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)

#define	PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)

#define	PXP_CTRL_TOG_ROT_POS_SHIFT (22U)

#define	PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)

#define	PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)

#define	PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)

#define	PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)

#define	PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)

#define	PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)

#define	PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)

#define	PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)

#define	PXP_CTRL_TOG_CLKGATE_SHIFT (30U)

#define	PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)

#define	PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)

#define	PXP_CTRL_TOG_SFTRST_SHIFT (31U)

#define	PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)

STAT - Status Register
#define	PXP_STAT_IRQ_MASK (0x1U)

#define	PXP_STAT_IRQ_SHIFT (0U)

#define	PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)

#define	PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)

#define	PXP_STAT_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)

#define	PXP_STAT_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)

#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_BLOCKY_SHIFT (16U)

#define	PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)

#define	PXP_STAT_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_BLOCKX_SHIFT (24U)

#define	PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)

STAT_SET - Status Register
#define	PXP_STAT_SET_IRQ_MASK (0x1U)

#define	PXP_STAT_SET_IRQ_SHIFT (0U)

#define	PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)

#define	PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)

#define	PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)

#define	PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)

#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_SET_BLOCKY_SHIFT (16U)

#define	PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)

#define	PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_SET_BLOCKX_SHIFT (24U)

#define	PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)

STAT_CLR - Status Register
#define	PXP_STAT_CLR_IRQ_MASK (0x1U)

#define	PXP_STAT_CLR_IRQ_SHIFT (0U)

#define	PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)

#define	PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)

#define	PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)

#define	PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)

#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_CLR_BLOCKY_SHIFT (16U)

#define	PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)

#define	PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_CLR_BLOCKX_SHIFT (24U)

#define	PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)

STAT_TOG - Status Register
#define	PXP_STAT_TOG_IRQ_MASK (0x1U)

#define	PXP_STAT_TOG_IRQ_SHIFT (0U)

#define	PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)

#define	PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)

#define	PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)

#define	PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)

#define	PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)

#define	PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)

#define	PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)

#define	PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)

#define	PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)

#define	PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)

#define	PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)

#define	PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)

#define	PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)

#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)

#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)

#define	PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)

#define	PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)

#define	PXP_STAT_TOG_BLOCKY_SHIFT (16U)

#define	PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)

#define	PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)

#define	PXP_STAT_TOG_BLOCKX_SHIFT (24U)

#define	PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)

OUT_CTRL - Output Buffer Control Register
#define	PXP_OUT_CTRL_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)

#define	PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)

OUT_CTRL_SET - Output Buffer Control Register
#define	PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)

#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)

OUT_CTRL_CLR - Output Buffer Control Register
#define	PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)

#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)

OUT_CTRL_TOG - Output Buffer Control Register
#define	PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)

#define	PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)

#define	PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)

#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)

#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)

#define	PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)

#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)

#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)

#define	PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)

#define	PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)

#define	PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)

#define	PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)

OUT_BUF - Output Frame Buffer Pointer
#define	PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_OUT_BUF_ADDR_SHIFT (0U)

#define	PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)

OUT_BUF2 - Output Frame Buffer Pointer #2
#define	PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_OUT_BUF2_ADDR_SHIFT (0U)

#define	PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)

OUT_PITCH - Output Buffer Pitch
#define	PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)

#define	PXP_OUT_PITCH_PITCH_SHIFT (0U)

#define	PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)

OUT_LRC - Output Surface Lower Right Coordinate
#define	PXP_OUT_LRC_Y_MASK (0x3FFFU)

#define	PXP_OUT_LRC_Y_SHIFT (0U)

#define	PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)

#define	PXP_OUT_LRC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_LRC_X_SHIFT (16U)

#define	PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)

OUT_PS_ULC - Processed Surface Upper Left Coordinate
#define	PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)

#define	PXP_OUT_PS_ULC_Y_SHIFT (0U)

#define	PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)

#define	PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_PS_ULC_X_SHIFT (16U)

#define	PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)

OUT_PS_LRC - Processed Surface Lower Right Coordinate
#define	PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)

#define	PXP_OUT_PS_LRC_Y_SHIFT (0U)

#define	PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)

#define	PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_PS_LRC_X_SHIFT (16U)

#define	PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)

OUT_AS_ULC - Alpha Surface Upper Left Coordinate
#define	PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)

#define	PXP_OUT_AS_ULC_Y_SHIFT (0U)

#define	PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)

#define	PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_AS_ULC_X_SHIFT (16U)

#define	PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)

OUT_AS_LRC - Alpha Surface Lower Right Coordinate
#define	PXP_OUT_AS_LRC_Y_MASK (0x3FFFU)

#define	PXP_OUT_AS_LRC_Y_SHIFT (0U)

#define	PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)

#define	PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)

#define	PXP_OUT_AS_LRC_X_SHIFT (16U)

#define	PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)

PS_CTRL - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)

#define	PXP_PS_CTRL_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)

#define	PXP_PS_CTRL_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)

#define	PXP_PS_CTRL_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)

PS_CTRL_SET - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)

#define	PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)

#define	PXP_PS_CTRL_SET_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_SET_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)

#define	PXP_PS_CTRL_SET_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_SET_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)

PS_CTRL_CLR - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)

#define	PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)

#define	PXP_PS_CTRL_CLR_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_CLR_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)

#define	PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_CLR_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)

PS_CTRL_TOG - Processed Surface (PS) Control Register
#define	PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU)

#define	PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)

#define	PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)

#define	PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U)

#define	PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U)

#define	PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)

#define	PXP_PS_CTRL_TOG_DECY_MASK (0x300U)

#define	PXP_PS_CTRL_TOG_DECY_SHIFT (8U)

#define	PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)

#define	PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)

#define	PXP_PS_CTRL_TOG_DECX_SHIFT (10U)

#define	PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)

PS_BUF - PS Input Buffer Address
#define	PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_PS_BUF_ADDR_SHIFT (0U)

#define	PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)

PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address
#define	PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_PS_UBUF_ADDR_SHIFT (0U)

#define	PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)

PS_VBUF - PS V/Cr Input Buffer Address
#define	PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_PS_VBUF_ADDR_SHIFT (0U)

#define	PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)

PS_PITCH - Processed Surface Pitch
#define	PXP_PS_PITCH_PITCH_MASK (0xFFFFU)

#define	PXP_PS_PITCH_PITCH_SHIFT (0U)

#define	PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)

PS_BACKGROUND - PS Background Color
#define	PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)

#define	PXP_PS_BACKGROUND_COLOR_SHIFT (0U)

#define	PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)

PS_SCALE - PS Scale Factor Register
#define	PXP_PS_SCALE_XSCALE_MASK (0x7FFFU)

#define	PXP_PS_SCALE_XSCALE_SHIFT (0U)

#define	PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)

#define	PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)

#define	PXP_PS_SCALE_YSCALE_SHIFT (16U)

#define	PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)

PS_OFFSET - PS Scale Offset Register
#define	PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)

#define	PXP_PS_OFFSET_XOFFSET_SHIFT (0U)

#define	PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)

#define	PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)

#define	PXP_PS_OFFSET_YOFFSET_SHIFT (16U)

#define	PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)

PS_CLRKEYLOW - PS Color Key Low
#define	PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)

#define	PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)

#define	PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)

PS_CLRKEYHIGH - PS Color Key High
#define	PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)

#define	PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)

#define	PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)

AS_CTRL - Alpha Surface Control
#define	PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)

#define	PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)

#define	PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)

#define	PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)

#define	PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)

#define	PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)

#define	PXP_AS_CTRL_FORMAT_MASK (0xF0U)

#define	PXP_AS_CTRL_FORMAT_SHIFT (4U)

#define	PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)

#define	PXP_AS_CTRL_ALPHA_MASK (0xFF00U)

#define	PXP_AS_CTRL_ALPHA_SHIFT (8U)

#define	PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)

#define	PXP_AS_CTRL_ROP_MASK (0xF0000U)

#define	PXP_AS_CTRL_ROP_SHIFT (16U)

#define	PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)

#define	PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)

#define	PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)

#define	PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)

AS_BUF - Alpha Surface Buffer Pointer
#define	PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)

#define	PXP_AS_BUF_ADDR_SHIFT (0U)

#define	PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)

AS_PITCH - Alpha Surface Pitch
#define	PXP_AS_PITCH_PITCH_MASK (0xFFFFU)

#define	PXP_AS_PITCH_PITCH_SHIFT (0U)

#define	PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)

AS_CLRKEYLOW - Overlay Color Key Low
#define	PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)

#define	PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)

#define	PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)

AS_CLRKEYHIGH - Overlay Color Key High
#define	PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)

#define	PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)

#define	PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)

CSC1_COEF0 - Color Space Conversion Coefficient Register 0
#define	PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)

#define	PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)

#define	PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)

#define	PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)

#define	PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)

#define	PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)

#define	PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)

#define	PXP_CSC1_COEF0_C0_SHIFT (18U)

#define	PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)

#define	PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)

#define	PXP_CSC1_COEF0_BYPASS_SHIFT (30U)

#define	PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)

#define	PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)

#define	PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)

#define	PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)

CSC1_COEF1 - Color Space Conversion Coefficient Register 1
#define	PXP_CSC1_COEF1_C4_MASK (0x7FFU)

#define	PXP_CSC1_COEF1_C4_SHIFT (0U)

#define	PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)

#define	PXP_CSC1_COEF1_C1_MASK (0x7FF0000U)

#define	PXP_CSC1_COEF1_C1_SHIFT (16U)

#define	PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)

CSC1_COEF2 - Color Space Conversion Coefficient Register 2
#define	PXP_CSC1_COEF2_C3_MASK (0x7FFU)

#define	PXP_CSC1_COEF2_C3_SHIFT (0U)

#define	PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)

#define	PXP_CSC1_COEF2_C2_MASK (0x7FF0000U)

#define	PXP_CSC1_COEF2_C2_SHIFT (16U)

#define	PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)

POWER - PXP Power Control Register
#define	PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)

#define	PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)

#define	PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)

NEXT - Next Frame Pointer
#define	PXP_NEXT_ENABLED_MASK (0x1U)

#define	PXP_NEXT_ENABLED_SHIFT (0U)

#define	PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)

#define	PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)

#define	PXP_NEXT_POINTER_SHIFT (2U)

#define	PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)

PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register.
#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)

#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)

#define	PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)

#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)

#define	PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)

#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)

#define	PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)

#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)

#define	PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)

#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)

#define	PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)

#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)

#define	PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)

#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)

#define	PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)

#define	PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)

#define	PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)

Detailed Description

Macro Definition Documentation

◆ PXP_AS_CTRL_ALPHA_CTRL [1/3]

#define PXP_AS_CTRL_ALPHA_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)

ALPHA_CTRL 0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored. 0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. 0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. 0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.

◆ PXP_AS_CTRL_ALPHA_CTRL [2/3]

#define PXP_AS_CTRL_ALPHA_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)

ALPHA_CTRL 0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored. 0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. 0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. 0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.

◆ PXP_AS_CTRL_ALPHA_CTRL [3/3]

#define PXP_AS_CTRL_ALPHA_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)

ALPHA_CTRL 0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored. 0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. 0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. 0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.

◆ PXP_AS_CTRL_ALPHA_INVERT [1/3]

#define PXP_AS_CTRL_ALPHA_INVERT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)

ALPHA_INVERT 0b0..Not inverted 0b1..Inverted

◆ PXP_AS_CTRL_ALPHA_INVERT [2/3]

#define PXP_AS_CTRL_ALPHA_INVERT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)

ALPHA_INVERT 0b0..Not inverted 0b1..Inverted

◆ PXP_AS_CTRL_ALPHA_INVERT [3/3]

#define PXP_AS_CTRL_ALPHA_INVERT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)

ALPHA_INVERT 0b0..Not inverted 0b1..Inverted

◆ PXP_AS_CTRL_ENABLE_COLORKEY [1/3]

#define PXP_AS_CTRL_ENABLE_COLORKEY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)

ENABLE_COLORKEY 0b0..Disabled 0b1..Enabled

◆ PXP_AS_CTRL_ENABLE_COLORKEY [2/3]

#define PXP_AS_CTRL_ENABLE_COLORKEY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)

ENABLE_COLORKEY 0b0..Disabled 0b1..Enabled

◆ PXP_AS_CTRL_ENABLE_COLORKEY [3/3]

#define PXP_AS_CTRL_ENABLE_COLORKEY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)

ENABLE_COLORKEY 0b0..Disabled 0b1..Enabled

◆ PXP_AS_CTRL_FORMAT [1/3]

#define PXP_AS_CTRL_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)

FORMAT 0b0000..32-bit pixels with alpha 0b0001..2-bit pixel with alpha at low 8 bits 0b0100..32-bit pixels without alpha (unpacked 24-bit format) 0b1000..16-bit pixels with alpha 0b1001..16-bit pixels with alpha 0b1010..16-bit pixel with alpha at low 1 bit 0b1011..16-bit pixel with alpha at low 4 bits 0b1100..16-bit pixels without alpha 0b1101..16-bit pixels without alpha 0b1110..16-bit pixels without alpha

◆ PXP_AS_CTRL_FORMAT [2/3]

#define PXP_AS_CTRL_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)

FORMAT 0b0000..32-bit pixels with alpha 0b0001..2-bit pixel with alpha at low 8 bits 0b0100..32-bit pixels without alpha (unpacked 24-bit format) 0b1000..16-bit pixels with alpha 0b1001..16-bit pixels with alpha 0b1010..16-bit pixel with alpha at low 1 bit 0b1011..16-bit pixel with alpha at low 4 bits 0b1100..16-bit pixels without alpha 0b1101..16-bit pixels without alpha 0b1110..16-bit pixels without alpha

◆ PXP_AS_CTRL_FORMAT [3/3]

#define PXP_AS_CTRL_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)

FORMAT 0b0000..32-bit pixels with alpha 0b0001..2-bit pixel with alpha at low 8 bits 0b0100..32-bit pixels without alpha (unpacked 24-bit format) 0b1000..16-bit pixels with alpha 0b1001..16-bit pixels with alpha 0b1010..16-bit pixel with alpha at low 1 bit 0b1011..16-bit pixel with alpha at low 4 bits 0b1100..16-bit pixels without alpha 0b1101..16-bit pixels without alpha 0b1110..16-bit pixels without alpha

◆ PXP_AS_CTRL_ROP [1/3]

#define PXP_AS_CTRL_ROP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)

ROP 0b0000..AS AND PS 0b0001..nAS AND PS 0b0010..AS AND nPS 0b0011..AS OR PS 0b0100..nAS OR PS 0b0101..AS OR nPS 0b0110..nAS 0b0111..nPS 0b1000..AS NAND PS 0b1001..AS NOR PS 0b1010..AS XOR PS 0b1011..AS XNOR PS

◆ PXP_AS_CTRL_ROP [2/3]

#define PXP_AS_CTRL_ROP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)

ROP 0b0000..AS AND PS 0b0001..nAS AND PS 0b0010..AS AND nPS 0b0011..AS OR PS 0b0100..nAS OR PS 0b0101..AS OR nPS 0b0110..nAS 0b0111..nPS 0b1000..AS NAND PS 0b1001..AS NOR PS 0b1010..AS XOR PS 0b1011..AS XNOR PS

◆ PXP_AS_CTRL_ROP [3/3]

#define PXP_AS_CTRL_ROP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)

ROP 0b0000..AS AND PS 0b0001..nAS AND PS 0b0010..AS AND nPS 0b0011..AS OR PS 0b0100..nAS OR PS 0b0101..AS OR nPS 0b0110..nAS 0b0111..nPS 0b1000..AS NAND PS 0b1001..AS NOR PS 0b1010..AS XOR PS 0b1011..AS XNOR PS

◆ PXP_CSC1_COEF0_YCBCR_MODE [1/3]

#define PXP_CSC1_COEF0_YCBCR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)

YCBCR_MODE 0b0..YUV to RGB 0b1..YCbCr to RGB

◆ PXP_CSC1_COEF0_YCBCR_MODE [2/3]

#define PXP_CSC1_COEF0_YCBCR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)

YCBCR_MODE 0b0..YUV to RGB 0b1..YCbCr to RGB

◆ PXP_CSC1_COEF0_YCBCR_MODE [3/3]

#define PXP_CSC1_COEF0_YCBCR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)

YCBCR_MODE 0b0..YUV to RGB 0b1..YCbCr to RGB

◆ PXP_CTRL_BLOCK_SIZE [1/3]

#define PXP_CTRL_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_BLOCK_SIZE [2/3]

#define PXP_CTRL_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_BLOCK_SIZE [3/3]

#define PXP_CTRL_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_CLKGATE [1/3]

#define PXP_CTRL_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_CLKGATE [2/3]

#define PXP_CTRL_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_CLKGATE [3/3]

#define PXP_CTRL_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_CLR_BLOCK_SIZE [1/3]

#define PXP_CTRL_CLR_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_CLR_BLOCK_SIZE [2/3]

#define PXP_CTRL_CLR_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_CLR_BLOCK_SIZE [3/3]

#define PXP_CTRL_CLR_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_CLR_CLKGATE [1/3]

#define PXP_CTRL_CLR_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_CLR_CLKGATE [2/3]

#define PXP_CTRL_CLR_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_CLR_CLKGATE [3/3]

#define PXP_CTRL_CLR_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_CLR_EN_REPEAT [1/3]

#define PXP_CTRL_CLR_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_CLR_EN_REPEAT [2/3]

#define PXP_CTRL_CLR_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_CLR_EN_REPEAT [3/3]

#define PXP_CTRL_CLR_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_CLR_ENABLE [1/3]

#define PXP_CTRL_CLR_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_CLR_ENABLE [2/3]

#define PXP_CTRL_CLR_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_CLR_ENABLE [3/3]

#define PXP_CTRL_CLR_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_CLR_HFLIP [1/3]

#define PXP_CTRL_CLR_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_CLR_HFLIP [2/3]

#define PXP_CTRL_CLR_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_CLR_HFLIP [3/3]

#define PXP_CTRL_CLR_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_CLR_IRQ_ENABLE [1/3]

#define PXP_CTRL_CLR_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_CLR_IRQ_ENABLE [2/3]

#define PXP_CTRL_CLR_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_CLR_IRQ_ENABLE [3/3]

#define PXP_CTRL_CLR_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_CLR_NEXT_IRQ_ENABLE [1/3]

#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_CLR_NEXT_IRQ_ENABLE [2/3]

#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_CLR_NEXT_IRQ_ENABLE [3/3]

#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_CLR_ROTATE [1/3]

#define PXP_CTRL_CLR_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_CLR_ROTATE [2/3]

#define PXP_CTRL_CLR_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_CLR_ROTATE [3/3]

#define PXP_CTRL_CLR_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_CLR_SFTRST [1/3]

#define PXP_CTRL_CLR_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_CLR_SFTRST [2/3]

#define PXP_CTRL_CLR_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_CLR_SFTRST [3/3]

#define PXP_CTRL_CLR_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_CLR_VFLIP [1/3]

#define PXP_CTRL_CLR_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_CTRL_CLR_VFLIP [2/3]

#define PXP_CTRL_CLR_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_CTRL_CLR_VFLIP [3/3]

#define PXP_CTRL_CLR_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_CTRL_EN_REPEAT [1/3]

#define PXP_CTRL_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_EN_REPEAT [2/3]

#define PXP_CTRL_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_EN_REPEAT [3/3]

#define PXP_CTRL_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_ENABLE [1/3]

#define PXP_CTRL_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_ENABLE [2/3]

#define PXP_CTRL_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_ENABLE [3/3]

#define PXP_CTRL_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_HFLIP [1/3]

#define PXP_CTRL_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_HFLIP [2/3]

#define PXP_CTRL_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_HFLIP [3/3]

#define PXP_CTRL_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_IRQ_ENABLE [1/3]

#define PXP_CTRL_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_IRQ_ENABLE [2/3]

#define PXP_CTRL_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_IRQ_ENABLE [3/3]

#define PXP_CTRL_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_NEXT_IRQ_ENABLE [1/3]

#define PXP_CTRL_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_NEXT_IRQ_ENABLE [2/3]

#define PXP_CTRL_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_NEXT_IRQ_ENABLE [3/3]

#define PXP_CTRL_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_ROTATE [1/3]

#define PXP_CTRL_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_ROTATE [2/3]

#define PXP_CTRL_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_ROTATE [3/3]

#define PXP_CTRL_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_SET_BLOCK_SIZE [1/3]

#define PXP_CTRL_SET_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_SET_BLOCK_SIZE [2/3]

#define PXP_CTRL_SET_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_SET_BLOCK_SIZE [3/3]

#define PXP_CTRL_SET_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_SET_CLKGATE [1/3]

#define PXP_CTRL_SET_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_SET_CLKGATE [2/3]

#define PXP_CTRL_SET_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_SET_CLKGATE [3/3]

#define PXP_CTRL_SET_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_SET_EN_REPEAT [1/3]

#define PXP_CTRL_SET_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_SET_EN_REPEAT [2/3]

#define PXP_CTRL_SET_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_SET_EN_REPEAT [3/3]

#define PXP_CTRL_SET_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_SET_ENABLE [1/3]

#define PXP_CTRL_SET_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_SET_ENABLE [2/3]

#define PXP_CTRL_SET_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_SET_ENABLE [3/3]

#define PXP_CTRL_SET_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_SET_HFLIP [1/3]

#define PXP_CTRL_SET_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_SET_HFLIP [2/3]

#define PXP_CTRL_SET_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_SET_HFLIP [3/3]

#define PXP_CTRL_SET_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_SET_IRQ_ENABLE [1/3]

#define PXP_CTRL_SET_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_SET_IRQ_ENABLE [2/3]

#define PXP_CTRL_SET_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_SET_IRQ_ENABLE [3/3]

#define PXP_CTRL_SET_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_SET_NEXT_IRQ_ENABLE [1/3]

#define PXP_CTRL_SET_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_SET_NEXT_IRQ_ENABLE [2/3]

#define PXP_CTRL_SET_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_SET_NEXT_IRQ_ENABLE [3/3]

#define PXP_CTRL_SET_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_SET_ROTATE [1/3]

#define PXP_CTRL_SET_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_SET_ROTATE [2/3]

#define PXP_CTRL_SET_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_SET_ROTATE [3/3]

#define PXP_CTRL_SET_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_SET_SFTRST [1/3]

#define PXP_CTRL_SET_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_SET_SFTRST [2/3]

#define PXP_CTRL_SET_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_SET_SFTRST [3/3]

#define PXP_CTRL_SET_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_SET_VFLIP [1/3]

#define PXP_CTRL_SET_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_CTRL_SET_VFLIP [2/3]

#define PXP_CTRL_SET_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_CTRL_SET_VFLIP [3/3]

#define PXP_CTRL_SET_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_CTRL_SFTRST [1/3]

#define PXP_CTRL_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_SFTRST [2/3]

#define PXP_CTRL_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_SFTRST [3/3]

#define PXP_CTRL_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_TOG_BLOCK_SIZE [1/3]

#define PXP_CTRL_TOG_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_TOG_BLOCK_SIZE [2/3]

#define PXP_CTRL_TOG_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_TOG_BLOCK_SIZE [3/3]

#define PXP_CTRL_TOG_BLOCK_SIZE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)

BLOCK_SIZE 0b0..Process 8x8 pixel blocks. 0b1..Process 16x16 pixel blocks.

◆ PXP_CTRL_TOG_CLKGATE [1/3]

#define PXP_CTRL_TOG_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_TOG_CLKGATE [2/3]

#define PXP_CTRL_TOG_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_TOG_CLKGATE [3/3]

#define PXP_CTRL_TOG_CLKGATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)

CLKGATE 0b0..Normal operation 0b1..All clocks to PXP is gated-off

◆ PXP_CTRL_TOG_EN_REPEAT [1/3]

#define PXP_CTRL_TOG_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_TOG_EN_REPEAT [2/3]

#define PXP_CTRL_TOG_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_TOG_EN_REPEAT [3/3]

#define PXP_CTRL_TOG_EN_REPEAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)

EN_REPEAT 0b1..PXP will repeat based on the current configuration register settings 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed

◆ PXP_CTRL_TOG_ENABLE [1/3]

#define PXP_CTRL_TOG_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_TOG_ENABLE [2/3]

#define PXP_CTRL_TOG_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_TOG_ENABLE [3/3]

#define PXP_CTRL_TOG_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)

ENABLE 0b1..PXP is enabled 0b0..PXP is disabled

◆ PXP_CTRL_TOG_HFLIP [1/3]

#define PXP_CTRL_TOG_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_TOG_HFLIP [2/3]

#define PXP_CTRL_TOG_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_TOG_HFLIP [3/3]

#define PXP_CTRL_TOG_HFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)

HFLIP 0b0..Horizontal Flip is disabled 0b1..Horizontal Flip is enabled

◆ PXP_CTRL_TOG_IRQ_ENABLE [1/3]

#define PXP_CTRL_TOG_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_TOG_IRQ_ENABLE [2/3]

#define PXP_CTRL_TOG_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_TOG_IRQ_ENABLE [3/3]

#define PXP_CTRL_TOG_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)

IRQ_ENABLE 0b1..PXP interrupt is enabled 0b0..PXP interrupt is disabled

◆ PXP_CTRL_TOG_NEXT_IRQ_ENABLE [1/3]

#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_TOG_NEXT_IRQ_ENABLE [2/3]

#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_TOG_NEXT_IRQ_ENABLE [3/3]

#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)

NEXT_IRQ_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_CTRL_TOG_ROTATE [1/3]

#define PXP_CTRL_TOG_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_TOG_ROTATE [2/3]

#define PXP_CTRL_TOG_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_TOG_ROTATE [3/3]

#define PXP_CTRL_TOG_ROTATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)

ROTATE 0b00..ROT_0 0b01..ROT_90 0b10..ROT_180 0b11..ROT_270

◆ PXP_CTRL_TOG_SFTRST [1/3]

#define PXP_CTRL_TOG_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_TOG_SFTRST [2/3]

#define PXP_CTRL_TOG_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_TOG_SFTRST [3/3]

#define PXP_CTRL_TOG_SFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)

SFTRST 0b0..Normal PXP operation is enabled 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.

◆ PXP_CTRL_TOG_VFLIP [1/3]

#define PXP_CTRL_TOG_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_CTRL_TOG_VFLIP [2/3]

#define PXP_CTRL_TOG_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_CTRL_TOG_VFLIP [3/3]

#define PXP_CTRL_TOG_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_CTRL_VFLIP [1/3]

#define PXP_CTRL_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_CTRL_VFLIP [2/3]

#define PXP_CTRL_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_CTRL_VFLIP [3/3]

#define PXP_CTRL_VFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)

VFLIP 0b0..Vertical Flip is disabled 0b1..Vertical Flip is enabled

◆ PXP_OUT_CTRL_ALPHA_OUTPUT [1/3]

#define PXP_OUT_CTRL_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_ALPHA_OUTPUT [2/3]

#define PXP_OUT_CTRL_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_ALPHA_OUTPUT [3/3]

#define PXP_OUT_CTRL_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_CLR_ALPHA_OUTPUT [1/3]

#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_CLR_ALPHA_OUTPUT [2/3]

#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_CLR_ALPHA_OUTPUT [3/3]

#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_CLR_FORMAT [1/3]

#define PXP_OUT_CTRL_CLR_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_CLR_FORMAT [2/3]

#define PXP_OUT_CTRL_CLR_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_CLR_FORMAT [3/3]

#define PXP_OUT_CTRL_CLR_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT [1/3]

#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT [2/3]

#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT [3/3]

#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_OUT_CTRL_FORMAT [1/3]

#define PXP_OUT_CTRL_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_FORMAT [2/3]

#define PXP_OUT_CTRL_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_FORMAT [3/3]

#define PXP_OUT_CTRL_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_INTERLACED_OUTPUT [1/3]

#define PXP_OUT_CTRL_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_OUT_CTRL_INTERLACED_OUTPUT [2/3]

#define PXP_OUT_CTRL_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_OUT_CTRL_INTERLACED_OUTPUT [3/3]

#define PXP_OUT_CTRL_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_OUT_CTRL_SET_ALPHA_OUTPUT [1/3]

#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_SET_ALPHA_OUTPUT [2/3]

#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_SET_ALPHA_OUTPUT [3/3]

#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_SET_FORMAT [1/3]

#define PXP_OUT_CTRL_SET_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_SET_FORMAT [2/3]

#define PXP_OUT_CTRL_SET_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_SET_FORMAT [3/3]

#define PXP_OUT_CTRL_SET_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_SET_INTERLACED_OUTPUT [1/3]

#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_OUT_CTRL_SET_INTERLACED_OUTPUT [2/3]

#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_OUT_CTRL_SET_INTERLACED_OUTPUT [3/3]

#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_OUT_CTRL_TOG_ALPHA_OUTPUT [1/3]

#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_TOG_ALPHA_OUTPUT [2/3]

#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_TOG_ALPHA_OUTPUT [3/3]

#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)

ALPHA_OUTPUT 0b0..Retain 0b1..Overwritten

◆ PXP_OUT_CTRL_TOG_FORMAT [1/3]

#define PXP_OUT_CTRL_TOG_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_TOG_FORMAT [2/3]

#define PXP_OUT_CTRL_TOG_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_TOG_FORMAT [3/3]

#define PXP_OUT_CTRL_TOG_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)

FORMAT 0b00000..32-bit pixels 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.) 0b00101..24-bit pixels (packed 24-bit format) 0b01000..16-bit pixels 0b01001..16-bit pixels 0b01100..16-bit pixels 0b01101..16-bit pixels 0b01110..16-bit pixels 0b10000..32-bit pixels (1-plane XYUV unpacked) 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b10100..8-bit monochrome pixels (1-plane Y luma output) 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b11000..16-bit pixels (2-plane UV interleaved bytes) 0b11001..16-bit pixels (2-plane UV) 0b11010..16-bit pixels (2-plane VU interleaved bytes) 0b11011..16-bit pixels (2-plane VU)

◆ PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT [1/3]

#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT [2/3]

#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT [3/3]

#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)

INTERLACED_OUTPUT 0b00..All data written in progressive format to the OUTBUF Pointer. 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer. 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer. 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.

◆ PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE [1/3]

#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)

PORTER_DUFF_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE [2/3]

#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)

PORTER_DUFF_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE [3/3]

#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)

PORTER_DUFF_ENABLE 0b0..Disabled 0b1..Enabled

◆ PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE [1/3]

#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)

S0_ALPHA_MODE 0b0..Straight mode 0b1..Inverted mode

◆ PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE [2/3]

#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)

S0_ALPHA_MODE 0b0..Straight mode 0b1..Inverted mode

◆ PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE [3/3]

#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)

S0_ALPHA_MODE 0b0..Straight mode 0b1..Inverted mode

◆ PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE [1/3]

#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)

S0_COLOR_MODE 0b0..Original pixel 0b1..Scaled pixel

◆ PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE [2/3]

#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)

S0_COLOR_MODE 0b0..Original pixel 0b1..Scaled pixel

◆ PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE [3/3]

#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)

S0_COLOR_MODE 0b0..Original pixel 0b1..Scaled pixel

◆ PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE [1/3]

#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)

S0_GLOBAL_ALPHA_MODE 0b00..Global alpha 0b01..Local alpha 0b10..Scaled alpha 0b11..Scaled alpha

◆ PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE [2/3]

#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)

S0_GLOBAL_ALPHA_MODE 0b00..Global alpha 0b01..Local alpha 0b10..Scaled alpha 0b11..Scaled alpha

◆ PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE [3/3]

#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)

S0_GLOBAL_ALPHA_MODE 0b00..Global alpha 0b01..Local alpha 0b10..Scaled alpha 0b11..Scaled alpha

◆ PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE [1/3]

#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)

S0_S1_FACTOR_MODE 0b00..1 0b01..0 0b10..Straight alpha 0b11..Inverse alpha

◆ PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE [2/3]

#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)

S0_S1_FACTOR_MODE 0b00..1 0b01..0 0b10..Straight alpha 0b11..Inverse alpha

◆ PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE [3/3]

#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)

S0_S1_FACTOR_MODE 0b00..1 0b01..0 0b10..Straight alpha 0b11..Inverse alpha

◆ PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE [1/3]

#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)

S1_ALPHA_MODE 0b0..Straight mode 0b1..Inverted mode

◆ PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE [2/3]

#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)

S1_ALPHA_MODE 0b0..Straight mode 0b1..Inverted mode

◆ PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE [3/3]

#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)

S1_ALPHA_MODE 0b0..Straight mode 0b1..Inverted mode

◆ PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE [1/3]

#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)

S1_COLOR_MODE 0b0..Original pixel 0b1..Scaled pixel

◆ PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE [2/3]

#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)

S1_COLOR_MODE 0b0..Original pixel 0b1..Scaled pixel

◆ PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE [3/3]

#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)

S1_COLOR_MODE 0b0..Original pixel 0b1..Scaled pixel

◆ PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE [1/3]

#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)

S1_GLOBAL_ALPHA_MODE 0b00..Global alpha 0b01..Local alpha 0b10..Scaled alpha 0b11..Scaled alpha

◆ PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE [2/3]

#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)

S1_GLOBAL_ALPHA_MODE 0b00..Global alpha 0b01..Local alpha 0b10..Scaled alpha 0b11..Scaled alpha

◆ PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE [3/3]

#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)

S1_GLOBAL_ALPHA_MODE 0b00..Global alpha 0b01..Local alpha 0b10..Scaled alpha 0b11..Scaled alpha

◆ PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE [1/3]

#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)

S1_S0_FACTOR_MODE 0b00..1 0b01..0 0b10..Straight alpha 0b11..Inverse alpha

◆ PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE [2/3]

#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)

S1_S0_FACTOR_MODE 0b00..1 0b01..0 0b10..Straight alpha 0b11..Inverse alpha

◆ PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE [3/3]

#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)

S1_S0_FACTOR_MODE 0b00..1 0b01..0 0b10..Straight alpha 0b11..Inverse alpha

◆ PXP_POWER_ROT_MEM_LP_STATE [1/3]

#define PXP_POWER_ROT_MEM_LP_STATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)

ROT_MEM_LP_STATE 0b000..Memory is not in low power state. 0b001..Light Sleep Mode. Low leakage mode, maintain memory contents. 0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents. 0b100..Shut Down Mode. Shut Down periphery and core, no memory retention.

◆ PXP_POWER_ROT_MEM_LP_STATE [2/3]

#define PXP_POWER_ROT_MEM_LP_STATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)

ROT_MEM_LP_STATE 0b000..Memory is not in low power state. 0b001..Light Sleep Mode. Low leakage mode, maintain memory contents. 0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents. 0b100..Shut Down Mode. Shut Down periphery and core, no memory retention.

◆ PXP_POWER_ROT_MEM_LP_STATE [3/3]

#define PXP_POWER_ROT_MEM_LP_STATE ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)

ROT_MEM_LP_STATE 0b000..Memory is not in low power state. 0b001..Light Sleep Mode. Low leakage mode, maintain memory contents. 0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents. 0b100..Shut Down Mode. Shut Down periphery and core, no memory retention.

◆ PXP_PS_CTRL_CLR_DECX [1/3]

#define PXP_PS_CTRL_CLR_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_CLR_DECX [2/3]

#define PXP_PS_CTRL_CLR_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_CLR_DECX [3/3]

#define PXP_PS_CTRL_CLR_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_CLR_DECY [1/3]

#define PXP_PS_CTRL_CLR_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_CLR_DECY [2/3]

#define PXP_PS_CTRL_CLR_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_CLR_DECY [3/3]

#define PXP_PS_CTRL_CLR_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_CLR_FORMAT [1/3]

#define PXP_PS_CTRL_CLR_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_CLR_FORMAT [2/3]

#define PXP_PS_CTRL_CLR_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_CLR_FORMAT [3/3]

#define PXP_PS_CTRL_CLR_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_CLR_WB_SWAP [1/3]

#define PXP_PS_CTRL_CLR_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_PS_CTRL_CLR_WB_SWAP [2/3]

#define PXP_PS_CTRL_CLR_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_PS_CTRL_CLR_WB_SWAP [3/3]

#define PXP_PS_CTRL_CLR_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_PS_CTRL_DECX [1/3]

#define PXP_PS_CTRL_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_DECX [2/3]

#define PXP_PS_CTRL_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_DECX [3/3]

#define PXP_PS_CTRL_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_DECY [1/3]

#define PXP_PS_CTRL_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_DECY [2/3]

#define PXP_PS_CTRL_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_DECY [3/3]

#define PXP_PS_CTRL_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_FORMAT [1/3]

#define PXP_PS_CTRL_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_FORMAT [2/3]

#define PXP_PS_CTRL_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_FORMAT [3/3]

#define PXP_PS_CTRL_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_SET_DECX [1/3]

#define PXP_PS_CTRL_SET_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_SET_DECX [2/3]

#define PXP_PS_CTRL_SET_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_SET_DECX [3/3]

#define PXP_PS_CTRL_SET_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_SET_DECY [1/3]

#define PXP_PS_CTRL_SET_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_SET_DECY [2/3]

#define PXP_PS_CTRL_SET_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_SET_DECY [3/3]

#define PXP_PS_CTRL_SET_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_SET_FORMAT [1/3]

#define PXP_PS_CTRL_SET_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_SET_FORMAT [2/3]

#define PXP_PS_CTRL_SET_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_SET_FORMAT [3/3]

#define PXP_PS_CTRL_SET_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_SET_WB_SWAP [1/3]

#define PXP_PS_CTRL_SET_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_PS_CTRL_SET_WB_SWAP [2/3]

#define PXP_PS_CTRL_SET_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_PS_CTRL_SET_WB_SWAP [3/3]

#define PXP_PS_CTRL_SET_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_PS_CTRL_TOG_DECX [1/3]

#define PXP_PS_CTRL_TOG_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_TOG_DECX [2/3]

#define PXP_PS_CTRL_TOG_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_TOG_DECX [3/3]

#define PXP_PS_CTRL_TOG_DECX ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)

DECX 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_TOG_DECY [1/3]

#define PXP_PS_CTRL_TOG_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_TOG_DECY [2/3]

#define PXP_PS_CTRL_TOG_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_TOG_DECY [3/3]

#define PXP_PS_CTRL_TOG_DECY ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)

DECY 0b00..Disable pre-decimation filter. 0b01..Decimate PS by 2. 0b10..Decimate PS by 4. 0b11..Decimate PS by 8.

◆ PXP_PS_CTRL_TOG_FORMAT [1/3]

#define PXP_PS_CTRL_TOG_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_TOG_FORMAT [2/3]

#define PXP_PS_CTRL_TOG_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_TOG_FORMAT [3/3]

#define PXP_PS_CTRL_TOG_FORMAT ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)

FORMAT 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits) 0b001100..16-bit pixels with/without alpha at high 1bit 0b001101..16-bit pixels with/without alpha at high 4 bits 0b001110..16-bit pixels 0b010000..32-bit pixels (1-plane XYUV unpacked) 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) 0b010100..8-bit monochrome pixels (1-plane Y luma output) 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) 0b011000..16-bit pixels (2-plane UV interleaved bytes) 0b011001..16-bit pixels (2-plane UV) 0b011010..16-bit pixels (2-plane VU interleaved bytes) 0b011011..16-bit pixels (2-plane VU) 0b011110..16-bit pixels (3-plane format) 0b011111..16-bit pixels (3-plane format) 0b100100..2-bit pixels with alpha at the low 8 bits 0b101100..16-bit pixels with alpha at the low 1bits 0b101101..16-bit pixels with alpha at the low 4 bits

◆ PXP_PS_CTRL_TOG_WB_SWAP [1/3]

#define PXP_PS_CTRL_TOG_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_PS_CTRL_TOG_WB_SWAP [2/3]

#define PXP_PS_CTRL_TOG_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_PS_CTRL_TOG_WB_SWAP [3/3]

#define PXP_PS_CTRL_TOG_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_PS_CTRL_WB_SWAP [1/3]

#define PXP_PS_CTRL_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_PS_CTRL_WB_SWAP [2/3]

#define PXP_PS_CTRL_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_PS_CTRL_WB_SWAP [3/3]

#define PXP_PS_CTRL_WB_SWAP ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)

WB_SWAP 0b0..Byte swap is disabled 0b1..Byte swap is enabled

◆ PXP_STAT_AXI_READ_ERROR [1/3]

#define PXP_STAT_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_AXI_READ_ERROR [2/3]

#define PXP_STAT_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_AXI_READ_ERROR [3/3]

#define PXP_STAT_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_AXI_WRITE_ERROR [1/3]

#define PXP_STAT_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_AXI_WRITE_ERROR [2/3]

#define PXP_STAT_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_AXI_WRITE_ERROR [3/3]

#define PXP_STAT_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_CLR_AXI_READ_ERROR [1/3]

#define PXP_STAT_CLR_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_CLR_AXI_READ_ERROR [2/3]

#define PXP_STAT_CLR_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_CLR_AXI_READ_ERROR [3/3]

#define PXP_STAT_CLR_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_CLR_AXI_WRITE_ERROR [1/3]

#define PXP_STAT_CLR_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_CLR_AXI_WRITE_ERROR [2/3]

#define PXP_STAT_CLR_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_CLR_AXI_WRITE_ERROR [3/3]

#define PXP_STAT_CLR_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_CLR_IRQ [1/3]

#define PXP_STAT_CLR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_CLR_IRQ [2/3]

#define PXP_STAT_CLR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_CLR_IRQ [3/3]

#define PXP_STAT_CLR_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ [1/3]

#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

◆ PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ [2/3]

#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

◆ PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ [3/3]

#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

◆ PXP_STAT_IRQ [1/3]

#define PXP_STAT_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_IRQ [2/3]

#define PXP_STAT_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_IRQ [3/3]

#define PXP_STAT_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_LUT_DMA_LOAD_DONE_IRQ [1/3]

#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

◆ PXP_STAT_LUT_DMA_LOAD_DONE_IRQ [2/3]

#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

◆ PXP_STAT_LUT_DMA_LOAD_DONE_IRQ [3/3]

#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

◆ PXP_STAT_SET_AXI_READ_ERROR [1/3]

#define PXP_STAT_SET_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_SET_AXI_READ_ERROR [2/3]

#define PXP_STAT_SET_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_SET_AXI_READ_ERROR [3/3]

#define PXP_STAT_SET_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_SET_AXI_WRITE_ERROR [1/3]

#define PXP_STAT_SET_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_SET_AXI_WRITE_ERROR [2/3]

#define PXP_STAT_SET_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_SET_AXI_WRITE_ERROR [3/3]

#define PXP_STAT_SET_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_SET_IRQ [1/3]

#define PXP_STAT_SET_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_SET_IRQ [2/3]

#define PXP_STAT_SET_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_SET_IRQ [3/3]

#define PXP_STAT_SET_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ [1/3]

#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

◆ PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ [2/3]

#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

◆ PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ [3/3]

#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

◆ PXP_STAT_TOG_AXI_READ_ERROR [1/3]

#define PXP_STAT_TOG_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_TOG_AXI_READ_ERROR [2/3]

#define PXP_STAT_TOG_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_TOG_AXI_READ_ERROR [3/3]

#define PXP_STAT_TOG_AXI_READ_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)

AXI_READ_ERROR 0b0..AXI read is normal 0b1..AXI read error has occurred

◆ PXP_STAT_TOG_AXI_WRITE_ERROR [1/3]

#define PXP_STAT_TOG_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_TOG_AXI_WRITE_ERROR [2/3]

#define PXP_STAT_TOG_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_TOG_AXI_WRITE_ERROR [3/3]

#define PXP_STAT_TOG_AXI_WRITE_ERROR ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)

AXI_WRITE_ERROR 0b0..AXI write is normal 0b1..AXI write error has occurred

◆ PXP_STAT_TOG_IRQ [1/3]

#define PXP_STAT_TOG_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_TOG_IRQ [2/3]

#define PXP_STAT_TOG_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_TOG_IRQ [3/3]

#define PXP_STAT_TOG_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)

IRQ 0b0..No interrupt 0b1..Interrupt generated

◆ PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ [1/3]

#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

◆ PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ [2/3]

#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

◆ PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ [3/3]

#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ ( x ) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)

LUT_DMA_LOAD_DONE_IRQ 0b0..LUT DMA LOAD transfer is active 0b1..LUT DMA LOAD transfer is complete

CTRL - Control Register 0

CTRL_SET - Control Register 0

CTRL_CLR - Control Register 0

CTRL_TOG - Control Register 0

STAT - Status Register

STAT_SET - Status Register

STAT_CLR - Status Register

STAT_TOG - Status Register

OUT_CTRL - Output Buffer Control Register

OUT_CTRL_SET - Output Buffer Control Register

OUT_CTRL_CLR - Output Buffer Control Register

OUT_CTRL_TOG - Output Buffer Control Register

OUT_BUF - Output Frame Buffer Pointer

OUT_BUF2 - Output Frame Buffer Pointer #2

OUT_PITCH - Output Buffer Pitch

OUT_LRC - Output Surface Lower Right Coordinate

OUT_PS_ULC - Processed Surface Upper Left Coordinate

OUT_PS_LRC - Processed Surface Lower Right Coordinate

OUT_AS_ULC - Alpha Surface Upper Left Coordinate

OUT_AS_LRC - Alpha Surface Lower Right Coordinate

PS_CTRL - Processed Surface (PS) Control Register

PS_CTRL_SET - Processed Surface (PS) Control Register

PS_CTRL_CLR - Processed Surface (PS) Control Register

PS_CTRL_TOG - Processed Surface (PS) Control Register

PS_BUF - PS Input Buffer Address

PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address

PS_VBUF - PS V/Cr Input Buffer Address

PS_PITCH - Processed Surface Pitch

PS_BACKGROUND - PS Background Color

PS_SCALE - PS Scale Factor Register

PS_OFFSET - PS Scale Offset Register

PS_CLRKEYLOW - PS Color Key Low

PS_CLRKEYHIGH - PS Color Key High

AS_CTRL - Alpha Surface Control

AS_BUF - Alpha Surface Buffer Pointer

AS_PITCH - Alpha Surface Pitch

AS_CLRKEYLOW - Overlay Color Key Low

AS_CLRKEYHIGH - Overlay Color Key High

CSC1_COEF0 - Color Space Conversion Coefficient Register 0

CSC1_COEF1 - Color Space Conversion Coefficient Register 1

CSC1_COEF2 - Color Space Conversion Coefficient Register 2

POWER - PXP Power Control Register

NEXT - Next Frame Pointer

PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register.

CTRL - Control Register 0

CTRL_SET - Control Register 0

CTRL_CLR - Control Register 0

CTRL_TOG - Control Register 0

STAT - Status Register

STAT_SET - Status Register

STAT_CLR - Status Register

STAT_TOG - Status Register

OUT_CTRL - Output Buffer Control Register

OUT_CTRL_SET - Output Buffer Control Register

OUT_CTRL_CLR - Output Buffer Control Register

OUT_CTRL_TOG - Output Buffer Control Register

OUT_BUF - Output Frame Buffer Pointer

OUT_BUF2 - Output Frame Buffer Pointer #2

OUT_PITCH - Output Buffer Pitch

OUT_LRC - Output Surface Lower Right Coordinate

OUT_PS_ULC - Processed Surface Upper Left Coordinate

OUT_PS_LRC - Processed Surface Lower Right Coordinate

OUT_AS_ULC - Alpha Surface Upper Left Coordinate

OUT_AS_LRC - Alpha Surface Lower Right Coordinate

PS_CTRL - Processed Surface (PS) Control Register

PS_CTRL_SET - Processed Surface (PS) Control Register

PS_CTRL_CLR - Processed Surface (PS) Control Register

PS_CTRL_TOG - Processed Surface (PS) Control Register

PS_BUF - PS Input Buffer Address

PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address

PS_VBUF - PS V/Cr Input Buffer Address

PS_PITCH - Processed Surface Pitch

PS_BACKGROUND - PS Background Color

PS_SCALE - PS Scale Factor Register

PS_OFFSET - PS Scale Offset Register

PS_CLRKEYLOW - PS Color Key Low

PS_CLRKEYHIGH - PS Color Key High

AS_CTRL - Alpha Surface Control

AS_BUF - Alpha Surface Buffer Pointer

AS_PITCH - Alpha Surface Pitch