USDHC Peripheral Access Layer

Modules
	USDHC Register Masks

Data Structures
struct	USDHC_Type

Macros
#define	USDHC1_BASE   (0x402C0000u)
#define	USDHC1   ((USDHC_Type *)USDHC1_BASE)
#define	USDHC2_BASE   (0x402C4000u)
#define	USDHC2   ((USDHC_Type *)USDHC2_BASE)
#define	USDHC_BASE_ADDRS   { 0u, USDHC1_BASE, USDHC2_BASE }
#define	USDHC_BASE_PTRS   { (USDHC_Type *)0u, USDHC1, USDHC2 }
#define	USDHC_IRQS   { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
#define	USDHC1_BASE   (0x40418000u)
#define	USDHC1   ((USDHC_Type *)USDHC1_BASE)
#define	USDHC2_BASE   (0x4041C000u)
#define	USDHC2   ((USDHC_Type *)USDHC2_BASE)
#define	USDHC_BASE_ADDRS   { 0u, USDHC1_BASE, USDHC2_BASE }
#define	USDHC_BASE_PTRS   { (USDHC_Type *)0u, USDHC1, USDHC2 }
#define	USDHC_IRQS   { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
#define	USDHC1_BASE   (0x40418000u)
#define	USDHC1   ((USDHC_Type *)USDHC1_BASE)
#define	USDHC2_BASE   (0x4041C000u)
#define	USDHC2   ((USDHC_Type *)USDHC2_BASE)
#define	USDHC_BASE_ADDRS   { 0u, USDHC1_BASE, USDHC2_BASE }
#define	USDHC_BASE_PTRS   { (USDHC_Type *)0u, USDHC1, USDHC2 }
#define	USDHC_IRQS   { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }

Detailed Description

Macro Definition Documentation

USDHC1 [1/3]

#define USDHC1   ((USDHC_Type *)USDHC1_BASE)

Peripheral USDHC1 base pointer

USDHC1 [2/3]

#define USDHC1   ((USDHC_Type *)USDHC1_BASE)

Peripheral USDHC1 base pointer

USDHC1 [3/3]

#define USDHC1   ((USDHC_Type *)USDHC1_BASE)

Peripheral USDHC1 base pointer

USDHC1_BASE [1/3]

#define USDHC1_BASE   (0x402C0000u)

Peripheral USDHC1 base address

USDHC1_BASE [2/3]

#define USDHC1_BASE   (0x40418000u)

Peripheral USDHC1 base address

USDHC1_BASE [3/3]

#define USDHC1_BASE   (0x40418000u)

Peripheral USDHC1 base address

USDHC2 [1/3]

#define USDHC2   ((USDHC_Type *)USDHC2_BASE)

Peripheral USDHC2 base pointer

USDHC2 [2/3]

#define USDHC2   ((USDHC_Type *)USDHC2_BASE)

Peripheral USDHC2 base pointer

USDHC2 [3/3]

#define USDHC2   ((USDHC_Type *)USDHC2_BASE)

Peripheral USDHC2 base pointer

USDHC2_BASE [1/3]

#define USDHC2_BASE   (0x402C4000u)

Peripheral USDHC2 base address

USDHC2_BASE [2/3]

#define USDHC2_BASE   (0x4041C000u)

Peripheral USDHC2 base address

USDHC2_BASE [3/3]

#define USDHC2_BASE   (0x4041C000u)

Peripheral USDHC2 base address

USDHC_BASE_ADDRS [1/3]

#define USDHC_BASE_ADDRS   { 0u, USDHC1_BASE, USDHC2_BASE }

Array initializer of USDHC peripheral base addresses

USDHC_BASE_ADDRS [2/3]

#define USDHC_BASE_ADDRS   { 0u, USDHC1_BASE, USDHC2_BASE }

Array initializer of USDHC peripheral base addresses

USDHC_BASE_ADDRS [3/3]

#define USDHC_BASE_ADDRS   { 0u, USDHC1_BASE, USDHC2_BASE }

Array initializer of USDHC peripheral base addresses

USDHC_BASE_PTRS [1/3]

#define USDHC_BASE_PTRS   { (USDHC_Type *)0u, USDHC1, USDHC2 }

Array initializer of USDHC peripheral base pointers

USDHC_BASE_PTRS [2/3]

#define USDHC_BASE_PTRS   { (USDHC_Type *)0u, USDHC1, USDHC2 }

Array initializer of USDHC peripheral base pointers

USDHC_BASE_PTRS [3/3]

#define USDHC_BASE_PTRS   { (USDHC_Type *)0u, USDHC1, USDHC2 }

Array initializer of USDHC peripheral base pointers

USDHC_IRQS [1/3]

#define USDHC_IRQS   { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }

Interrupt vectors for the USDHC peripheral type

USDHC_IRQS [2/3]

#define USDHC_IRQS   { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }

Interrupt vectors for the USDHC peripheral type

USDHC_IRQS [3/3]

#define USDHC_IRQS   { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }

Interrupt vectors for the USDHC peripheral type