SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)

SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)

SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)

SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)

SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)

SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)

SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)

SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)

SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)

SW_MUX_CTL_PAD_WAKEUP_DIG - SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK)

SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG - SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK)

SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG - SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK)

SW_PAD_CTL_PAD_TEST_MODE_DIG - SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_POR_B_DIG - SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_ONOFF_DIG - SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_WAKEUP_DIG - SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG - SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG - SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK)

SW_MUX_CTL_PAD_WAKEUP_DIG - SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK)

SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG - SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK)

SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG - SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK)

SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register
#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK (0x7U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK (0x10U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT (4U)

#define	IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK)

SW_PAD_CTL_PAD_TEST_MODE_DIG - SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_POR_B_DIG - SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_ONOFF_DIG - SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_WAKEUP_DIG - SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG - SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG - SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK)

SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register
#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK (0x1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT (0U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK (0x2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT (1U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK (0x4U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT (2U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK (0x8U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT (3U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK (0x40U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT (6U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK (0x30000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT (28U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK)

Detailed Description

Macro Definition Documentation

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER0 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO03 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER0 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO03 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_00_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_00_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER1 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO04 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER1 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO04 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_01_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_01_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER2 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO05 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER2 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO05 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_02_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_02_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER3 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO06 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER3 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO06 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_03_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_03_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER4 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO07 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER4 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO07 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_04_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_04_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER5 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO08 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER5 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO08 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_05_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_05_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER6 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO09 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER6 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO09 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_06_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_06_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER7 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO10 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER7 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO10 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_07_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_07_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER8 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO11 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER8 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO11 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_08_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_08_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER9 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO12 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER9 of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO12 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_09_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_SNVS_09_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO01 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: SNVS_LP 0b101..Select mux mode: ALT5 mux port: GPIO13_IO01 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad PMIC_ON_REQ_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad PMIC_ON_REQ_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: SNVS_PMIC_ON_REQ of instance: snvs 0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad PMIC_ON_REQ 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: CCM 0b101..Select mux mode: ALT5 mux port: GPIO13_IO02 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: CCM 0b101..Select mux mode: ALT5 mux port: GPIO13_IO02 of instance: GPIO13

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad PMIC_STBY_REQ_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad PMIC_STBY_REQ_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_STBY_REQ of instance: ccm 0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad PMIC_STBY_REQ 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b101..Select mux mode: ALT5 mux port: GPIO13_IO00 of instance: GPIO13 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: NMI_GLUE

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b101..Select mux mode: ALT5 mux port: GPIO13_IO00 of instance: GPIO13 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: NMI_GLUE

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION [1/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad WAKEUP_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION [2/2]

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad WAKEUP_DIG 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 0b111..Select mux mode: ALT7 mux port: NMI of instance: CM7

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION

#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad WAKEUP 0b0..Input Path is determined by functionality

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)

DSE - Drive Strength Field 0b000..HI-Z 0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V 0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V 0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V 0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V 0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V 0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V 0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled (CMOS input) 0b1..Hysteresis Enabled (Schmitt Trigger input)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled (Output is CMOS) 0b1..Open Drain Enabled (Output is Open Drain)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)

PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. 0b0..Keep the previous output value when the output driver is disabled. 0b1..Pull-up or pull-down (determined by PUS field).

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)

PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)

SPEED - Speed Field 0b10..100MHz

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)

DSE - Drive Strength Field 0b000..HI-Z 0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V 0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V 0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V 0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V 0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V 0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V 0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled (CMOS input) 0b1..Hysteresis Enabled (Schmitt Trigger input)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled (Output is CMOS) 0b1..Open Drain Enabled (Output is Open Drain)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)

PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. 0b0..Keep the previous output value when the output driver is disabled. 0b1..Pull-up or pull-down (determined by PUS field).

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)

PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)

SPEED - Speed Field 0b10..100MHz

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)

DSE - Drive Strength Field 0b000..HI-Z 0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V 0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V 0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V 0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V 0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V 0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V 0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled (CMOS input) 0b1..Hysteresis Enabled (Schmitt Trigger input)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled (Output is CMOS) 0b1..Open Drain Enabled (Output is Open Drain)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)

PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. 0b0..Keep the previous output value when the output driver is disabled. 0b1..Pull-up or pull-down (determined by PUS field).

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)

PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)

SPEED - Speed Field 0b10..100MHz

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)

DSE - Drive Strength Field 0b000..HI-Z 0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V 0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V 0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V 0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V 0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V 0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V 0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled (CMOS input) 0b1..Hysteresis Enabled (Schmitt Trigger input)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled (Output is CMOS) 0b1..Open Drain Enabled (Output is Open Drain)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)

PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. 0b0..Keep the previous output value when the output driver is disabled. 0b1..Pull-up or pull-down (determined by PUS field).

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)

PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)

SPEED - Speed Field 0b10..100MHz

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)

DSE - Drive Strength Field 0b000..HI-Z 0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V 0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V 0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V 0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V 0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V 0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V 0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled (CMOS input) 0b1..Hysteresis Enabled (Schmitt Trigger input)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled (Output is CMOS) 0b1..Open Drain Enabled (Output is Open Drain)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)

PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. 0b0..Keep the previous output value when the output driver is disabled. 0b1..Pull-up or pull-down (determined by PUS field).

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)

PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)

SPEED - Speed Field 0b10..100MHz

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK)

ODE_SNVS - Open Drain SNVS Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE [1/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE [2/2]

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)

DSE - Drive Strength Field 0b000..HI-Z 0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V 0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V 0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V 0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V 0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V 0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V 0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled (CMOS input) 0b1..Hysteresis Enabled (Schmitt Trigger input)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled (Output is CMOS) 0b1..Open Drain Enabled (Output is Open Drain)

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)

PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. 0b0..Keep the previous output value when the output driver is disabled. 0b1..Pull-up or pull-down (determined by PUS field).

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)

PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)

SPEED - Speed Field 0b10..100MHz

◆ IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE

#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register

SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register

SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register

SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register

SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register

SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register

SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register

SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register

SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register

SW_MUX_CTL_PAD_WAKEUP_DIG - SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register

SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG - SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register

SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG - SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register

SW_PAD_CTL_PAD_TEST_MODE_DIG - SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register

SW_PAD_CTL_PAD_POR_B_DIG - SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register

SW_PAD_CTL_PAD_ONOFF_DIG - SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register

SW_PAD_CTL_PAD_WAKEUP_DIG - SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register

SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG - SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register

SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG - SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register

SW_MUX_CTL_PAD_WAKEUP_DIG - SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register

SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG - SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register

SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG - SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register

SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register

SW_PAD_CTL_PAD_TEST_MODE_DIG - SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register

SW_PAD_CTL_PAD_POR_B_DIG - SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register

SW_PAD_CTL_PAD_ONOFF_DIG - SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register

SW_PAD_CTL_PAD_WAKEUP_DIG - SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register

SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG - SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register

SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG - SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register

SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register

Detailed Description

Macro Definition Documentation

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE [1/2]

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE [2/2]

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION [1/2]

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION [2/2]

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE [1/2]

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE [2/2]

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION [1/2]

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION [2/2]

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE [1/2]

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE [2/2]

◆ IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION [1/2]