CAN Peripheral Access Layer

Modules
	CAN Register Masks

Data Structures
struct	CAN_Type

Macros
#define	CAN1_BASE   (0x401D0000u)
#define	CAN1   ((CAN_Type *)CAN1_BASE)
#define	CAN2_BASE   (0x401D4000u)
#define	CAN2   ((CAN_Type *)CAN2_BASE)
#define	CAN_BASE_ADDRS   { 0u, CAN1_BASE, CAN2_BASE }
#define	CAN_BASE_PTRS   { (CAN_Type *)0u, CAN1, CAN2 }
#define	CAN_Rx_Warning_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
#define	CAN_Tx_Warning_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
#define	CAN_Wake_Up_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
#define	CAN_Error_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
#define	CAN_Bus_Off_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
#define	CAN_ORed_Message_buffer_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
#define	CAN_ECR_TXERRCNT_MASK   CAN_ECR_TX_ERR_COUNTER_MASK
#define	CAN_ECR_TXERRCNT_SHIFT   CAN_ECR_TX_ERR_COUNTER_SHIFT
#define	CAN_ECR_TXERRCNT(x)   CAN_ECR_TX_ERR_COUNTER(x)
#define	CAN_ECR_RXERRCNT_MASK   CAN_ECR_RX_ERR_COUNTER_MASK
#define	CAN_ECR_RXERRCNT_SHIFT   CAN_ECR_RX_ERR_COUNTER_SHIFT
#define	CAN_ECR_RXERRCNT(x)   CAN_ECR_RX_ERR_COUNTER(x)
#define	CAN1_BASE   (0x400C4000u)
#define	CAN1   ((CAN_Type *)CAN1_BASE)
#define	CAN2_BASE   (0x400C8000u)
#define	CAN2   ((CAN_Type *)CAN2_BASE)
#define	CAN3_BASE   (0x40C3C000u)
#define	CAN3   ((CAN_Type *)CAN3_BASE)
#define	CAN_BASE_ADDRS   { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
#define	CAN_BASE_PTRS   { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
#define	CAN_Rx_Warning_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Tx_Warning_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Wake_Up_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Error_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Bus_Off_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_ORed_Message_buffer_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN1_BASE   (0x400C4000u)
#define	CAN1   ((CAN_Type *)CAN1_BASE)
#define	CAN2_BASE   (0x400C8000u)
#define	CAN2   ((CAN_Type *)CAN2_BASE)
#define	CAN3_BASE   (0x40C3C000u)
#define	CAN3   ((CAN_Type *)CAN3_BASE)
#define	CAN_BASE_ADDRS   { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
#define	CAN_BASE_PTRS   { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
#define	CAN_Rx_Warning_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Tx_Warning_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Wake_Up_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Error_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_Bus_Off_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define	CAN_ORed_Message_buffer_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }

Detailed Description

Macro Definition Documentation

CAN1 [1/3]

#define CAN1   ((CAN_Type *)CAN1_BASE)

Peripheral CAN1 base pointer

CAN1 [2/3]

#define CAN1   ((CAN_Type *)CAN1_BASE)

Peripheral CAN1 base pointer

CAN1 [3/3]

#define CAN1   ((CAN_Type *)CAN1_BASE)

Peripheral CAN1 base pointer

CAN1_BASE [1/3]

#define CAN1_BASE   (0x401D0000u)

Peripheral CAN1 base address

CAN1_BASE [2/3]

#define CAN1_BASE   (0x400C4000u)

Peripheral CAN1 base address

CAN1_BASE [3/3]

#define CAN1_BASE   (0x400C4000u)

Peripheral CAN1 base address

CAN2 [1/3]

#define CAN2   ((CAN_Type *)CAN2_BASE)

Peripheral CAN2 base pointer

CAN2 [2/3]

#define CAN2   ((CAN_Type *)CAN2_BASE)

Peripheral CAN2 base pointer

CAN2 [3/3]

#define CAN2   ((CAN_Type *)CAN2_BASE)

Peripheral CAN2 base pointer

CAN2_BASE [1/3]

#define CAN2_BASE   (0x401D4000u)

Peripheral CAN2 base address

CAN2_BASE [2/3]

#define CAN2_BASE   (0x400C8000u)

Peripheral CAN2 base address

CAN2_BASE [3/3]

#define CAN2_BASE   (0x400C8000u)

Peripheral CAN2 base address

CAN3 [1/2]

#define CAN3   ((CAN_Type *)CAN3_BASE)

Peripheral CAN3 base pointer

CAN3 [2/2]

#define CAN3   ((CAN_Type *)CAN3_BASE)

Peripheral CAN3 base pointer

CAN3_BASE [1/2]

#define CAN3_BASE   (0x40C3C000u)

Peripheral CAN3 base address

CAN3_BASE [2/2]

#define CAN3_BASE   (0x40C3C000u)

Peripheral CAN3 base address

CAN_BASE_ADDRS [1/3]

#define CAN_BASE_ADDRS   { 0u, CAN1_BASE, CAN2_BASE }

Array initializer of CAN peripheral base addresses

CAN_BASE_ADDRS [2/3]

#define CAN_BASE_ADDRS   { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }

Array initializer of CAN peripheral base addresses

CAN_BASE_ADDRS [3/3]

#define CAN_BASE_ADDRS   { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }

Array initializer of CAN peripheral base addresses

CAN_BASE_PTRS [1/3]

#define CAN_BASE_PTRS   { (CAN_Type *)0u, CAN1, CAN2 }

Array initializer of CAN peripheral base pointers

CAN_BASE_PTRS [2/3]

#define CAN_BASE_PTRS   { (CAN_Type *)0u, CAN1, CAN2, CAN3 }

Array initializer of CAN peripheral base pointers

CAN_BASE_PTRS [3/3]

#define CAN_BASE_PTRS   { (CAN_Type *)0u, CAN1, CAN2, CAN3 }

Array initializer of CAN peripheral base pointers

CAN_Rx_Warning_IRQS [1/3]

#define CAN_Rx_Warning_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }

Interrupt vectors for the CAN peripheral type

CAN_Rx_Warning_IRQS [2/3]

#define CAN_Rx_Warning_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }

Interrupt vectors for the CAN peripheral type

CAN_Rx_Warning_IRQS [3/3]

#define CAN_Rx_Warning_IRQS   { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }

Interrupt vectors for the CAN peripheral type