RTEMS 6.1-rc1
Modules | Data Structures | Macros

Modules

 TMR Register Masks
 

Data Structures

struct  TMR_Type
 

Macros

#define TMR1_BASE   (0x401DC000u)
 
#define TMR1   ((TMR_Type *)TMR1_BASE)
 
#define TMR2_BASE   (0x401E0000u)
 
#define TMR2   ((TMR_Type *)TMR2_BASE)
 
#define TMR3_BASE   (0x401E4000u)
 
#define TMR3   ((TMR_Type *)TMR3_BASE)
 
#define TMR4_BASE   (0x401E8000u)
 
#define TMR4   ((TMR_Type *)TMR4_BASE)
 
#define TMR_BASE_ADDRS   { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
 
#define TMR_BASE_PTRS   { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
 
#define TMR_IRQS   { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
 
#define TMR1_BASE   (0x4015C000u)
 
#define TMR1   ((TMR_Type *)TMR1_BASE)
 
#define TMR2_BASE   (0x40160000u)
 
#define TMR2   ((TMR_Type *)TMR2_BASE)
 
#define TMR3_BASE   (0x40164000u)
 
#define TMR3   ((TMR_Type *)TMR3_BASE)
 
#define TMR4_BASE   (0x40168000u)
 
#define TMR4   ((TMR_Type *)TMR4_BASE)
 
#define TMR_BASE_ADDRS   { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
 
#define TMR_BASE_PTRS   { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
 
#define TMR_IRQS   { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
 
#define TMR1_BASE   (0x4015C000u)
 
#define TMR1   ((TMR_Type *)TMR1_BASE)
 
#define TMR2_BASE   (0x40160000u)
 
#define TMR2   ((TMR_Type *)TMR2_BASE)
 
#define TMR3_BASE   (0x40164000u)
 
#define TMR3   ((TMR_Type *)TMR3_BASE)
 
#define TMR4_BASE   (0x40168000u)
 
#define TMR4   ((TMR_Type *)TMR4_BASE)
 
#define TMR_BASE_ADDRS   { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
 
#define TMR_BASE_PTRS   { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
 
#define TMR_IRQS   { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
 

Detailed Description

Macro Definition Documentation

◆ TMR1 [1/3]

#define TMR1   ((TMR_Type *)TMR1_BASE)

Peripheral TMR1 base pointer

◆ TMR1 [2/3]

#define TMR1   ((TMR_Type *)TMR1_BASE)

Peripheral TMR1 base pointer

◆ TMR1 [3/3]

#define TMR1   ((TMR_Type *)TMR1_BASE)

Peripheral TMR1 base pointer

◆ TMR1_BASE [1/3]

#define TMR1_BASE   (0x401DC000u)

Peripheral TMR1 base address

◆ TMR1_BASE [2/3]

#define TMR1_BASE   (0x4015C000u)

Peripheral TMR1 base address

◆ TMR1_BASE [3/3]

#define TMR1_BASE   (0x4015C000u)

Peripheral TMR1 base address

◆ TMR2 [1/3]

#define TMR2   ((TMR_Type *)TMR2_BASE)

Peripheral TMR2 base pointer

◆ TMR2 [2/3]

#define TMR2   ((TMR_Type *)TMR2_BASE)

Peripheral TMR2 base pointer

◆ TMR2 [3/3]

#define TMR2   ((TMR_Type *)TMR2_BASE)

Peripheral TMR2 base pointer

◆ TMR2_BASE [1/3]

#define TMR2_BASE   (0x401E0000u)

Peripheral TMR2 base address

◆ TMR2_BASE [2/3]

#define TMR2_BASE   (0x40160000u)

Peripheral TMR2 base address

◆ TMR2_BASE [3/3]

#define TMR2_BASE   (0x40160000u)

Peripheral TMR2 base address

◆ TMR3 [1/3]

#define TMR3   ((TMR_Type *)TMR3_BASE)

Peripheral TMR3 base pointer

◆ TMR3 [2/3]

#define TMR3   ((TMR_Type *)TMR3_BASE)

Peripheral TMR3 base pointer

◆ TMR3 [3/3]

#define TMR3   ((TMR_Type *)TMR3_BASE)

Peripheral TMR3 base pointer

◆ TMR3_BASE [1/3]

#define TMR3_BASE   (0x401E4000u)

Peripheral TMR3 base address

◆ TMR3_BASE [2/3]

#define TMR3_BASE   (0x40164000u)

Peripheral TMR3 base address

◆ TMR3_BASE [3/3]

#define TMR3_BASE   (0x40164000u)

Peripheral TMR3 base address

◆ TMR4 [1/3]

#define TMR4   ((TMR_Type *)TMR4_BASE)

Peripheral TMR4 base pointer

◆ TMR4 [2/3]

#define TMR4   ((TMR_Type *)TMR4_BASE)

Peripheral TMR4 base pointer

◆ TMR4 [3/3]

#define TMR4   ((TMR_Type *)TMR4_BASE)

Peripheral TMR4 base pointer

◆ TMR4_BASE [1/3]

#define TMR4_BASE   (0x401E8000u)

Peripheral TMR4 base address

◆ TMR4_BASE [2/3]

#define TMR4_BASE   (0x40168000u)

Peripheral TMR4 base address

◆ TMR4_BASE [3/3]

#define TMR4_BASE   (0x40168000u)

Peripheral TMR4 base address

◆ TMR_BASE_ADDRS [1/3]

#define TMR_BASE_ADDRS   { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }

Array initializer of TMR peripheral base addresses

◆ TMR_BASE_ADDRS [2/3]

#define TMR_BASE_ADDRS   { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }

Array initializer of TMR peripheral base addresses

◆ TMR_BASE_ADDRS [3/3]

#define TMR_BASE_ADDRS   { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }

Array initializer of TMR peripheral base addresses

◆ TMR_BASE_PTRS [1/3]

#define TMR_BASE_PTRS   { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }

Array initializer of TMR peripheral base pointers

◆ TMR_BASE_PTRS [2/3]

#define TMR_BASE_PTRS   { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }

Array initializer of TMR peripheral base pointers

◆ TMR_BASE_PTRS [3/3]

#define TMR_BASE_PTRS   { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }

Array initializer of TMR peripheral base pointers

◆ TMR_IRQS [1/3]

#define TMR_IRQS   { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }

Interrupt vectors for the TMR peripheral type

◆ TMR_IRQS [2/3]

#define TMR_IRQS   { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }

Interrupt vectors for the TMR peripheral type

◆ TMR_IRQS [3/3]

#define TMR_IRQS   { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }

Interrupt vectors for the TMR peripheral type