CR0 - CMP Control Register 0
#define	CMP_CR0_HYSTCTR_MASK (0x3U)

#define	CMP_CR0_HYSTCTR_SHIFT (0U)

#define	CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)

#define	CMP_CR0_FILTER_CNT_MASK (0x70U)

#define	CMP_CR0_FILTER_CNT_SHIFT (4U)

#define	CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)

CR1 - CMP Control Register 1
#define	CMP_CR1_EN_MASK (0x1U)

#define	CMP_CR1_EN_SHIFT (0U)

#define	CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)

#define	CMP_CR1_OPE_MASK (0x2U)

#define	CMP_CR1_OPE_SHIFT (1U)

#define	CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)

#define	CMP_CR1_COS_MASK (0x4U)

#define	CMP_CR1_COS_SHIFT (2U)

#define	CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)

#define	CMP_CR1_INV_MASK (0x8U)

#define	CMP_CR1_INV_SHIFT (3U)

#define	CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)

#define	CMP_CR1_PMODE_MASK (0x10U)

#define	CMP_CR1_PMODE_SHIFT (4U)

#define	CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)

#define	CMP_CR1_WE_MASK (0x40U)

#define	CMP_CR1_WE_SHIFT (6U)

#define	CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)

#define	CMP_CR1_SE_MASK (0x80U)

#define	CMP_CR1_SE_SHIFT (7U)

#define	CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)

FPR - CMP Filter Period Register
#define	CMP_FPR_FILT_PER_MASK (0xFFU)

#define	CMP_FPR_FILT_PER_SHIFT (0U)

#define	CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)

SCR - CMP Status and Control Register
#define	CMP_SCR_COUT_MASK (0x1U)

#define	CMP_SCR_COUT_SHIFT (0U)

#define	CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)

#define	CMP_SCR_CFF_MASK (0x2U)

#define	CMP_SCR_CFF_SHIFT (1U)

#define	CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)

#define	CMP_SCR_CFR_MASK (0x4U)

#define	CMP_SCR_CFR_SHIFT (2U)

#define	CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)

#define	CMP_SCR_IEF_MASK (0x8U)

#define	CMP_SCR_IEF_SHIFT (3U)

#define	CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)

#define	CMP_SCR_IER_MASK (0x10U)

#define	CMP_SCR_IER_SHIFT (4U)

#define	CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)

#define	CMP_SCR_DMAEN_MASK (0x40U)

#define	CMP_SCR_DMAEN_SHIFT (6U)

#define	CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)

DACCR - DAC Control Register
#define	CMP_DACCR_VOSEL_MASK (0x3FU)

#define	CMP_DACCR_VOSEL_SHIFT (0U)

#define	CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)

#define	CMP_DACCR_VRSEL_MASK (0x40U)

#define	CMP_DACCR_VRSEL_SHIFT (6U)

#define	CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)

#define	CMP_DACCR_DACEN_MASK (0x80U)

#define	CMP_DACCR_DACEN_SHIFT (7U)

#define	CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)

MUXCR - MUX Control Register
#define	CMP_MUXCR_MSEL_MASK (0x7U)

#define	CMP_MUXCR_MSEL_SHIFT (0U)

#define	CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)

#define	CMP_MUXCR_PSEL_MASK (0x38U)

#define	CMP_MUXCR_PSEL_SHIFT (3U)

#define	CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)

VERID - Version ID Register
#define	CMP_VERID_FEATURE_MASK (0xFFFFU)

#define	CMP_VERID_FEATURE_SHIFT (0U)

#define	CMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)

#define	CMP_VERID_MINOR_MASK (0xFF0000U)

#define	CMP_VERID_MINOR_SHIFT (16U)

#define	CMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)

#define	CMP_VERID_MAJOR_MASK (0xFF000000U)

#define	CMP_VERID_MAJOR_SHIFT (24U)

#define	CMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	CMP_PARAM_PARAM_MASK (0xFFFFFFFFU)

#define	CMP_PARAM_PARAM_SHIFT (0U)

#define	CMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)

C0 - CMP Control Register 0
#define	CMP_C0_HYSTCTR_MASK (0x3U)

#define	CMP_C0_HYSTCTR_SHIFT (0U)

#define	CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)

#define	CMP_C0_FILTER_CNT_MASK (0x70U)

#define	CMP_C0_FILTER_CNT_SHIFT (4U)

#define	CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)

#define	CMP_C0_EN_MASK (0x100U)

#define	CMP_C0_EN_SHIFT (8U)

#define	CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)

#define	CMP_C0_OPE_MASK (0x200U)

#define	CMP_C0_OPE_SHIFT (9U)

#define	CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)

#define	CMP_C0_COS_MASK (0x400U)

#define	CMP_C0_COS_SHIFT (10U)

#define	CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)

#define	CMP_C0_INVT_MASK (0x800U)

#define	CMP_C0_INVT_SHIFT (11U)

#define	CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)

#define	CMP_C0_PMODE_MASK (0x1000U)

#define	CMP_C0_PMODE_SHIFT (12U)

#define	CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)

#define	CMP_C0_WE_MASK (0x4000U)

#define	CMP_C0_WE_SHIFT (14U)

#define	CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)

#define	CMP_C0_SE_MASK (0x8000U)

#define	CMP_C0_SE_SHIFT (15U)

#define	CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)

#define	CMP_C0_FPR_MASK (0xFF0000U)

#define	CMP_C0_FPR_SHIFT (16U)

#define	CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)

#define	CMP_C0_COUT_MASK (0x1000000U)

#define	CMP_C0_COUT_SHIFT (24U)

#define	CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)

#define	CMP_C0_CFF_MASK (0x2000000U)

#define	CMP_C0_CFF_SHIFT (25U)

#define	CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)

#define	CMP_C0_CFR_MASK (0x4000000U)

#define	CMP_C0_CFR_SHIFT (26U)

#define	CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)

#define	CMP_C0_IEF_MASK (0x8000000U)

#define	CMP_C0_IEF_SHIFT (27U)

#define	CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)

#define	CMP_C0_IER_MASK (0x10000000U)

#define	CMP_C0_IER_SHIFT (28U)

#define	CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)

#define	CMP_C0_DMAEN_MASK (0x40000000U)

#define	CMP_C0_DMAEN_SHIFT (30U)

#define	CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)

#define	CMP_C0_LINKEN_MASK (0x80000000U)

#define	CMP_C0_LINKEN_SHIFT (31U)

#define	CMP_C0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)

C1 - CMP Control Register 1
#define	CMP_C1_VOSEL_MASK (0xFFU)

#define	CMP_C1_VOSEL_SHIFT (0U)

#define	CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)

#define	CMP_C1_DMODE_MASK (0x100U)

#define	CMP_C1_DMODE_SHIFT (8U)

#define	CMP_C1_DMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)

#define	CMP_C1_VRSEL_MASK (0x200U)

#define	CMP_C1_VRSEL_SHIFT (9U)

#define	CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)

#define	CMP_C1_DACEN_MASK (0x400U)

#define	CMP_C1_DACEN_SHIFT (10U)

#define	CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)

#define	CMP_C1_CHN0_MASK (0x10000U)

#define	CMP_C1_CHN0_SHIFT (16U)

#define	CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)

#define	CMP_C1_CHN1_MASK (0x20000U)

#define	CMP_C1_CHN1_SHIFT (17U)

#define	CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)

#define	CMP_C1_CHN2_MASK (0x40000U)

#define	CMP_C1_CHN2_SHIFT (18U)

#define	CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)

#define	CMP_C1_CHN3_MASK (0x80000U)

#define	CMP_C1_CHN3_SHIFT (19U)

#define	CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)

#define	CMP_C1_CHN4_MASK (0x100000U)

#define	CMP_C1_CHN4_SHIFT (20U)

#define	CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)

#define	CMP_C1_CHN5_MASK (0x200000U)

#define	CMP_C1_CHN5_SHIFT (21U)

#define	CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)

#define	CMP_C1_MSEL_MASK (0x7000000U)

#define	CMP_C1_MSEL_SHIFT (24U)

#define	CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)

#define	CMP_C1_PSEL_MASK (0x70000000U)

#define	CMP_C1_PSEL_SHIFT (28U)

#define	CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)

C2 - CMP Control Register 2
#define	CMP_C2_ACOn_MASK (0x3FU)

#define	CMP_C2_ACOn_SHIFT (0U)

#define	CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)

#define	CMP_C2_INITMOD_MASK (0x3F00U)

#define	CMP_C2_INITMOD_SHIFT (8U)

#define	CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)

#define	CMP_C2_NSAM_MASK (0xC000U)

#define	CMP_C2_NSAM_SHIFT (14U)

#define	CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)

#define	CMP_C2_CH0F_MASK (0x10000U)

#define	CMP_C2_CH0F_SHIFT (16U)

#define	CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)

#define	CMP_C2_CH1F_MASK (0x20000U)

#define	CMP_C2_CH1F_SHIFT (17U)

#define	CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)

#define	CMP_C2_CH2F_MASK (0x40000U)

#define	CMP_C2_CH2F_SHIFT (18U)

#define	CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)

#define	CMP_C2_CH3F_MASK (0x80000U)

#define	CMP_C2_CH3F_SHIFT (19U)

#define	CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)

#define	CMP_C2_CH4F_MASK (0x100000U)

#define	CMP_C2_CH4F_SHIFT (20U)

#define	CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)

#define	CMP_C2_CH5F_MASK (0x200000U)

#define	CMP_C2_CH5F_SHIFT (21U)

#define	CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)

#define	CMP_C2_FXMXCH_MASK (0xE000000U)

#define	CMP_C2_FXMXCH_SHIFT (25U)

#define	CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)

#define	CMP_C2_FXMP_MASK (0x20000000U)

#define	CMP_C2_FXMP_SHIFT (29U)

#define	CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)

#define	CMP_C2_RRIE_MASK (0x40000000U)

#define	CMP_C2_RRIE_SHIFT (30U)

#define	CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)

C3 - CMP Control Register 3
#define	CMP_C3_ACPH2TC_MASK (0x70U)

#define	CMP_C3_ACPH2TC_SHIFT (4U)

#define	CMP_C3_ACPH2TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)

#define	CMP_C3_ACPH1TC_MASK (0x700U)

#define	CMP_C3_ACPH1TC_SHIFT (8U)

#define	CMP_C3_ACPH1TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)

#define	CMP_C3_ACSAT_MASK (0x7000U)

#define	CMP_C3_ACSAT_SHIFT (12U)

#define	CMP_C3_ACSAT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)

#define	CMP_C3_DMCS_MASK (0x10000U)

#define	CMP_C3_DMCS_SHIFT (16U)

#define	CMP_C3_DMCS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)

#define	CMP_C3_RDIVE_MASK (0x100000U)

#define	CMP_C3_RDIVE_SHIFT (20U)

#define	CMP_C3_RDIVE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)

#define	CMP_C3_NCHCTEN_MASK (0x1000000U)

#define	CMP_C3_NCHCTEN_SHIFT (24U)

#define	CMP_C3_NCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)

#define	CMP_C3_PCHCTEN_MASK (0x10000000U)

#define	CMP_C3_PCHCTEN_SHIFT (28U)

#define	CMP_C3_PCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)

VERID - Version ID Register
#define	CMP_VERID_FEATURE_MASK (0xFFFFU)

#define	CMP_VERID_FEATURE_SHIFT (0U)

#define	CMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)

#define	CMP_VERID_MINOR_MASK (0xFF0000U)

#define	CMP_VERID_MINOR_SHIFT (16U)

#define	CMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)

#define	CMP_VERID_MAJOR_MASK (0xFF000000U)

#define	CMP_VERID_MAJOR_SHIFT (24U)

#define	CMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	CMP_PARAM_PARAM_MASK (0xFFFFFFFFU)

#define	CMP_PARAM_PARAM_SHIFT (0U)

#define	CMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)

C0 - CMP Control Register 0
#define	CMP_C0_HYSTCTR_MASK (0x3U)

#define	CMP_C0_HYSTCTR_SHIFT (0U)

#define	CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)

#define	CMP_C0_FILTER_CNT_MASK (0x70U)

#define	CMP_C0_FILTER_CNT_SHIFT (4U)

#define	CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)

#define	CMP_C0_EN_MASK (0x100U)

#define	CMP_C0_EN_SHIFT (8U)

#define	CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)

#define	CMP_C0_OPE_MASK (0x200U)

#define	CMP_C0_OPE_SHIFT (9U)

#define	CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)

#define	CMP_C0_COS_MASK (0x400U)

#define	CMP_C0_COS_SHIFT (10U)

#define	CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)

#define	CMP_C0_INVT_MASK (0x800U)

#define	CMP_C0_INVT_SHIFT (11U)

#define	CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)

#define	CMP_C0_PMODE_MASK (0x1000U)

#define	CMP_C0_PMODE_SHIFT (12U)

#define	CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)

#define	CMP_C0_WE_MASK (0x4000U)

#define	CMP_C0_WE_SHIFT (14U)

#define	CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)

#define	CMP_C0_SE_MASK (0x8000U)

#define	CMP_C0_SE_SHIFT (15U)

#define	CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)

#define	CMP_C0_FPR_MASK (0xFF0000U)

#define	CMP_C0_FPR_SHIFT (16U)

#define	CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)

#define	CMP_C0_COUT_MASK (0x1000000U)

#define	CMP_C0_COUT_SHIFT (24U)

#define	CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)

#define	CMP_C0_CFF_MASK (0x2000000U)

#define	CMP_C0_CFF_SHIFT (25U)

#define	CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)

#define	CMP_C0_CFR_MASK (0x4000000U)

#define	CMP_C0_CFR_SHIFT (26U)

#define	CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)

#define	CMP_C0_IEF_MASK (0x8000000U)

#define	CMP_C0_IEF_SHIFT (27U)

#define	CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)

#define	CMP_C0_IER_MASK (0x10000000U)

#define	CMP_C0_IER_SHIFT (28U)

#define	CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)

#define	CMP_C0_DMAEN_MASK (0x40000000U)

#define	CMP_C0_DMAEN_SHIFT (30U)

#define	CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)

#define	CMP_C0_LINKEN_MASK (0x80000000U)

#define	CMP_C0_LINKEN_SHIFT (31U)

#define	CMP_C0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)

C1 - CMP Control Register 1
#define	CMP_C1_VOSEL_MASK (0xFFU)

#define	CMP_C1_VOSEL_SHIFT (0U)

#define	CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)

#define	CMP_C1_DMODE_MASK (0x100U)

#define	CMP_C1_DMODE_SHIFT (8U)

#define	CMP_C1_DMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)

#define	CMP_C1_VRSEL_MASK (0x200U)

#define	CMP_C1_VRSEL_SHIFT (9U)

#define	CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)

#define	CMP_C1_DACEN_MASK (0x400U)

#define	CMP_C1_DACEN_SHIFT (10U)

#define	CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)

#define	CMP_C1_CHN0_MASK (0x10000U)

#define	CMP_C1_CHN0_SHIFT (16U)

#define	CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)

#define	CMP_C1_CHN1_MASK (0x20000U)

#define	CMP_C1_CHN1_SHIFT (17U)

#define	CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)

#define	CMP_C1_CHN2_MASK (0x40000U)

#define	CMP_C1_CHN2_SHIFT (18U)

#define	CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)

#define	CMP_C1_CHN3_MASK (0x80000U)

#define	CMP_C1_CHN3_SHIFT (19U)

#define	CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)

#define	CMP_C1_CHN4_MASK (0x100000U)

#define	CMP_C1_CHN4_SHIFT (20U)

#define	CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)

#define	CMP_C1_CHN5_MASK (0x200000U)

#define	CMP_C1_CHN5_SHIFT (21U)

#define	CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)

#define	CMP_C1_MSEL_MASK (0x7000000U)

#define	CMP_C1_MSEL_SHIFT (24U)

#define	CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)

#define	CMP_C1_PSEL_MASK (0x70000000U)

#define	CMP_C1_PSEL_SHIFT (28U)

#define	CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)

C2 - CMP Control Register 2
#define	CMP_C2_ACOn_MASK (0x3FU)

#define	CMP_C2_ACOn_SHIFT (0U)

#define	CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)

#define	CMP_C2_INITMOD_MASK (0x3F00U)

#define	CMP_C2_INITMOD_SHIFT (8U)

#define	CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)

#define	CMP_C2_NSAM_MASK (0xC000U)

#define	CMP_C2_NSAM_SHIFT (14U)

#define	CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)

#define	CMP_C2_CH0F_MASK (0x10000U)

#define	CMP_C2_CH0F_SHIFT (16U)

#define	CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)

#define	CMP_C2_CH1F_MASK (0x20000U)

#define	CMP_C2_CH1F_SHIFT (17U)

#define	CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)

#define	CMP_C2_CH2F_MASK (0x40000U)

#define	CMP_C2_CH2F_SHIFT (18U)

#define	CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)

#define	CMP_C2_CH3F_MASK (0x80000U)

#define	CMP_C2_CH3F_SHIFT (19U)

#define	CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)

#define	CMP_C2_CH4F_MASK (0x100000U)

#define	CMP_C2_CH4F_SHIFT (20U)

#define	CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)

#define	CMP_C2_CH5F_MASK (0x200000U)

#define	CMP_C2_CH5F_SHIFT (21U)

#define	CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)

#define	CMP_C2_FXMXCH_MASK (0xE000000U)

#define	CMP_C2_FXMXCH_SHIFT (25U)

#define	CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)

#define	CMP_C2_FXMP_MASK (0x20000000U)

#define	CMP_C2_FXMP_SHIFT (29U)

#define	CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)

#define	CMP_C2_RRIE_MASK (0x40000000U)

#define	CMP_C2_RRIE_SHIFT (30U)

#define	CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)

C3 - CMP Control Register 3
#define	CMP_C3_ACPH2TC_MASK (0x70U)

#define	CMP_C3_ACPH2TC_SHIFT (4U)

#define	CMP_C3_ACPH2TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)

#define	CMP_C3_ACPH1TC_MASK (0x700U)

#define	CMP_C3_ACPH1TC_SHIFT (8U)

#define	CMP_C3_ACPH1TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)

#define	CMP_C3_ACSAT_MASK (0x7000U)

#define	CMP_C3_ACSAT_SHIFT (12U)

#define	CMP_C3_ACSAT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)

#define	CMP_C3_DMCS_MASK (0x10000U)

#define	CMP_C3_DMCS_SHIFT (16U)

#define	CMP_C3_DMCS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)

#define	CMP_C3_RDIVE_MASK (0x100000U)

#define	CMP_C3_RDIVE_SHIFT (20U)

#define	CMP_C3_RDIVE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)

#define	CMP_C3_NCHCTEN_MASK (0x1000000U)

#define	CMP_C3_NCHCTEN_SHIFT (24U)

#define	CMP_C3_NCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)

#define	CMP_C3_PCHCTEN_MASK (0x10000000U)

#define	CMP_C3_PCHCTEN_SHIFT (28U)

#define	CMP_C3_PCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)

Detailed Description

Macro Definition Documentation

◆ CMP_C0_CFF [1/2]

#define CMP_C0_CFF ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)

CFF - Analog Comparator Flag Falling 0b0..A falling edge has not been detected on COUT. 0b1..A falling edge on COUT has occurred.

◆ CMP_C0_CFF [2/2]

#define CMP_C0_CFF ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)

CFF - Analog Comparator Flag Falling 0b0..A falling edge has not been detected on COUT. 0b1..A falling edge on COUT has occurred.

◆ CMP_C0_CFR [1/2]

#define CMP_C0_CFR ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)

CFR - Analog Comparator Flag Rising 0b0..A rising edge has not been detected on COUT. 0b1..A rising edge on COUT has occurred.

◆ CMP_C0_CFR [2/2]

#define CMP_C0_CFR ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)

CFR - Analog Comparator Flag Rising 0b0..A rising edge has not been detected on COUT. 0b1..A rising edge on COUT has occurred.

◆ CMP_C0_COS [1/2]

#define CMP_C0_COS ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)

COS - Comparator Output Select 0b0..Set CMPO to equal COUT (filtered comparator output). 0b1..Set CMPO to equal COUTA (unfiltered comparator output).

◆ CMP_C0_COS [2/2]

#define CMP_C0_COS ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)

COS - Comparator Output Select 0b0..Set CMPO to equal COUT (filtered comparator output). 0b1..Set CMPO to equal COUTA (unfiltered comparator output).

◆ CMP_C0_COUT [1/2]

#define CMP_C0_COUT ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)

COUT - Analog Comparator Output

◆ CMP_C0_COUT [2/2]

#define CMP_C0_COUT ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)

COUT - Analog Comparator Output

◆ CMP_C0_DMAEN [1/2]

#define CMP_C0_DMAEN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)

DMAEN - DMA Enable 0b0..DMA is disabled. 0b1..DMA is enabled.

◆ CMP_C0_DMAEN [2/2]

#define CMP_C0_DMAEN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)

DMAEN - DMA Enable 0b0..DMA is disabled. 0b1..DMA is enabled.

◆ CMP_C0_EN [1/2]

#define CMP_C0_EN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)

EN - Comparator Module Enable 0b0..Analog Comparator is disabled. 0b1..Analog Comparator is enabled.

◆ CMP_C0_EN [2/2]

#define CMP_C0_EN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)

EN - Comparator Module Enable 0b0..Analog Comparator is disabled. 0b1..Analog Comparator is enabled.

◆ CMP_C0_FILTER_CNT [1/2]

#define CMP_C0_FILTER_CNT ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)

FILTER_CNT - Filter Sample Count 0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. 0b001..1 consecutive sample must agree (comparator output is simply sampled). 0b010..2 consecutive samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5 consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.

◆ CMP_C0_FILTER_CNT [2/2]

#define CMP_C0_FILTER_CNT ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)

FILTER_CNT - Filter Sample Count 0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. 0b001..1 consecutive sample must agree (comparator output is simply sampled). 0b010..2 consecutive samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5 consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.

◆ CMP_C0_FPR [1/2]

#define CMP_C0_FPR ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)

FPR - Filter Sample Period

◆ CMP_C0_FPR [2/2]

#define CMP_C0_FPR ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)

FPR - Filter Sample Period

◆ CMP_C0_HYSTCTR [1/2]

#define CMP_C0_HYSTCTR ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)

HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level 0b00..The hard block output has level 0 hysteresis internally. 0b01..The hard block output has level 1 hysteresis internally. 0b10..The hard block output has level 2 hysteresis internally. 0b11..The hard block output has level 3 hysteresis internally.

◆ CMP_C0_HYSTCTR [2/2]

#define CMP_C0_HYSTCTR ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)

HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level 0b00..The hard block output has level 0 hysteresis internally. 0b01..The hard block output has level 1 hysteresis internally. 0b10..The hard block output has level 2 hysteresis internally. 0b11..The hard block output has level 3 hysteresis internally.

◆ CMP_C0_IEF [1/2]

#define CMP_C0_IEF ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)

IEF - Comparator Interrupt Enable Falling 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CMP_C0_IEF [2/2]

#define CMP_C0_IEF ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)

IEF - Comparator Interrupt Enable Falling 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CMP_C0_IER [1/2]

#define CMP_C0_IER ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)

IER - Comparator Interrupt Enable Rising 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CMP_C0_IER [2/2]

#define CMP_C0_IER ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)

IER - Comparator Interrupt Enable Rising 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CMP_C0_INVT [1/2]

#define CMP_C0_INVT ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)

INVT - Comparator invert 0b0..Does not invert the comparator output. 0b1..Inverts the comparator output.

◆ CMP_C0_INVT [2/2]

#define CMP_C0_INVT ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)

INVT - Comparator invert 0b0..Does not invert the comparator output. 0b1..Inverts the comparator output.

◆ CMP_C0_LINKEN [1/2]

#define CMP_C0_LINKEN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)

LINKEN - CMP to DAC link enable. 0b0..CMP to DAC link is disabled 0b1..CMP to DAC link is enabled.

◆ CMP_C0_LINKEN [2/2]

#define CMP_C0_LINKEN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)

LINKEN - CMP to DAC link enable. 0b0..CMP to DAC link is disabled 0b1..CMP to DAC link is enabled.

◆ CMP_C0_OPE [1/2]

#define CMP_C0_OPE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)

OPE - Comparator Output Pin Enable 0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. 0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.

◆ CMP_C0_OPE [2/2]

#define CMP_C0_OPE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)

OPE - Comparator Output Pin Enable 0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. 0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.

◆ CMP_C0_PMODE [1/2]

#define CMP_C0_PMODE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)

PMODE - Power Mode Select 0b0..Low Speed (LS) comparison mode is selected. 0b1..High Speed (HS) comparison mode is selected.

◆ CMP_C0_PMODE [2/2]

#define CMP_C0_PMODE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)

PMODE - Power Mode Select 0b0..Low Speed (LS) comparison mode is selected. 0b1..High Speed (HS) comparison mode is selected.

◆ CMP_C0_SE [1/2]

#define CMP_C0_SE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)

SE - Sample Enable 0b0..Sampling mode is not selected. 0b1..Sampling mode is selected.

◆ CMP_C0_SE [2/2]

#define CMP_C0_SE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)

SE - Sample Enable 0b0..Sampling mode is not selected. 0b1..Sampling mode is selected.

◆ CMP_C0_WE [1/2]

#define CMP_C0_WE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)

WE - Windowing Enable 0b0..Windowing mode is not selected. 0b1..Windowing mode is selected.

◆ CMP_C0_WE [2/2]

#define CMP_C0_WE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)

WE - Windowing Enable 0b0..Windowing mode is not selected. 0b1..Windowing mode is selected.

◆ CMP_C1_CHN0 [1/2]

#define CMP_C1_CHN0 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)

CHN0 - Channel 0 input enable

◆ CMP_C1_CHN0 [2/2]

#define CMP_C1_CHN0 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)

CHN0 - Channel 0 input enable

◆ CMP_C1_CHN1 [1/2]

#define CMP_C1_CHN1 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)

CHN1 - Channel 1 input enable

◆ CMP_C1_CHN1 [2/2]

#define CMP_C1_CHN1 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)

CHN1 - Channel 1 input enable

◆ CMP_C1_CHN2 [1/2]

#define CMP_C1_CHN2 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)

CHN2 - Channel 2 input enable

◆ CMP_C1_CHN2 [2/2]

#define CMP_C1_CHN2 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)

CHN2 - Channel 2 input enable

◆ CMP_C1_CHN3 [1/2]

#define CMP_C1_CHN3 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)

CHN3 - Channel 3 input enable

◆ CMP_C1_CHN3 [2/2]

#define CMP_C1_CHN3 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)

CHN3 - Channel 3 input enable

◆ CMP_C1_CHN4 [1/2]

#define CMP_C1_CHN4 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)

CHN4 - Channel 4 input enable

◆ CMP_C1_CHN4 [2/2]

#define CMP_C1_CHN4 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)

CHN4 - Channel 4 input enable

◆ CMP_C1_CHN5 [1/2]

#define CMP_C1_CHN5 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)

CHN5 - Channel 5 input enable

◆ CMP_C1_CHN5 [2/2]

#define CMP_C1_CHN5 ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)

CHN5 - Channel 5 input enable

◆ CMP_C1_DACEN [1/2]

#define CMP_C1_DACEN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)

DACEN - DAC Enable 0b0..DAC is disabled. 0b1..DAC is enabled.

◆ CMP_C1_DACEN [2/2]

#define CMP_C1_DACEN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)

DACEN - DAC Enable 0b0..DAC is disabled. 0b1..DAC is enabled.

◆ CMP_C1_DMODE [1/2]

#define CMP_C1_DMODE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)

DMODE - DAC Mode Selection 0b0..DAC is selected to work in low speed and low power mode. 0b1..DAC is selected to work in high speed high power mode.

◆ CMP_C1_DMODE [2/2]

#define CMP_C1_DMODE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)

DMODE - DAC Mode Selection 0b0..DAC is selected to work in low speed and low power mode. 0b1..DAC is selected to work in high speed high power mode.

◆ CMP_C1_MSEL [1/2]

#define CMP_C1_MSEL ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)

MSEL - Minus Input MUX Control 0b000..Internal Negative Input 0 for Minus Channel – Internal Minus Input 0b001..External Input 1 for Minus Channel – Reference Input 0 0b010..External Input 2 for Minus Channel – Reference Input 1 0b011..External Input 3 for Minus Channel – Reference Input 2 0b100..External Input 4 for Minus Channel – Reference Input 3 0b101..External Input 5 for Minus Channel – Reference Input 4 0b110..External Input 6 for Minus Channel – Reference Input 5 0b111..Internal 8b DAC output

◆ CMP_C1_MSEL [2/2]

#define CMP_C1_MSEL ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)

MSEL - Minus Input MUX Control 0b000..Internal Negative Input 0 for Minus Channel – Internal Minus Input 0b001..External Input 1 for Minus Channel – Reference Input 0 0b010..External Input 2 for Minus Channel – Reference Input 1 0b011..External Input 3 for Minus Channel – Reference Input 2 0b100..External Input 4 for Minus Channel – Reference Input 3 0b101..External Input 5 for Minus Channel – Reference Input 4 0b110..External Input 6 for Minus Channel – Reference Input 5 0b111..Internal 8b DAC output

◆ CMP_C1_PSEL [1/2]

#define CMP_C1_PSEL ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)

PSEL - Plus Input MUX Control 0b000..Internal Positive Input 0 for Plus Channel – Internal Plus Input 0b001..External Input 1 for Plus Channel – Reference Input 0 0b010..External Input 2 for Plus Channel – Reference Input 1 0b011..External Input 3 for Plus Channel – Reference Input 2 0b100..External Input 4 for Plus Channel – Reference Input 3 0b101..External Input 5 for Plus Channel – Reference Input 4 0b110..External Input 6 for Plus Channel – Reference Input 5 0b111..Internal 8b DAC output

◆ CMP_C1_PSEL [2/2]

#define CMP_C1_PSEL ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)

PSEL - Plus Input MUX Control 0b000..Internal Positive Input 0 for Plus Channel – Internal Plus Input 0b001..External Input 1 for Plus Channel – Reference Input 0 0b010..External Input 2 for Plus Channel – Reference Input 1 0b011..External Input 3 for Plus Channel – Reference Input 2 0b100..External Input 4 for Plus Channel – Reference Input 3 0b101..External Input 5 for Plus Channel – Reference Input 4 0b110..External Input 6 for Plus Channel – Reference Input 5 0b111..Internal 8b DAC output

◆ CMP_C1_VOSEL [1/2]

#define CMP_C1_VOSEL ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)

VOSEL - DAC Output Voltage Select

◆ CMP_C1_VOSEL [2/2]

#define CMP_C1_VOSEL ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)

VOSEL - DAC Output Voltage Select

◆ CMP_C1_VRSEL [1/2]

#define CMP_C1_VRSEL ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)

VRSEL - Supply Voltage Reference Source Select 0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC. 0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD.

◆ CMP_C1_VRSEL [2/2]

#define CMP_C1_VRSEL ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)

VRSEL - Supply Voltage Reference Source Select 0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC. 0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD.

◆ CMP_C2_ACOn [1/2]

#define CMP_C2_ACOn ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)

ACOn - ACOn

◆ CMP_C2_ACOn [2/2]

#define CMP_C2_ACOn ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)

ACOn - ACOn

◆ CMP_C2_CH0F [1/2]

#define CMP_C2_CH0F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)

CH0F - CH0F

◆ CMP_C2_CH0F [2/2]

#define CMP_C2_CH0F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)

CH0F - CH0F

◆ CMP_C2_CH1F [1/2]

#define CMP_C2_CH1F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)

CH1F - CH1F

◆ CMP_C2_CH1F [2/2]

#define CMP_C2_CH1F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)

CH1F - CH1F

◆ CMP_C2_CH2F [1/2]

#define CMP_C2_CH2F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)

CH2F - CH2F

◆ CMP_C2_CH2F [2/2]

#define CMP_C2_CH2F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)

CH2F - CH2F

◆ CMP_C2_CH3F [1/2]

#define CMP_C2_CH3F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)

CH3F - CH3F

◆ CMP_C2_CH3F [2/2]

#define CMP_C2_CH3F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)

CH3F - CH3F

◆ CMP_C2_CH4F [1/2]

#define CMP_C2_CH4F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)

CH4F - CH4F

◆ CMP_C2_CH4F [2/2]

#define CMP_C2_CH4F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)

CH4F - CH4F

◆ CMP_C2_CH5F [1/2]

#define CMP_C2_CH5F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)

CH5F - CH5F

◆ CMP_C2_CH5F [2/2]

#define CMP_C2_CH5F ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)

CH5F - CH5F

◆ CMP_C2_FXMP [1/2]

#define CMP_C2_FXMP ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)

FXMP - Fixed MUX Port 0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round. 0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round.

◆ CMP_C2_FXMP [2/2]

#define CMP_C2_FXMP ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)

FXMP - Fixed MUX Port 0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round. 0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round.

◆ CMP_C2_FXMXCH [1/2]

#define CMP_C2_FXMXCH ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)

FXMXCH - Fixed channel selection 0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port. 0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port. 0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port. 0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port. 0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port. 0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port. 0b110..Reserved. 0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port.

◆ CMP_C2_FXMXCH [2/2]

#define CMP_C2_FXMXCH ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)

FXMXCH - Fixed channel selection 0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port. 0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port. 0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port. 0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port. 0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port. 0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port. 0b110..Reserved. 0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port.

◆ CMP_C2_INITMOD [1/2]

#define CMP_C2_INITMOD ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)

INITMOD - Comparator and DAC initialization delay modulus.

◆ CMP_C2_INITMOD [2/2]

#define CMP_C2_INITMOD ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)

INITMOD - Comparator and DAC initialization delay modulus.

◆ CMP_C2_NSAM [1/2]

#define CMP_C2_NSAM ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)

NSAM - Number of sample clocks 0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. 0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock. 0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock. 0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.

◆ CMP_C2_NSAM [2/2]

#define CMP_C2_NSAM ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)

NSAM - Number of sample clocks 0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. 0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock. 0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock. 0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.

◆ CMP_C2_RRIE [1/2]

#define CMP_C2_RRIE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)

RRIE - Round-Robin interrupt enable 0b0..The round-robin interrupt is disabled. 0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample.

◆ CMP_C2_RRIE [2/2]

#define CMP_C2_RRIE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)

RRIE - Round-Robin interrupt enable 0b0..The round-robin interrupt is disabled. 0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample.

◆ CMP_C3_ACPH1TC [1/2]

#define CMP_C3_ACPH1TC ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)

ACPH1TC - Analog Comparator Phase1 Timing Control. 0b000..Phase1 active time in one sampling period equals to T 0b001..Phase1 active time in one sampling period equals to 2*T 0b010..Phase1 active time in one sampling period equals to 4*T 0b011..Phase1 active time in one sampling period equals to 8*T 0b100..Phase1 active time in one sampling period equals to T 0b101..Phase1 active time in one sampling period equals to T 0b110..Phase1 active time in one sampling period equals to T 0b111..Phase1 active time in one sampling period equals to 0

◆ CMP_C3_ACPH1TC [2/2]

#define CMP_C3_ACPH1TC ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)

ACPH1TC - Analog Comparator Phase1 Timing Control. 0b000..Phase1 active time in one sampling period equals to T 0b001..Phase1 active time in one sampling period equals to 2*T 0b010..Phase1 active time in one sampling period equals to 4*T 0b011..Phase1 active time in one sampling period equals to 8*T 0b100..Phase1 active time in one sampling period equals to T 0b101..Phase1 active time in one sampling period equals to T 0b110..Phase1 active time in one sampling period equals to T 0b111..Phase1 active time in one sampling period equals to 0

◆ CMP_C3_ACPH2TC [1/2]

#define CMP_C3_ACPH2TC ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)

ACPH2TC - Analog Comparator Phase2 Timing Control. 0b000..Phase2 active time in one sampling period equals to T 0b001..Phase2 active time in one sampling period equals to 2*T 0b010..Phase2 active time in one sampling period equals to 4*T 0b011..Phase2 active time in one sampling period equals to 8*T 0b100..Phase2 active time in one sampling period equals to 16*T 0b101..Phase2 active time in one sampling period equals to 32*T 0b110..Phase2 active time in one sampling period equals to 64*T 0b111..Phase2 active time in one sampling period equals to 16*T

◆ CMP_C3_ACPH2TC [2/2]

#define CMP_C3_ACPH2TC ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)

ACPH2TC - Analog Comparator Phase2 Timing Control. 0b000..Phase2 active time in one sampling period equals to T 0b001..Phase2 active time in one sampling period equals to 2*T 0b010..Phase2 active time in one sampling period equals to 4*T 0b011..Phase2 active time in one sampling period equals to 8*T 0b100..Phase2 active time in one sampling period equals to 16*T 0b101..Phase2 active time in one sampling period equals to 32*T 0b110..Phase2 active time in one sampling period equals to 64*T 0b111..Phase2 active time in one sampling period equals to 16*T

◆ CMP_C3_ACSAT [1/2]

#define CMP_C3_ACSAT ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)

ACSAT - Analog Comparator Sampling Time control. 0b000..The sampling time equals to T 0b001..The sampling time equasl to 2*T 0b010..The sampling time equasl to 4*T 0b011..The sampling time equasl to 8*T 0b100..The sampling time equasl to 16*T 0b101..The sampling time equasl to 32*T 0b110..The sampling time equasl to 64*T 0b111..The sampling time equasl to 256*T

◆ CMP_C3_ACSAT [2/2]

#define CMP_C3_ACSAT ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)

ACSAT - Analog Comparator Sampling Time control. 0b000..The sampling time equals to T 0b001..The sampling time equasl to 2*T 0b010..The sampling time equasl to 4*T 0b011..The sampling time equasl to 8*T 0b100..The sampling time equasl to 16*T 0b101..The sampling time equasl to 32*T 0b110..The sampling time equasl to 64*T 0b111..The sampling time equasl to 256*T

◆ CMP_C3_DMCS [1/2]

#define CMP_C3_DMCS ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)

DMCS - Discrete Mode Clock Selection 0b0..Slow clock is selected for the timing generation. 0b1..Fast clock is selected for the timing generation.

◆ CMP_C3_DMCS [2/2]

#define CMP_C3_DMCS ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)

DMCS - Discrete Mode Clock Selection 0b0..Slow clock is selected for the timing generation. 0b1..Fast clock is selected for the timing generation.

◆ CMP_C3_NCHCTEN [1/2]

#define CMP_C3_NCHCTEN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)

NCHCTEN - Negative Channel Continuous Mode Enable. 0b0..Negative channel is in Discrete Mode and special timing needs to be configured. 0b1..Negative channel is in Continuous Mode and no special timing is requried.

◆ CMP_C3_NCHCTEN [2/2]

#define CMP_C3_NCHCTEN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)

NCHCTEN - Negative Channel Continuous Mode Enable. 0b0..Negative channel is in Discrete Mode and special timing needs to be configured. 0b1..Negative channel is in Continuous Mode and no special timing is requried.

◆ CMP_C3_PCHCTEN [1/2]

#define CMP_C3_PCHCTEN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)

PCHCTEN - Positive Channel Continuous Mode Enable. 0b0..Positive channel is in Discrete Mode and special timing needs to be configured. 0b1..Positive channel is in Continuous Mode and no special timing is requried.

◆ CMP_C3_PCHCTEN [2/2]

#define CMP_C3_PCHCTEN ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)

PCHCTEN - Positive Channel Continuous Mode Enable. 0b0..Positive channel is in Discrete Mode and special timing needs to be configured. 0b1..Positive channel is in Continuous Mode and no special timing is requried.

◆ CMP_C3_RDIVE [1/2]

#define CMP_C3_RDIVE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)

RDIVE - Resistor Divider Enable 0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v. 0b1..The resistor is enabled because the inputs are above 1.8v.

◆ CMP_C3_RDIVE [2/2]

#define CMP_C3_RDIVE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)

RDIVE - Resistor Divider Enable 0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v. 0b1..The resistor is enabled because the inputs are above 1.8v.

◆ CMP_CR0_FILTER_CNT

#define CMP_CR0_FILTER_CNT ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)

FILTER_CNT - Filter Sample Count 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. 0b001..One sample must agree. The comparator output is simply sampled. 0b010..2 consecutive samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5 consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.

◆ CMP_CR0_HYSTCTR

#define CMP_CR0_HYSTCTR ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)

HYSTCTR - Comparator hard block hysteresis control 0b00..Level 0 0b01..Level 1 0b10..Level 2 0b11..Level 3

◆ CMP_CR1_COS

#define CMP_CR1_COS ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)

COS - Comparator Output Select 0b0..Set the filtered comparator output (CMPO) to equal COUT. 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.

◆ CMP_CR1_EN

#define CMP_CR1_EN ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)

EN - Comparator Module Enable 0b0..Analog Comparator is disabled. 0b1..Analog Comparator is enabled.

◆ CMP_CR1_INV

#define CMP_CR1_INV ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)

INV - Comparator INVERT 0b0..Does not invert the comparator output. 0b1..Inverts the comparator output.

◆ CMP_CR1_OPE

#define CMP_CR1_OPE ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)

OPE - Comparator Output Pin Enable 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.

◆ CMP_CR1_PMODE

#define CMP_CR1_PMODE ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)

PMODE - Power Mode Select 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.

◆ CMP_CR1_SE

#define CMP_CR1_SE ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)

SE - Sample Enable 0b0..Sampling mode is not selected. 0b1..Sampling mode is selected.

◆ CMP_CR1_WE

#define CMP_CR1_WE ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)

WE - Windowing Enable 0b0..Windowing mode is not selected. 0b1..Windowing mode is selected.

◆ CMP_DACCR_DACEN

#define CMP_DACCR_DACEN ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)

DACEN - DAC Enable 0b0..DAC is disabled. 0b1..DAC is enabled.

◆ CMP_DACCR_VOSEL

#define CMP_DACCR_VOSEL ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)

VOSEL - DAC Output Voltage Select

◆ CMP_DACCR_VRSEL

#define CMP_DACCR_VRSEL ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)

VRSEL - Supply Voltage Reference Source Select 0b0..Vin1 is selected as resistor ladder network supply reference. 0b1..Vin2 is selected as resistor ladder network supply reference.

◆ CMP_FPR_FILT_PER

#define CMP_FPR_FILT_PER ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)

FILT_PER - Filter Sample Period

◆ CMP_MUXCR_MSEL

#define CMP_MUXCR_MSEL ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)

MSEL - Minus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

◆ CMP_MUXCR_PSEL

#define CMP_MUXCR_PSEL ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)

PSEL - Plus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

◆ CMP_PARAM_PARAM [1/2]

#define CMP_PARAM_PARAM ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)

PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register.

◆ CMP_PARAM_PARAM [2/2]

#define CMP_PARAM_PARAM ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)

PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register.

◆ CMP_SCR_CFF

#define CMP_SCR_CFF ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)

CFF - Analog Comparator Flag Falling 0b0..Falling-edge on COUT has not been detected. 0b1..Falling-edge on COUT has occurred.

◆ CMP_SCR_CFR

#define CMP_SCR_CFR ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)

CFR - Analog Comparator Flag Rising 0b0..Rising-edge on COUT has not been detected. 0b1..Rising-edge on COUT has occurred.

◆ CMP_SCR_COUT

#define CMP_SCR_COUT ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)

COUT - Analog Comparator Output

◆ CMP_SCR_DMAEN

#define CMP_SCR_DMAEN ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)

DMAEN - DMA Enable Control 0b0..DMA is disabled. 0b1..DMA is enabled.

◆ CMP_SCR_IEF

#define CMP_SCR_IEF ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)

IEF - Comparator Interrupt Enable Falling 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CMP_SCR_IER

#define CMP_SCR_IER ( x ) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)

IER - Comparator Interrupt Enable Rising 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CMP_VERID_FEATURE [1/2]

#define CMP_VERID_FEATURE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number. This read only filed returns the feature set number.

◆ CMP_VERID_FEATURE [2/2]

#define CMP_VERID_FEATURE ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number. This read only filed returns the feature set number.

◆ CMP_VERID_MAJOR [1/2]

#define CMP_VERID_MAJOR ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)

MAJOR - Major Version Number. This read only field returns the major version number for the module specification.

◆ CMP_VERID_MAJOR [2/2]

#define CMP_VERID_MAJOR ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)

MAJOR - Major Version Number. This read only field returns the major version number for the module specification.

◆ CMP_VERID_MINOR [1/2]

#define CMP_VERID_MINOR ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)

MINOR - Minor Version Number. This read only field returns the minor version number for the module specification.

◆ CMP_VERID_MINOR [2/2]

#define CMP_VERID_MINOR ( x ) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)

MINOR - Minor Version Number. This read only field returns the minor version number for the module specification.

CR0 - CMP Control Register 0

CR1 - CMP Control Register 1

FPR - CMP Filter Period Register

SCR - CMP Status and Control Register

DACCR - DAC Control Register

MUXCR - MUX Control Register

VERID - Version ID Register

PARAM - Parameter Register

C0 - CMP Control Register 0

C1 - CMP Control Register 1

C2 - CMP Control Register 2

C3 - CMP Control Register 3

VERID - Version ID Register

PARAM - Parameter Register

C0 - CMP Control Register 0

C1 - CMP Control Register 1

C2 - CMP Control Register 2

C3 - CMP Control Register 3

Detailed Description

Macro Definition Documentation

◆ CMP_C0_CFF [1/2]

◆ CMP_C0_CFF [2/2]

◆ CMP_C0_CFR [1/2]

◆ CMP_C0_CFR [2/2]

◆ CMP_C0_COS [1/2]

◆ CMP_C0_COS [2/2]

◆ CMP_C0_COUT [1/2]

◆ CMP_C0_COUT [2/2]

◆ CMP_C0_DMAEN [1/2]

◆ CMP_C0_DMAEN [2/2]

◆ CMP_C0_EN [1/2]

◆ CMP_C0_EN [2/2]

◆ CMP_C0_FILTER_CNT [1/2]

◆ CMP_C0_FILTER_CNT [2/2]

◆ CMP_C0_FPR [1/2]

◆ CMP_C0_FPR [2/2]

◆ CMP_C0_HYSTCTR [1/2]

◆ CMP_C0_HYSTCTR [2/2]

◆ CMP_C0_IEF [1/2]

◆ CMP_C0_IEF [2/2]

◆ CMP_C0_IER [1/2]

◆ CMP_C0_IER [2/2]

◆ CMP_C0_INVT [1/2]

◆ CMP_C0_INVT [2/2]

◆ CMP_C0_LINKEN [1/2]

◆ CMP_C0_LINKEN [2/2]

◆ CMP_C0_OPE [1/2]

◆ CMP_C0_OPE [2/2]

◆ CMP_C0_PMODE [1/2]

◆ CMP_C0_PMODE [2/2]

◆ CMP_C0_SE [1/2]

◆ CMP_C0_SE [2/2]

◆ CMP_C0_WE [1/2]

◆ CMP_C0_WE [2/2]

◆ CMP_C1_CHN0 [1/2]

◆ CMP_C1_CHN0 [2/2]

◆ CMP_C1_CHN1 [1/2]

◆ CMP_C1_CHN1 [2/2]

◆ CMP_C1_CHN2 [1/2]

◆ CMP_C1_CHN2 [2/2]

◆ CMP_C1_CHN3 [1/2]

◆ CMP_C1_CHN3 [2/2]

◆ CMP_C1_CHN4 [1/2]

◆ CMP_C1_CHN4 [2/2]

◆ CMP_C1_CHN5 [1/2]

◆ CMP_C1_CHN5 [2/2]

◆ CMP_C1_DACEN [1/2]

◆ CMP_C1_DACEN [2/2]

◆ CMP_C1_DMODE [1/2]

◆ CMP_C1_DMODE [2/2]

◆ CMP_C1_MSEL [1/2]

◆ CMP_C1_MSEL [2/2]

◆ CMP_C1_PSEL [1/2]

◆ CMP_C1_PSEL [2/2]

◆ CMP_C1_VOSEL [1/2]

◆ CMP_C1_VOSEL [2/2]

◆ CMP_C1_VRSEL [1/2]

◆ CMP_C1_VRSEL [2/2]

◆ CMP_C2_ACOn [1/2]

◆ CMP_C2_ACOn [2/2]