PLL_ARM - Analog ARM PLL control Register
#define	CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)

#define	CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)

#define	CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)

#define	CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)

#define	CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)

#define	CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)

PLL_ARM_SET - Analog ARM PLL control Register
#define	CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)

#define	CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)

#define	CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)

#define	CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)

#define	CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)

#define	CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)

PLL_ARM_CLR - Analog ARM PLL control Register
#define	CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)

#define	CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)

#define	CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)

#define	CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)

#define	CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)

#define	CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)

PLL_ARM_TOG - Analog ARM PLL control Register
#define	CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)

#define	CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)

#define	CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)

#define	CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)

#define	CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)

#define	CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)

PLL_USB1 - Analog USB1 480MHz PLL Control Register
#define	CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)

#define	CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)

#define	CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)

#define	CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)

#define	CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)

#define	CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)

#define	CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)

#define	CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)

#define	CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)

#define	CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)

#define	CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)

PLL_USB1_SET - Analog USB1 480MHz PLL Control Register
#define	CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)

#define	CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)

#define	CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)

#define	CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)

#define	CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)

#define	CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)

#define	CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)

#define	CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)

#define	CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)

#define	CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)

#define	CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)

PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register
#define	CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)

#define	CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)

#define	CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)

#define	CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)

#define	CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)

#define	CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)

#define	CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)

#define	CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)

#define	CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)

#define	CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)

#define	CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)

PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register
#define	CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)

#define	CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)

#define	CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)

#define	CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)

#define	CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)

#define	CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)

#define	CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)

#define	CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)

#define	CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)

#define	CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)

#define	CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)

PLL_USB2 - Analog USB2 480MHz PLL Control Register
#define	CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U)

#define	CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U)

#define	CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)

#define	CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)

#define	CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)

#define	CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)

#define	CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)

#define	CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)

#define	CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)

#define	CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)

#define	CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)

PLL_USB2_SET - Analog USB2 480MHz PLL Control Register
#define	CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U)

#define	CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U)

#define	CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)

#define	CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)

#define	CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)

#define	CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)

#define	CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)

#define	CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)

#define	CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)

#define	CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)

#define	CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)

PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register
#define	CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U)

#define	CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U)

#define	CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)

#define	CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)

#define	CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)

#define	CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)

#define	CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)

#define	CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)

#define	CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)

#define	CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)

#define	CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)

PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register
#define	CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U)

#define	CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U)

#define	CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)

#define	CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)

#define	CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)

#define	CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)

#define	CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)

#define	CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)

#define	CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)

#define	CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)

#define	CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)

PLL_SYS - Analog System PLL Control Register
#define	CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)

#define	CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)

#define	CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)

#define	CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)

PLL_SYS_SET - Analog System PLL Control Register
#define	CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)

#define	CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)

#define	CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)

#define	CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)

PLL_SYS_CLR - Analog System PLL Control Register
#define	CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)

#define	CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)

#define	CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)

#define	CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)

PLL_SYS_TOG - Analog System PLL Control Register
#define	CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)

#define	CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)

#define	CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)

#define	CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)

PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register
#define	CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)

#define	CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)

#define	CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)

#define	CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)

#define	CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)

#define	CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)

#define	CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)

#define	CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)

#define	CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)

PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register
#define	CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)

#define	CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)

#define	CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)

PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register
#define	CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)

#define	CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)

#define	CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)

PLL_AUDIO - Analog Audio PLL control Register
#define	CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)

#define	CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)

#define	CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)

#define	CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)

#define	CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)

PLL_AUDIO_SET - Analog Audio PLL control Register
#define	CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)

#define	CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)

#define	CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)

#define	CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)

#define	CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)

PLL_AUDIO_CLR - Analog Audio PLL control Register
#define	CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)

#define	CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)

#define	CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)

PLL_AUDIO_TOG - Analog Audio PLL control Register
#define	CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)

#define	CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)

#define	CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)

PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register
#define	CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)

#define	CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)

#define	CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)

PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register
#define	CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)

#define	CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)

#define	CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)

PLL_VIDEO - Analog Video PLL control Register
#define	CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)

#define	CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)

#define	CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)

#define	CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)

#define	CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)

PLL_VIDEO_SET - Analog Video PLL control Register
#define	CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)

#define	CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)

#define	CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)

#define	CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)

#define	CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)

PLL_VIDEO_CLR - Analog Video PLL control Register
#define	CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)

#define	CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)

#define	CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)

PLL_VIDEO_TOG - Analog Video PLL control Register
#define	CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)

#define	CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)

#define	CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)

#define	CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)

PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register
#define	CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)

#define	CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)

#define	CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)

PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register
#define	CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)

#define	CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)

#define	CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)

PLL_ENET - Analog ENET PLL Control Register
#define	CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)

#define	CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)

#define	CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)

#define	CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)

#define	CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)

#define	CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)

#define	CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)

PLL_ENET_SET - Analog ENET PLL Control Register
#define	CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)

#define	CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)

#define	CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)

#define	CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)

#define	CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)

#define	CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)

#define	CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)

PLL_ENET_CLR - Analog ENET PLL Control Register
#define	CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)

#define	CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)

#define	CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)

#define	CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)

#define	CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)

#define	CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)

#define	CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)

PLL_ENET_TOG - Analog ENET PLL Control Register
#define	CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)

#define	CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)

#define	CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)

#define	CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)

#define	CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)

#define	CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)

#define	CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)

#define	CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)

#define	CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)

#define	CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)

#define	CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)

#define	CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)

#define	CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)

#define	CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)

#define	CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)

#define	CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)

#define	CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)

#define	CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)

#define	CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)

#define	CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)

#define	CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)

PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register
#define	CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)

#define	CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)

#define	CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)

#define	CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)

#define	CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)

#define	CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)

#define	CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)

#define	CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)

#define	CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)

#define	CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)

#define	CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)

#define	CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)

#define	CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)

#define	CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)

#define	CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)

#define	CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)

#define	CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)

#define	CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)

#define	CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)

#define	CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)

#define	CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)

#define	CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)

#define	CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)

#define	CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)

#define	CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)

PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register
#define	CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)

#define	CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)

#define	CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)

#define	CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)

#define	CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)

#define	CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)

#define	CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)

#define	CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)

#define	CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)

#define	CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)

#define	CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)

#define	CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)

#define	CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)

#define	CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)

#define	CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)

#define	CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)

#define	CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)

#define	CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)

#define	CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)

#define	CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)

#define	CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)

#define	CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)

#define	CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)

#define	CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)

#define	CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)

PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register
#define	CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)

#define	CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)

#define	CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)

#define	CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)

#define	CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)

#define	CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)

#define	CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)

#define	CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)

#define	CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)

#define	CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)

#define	CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)

#define	CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)

#define	CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)

#define	CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)

#define	CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)

#define	CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)

#define	CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)

#define	CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)

#define	CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)

#define	CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)

#define	CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)

#define	CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)

#define	CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)

#define	CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)

#define	CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)

PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register
#define	CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)

#define	CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)

#define	CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)

#define	CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)

#define	CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)

#define	CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)

#define	CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)

#define	CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)

#define	CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)

#define	CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)

#define	CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)

#define	CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)

#define	CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)

#define	CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)

#define	CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)

#define	CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)

#define	CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)

#define	CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)

#define	CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)

#define	CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)

#define	CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)

#define	CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)

#define	CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)

#define	CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)

#define	CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)

#define	CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)

#define	CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)

PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register
#define	CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)

#define	CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)

#define	CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)

#define	CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)

#define	CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)

#define	CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)

#define	CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)

#define	CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)

#define	CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)

#define	CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)

#define	CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)

#define	CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)

#define	CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)

#define	CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)

#define	CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)

#define	CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)

#define	CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)

#define	CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)

#define	CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)

#define	CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)

#define	CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)

#define	CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)

#define	CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)

#define	CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)

#define	CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)

PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register
#define	CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)

#define	CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)

#define	CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)

#define	CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)

#define	CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)

#define	CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)

#define	CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)

#define	CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)

#define	CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)

#define	CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)

#define	CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)

#define	CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)

#define	CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)

#define	CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)

#define	CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)

#define	CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)

#define	CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)

#define	CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)

#define	CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)

#define	CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)

#define	CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)

#define	CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)

#define	CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)

#define	CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)

#define	CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)

PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register
#define	CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)

#define	CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)

#define	CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)

#define	CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)

#define	CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)

#define	CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)

#define	CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)

#define	CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)

#define	CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)

#define	CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)

#define	CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)

#define	CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)

#define	CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)

#define	CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)

#define	CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)

#define	CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)

#define	CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)

#define	CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)

#define	CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)

#define	CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)

#define	CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)

#define	CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)

#define	CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)

#define	CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)

#define	CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)

PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register
#define	CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)

#define	CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)

#define	CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)

#define	CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)

#define	CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)

#define	CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)

#define	CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)

#define	CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)

#define	CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)

#define	CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)

#define	CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)

#define	CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)

#define	CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)

#define	CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)

#define	CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)

#define	CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)

#define	CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)

#define	CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)

#define	CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)

#define	CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)

#define	CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)

#define	CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)

#define	CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)

#define	CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)

#define	CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)

#define	CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)

#define	CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)

#define	CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)

MISC0 - Miscellaneous Register 0
#define	CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)

#define	CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)

#define	CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)

#define	CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)

#define	CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)

#define	CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)

#define	CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)

#define	CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)

#define	CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)

#define	CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)

#define	CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)

#define	CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)

#define	CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)

#define	CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)

#define	CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)

#define	CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)

#define	CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)

#define	CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)

#define	CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)

#define	CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)

#define	CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)

#define	CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)

#define	CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)

#define	CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)

#define	CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)

#define	CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)

#define	CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)

#define	CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)

#define	CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)

#define	CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)

#define	CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)

#define	CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)

#define	CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)

#define	CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)

#define	CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_REFTOP_PWD_MASK (0x1U)

#define	PMU_MISC0_REFTOP_PWD_SHIFT (0U)

#define	PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)

#define	PMU_MISC0_REFTOP_PWDVBGUP_MASK (0x2U)

#define	PMU_MISC0_REFTOP_PWDVBGUP_SHIFT (1U)

#define	PMU_MISC0_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_REFTOP_PWDVBGUP_MASK)

#define	PMU_MISC0_REFTOP_LOWPOWER_MASK (0x4U)

#define	PMU_MISC0_REFTOP_LOWPOWER_SHIFT (2U)

#define	PMU_MISC0_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_REFTOP_LOWPOWER_MASK)

#define	PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)

#define	PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)

#define	PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)

#define	PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)

#define	PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)

#define	PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)

#define	PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)

#define	PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)

#define	PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)

#define	PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)

#define	PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)

#define	PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)

#define	PMU_MISC0_OSC_I_MASK (0x6000U)

#define	PMU_MISC0_OSC_I_SHIFT (13U)

#define	PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)

#define	PMU_MISC0_OSC_XTALOK_MASK (0x8000U)

#define	PMU_MISC0_OSC_XTALOK_SHIFT (15U)

#define	PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)

#define	PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)

#define	PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)

#define	PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)

#define	PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)

#define	PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)

#define	PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)

#define	PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)

#define	PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)

#define	PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)

#define	PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)

#define	PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)

#define	PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)

#define	PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)

#define	PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)

#define	PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)

#define	PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)

#define	XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)

#define	XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)

#define	XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)

#define	XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)

#define	XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)

#define	XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)

#define	XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)

#define	XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)

#define	XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)

#define	XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)

#define	XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)

#define	XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)

#define	XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)

#define	XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)

#define	XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)

#define	XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)

#define	XTALOSC24M_MISC0_OSC_I_SHIFT (13U)

#define	XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)

#define	XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)

#define	XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)

#define	XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)

#define	XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)

#define	XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)

#define	XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)

#define	XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)

#define	XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)

#define	XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)

#define	XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)

#define	XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)

#define	XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)

#define	XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)

#define	XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)

#define	XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)

#define	XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)

#define	XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)

#define	XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)

#define	XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)

#define	XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)

MISC0_SET - Miscellaneous Register 0
#define	CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)

#define	CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)

#define	CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)

#define	CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)

#define	CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)

#define	CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)

#define	CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)

#define	CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)

#define	CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)

#define	CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)

#define	CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)

#define	CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)

#define	CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)

#define	CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)

#define	CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)

#define	CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)

#define	CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)

#define	CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)

#define	CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)

#define	CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)

#define	CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)

#define	CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)

#define	CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)

#define	CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)

#define	CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)

#define	CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)

#define	CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)

#define	CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)

#define	CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)

#define	CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)

#define	CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)

#define	CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)

#define	CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)

#define	CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)

#define	CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)

#define	PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)

#define	PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)

#define	PMU_MISC0_SET_REFTOP_PWDVBGUP_MASK (0x2U)

#define	PMU_MISC0_SET_REFTOP_PWDVBGUP_SHIFT (1U)

#define	PMU_MISC0_SET_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_PWDVBGUP_MASK)

#define	PMU_MISC0_SET_REFTOP_LOWPOWER_MASK (0x4U)

#define	PMU_MISC0_SET_REFTOP_LOWPOWER_SHIFT (2U)

#define	PMU_MISC0_SET_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_SET_REFTOP_LOWPOWER_MASK)

#define	PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)

#define	PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)

#define	PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)

#define	PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)

#define	PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)

#define	PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)

#define	PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)

#define	PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)

#define	PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)

#define	PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)

#define	PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)

#define	PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)

#define	PMU_MISC0_SET_OSC_I_MASK (0x6000U)

#define	PMU_MISC0_SET_OSC_I_SHIFT (13U)

#define	PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)

#define	PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)

#define	PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)

#define	PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)

#define	PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)

#define	PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)

#define	PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)

#define	PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)

#define	PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)

#define	PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)

#define	PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)

#define	PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)

#define	PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)

#define	PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)

#define	PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)

#define	PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)

#define	PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)

#define	PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)

#define	PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)

#define	PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)

#define	XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)

#define	XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)

#define	XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)

#define	XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)

#define	XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)

#define	XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)

#define	XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)

#define	XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)

#define	XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)

#define	XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)

#define	XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)

#define	XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)

#define	XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)

#define	XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)

#define	XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)

#define	XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)

#define	XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)

#define	XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)

#define	XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)

#define	XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)

#define	XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)

#define	XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)

#define	XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)

#define	XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)

#define	XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)

#define	XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)

#define	XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)

#define	XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)

#define	XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)

#define	XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)

#define	XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)

#define	XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)

#define	XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)

#define	XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)

#define	XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)

#define	XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)

#define	XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)

#define	XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)

MISC0_CLR - Miscellaneous Register 0
#define	CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)

#define	CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)

#define	CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)

#define	CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)

#define	CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)

#define	CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)

#define	CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)

#define	CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)

#define	CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)

#define	CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)

#define	CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)

#define	CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)

#define	CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)

#define	CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)

#define	CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)

#define	CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)

#define	CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)

#define	CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)

#define	CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)

#define	CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)

#define	CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)

#define	CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)

#define	CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)

#define	CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)

#define	CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)

#define	CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)

#define	CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)

#define	CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)

#define	CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)

#define	CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)

#define	CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)

#define	CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)

#define	CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)

#define	CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)

#define	CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)

#define	PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)

#define	PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)

#define	PMU_MISC0_CLR_REFTOP_PWDVBGUP_MASK (0x2U)

#define	PMU_MISC0_CLR_REFTOP_PWDVBGUP_SHIFT (1U)

#define	PMU_MISC0_CLR_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWDVBGUP_MASK)

#define	PMU_MISC0_CLR_REFTOP_LOWPOWER_MASK (0x4U)

#define	PMU_MISC0_CLR_REFTOP_LOWPOWER_SHIFT (2U)

#define	PMU_MISC0_CLR_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_CLR_REFTOP_LOWPOWER_MASK)

#define	PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)

#define	PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)

#define	PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)

#define	PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)

#define	PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)

#define	PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)

#define	PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)

#define	PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)

#define	PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)

#define	PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)

#define	PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)

#define	PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)

#define	PMU_MISC0_CLR_OSC_I_MASK (0x6000U)

#define	PMU_MISC0_CLR_OSC_I_SHIFT (13U)

#define	PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)

#define	PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)

#define	PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)

#define	PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)

#define	PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)

#define	PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)

#define	PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)

#define	PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)

#define	PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)

#define	PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)

#define	PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)

#define	PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)

#define	PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)

#define	PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)

#define	PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)

#define	PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)

#define	PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)

#define	PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)

#define	PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)

#define	PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)

#define	XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)

#define	XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)

#define	XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)

#define	XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)

#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)

#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)

#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)

#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)

#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)

#define	XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)

#define	XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)

#define	XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)

#define	XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)

#define	XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)

#define	XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)

#define	XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)

#define	XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)

#define	XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)

#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)

#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)

#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)

#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)

#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)

#define	XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)

#define	XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)

#define	XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)

#define	XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)

#define	XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)

#define	XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)

#define	XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)

#define	XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)

#define	XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)

#define	XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)

#define	XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)

#define	XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)

#define	XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)

#define	XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)

#define	XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)

MISC0_TOG - Miscellaneous Register 0
#define	CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)

#define	CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)

#define	CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)

#define	CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)

#define	CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)

#define	CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)

#define	CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)

#define	CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)

#define	CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)

#define	CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)

#define	CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)

#define	CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)

#define	CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)

#define	CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)

#define	CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)

#define	CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)

#define	CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)

#define	CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)

#define	CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)

#define	CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)

#define	CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)

#define	CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)

#define	CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)

#define	CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)

#define	CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)

#define	CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)

#define	CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)

#define	CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)

#define	CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)

#define	CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)

#define	CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)

#define	CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)

#define	CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)

#define	CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)

#define	CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)

#define	PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)

#define	PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)

#define	PMU_MISC0_TOG_REFTOP_PWDVBGUP_MASK (0x2U)

#define	PMU_MISC0_TOG_REFTOP_PWDVBGUP_SHIFT (1U)

#define	PMU_MISC0_TOG_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWDVBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWDVBGUP_MASK)

#define	PMU_MISC0_TOG_REFTOP_LOWPOWER_MASK (0x4U)

#define	PMU_MISC0_TOG_REFTOP_LOWPOWER_SHIFT (2U)

#define	PMU_MISC0_TOG_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_LOWPOWER_SHIFT)) & PMU_MISC0_TOG_REFTOP_LOWPOWER_MASK)

#define	PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)

#define	PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)

#define	PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)

#define	PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)

#define	PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)

#define	PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)

#define	PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)

#define	PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)

#define	PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)

#define	PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)

#define	PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)

#define	PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)

#define	PMU_MISC0_TOG_OSC_I_MASK (0x6000U)

#define	PMU_MISC0_TOG_OSC_I_SHIFT (13U)

#define	PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)

#define	PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)

#define	PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)

#define	PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)

#define	PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)

#define	PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)

#define	PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)

#define	PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)

#define	PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)

#define	PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)

#define	PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)

#define	PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)

#define	PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)

#define	PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)

#define	PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)

#define	PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)

#define	PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)

#define	PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)

#define	PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)

#define	PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)

#define	PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)

#define	XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)

#define	XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)

#define	XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)

#define	XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)

#define	XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)

#define	XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)

#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)

#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)

#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)

#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)

#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)

#define	XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)

#define	XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)

#define	XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)

#define	XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)

#define	XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)

#define	XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)

#define	XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)

#define	XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)

#define	XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)

#define	XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)

#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)

#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)

#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)

#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)

#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)

#define	XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)

#define	XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)

#define	XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)

#define	XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)

#define	XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)

#define	XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)

#define	XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)

#define	XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)

#define	XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)

#define	XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)

#define	XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)

#define	XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)

#define	XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)

#define	XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)

#define	XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)

#define	XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)

MISC1 - Miscellaneous Register 1
#define	CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)

#define	CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)

#define	CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)

#define	CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)

#define	CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)

#define	CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)

#define	CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)

#define	CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)

#define	CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)

#define	CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)

#define	CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)

#define	CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)

#define	CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)

#define	CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)

#define	CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)

#define	CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)

#define	CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)

#define	CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)

#define	CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)

#define	CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)

#define	CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)

#define	CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)

#define	CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)

#define	CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)

#define	PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)

#define	PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)

#define	PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)

#define	PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)

#define	PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)

#define	PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)

#define	PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)

#define	PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)

#define	PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)

#define	PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)

#define	PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)

#define	PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)

#define	PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)

#define	PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)

#define	PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)

#define	PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)

#define	PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)

#define	PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)

#define	PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)

#define	PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)

#define	PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)

#define	PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)

#define	PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)

#define	PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)

#define	PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)

#define	PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)

#define	PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)

#define	PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)

#define	PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)

#define	PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)

#define	PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)

#define	PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)

#define	PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)

MISC1_SET - Miscellaneous Register 1
#define	CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)

#define	CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)

#define	CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)

#define	CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)

#define	CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)

#define	CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)

#define	CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)

#define	CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)

#define	CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)

#define	CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)

#define	CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)

#define	CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)

#define	CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)

#define	CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)

#define	CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)

#define	CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)

#define	CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)

#define	CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)

#define	CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)

#define	CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)

#define	CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)

#define	CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)

#define	CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)

#define	CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)

#define	PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)

#define	PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)

#define	PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)

#define	PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)

#define	PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)

#define	PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)

#define	PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)

#define	PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)

#define	PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)

#define	PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)

#define	PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)

#define	PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)

#define	PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)

#define	PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)

#define	PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)

#define	PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)

#define	PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)

#define	PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)

#define	PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)

#define	PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)

#define	PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)

#define	PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)

#define	PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)

#define	PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)

#define	PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)

#define	PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)

#define	PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)

#define	PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)

#define	PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)

#define	PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)

#define	PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)

#define	PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)

#define	PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)

MISC1_CLR - Miscellaneous Register 1
#define	CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)

#define	CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)

#define	CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)

#define	CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)

#define	CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)

#define	CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)

#define	CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)

#define	CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)

#define	CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)

#define	CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)

#define	CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)

#define	CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)

#define	CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)

#define	CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)

#define	CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)

#define	CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)

#define	CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)

#define	CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)

#define	CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)

#define	CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)

#define	CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)

#define	CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)

#define	CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)

#define	CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)

#define	PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)

#define	PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)

#define	PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)

#define	PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)

#define	PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)

#define	PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)

#define	PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)

#define	PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)

#define	PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)

#define	PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)

#define	PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)

#define	PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)

#define	PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)

#define	PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)

#define	PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)

#define	PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)

#define	PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)

#define	PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)

#define	PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)

#define	PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)

#define	PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)

#define	PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)

#define	PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)

#define	PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)

#define	PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)

#define	PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)

#define	PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)

#define	PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)

#define	PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)

#define	PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)

#define	PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)

#define	PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)

#define	PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)

MISC1_TOG - Miscellaneous Register 1
#define	CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)

#define	CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)

#define	CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)

#define	CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)

#define	CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)

#define	CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)

#define	CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)

#define	CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)

#define	CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)

#define	CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)

#define	CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)

#define	CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)

#define	CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)

#define	CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)

#define	CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)

#define	CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)

#define	CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)

#define	CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)

#define	CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)

#define	CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)

#define	CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)

#define	CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)

#define	CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)

#define	CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)

#define	PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)

#define	PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)

#define	PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)

#define	PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)

#define	PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)

#define	PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)

#define	PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)

#define	PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)

#define	PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)

#define	PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)

#define	PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)

#define	PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)

#define	PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)

#define	PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)

#define	PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)

#define	PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)

#define	PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)

#define	PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)

#define	PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)

#define	PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)

#define	PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)

#define	PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)

#define	PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)

#define	PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)

#define	PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)

#define	PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)

#define	PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)

#define	PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)

#define	PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)

#define	PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)

#define	PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)

#define	PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)

#define	PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)

#define	PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)

#define	PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)

#define	PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)

#define	PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)

#define	PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)

#define	PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)

MISC2 - Miscellaneous Register 2
#define	CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)

#define	CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)

#define	CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)

#define	CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)

#define	CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)

#define	CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)

#define	CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)

#define	CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)

#define	CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)

#define	CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U)

#define	CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U)

#define	CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK)

#define	CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)

#define	CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)

#define	CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)

#define	CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)

#define	CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)

#define	CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)

#define	CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)

#define	CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)

#define	CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)

#define	CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)

#define	CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)

#define	CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)

#define	CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)

#define	CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)

#define	CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)

#define	CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)

#define	CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)

#define	CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)

#define	CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)

#define	CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)

#define	CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)

#define	CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)

#define	CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)

#define	CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)

#define	CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)

#define	CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)

#define	CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)

#define	CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)

#define	CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)

#define	CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)

#define	CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)

#define	CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)

#define	CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)

MISC2_SET - Miscellaneous Register 2
#define	CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)

#define	CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)

#define	CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)

#define	CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)

#define	CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)

#define	CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)

#define	CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)

#define	CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)

#define	CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)

#define	CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U)

#define	CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U)

#define	CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK)

#define	CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)

#define	CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)

#define	CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)

#define	CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)

#define	CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)

#define	CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)

#define	CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)

#define	CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)

#define	CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)

#define	CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)

#define	CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)

#define	CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)

#define	CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)

#define	CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)

#define	CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)

#define	CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)

#define	CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)

#define	CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)

#define	CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)

#define	CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)

#define	CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)

#define	CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)

#define	CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)

#define	CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)

#define	CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)

#define	CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)

#define	CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)

#define	CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)

#define	CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)

#define	CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)

#define	CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)

#define	CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)

#define	CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)

MISC2_CLR - Miscellaneous Register 2
#define	CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)

#define	CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)

#define	CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)

#define	CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)

#define	CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)

#define	CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)

#define	CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)

#define	CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)

#define	CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)

#define	CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U)

#define	CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U)

#define	CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)

#define	CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)

#define	CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)

#define	CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)

#define	CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)

#define	CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)

#define	CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)

#define	CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)

#define	CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)

#define	CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)

#define	CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)

#define	CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)

#define	CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)

#define	CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)

#define	CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)

#define	CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)

#define	CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)

#define	CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)

#define	CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)

#define	CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)

#define	CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)

#define	CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)

#define	CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)

#define	CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)

#define	CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)

#define	CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)

#define	CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)

#define	CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)

#define	CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)

#define	CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)

#define	CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)

MISC2_TOG - Miscellaneous Register 2
#define	CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)

#define	CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)

#define	CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)

#define	CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)

#define	CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)

#define	CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)

#define	CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)

#define	CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)

#define	CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)

#define	CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U)

#define	CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U)

#define	CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)

#define	CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)

#define	CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)

#define	CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)

#define	CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)

#define	CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)

#define	CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)

#define	CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)

#define	CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)

#define	CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)

#define	CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)

#define	CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)

#define	CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)

#define	CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)

#define	CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)

#define	CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)

#define	CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)

#define	CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)

#define	CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)

#define	CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)

#define	CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)

#define	CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)

#define	CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)

#define	CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)

#define	CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)

#define	CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)

#define	CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)

#define	CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)

#define	CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)

#define	CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)

#define	CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)

#define	CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)

Detailed Description

Macro Definition Documentation

◆ CCM_ANALOG_MISC0_CLKGATE_CTRL

#define CCM_ANALOG_MISC0_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ CCM_ANALOG_MISC0_CLKGATE_DELAY

#define CCM_ANALOG_MISC0_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL

#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY

#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS

#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ CCM_ANALOG_MISC0_CLR_OSC_I

#define CCM_ANALOG_MISC0_CLR_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF

#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ

#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE

#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG

#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except RTC powered down on stop mode assertion. 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.

◆ CCM_ANALOG_MISC0_DISCON_HIGH_SNVS

#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ CCM_ANALOG_MISC0_OSC_I

#define CCM_ANALOG_MISC0_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF

#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ CCM_ANALOG_MISC0_REFTOP_VBGADJ

#define CCM_ANALOG_MISC0_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ CCM_ANALOG_MISC0_RTC_XTAL_SOURCE

#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ CCM_ANALOG_MISC0_SET_CLKGATE_CTRL

#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ CCM_ANALOG_MISC0_SET_CLKGATE_DELAY

#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS

#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ CCM_ANALOG_MISC0_SET_OSC_I

#define CCM_ANALOG_MISC0_SET_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF

#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ

#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE

#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG

#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except RTC powered down on stop mode assertion. 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.

◆ CCM_ANALOG_MISC0_STOP_MODE_CONFIG

#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except RTC powered down on stop mode assertion. 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.

◆ CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL

#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY

#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS

#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ CCM_ANALOG_MISC0_TOG_OSC_I

#define CCM_ANALOG_MISC0_TOG_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF

#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ

#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE

#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG

#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except RTC powered down on stop mode assertion. 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.

◆ CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL

#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

◆ CCM_ANALOG_MISC1_LVDS1_CLK_SEL

#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

◆ CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL

#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

◆ CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL

#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..Arm PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

◆ CCM_ANALOG_MISC2_AUDIO_DIV_LSB

#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

◆ CCM_ANALOG_MISC2_AUDIO_DIV_MSB

#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

◆ CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB

#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

◆ CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB

#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

◆ CCM_ANALOG_MISC2_CLR_PLL3_DISABLE

#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK)

PLL3_DISABLE 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode 0b1..PLL3 can be disabled when the SoC is not in any low power mode

◆ CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET

#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS

#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

◆ CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME

#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET

#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS

#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

◆ CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME

#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET

#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME

#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_CLR_VIDEO_DIV

#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

◆ CCM_ANALOG_MISC2_PLL3_DISABLE

#define CCM_ANALOG_MISC2_PLL3_DISABLE ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK)

PLL3_DISABLE 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode 0b1..PLL3 can be disabled when the SoC is not in any low power mode

◆ CCM_ANALOG_MISC2_REG0_BO_OFFSET

#define CCM_ANALOG_MISC2_REG0_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_REG0_BO_STATUS

#define CCM_ANALOG_MISC2_REG0_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

◆ CCM_ANALOG_MISC2_REG0_STEP_TIME

#define CCM_ANALOG_MISC2_REG0_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_REG1_BO_OFFSET

#define CCM_ANALOG_MISC2_REG1_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_REG1_BO_STATUS

#define CCM_ANALOG_MISC2_REG1_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

◆ CCM_ANALOG_MISC2_REG1_STEP_TIME

#define CCM_ANALOG_MISC2_REG1_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_REG2_BO_OFFSET

#define CCM_ANALOG_MISC2_REG2_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_REG2_STEP_TIME

#define CCM_ANALOG_MISC2_REG2_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB

#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

◆ CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB

#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

◆ CCM_ANALOG_MISC2_SET_PLL3_DISABLE

#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK)

PLL3_DISABLE 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode 0b1..PLL3 can be disabled when the SoC is not in any low power mode

◆ CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET

#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_SET_REG0_BO_STATUS

#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

◆ CCM_ANALOG_MISC2_SET_REG0_STEP_TIME

#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET

#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_SET_REG1_BO_STATUS

#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

◆ CCM_ANALOG_MISC2_SET_REG1_STEP_TIME

#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET

#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_SET_REG2_STEP_TIME

#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_SET_VIDEO_DIV

#define CCM_ANALOG_MISC2_SET_VIDEO_DIV ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

◆ CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB

#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)

AUDIO_DIV_LSB 0b0..divide by 1 (Default) 0b1..divide by 2

◆ CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB

#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)

AUDIO_DIV_MSB 0b0..divide by 1 (Default) 0b1..divide by 2

◆ CCM_ANALOG_MISC2_TOG_PLL3_DISABLE

#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK)

PLL3_DISABLE 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode 0b1..PLL3 can be disabled when the SoC is not in any low power mode

◆ CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET

#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)

REG0_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS

#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)

REG0_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

◆ CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME

#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)

REG0_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET

#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)

REG1_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS

#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)

REG1_BO_STATUS 0b1..Brownout, supply is below target minus brownout offset.

◆ CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME

#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)

REG1_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET

#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)

REG2_BO_OFFSET 0b100..Brownout offset = 0.100V 0b111..Brownout offset = 0.175V

◆ CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME

#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)

REG2_STEP_TIME 0b00..64 0b01..128 0b10..256 0b11..512

◆ CCM_ANALOG_MISC2_TOG_VIDEO_DIV

#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

◆ CCM_ANALOG_MISC2_VIDEO_DIV

#define CCM_ANALOG_MISC2_VIDEO_DIV ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)

VIDEO_DIV 0b00..divide by 1 (Default) 0b01..divide by 2 0b10..divide by 1 0b11..divide by 4

◆ CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT

#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)

POST_DIV_SELECT 0b00..Divide by 4. 0b01..Divide by 2. 0b10..Divide by 1. 0b11..Reserved

◆ CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT

#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)

POST_DIV_SELECT 0b00..Divide by 4. 0b01..Divide by 2. 0b10..Divide by 1. 0b11..Reserved

◆ CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT

#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)

POST_DIV_SELECT 0b00..Divide by 4. 0b01..Divide by 2. 0b10..Divide by 1. 0b11..Reserved

◆ CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT

#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)

POST_DIV_SELECT 0b00..Divide by 4. 0b01..Divide by 2. 0b10..Divide by 1. 0b11..Reserved

◆ CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source.

◆ CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source.

◆ CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source.

◆ CCM_ANALOG_PLL_SYS_SS_ENABLE

#define CCM_ANALOG_PLL_SYS_SS_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)

ENABLE - Enable bit 0b0..Spread spectrum modulation disabled 0b1..Soread spectrum modulation enabled

◆ CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source.

◆ CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source.

◆ CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source.

◆ CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS

#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)

EN_USB_CLKS 0b0..PLL outputs for USBPHYn off. 0b1..PLL outputs for USBPHYn on.

◆ CCM_ANALOG_PLL_USB1_EN_USB_CLKS

#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)

EN_USB_CLKS 0b0..PLL outputs for USBPHYn off. 0b1..PLL outputs for USBPHYn on.

◆ CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source.

◆ CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS

#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)

EN_USB_CLKS 0b0..PLL outputs for USBPHYn off. 0b1..PLL outputs for USBPHYn on.

◆ CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source.

◆ CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS

#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)

EN_USB_CLKS 0b0..PLL outputs for USBPHYn off. 0b1..PLL outputs for USBPHYn on.

◆ CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT

#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)

POST_DIV_SELECT 0b00..Divide by 4. 0b01..Divide by 2. 0b10..Divide by 1. 0b11..Reserved

◆ CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT

#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)

POST_DIV_SELECT 0b00..Divide by 4. 0b01..Divide by 2. 0b10..Divide by 1. 0b11..Reserved

◆ CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT

#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)

POST_DIV_SELECT 0b00..Divide by 4. 0b01..Divide by 2. 0b10..Divide by 1. 0b11..Reserved

◆ CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC

#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)

BYPASS_CLK_SRC 0b00..Select the 24MHz oscillator as source. 0b01..Select the CLK1_N / CLK1_P as source. 0b10..Reserved1 0b11..Reserved2

◆ CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT

#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT ( x ) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)

POST_DIV_SELECT 0b00..Divide by 4. 0b01..Divide by 2. 0b10..Divide by 1. 0b11..Reserved

◆ PMU_MISC0_CLKGATE_CTRL

#define PMU_MISC0_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ PMU_MISC0_CLKGATE_DELAY

#define PMU_MISC0_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ PMU_MISC0_CLR_CLKGATE_CTRL

#define PMU_MISC0_CLR_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ PMU_MISC0_CLR_CLKGATE_DELAY

#define PMU_MISC0_CLR_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ PMU_MISC0_CLR_DISCON_HIGH_SNVS

#define PMU_MISC0_CLR_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ PMU_MISC0_CLR_OSC_I

#define PMU_MISC0_CLR_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ PMU_MISC0_CLR_REFTOP_SELFBIASOFF

#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ PMU_MISC0_CLR_REFTOP_VBGADJ

#define PMU_MISC0_CLR_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ PMU_MISC0_CLR_RTC_XTAL_SOURCE

#define PMU_MISC0_CLR_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ PMU_MISC0_CLR_STOP_MODE_CONFIG

#define PMU_MISC0_CLR_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

◆ PMU_MISC0_CLR_VID_PLL_PREDIV

#define PMU_MISC0_CLR_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

◆ PMU_MISC0_DISCON_HIGH_SNVS

#define PMU_MISC0_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ PMU_MISC0_OSC_I

#define PMU_MISC0_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ PMU_MISC0_REFTOP_SELFBIASOFF

#define PMU_MISC0_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ PMU_MISC0_REFTOP_VBGADJ

#define PMU_MISC0_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ PMU_MISC0_RTC_XTAL_SOURCE

#define PMU_MISC0_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ PMU_MISC0_SET_CLKGATE_CTRL

#define PMU_MISC0_SET_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ PMU_MISC0_SET_CLKGATE_DELAY

#define PMU_MISC0_SET_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ PMU_MISC0_SET_DISCON_HIGH_SNVS

#define PMU_MISC0_SET_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ PMU_MISC0_SET_OSC_I

#define PMU_MISC0_SET_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ PMU_MISC0_SET_REFTOP_SELFBIASOFF

#define PMU_MISC0_SET_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ PMU_MISC0_SET_REFTOP_VBGADJ

#define PMU_MISC0_SET_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ PMU_MISC0_SET_RTC_XTAL_SOURCE

#define PMU_MISC0_SET_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ PMU_MISC0_SET_STOP_MODE_CONFIG

#define PMU_MISC0_SET_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

◆ PMU_MISC0_SET_VID_PLL_PREDIV

#define PMU_MISC0_SET_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

◆ PMU_MISC0_STOP_MODE_CONFIG

#define PMU_MISC0_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

◆ PMU_MISC0_TOG_CLKGATE_CTRL

#define PMU_MISC0_TOG_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ PMU_MISC0_TOG_CLKGATE_DELAY

#define PMU_MISC0_TOG_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ PMU_MISC0_TOG_DISCON_HIGH_SNVS

#define PMU_MISC0_TOG_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ PMU_MISC0_TOG_OSC_I

#define PMU_MISC0_TOG_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ PMU_MISC0_TOG_REFTOP_SELFBIASOFF

#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ PMU_MISC0_TOG_REFTOP_VBGADJ

#define PMU_MISC0_TOG_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ PMU_MISC0_TOG_RTC_XTAL_SOURCE

#define PMU_MISC0_TOG_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ PMU_MISC0_TOG_STOP_MODE_CONFIG

#define PMU_MISC0_TOG_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..SUSPEND (DSM) 0b01..Analog regulators are ON. 0b10..STOP (lower power) 0b11..STOP (very lower power)

◆ PMU_MISC0_TOG_VID_PLL_PREDIV

#define PMU_MISC0_TOG_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

◆ PMU_MISC0_VID_PLL_PREDIV

#define PMU_MISC0_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

◆ PMU_MISC1_CLR_LVDS1_CLK_SEL

#define PMU_MISC1_CLR_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..ARM PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

◆ PMU_MISC1_CLR_LVDS2_CLK_SEL

#define PMU_MISC1_CLR_LVDS2_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..ARM PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

◆ PMU_MISC1_LVDS1_CLK_SEL

#define PMU_MISC1_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..ARM PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

◆ PMU_MISC1_LVDS2_CLK_SEL

#define PMU_MISC1_LVDS2_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..ARM PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

◆ PMU_MISC1_SET_LVDS1_CLK_SEL

#define PMU_MISC1_SET_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..ARM PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

◆ PMU_MISC1_SET_LVDS2_CLK_SEL

#define PMU_MISC1_SET_LVDS2_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..ARM PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

◆ PMU_MISC1_TOG_LVDS1_CLK_SEL

#define PMU_MISC1_TOG_LVDS1_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)

LVDS1_CLK_SEL 0b00000..ARM PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M)

◆ PMU_MISC1_TOG_LVDS2_CLK_SEL

#define PMU_MISC1_TOG_LVDS2_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)

LVDS2_CLK_SEL 0b00000..ARM PLL 0b00001..System PLL 0b00010..ref_pfd4_clk == pll2_pfd0_clk 0b00011..ref_pfd5_clk == pll2_pfd1_clk 0b00100..ref_pfd6_clk == pll2_pfd2_clk 0b00101..ref_pfd7_clk == pll2_pfd3_clk 0b00110..Audio PLL 0b00111..Video PLL 0b01000..MLB PLL 0b01001..ethernet ref clock (ENET_PLL) 0b01010..PCIe ref clock (125M) 0b01011..SATA ref clock (100M) 0b01100..USB1 PLL clock 0b01101..USB2 PLL clock 0b01110..ref_pfd0_clk == pll3_pfd0_clk 0b01111..ref_pfd1_clk == pll3_pfd1_clk 0b10000..ref_pfd2_clk == pll3_pfd2_clk 0b10001..ref_pfd3_clk == pll3_pfd3_clk 0b10010..xtal (24M) 0b10011..LVDS1 (loopback) 0b10100..LVDS2 (not useful)

◆ XTALOSC24M_MISC0_CLKGATE_CTRL

#define XTALOSC24M_MISC0_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ XTALOSC24M_MISC0_CLKGATE_DELAY

#define XTALOSC24M_MISC0_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ XTALOSC24M_MISC0_CLR_CLKGATE_CTRL

#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ XTALOSC24M_MISC0_CLR_CLKGATE_DELAY

#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS

#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ XTALOSC24M_MISC0_CLR_OSC_I

#define XTALOSC24M_MISC0_CLR_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF

#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ

#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE

#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG

#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.

◆ XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV

#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

◆ XTALOSC24M_MISC0_DISCON_HIGH_SNVS

#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ XTALOSC24M_MISC0_OSC_I

#define XTALOSC24M_MISC0_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ XTALOSC24M_MISC0_REFTOP_SELFBIASOFF

#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ XTALOSC24M_MISC0_REFTOP_VBGADJ

#define XTALOSC24M_MISC0_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ XTALOSC24M_MISC0_RTC_XTAL_SOURCE

#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ XTALOSC24M_MISC0_SET_CLKGATE_CTRL

#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ XTALOSC24M_MISC0_SET_CLKGATE_DELAY

#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS

#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ XTALOSC24M_MISC0_SET_OSC_I

#define XTALOSC24M_MISC0_SET_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF

#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ XTALOSC24M_MISC0_SET_REFTOP_VBGADJ

#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE

#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG

#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.

◆ XTALOSC24M_MISC0_SET_VID_PLL_PREDIV

#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

◆ XTALOSC24M_MISC0_STOP_MODE_CONFIG

#define XTALOSC24M_MISC0_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.

◆ XTALOSC24M_MISC0_TOG_CLKGATE_CTRL

#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)

CLKGATE_CTRL 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. 0b1..Prevent the logic from ever gating off the clock.

◆ XTALOSC24M_MISC0_TOG_CLKGATE_DELAY

#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)

CLKGATE_DELAY 0b000..0.5ms 0b001..1.0ms 0b010..2.0ms 0b011..3.0ms 0b100..4.0ms 0b101..5.0ms 0b110..6.0ms 0b111..7.0ms

◆ XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS

#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)

DISCON_HIGH_SNVS 0b0..Turn on the switch 0b1..Turn off the switch

◆ XTALOSC24M_MISC0_TOG_OSC_I

#define XTALOSC24M_MISC0_TOG_OSC_I ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)

OSC_I 0b00..Nominal 0b01..Decrease current by 12.5% 0b10..Decrease current by 25.0% 0b11..Decrease current by 37.5%

◆ XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF

#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)

REFTOP_SELFBIASOFF 0b0..Uses coarse bias currents for startup 0b1..Uses bandgap-based bias currents for best performance.

◆ XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ

#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)

REFTOP_VBGADJ 0b000..Nominal VBG 0b001..VBG+0.78% 0b010..VBG+1.56% 0b011..VBG+2.34% 0b100..VBG-0.78% 0b101..VBG-1.56% 0b110..VBG-2.34% 0b111..VBG-3.12%

◆ XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE

#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)

RTC_XTAL_SOURCE 0b0..Internal ring oscillator 0b1..RTC_XTAL

◆ XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG

#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)

STOP_MODE_CONFIG 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.

◆ XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV

#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

◆ XTALOSC24M_MISC0_VID_PLL_PREDIV

#define XTALOSC24M_MISC0_VID_PLL_PREDIV ( x ) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)

VID_PLL_PREDIV 0b0..Divide by 1 0b1..Divide by 2

PLL_ARM - Analog ARM PLL control Register

PLL_ARM_SET - Analog ARM PLL control Register

PLL_ARM_CLR - Analog ARM PLL control Register

PLL_ARM_TOG - Analog ARM PLL control Register

PLL_USB1 - Analog USB1 480MHz PLL Control Register

PLL_USB1_SET - Analog USB1 480MHz PLL Control Register

PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register

PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register

PLL_USB2 - Analog USB2 480MHz PLL Control Register

PLL_USB2_SET - Analog USB2 480MHz PLL Control Register

PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register

PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register

PLL_SYS - Analog System PLL Control Register

PLL_SYS_SET - Analog System PLL Control Register

PLL_SYS_CLR - Analog System PLL Control Register

PLL_SYS_TOG - Analog System PLL Control Register

PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register

PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register

PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register

PLL_AUDIO - Analog Audio PLL control Register

PLL_AUDIO_SET - Analog Audio PLL control Register

PLL_AUDIO_CLR - Analog Audio PLL control Register

PLL_AUDIO_TOG - Analog Audio PLL control Register

PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register

PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register

PLL_VIDEO - Analog Video PLL control Register

PLL_VIDEO_SET - Analog Video PLL control Register

PLL_VIDEO_CLR - Analog Video PLL control Register

PLL_VIDEO_TOG - Analog Video PLL control Register

PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register

PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register

PLL_ENET - Analog ENET PLL Control Register

PLL_ENET_SET - Analog ENET PLL Control Register

PLL_ENET_CLR - Analog ENET PLL Control Register

PLL_ENET_TOG - Analog ENET PLL Control Register

PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register

PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register

PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register

PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register

PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register

PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register

PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register

PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register

MISC0 - Miscellaneous Register 0

MISC0_SET - Miscellaneous Register 0

MISC0_CLR - Miscellaneous Register 0

MISC0_TOG - Miscellaneous Register 0

MISC1 - Miscellaneous Register 1

MISC1_SET - Miscellaneous Register 1

MISC1_CLR - Miscellaneous Register 1

MISC1_TOG - Miscellaneous Register 1

MISC2 - Miscellaneous Register 2

MISC2_SET - Miscellaneous Register 2

MISC2_CLR - Miscellaneous Register 2

MISC2_TOG - Miscellaneous Register 2

Detailed Description

Macro Definition Documentation

◆ CCM_ANALOG_MISC0_CLKGATE_CTRL

◆ CCM_ANALOG_MISC0_CLKGATE_DELAY

◆ CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL

◆ CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY

◆ CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS

◆ CCM_ANALOG_MISC0_CLR_OSC_I

◆ CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF

◆ CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ

◆ CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE

◆ CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG

◆ CCM_ANALOG_MISC0_DISCON_HIGH_SNVS

◆ CCM_ANALOG_MISC0_OSC_I

◆ CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF

◆ CCM_ANALOG_MISC0_REFTOP_VBGADJ

◆ CCM_ANALOG_MISC0_RTC_XTAL_SOURCE

◆ CCM_ANALOG_MISC0_SET_CLKGATE_CTRL

◆ CCM_ANALOG_MISC0_SET_CLKGATE_DELAY

◆ CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS

◆ CCM_ANALOG_MISC0_SET_OSC_I

◆ CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF

◆ CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ

◆ CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE

◆ CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG