IOMUXC Register Masks

Macros
#define	IOMUXC_SW_MUX_CTL_PAD_COUNT   (124U)
#define	IOMUXC_SW_PAD_CTL_PAD_COUNT   (124U)
#define	IOMUXC_SELECT_INPUT_COUNT   (154U)
#define	IOMUXC_SW_MUX_CTL_PAD_COUNT   (145U)
#define	IOMUXC_SW_PAD_CTL_PAD_COUNT   (145U)
#define	IOMUXC_SELECT_INPUT_COUNT   (160U)
#define	IOMUXC_SW_MUX_CTL_PAD_COUNT   (145U)
#define	IOMUXC_SW_PAD_CTL_PAD_COUNT   (145U)
#define	IOMUXC_SELECT_INPUT_COUNT   (160U)

SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK   (0x7U)
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
#define	IOMUXC_SW_MUX_CTL_PAD_SION_MASK   (0x10U)
#define	IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT   (4U)
#define	IOMUXC_SW_MUX_CTL_PAD_SION(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)

SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register
#define	IOMUXC_SW_PAD_CTL_PAD_SRE_MASK   (0x1U)
#define	IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT   (0U)
#define	IOMUXC_SW_PAD_CTL_PAD_SRE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE_MASK   (0x38U)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT   (3U)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK   (0xC0U)
#define	IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT   (6U)
#define	IOMUXC_SW_PAD_CTL_PAD_SPEED(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE_MASK   (0x800U)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT   (11U)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_PKE_MASK   (0x1000U)
#define	IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT   (12U)
#define	IOMUXC_SW_PAD_CTL_PAD_PKE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE_MASK   (0x2000U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT   (13U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS_MASK   (0xC000U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT   (14U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_HYS_MASK   (0x10000U)
#define	IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT   (16U)
#define	IOMUXC_SW_PAD_CTL_PAD_HYS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)

SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR_INOUT23_SELECT_INPUT DAISY Register
#define	IOMUXC_SELECT_INPUT_DAISY_MASK   (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
#define	IOMUXC_SELECT_INPUT_DAISY_SHIFT   (0U)
#define	IOMUXC_SELECT_INPUT_DAISY(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */

SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK   (0xFU)
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
#define	IOMUXC_SW_MUX_CTL_PAD_SION_MASK   (0x10U)
#define	IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT   (4U)
#define	IOMUXC_SW_MUX_CTL_PAD_SION(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)

SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register
#define	IOMUXC_SW_PAD_CTL_PAD_SRE_MASK   (0x1U)
#define	IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT   (0U)
#define	IOMUXC_SW_PAD_CTL_PAD_SRE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE_MASK   (0x2U)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT   (1U)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK   (0x2U)
#define	IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT   (1U)
#define	IOMUXC_SW_PAD_CTL_PAD_PDRV(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE_MASK   (0x4U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT   (2U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_PULL_MASK   (0xCU)
#define	IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT   (2U)
#define	IOMUXC_SW_PAD_CTL_PAD_PULL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS_MASK   (0x8U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT   (3U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE_MASK   (0x10U)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT   (4U)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_MASK   (0x30000000U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT   (28U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK)

SELECT_INPUT - FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register
#define	IOMUXC_SELECT_INPUT_DAISY_MASK   (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
#define	IOMUXC_SELECT_INPUT_DAISY_SHIFT   (0U)
#define	IOMUXC_SELECT_INPUT_DAISY(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */

SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK   (0xFU)
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT   (0U)
#define	IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
#define	IOMUXC_SW_MUX_CTL_PAD_SION_MASK   (0x10U)
#define	IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT   (4U)
#define	IOMUXC_SW_MUX_CTL_PAD_SION(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)

SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register
#define	IOMUXC_SW_PAD_CTL_PAD_SRE_MASK   (0x1U)
#define	IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT   (0U)
#define	IOMUXC_SW_PAD_CTL_PAD_SRE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE_MASK   (0x2U)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT   (1U)
#define	IOMUXC_SW_PAD_CTL_PAD_DSE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK   (0x2U)
#define	IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT   (1U)
#define	IOMUXC_SW_PAD_CTL_PAD_PDRV(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE_MASK   (0x4U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT   (2U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_PULL_MASK   (0xCU)
#define	IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT   (2U)
#define	IOMUXC_SW_PAD_CTL_PAD_PULL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS_MASK   (0x8U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT   (3U)
#define	IOMUXC_SW_PAD_CTL_PAD_PUS(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE_MASK   (0x10U)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT   (4U)
#define	IOMUXC_SW_PAD_CTL_PAD_ODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_MASK   (0x30000000U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT   (28U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK   (0xC0000000U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT   (30U)
#define	IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK)

SELECT_INPUT - FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register
#define	IOMUXC_SELECT_INPUT_DAISY_MASK   (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
#define	IOMUXC_SELECT_INPUT_DAISY_SHIFT   (0U)
#define	IOMUXC_SELECT_INPUT_DAISY(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */

Detailed Description

Macro Definition Documentation

IOMUXC_SELECT_INPUT_DAISY [1/3]

#define IOMUXC_SELECT_INPUT_DAISY

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */

DAISY - Selecting Pads Involved in Daisy Chain. 0b000..Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6 0b001..Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1 0b010..Selecting Pad: GPIO_AD_B1_01 for Mode: ALT4 0b011..Selecting Pad: GPIO_AD_B1_08 for Mode: ALT3 0b100..Selecting Pad: GPIO_EMC_32 for Mode: ALT3

IOMUXC_SELECT_INPUT_DAISY [2/3]

#define IOMUXC_SELECT_INPUT_DAISY

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */

DAISY - Selecting Pads Involved in Daisy Chain. 0b00..Selecting Pad: GPIO_EMC_B2_19 for Mode: ALT3 0b01..Selecting Pad: GPIO_SD_B2_11 for Mode: ALT3 0b10..Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT2 0b11..Selecting Pad: GPIO_DISP_B2_14 for Mode: ALT4

IOMUXC_SELECT_INPUT_DAISY [3/3]

#define IOMUXC_SELECT_INPUT_DAISY

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */

DAISY - Selecting Pads Involved in Daisy Chain. 0b00..Selecting Pad: GPIO_EMC_B2_19 for Mode: ALT3 0b01..Selecting Pad: GPIO_SD_B2_11 for Mode: ALT3 0b10..Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT2 0b11..Selecting Pad: GPIO_DISP_B2_14 for Mode: ALT4

IOMUXC_SW_MUX_CTL_PAD_MUX_MODE [1/3]

#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. Note: Some functions are available on multiple pins. A given function should not be selected for more than one pin. 0b000..Select mux mode: ALT0 mux port: USB_OTG2_PWR of instance: usb 0b001..Select mux mode: ALT1 mux port: XBAR1_IN25 of instance: xbar1 0b010..Select mux mode: ALT2 mux port: LPUART1_RTS_B of instance: lpuart1 0b011..Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: enet 0b100..Select mux mode: ALT4 mux port: CSI_HSYNC of instance: csi 0b101..Select mux mode: ALT5 mux port: GPIO1_IO15 of instance: gpio1 0b110..Select mux mode: ALT6 mux port: FLEXCAN2_RX of instance: flexcan2 0b111..Select mux mode: ALT7 mux port: WDOG1_WDOG_RST_B_DEB of instance: wdog1

IOMUXC_SW_MUX_CTL_PAD_MUX_MODE [2/3]

#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b0000..Select mux mode: ALT0 mux port: SEMC_DATA22 of instance: SEMC 0b0001..Select mux mode: ALT1 mux port: GPT3_CAPTURE1 of instance: GPT3 0b1010..Select mux mode: ALT10 mux port: GPIO8_IO16 of instance: GPIO8 0b0010..Select mux mode: ALT2 mux port: SAI2_RX_BCLK of instance: SAI2 0b1011..Select mux mode: ALT11 mux port: FLEXPWM3_PWM3_A of instance: FLEXPWM3 0b0011..Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA19 of instance: VIDEO_MUX 0b0100..Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA00 of instance: FLEXSPI2 0b0101..Select mux mode: ALT5 mux port: GPIO_MUX2_IO16 of instance: GPIO_MUX2 0b0110..Select mux mode: ALT6 mux port: XBAR1_INOUT26 of instance: XBAR1 0b0111..Select mux mode: ALT7 mux port: ENET_1G_TX_ER of instance: ENET_1G 0b1000..Select mux mode: ALT8 mux port: LPSPI3_SOUT of instance: LPSPI3 0b1001..Select mux mode: ALT9 mux port: PIT1_TRIGGER1 of instance: PIT1

IOMUXC_SW_MUX_CTL_PAD_MUX_MODE [3/3]

#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b0000..Select mux mode: ALT0 mux port: SEMC_DATA22 of instance: SEMC 0b0001..Select mux mode: ALT1 mux port: GPT3_CAPTURE1 of instance: GPT3 0b1010..Select mux mode: ALT10 mux port: GPIO8_IO16 of instance: GPIO8 0b0010..Select mux mode: ALT2 mux port: SAI2_RX_BCLK of instance: SAI2 0b1011..Select mux mode: ALT11 mux port: FLEXPWM3_PWM3_A of instance: FLEXPWM3 0b0011..Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA19 of instance: VIDEO_MUX 0b0100..Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA00 of instance: FLEXSPI2 0b0101..Select mux mode: ALT5 mux port: GPIO_MUX2_IO16 of instance: GPIO_MUX2 0b0110..Select mux mode: ALT6 mux port: XBAR1_INOUT26 of instance: XBAR1 0b0111..Select mux mode: ALT7 mux port: ENET_1G_TX_ER of instance: ENET_1G 0b1000..Select mux mode: ALT8 mux port: LPSPI3_SOUT of instance: LPSPI3 0b1001..Select mux mode: ALT9 mux port: PIT1_TRIGGER1 of instance: PIT1

IOMUXC_SW_MUX_CTL_PAD_SION [1/3]

#define IOMUXC_SW_MUX_CTL_PAD_SION

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_AD_B0_00 0b0..Input Path is determined by functionality

IOMUXC_SW_MUX_CTL_PAD_SION [2/3]

#define IOMUXC_SW_MUX_CTL_PAD_SION

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_DISP_B1_00 0b0..Input Path is determined by functionality

IOMUXC_SW_MUX_CTL_PAD_SION [3/3]

#define IOMUXC_SW_MUX_CTL_PAD_SION

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_DISP_B1_00 0b0..Input Path is determined by functionality

IOMUXC_SW_PAD_CTL_PAD_DSE [1/3]

#define IOMUXC_SW_PAD_CTL_PAD_DSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)

DSE - Drive Strength Field 0b000..HI-Z 0b001..Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V 0b010..Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V 0b011..Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V 0b100..Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V 0b101..Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V 0b110..Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V 0b111..Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V

IOMUXC_SW_PAD_CTL_PAD_DSE [2/3]

#define IOMUXC_SW_PAD_CTL_PAD_DSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)

DSE - Drive Strength Field 0b0..normal drive strength 0b1..high drive strength

IOMUXC_SW_PAD_CTL_PAD_DSE [3/3]

#define IOMUXC_SW_PAD_CTL_PAD_DSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)

DSE - Drive Strength Field 0b0..normal drive strength 0b1..high drive strength

IOMUXC_SW_PAD_CTL_PAD_DWP [1/2]

#define IOMUXC_SW_PAD_CTL_PAD_DWP

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

IOMUXC_SW_PAD_CTL_PAD_DWP [2/2]

#define IOMUXC_SW_PAD_CTL_PAD_DWP

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK [1/2]

#define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK [2/2]

#define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

IOMUXC_SW_PAD_CTL_PAD_HYS

#define IOMUXC_SW_PAD_CTL_PAD_HYS

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)

HYS - Hyst. Enable Field 0b0..Hysteresis Disabled (CMOS input) 0b1..Hysteresis Enabled (Schmitt Trigger input)

IOMUXC_SW_PAD_CTL_PAD_ODE [1/3]

#define IOMUXC_SW_PAD_CTL_PAD_ODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)

ODE - Open Drain Enable Field 0b0..Open Drain Disabled (Output is CMOS) 0b1..Open Drain Enabled (Output is Open Drain)

IOMUXC_SW_PAD_CTL_PAD_ODE [2/3]

#define IOMUXC_SW_PAD_CTL_PAD_ODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)

ODE - Open Drain Field 0b0..Disabled 0b1..Enabled

IOMUXC_SW_PAD_CTL_PAD_ODE [3/3]

#define IOMUXC_SW_PAD_CTL_PAD_ODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)

ODE - Open Drain Field 0b0..Disabled 0b1..Enabled

IOMUXC_SW_PAD_CTL_PAD_PDRV [1/2]

#define IOMUXC_SW_PAD_CTL_PAD_PDRV

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK)

PDRV - PDRV Field 0b0..high drive strength 0b1..normal drive strength

IOMUXC_SW_PAD_CTL_PAD_PDRV [2/2]

#define IOMUXC_SW_PAD_CTL_PAD_PDRV

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK)

PDRV - PDRV Field 0b0..high drive strength 0b1..normal drive strength

IOMUXC_SW_PAD_CTL_PAD_PKE

#define IOMUXC_SW_PAD_CTL_PAD_PKE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)

PKE - Pull / Keep Enable Field 0b0..Pull/Keeper Disabled 0b1..Pull/Keeper Enabled

IOMUXC_SW_PAD_CTL_PAD_PUE [1/3]

#define IOMUXC_SW_PAD_CTL_PAD_PUE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)

PUE - Pull / Keep Select Field Control signal to enable internal pull-up/down resistors or pad keeper functionality. 0b0..Keep the previous output value when the output driver is disabled. 0b1..Pull-up or pull-down (determined by PUS field).

IOMUXC_SW_PAD_CTL_PAD_PUE [2/3]

#define IOMUXC_SW_PAD_CTL_PAD_PUE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable, Highz 0b1..Pull Enable

IOMUXC_SW_PAD_CTL_PAD_PUE [3/3]

#define IOMUXC_SW_PAD_CTL_PAD_PUE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable, Highz 0b1..Pull Enable

IOMUXC_SW_PAD_CTL_PAD_PULL [1/2]

#define IOMUXC_SW_PAD_CTL_PAD_PULL

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK)

PULL - Pull Down Pull Up Field 0b00..Forbidden 0b01..Internal pullup resistor enabled 0b10..Internal pulldown resistor enabled 0b11..No Pull

IOMUXC_SW_PAD_CTL_PAD_PULL [2/2]

#define IOMUXC_SW_PAD_CTL_PAD_PULL

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK)

PULL - Pull Down Pull Up Field 0b00..Forbidden 0b01..Internal pullup resistor enabled 0b10..Internal pulldown resistor enabled 0b11..No Pull

IOMUXC_SW_PAD_CTL_PAD_PUS [1/3]

#define IOMUXC_SW_PAD_CTL_PAD_PUS

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)

PUS - Pull Up / Down Config. Field Controls signals to select pull-up or pull-down internal resistance strength. 0b00..100K Ohm Pull Down 0b01..47K Ohm Pull Up 0b10..100K Ohm Pull Up 0b11..22K Ohm Pull Up

IOMUXC_SW_PAD_CTL_PAD_PUS [2/3]

#define IOMUXC_SW_PAD_CTL_PAD_PUS

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

IOMUXC_SW_PAD_CTL_PAD_PUS [3/3]

#define IOMUXC_SW_PAD_CTL_PAD_PUS

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)

PUS - Pull Up / Down Config. Field 0b0..Weak pull down 0b1..Weak pull up

IOMUXC_SW_PAD_CTL_PAD_SPEED

#define IOMUXC_SW_PAD_CTL_PAD_SPEED

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)

SPEED - Speed Field 0b00..50MHz 0b01..100MHz - 150MHz 0b10..100MHz - 150MHz 0b11..150MHz - 200MHz

IOMUXC_SW_PAD_CTL_PAD_SRE [1/3]

#define IOMUXC_SW_PAD_CTL_PAD_SRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

IOMUXC_SW_PAD_CTL_PAD_SRE [2/3]

#define IOMUXC_SW_PAD_CTL_PAD_SRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate

IOMUXC_SW_PAD_CTL_PAD_SRE [3/3]

#define IOMUXC_SW_PAD_CTL_PAD_SRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)

SRE - Slew Rate Field 0b0..Slow Slew Rate 0b1..Fast Slew Rate