SEL0 - Crossbar A Select Register 0
#define	XBARA_SEL0_SEL0_MASK (0x7FU)

#define	XBARA_SEL0_SEL0_SHIFT (0U)

#define	XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)

#define	XBARA_SEL0_SEL1_MASK (0x7F00U)

#define	XBARA_SEL0_SEL1_SHIFT (8U)

#define	XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)

SEL1 - Crossbar A Select Register 1
#define	XBARA_SEL1_SEL2_MASK (0x7FU)

#define	XBARA_SEL1_SEL2_SHIFT (0U)

#define	XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)

#define	XBARA_SEL1_SEL3_MASK (0x7F00U)

#define	XBARA_SEL1_SEL3_SHIFT (8U)

#define	XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)

SEL2 - Crossbar A Select Register 2
#define	XBARA_SEL2_SEL4_MASK (0x7FU)

#define	XBARA_SEL2_SEL4_SHIFT (0U)

#define	XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)

#define	XBARA_SEL2_SEL5_MASK (0x7F00U)

#define	XBARA_SEL2_SEL5_SHIFT (8U)

#define	XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)

SEL3 - Crossbar A Select Register 3
#define	XBARA_SEL3_SEL6_MASK (0x7FU)

#define	XBARA_SEL3_SEL6_SHIFT (0U)

#define	XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)

#define	XBARA_SEL3_SEL7_MASK (0x7F00U)

#define	XBARA_SEL3_SEL7_SHIFT (8U)

#define	XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)

SEL4 - Crossbar A Select Register 4
#define	XBARA_SEL4_SEL8_MASK (0x7FU)

#define	XBARA_SEL4_SEL8_SHIFT (0U)

#define	XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)

#define	XBARA_SEL4_SEL9_MASK (0x7F00U)

#define	XBARA_SEL4_SEL9_SHIFT (8U)

#define	XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)

SEL5 - Crossbar A Select Register 5
#define	XBARA_SEL5_SEL10_MASK (0x7FU)

#define	XBARA_SEL5_SEL10_SHIFT (0U)

#define	XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)

#define	XBARA_SEL5_SEL11_MASK (0x7F00U)

#define	XBARA_SEL5_SEL11_SHIFT (8U)

#define	XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)

SEL6 - Crossbar A Select Register 6
#define	XBARA_SEL6_SEL12_MASK (0x7FU)

#define	XBARA_SEL6_SEL12_SHIFT (0U)

#define	XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)

#define	XBARA_SEL6_SEL13_MASK (0x7F00U)

#define	XBARA_SEL6_SEL13_SHIFT (8U)

#define	XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)

SEL7 - Crossbar A Select Register 7
#define	XBARA_SEL7_SEL14_MASK (0x7FU)

#define	XBARA_SEL7_SEL14_SHIFT (0U)

#define	XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)

#define	XBARA_SEL7_SEL15_MASK (0x7F00U)

#define	XBARA_SEL7_SEL15_SHIFT (8U)

#define	XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)

SEL8 - Crossbar A Select Register 8
#define	XBARA_SEL8_SEL16_MASK (0x7FU)

#define	XBARA_SEL8_SEL16_SHIFT (0U)

#define	XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)

#define	XBARA_SEL8_SEL17_MASK (0x7F00U)

#define	XBARA_SEL8_SEL17_SHIFT (8U)

#define	XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)

SEL9 - Crossbar A Select Register 9
#define	XBARA_SEL9_SEL18_MASK (0x7FU)

#define	XBARA_SEL9_SEL18_SHIFT (0U)

#define	XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)

#define	XBARA_SEL9_SEL19_MASK (0x7F00U)

#define	XBARA_SEL9_SEL19_SHIFT (8U)

#define	XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)

SEL10 - Crossbar A Select Register 10
#define	XBARA_SEL10_SEL20_MASK (0x7FU)

#define	XBARA_SEL10_SEL20_SHIFT (0U)

#define	XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)

#define	XBARA_SEL10_SEL21_MASK (0x7F00U)

#define	XBARA_SEL10_SEL21_SHIFT (8U)

#define	XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)

SEL11 - Crossbar A Select Register 11
#define	XBARA_SEL11_SEL22_MASK (0x7FU)

#define	XBARA_SEL11_SEL22_SHIFT (0U)

#define	XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)

#define	XBARA_SEL11_SEL23_MASK (0x7F00U)

#define	XBARA_SEL11_SEL23_SHIFT (8U)

#define	XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)

SEL12 - Crossbar A Select Register 12
#define	XBARA_SEL12_SEL24_MASK (0x7FU)

#define	XBARA_SEL12_SEL24_SHIFT (0U)

#define	XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)

#define	XBARA_SEL12_SEL25_MASK (0x7F00U)

#define	XBARA_SEL12_SEL25_SHIFT (8U)

#define	XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)

SEL13 - Crossbar A Select Register 13
#define	XBARA_SEL13_SEL26_MASK (0x7FU)

#define	XBARA_SEL13_SEL26_SHIFT (0U)

#define	XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)

#define	XBARA_SEL13_SEL27_MASK (0x7F00U)

#define	XBARA_SEL13_SEL27_SHIFT (8U)

#define	XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)

SEL14 - Crossbar A Select Register 14
#define	XBARA_SEL14_SEL28_MASK (0x7FU)

#define	XBARA_SEL14_SEL28_SHIFT (0U)

#define	XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)

#define	XBARA_SEL14_SEL29_MASK (0x7F00U)

#define	XBARA_SEL14_SEL29_SHIFT (8U)

#define	XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)

SEL15 - Crossbar A Select Register 15
#define	XBARA_SEL15_SEL30_MASK (0x7FU)

#define	XBARA_SEL15_SEL30_SHIFT (0U)

#define	XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)

#define	XBARA_SEL15_SEL31_MASK (0x7F00U)

#define	XBARA_SEL15_SEL31_SHIFT (8U)

#define	XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)

SEL16 - Crossbar A Select Register 16
#define	XBARA_SEL16_SEL32_MASK (0x7FU)

#define	XBARA_SEL16_SEL32_SHIFT (0U)

#define	XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)

#define	XBARA_SEL16_SEL33_MASK (0x7F00U)

#define	XBARA_SEL16_SEL33_SHIFT (8U)

#define	XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)

SEL17 - Crossbar A Select Register 17
#define	XBARA_SEL17_SEL34_MASK (0x7FU)

#define	XBARA_SEL17_SEL34_SHIFT (0U)

#define	XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)

#define	XBARA_SEL17_SEL35_MASK (0x7F00U)

#define	XBARA_SEL17_SEL35_SHIFT (8U)

#define	XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)

SEL18 - Crossbar A Select Register 18
#define	XBARA_SEL18_SEL36_MASK (0x7FU)

#define	XBARA_SEL18_SEL36_SHIFT (0U)

#define	XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)

#define	XBARA_SEL18_SEL37_MASK (0x7F00U)

#define	XBARA_SEL18_SEL37_SHIFT (8U)

#define	XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)

SEL19 - Crossbar A Select Register 19
#define	XBARA_SEL19_SEL38_MASK (0x7FU)

#define	XBARA_SEL19_SEL38_SHIFT (0U)

#define	XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)

#define	XBARA_SEL19_SEL39_MASK (0x7F00U)

#define	XBARA_SEL19_SEL39_SHIFT (8U)

#define	XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)

SEL20 - Crossbar A Select Register 20
#define	XBARA_SEL20_SEL40_MASK (0x7FU)

#define	XBARA_SEL20_SEL40_SHIFT (0U)

#define	XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)

#define	XBARA_SEL20_SEL41_MASK (0x7F00U)

#define	XBARA_SEL20_SEL41_SHIFT (8U)

#define	XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)

SEL21 - Crossbar A Select Register 21
#define	XBARA_SEL21_SEL42_MASK (0x7FU)

#define	XBARA_SEL21_SEL42_SHIFT (0U)

#define	XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)

#define	XBARA_SEL21_SEL43_MASK (0x7F00U)

#define	XBARA_SEL21_SEL43_SHIFT (8U)

#define	XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)

SEL22 - Crossbar A Select Register 22
#define	XBARA_SEL22_SEL44_MASK (0x7FU)

#define	XBARA_SEL22_SEL44_SHIFT (0U)

#define	XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)

#define	XBARA_SEL22_SEL45_MASK (0x7F00U)

#define	XBARA_SEL22_SEL45_SHIFT (8U)

#define	XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)

SEL23 - Crossbar A Select Register 23
#define	XBARA_SEL23_SEL46_MASK (0x7FU)

#define	XBARA_SEL23_SEL46_SHIFT (0U)

#define	XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)

#define	XBARA_SEL23_SEL47_MASK (0x7F00U)

#define	XBARA_SEL23_SEL47_SHIFT (8U)

#define	XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)

SEL24 - Crossbar A Select Register 24
#define	XBARA_SEL24_SEL48_MASK (0x7FU)

#define	XBARA_SEL24_SEL48_SHIFT (0U)

#define	XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)

#define	XBARA_SEL24_SEL49_MASK (0x7F00U)

#define	XBARA_SEL24_SEL49_SHIFT (8U)

#define	XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)

SEL25 - Crossbar A Select Register 25
#define	XBARA_SEL25_SEL50_MASK (0x7FU)

#define	XBARA_SEL25_SEL50_SHIFT (0U)

#define	XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)

#define	XBARA_SEL25_SEL51_MASK (0x7F00U)

#define	XBARA_SEL25_SEL51_SHIFT (8U)

#define	XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)

SEL26 - Crossbar A Select Register 26
#define	XBARA_SEL26_SEL52_MASK (0x7FU)

#define	XBARA_SEL26_SEL52_SHIFT (0U)

#define	XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)

#define	XBARA_SEL26_SEL53_MASK (0x7F00U)

#define	XBARA_SEL26_SEL53_SHIFT (8U)

#define	XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)

SEL27 - Crossbar A Select Register 27
#define	XBARA_SEL27_SEL54_MASK (0x7FU)

#define	XBARA_SEL27_SEL54_SHIFT (0U)

#define	XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)

#define	XBARA_SEL27_SEL55_MASK (0x7F00U)

#define	XBARA_SEL27_SEL55_SHIFT (8U)

#define	XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)

SEL28 - Crossbar A Select Register 28
#define	XBARA_SEL28_SEL56_MASK (0x7FU)

#define	XBARA_SEL28_SEL56_SHIFT (0U)

#define	XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)

#define	XBARA_SEL28_SEL57_MASK (0x7F00U)

#define	XBARA_SEL28_SEL57_SHIFT (8U)

#define	XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)

SEL29 - Crossbar A Select Register 29
#define	XBARA_SEL29_SEL58_MASK (0x7FU)

#define	XBARA_SEL29_SEL58_SHIFT (0U)

#define	XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)

#define	XBARA_SEL29_SEL59_MASK (0x7F00U)

#define	XBARA_SEL29_SEL59_SHIFT (8U)

#define	XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)

SEL30 - Crossbar A Select Register 30
#define	XBARA_SEL30_SEL60_MASK (0x7FU)

#define	XBARA_SEL30_SEL60_SHIFT (0U)

#define	XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)

#define	XBARA_SEL30_SEL61_MASK (0x7F00U)

#define	XBARA_SEL30_SEL61_SHIFT (8U)

#define	XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)

SEL31 - Crossbar A Select Register 31
#define	XBARA_SEL31_SEL62_MASK (0x7FU)

#define	XBARA_SEL31_SEL62_SHIFT (0U)

#define	XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)

#define	XBARA_SEL31_SEL63_MASK (0x7F00U)

#define	XBARA_SEL31_SEL63_SHIFT (8U)

#define	XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)

SEL32 - Crossbar A Select Register 32
#define	XBARA_SEL32_SEL64_MASK (0x7FU)

#define	XBARA_SEL32_SEL64_SHIFT (0U)

#define	XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)

#define	XBARA_SEL32_SEL65_MASK (0x7F00U)

#define	XBARA_SEL32_SEL65_SHIFT (8U)

#define	XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)

SEL33 - Crossbar A Select Register 33
#define	XBARA_SEL33_SEL66_MASK (0x7FU)

#define	XBARA_SEL33_SEL66_SHIFT (0U)

#define	XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)

#define	XBARA_SEL33_SEL67_MASK (0x7F00U)

#define	XBARA_SEL33_SEL67_SHIFT (8U)

#define	XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)

SEL34 - Crossbar A Select Register 34
#define	XBARA_SEL34_SEL68_MASK (0x7FU)

#define	XBARA_SEL34_SEL68_SHIFT (0U)

#define	XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)

#define	XBARA_SEL34_SEL69_MASK (0x7F00U)

#define	XBARA_SEL34_SEL69_SHIFT (8U)

#define	XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)

SEL35 - Crossbar A Select Register 35
#define	XBARA_SEL35_SEL70_MASK (0x7FU)

#define	XBARA_SEL35_SEL70_SHIFT (0U)

#define	XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)

#define	XBARA_SEL35_SEL71_MASK (0x7F00U)

#define	XBARA_SEL35_SEL71_SHIFT (8U)

#define	XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)

SEL36 - Crossbar A Select Register 36
#define	XBARA_SEL36_SEL72_MASK (0x7FU)

#define	XBARA_SEL36_SEL72_SHIFT (0U)

#define	XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)

#define	XBARA_SEL36_SEL73_MASK (0x7F00U)

#define	XBARA_SEL36_SEL73_SHIFT (8U)

#define	XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)

SEL37 - Crossbar A Select Register 37
#define	XBARA_SEL37_SEL74_MASK (0x7FU)

#define	XBARA_SEL37_SEL74_SHIFT (0U)

#define	XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)

#define	XBARA_SEL37_SEL75_MASK (0x7F00U)

#define	XBARA_SEL37_SEL75_SHIFT (8U)

#define	XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)

SEL38 - Crossbar A Select Register 38
#define	XBARA_SEL38_SEL76_MASK (0x7FU)

#define	XBARA_SEL38_SEL76_SHIFT (0U)

#define	XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)

#define	XBARA_SEL38_SEL77_MASK (0x7F00U)

#define	XBARA_SEL38_SEL77_SHIFT (8U)

#define	XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)

SEL39 - Crossbar A Select Register 39
#define	XBARA_SEL39_SEL78_MASK (0x7FU)

#define	XBARA_SEL39_SEL78_SHIFT (0U)

#define	XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)

#define	XBARA_SEL39_SEL79_MASK (0x7F00U)

#define	XBARA_SEL39_SEL79_SHIFT (8U)

#define	XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)

SEL40 - Crossbar A Select Register 40
#define	XBARA_SEL40_SEL80_MASK (0x7FU)

#define	XBARA_SEL40_SEL80_SHIFT (0U)

#define	XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)

#define	XBARA_SEL40_SEL81_MASK (0x7F00U)

#define	XBARA_SEL40_SEL81_SHIFT (8U)

#define	XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)

SEL41 - Crossbar A Select Register 41
#define	XBARA_SEL41_SEL82_MASK (0x7FU)

#define	XBARA_SEL41_SEL82_SHIFT (0U)

#define	XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)

#define	XBARA_SEL41_SEL83_MASK (0x7F00U)

#define	XBARA_SEL41_SEL83_SHIFT (8U)

#define	XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)

SEL42 - Crossbar A Select Register 42
#define	XBARA_SEL42_SEL84_MASK (0x7FU)

#define	XBARA_SEL42_SEL84_SHIFT (0U)

#define	XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)

#define	XBARA_SEL42_SEL85_MASK (0x7F00U)

#define	XBARA_SEL42_SEL85_SHIFT (8U)

#define	XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)

SEL43 - Crossbar A Select Register 43
#define	XBARA_SEL43_SEL86_MASK (0x7FU)

#define	XBARA_SEL43_SEL86_SHIFT (0U)

#define	XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)

#define	XBARA_SEL43_SEL87_MASK (0x7F00U)

#define	XBARA_SEL43_SEL87_SHIFT (8U)

#define	XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)

SEL44 - Crossbar A Select Register 44
#define	XBARA_SEL44_SEL88_MASK (0x7FU)

#define	XBARA_SEL44_SEL88_SHIFT (0U)

#define	XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)

#define	XBARA_SEL44_SEL89_MASK (0x7F00U)

#define	XBARA_SEL44_SEL89_SHIFT (8U)

#define	XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)

SEL45 - Crossbar A Select Register 45
#define	XBARA_SEL45_SEL90_MASK (0x7FU)

#define	XBARA_SEL45_SEL90_SHIFT (0U)

#define	XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)

#define	XBARA_SEL45_SEL91_MASK (0x7F00U)

#define	XBARA_SEL45_SEL91_SHIFT (8U)

#define	XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)

SEL46 - Crossbar A Select Register 46
#define	XBARA_SEL46_SEL92_MASK (0x7FU)

#define	XBARA_SEL46_SEL92_SHIFT (0U)

#define	XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)

#define	XBARA_SEL46_SEL93_MASK (0x7F00U)

#define	XBARA_SEL46_SEL93_SHIFT (8U)

#define	XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)

SEL47 - Crossbar A Select Register 47
#define	XBARA_SEL47_SEL94_MASK (0x7FU)

#define	XBARA_SEL47_SEL94_SHIFT (0U)

#define	XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)

#define	XBARA_SEL47_SEL95_MASK (0x7F00U)

#define	XBARA_SEL47_SEL95_SHIFT (8U)

#define	XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)

SEL48 - Crossbar A Select Register 48
#define	XBARA_SEL48_SEL96_MASK (0x7FU)

#define	XBARA_SEL48_SEL96_SHIFT (0U)

#define	XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)

#define	XBARA_SEL48_SEL97_MASK (0x7F00U)

#define	XBARA_SEL48_SEL97_SHIFT (8U)

#define	XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)

SEL49 - Crossbar A Select Register 49
#define	XBARA_SEL49_SEL98_MASK (0x7FU)

#define	XBARA_SEL49_SEL98_SHIFT (0U)

#define	XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)

#define	XBARA_SEL49_SEL99_MASK (0x7F00U)

#define	XBARA_SEL49_SEL99_SHIFT (8U)

#define	XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)

SEL50 - Crossbar A Select Register 50
#define	XBARA_SEL50_SEL100_MASK (0x7FU)

#define	XBARA_SEL50_SEL100_SHIFT (0U)

#define	XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)

#define	XBARA_SEL50_SEL101_MASK (0x7F00U)

#define	XBARA_SEL50_SEL101_SHIFT (8U)

#define	XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)

SEL51 - Crossbar A Select Register 51
#define	XBARA_SEL51_SEL102_MASK (0x7FU)

#define	XBARA_SEL51_SEL102_SHIFT (0U)

#define	XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)

#define	XBARA_SEL51_SEL103_MASK (0x7F00U)

#define	XBARA_SEL51_SEL103_SHIFT (8U)

#define	XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)

SEL52 - Crossbar A Select Register 52
#define	XBARA_SEL52_SEL104_MASK (0x7FU)

#define	XBARA_SEL52_SEL104_SHIFT (0U)

#define	XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)

#define	XBARA_SEL52_SEL105_MASK (0x7F00U)

#define	XBARA_SEL52_SEL105_SHIFT (8U)

#define	XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)

SEL53 - Crossbar A Select Register 53
#define	XBARA_SEL53_SEL106_MASK (0x7FU)

#define	XBARA_SEL53_SEL106_SHIFT (0U)

#define	XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)

#define	XBARA_SEL53_SEL107_MASK (0x7F00U)

#define	XBARA_SEL53_SEL107_SHIFT (8U)

#define	XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)

SEL54 - Crossbar A Select Register 54
#define	XBARA_SEL54_SEL108_MASK (0x7FU)

#define	XBARA_SEL54_SEL108_SHIFT (0U)

#define	XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)

#define	XBARA_SEL54_SEL109_MASK (0x7F00U)

#define	XBARA_SEL54_SEL109_SHIFT (8U)

#define	XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)

SEL55 - Crossbar A Select Register 55
#define	XBARA_SEL55_SEL110_MASK (0x7FU)

#define	XBARA_SEL55_SEL110_SHIFT (0U)

#define	XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)

#define	XBARA_SEL55_SEL111_MASK (0x7F00U)

#define	XBARA_SEL55_SEL111_SHIFT (8U)

#define	XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)

SEL56 - Crossbar A Select Register 56
#define	XBARA_SEL56_SEL112_MASK (0x7FU)

#define	XBARA_SEL56_SEL112_SHIFT (0U)

#define	XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)

#define	XBARA_SEL56_SEL113_MASK (0x7F00U)

#define	XBARA_SEL56_SEL113_SHIFT (8U)

#define	XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)

SEL57 - Crossbar A Select Register 57
#define	XBARA_SEL57_SEL114_MASK (0x7FU)

#define	XBARA_SEL57_SEL114_SHIFT (0U)

#define	XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)

#define	XBARA_SEL57_SEL115_MASK (0x7F00U)

#define	XBARA_SEL57_SEL115_SHIFT (8U)

#define	XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)

SEL58 - Crossbar A Select Register 58
#define	XBARA_SEL58_SEL116_MASK (0x7FU)

#define	XBARA_SEL58_SEL116_SHIFT (0U)

#define	XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)

#define	XBARA_SEL58_SEL117_MASK (0x7F00U)

#define	XBARA_SEL58_SEL117_SHIFT (8U)

#define	XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)

SEL59 - Crossbar A Select Register 59
#define	XBARA_SEL59_SEL118_MASK (0x7FU)

#define	XBARA_SEL59_SEL118_SHIFT (0U)

#define	XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)

#define	XBARA_SEL59_SEL119_MASK (0x7F00U)

#define	XBARA_SEL59_SEL119_SHIFT (8U)

#define	XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)

SEL60 - Crossbar A Select Register 60
#define	XBARA_SEL60_SEL120_MASK (0x7FU)

#define	XBARA_SEL60_SEL120_SHIFT (0U)

#define	XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)

#define	XBARA_SEL60_SEL121_MASK (0x7F00U)

#define	XBARA_SEL60_SEL121_SHIFT (8U)

#define	XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)

SEL61 - Crossbar A Select Register 61
#define	XBARA_SEL61_SEL122_MASK (0x7FU)

#define	XBARA_SEL61_SEL122_SHIFT (0U)

#define	XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)

#define	XBARA_SEL61_SEL123_MASK (0x7F00U)

#define	XBARA_SEL61_SEL123_SHIFT (8U)

#define	XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)

SEL62 - Crossbar A Select Register 62
#define	XBARA_SEL62_SEL124_MASK (0x7FU)

#define	XBARA_SEL62_SEL124_SHIFT (0U)

#define	XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)

#define	XBARA_SEL62_SEL125_MASK (0x7F00U)

#define	XBARA_SEL62_SEL125_SHIFT (8U)

#define	XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)

SEL63 - Crossbar A Select Register 63
#define	XBARA_SEL63_SEL126_MASK (0x7FU)

#define	XBARA_SEL63_SEL126_SHIFT (0U)

#define	XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)

#define	XBARA_SEL63_SEL127_MASK (0x7F00U)

#define	XBARA_SEL63_SEL127_SHIFT (8U)

#define	XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)

SEL64 - Crossbar A Select Register 64
#define	XBARA_SEL64_SEL128_MASK (0x7FU)

#define	XBARA_SEL64_SEL128_SHIFT (0U)

#define	XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)

#define	XBARA_SEL64_SEL129_MASK (0x7F00U)

#define	XBARA_SEL64_SEL129_SHIFT (8U)

#define	XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)

SEL65 - Crossbar A Select Register 65
#define	XBARA_SEL65_SEL130_MASK (0x7FU)

#define	XBARA_SEL65_SEL130_SHIFT (0U)

#define	XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)

#define	XBARA_SEL65_SEL131_MASK (0x7F00U)

#define	XBARA_SEL65_SEL131_SHIFT (8U)

#define	XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)

CTRL0 - Crossbar A Control Register 0
#define	XBARA_CTRL0_DEN0_MASK (0x1U)

#define	XBARA_CTRL0_DEN0_SHIFT (0U)

#define	XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)

#define	XBARA_CTRL0_IEN0_MASK (0x2U)

#define	XBARA_CTRL0_IEN0_SHIFT (1U)

#define	XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)

#define	XBARA_CTRL0_EDGE0_MASK (0xCU)

#define	XBARA_CTRL0_EDGE0_SHIFT (2U)

#define	XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)

#define	XBARA_CTRL0_STS0_MASK (0x10U)

#define	XBARA_CTRL0_STS0_SHIFT (4U)

#define	XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)

#define	XBARA_CTRL0_DEN1_MASK (0x100U)

#define	XBARA_CTRL0_DEN1_SHIFT (8U)

#define	XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)

#define	XBARA_CTRL0_IEN1_MASK (0x200U)

#define	XBARA_CTRL0_IEN1_SHIFT (9U)

#define	XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)

#define	XBARA_CTRL0_EDGE1_MASK (0xC00U)

#define	XBARA_CTRL0_EDGE1_SHIFT (10U)

#define	XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)

#define	XBARA_CTRL0_STS1_MASK (0x1000U)

#define	XBARA_CTRL0_STS1_SHIFT (12U)

#define	XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)

CTRL1 - Crossbar A Control Register 1
#define	XBARA_CTRL1_DEN2_MASK (0x1U)

#define	XBARA_CTRL1_DEN2_SHIFT (0U)

#define	XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)

#define	XBARA_CTRL1_IEN2_MASK (0x2U)

#define	XBARA_CTRL1_IEN2_SHIFT (1U)

#define	XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)

#define	XBARA_CTRL1_EDGE2_MASK (0xCU)

#define	XBARA_CTRL1_EDGE2_SHIFT (2U)

#define	XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)

#define	XBARA_CTRL1_STS2_MASK (0x10U)

#define	XBARA_CTRL1_STS2_SHIFT (4U)

#define	XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)

#define	XBARA_CTRL1_DEN3_MASK (0x100U)

#define	XBARA_CTRL1_DEN3_SHIFT (8U)

#define	XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)

#define	XBARA_CTRL1_IEN3_MASK (0x200U)

#define	XBARA_CTRL1_IEN3_SHIFT (9U)

#define	XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)

#define	XBARA_CTRL1_EDGE3_MASK (0xC00U)

#define	XBARA_CTRL1_EDGE3_SHIFT (10U)

#define	XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)

#define	XBARA_CTRL1_STS3_MASK (0x1000U)

#define	XBARA_CTRL1_STS3_SHIFT (12U)

#define	XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)

SEL0 - Crossbar A Select Register 0
#define	XBARA_SEL0_SEL0_MASK (0xFFU)

#define	XBARA_SEL0_SEL0_SHIFT (0U)

#define	XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)

#define	XBARA_SEL0_SEL1_MASK (0xFF00U)

#define	XBARA_SEL0_SEL1_SHIFT (8U)

#define	XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)

SEL1 - Crossbar A Select Register 1
#define	XBARA_SEL1_SEL2_MASK (0xFFU)

#define	XBARA_SEL1_SEL2_SHIFT (0U)

#define	XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)

#define	XBARA_SEL1_SEL3_MASK (0xFF00U)

#define	XBARA_SEL1_SEL3_SHIFT (8U)

#define	XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)

SEL2 - Crossbar A Select Register 2
#define	XBARA_SEL2_SEL4_MASK (0xFFU)

#define	XBARA_SEL2_SEL4_SHIFT (0U)

#define	XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)

#define	XBARA_SEL2_SEL5_MASK (0xFF00U)

#define	XBARA_SEL2_SEL5_SHIFT (8U)

#define	XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)

SEL3 - Crossbar A Select Register 3
#define	XBARA_SEL3_SEL6_MASK (0xFFU)

#define	XBARA_SEL3_SEL6_SHIFT (0U)

#define	XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)

#define	XBARA_SEL3_SEL7_MASK (0xFF00U)

#define	XBARA_SEL3_SEL7_SHIFT (8U)

#define	XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)

SEL4 - Crossbar A Select Register 4
#define	XBARA_SEL4_SEL8_MASK (0xFFU)

#define	XBARA_SEL4_SEL8_SHIFT (0U)

#define	XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)

#define	XBARA_SEL4_SEL9_MASK (0xFF00U)

#define	XBARA_SEL4_SEL9_SHIFT (8U)

#define	XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)

SEL5 - Crossbar A Select Register 5
#define	XBARA_SEL5_SEL10_MASK (0xFFU)

#define	XBARA_SEL5_SEL10_SHIFT (0U)

#define	XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)

#define	XBARA_SEL5_SEL11_MASK (0xFF00U)

#define	XBARA_SEL5_SEL11_SHIFT (8U)

#define	XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)

SEL6 - Crossbar A Select Register 6
#define	XBARA_SEL6_SEL12_MASK (0xFFU)

#define	XBARA_SEL6_SEL12_SHIFT (0U)

#define	XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)

#define	XBARA_SEL6_SEL13_MASK (0xFF00U)

#define	XBARA_SEL6_SEL13_SHIFT (8U)

#define	XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)

SEL7 - Crossbar A Select Register 7
#define	XBARA_SEL7_SEL14_MASK (0xFFU)

#define	XBARA_SEL7_SEL14_SHIFT (0U)

#define	XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)

#define	XBARA_SEL7_SEL15_MASK (0xFF00U)

#define	XBARA_SEL7_SEL15_SHIFT (8U)

#define	XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)

SEL8 - Crossbar A Select Register 8
#define	XBARA_SEL8_SEL16_MASK (0xFFU)

#define	XBARA_SEL8_SEL16_SHIFT (0U)

#define	XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)

#define	XBARA_SEL8_SEL17_MASK (0xFF00U)

#define	XBARA_SEL8_SEL17_SHIFT (8U)

#define	XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)

SEL9 - Crossbar A Select Register 9
#define	XBARA_SEL9_SEL18_MASK (0xFFU)

#define	XBARA_SEL9_SEL18_SHIFT (0U)

#define	XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)

#define	XBARA_SEL9_SEL19_MASK (0xFF00U)

#define	XBARA_SEL9_SEL19_SHIFT (8U)

#define	XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)

SEL10 - Crossbar A Select Register 10
#define	XBARA_SEL10_SEL20_MASK (0xFFU)

#define	XBARA_SEL10_SEL20_SHIFT (0U)

#define	XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)

#define	XBARA_SEL10_SEL21_MASK (0xFF00U)

#define	XBARA_SEL10_SEL21_SHIFT (8U)

#define	XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)

SEL11 - Crossbar A Select Register 11
#define	XBARA_SEL11_SEL22_MASK (0xFFU)

#define	XBARA_SEL11_SEL22_SHIFT (0U)

#define	XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)

#define	XBARA_SEL11_SEL23_MASK (0xFF00U)

#define	XBARA_SEL11_SEL23_SHIFT (8U)

#define	XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)

SEL12 - Crossbar A Select Register 12
#define	XBARA_SEL12_SEL24_MASK (0xFFU)

#define	XBARA_SEL12_SEL24_SHIFT (0U)

#define	XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)

#define	XBARA_SEL12_SEL25_MASK (0xFF00U)

#define	XBARA_SEL12_SEL25_SHIFT (8U)

#define	XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)

SEL13 - Crossbar A Select Register 13
#define	XBARA_SEL13_SEL26_MASK (0xFFU)

#define	XBARA_SEL13_SEL26_SHIFT (0U)

#define	XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)

#define	XBARA_SEL13_SEL27_MASK (0xFF00U)

#define	XBARA_SEL13_SEL27_SHIFT (8U)

#define	XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)

SEL14 - Crossbar A Select Register 14
#define	XBARA_SEL14_SEL28_MASK (0xFFU)

#define	XBARA_SEL14_SEL28_SHIFT (0U)

#define	XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)

#define	XBARA_SEL14_SEL29_MASK (0xFF00U)

#define	XBARA_SEL14_SEL29_SHIFT (8U)

#define	XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)

SEL15 - Crossbar A Select Register 15
#define	XBARA_SEL15_SEL30_MASK (0xFFU)

#define	XBARA_SEL15_SEL30_SHIFT (0U)

#define	XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)

#define	XBARA_SEL15_SEL31_MASK (0xFF00U)

#define	XBARA_SEL15_SEL31_SHIFT (8U)

#define	XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)

SEL16 - Crossbar A Select Register 16
#define	XBARA_SEL16_SEL32_MASK (0xFFU)

#define	XBARA_SEL16_SEL32_SHIFT (0U)

#define	XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)

#define	XBARA_SEL16_SEL33_MASK (0xFF00U)

#define	XBARA_SEL16_SEL33_SHIFT (8U)

#define	XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)

SEL17 - Crossbar A Select Register 17
#define	XBARA_SEL17_SEL34_MASK (0xFFU)

#define	XBARA_SEL17_SEL34_SHIFT (0U)

#define	XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)

#define	XBARA_SEL17_SEL35_MASK (0xFF00U)

#define	XBARA_SEL17_SEL35_SHIFT (8U)

#define	XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)

SEL18 - Crossbar A Select Register 18
#define	XBARA_SEL18_SEL36_MASK (0xFFU)

#define	XBARA_SEL18_SEL36_SHIFT (0U)

#define	XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)

#define	XBARA_SEL18_SEL37_MASK (0xFF00U)

#define	XBARA_SEL18_SEL37_SHIFT (8U)

#define	XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)

SEL19 - Crossbar A Select Register 19
#define	XBARA_SEL19_SEL38_MASK (0xFFU)

#define	XBARA_SEL19_SEL38_SHIFT (0U)

#define	XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)

#define	XBARA_SEL19_SEL39_MASK (0xFF00U)

#define	XBARA_SEL19_SEL39_SHIFT (8U)

#define	XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)

SEL20 - Crossbar A Select Register 20
#define	XBARA_SEL20_SEL40_MASK (0xFFU)

#define	XBARA_SEL20_SEL40_SHIFT (0U)

#define	XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)

#define	XBARA_SEL20_SEL41_MASK (0xFF00U)

#define	XBARA_SEL20_SEL41_SHIFT (8U)

#define	XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)

SEL21 - Crossbar A Select Register 21
#define	XBARA_SEL21_SEL42_MASK (0xFFU)

#define	XBARA_SEL21_SEL42_SHIFT (0U)

#define	XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)

#define	XBARA_SEL21_SEL43_MASK (0xFF00U)

#define	XBARA_SEL21_SEL43_SHIFT (8U)

#define	XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)

SEL22 - Crossbar A Select Register 22
#define	XBARA_SEL22_SEL44_MASK (0xFFU)

#define	XBARA_SEL22_SEL44_SHIFT (0U)

#define	XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)

#define	XBARA_SEL22_SEL45_MASK (0xFF00U)

#define	XBARA_SEL22_SEL45_SHIFT (8U)

#define	XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)

SEL23 - Crossbar A Select Register 23
#define	XBARA_SEL23_SEL46_MASK (0xFFU)

#define	XBARA_SEL23_SEL46_SHIFT (0U)

#define	XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)

#define	XBARA_SEL23_SEL47_MASK (0xFF00U)

#define	XBARA_SEL23_SEL47_SHIFT (8U)

#define	XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)

SEL24 - Crossbar A Select Register 24
#define	XBARA_SEL24_SEL48_MASK (0xFFU)

#define	XBARA_SEL24_SEL48_SHIFT (0U)

#define	XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)

#define	XBARA_SEL24_SEL49_MASK (0xFF00U)

#define	XBARA_SEL24_SEL49_SHIFT (8U)

#define	XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)

SEL25 - Crossbar A Select Register 25
#define	XBARA_SEL25_SEL50_MASK (0xFFU)

#define	XBARA_SEL25_SEL50_SHIFT (0U)

#define	XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)

#define	XBARA_SEL25_SEL51_MASK (0xFF00U)

#define	XBARA_SEL25_SEL51_SHIFT (8U)

#define	XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)

SEL26 - Crossbar A Select Register 26
#define	XBARA_SEL26_SEL52_MASK (0xFFU)

#define	XBARA_SEL26_SEL52_SHIFT (0U)

#define	XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)

#define	XBARA_SEL26_SEL53_MASK (0xFF00U)

#define	XBARA_SEL26_SEL53_SHIFT (8U)

#define	XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)

SEL27 - Crossbar A Select Register 27
#define	XBARA_SEL27_SEL54_MASK (0xFFU)

#define	XBARA_SEL27_SEL54_SHIFT (0U)

#define	XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)

#define	XBARA_SEL27_SEL55_MASK (0xFF00U)

#define	XBARA_SEL27_SEL55_SHIFT (8U)

#define	XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)

SEL28 - Crossbar A Select Register 28
#define	XBARA_SEL28_SEL56_MASK (0xFFU)

#define	XBARA_SEL28_SEL56_SHIFT (0U)

#define	XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)

#define	XBARA_SEL28_SEL57_MASK (0xFF00U)

#define	XBARA_SEL28_SEL57_SHIFT (8U)

#define	XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)

SEL29 - Crossbar A Select Register 29
#define	XBARA_SEL29_SEL58_MASK (0xFFU)

#define	XBARA_SEL29_SEL58_SHIFT (0U)

#define	XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)

#define	XBARA_SEL29_SEL59_MASK (0xFF00U)

#define	XBARA_SEL29_SEL59_SHIFT (8U)

#define	XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)

SEL30 - Crossbar A Select Register 30
#define	XBARA_SEL30_SEL60_MASK (0xFFU)

#define	XBARA_SEL30_SEL60_SHIFT (0U)

#define	XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)

#define	XBARA_SEL30_SEL61_MASK (0xFF00U)

#define	XBARA_SEL30_SEL61_SHIFT (8U)

#define	XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)

SEL31 - Crossbar A Select Register 31
#define	XBARA_SEL31_SEL62_MASK (0xFFU)

#define	XBARA_SEL31_SEL62_SHIFT (0U)

#define	XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)

#define	XBARA_SEL31_SEL63_MASK (0xFF00U)

#define	XBARA_SEL31_SEL63_SHIFT (8U)

#define	XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)

SEL32 - Crossbar A Select Register 32
#define	XBARA_SEL32_SEL64_MASK (0xFFU)

#define	XBARA_SEL32_SEL64_SHIFT (0U)

#define	XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)

#define	XBARA_SEL32_SEL65_MASK (0xFF00U)

#define	XBARA_SEL32_SEL65_SHIFT (8U)

#define	XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)

SEL33 - Crossbar A Select Register 33
#define	XBARA_SEL33_SEL66_MASK (0xFFU)

#define	XBARA_SEL33_SEL66_SHIFT (0U)

#define	XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)

#define	XBARA_SEL33_SEL67_MASK (0xFF00U)

#define	XBARA_SEL33_SEL67_SHIFT (8U)

#define	XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)

SEL34 - Crossbar A Select Register 34
#define	XBARA_SEL34_SEL68_MASK (0xFFU)

#define	XBARA_SEL34_SEL68_SHIFT (0U)

#define	XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)

#define	XBARA_SEL34_SEL69_MASK (0xFF00U)

#define	XBARA_SEL34_SEL69_SHIFT (8U)

#define	XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)

SEL35 - Crossbar A Select Register 35
#define	XBARA_SEL35_SEL70_MASK (0xFFU)

#define	XBARA_SEL35_SEL70_SHIFT (0U)

#define	XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)

#define	XBARA_SEL35_SEL71_MASK (0xFF00U)

#define	XBARA_SEL35_SEL71_SHIFT (8U)

#define	XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)

SEL36 - Crossbar A Select Register 36
#define	XBARA_SEL36_SEL72_MASK (0xFFU)

#define	XBARA_SEL36_SEL72_SHIFT (0U)

#define	XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)

#define	XBARA_SEL36_SEL73_MASK (0xFF00U)

#define	XBARA_SEL36_SEL73_SHIFT (8U)

#define	XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)

SEL37 - Crossbar A Select Register 37
#define	XBARA_SEL37_SEL74_MASK (0xFFU)

#define	XBARA_SEL37_SEL74_SHIFT (0U)

#define	XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)

#define	XBARA_SEL37_SEL75_MASK (0xFF00U)

#define	XBARA_SEL37_SEL75_SHIFT (8U)

#define	XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)

SEL38 - Crossbar A Select Register 38
#define	XBARA_SEL38_SEL76_MASK (0xFFU)

#define	XBARA_SEL38_SEL76_SHIFT (0U)

#define	XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)

#define	XBARA_SEL38_SEL77_MASK (0xFF00U)

#define	XBARA_SEL38_SEL77_SHIFT (8U)

#define	XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)

SEL39 - Crossbar A Select Register 39
#define	XBARA_SEL39_SEL78_MASK (0xFFU)

#define	XBARA_SEL39_SEL78_SHIFT (0U)

#define	XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)

#define	XBARA_SEL39_SEL79_MASK (0xFF00U)

#define	XBARA_SEL39_SEL79_SHIFT (8U)

#define	XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)

SEL40 - Crossbar A Select Register 40
#define	XBARA_SEL40_SEL80_MASK (0xFFU)

#define	XBARA_SEL40_SEL80_SHIFT (0U)

#define	XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)

#define	XBARA_SEL40_SEL81_MASK (0xFF00U)

#define	XBARA_SEL40_SEL81_SHIFT (8U)

#define	XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)

SEL41 - Crossbar A Select Register 41
#define	XBARA_SEL41_SEL82_MASK (0xFFU)

#define	XBARA_SEL41_SEL82_SHIFT (0U)

#define	XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)

#define	XBARA_SEL41_SEL83_MASK (0xFF00U)

#define	XBARA_SEL41_SEL83_SHIFT (8U)

#define	XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)

SEL42 - Crossbar A Select Register 42
#define	XBARA_SEL42_SEL84_MASK (0xFFU)

#define	XBARA_SEL42_SEL84_SHIFT (0U)

#define	XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)

#define	XBARA_SEL42_SEL85_MASK (0xFF00U)

#define	XBARA_SEL42_SEL85_SHIFT (8U)

#define	XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)

SEL43 - Crossbar A Select Register 43
#define	XBARA_SEL43_SEL86_MASK (0xFFU)

#define	XBARA_SEL43_SEL86_SHIFT (0U)

#define	XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)

#define	XBARA_SEL43_SEL87_MASK (0xFF00U)

#define	XBARA_SEL43_SEL87_SHIFT (8U)

#define	XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)

SEL44 - Crossbar A Select Register 44
#define	XBARA_SEL44_SEL88_MASK (0xFFU)

#define	XBARA_SEL44_SEL88_SHIFT (0U)

#define	XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)

#define	XBARA_SEL44_SEL89_MASK (0xFF00U)

#define	XBARA_SEL44_SEL89_SHIFT (8U)

#define	XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)

SEL45 - Crossbar A Select Register 45
#define	XBARA_SEL45_SEL90_MASK (0xFFU)

#define	XBARA_SEL45_SEL90_SHIFT (0U)

#define	XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)

#define	XBARA_SEL45_SEL91_MASK (0xFF00U)

#define	XBARA_SEL45_SEL91_SHIFT (8U)

#define	XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)

SEL46 - Crossbar A Select Register 46
#define	XBARA_SEL46_SEL92_MASK (0xFFU)

#define	XBARA_SEL46_SEL92_SHIFT (0U)

#define	XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)

#define	XBARA_SEL46_SEL93_MASK (0xFF00U)

#define	XBARA_SEL46_SEL93_SHIFT (8U)

#define	XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)

SEL47 - Crossbar A Select Register 47
#define	XBARA_SEL47_SEL94_MASK (0xFFU)

#define	XBARA_SEL47_SEL94_SHIFT (0U)

#define	XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)

#define	XBARA_SEL47_SEL95_MASK (0xFF00U)

#define	XBARA_SEL47_SEL95_SHIFT (8U)

#define	XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)

SEL48 - Crossbar A Select Register 48
#define	XBARA_SEL48_SEL96_MASK (0xFFU)

#define	XBARA_SEL48_SEL96_SHIFT (0U)

#define	XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)

#define	XBARA_SEL48_SEL97_MASK (0xFF00U)

#define	XBARA_SEL48_SEL97_SHIFT (8U)

#define	XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)

SEL49 - Crossbar A Select Register 49
#define	XBARA_SEL49_SEL98_MASK (0xFFU)

#define	XBARA_SEL49_SEL98_SHIFT (0U)

#define	XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)

#define	XBARA_SEL49_SEL99_MASK (0xFF00U)

#define	XBARA_SEL49_SEL99_SHIFT (8U)

#define	XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)

SEL50 - Crossbar A Select Register 50
#define	XBARA_SEL50_SEL100_MASK (0xFFU)

#define	XBARA_SEL50_SEL100_SHIFT (0U)

#define	XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)

#define	XBARA_SEL50_SEL101_MASK (0xFF00U)

#define	XBARA_SEL50_SEL101_SHIFT (8U)

#define	XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)

SEL51 - Crossbar A Select Register 51
#define	XBARA_SEL51_SEL102_MASK (0xFFU)

#define	XBARA_SEL51_SEL102_SHIFT (0U)

#define	XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)

#define	XBARA_SEL51_SEL103_MASK (0xFF00U)

#define	XBARA_SEL51_SEL103_SHIFT (8U)

#define	XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)

SEL52 - Crossbar A Select Register 52
#define	XBARA_SEL52_SEL104_MASK (0xFFU)

#define	XBARA_SEL52_SEL104_SHIFT (0U)

#define	XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)

#define	XBARA_SEL52_SEL105_MASK (0xFF00U)

#define	XBARA_SEL52_SEL105_SHIFT (8U)

#define	XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)

SEL53 - Crossbar A Select Register 53
#define	XBARA_SEL53_SEL106_MASK (0xFFU)

#define	XBARA_SEL53_SEL106_SHIFT (0U)

#define	XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)

#define	XBARA_SEL53_SEL107_MASK (0xFF00U)

#define	XBARA_SEL53_SEL107_SHIFT (8U)

#define	XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)

SEL54 - Crossbar A Select Register 54
#define	XBARA_SEL54_SEL108_MASK (0xFFU)

#define	XBARA_SEL54_SEL108_SHIFT (0U)

#define	XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)

#define	XBARA_SEL54_SEL109_MASK (0xFF00U)

#define	XBARA_SEL54_SEL109_SHIFT (8U)

#define	XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)

SEL55 - Crossbar A Select Register 55
#define	XBARA_SEL55_SEL110_MASK (0xFFU)

#define	XBARA_SEL55_SEL110_SHIFT (0U)

#define	XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)

#define	XBARA_SEL55_SEL111_MASK (0xFF00U)

#define	XBARA_SEL55_SEL111_SHIFT (8U)

#define	XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)

SEL56 - Crossbar A Select Register 56
#define	XBARA_SEL56_SEL112_MASK (0xFFU)

#define	XBARA_SEL56_SEL112_SHIFT (0U)

#define	XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)

#define	XBARA_SEL56_SEL113_MASK (0xFF00U)

#define	XBARA_SEL56_SEL113_SHIFT (8U)

#define	XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)

SEL57 - Crossbar A Select Register 57
#define	XBARA_SEL57_SEL114_MASK (0xFFU)

#define	XBARA_SEL57_SEL114_SHIFT (0U)

#define	XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)

#define	XBARA_SEL57_SEL115_MASK (0xFF00U)

#define	XBARA_SEL57_SEL115_SHIFT (8U)

#define	XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)

SEL58 - Crossbar A Select Register 58
#define	XBARA_SEL58_SEL116_MASK (0xFFU)

#define	XBARA_SEL58_SEL116_SHIFT (0U)

#define	XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)

#define	XBARA_SEL58_SEL117_MASK (0xFF00U)

#define	XBARA_SEL58_SEL117_SHIFT (8U)

#define	XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)

SEL59 - Crossbar A Select Register 59
#define	XBARA_SEL59_SEL118_MASK (0xFFU)

#define	XBARA_SEL59_SEL118_SHIFT (0U)

#define	XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)

#define	XBARA_SEL59_SEL119_MASK (0xFF00U)

#define	XBARA_SEL59_SEL119_SHIFT (8U)

#define	XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)

SEL60 - Crossbar A Select Register 60
#define	XBARA_SEL60_SEL120_MASK (0xFFU)

#define	XBARA_SEL60_SEL120_SHIFT (0U)

#define	XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)

#define	XBARA_SEL60_SEL121_MASK (0xFF00U)

#define	XBARA_SEL60_SEL121_SHIFT (8U)

#define	XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)

SEL61 - Crossbar A Select Register 61
#define	XBARA_SEL61_SEL122_MASK (0xFFU)

#define	XBARA_SEL61_SEL122_SHIFT (0U)

#define	XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)

#define	XBARA_SEL61_SEL123_MASK (0xFF00U)

#define	XBARA_SEL61_SEL123_SHIFT (8U)

#define	XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)

SEL62 - Crossbar A Select Register 62
#define	XBARA_SEL62_SEL124_MASK (0xFFU)

#define	XBARA_SEL62_SEL124_SHIFT (0U)

#define	XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)

#define	XBARA_SEL62_SEL125_MASK (0xFF00U)

#define	XBARA_SEL62_SEL125_SHIFT (8U)

#define	XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)

SEL63 - Crossbar A Select Register 63
#define	XBARA_SEL63_SEL126_MASK (0xFFU)

#define	XBARA_SEL63_SEL126_SHIFT (0U)

#define	XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)

#define	XBARA_SEL63_SEL127_MASK (0xFF00U)

#define	XBARA_SEL63_SEL127_SHIFT (8U)

#define	XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)

SEL64 - Crossbar A Select Register 64
#define	XBARA_SEL64_SEL128_MASK (0xFFU)

#define	XBARA_SEL64_SEL128_SHIFT (0U)

#define	XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)

#define	XBARA_SEL64_SEL129_MASK (0xFF00U)

#define	XBARA_SEL64_SEL129_SHIFT (8U)

#define	XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)

SEL65 - Crossbar A Select Register 65
#define	XBARA_SEL65_SEL130_MASK (0xFFU)

#define	XBARA_SEL65_SEL130_SHIFT (0U)

#define	XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)

#define	XBARA_SEL65_SEL131_MASK (0xFF00U)

#define	XBARA_SEL65_SEL131_SHIFT (8U)

#define	XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)

SEL66 - Crossbar A Select Register 66
#define	XBARA_SEL66_SEL132_MASK (0xFFU)

#define	XBARA_SEL66_SEL132_SHIFT (0U)

#define	XBARA_SEL66_SEL132(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL132_SHIFT)) & XBARA_SEL66_SEL132_MASK)

#define	XBARA_SEL66_SEL133_MASK (0xFF00U)

#define	XBARA_SEL66_SEL133_SHIFT (8U)

#define	XBARA_SEL66_SEL133(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL133_SHIFT)) & XBARA_SEL66_SEL133_MASK)

SEL67 - Crossbar A Select Register 67
#define	XBARA_SEL67_SEL134_MASK (0xFFU)

#define	XBARA_SEL67_SEL134_SHIFT (0U)

#define	XBARA_SEL67_SEL134(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL134_SHIFT)) & XBARA_SEL67_SEL134_MASK)

#define	XBARA_SEL67_SEL135_MASK (0xFF00U)

#define	XBARA_SEL67_SEL135_SHIFT (8U)

#define	XBARA_SEL67_SEL135(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL135_SHIFT)) & XBARA_SEL67_SEL135_MASK)

SEL68 - Crossbar A Select Register 68
#define	XBARA_SEL68_SEL136_MASK (0xFFU)

#define	XBARA_SEL68_SEL136_SHIFT (0U)

#define	XBARA_SEL68_SEL136(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL136_SHIFT)) & XBARA_SEL68_SEL136_MASK)

#define	XBARA_SEL68_SEL137_MASK (0xFF00U)

#define	XBARA_SEL68_SEL137_SHIFT (8U)

#define	XBARA_SEL68_SEL137(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL137_SHIFT)) & XBARA_SEL68_SEL137_MASK)

SEL69 - Crossbar A Select Register 69
#define	XBARA_SEL69_SEL138_MASK (0xFFU)

#define	XBARA_SEL69_SEL138_SHIFT (0U)

#define	XBARA_SEL69_SEL138(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL138_SHIFT)) & XBARA_SEL69_SEL138_MASK)

#define	XBARA_SEL69_SEL139_MASK (0xFF00U)

#define	XBARA_SEL69_SEL139_SHIFT (8U)

#define	XBARA_SEL69_SEL139(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL139_SHIFT)) & XBARA_SEL69_SEL139_MASK)

SEL70 - Crossbar A Select Register 70
#define	XBARA_SEL70_SEL140_MASK (0xFFU)

#define	XBARA_SEL70_SEL140_SHIFT (0U)

#define	XBARA_SEL70_SEL140(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL140_SHIFT)) & XBARA_SEL70_SEL140_MASK)

#define	XBARA_SEL70_SEL141_MASK (0xFF00U)

#define	XBARA_SEL70_SEL141_SHIFT (8U)

#define	XBARA_SEL70_SEL141(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL141_SHIFT)) & XBARA_SEL70_SEL141_MASK)

SEL71 - Crossbar A Select Register 71
#define	XBARA_SEL71_SEL142_MASK (0xFFU)

#define	XBARA_SEL71_SEL142_SHIFT (0U)

#define	XBARA_SEL71_SEL142(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL142_SHIFT)) & XBARA_SEL71_SEL142_MASK)

#define	XBARA_SEL71_SEL143_MASK (0xFF00U)

#define	XBARA_SEL71_SEL143_SHIFT (8U)

#define	XBARA_SEL71_SEL143(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL143_SHIFT)) & XBARA_SEL71_SEL143_MASK)

SEL72 - Crossbar A Select Register 72
#define	XBARA_SEL72_SEL144_MASK (0xFFU)

#define	XBARA_SEL72_SEL144_SHIFT (0U)

#define	XBARA_SEL72_SEL144(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL144_SHIFT)) & XBARA_SEL72_SEL144_MASK)

#define	XBARA_SEL72_SEL145_MASK (0xFF00U)

#define	XBARA_SEL72_SEL145_SHIFT (8U)

#define	XBARA_SEL72_SEL145(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL145_SHIFT)) & XBARA_SEL72_SEL145_MASK)

SEL73 - Crossbar A Select Register 73
#define	XBARA_SEL73_SEL146_MASK (0xFFU)

#define	XBARA_SEL73_SEL146_SHIFT (0U)

#define	XBARA_SEL73_SEL146(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL146_SHIFT)) & XBARA_SEL73_SEL146_MASK)

#define	XBARA_SEL73_SEL147_MASK (0xFF00U)

#define	XBARA_SEL73_SEL147_SHIFT (8U)

#define	XBARA_SEL73_SEL147(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL147_SHIFT)) & XBARA_SEL73_SEL147_MASK)

SEL74 - Crossbar A Select Register 74
#define	XBARA_SEL74_SEL148_MASK (0xFFU)

#define	XBARA_SEL74_SEL148_SHIFT (0U)

#define	XBARA_SEL74_SEL148(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL148_SHIFT)) & XBARA_SEL74_SEL148_MASK)

#define	XBARA_SEL74_SEL149_MASK (0xFF00U)

#define	XBARA_SEL74_SEL149_SHIFT (8U)

#define	XBARA_SEL74_SEL149(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL149_SHIFT)) & XBARA_SEL74_SEL149_MASK)

SEL75 - Crossbar A Select Register 75
#define	XBARA_SEL75_SEL150_MASK (0xFFU)

#define	XBARA_SEL75_SEL150_SHIFT (0U)

#define	XBARA_SEL75_SEL150(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL150_SHIFT)) & XBARA_SEL75_SEL150_MASK)

#define	XBARA_SEL75_SEL151_MASK (0xFF00U)

#define	XBARA_SEL75_SEL151_SHIFT (8U)

#define	XBARA_SEL75_SEL151(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL151_SHIFT)) & XBARA_SEL75_SEL151_MASK)

SEL76 - Crossbar A Select Register 76
#define	XBARA_SEL76_SEL152_MASK (0xFFU)

#define	XBARA_SEL76_SEL152_SHIFT (0U)

#define	XBARA_SEL76_SEL152(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL152_SHIFT)) & XBARA_SEL76_SEL152_MASK)

#define	XBARA_SEL76_SEL153_MASK (0xFF00U)

#define	XBARA_SEL76_SEL153_SHIFT (8U)

#define	XBARA_SEL76_SEL153(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL153_SHIFT)) & XBARA_SEL76_SEL153_MASK)

SEL77 - Crossbar A Select Register 77
#define	XBARA_SEL77_SEL154_MASK (0xFFU)

#define	XBARA_SEL77_SEL154_SHIFT (0U)

#define	XBARA_SEL77_SEL154(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL154_SHIFT)) & XBARA_SEL77_SEL154_MASK)

#define	XBARA_SEL77_SEL155_MASK (0xFF00U)

#define	XBARA_SEL77_SEL155_SHIFT (8U)

#define	XBARA_SEL77_SEL155(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL155_SHIFT)) & XBARA_SEL77_SEL155_MASK)

SEL78 - Crossbar A Select Register 78
#define	XBARA_SEL78_SEL156_MASK (0xFFU)

#define	XBARA_SEL78_SEL156_SHIFT (0U)

#define	XBARA_SEL78_SEL156(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL156_SHIFT)) & XBARA_SEL78_SEL156_MASK)

#define	XBARA_SEL78_SEL157_MASK (0xFF00U)

#define	XBARA_SEL78_SEL157_SHIFT (8U)

#define	XBARA_SEL78_SEL157(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL157_SHIFT)) & XBARA_SEL78_SEL157_MASK)

SEL79 - Crossbar A Select Register 79
#define	XBARA_SEL79_SEL158_MASK (0xFFU)

#define	XBARA_SEL79_SEL158_SHIFT (0U)

#define	XBARA_SEL79_SEL158(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL158_SHIFT)) & XBARA_SEL79_SEL158_MASK)

#define	XBARA_SEL79_SEL159_MASK (0xFF00U)

#define	XBARA_SEL79_SEL159_SHIFT (8U)

#define	XBARA_SEL79_SEL159(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL159_SHIFT)) & XBARA_SEL79_SEL159_MASK)

SEL80 - Crossbar A Select Register 80
#define	XBARA_SEL80_SEL160_MASK (0xFFU)

#define	XBARA_SEL80_SEL160_SHIFT (0U)

#define	XBARA_SEL80_SEL160(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL160_SHIFT)) & XBARA_SEL80_SEL160_MASK)

#define	XBARA_SEL80_SEL161_MASK (0xFF00U)

#define	XBARA_SEL80_SEL161_SHIFT (8U)

#define	XBARA_SEL80_SEL161(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL161_SHIFT)) & XBARA_SEL80_SEL161_MASK)

SEL81 - Crossbar A Select Register 81
#define	XBARA_SEL81_SEL162_MASK (0xFFU)

#define	XBARA_SEL81_SEL162_SHIFT (0U)

#define	XBARA_SEL81_SEL162(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL162_SHIFT)) & XBARA_SEL81_SEL162_MASK)

#define	XBARA_SEL81_SEL163_MASK (0xFF00U)

#define	XBARA_SEL81_SEL163_SHIFT (8U)

#define	XBARA_SEL81_SEL163(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL163_SHIFT)) & XBARA_SEL81_SEL163_MASK)

SEL82 - Crossbar A Select Register 82
#define	XBARA_SEL82_SEL164_MASK (0xFFU)

#define	XBARA_SEL82_SEL164_SHIFT (0U)

#define	XBARA_SEL82_SEL164(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL164_SHIFT)) & XBARA_SEL82_SEL164_MASK)

#define	XBARA_SEL82_SEL165_MASK (0xFF00U)

#define	XBARA_SEL82_SEL165_SHIFT (8U)

#define	XBARA_SEL82_SEL165(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL165_SHIFT)) & XBARA_SEL82_SEL165_MASK)

SEL83 - Crossbar A Select Register 83
#define	XBARA_SEL83_SEL166_MASK (0xFFU)

#define	XBARA_SEL83_SEL166_SHIFT (0U)

#define	XBARA_SEL83_SEL166(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL166_SHIFT)) & XBARA_SEL83_SEL166_MASK)

#define	XBARA_SEL83_SEL167_MASK (0xFF00U)

#define	XBARA_SEL83_SEL167_SHIFT (8U)

#define	XBARA_SEL83_SEL167(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL167_SHIFT)) & XBARA_SEL83_SEL167_MASK)

SEL84 - Crossbar A Select Register 84
#define	XBARA_SEL84_SEL168_MASK (0xFFU)

#define	XBARA_SEL84_SEL168_SHIFT (0U)

#define	XBARA_SEL84_SEL168(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL168_SHIFT)) & XBARA_SEL84_SEL168_MASK)

#define	XBARA_SEL84_SEL169_MASK (0xFF00U)

#define	XBARA_SEL84_SEL169_SHIFT (8U)

#define	XBARA_SEL84_SEL169(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL169_SHIFT)) & XBARA_SEL84_SEL169_MASK)

SEL85 - Crossbar A Select Register 85
#define	XBARA_SEL85_SEL170_MASK (0xFFU)

#define	XBARA_SEL85_SEL170_SHIFT (0U)

#define	XBARA_SEL85_SEL170(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL170_SHIFT)) & XBARA_SEL85_SEL170_MASK)

#define	XBARA_SEL85_SEL171_MASK (0xFF00U)

#define	XBARA_SEL85_SEL171_SHIFT (8U)

#define	XBARA_SEL85_SEL171(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL171_SHIFT)) & XBARA_SEL85_SEL171_MASK)

SEL86 - Crossbar A Select Register 86
#define	XBARA_SEL86_SEL172_MASK (0xFFU)

#define	XBARA_SEL86_SEL172_SHIFT (0U)

#define	XBARA_SEL86_SEL172(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL172_SHIFT)) & XBARA_SEL86_SEL172_MASK)

#define	XBARA_SEL86_SEL173_MASK (0xFF00U)

#define	XBARA_SEL86_SEL173_SHIFT (8U)

#define	XBARA_SEL86_SEL173(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL173_SHIFT)) & XBARA_SEL86_SEL173_MASK)

SEL87 - Crossbar A Select Register 87
#define	XBARA_SEL87_SEL174_MASK (0xFFU)

#define	XBARA_SEL87_SEL174_SHIFT (0U)

#define	XBARA_SEL87_SEL174(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL174_SHIFT)) & XBARA_SEL87_SEL174_MASK)

#define	XBARA_SEL87_SEL175_MASK (0xFF00U)

#define	XBARA_SEL87_SEL175_SHIFT (8U)

#define	XBARA_SEL87_SEL175(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL175_SHIFT)) & XBARA_SEL87_SEL175_MASK)

CTRL0 - Crossbar A Control Register 0
#define	XBARA_CTRL0_DEN0_MASK (0x1U)

#define	XBARA_CTRL0_DEN0_SHIFT (0U)

#define	XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)

#define	XBARA_CTRL0_IEN0_MASK (0x2U)

#define	XBARA_CTRL0_IEN0_SHIFT (1U)

#define	XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)

#define	XBARA_CTRL0_EDGE0_MASK (0xCU)

#define	XBARA_CTRL0_EDGE0_SHIFT (2U)

#define	XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)

#define	XBARA_CTRL0_STS0_MASK (0x10U)

#define	XBARA_CTRL0_STS0_SHIFT (4U)

#define	XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)

#define	XBARA_CTRL0_DEN1_MASK (0x100U)

#define	XBARA_CTRL0_DEN1_SHIFT (8U)

#define	XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)

#define	XBARA_CTRL0_IEN1_MASK (0x200U)

#define	XBARA_CTRL0_IEN1_SHIFT (9U)

#define	XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)

#define	XBARA_CTRL0_EDGE1_MASK (0xC00U)

#define	XBARA_CTRL0_EDGE1_SHIFT (10U)

#define	XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)

#define	XBARA_CTRL0_STS1_MASK (0x1000U)

#define	XBARA_CTRL0_STS1_SHIFT (12U)

#define	XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)

CTRL1 - Crossbar A Control Register 1
#define	XBARA_CTRL1_DEN2_MASK (0x1U)

#define	XBARA_CTRL1_DEN2_SHIFT (0U)

#define	XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)

#define	XBARA_CTRL1_IEN2_MASK (0x2U)

#define	XBARA_CTRL1_IEN2_SHIFT (1U)

#define	XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)

#define	XBARA_CTRL1_EDGE2_MASK (0xCU)

#define	XBARA_CTRL1_EDGE2_SHIFT (2U)

#define	XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)

#define	XBARA_CTRL1_STS2_MASK (0x10U)

#define	XBARA_CTRL1_STS2_SHIFT (4U)

#define	XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)

#define	XBARA_CTRL1_DEN3_MASK (0x100U)

#define	XBARA_CTRL1_DEN3_SHIFT (8U)

#define	XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)

#define	XBARA_CTRL1_IEN3_MASK (0x200U)

#define	XBARA_CTRL1_IEN3_SHIFT (9U)

#define	XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)

#define	XBARA_CTRL1_EDGE3_MASK (0xC00U)

#define	XBARA_CTRL1_EDGE3_SHIFT (10U)

#define	XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)

#define	XBARA_CTRL1_STS3_MASK (0x1000U)

#define	XBARA_CTRL1_STS3_SHIFT (12U)

#define	XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)

SEL0 - Crossbar A Select Register 0
#define	XBARA_SEL0_SEL0_MASK (0xFFU)

#define	XBARA_SEL0_SEL0_SHIFT (0U)

#define	XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)

#define	XBARA_SEL0_SEL1_MASK (0xFF00U)

#define	XBARA_SEL0_SEL1_SHIFT (8U)

#define	XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)

SEL1 - Crossbar A Select Register 1
#define	XBARA_SEL1_SEL2_MASK (0xFFU)

#define	XBARA_SEL1_SEL2_SHIFT (0U)

#define	XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)

#define	XBARA_SEL1_SEL3_MASK (0xFF00U)

#define	XBARA_SEL1_SEL3_SHIFT (8U)

#define	XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)

SEL2 - Crossbar A Select Register 2
#define	XBARA_SEL2_SEL4_MASK (0xFFU)

#define	XBARA_SEL2_SEL4_SHIFT (0U)

#define	XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)

#define	XBARA_SEL2_SEL5_MASK (0xFF00U)

#define	XBARA_SEL2_SEL5_SHIFT (8U)

#define	XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)

SEL3 - Crossbar A Select Register 3
#define	XBARA_SEL3_SEL6_MASK (0xFFU)

#define	XBARA_SEL3_SEL6_SHIFT (0U)

#define	XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)

#define	XBARA_SEL3_SEL7_MASK (0xFF00U)

#define	XBARA_SEL3_SEL7_SHIFT (8U)

#define	XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)

SEL4 - Crossbar A Select Register 4
#define	XBARA_SEL4_SEL8_MASK (0xFFU)

#define	XBARA_SEL4_SEL8_SHIFT (0U)

#define	XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)

#define	XBARA_SEL4_SEL9_MASK (0xFF00U)

#define	XBARA_SEL4_SEL9_SHIFT (8U)

#define	XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)

SEL5 - Crossbar A Select Register 5
#define	XBARA_SEL5_SEL10_MASK (0xFFU)

#define	XBARA_SEL5_SEL10_SHIFT (0U)

#define	XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)

#define	XBARA_SEL5_SEL11_MASK (0xFF00U)

#define	XBARA_SEL5_SEL11_SHIFT (8U)

#define	XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)

SEL6 - Crossbar A Select Register 6
#define	XBARA_SEL6_SEL12_MASK (0xFFU)

#define	XBARA_SEL6_SEL12_SHIFT (0U)

#define	XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)

#define	XBARA_SEL6_SEL13_MASK (0xFF00U)

#define	XBARA_SEL6_SEL13_SHIFT (8U)

#define	XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)

SEL7 - Crossbar A Select Register 7
#define	XBARA_SEL7_SEL14_MASK (0xFFU)

#define	XBARA_SEL7_SEL14_SHIFT (0U)

#define	XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)

#define	XBARA_SEL7_SEL15_MASK (0xFF00U)

#define	XBARA_SEL7_SEL15_SHIFT (8U)

#define	XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)

SEL8 - Crossbar A Select Register 8
#define	XBARA_SEL8_SEL16_MASK (0xFFU)

#define	XBARA_SEL8_SEL16_SHIFT (0U)

#define	XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)

#define	XBARA_SEL8_SEL17_MASK (0xFF00U)

#define	XBARA_SEL8_SEL17_SHIFT (8U)

#define	XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)

SEL9 - Crossbar A Select Register 9
#define	XBARA_SEL9_SEL18_MASK (0xFFU)

#define	XBARA_SEL9_SEL18_SHIFT (0U)

#define	XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)

#define	XBARA_SEL9_SEL19_MASK (0xFF00U)

#define	XBARA_SEL9_SEL19_SHIFT (8U)

#define	XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)

SEL10 - Crossbar A Select Register 10
#define	XBARA_SEL10_SEL20_MASK (0xFFU)

#define	XBARA_SEL10_SEL20_SHIFT (0U)

#define	XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)

#define	XBARA_SEL10_SEL21_MASK (0xFF00U)

#define	XBARA_SEL10_SEL21_SHIFT (8U)

#define	XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)

SEL11 - Crossbar A Select Register 11
#define	XBARA_SEL11_SEL22_MASK (0xFFU)

#define	XBARA_SEL11_SEL22_SHIFT (0U)

#define	XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)

#define	XBARA_SEL11_SEL23_MASK (0xFF00U)

#define	XBARA_SEL11_SEL23_SHIFT (8U)

#define	XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)

SEL12 - Crossbar A Select Register 12
#define	XBARA_SEL12_SEL24_MASK (0xFFU)

#define	XBARA_SEL12_SEL24_SHIFT (0U)

#define	XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)

#define	XBARA_SEL12_SEL25_MASK (0xFF00U)

#define	XBARA_SEL12_SEL25_SHIFT (8U)

#define	XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)

SEL13 - Crossbar A Select Register 13
#define	XBARA_SEL13_SEL26_MASK (0xFFU)

#define	XBARA_SEL13_SEL26_SHIFT (0U)

#define	XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)

#define	XBARA_SEL13_SEL27_MASK (0xFF00U)

#define	XBARA_SEL13_SEL27_SHIFT (8U)

#define	XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)

SEL14 - Crossbar A Select Register 14
#define	XBARA_SEL14_SEL28_MASK (0xFFU)

#define	XBARA_SEL14_SEL28_SHIFT (0U)

#define	XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)

#define	XBARA_SEL14_SEL29_MASK (0xFF00U)

#define	XBARA_SEL14_SEL29_SHIFT (8U)

#define	XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)

SEL15 - Crossbar A Select Register 15
#define	XBARA_SEL15_SEL30_MASK (0xFFU)

#define	XBARA_SEL15_SEL30_SHIFT (0U)

#define	XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)

#define	XBARA_SEL15_SEL31_MASK (0xFF00U)

#define	XBARA_SEL15_SEL31_SHIFT (8U)

#define	XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)

SEL16 - Crossbar A Select Register 16
#define	XBARA_SEL16_SEL32_MASK (0xFFU)

#define	XBARA_SEL16_SEL32_SHIFT (0U)

#define	XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)

#define	XBARA_SEL16_SEL33_MASK (0xFF00U)

#define	XBARA_SEL16_SEL33_SHIFT (8U)

#define	XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)

SEL17 - Crossbar A Select Register 17
#define	XBARA_SEL17_SEL34_MASK (0xFFU)

#define	XBARA_SEL17_SEL34_SHIFT (0U)

#define	XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)

#define	XBARA_SEL17_SEL35_MASK (0xFF00U)

#define	XBARA_SEL17_SEL35_SHIFT (8U)

#define	XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)

SEL18 - Crossbar A Select Register 18
#define	XBARA_SEL18_SEL36_MASK (0xFFU)

#define	XBARA_SEL18_SEL36_SHIFT (0U)

#define	XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)

#define	XBARA_SEL18_SEL37_MASK (0xFF00U)

#define	XBARA_SEL18_SEL37_SHIFT (8U)

#define	XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)

SEL19 - Crossbar A Select Register 19
#define	XBARA_SEL19_SEL38_MASK (0xFFU)

#define	XBARA_SEL19_SEL38_SHIFT (0U)

#define	XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)

#define	XBARA_SEL19_SEL39_MASK (0xFF00U)

#define	XBARA_SEL19_SEL39_SHIFT (8U)

#define	XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)

SEL20 - Crossbar A Select Register 20
#define	XBARA_SEL20_SEL40_MASK (0xFFU)

#define	XBARA_SEL20_SEL40_SHIFT (0U)

#define	XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)

#define	XBARA_SEL20_SEL41_MASK (0xFF00U)

#define	XBARA_SEL20_SEL41_SHIFT (8U)

#define	XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)

SEL21 - Crossbar A Select Register 21
#define	XBARA_SEL21_SEL42_MASK (0xFFU)

#define	XBARA_SEL21_SEL42_SHIFT (0U)

#define	XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)

#define	XBARA_SEL21_SEL43_MASK (0xFF00U)

#define	XBARA_SEL21_SEL43_SHIFT (8U)

#define	XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)

SEL22 - Crossbar A Select Register 22
#define	XBARA_SEL22_SEL44_MASK (0xFFU)

#define	XBARA_SEL22_SEL44_SHIFT (0U)

#define	XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)

#define	XBARA_SEL22_SEL45_MASK (0xFF00U)

#define	XBARA_SEL22_SEL45_SHIFT (8U)

#define	XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)

SEL23 - Crossbar A Select Register 23
#define	XBARA_SEL23_SEL46_MASK (0xFFU)

#define	XBARA_SEL23_SEL46_SHIFT (0U)

#define	XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)

#define	XBARA_SEL23_SEL47_MASK (0xFF00U)

#define	XBARA_SEL23_SEL47_SHIFT (8U)

#define	XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)

SEL24 - Crossbar A Select Register 24
#define	XBARA_SEL24_SEL48_MASK (0xFFU)

#define	XBARA_SEL24_SEL48_SHIFT (0U)

#define	XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)

#define	XBARA_SEL24_SEL49_MASK (0xFF00U)

#define	XBARA_SEL24_SEL49_SHIFT (8U)

#define	XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)

SEL25 - Crossbar A Select Register 25
#define	XBARA_SEL25_SEL50_MASK (0xFFU)

#define	XBARA_SEL25_SEL50_SHIFT (0U)

#define	XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)

#define	XBARA_SEL25_SEL51_MASK (0xFF00U)

#define	XBARA_SEL25_SEL51_SHIFT (8U)

#define	XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)

SEL26 - Crossbar A Select Register 26
#define	XBARA_SEL26_SEL52_MASK (0xFFU)

#define	XBARA_SEL26_SEL52_SHIFT (0U)

#define	XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)

#define	XBARA_SEL26_SEL53_MASK (0xFF00U)

#define	XBARA_SEL26_SEL53_SHIFT (8U)

#define	XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)

SEL27 - Crossbar A Select Register 27
#define	XBARA_SEL27_SEL54_MASK (0xFFU)

#define	XBARA_SEL27_SEL54_SHIFT (0U)

#define	XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)

#define	XBARA_SEL27_SEL55_MASK (0xFF00U)

#define	XBARA_SEL27_SEL55_SHIFT (8U)

#define	XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)

SEL28 - Crossbar A Select Register 28
#define	XBARA_SEL28_SEL56_MASK (0xFFU)

#define	XBARA_SEL28_SEL56_SHIFT (0U)

#define	XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)

#define	XBARA_SEL28_SEL57_MASK (0xFF00U)

#define	XBARA_SEL28_SEL57_SHIFT (8U)

#define	XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)

SEL29 - Crossbar A Select Register 29
#define	XBARA_SEL29_SEL58_MASK (0xFFU)

#define	XBARA_SEL29_SEL58_SHIFT (0U)

#define	XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)

#define	XBARA_SEL29_SEL59_MASK (0xFF00U)

#define	XBARA_SEL29_SEL59_SHIFT (8U)

#define	XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)

SEL30 - Crossbar A Select Register 30
#define	XBARA_SEL30_SEL60_MASK (0xFFU)

#define	XBARA_SEL30_SEL60_SHIFT (0U)

#define	XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)

#define	XBARA_SEL30_SEL61_MASK (0xFF00U)

#define	XBARA_SEL30_SEL61_SHIFT (8U)

#define	XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)

SEL31 - Crossbar A Select Register 31
#define	XBARA_SEL31_SEL62_MASK (0xFFU)

#define	XBARA_SEL31_SEL62_SHIFT (0U)

#define	XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)

#define	XBARA_SEL31_SEL63_MASK (0xFF00U)

#define	XBARA_SEL31_SEL63_SHIFT (8U)

#define	XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)

SEL32 - Crossbar A Select Register 32
#define	XBARA_SEL32_SEL64_MASK (0xFFU)

#define	XBARA_SEL32_SEL64_SHIFT (0U)

#define	XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)

#define	XBARA_SEL32_SEL65_MASK (0xFF00U)

#define	XBARA_SEL32_SEL65_SHIFT (8U)

#define	XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)

SEL33 - Crossbar A Select Register 33
#define	XBARA_SEL33_SEL66_MASK (0xFFU)

#define	XBARA_SEL33_SEL66_SHIFT (0U)

#define	XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)

#define	XBARA_SEL33_SEL67_MASK (0xFF00U)

#define	XBARA_SEL33_SEL67_SHIFT (8U)

#define	XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)

SEL34 - Crossbar A Select Register 34
#define	XBARA_SEL34_SEL68_MASK (0xFFU)

#define	XBARA_SEL34_SEL68_SHIFT (0U)

#define	XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)

#define	XBARA_SEL34_SEL69_MASK (0xFF00U)

#define	XBARA_SEL34_SEL69_SHIFT (8U)

#define	XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)

SEL35 - Crossbar A Select Register 35
#define	XBARA_SEL35_SEL70_MASK (0xFFU)

#define	XBARA_SEL35_SEL70_SHIFT (0U)

#define	XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)

#define	XBARA_SEL35_SEL71_MASK (0xFF00U)

#define	XBARA_SEL35_SEL71_SHIFT (8U)

#define	XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)

SEL36 - Crossbar A Select Register 36
#define	XBARA_SEL36_SEL72_MASK (0xFFU)

#define	XBARA_SEL36_SEL72_SHIFT (0U)

#define	XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)

#define	XBARA_SEL36_SEL73_MASK (0xFF00U)

#define	XBARA_SEL36_SEL73_SHIFT (8U)

#define	XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)

SEL37 - Crossbar A Select Register 37
#define	XBARA_SEL37_SEL74_MASK (0xFFU)

#define	XBARA_SEL37_SEL74_SHIFT (0U)

#define	XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)

#define	XBARA_SEL37_SEL75_MASK (0xFF00U)

#define	XBARA_SEL37_SEL75_SHIFT (8U)

#define	XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)

SEL38 - Crossbar A Select Register 38
#define	XBARA_SEL38_SEL76_MASK (0xFFU)

#define	XBARA_SEL38_SEL76_SHIFT (0U)

#define	XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)

#define	XBARA_SEL38_SEL77_MASK (0xFF00U)

#define	XBARA_SEL38_SEL77_SHIFT (8U)

#define	XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)

SEL39 - Crossbar A Select Register 39
#define	XBARA_SEL39_SEL78_MASK (0xFFU)

#define	XBARA_SEL39_SEL78_SHIFT (0U)

#define	XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)

#define	XBARA_SEL39_SEL79_MASK (0xFF00U)

#define	XBARA_SEL39_SEL79_SHIFT (8U)

#define	XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)

SEL40 - Crossbar A Select Register 40
#define	XBARA_SEL40_SEL80_MASK (0xFFU)

#define	XBARA_SEL40_SEL80_SHIFT (0U)

#define	XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)

#define	XBARA_SEL40_SEL81_MASK (0xFF00U)

#define	XBARA_SEL40_SEL81_SHIFT (8U)

#define	XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)

SEL41 - Crossbar A Select Register 41
#define	XBARA_SEL41_SEL82_MASK (0xFFU)

#define	XBARA_SEL41_SEL82_SHIFT (0U)

#define	XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)

#define	XBARA_SEL41_SEL83_MASK (0xFF00U)

#define	XBARA_SEL41_SEL83_SHIFT (8U)

#define	XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)

SEL42 - Crossbar A Select Register 42
#define	XBARA_SEL42_SEL84_MASK (0xFFU)

#define	XBARA_SEL42_SEL84_SHIFT (0U)

#define	XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)

#define	XBARA_SEL42_SEL85_MASK (0xFF00U)

#define	XBARA_SEL42_SEL85_SHIFT (8U)

#define	XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)

SEL43 - Crossbar A Select Register 43
#define	XBARA_SEL43_SEL86_MASK (0xFFU)

#define	XBARA_SEL43_SEL86_SHIFT (0U)

#define	XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)

#define	XBARA_SEL43_SEL87_MASK (0xFF00U)

#define	XBARA_SEL43_SEL87_SHIFT (8U)

#define	XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)

SEL44 - Crossbar A Select Register 44
#define	XBARA_SEL44_SEL88_MASK (0xFFU)

#define	XBARA_SEL44_SEL88_SHIFT (0U)

#define	XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)

#define	XBARA_SEL44_SEL89_MASK (0xFF00U)

#define	XBARA_SEL44_SEL89_SHIFT (8U)

#define	XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)

SEL45 - Crossbar A Select Register 45
#define	XBARA_SEL45_SEL90_MASK (0xFFU)

#define	XBARA_SEL45_SEL90_SHIFT (0U)

#define	XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)

#define	XBARA_SEL45_SEL91_MASK (0xFF00U)

#define	XBARA_SEL45_SEL91_SHIFT (8U)

#define	XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)

SEL46 - Crossbar A Select Register 46
#define	XBARA_SEL46_SEL92_MASK (0xFFU)

#define	XBARA_SEL46_SEL92_SHIFT (0U)

#define	XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)

#define	XBARA_SEL46_SEL93_MASK (0xFF00U)

#define	XBARA_SEL46_SEL93_SHIFT (8U)

#define	XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)

SEL47 - Crossbar A Select Register 47
#define	XBARA_SEL47_SEL94_MASK (0xFFU)

#define	XBARA_SEL47_SEL94_SHIFT (0U)

#define	XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)

#define	XBARA_SEL47_SEL95_MASK (0xFF00U)

#define	XBARA_SEL47_SEL95_SHIFT (8U)

#define	XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)

SEL48 - Crossbar A Select Register 48
#define	XBARA_SEL48_SEL96_MASK (0xFFU)

#define	XBARA_SEL48_SEL96_SHIFT (0U)

#define	XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)

#define	XBARA_SEL48_SEL97_MASK (0xFF00U)

#define	XBARA_SEL48_SEL97_SHIFT (8U)

#define	XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)

SEL49 - Crossbar A Select Register 49
#define	XBARA_SEL49_SEL98_MASK (0xFFU)

#define	XBARA_SEL49_SEL98_SHIFT (0U)

#define	XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)

#define	XBARA_SEL49_SEL99_MASK (0xFF00U)

#define	XBARA_SEL49_SEL99_SHIFT (8U)

#define	XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)

SEL50 - Crossbar A Select Register 50
#define	XBARA_SEL50_SEL100_MASK (0xFFU)

#define	XBARA_SEL50_SEL100_SHIFT (0U)

#define	XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)

#define	XBARA_SEL50_SEL101_MASK (0xFF00U)

#define	XBARA_SEL50_SEL101_SHIFT (8U)

#define	XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)

SEL51 - Crossbar A Select Register 51
#define	XBARA_SEL51_SEL102_MASK (0xFFU)

#define	XBARA_SEL51_SEL102_SHIFT (0U)

#define	XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)

#define	XBARA_SEL51_SEL103_MASK (0xFF00U)

#define	XBARA_SEL51_SEL103_SHIFT (8U)

#define	XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)

SEL52 - Crossbar A Select Register 52
#define	XBARA_SEL52_SEL104_MASK (0xFFU)

#define	XBARA_SEL52_SEL104_SHIFT (0U)

#define	XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)

#define	XBARA_SEL52_SEL105_MASK (0xFF00U)

#define	XBARA_SEL52_SEL105_SHIFT (8U)

#define	XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)

SEL53 - Crossbar A Select Register 53
#define	XBARA_SEL53_SEL106_MASK (0xFFU)

#define	XBARA_SEL53_SEL106_SHIFT (0U)

#define	XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)

#define	XBARA_SEL53_SEL107_MASK (0xFF00U)

#define	XBARA_SEL53_SEL107_SHIFT (8U)

#define	XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)

SEL54 - Crossbar A Select Register 54
#define	XBARA_SEL54_SEL108_MASK (0xFFU)

#define	XBARA_SEL54_SEL108_SHIFT (0U)

#define	XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)

#define	XBARA_SEL54_SEL109_MASK (0xFF00U)

#define	XBARA_SEL54_SEL109_SHIFT (8U)

#define	XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)

SEL55 - Crossbar A Select Register 55
#define	XBARA_SEL55_SEL110_MASK (0xFFU)

#define	XBARA_SEL55_SEL110_SHIFT (0U)

#define	XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)

#define	XBARA_SEL55_SEL111_MASK (0xFF00U)

#define	XBARA_SEL55_SEL111_SHIFT (8U)

#define	XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)

SEL56 - Crossbar A Select Register 56
#define	XBARA_SEL56_SEL112_MASK (0xFFU)

#define	XBARA_SEL56_SEL112_SHIFT (0U)

#define	XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)

#define	XBARA_SEL56_SEL113_MASK (0xFF00U)

#define	XBARA_SEL56_SEL113_SHIFT (8U)

#define	XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)

SEL57 - Crossbar A Select Register 57
#define	XBARA_SEL57_SEL114_MASK (0xFFU)

#define	XBARA_SEL57_SEL114_SHIFT (0U)

#define	XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)

#define	XBARA_SEL57_SEL115_MASK (0xFF00U)

#define	XBARA_SEL57_SEL115_SHIFT (8U)

#define	XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)

SEL58 - Crossbar A Select Register 58
#define	XBARA_SEL58_SEL116_MASK (0xFFU)

#define	XBARA_SEL58_SEL116_SHIFT (0U)

#define	XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)

#define	XBARA_SEL58_SEL117_MASK (0xFF00U)

#define	XBARA_SEL58_SEL117_SHIFT (8U)

#define	XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)

SEL59 - Crossbar A Select Register 59
#define	XBARA_SEL59_SEL118_MASK (0xFFU)

#define	XBARA_SEL59_SEL118_SHIFT (0U)

#define	XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)

#define	XBARA_SEL59_SEL119_MASK (0xFF00U)

#define	XBARA_SEL59_SEL119_SHIFT (8U)

#define	XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)

SEL60 - Crossbar A Select Register 60
#define	XBARA_SEL60_SEL120_MASK (0xFFU)

#define	XBARA_SEL60_SEL120_SHIFT (0U)

#define	XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)

#define	XBARA_SEL60_SEL121_MASK (0xFF00U)

#define	XBARA_SEL60_SEL121_SHIFT (8U)

#define	XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)

SEL61 - Crossbar A Select Register 61
#define	XBARA_SEL61_SEL122_MASK (0xFFU)

#define	XBARA_SEL61_SEL122_SHIFT (0U)

#define	XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)

#define	XBARA_SEL61_SEL123_MASK (0xFF00U)

#define	XBARA_SEL61_SEL123_SHIFT (8U)

#define	XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)

SEL62 - Crossbar A Select Register 62
#define	XBARA_SEL62_SEL124_MASK (0xFFU)

#define	XBARA_SEL62_SEL124_SHIFT (0U)

#define	XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)

#define	XBARA_SEL62_SEL125_MASK (0xFF00U)

#define	XBARA_SEL62_SEL125_SHIFT (8U)

#define	XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)

SEL63 - Crossbar A Select Register 63
#define	XBARA_SEL63_SEL126_MASK (0xFFU)

#define	XBARA_SEL63_SEL126_SHIFT (0U)

#define	XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)

#define	XBARA_SEL63_SEL127_MASK (0xFF00U)

#define	XBARA_SEL63_SEL127_SHIFT (8U)

#define	XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)

SEL64 - Crossbar A Select Register 64
#define	XBARA_SEL64_SEL128_MASK (0xFFU)

#define	XBARA_SEL64_SEL128_SHIFT (0U)

#define	XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)

#define	XBARA_SEL64_SEL129_MASK (0xFF00U)

#define	XBARA_SEL64_SEL129_SHIFT (8U)

#define	XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)

SEL65 - Crossbar A Select Register 65
#define	XBARA_SEL65_SEL130_MASK (0xFFU)

#define	XBARA_SEL65_SEL130_SHIFT (0U)

#define	XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)

#define	XBARA_SEL65_SEL131_MASK (0xFF00U)

#define	XBARA_SEL65_SEL131_SHIFT (8U)

#define	XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)

SEL66 - Crossbar A Select Register 66
#define	XBARA_SEL66_SEL132_MASK (0xFFU)

#define	XBARA_SEL66_SEL132_SHIFT (0U)

#define	XBARA_SEL66_SEL132(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL132_SHIFT)) & XBARA_SEL66_SEL132_MASK)

#define	XBARA_SEL66_SEL133_MASK (0xFF00U)

#define	XBARA_SEL66_SEL133_SHIFT (8U)

#define	XBARA_SEL66_SEL133(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL133_SHIFT)) & XBARA_SEL66_SEL133_MASK)

SEL67 - Crossbar A Select Register 67
#define	XBARA_SEL67_SEL134_MASK (0xFFU)

#define	XBARA_SEL67_SEL134_SHIFT (0U)

#define	XBARA_SEL67_SEL134(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL134_SHIFT)) & XBARA_SEL67_SEL134_MASK)

#define	XBARA_SEL67_SEL135_MASK (0xFF00U)

#define	XBARA_SEL67_SEL135_SHIFT (8U)

#define	XBARA_SEL67_SEL135(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL135_SHIFT)) & XBARA_SEL67_SEL135_MASK)

SEL68 - Crossbar A Select Register 68
#define	XBARA_SEL68_SEL136_MASK (0xFFU)

#define	XBARA_SEL68_SEL136_SHIFT (0U)

#define	XBARA_SEL68_SEL136(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL136_SHIFT)) & XBARA_SEL68_SEL136_MASK)

#define	XBARA_SEL68_SEL137_MASK (0xFF00U)

#define	XBARA_SEL68_SEL137_SHIFT (8U)

#define	XBARA_SEL68_SEL137(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL137_SHIFT)) & XBARA_SEL68_SEL137_MASK)

SEL69 - Crossbar A Select Register 69
#define	XBARA_SEL69_SEL138_MASK (0xFFU)

#define	XBARA_SEL69_SEL138_SHIFT (0U)

#define	XBARA_SEL69_SEL138(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL138_SHIFT)) & XBARA_SEL69_SEL138_MASK)

#define	XBARA_SEL69_SEL139_MASK (0xFF00U)

#define	XBARA_SEL69_SEL139_SHIFT (8U)

#define	XBARA_SEL69_SEL139(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL139_SHIFT)) & XBARA_SEL69_SEL139_MASK)

SEL70 - Crossbar A Select Register 70
#define	XBARA_SEL70_SEL140_MASK (0xFFU)

#define	XBARA_SEL70_SEL140_SHIFT (0U)

#define	XBARA_SEL70_SEL140(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL140_SHIFT)) & XBARA_SEL70_SEL140_MASK)

#define	XBARA_SEL70_SEL141_MASK (0xFF00U)

#define	XBARA_SEL70_SEL141_SHIFT (8U)

#define	XBARA_SEL70_SEL141(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL141_SHIFT)) & XBARA_SEL70_SEL141_MASK)

SEL71 - Crossbar A Select Register 71
#define	XBARA_SEL71_SEL142_MASK (0xFFU)

#define	XBARA_SEL71_SEL142_SHIFT (0U)

#define	XBARA_SEL71_SEL142(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL142_SHIFT)) & XBARA_SEL71_SEL142_MASK)

#define	XBARA_SEL71_SEL143_MASK (0xFF00U)

#define	XBARA_SEL71_SEL143_SHIFT (8U)

#define	XBARA_SEL71_SEL143(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL143_SHIFT)) & XBARA_SEL71_SEL143_MASK)

SEL72 - Crossbar A Select Register 72
#define	XBARA_SEL72_SEL144_MASK (0xFFU)

#define	XBARA_SEL72_SEL144_SHIFT (0U)

#define	XBARA_SEL72_SEL144(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL144_SHIFT)) & XBARA_SEL72_SEL144_MASK)

#define	XBARA_SEL72_SEL145_MASK (0xFF00U)

#define	XBARA_SEL72_SEL145_SHIFT (8U)

#define	XBARA_SEL72_SEL145(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL145_SHIFT)) & XBARA_SEL72_SEL145_MASK)

SEL73 - Crossbar A Select Register 73
#define	XBARA_SEL73_SEL146_MASK (0xFFU)

#define	XBARA_SEL73_SEL146_SHIFT (0U)

#define	XBARA_SEL73_SEL146(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL146_SHIFT)) & XBARA_SEL73_SEL146_MASK)

#define	XBARA_SEL73_SEL147_MASK (0xFF00U)

#define	XBARA_SEL73_SEL147_SHIFT (8U)

#define	XBARA_SEL73_SEL147(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL147_SHIFT)) & XBARA_SEL73_SEL147_MASK)

SEL74 - Crossbar A Select Register 74
#define	XBARA_SEL74_SEL148_MASK (0xFFU)

#define	XBARA_SEL74_SEL148_SHIFT (0U)

#define	XBARA_SEL74_SEL148(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL148_SHIFT)) & XBARA_SEL74_SEL148_MASK)

#define	XBARA_SEL74_SEL149_MASK (0xFF00U)

#define	XBARA_SEL74_SEL149_SHIFT (8U)

#define	XBARA_SEL74_SEL149(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL149_SHIFT)) & XBARA_SEL74_SEL149_MASK)

SEL75 - Crossbar A Select Register 75
#define	XBARA_SEL75_SEL150_MASK (0xFFU)

#define	XBARA_SEL75_SEL150_SHIFT (0U)

#define	XBARA_SEL75_SEL150(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL150_SHIFT)) & XBARA_SEL75_SEL150_MASK)

#define	XBARA_SEL75_SEL151_MASK (0xFF00U)

#define	XBARA_SEL75_SEL151_SHIFT (8U)

#define	XBARA_SEL75_SEL151(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL151_SHIFT)) & XBARA_SEL75_SEL151_MASK)

SEL76 - Crossbar A Select Register 76
#define	XBARA_SEL76_SEL152_MASK (0xFFU)

#define	XBARA_SEL76_SEL152_SHIFT (0U)

#define	XBARA_SEL76_SEL152(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL152_SHIFT)) & XBARA_SEL76_SEL152_MASK)

#define	XBARA_SEL76_SEL153_MASK (0xFF00U)

#define	XBARA_SEL76_SEL153_SHIFT (8U)

#define	XBARA_SEL76_SEL153(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL153_SHIFT)) & XBARA_SEL76_SEL153_MASK)

SEL77 - Crossbar A Select Register 77
#define	XBARA_SEL77_SEL154_MASK (0xFFU)

#define	XBARA_SEL77_SEL154_SHIFT (0U)

#define	XBARA_SEL77_SEL154(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL154_SHIFT)) & XBARA_SEL77_SEL154_MASK)

#define	XBARA_SEL77_SEL155_MASK (0xFF00U)

#define	XBARA_SEL77_SEL155_SHIFT (8U)

#define	XBARA_SEL77_SEL155(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL155_SHIFT)) & XBARA_SEL77_SEL155_MASK)

SEL78 - Crossbar A Select Register 78
#define	XBARA_SEL78_SEL156_MASK (0xFFU)

#define	XBARA_SEL78_SEL156_SHIFT (0U)

#define	XBARA_SEL78_SEL156(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL156_SHIFT)) & XBARA_SEL78_SEL156_MASK)

#define	XBARA_SEL78_SEL157_MASK (0xFF00U)

#define	XBARA_SEL78_SEL157_SHIFT (8U)

#define	XBARA_SEL78_SEL157(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL157_SHIFT)) & XBARA_SEL78_SEL157_MASK)

SEL79 - Crossbar A Select Register 79
#define	XBARA_SEL79_SEL158_MASK (0xFFU)

#define	XBARA_SEL79_SEL158_SHIFT (0U)

#define	XBARA_SEL79_SEL158(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL158_SHIFT)) & XBARA_SEL79_SEL158_MASK)

#define	XBARA_SEL79_SEL159_MASK (0xFF00U)

#define	XBARA_SEL79_SEL159_SHIFT (8U)

#define	XBARA_SEL79_SEL159(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL159_SHIFT)) & XBARA_SEL79_SEL159_MASK)

SEL80 - Crossbar A Select Register 80
#define	XBARA_SEL80_SEL160_MASK (0xFFU)

#define	XBARA_SEL80_SEL160_SHIFT (0U)

#define	XBARA_SEL80_SEL160(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL160_SHIFT)) & XBARA_SEL80_SEL160_MASK)

#define	XBARA_SEL80_SEL161_MASK (0xFF00U)

#define	XBARA_SEL80_SEL161_SHIFT (8U)

#define	XBARA_SEL80_SEL161(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL161_SHIFT)) & XBARA_SEL80_SEL161_MASK)

SEL81 - Crossbar A Select Register 81
#define	XBARA_SEL81_SEL162_MASK (0xFFU)

#define	XBARA_SEL81_SEL162_SHIFT (0U)

#define	XBARA_SEL81_SEL162(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL162_SHIFT)) & XBARA_SEL81_SEL162_MASK)

#define	XBARA_SEL81_SEL163_MASK (0xFF00U)

#define	XBARA_SEL81_SEL163_SHIFT (8U)

#define	XBARA_SEL81_SEL163(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL163_SHIFT)) & XBARA_SEL81_SEL163_MASK)

SEL82 - Crossbar A Select Register 82
#define	XBARA_SEL82_SEL164_MASK (0xFFU)

#define	XBARA_SEL82_SEL164_SHIFT (0U)

#define	XBARA_SEL82_SEL164(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL164_SHIFT)) & XBARA_SEL82_SEL164_MASK)

#define	XBARA_SEL82_SEL165_MASK (0xFF00U)

#define	XBARA_SEL82_SEL165_SHIFT (8U)

#define	XBARA_SEL82_SEL165(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL165_SHIFT)) & XBARA_SEL82_SEL165_MASK)

SEL83 - Crossbar A Select Register 83
#define	XBARA_SEL83_SEL166_MASK (0xFFU)

#define	XBARA_SEL83_SEL166_SHIFT (0U)

#define	XBARA_SEL83_SEL166(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL166_SHIFT)) & XBARA_SEL83_SEL166_MASK)

#define	XBARA_SEL83_SEL167_MASK (0xFF00U)

#define	XBARA_SEL83_SEL167_SHIFT (8U)

#define	XBARA_SEL83_SEL167(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL167_SHIFT)) & XBARA_SEL83_SEL167_MASK)

SEL84 - Crossbar A Select Register 84
#define	XBARA_SEL84_SEL168_MASK (0xFFU)

#define	XBARA_SEL84_SEL168_SHIFT (0U)

#define	XBARA_SEL84_SEL168(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL168_SHIFT)) & XBARA_SEL84_SEL168_MASK)

#define	XBARA_SEL84_SEL169_MASK (0xFF00U)

#define	XBARA_SEL84_SEL169_SHIFT (8U)

#define	XBARA_SEL84_SEL169(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL169_SHIFT)) & XBARA_SEL84_SEL169_MASK)

SEL85 - Crossbar A Select Register 85
#define	XBARA_SEL85_SEL170_MASK (0xFFU)

#define	XBARA_SEL85_SEL170_SHIFT (0U)

#define	XBARA_SEL85_SEL170(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL170_SHIFT)) & XBARA_SEL85_SEL170_MASK)

#define	XBARA_SEL85_SEL171_MASK (0xFF00U)

#define	XBARA_SEL85_SEL171_SHIFT (8U)

#define	XBARA_SEL85_SEL171(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL171_SHIFT)) & XBARA_SEL85_SEL171_MASK)

SEL86 - Crossbar A Select Register 86
#define	XBARA_SEL86_SEL172_MASK (0xFFU)

#define	XBARA_SEL86_SEL172_SHIFT (0U)

#define	XBARA_SEL86_SEL172(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL172_SHIFT)) & XBARA_SEL86_SEL172_MASK)

#define	XBARA_SEL86_SEL173_MASK (0xFF00U)

#define	XBARA_SEL86_SEL173_SHIFT (8U)

#define	XBARA_SEL86_SEL173(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL173_SHIFT)) & XBARA_SEL86_SEL173_MASK)

SEL87 - Crossbar A Select Register 87
#define	XBARA_SEL87_SEL174_MASK (0xFFU)

#define	XBARA_SEL87_SEL174_SHIFT (0U)

#define	XBARA_SEL87_SEL174(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL174_SHIFT)) & XBARA_SEL87_SEL174_MASK)

#define	XBARA_SEL87_SEL175_MASK (0xFF00U)

#define	XBARA_SEL87_SEL175_SHIFT (8U)

#define	XBARA_SEL87_SEL175(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL175_SHIFT)) & XBARA_SEL87_SEL175_MASK)

CTRL0 - Crossbar A Control Register 0
#define	XBARA_CTRL0_DEN0_MASK (0x1U)

#define	XBARA_CTRL0_DEN0_SHIFT (0U)

#define	XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)

#define	XBARA_CTRL0_IEN0_MASK (0x2U)

#define	XBARA_CTRL0_IEN0_SHIFT (1U)

#define	XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)

#define	XBARA_CTRL0_EDGE0_MASK (0xCU)

#define	XBARA_CTRL0_EDGE0_SHIFT (2U)

#define	XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)

#define	XBARA_CTRL0_STS0_MASK (0x10U)

#define	XBARA_CTRL0_STS0_SHIFT (4U)

#define	XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)

#define	XBARA_CTRL0_DEN1_MASK (0x100U)

#define	XBARA_CTRL0_DEN1_SHIFT (8U)

#define	XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)

#define	XBARA_CTRL0_IEN1_MASK (0x200U)

#define	XBARA_CTRL0_IEN1_SHIFT (9U)

#define	XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)

#define	XBARA_CTRL0_EDGE1_MASK (0xC00U)

#define	XBARA_CTRL0_EDGE1_SHIFT (10U)

#define	XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)

#define	XBARA_CTRL0_STS1_MASK (0x1000U)

#define	XBARA_CTRL0_STS1_SHIFT (12U)

#define	XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)

CTRL1 - Crossbar A Control Register 1
#define	XBARA_CTRL1_DEN2_MASK (0x1U)

#define	XBARA_CTRL1_DEN2_SHIFT (0U)

#define	XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)

#define	XBARA_CTRL1_IEN2_MASK (0x2U)

#define	XBARA_CTRL1_IEN2_SHIFT (1U)

#define	XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)

#define	XBARA_CTRL1_EDGE2_MASK (0xCU)

#define	XBARA_CTRL1_EDGE2_SHIFT (2U)

#define	XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)

#define	XBARA_CTRL1_STS2_MASK (0x10U)

#define	XBARA_CTRL1_STS2_SHIFT (4U)

#define	XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)

#define	XBARA_CTRL1_DEN3_MASK (0x100U)

#define	XBARA_CTRL1_DEN3_SHIFT (8U)

#define	XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)

#define	XBARA_CTRL1_IEN3_MASK (0x200U)

#define	XBARA_CTRL1_IEN3_SHIFT (9U)

#define	XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)

#define	XBARA_CTRL1_EDGE3_MASK (0xC00U)

#define	XBARA_CTRL1_EDGE3_SHIFT (10U)

#define	XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)

#define	XBARA_CTRL1_STS3_MASK (0x1000U)

#define	XBARA_CTRL1_STS3_SHIFT (12U)

#define	XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)

Detailed Description

Macro Definition Documentation

◆ XBARA_CTRL0_DEN0 [1/3]

#define XBARA_CTRL0_DEN0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)

DEN0 - DMA Enable for XBAR_OUT0 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL0_DEN0 [2/3]

#define XBARA_CTRL0_DEN0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)

DEN0 - DMA Enable for XBAR_OUT0 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL0_DEN0 [3/3]

#define XBARA_CTRL0_DEN0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)

DEN0 - DMA Enable for XBAR_OUT0 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL0_DEN1 [1/3]

#define XBARA_CTRL0_DEN1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)

DEN1 - DMA Enable for XBAR_OUT1 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL0_DEN1 [2/3]

#define XBARA_CTRL0_DEN1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)

DEN1 - DMA Enable for XBAR_OUT1 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL0_DEN1 [3/3]

#define XBARA_CTRL0_DEN1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)

DEN1 - DMA Enable for XBAR_OUT1 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL0_EDGE0 [1/3]

#define XBARA_CTRL0_EDGE0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)

EDGE0 - Active edge for edge detection on XBAR_OUT0 0b00..STS0 never asserts 0b01..STS0 asserts on rising edges of XBAR_OUT0 0b10..STS0 asserts on falling edges of XBAR_OUT0 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0

◆ XBARA_CTRL0_EDGE0 [2/3]

#define XBARA_CTRL0_EDGE0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)

EDGE0 - Active edge for edge detection on XBAR_OUT0 0b00..STS0 never asserts 0b01..STS0 asserts on rising edges of XBAR_OUT0 0b10..STS0 asserts on falling edges of XBAR_OUT0 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0

◆ XBARA_CTRL0_EDGE0 [3/3]

#define XBARA_CTRL0_EDGE0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)

EDGE0 - Active edge for edge detection on XBAR_OUT0 0b00..STS0 never asserts 0b01..STS0 asserts on rising edges of XBAR_OUT0 0b10..STS0 asserts on falling edges of XBAR_OUT0 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0

◆ XBARA_CTRL0_EDGE1 [1/3]

#define XBARA_CTRL0_EDGE1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)

EDGE1 - Active edge for edge detection on XBAR_OUT1 0b00..STS1 never asserts 0b01..STS1 asserts on rising edges of XBAR_OUT1 0b10..STS1 asserts on falling edges of XBAR_OUT1 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1

◆ XBARA_CTRL0_EDGE1 [2/3]

#define XBARA_CTRL0_EDGE1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)

EDGE1 - Active edge for edge detection on XBAR_OUT1 0b00..STS1 never asserts 0b01..STS1 asserts on rising edges of XBAR_OUT1 0b10..STS1 asserts on falling edges of XBAR_OUT1 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1

◆ XBARA_CTRL0_EDGE1 [3/3]

#define XBARA_CTRL0_EDGE1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)

EDGE1 - Active edge for edge detection on XBAR_OUT1 0b00..STS1 never asserts 0b01..STS1 asserts on rising edges of XBAR_OUT1 0b10..STS1 asserts on falling edges of XBAR_OUT1 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1

◆ XBARA_CTRL0_IEN0 [1/3]

#define XBARA_CTRL0_IEN0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)

IEN0 - Interrupt Enable for XBAR_OUT0 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL0_IEN0 [2/3]

#define XBARA_CTRL0_IEN0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)

IEN0 - Interrupt Enable for XBAR_OUT0 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL0_IEN0 [3/3]

#define XBARA_CTRL0_IEN0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)

IEN0 - Interrupt Enable for XBAR_OUT0 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL0_IEN1 [1/3]

#define XBARA_CTRL0_IEN1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)

IEN1 - Interrupt Enable for XBAR_OUT1 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL0_IEN1 [2/3]

#define XBARA_CTRL0_IEN1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)

IEN1 - Interrupt Enable for XBAR_OUT1 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL0_IEN1 [3/3]

#define XBARA_CTRL0_IEN1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)

IEN1 - Interrupt Enable for XBAR_OUT1 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL0_STS0 [1/3]

#define XBARA_CTRL0_STS0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)

STS0 - Edge detection status for XBAR_OUT0 0b0..Active edge not yet detected on XBAR_OUT0 0b1..Active edge detected on XBAR_OUT0

◆ XBARA_CTRL0_STS0 [2/3]

#define XBARA_CTRL0_STS0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)

STS0 - Edge detection status for XBAR_OUT0 0b0..Active edge not yet detected on XBAR_OUT0 0b1..Active edge detected on XBAR_OUT0

◆ XBARA_CTRL0_STS0 [3/3]

#define XBARA_CTRL0_STS0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)

STS0 - Edge detection status for XBAR_OUT0 0b0..Active edge not yet detected on XBAR_OUT0 0b1..Active edge detected on XBAR_OUT0

◆ XBARA_CTRL0_STS1 [1/3]

#define XBARA_CTRL0_STS1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)

STS1 - Edge detection status for XBAR_OUT1 0b0..Active edge not yet detected on XBAR_OUT1 0b1..Active edge detected on XBAR_OUT1

◆ XBARA_CTRL0_STS1 [2/3]

#define XBARA_CTRL0_STS1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)

STS1 - Edge detection status for XBAR_OUT1 0b0..Active edge not yet detected on XBAR_OUT1 0b1..Active edge detected on XBAR_OUT1

◆ XBARA_CTRL0_STS1 [3/3]

#define XBARA_CTRL0_STS1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)

STS1 - Edge detection status for XBAR_OUT1 0b0..Active edge not yet detected on XBAR_OUT1 0b1..Active edge detected on XBAR_OUT1

◆ XBARA_CTRL1_DEN2 [1/3]

#define XBARA_CTRL1_DEN2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)

DEN2 - DMA Enable for XBAR_OUT2 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL1_DEN2 [2/3]

#define XBARA_CTRL1_DEN2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)

DEN2 - DMA Enable for XBAR_OUT2 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL1_DEN2 [3/3]

#define XBARA_CTRL1_DEN2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)

DEN2 - DMA Enable for XBAR_OUT2 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL1_DEN3 [1/3]

#define XBARA_CTRL1_DEN3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)

DEN3 - DMA Enable for XBAR_OUT3 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL1_DEN3 [2/3]

#define XBARA_CTRL1_DEN3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)

DEN3 - DMA Enable for XBAR_OUT3 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL1_DEN3 [3/3]

#define XBARA_CTRL1_DEN3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)

DEN3 - DMA Enable for XBAR_OUT3 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL1_EDGE2 [1/3]

#define XBARA_CTRL1_EDGE2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)

EDGE2 - Active edge for edge detection on XBAR_OUT2 0b00..STS2 never asserts 0b01..STS2 asserts on rising edges of XBAR_OUT2 0b10..STS2 asserts on falling edges of XBAR_OUT2 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2

◆ XBARA_CTRL1_EDGE2 [2/3]

#define XBARA_CTRL1_EDGE2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)

EDGE2 - Active edge for edge detection on XBAR_OUT2 0b00..STS2 never asserts 0b01..STS2 asserts on rising edges of XBAR_OUT2 0b10..STS2 asserts on falling edges of XBAR_OUT2 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2

◆ XBARA_CTRL1_EDGE2 [3/3]

#define XBARA_CTRL1_EDGE2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)

EDGE2 - Active edge for edge detection on XBAR_OUT2 0b00..STS2 never asserts 0b01..STS2 asserts on rising edges of XBAR_OUT2 0b10..STS2 asserts on falling edges of XBAR_OUT2 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2

◆ XBARA_CTRL1_EDGE3 [1/3]

#define XBARA_CTRL1_EDGE3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)

EDGE3 - Active edge for edge detection on XBAR_OUT3 0b00..STS3 never asserts 0b01..STS3 asserts on rising edges of XBAR_OUT3 0b10..STS3 asserts on falling edges of XBAR_OUT3 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3

◆ XBARA_CTRL1_EDGE3 [2/3]

#define XBARA_CTRL1_EDGE3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)

EDGE3 - Active edge for edge detection on XBAR_OUT3 0b00..STS3 never asserts 0b01..STS3 asserts on rising edges of XBAR_OUT3 0b10..STS3 asserts on falling edges of XBAR_OUT3 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3

◆ XBARA_CTRL1_EDGE3 [3/3]

#define XBARA_CTRL1_EDGE3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)

EDGE3 - Active edge for edge detection on XBAR_OUT3 0b00..STS3 never asserts 0b01..STS3 asserts on rising edges of XBAR_OUT3 0b10..STS3 asserts on falling edges of XBAR_OUT3 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3

◆ XBARA_CTRL1_IEN2 [1/3]

#define XBARA_CTRL1_IEN2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)

IEN2 - Interrupt Enable for XBAR_OUT2 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL1_IEN2 [2/3]

#define XBARA_CTRL1_IEN2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)

IEN2 - Interrupt Enable for XBAR_OUT2 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL1_IEN2 [3/3]

#define XBARA_CTRL1_IEN2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)

IEN2 - Interrupt Enable for XBAR_OUT2 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL1_IEN3 [1/3]

#define XBARA_CTRL1_IEN3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)

IEN3 - Interrupt Enable for XBAR_OUT3 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL1_IEN3 [2/3]

#define XBARA_CTRL1_IEN3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)

IEN3 - Interrupt Enable for XBAR_OUT3 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL1_IEN3 [3/3]

#define XBARA_CTRL1_IEN3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)

IEN3 - Interrupt Enable for XBAR_OUT3 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL1_STS2 [1/3]

#define XBARA_CTRL1_STS2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)

STS2 - Edge detection status for XBAR_OUT2 0b0..Active edge not yet detected on XBAR_OUT2 0b1..Active edge detected on XBAR_OUT2

◆ XBARA_CTRL1_STS2 [2/3]

#define XBARA_CTRL1_STS2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)

STS2 - Edge detection status for XBAR_OUT2 0b0..Active edge not yet detected on XBAR_OUT2 0b1..Active edge detected on XBAR_OUT2

◆ XBARA_CTRL1_STS2 [3/3]

#define XBARA_CTRL1_STS2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)

STS2 - Edge detection status for XBAR_OUT2 0b0..Active edge not yet detected on XBAR_OUT2 0b1..Active edge detected on XBAR_OUT2

◆ XBARA_CTRL1_STS3 [1/3]

#define XBARA_CTRL1_STS3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)

STS3 - Edge detection status for XBAR_OUT3 0b0..Active edge not yet detected on XBAR_OUT3 0b1..Active edge detected on XBAR_OUT3

◆ XBARA_CTRL1_STS3 [2/3]

#define XBARA_CTRL1_STS3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)

STS3 - Edge detection status for XBAR_OUT3 0b0..Active edge not yet detected on XBAR_OUT3 0b1..Active edge detected on XBAR_OUT3

◆ XBARA_CTRL1_STS3 [3/3]

#define XBARA_CTRL1_STS3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)

STS3 - Edge detection status for XBAR_OUT3 0b0..Active edge not yet detected on XBAR_OUT3 0b1..Active edge detected on XBAR_OUT3

SEL0 - Crossbar A Select Register 0

SEL1 - Crossbar A Select Register 1

SEL2 - Crossbar A Select Register 2

SEL3 - Crossbar A Select Register 3

SEL4 - Crossbar A Select Register 4

SEL5 - Crossbar A Select Register 5

SEL6 - Crossbar A Select Register 6

SEL7 - Crossbar A Select Register 7

SEL8 - Crossbar A Select Register 8

SEL9 - Crossbar A Select Register 9

SEL10 - Crossbar A Select Register 10

SEL11 - Crossbar A Select Register 11

SEL12 - Crossbar A Select Register 12

SEL13 - Crossbar A Select Register 13

SEL14 - Crossbar A Select Register 14

SEL15 - Crossbar A Select Register 15

SEL16 - Crossbar A Select Register 16

SEL17 - Crossbar A Select Register 17

SEL18 - Crossbar A Select Register 18

SEL19 - Crossbar A Select Register 19

SEL20 - Crossbar A Select Register 20

SEL21 - Crossbar A Select Register 21

SEL22 - Crossbar A Select Register 22

SEL23 - Crossbar A Select Register 23

SEL24 - Crossbar A Select Register 24

SEL25 - Crossbar A Select Register 25

SEL26 - Crossbar A Select Register 26

SEL27 - Crossbar A Select Register 27

SEL28 - Crossbar A Select Register 28

SEL29 - Crossbar A Select Register 29

SEL30 - Crossbar A Select Register 30

SEL31 - Crossbar A Select Register 31

SEL32 - Crossbar A Select Register 32

SEL33 - Crossbar A Select Register 33

SEL34 - Crossbar A Select Register 34

SEL35 - Crossbar A Select Register 35

SEL36 - Crossbar A Select Register 36

SEL37 - Crossbar A Select Register 37

SEL38 - Crossbar A Select Register 38

SEL39 - Crossbar A Select Register 39

SEL40 - Crossbar A Select Register 40

SEL41 - Crossbar A Select Register 41

SEL42 - Crossbar A Select Register 42

SEL43 - Crossbar A Select Register 43

SEL44 - Crossbar A Select Register 44

SEL45 - Crossbar A Select Register 45

SEL46 - Crossbar A Select Register 46

SEL47 - Crossbar A Select Register 47

SEL48 - Crossbar A Select Register 48

SEL49 - Crossbar A Select Register 49

SEL50 - Crossbar A Select Register 50

SEL51 - Crossbar A Select Register 51

SEL52 - Crossbar A Select Register 52

SEL53 - Crossbar A Select Register 53

SEL54 - Crossbar A Select Register 54

SEL55 - Crossbar A Select Register 55

SEL56 - Crossbar A Select Register 56

SEL57 - Crossbar A Select Register 57

SEL58 - Crossbar A Select Register 58

SEL59 - Crossbar A Select Register 59

SEL60 - Crossbar A Select Register 60

SEL61 - Crossbar A Select Register 61

SEL62 - Crossbar A Select Register 62

SEL63 - Crossbar A Select Register 63

SEL64 - Crossbar A Select Register 64

SEL65 - Crossbar A Select Register 65

CTRL0 - Crossbar A Control Register 0

CTRL1 - Crossbar A Control Register 1

SEL0 - Crossbar A Select Register 0

SEL1 - Crossbar A Select Register 1

SEL2 - Crossbar A Select Register 2

SEL3 - Crossbar A Select Register 3

SEL4 - Crossbar A Select Register 4

SEL5 - Crossbar A Select Register 5

SEL6 - Crossbar A Select Register 6

SEL7 - Crossbar A Select Register 7

SEL8 - Crossbar A Select Register 8

SEL9 - Crossbar A Select Register 9

SEL10 - Crossbar A Select Register 10

SEL11 - Crossbar A Select Register 11