Macros
#define	ENET_TXIC_COUNT (1U)

#define	ENET_RXIC_COUNT (1U)

#define	ENET_TCSR_COUNT (4U)

#define	ENET_TCCR_COUNT (4U)

#define	ENET_TXIC_COUNT (3U)

#define	ENET_RXIC_COUNT (3U)

#define	ENET_RCMR_COUNT (2U)

#define	ENET_DMACFG_COUNT (2U)

#define	ENET_TCSR_COUNT (4U)

#define	ENET_TCCR_COUNT (4U)

#define	ENET_TXIC_COUNT (3U)

#define	ENET_RXIC_COUNT (3U)

#define	ENET_RCMR_COUNT (2U)

#define	ENET_DMACFG_COUNT (2U)

#define	ENET_TCSR_COUNT (4U)

#define	ENET_TCCR_COUNT (4U)

EIR - Interrupt Event Register
#define	ENET_EIR_TS_TIMER_MASK (0x8000U)

#define	ENET_EIR_TS_TIMER_SHIFT (15U)

#define	ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)

#define	ENET_EIR_TS_AVAIL_MASK (0x10000U)

#define	ENET_EIR_TS_AVAIL_SHIFT (16U)

#define	ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)

#define	ENET_EIR_WAKEUP_MASK (0x20000U)

#define	ENET_EIR_WAKEUP_SHIFT (17U)

#define	ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)

#define	ENET_EIR_PLR_MASK (0x40000U)

#define	ENET_EIR_PLR_SHIFT (18U)

#define	ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)

#define	ENET_EIR_UN_MASK (0x80000U)

#define	ENET_EIR_UN_SHIFT (19U)

#define	ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)

#define	ENET_EIR_RL_MASK (0x100000U)

#define	ENET_EIR_RL_SHIFT (20U)

#define	ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)

#define	ENET_EIR_LC_MASK (0x200000U)

#define	ENET_EIR_LC_SHIFT (21U)

#define	ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)

#define	ENET_EIR_EBERR_MASK (0x400000U)

#define	ENET_EIR_EBERR_SHIFT (22U)

#define	ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)

#define	ENET_EIR_MII_MASK (0x800000U)

#define	ENET_EIR_MII_SHIFT (23U)

#define	ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)

#define	ENET_EIR_RXB_MASK (0x1000000U)

#define	ENET_EIR_RXB_SHIFT (24U)

#define	ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)

#define	ENET_EIR_RXF_MASK (0x2000000U)

#define	ENET_EIR_RXF_SHIFT (25U)

#define	ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)

#define	ENET_EIR_TXB_MASK (0x4000000U)

#define	ENET_EIR_TXB_SHIFT (26U)

#define	ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)

#define	ENET_EIR_TXF_MASK (0x8000000U)

#define	ENET_EIR_TXF_SHIFT (27U)

#define	ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)

#define	ENET_EIR_GRA_MASK (0x10000000U)

#define	ENET_EIR_GRA_SHIFT (28U)

#define	ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)

#define	ENET_EIR_BABT_MASK (0x20000000U)

#define	ENET_EIR_BABT_SHIFT (29U)

#define	ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)

#define	ENET_EIR_BABR_MASK (0x40000000U)

#define	ENET_EIR_BABR_SHIFT (30U)

#define	ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)

EIMR - Interrupt Mask Register
#define	ENET_EIMR_TS_TIMER_MASK (0x8000U)

#define	ENET_EIMR_TS_TIMER_SHIFT (15U)

#define	ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)

#define	ENET_EIMR_TS_AVAIL_MASK (0x10000U)

#define	ENET_EIMR_TS_AVAIL_SHIFT (16U)

#define	ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)

#define	ENET_EIMR_WAKEUP_MASK (0x20000U)

#define	ENET_EIMR_WAKEUP_SHIFT (17U)

#define	ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)

#define	ENET_EIMR_PLR_MASK (0x40000U)

#define	ENET_EIMR_PLR_SHIFT (18U)

#define	ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)

#define	ENET_EIMR_UN_MASK (0x80000U)

#define	ENET_EIMR_UN_SHIFT (19U)

#define	ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)

#define	ENET_EIMR_RL_MASK (0x100000U)

#define	ENET_EIMR_RL_SHIFT (20U)

#define	ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)

#define	ENET_EIMR_LC_MASK (0x200000U)

#define	ENET_EIMR_LC_SHIFT (21U)

#define	ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)

#define	ENET_EIMR_EBERR_MASK (0x400000U)

#define	ENET_EIMR_EBERR_SHIFT (22U)

#define	ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)

#define	ENET_EIMR_MII_MASK (0x800000U)

#define	ENET_EIMR_MII_SHIFT (23U)

#define	ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)

#define	ENET_EIMR_RXB_MASK (0x1000000U)

#define	ENET_EIMR_RXB_SHIFT (24U)

#define	ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)

#define	ENET_EIMR_RXF_MASK (0x2000000U)

#define	ENET_EIMR_RXF_SHIFT (25U)

#define	ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)

#define	ENET_EIMR_TXB_MASK (0x4000000U)

#define	ENET_EIMR_TXB_SHIFT (26U)

#define	ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

#define	ENET_EIMR_TXF_MASK (0x8000000U)

#define	ENET_EIMR_TXF_SHIFT (27U)

#define	ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

#define	ENET_EIMR_GRA_MASK (0x10000000U)

#define	ENET_EIMR_GRA_SHIFT (28U)

#define	ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

#define	ENET_EIMR_BABT_MASK (0x20000000U)

#define	ENET_EIMR_BABT_SHIFT (29U)

#define	ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

#define	ENET_EIMR_BABR_MASK (0x40000000U)

#define	ENET_EIMR_BABR_SHIFT (30U)

#define	ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

RDAR - Receive Descriptor Active Register - Ring 0
#define	ENET_RDAR_RDAR_MASK (0x1000000U)

#define	ENET_RDAR_RDAR_SHIFT (24U)

#define	ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)

TDAR - Transmit Descriptor Active Register - Ring 0
#define	ENET_TDAR_TDAR_MASK (0x1000000U)

#define	ENET_TDAR_TDAR_SHIFT (24U)

#define	ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)

ECR - Ethernet Control Register
#define	ENET_ECR_RESET_MASK (0x1U)

#define	ENET_ECR_RESET_SHIFT (0U)

#define	ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)

#define	ENET_ECR_ETHEREN_MASK (0x2U)

#define	ENET_ECR_ETHEREN_SHIFT (1U)

#define	ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

#define	ENET_ECR_MAGICEN_MASK (0x4U)

#define	ENET_ECR_MAGICEN_SHIFT (2U)

#define	ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

#define	ENET_ECR_SLEEP_MASK (0x8U)

#define	ENET_ECR_SLEEP_SHIFT (3U)

#define	ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

#define	ENET_ECR_EN1588_MASK (0x10U)

#define	ENET_ECR_EN1588_SHIFT (4U)

#define	ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

#define	ENET_ECR_DBGEN_MASK (0x40U)

#define	ENET_ECR_DBGEN_SHIFT (6U)

#define	ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

#define	ENET_ECR_DBSWP_MASK (0x100U)

#define	ENET_ECR_DBSWP_SHIFT (8U)

#define	ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

MMFR - MII Management Frame Register
#define	ENET_MMFR_DATA_MASK (0xFFFFU)

#define	ENET_MMFR_DATA_SHIFT (0U)

#define	ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)

#define	ENET_MMFR_TA_MASK (0x30000U)

#define	ENET_MMFR_TA_SHIFT (16U)

#define	ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)

#define	ENET_MMFR_RA_MASK (0x7C0000U)

#define	ENET_MMFR_RA_SHIFT (18U)

#define	ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)

#define	ENET_MMFR_PA_MASK (0xF800000U)

#define	ENET_MMFR_PA_SHIFT (23U)

#define	ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)

#define	ENET_MMFR_OP_MASK (0x30000000U)

#define	ENET_MMFR_OP_SHIFT (28U)

#define	ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)

#define	ENET_MMFR_ST_MASK (0xC0000000U)

#define	ENET_MMFR_ST_SHIFT (30U)

#define	ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)

MSCR - MII Speed Control Register
#define	ENET_MSCR_MII_SPEED_MASK (0x7EU)

#define	ENET_MSCR_MII_SPEED_SHIFT (1U)

#define	ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)

#define	ENET_MSCR_DIS_PRE_MASK (0x80U)

#define	ENET_MSCR_DIS_PRE_SHIFT (7U)

#define	ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

#define	ENET_MSCR_HOLDTIME_MASK (0x700U)

#define	ENET_MSCR_HOLDTIME_SHIFT (8U)

#define	ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

MIBC - MIB Control Register
#define	ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)

#define	ENET_MIBC_MIB_CLEAR_SHIFT (29U)

#define	ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

#define	ENET_MIBC_MIB_IDLE_MASK (0x40000000U)

#define	ENET_MIBC_MIB_IDLE_SHIFT (30U)

#define	ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

#define	ENET_MIBC_MIB_DIS_MASK (0x80000000U)

#define	ENET_MIBC_MIB_DIS_SHIFT (31U)

#define	ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

RCR - Receive Control Register
#define	ENET_RCR_LOOP_MASK (0x1U)

#define	ENET_RCR_LOOP_SHIFT (0U)

#define	ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

#define	ENET_RCR_DRT_MASK (0x2U)

#define	ENET_RCR_DRT_SHIFT (1U)

#define	ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

#define	ENET_RCR_MII_MODE_MASK (0x4U)

#define	ENET_RCR_MII_MODE_SHIFT (2U)

#define	ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

#define	ENET_RCR_PROM_MASK (0x8U)

#define	ENET_RCR_PROM_SHIFT (3U)

#define	ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

#define	ENET_RCR_BC_REJ_MASK (0x10U)

#define	ENET_RCR_BC_REJ_SHIFT (4U)

#define	ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)

#define	ENET_RCR_FCE_MASK (0x20U)

#define	ENET_RCR_FCE_SHIFT (5U)

#define	ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)

#define	ENET_RCR_RMII_MODE_MASK (0x100U)

#define	ENET_RCR_RMII_MODE_SHIFT (8U)

#define	ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

#define	ENET_RCR_RMII_10T_MASK (0x200U)

#define	ENET_RCR_RMII_10T_SHIFT (9U)

#define	ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

#define	ENET_RCR_PADEN_MASK (0x1000U)

#define	ENET_RCR_PADEN_SHIFT (12U)

#define	ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

#define	ENET_RCR_PAUFWD_MASK (0x2000U)

#define	ENET_RCR_PAUFWD_SHIFT (13U)

#define	ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

#define	ENET_RCR_CRCFWD_MASK (0x4000U)

#define	ENET_RCR_CRCFWD_SHIFT (14U)

#define	ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

#define	ENET_RCR_CFEN_MASK (0x8000U)

#define	ENET_RCR_CFEN_SHIFT (15U)

#define	ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

#define	ENET_RCR_MAX_FL_MASK (0x3FFF0000U)

#define	ENET_RCR_MAX_FL_SHIFT (16U)

#define	ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)

#define	ENET_RCR_NLC_MASK (0x40000000U)

#define	ENET_RCR_NLC_SHIFT (30U)

#define	ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

#define	ENET_RCR_GRS_MASK (0x80000000U)

#define	ENET_RCR_GRS_SHIFT (31U)

#define	ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)

TCR - Transmit Control Register
#define	ENET_TCR_GTS_MASK (0x1U)

#define	ENET_TCR_GTS_SHIFT (0U)

#define	ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)

#define	ENET_TCR_FDEN_MASK (0x4U)

#define	ENET_TCR_FDEN_SHIFT (2U)

#define	ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)

#define	ENET_TCR_TFC_PAUSE_MASK (0x8U)

#define	ENET_TCR_TFC_PAUSE_SHIFT (3U)

#define	ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

#define	ENET_TCR_RFC_PAUSE_MASK (0x10U)

#define	ENET_TCR_RFC_PAUSE_SHIFT (4U)

#define	ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)

#define	ENET_TCR_ADDSEL_MASK (0xE0U)

#define	ENET_TCR_ADDSEL_SHIFT (5U)

#define	ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

#define	ENET_TCR_ADDINS_MASK (0x100U)

#define	ENET_TCR_ADDINS_SHIFT (8U)

#define	ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

#define	ENET_TCR_CRCFWD_MASK (0x200U)

#define	ENET_TCR_CRCFWD_SHIFT (9U)

#define	ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

PALR - Physical Address Lower Register
#define	ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)

#define	ENET_PALR_PADDR1_SHIFT (0U)

#define	ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)

PAUR - Physical Address Upper Register
#define	ENET_PAUR_TYPE_MASK (0xFFFFU)

#define	ENET_PAUR_TYPE_SHIFT (0U)

#define	ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)

#define	ENET_PAUR_PADDR2_MASK (0xFFFF0000U)

#define	ENET_PAUR_PADDR2_SHIFT (16U)

#define	ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)

OPD - Opcode/Pause Duration Register
#define	ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)

#define	ENET_OPD_PAUSE_DUR_SHIFT (0U)

#define	ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)

#define	ENET_OPD_OPCODE_MASK (0xFFFF0000U)

#define	ENET_OPD_OPCODE_SHIFT (16U)

#define	ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)

TXIC - Transmit Interrupt Coalescing Register
#define	ENET_TXIC_ICTT_MASK (0xFFFFU)

#define	ENET_TXIC_ICTT_SHIFT (0U)

#define	ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)

#define	ENET_TXIC_ICFT_MASK (0xFF00000U)

#define	ENET_TXIC_ICFT_SHIFT (20U)

#define	ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)

#define	ENET_TXIC_ICCS_MASK (0x40000000U)

#define	ENET_TXIC_ICCS_SHIFT (30U)

#define	ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)

#define	ENET_TXIC_ICEN_MASK (0x80000000U)

#define	ENET_TXIC_ICEN_SHIFT (31U)

#define	ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)

RXIC - Receive Interrupt Coalescing Register
#define	ENET_RXIC_ICTT_MASK (0xFFFFU)

#define	ENET_RXIC_ICTT_SHIFT (0U)

#define	ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)

#define	ENET_RXIC_ICFT_MASK (0xFF00000U)

#define	ENET_RXIC_ICFT_SHIFT (20U)

#define	ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)

#define	ENET_RXIC_ICCS_MASK (0x40000000U)

#define	ENET_RXIC_ICCS_SHIFT (30U)

#define	ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)

#define	ENET_RXIC_ICEN_MASK (0x80000000U)

#define	ENET_RXIC_ICEN_SHIFT (31U)

#define	ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)

IAUR - Descriptor Individual Upper Address Register
#define	ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)

#define	ENET_IAUR_IADDR1_SHIFT (0U)

#define	ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)

IALR - Descriptor Individual Lower Address Register
#define	ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)

#define	ENET_IALR_IADDR2_SHIFT (0U)

#define	ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)

GAUR - Descriptor Group Upper Address Register
#define	ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)

#define	ENET_GAUR_GADDR1_SHIFT (0U)

#define	ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)

GALR - Descriptor Group Lower Address Register
#define	ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)

#define	ENET_GALR_GADDR2_SHIFT (0U)

#define	ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)

TFWR - Transmit FIFO Watermark Register
#define	ENET_TFWR_TFWR_MASK (0x3FU)

#define	ENET_TFWR_TFWR_SHIFT (0U)

#define	ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)

#define	ENET_TFWR_STRFWD_MASK (0x100U)

#define	ENET_TFWR_STRFWD_SHIFT (8U)

#define	ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)

RDSR - Receive Descriptor Ring 0 Start Register
#define	ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_RDSR_R_DES_START_SHIFT (3U)

#define	ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)

TDSR - Transmit Buffer Descriptor Ring 0 Start Register
#define	ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_TDSR_X_DES_START_SHIFT (3U)

#define	ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)

MRBR - Maximum Receive Buffer Size Register - Ring 0
#define	ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)

#define	ENET_MRBR_R_BUF_SIZE_SHIFT (4U)

#define	ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)

RSFL - Receive FIFO Section Full Threshold
#define	ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)

#define	ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)

#define	ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)

RSEM - Receive FIFO Section Empty Threshold
#define	ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)

#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)

#define	ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)

#define	ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)

#define	ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)

#define	ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)

RAEM - Receive FIFO Almost Empty Threshold
#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)

#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)

#define	ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)

RAFL - Receive FIFO Almost Full Threshold
#define	ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)

#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)

#define	ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)

TSEM - Transmit FIFO Section Empty Threshold
#define	ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)

#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)

#define	ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)

TAEM - Transmit FIFO Almost Empty Threshold
#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)

#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)

#define	ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)

TAFL - Transmit FIFO Almost Full Threshold
#define	ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)

#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)

#define	ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)

TIPG - Transmit Inter-Packet Gap
#define	ENET_TIPG_IPG_MASK (0x1FU)

#define	ENET_TIPG_IPG_SHIFT (0U)

#define	ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)

FTRL - Frame Truncation Length
#define	ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)

#define	ENET_FTRL_TRUNC_FL_SHIFT (0U)

#define	ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)

TACC - Transmit Accelerator Function Configuration
#define	ENET_TACC_SHIFT16_MASK (0x1U)

#define	ENET_TACC_SHIFT16_SHIFT (0U)

#define	ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

#define	ENET_TACC_IPCHK_MASK (0x8U)

#define	ENET_TACC_IPCHK_SHIFT (3U)

#define	ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

#define	ENET_TACC_PROCHK_MASK (0x10U)

#define	ENET_TACC_PROCHK_SHIFT (4U)

#define	ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

RACC - Receive Accelerator Function Configuration
#define	ENET_RACC_PADREM_MASK (0x1U)

#define	ENET_RACC_PADREM_SHIFT (0U)

#define	ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

#define	ENET_RACC_IPDIS_MASK (0x2U)

#define	ENET_RACC_IPDIS_SHIFT (1U)

#define	ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

#define	ENET_RACC_PRODIS_MASK (0x4U)

#define	ENET_RACC_PRODIS_SHIFT (2U)

#define	ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

#define	ENET_RACC_LINEDIS_MASK (0x40U)

#define	ENET_RACC_LINEDIS_SHIFT (6U)

#define	ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

#define	ENET_RACC_SHIFT16_MASK (0x80U)

#define	ENET_RACC_SHIFT16_SHIFT (7U)

#define	ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

RMON_T_PACKETS - Tx Packet Count Statistic Register
#define	ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)

RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
#define	ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)

RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
#define	ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)

RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)

RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)

RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
#define	ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)

RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)

RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)

RMON_T_COL - Tx Collision Count Statistic Register
#define	ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_COL_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)

RMON_T_P64 - Tx 64-Byte Packets Statistic Register
#define	ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P64_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)

RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
#define	ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)

RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
#define	ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)

RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
#define	ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)

RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
#define	ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)

RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
#define	ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)

RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
#define	ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)

RMON_T_OCTETS - Tx Octets Statistic Register
#define	ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)

#define	ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)

#define	ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)

IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
#define	ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)

IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
#define	ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_1COL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)

IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
#define	ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)

IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
#define	ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_DEF_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)

IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
#define	ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)

IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
#define	ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)

IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
#define	ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)

IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
#define	ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)

IEEE_T_SQE - Reserved Statistic Register
#define	ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_SQE_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)

IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
#define	ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)

IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
#define	ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)

#define	ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)

RMON_R_PACKETS - Rx Packet Count Statistic Register
#define	ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)

#define	ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)

RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
#define	ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)

#define	ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)

RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
#define	ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)

#define	ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)

RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)

#define	ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)

RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
#define	ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)

#define	ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)

RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
#define	ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)

#define	ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)

RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_FRAG_COUNT_SHIFT (0U)

#define	ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)

RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_JAB_COUNT_SHIFT (0U)

#define	ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)

RMON_R_P64 - Rx 64-Byte Packets Statistic Register
#define	ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P64_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)

RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
#define	ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)

RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
#define	ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)

RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
#define	ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)

RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
#define	ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)

RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
#define	ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)

RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
#define	ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)

RMON_R_OCTETS - Rx Octets Statistic Register
#define	ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)

#define	ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)

#define	ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)

IEEE_R_DROP - Frames not Counted Correctly Statistic Register
#define	ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_DROP_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)

IEEE_R_FRAME_OK - Frames Received OK Statistic Register
#define	ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)

IEEE_R_CRC - Frames Received with CRC Error Statistic Register
#define	ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_CRC_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)

IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
#define	ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)

IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
#define	ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)

IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
#define	ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)

IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
#define	ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)

#define	ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)

ATCR - Adjustable Timer Control Register
#define	ENET_ATCR_EN_MASK (0x1U)

#define	ENET_ATCR_EN_SHIFT (0U)

#define	ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

#define	ENET_ATCR_OFFEN_MASK (0x4U)

#define	ENET_ATCR_OFFEN_SHIFT (2U)

#define	ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

#define	ENET_ATCR_OFFRST_MASK (0x8U)

#define	ENET_ATCR_OFFRST_SHIFT (3U)

#define	ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

#define	ENET_ATCR_PEREN_MASK (0x10U)

#define	ENET_ATCR_PEREN_SHIFT (4U)

#define	ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

#define	ENET_ATCR_PINPER_MASK (0x80U)

#define	ENET_ATCR_PINPER_SHIFT (7U)

#define	ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

#define	ENET_ATCR_RESTART_MASK (0x200U)

#define	ENET_ATCR_RESTART_SHIFT (9U)

#define	ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)

#define	ENET_ATCR_CAPTURE_MASK (0x800U)

#define	ENET_ATCR_CAPTURE_SHIFT (11U)

#define	ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

#define	ENET_ATCR_SLAVE_MASK (0x2000U)

#define	ENET_ATCR_SLAVE_SHIFT (13U)

#define	ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

ATVR - Timer Value Register
#define	ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)

#define	ENET_ATVR_ATIME_SHIFT (0U)

#define	ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)

ATOFF - Timer Offset Register
#define	ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)

#define	ENET_ATOFF_OFFSET_SHIFT (0U)

#define	ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)

ATPER - Timer Period Register
#define	ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)

#define	ENET_ATPER_PERIOD_SHIFT (0U)

#define	ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)

ATCOR - Timer Correction Register
#define	ENET_ATCOR_COR_MASK (0x7FFFFFFFU)

#define	ENET_ATCOR_COR_SHIFT (0U)

#define	ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)

ATINC - Time-Stamping Clock Period Register
#define	ENET_ATINC_INC_MASK (0x7FU)

#define	ENET_ATINC_INC_SHIFT (0U)

#define	ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)

#define	ENET_ATINC_INC_CORR_MASK (0x7F00U)

#define	ENET_ATINC_INC_CORR_SHIFT (8U)

#define	ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)

ATSTMP - Timestamp of Last Transmitted Frame
#define	ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)

#define	ENET_ATSTMP_TIMESTAMP_SHIFT (0U)

#define	ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)

TGSR - Timer Global Status Register
#define	ENET_TGSR_TF0_MASK (0x1U)

#define	ENET_TGSR_TF0_SHIFT (0U)

#define	ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)

#define	ENET_TGSR_TF1_MASK (0x2U)

#define	ENET_TGSR_TF1_SHIFT (1U)

#define	ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)

#define	ENET_TGSR_TF2_MASK (0x4U)

#define	ENET_TGSR_TF2_SHIFT (2U)

#define	ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)

#define	ENET_TGSR_TF3_MASK (0x8U)

#define	ENET_TGSR_TF3_SHIFT (3U)

#define	ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)

TCSR - Timer Control Status Register
#define	ENET_TCSR_TDRE_MASK (0x1U)

#define	ENET_TCSR_TDRE_SHIFT (0U)

#define	ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

#define	ENET_TCSR_TMODE_MASK (0x3CU)

#define	ENET_TCSR_TMODE_SHIFT (2U)

#define	ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

#define	ENET_TCSR_TIE_MASK (0x40U)

#define	ENET_TCSR_TIE_SHIFT (6U)

#define	ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

#define	ENET_TCSR_TF_MASK (0x80U)

#define	ENET_TCSR_TF_SHIFT (7U)

#define	ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

#define	ENET_TCSR_TPWC_MASK (0xF800U)

#define	ENET_TCSR_TPWC_SHIFT (11U)

#define	ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)

TCCR - Timer Compare Capture Register
#define	ENET_TCCR_TCC_MASK (0xFFFFFFFFU)

#define	ENET_TCCR_TCC_SHIFT (0U)

#define	ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)

EIR - Interrupt Event Register
#define	ENET_EIR_RXB1_MASK (0x1U)

#define	ENET_EIR_RXB1_SHIFT (0U)

#define	ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)

#define	ENET_EIR_RXF1_MASK (0x2U)

#define	ENET_EIR_RXF1_SHIFT (1U)

#define	ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)

#define	ENET_EIR_TXB1_MASK (0x4U)

#define	ENET_EIR_TXB1_SHIFT (2U)

#define	ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)

#define	ENET_EIR_TXF1_MASK (0x8U)

#define	ENET_EIR_TXF1_SHIFT (3U)

#define	ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)

#define	ENET_EIR_RXB2_MASK (0x10U)

#define	ENET_EIR_RXB2_SHIFT (4U)

#define	ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)

#define	ENET_EIR_RXF2_MASK (0x20U)

#define	ENET_EIR_RXF2_SHIFT (5U)

#define	ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)

#define	ENET_EIR_TXB2_MASK (0x40U)

#define	ENET_EIR_TXB2_SHIFT (6U)

#define	ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)

#define	ENET_EIR_TXF2_MASK (0x80U)

#define	ENET_EIR_TXF2_SHIFT (7U)

#define	ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)

#define	ENET_EIR_RXFLUSH_0_MASK (0x1000U)

#define	ENET_EIR_RXFLUSH_0_SHIFT (12U)

#define	ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)

#define	ENET_EIR_RXFLUSH_1_MASK (0x2000U)

#define	ENET_EIR_RXFLUSH_1_SHIFT (13U)

#define	ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)

#define	ENET_EIR_RXFLUSH_2_MASK (0x4000U)

#define	ENET_EIR_RXFLUSH_2_SHIFT (14U)

#define	ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)

#define	ENET_EIR_TS_TIMER_MASK (0x8000U)

#define	ENET_EIR_TS_TIMER_SHIFT (15U)

#define	ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)

#define	ENET_EIR_TS_AVAIL_MASK (0x10000U)

#define	ENET_EIR_TS_AVAIL_SHIFT (16U)

#define	ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)

#define	ENET_EIR_WAKEUP_MASK (0x20000U)

#define	ENET_EIR_WAKEUP_SHIFT (17U)

#define	ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)

#define	ENET_EIR_PLR_MASK (0x40000U)

#define	ENET_EIR_PLR_SHIFT (18U)

#define	ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)

#define	ENET_EIR_UN_MASK (0x80000U)

#define	ENET_EIR_UN_SHIFT (19U)

#define	ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)

#define	ENET_EIR_RL_MASK (0x100000U)

#define	ENET_EIR_RL_SHIFT (20U)

#define	ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)

#define	ENET_EIR_LC_MASK (0x200000U)

#define	ENET_EIR_LC_SHIFT (21U)

#define	ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)

#define	ENET_EIR_EBERR_MASK (0x400000U)

#define	ENET_EIR_EBERR_SHIFT (22U)

#define	ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)

#define	ENET_EIR_MII_MASK (0x800000U)

#define	ENET_EIR_MII_SHIFT (23U)

#define	ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)

#define	ENET_EIR_RXB_MASK (0x1000000U)

#define	ENET_EIR_RXB_SHIFT (24U)

#define	ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)

#define	ENET_EIR_RXF_MASK (0x2000000U)

#define	ENET_EIR_RXF_SHIFT (25U)

#define	ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)

#define	ENET_EIR_TXB_MASK (0x4000000U)

#define	ENET_EIR_TXB_SHIFT (26U)

#define	ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)

#define	ENET_EIR_TXF_MASK (0x8000000U)

#define	ENET_EIR_TXF_SHIFT (27U)

#define	ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)

#define	ENET_EIR_GRA_MASK (0x10000000U)

#define	ENET_EIR_GRA_SHIFT (28U)

#define	ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)

#define	ENET_EIR_BABT_MASK (0x20000000U)

#define	ENET_EIR_BABT_SHIFT (29U)

#define	ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)

#define	ENET_EIR_BABR_MASK (0x40000000U)

#define	ENET_EIR_BABR_SHIFT (30U)

#define	ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)

EIMR - Interrupt Mask Register
#define	ENET_EIMR_RXB1_MASK (0x1U)

#define	ENET_EIMR_RXB1_SHIFT (0U)

#define	ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)

#define	ENET_EIMR_RXF1_MASK (0x2U)

#define	ENET_EIMR_RXF1_SHIFT (1U)

#define	ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)

#define	ENET_EIMR_TXB1_MASK (0x4U)

#define	ENET_EIMR_TXB1_SHIFT (2U)

#define	ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)

#define	ENET_EIMR_TXF1_MASK (0x8U)

#define	ENET_EIMR_TXF1_SHIFT (3U)

#define	ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)

#define	ENET_EIMR_RXB2_MASK (0x10U)

#define	ENET_EIMR_RXB2_SHIFT (4U)

#define	ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)

#define	ENET_EIMR_RXF2_MASK (0x20U)

#define	ENET_EIMR_RXF2_SHIFT (5U)

#define	ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)

#define	ENET_EIMR_TXB2_MASK (0x40U)

#define	ENET_EIMR_TXB2_SHIFT (6U)

#define	ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)

#define	ENET_EIMR_TXF2_MASK (0x80U)

#define	ENET_EIMR_TXF2_SHIFT (7U)

#define	ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)

#define	ENET_EIMR_RXFLUSH_0_MASK (0x1000U)

#define	ENET_EIMR_RXFLUSH_0_SHIFT (12U)

#define	ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)

#define	ENET_EIMR_RXFLUSH_1_MASK (0x2000U)

#define	ENET_EIMR_RXFLUSH_1_SHIFT (13U)

#define	ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)

#define	ENET_EIMR_RXFLUSH_2_MASK (0x4000U)

#define	ENET_EIMR_RXFLUSH_2_SHIFT (14U)

#define	ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)

#define	ENET_EIMR_TS_TIMER_MASK (0x8000U)

#define	ENET_EIMR_TS_TIMER_SHIFT (15U)

#define	ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)

#define	ENET_EIMR_TS_AVAIL_MASK (0x10000U)

#define	ENET_EIMR_TS_AVAIL_SHIFT (16U)

#define	ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)

#define	ENET_EIMR_WAKEUP_MASK (0x20000U)

#define	ENET_EIMR_WAKEUP_SHIFT (17U)

#define	ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)

#define	ENET_EIMR_PLR_MASK (0x40000U)

#define	ENET_EIMR_PLR_SHIFT (18U)

#define	ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)

#define	ENET_EIMR_UN_MASK (0x80000U)

#define	ENET_EIMR_UN_SHIFT (19U)

#define	ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)

#define	ENET_EIMR_RL_MASK (0x100000U)

#define	ENET_EIMR_RL_SHIFT (20U)

#define	ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)

#define	ENET_EIMR_LC_MASK (0x200000U)

#define	ENET_EIMR_LC_SHIFT (21U)

#define	ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)

#define	ENET_EIMR_EBERR_MASK (0x400000U)

#define	ENET_EIMR_EBERR_SHIFT (22U)

#define	ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)

#define	ENET_EIMR_MII_MASK (0x800000U)

#define	ENET_EIMR_MII_SHIFT (23U)

#define	ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)

#define	ENET_EIMR_RXB_MASK (0x1000000U)

#define	ENET_EIMR_RXB_SHIFT (24U)

#define	ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)

#define	ENET_EIMR_RXF_MASK (0x2000000U)

#define	ENET_EIMR_RXF_SHIFT (25U)

#define	ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)

#define	ENET_EIMR_TXB_MASK (0x4000000U)

#define	ENET_EIMR_TXB_SHIFT (26U)

#define	ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

#define	ENET_EIMR_TXF_MASK (0x8000000U)

#define	ENET_EIMR_TXF_SHIFT (27U)

#define	ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

#define	ENET_EIMR_GRA_MASK (0x10000000U)

#define	ENET_EIMR_GRA_SHIFT (28U)

#define	ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

#define	ENET_EIMR_BABT_MASK (0x20000000U)

#define	ENET_EIMR_BABT_SHIFT (29U)

#define	ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

#define	ENET_EIMR_BABR_MASK (0x40000000U)

#define	ENET_EIMR_BABR_SHIFT (30U)

#define	ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

RDAR - Receive Descriptor Active Register - Ring 0
#define	ENET_RDAR_RDAR_MASK (0x1000000U)

#define	ENET_RDAR_RDAR_SHIFT (24U)

#define	ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)

TDAR - Transmit Descriptor Active Register - Ring 0
#define	ENET_TDAR_TDAR_MASK (0x1000000U)

#define	ENET_TDAR_TDAR_SHIFT (24U)

#define	ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)

ECR - Ethernet Control Register
#define	ENET_ECR_RESET_MASK (0x1U)

#define	ENET_ECR_RESET_SHIFT (0U)

#define	ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)

#define	ENET_ECR_ETHEREN_MASK (0x2U)

#define	ENET_ECR_ETHEREN_SHIFT (1U)

#define	ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

#define	ENET_ECR_MAGICEN_MASK (0x4U)

#define	ENET_ECR_MAGICEN_SHIFT (2U)

#define	ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

#define	ENET_ECR_SLEEP_MASK (0x8U)

#define	ENET_ECR_SLEEP_SHIFT (3U)

#define	ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

#define	ENET_ECR_EN1588_MASK (0x10U)

#define	ENET_ECR_EN1588_SHIFT (4U)

#define	ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

#define	ENET_ECR_SPEED_MASK (0x20U)

#define	ENET_ECR_SPEED_SHIFT (5U)

#define	ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)

#define	ENET_ECR_DBGEN_MASK (0x40U)

#define	ENET_ECR_DBGEN_SHIFT (6U)

#define	ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

#define	ENET_ECR_DBSWP_MASK (0x100U)

#define	ENET_ECR_DBSWP_SHIFT (8U)

#define	ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

#define	ENET_ECR_SVLANEN_MASK (0x200U)

#define	ENET_ECR_SVLANEN_SHIFT (9U)

#define	ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)

#define	ENET_ECR_VLANUSE2ND_MASK (0x400U)

#define	ENET_ECR_VLANUSE2ND_SHIFT (10U)

#define	ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)

#define	ENET_ECR_SVLANDBL_MASK (0x800U)

#define	ENET_ECR_SVLANDBL_SHIFT (11U)

#define	ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)

#define	ENET_ECR_TXC_DLY_MASK (0x10000U)

#define	ENET_ECR_TXC_DLY_SHIFT (16U)

#define	ENET_ECR_TXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)

MMFR - MII Management Frame Register
#define	ENET_MMFR_DATA_MASK (0xFFFFU)

#define	ENET_MMFR_DATA_SHIFT (0U)

#define	ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)

#define	ENET_MMFR_TA_MASK (0x30000U)

#define	ENET_MMFR_TA_SHIFT (16U)

#define	ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)

#define	ENET_MMFR_RA_MASK (0x7C0000U)

#define	ENET_MMFR_RA_SHIFT (18U)

#define	ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)

#define	ENET_MMFR_PA_MASK (0xF800000U)

#define	ENET_MMFR_PA_SHIFT (23U)

#define	ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)

#define	ENET_MMFR_OP_MASK (0x30000000U)

#define	ENET_MMFR_OP_SHIFT (28U)

#define	ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)

#define	ENET_MMFR_ST_MASK (0xC0000000U)

#define	ENET_MMFR_ST_SHIFT (30U)

#define	ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)

MSCR - MII Speed Control Register
#define	ENET_MSCR_MII_SPEED_MASK (0x7EU)

#define	ENET_MSCR_MII_SPEED_SHIFT (1U)

#define	ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)

#define	ENET_MSCR_DIS_PRE_MASK (0x80U)

#define	ENET_MSCR_DIS_PRE_SHIFT (7U)

#define	ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

#define	ENET_MSCR_HOLDTIME_MASK (0x700U)

#define	ENET_MSCR_HOLDTIME_SHIFT (8U)

#define	ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

MIBC - MIB Control Register
#define	ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)

#define	ENET_MIBC_MIB_CLEAR_SHIFT (29U)

#define	ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

#define	ENET_MIBC_MIB_IDLE_MASK (0x40000000U)

#define	ENET_MIBC_MIB_IDLE_SHIFT (30U)

#define	ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

#define	ENET_MIBC_MIB_DIS_MASK (0x80000000U)

#define	ENET_MIBC_MIB_DIS_SHIFT (31U)

#define	ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

RCR - Receive Control Register
#define	ENET_RCR_LOOP_MASK (0x1U)

#define	ENET_RCR_LOOP_SHIFT (0U)

#define	ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

#define	ENET_RCR_DRT_MASK (0x2U)

#define	ENET_RCR_DRT_SHIFT (1U)

#define	ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

#define	ENET_RCR_MII_MODE_MASK (0x4U)

#define	ENET_RCR_MII_MODE_SHIFT (2U)

#define	ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

#define	ENET_RCR_PROM_MASK (0x8U)

#define	ENET_RCR_PROM_SHIFT (3U)

#define	ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

#define	ENET_RCR_BC_REJ_MASK (0x10U)

#define	ENET_RCR_BC_REJ_SHIFT (4U)

#define	ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)

#define	ENET_RCR_FCE_MASK (0x20U)

#define	ENET_RCR_FCE_SHIFT (5U)

#define	ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)

#define	ENET_RCR_RGMII_EN_MASK (0x40U)

#define	ENET_RCR_RGMII_EN_SHIFT (6U)

#define	ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)

#define	ENET_RCR_RMII_MODE_MASK (0x100U)

#define	ENET_RCR_RMII_MODE_SHIFT (8U)

#define	ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

#define	ENET_RCR_RMII_10T_MASK (0x200U)

#define	ENET_RCR_RMII_10T_SHIFT (9U)

#define	ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

#define	ENET_RCR_PADEN_MASK (0x1000U)

#define	ENET_RCR_PADEN_SHIFT (12U)

#define	ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

#define	ENET_RCR_PAUFWD_MASK (0x2000U)

#define	ENET_RCR_PAUFWD_SHIFT (13U)

#define	ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

#define	ENET_RCR_CRCFWD_MASK (0x4000U)

#define	ENET_RCR_CRCFWD_SHIFT (14U)

#define	ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

#define	ENET_RCR_CFEN_MASK (0x8000U)

#define	ENET_RCR_CFEN_SHIFT (15U)

#define	ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

#define	ENET_RCR_MAX_FL_MASK (0x3FFF0000U)

#define	ENET_RCR_MAX_FL_SHIFT (16U)

#define	ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)

#define	ENET_RCR_NLC_MASK (0x40000000U)

#define	ENET_RCR_NLC_SHIFT (30U)

#define	ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

#define	ENET_RCR_GRS_MASK (0x80000000U)

#define	ENET_RCR_GRS_SHIFT (31U)

#define	ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)

TCR - Transmit Control Register
#define	ENET_TCR_GTS_MASK (0x1U)

#define	ENET_TCR_GTS_SHIFT (0U)

#define	ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)

#define	ENET_TCR_FDEN_MASK (0x4U)

#define	ENET_TCR_FDEN_SHIFT (2U)

#define	ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)

#define	ENET_TCR_TFC_PAUSE_MASK (0x8U)

#define	ENET_TCR_TFC_PAUSE_SHIFT (3U)

#define	ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

#define	ENET_TCR_RFC_PAUSE_MASK (0x10U)

#define	ENET_TCR_RFC_PAUSE_SHIFT (4U)

#define	ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)

#define	ENET_TCR_ADDSEL_MASK (0xE0U)

#define	ENET_TCR_ADDSEL_SHIFT (5U)

#define	ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

#define	ENET_TCR_ADDINS_MASK (0x100U)

#define	ENET_TCR_ADDINS_SHIFT (8U)

#define	ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

#define	ENET_TCR_CRCFWD_MASK (0x200U)

#define	ENET_TCR_CRCFWD_SHIFT (9U)

#define	ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

PALR - Physical Address Lower Register
#define	ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)

#define	ENET_PALR_PADDR1_SHIFT (0U)

#define	ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)

PAUR - Physical Address Upper Register
#define	ENET_PAUR_TYPE_MASK (0xFFFFU)

#define	ENET_PAUR_TYPE_SHIFT (0U)

#define	ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)

#define	ENET_PAUR_PADDR2_MASK (0xFFFF0000U)

#define	ENET_PAUR_PADDR2_SHIFT (16U)

#define	ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)

OPD - Opcode/Pause Duration Register
#define	ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)

#define	ENET_OPD_PAUSE_DUR_SHIFT (0U)

#define	ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)

#define	ENET_OPD_OPCODE_MASK (0xFFFF0000U)

#define	ENET_OPD_OPCODE_SHIFT (16U)

#define	ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)

TXIC - Transmit Interrupt Coalescing Register
#define	ENET_TXIC_ICTT_MASK (0xFFFFU)

#define	ENET_TXIC_ICTT_SHIFT (0U)

#define	ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)

#define	ENET_TXIC_ICFT_MASK (0xFF00000U)

#define	ENET_TXIC_ICFT_SHIFT (20U)

#define	ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)

#define	ENET_TXIC_ICCS_MASK (0x40000000U)

#define	ENET_TXIC_ICCS_SHIFT (30U)

#define	ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)

#define	ENET_TXIC_ICEN_MASK (0x80000000U)

#define	ENET_TXIC_ICEN_SHIFT (31U)

#define	ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)

RXIC - Receive Interrupt Coalescing Register
#define	ENET_RXIC_ICTT_MASK (0xFFFFU)

#define	ENET_RXIC_ICTT_SHIFT (0U)

#define	ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)

#define	ENET_RXIC_ICFT_MASK (0xFF00000U)

#define	ENET_RXIC_ICFT_SHIFT (20U)

#define	ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)

#define	ENET_RXIC_ICCS_MASK (0x40000000U)

#define	ENET_RXIC_ICCS_SHIFT (30U)

#define	ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)

#define	ENET_RXIC_ICEN_MASK (0x80000000U)

#define	ENET_RXIC_ICEN_SHIFT (31U)

#define	ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)

IAUR - Descriptor Individual Upper Address Register
#define	ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)

#define	ENET_IAUR_IADDR1_SHIFT (0U)

#define	ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)

IALR - Descriptor Individual Lower Address Register
#define	ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)

#define	ENET_IALR_IADDR2_SHIFT (0U)

#define	ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)

GAUR - Descriptor Group Upper Address Register
#define	ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)

#define	ENET_GAUR_GADDR1_SHIFT (0U)

#define	ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)

GALR - Descriptor Group Lower Address Register
#define	ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)

#define	ENET_GALR_GADDR2_SHIFT (0U)

#define	ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)

TFWR - Transmit FIFO Watermark Register
#define	ENET_TFWR_TFWR_MASK (0x3FU)

#define	ENET_TFWR_TFWR_SHIFT (0U)

#define	ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)

#define	ENET_TFWR_STRFWD_MASK (0x100U)

#define	ENET_TFWR_STRFWD_SHIFT (8U)

#define	ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)

RDSR1 - Receive Descriptor Ring 1 Start Register
#define	ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_RDSR1_R_DES_START_SHIFT (3U)

#define	ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)

TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register
#define	ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_TDSR1_X_DES_START_SHIFT (3U)

#define	ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)

MRBR1 - Maximum Receive Buffer Size Register - Ring 1
#define	ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U)

#define	ENET_MRBR1_R_BUF_SIZE_SHIFT (4U)

#define	ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)

RDSR2 - Receive Descriptor Ring 2 Start Register
#define	ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_RDSR2_R_DES_START_SHIFT (3U)

#define	ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)

TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register
#define	ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_TDSR2_X_DES_START_SHIFT (3U)

#define	ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)

MRBR2 - Maximum Receive Buffer Size Register - Ring 2
#define	ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U)

#define	ENET_MRBR2_R_BUF_SIZE_SHIFT (4U)

#define	ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)

RDSR - Receive Descriptor Ring 0 Start Register
#define	ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_RDSR_R_DES_START_SHIFT (3U)

#define	ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)

TDSR - Transmit Buffer Descriptor Ring 0 Start Register
#define	ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_TDSR_X_DES_START_SHIFT (3U)

#define	ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)

MRBR - Maximum Receive Buffer Size Register - Ring 0
#define	ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */

#define	ENET_MRBR_R_BUF_SIZE_SHIFT (4U)

#define	ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */

RSFL - Receive FIFO Section Full Threshold
#define	ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)

#define	ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RSEM - Receive FIFO Section Empty Threshold
#define	ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)

#define	ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)

#define	ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)

#define	ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)

RAEM - Receive FIFO Almost Empty Threshold
#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)

#define	ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RAFL - Receive FIFO Almost Full Threshold
#define	ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)

#define	ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TSEM - Transmit FIFO Section Empty Threshold
#define	ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)

#define	ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TAEM - Transmit FIFO Almost Empty Threshold
#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)

#define	ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TAFL - Transmit FIFO Almost Full Threshold
#define	ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)

#define	ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TIPG - Transmit Inter-Packet Gap
#define	ENET_TIPG_IPG_MASK (0x1FU)

#define	ENET_TIPG_IPG_SHIFT (0U)

#define	ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)

FTRL - Frame Truncation Length
#define	ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)

#define	ENET_FTRL_TRUNC_FL_SHIFT (0U)

#define	ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)

TACC - Transmit Accelerator Function Configuration
#define	ENET_TACC_SHIFT16_MASK (0x1U)

#define	ENET_TACC_SHIFT16_SHIFT (0U)

#define	ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

#define	ENET_TACC_IPCHK_MASK (0x8U)

#define	ENET_TACC_IPCHK_SHIFT (3U)

#define	ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

#define	ENET_TACC_PROCHK_MASK (0x10U)

#define	ENET_TACC_PROCHK_SHIFT (4U)

#define	ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

RACC - Receive Accelerator Function Configuration
#define	ENET_RACC_PADREM_MASK (0x1U)

#define	ENET_RACC_PADREM_SHIFT (0U)

#define	ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

#define	ENET_RACC_IPDIS_MASK (0x2U)

#define	ENET_RACC_IPDIS_SHIFT (1U)

#define	ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

#define	ENET_RACC_PRODIS_MASK (0x4U)

#define	ENET_RACC_PRODIS_SHIFT (2U)

#define	ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

#define	ENET_RACC_LINEDIS_MASK (0x40U)

#define	ENET_RACC_LINEDIS_SHIFT (6U)

#define	ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

#define	ENET_RACC_SHIFT16_MASK (0x80U)

#define	ENET_RACC_SHIFT16_SHIFT (7U)

#define	ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

RCMR - Receive Classification Match Register for Class n
#define	ENET_RCMR_CMP0_MASK (0x7U)

#define	ENET_RCMR_CMP0_SHIFT (0U)

#define	ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)

#define	ENET_RCMR_CMP1_MASK (0x70U)

#define	ENET_RCMR_CMP1_SHIFT (4U)

#define	ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)

#define	ENET_RCMR_CMP2_MASK (0x700U)

#define	ENET_RCMR_CMP2_SHIFT (8U)

#define	ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)

#define	ENET_RCMR_CMP3_MASK (0x7000U)

#define	ENET_RCMR_CMP3_SHIFT (12U)

#define	ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)

#define	ENET_RCMR_MATCHEN_MASK (0x10000U)

#define	ENET_RCMR_MATCHEN_SHIFT (16U)

#define	ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)

DMACFG - DMA Class Based Configuration
#define	ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU)

#define	ENET_DMACFG_IDLE_SLOPE_SHIFT (0U)

#define	ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)

#define	ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U)

#define	ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U)

#define	ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)

#define	ENET_DMACFG_CALC_NOIPG_MASK (0x20000U)

#define	ENET_DMACFG_CALC_NOIPG_SHIFT (17U)

#define	ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)

RDAR1 - Receive Descriptor Active Register - Ring 1
#define	ENET_RDAR1_RDAR_MASK (0x1000000U)

#define	ENET_RDAR1_RDAR_SHIFT (24U)

#define	ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)

TDAR1 - Transmit Descriptor Active Register - Ring 1
#define	ENET_TDAR1_TDAR_MASK (0x1000000U)

#define	ENET_TDAR1_TDAR_SHIFT (24U)

#define	ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)

RDAR2 - Receive Descriptor Active Register - Ring 2
#define	ENET_RDAR2_RDAR_MASK (0x1000000U)

#define	ENET_RDAR2_RDAR_SHIFT (24U)

#define	ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)

TDAR2 - Transmit Descriptor Active Register - Ring 2
#define	ENET_TDAR2_TDAR_MASK (0x1000000U)

#define	ENET_TDAR2_TDAR_SHIFT (24U)

#define	ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)

QOS - QOS Scheme
#define	ENET_QOS_TX_SCHEME_MASK (0x7U)

#define	ENET_QOS_TX_SCHEME_SHIFT (0U)

#define	ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)

#define	ENET_QOS_RX_FLUSH0_MASK (0x8U)

#define	ENET_QOS_RX_FLUSH0_SHIFT (3U)

#define	ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)

#define	ENET_QOS_RX_FLUSH1_MASK (0x10U)

#define	ENET_QOS_RX_FLUSH1_SHIFT (4U)

#define	ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)

#define	ENET_QOS_RX_FLUSH2_MASK (0x20U)

#define	ENET_QOS_RX_FLUSH2_SHIFT (5U)

#define	ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)

RMON_T_PACKETS - Tx Packet Count Statistic Register
#define	ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)

RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
#define	ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)

RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
#define	ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)

RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)

RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)

RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
#define	ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)

RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)

RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)

RMON_T_COL - Tx Collision Count Statistic Register
#define	ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_COL_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)

RMON_T_P64 - Tx 64-Byte Packets Statistic Register
#define	ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P64_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)

RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
#define	ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)

RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
#define	ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)

RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
#define	ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)

RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
#define	ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)

RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
#define	ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)

RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
#define	ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)

RMON_T_OCTETS - Tx Octets Statistic Register
#define	ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)

#define	ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)

#define	ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)

IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
#define	ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)

IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
#define	ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_1COL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)

IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
#define	ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)

IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
#define	ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_DEF_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)

IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
#define	ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)

IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
#define	ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)

IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
#define	ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)

IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
#define	ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)

IEEE_T_SQE - Reserved Statistic Register
#define	ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_SQE_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)

IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
#define	ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)

IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
#define	ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)

#define	ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)

RMON_R_PACKETS - Rx Packet Count Statistic Register
#define	ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)

#define	ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)

RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
#define	ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)

#define	ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)

RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
#define	ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)

#define	ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)

RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)

#define	ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)

RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
#define	ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)

#define	ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)

RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
#define	ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)

#define	ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)

RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_FRAG_COUNT_SHIFT (0U)

#define	ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)

RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_JAB_COUNT_SHIFT (0U)

#define	ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)

RMON_R_P64 - Rx 64-Byte Packets Statistic Register
#define	ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P64_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)

RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
#define	ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)

RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
#define	ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)

RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
#define	ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)

RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
#define	ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)

RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
#define	ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)

RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
#define	ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)

RMON_R_OCTETS - Rx Octets Statistic Register
#define	ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)

#define	ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)

#define	ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)

IEEE_R_DROP - Frames not Counted Correctly Statistic Register
#define	ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_DROP_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)

IEEE_R_FRAME_OK - Frames Received OK Statistic Register
#define	ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)

IEEE_R_CRC - Frames Received with CRC Error Statistic Register
#define	ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_CRC_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)

IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
#define	ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)

IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
#define	ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)

IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
#define	ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)

IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
#define	ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)

#define	ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)

ATCR - Adjustable Timer Control Register
#define	ENET_ATCR_EN_MASK (0x1U)

#define	ENET_ATCR_EN_SHIFT (0U)

#define	ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

#define	ENET_ATCR_OFFEN_MASK (0x4U)

#define	ENET_ATCR_OFFEN_SHIFT (2U)

#define	ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

#define	ENET_ATCR_OFFRST_MASK (0x8U)

#define	ENET_ATCR_OFFRST_SHIFT (3U)

#define	ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

#define	ENET_ATCR_PEREN_MASK (0x10U)

#define	ENET_ATCR_PEREN_SHIFT (4U)

#define	ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

#define	ENET_ATCR_PINPER_MASK (0x80U)

#define	ENET_ATCR_PINPER_SHIFT (7U)

#define	ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

#define	ENET_ATCR_RESTART_MASK (0x200U)

#define	ENET_ATCR_RESTART_SHIFT (9U)

#define	ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)

#define	ENET_ATCR_CAPTURE_MASK (0x800U)

#define	ENET_ATCR_CAPTURE_SHIFT (11U)

#define	ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

#define	ENET_ATCR_SLAVE_MASK (0x2000U)

#define	ENET_ATCR_SLAVE_SHIFT (13U)

#define	ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

ATVR - Timer Value Register
#define	ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)

#define	ENET_ATVR_ATIME_SHIFT (0U)

#define	ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)

ATOFF - Timer Offset Register
#define	ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)

#define	ENET_ATOFF_OFFSET_SHIFT (0U)

#define	ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)

ATPER - Timer Period Register
#define	ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)

#define	ENET_ATPER_PERIOD_SHIFT (0U)

#define	ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)

ATCOR - Timer Correction Register
#define	ENET_ATCOR_COR_MASK (0x7FFFFFFFU)

#define	ENET_ATCOR_COR_SHIFT (0U)

#define	ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)

ATINC - Time-Stamping Clock Period Register
#define	ENET_ATINC_INC_MASK (0x7FU)

#define	ENET_ATINC_INC_SHIFT (0U)

#define	ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)

#define	ENET_ATINC_INC_CORR_MASK (0x7F00U)

#define	ENET_ATINC_INC_CORR_SHIFT (8U)

#define	ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)

ATSTMP - Timestamp of Last Transmitted Frame
#define	ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)

#define	ENET_ATSTMP_TIMESTAMP_SHIFT (0U)

#define	ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)

TGSR - Timer Global Status Register
#define	ENET_TGSR_TF0_MASK (0x1U)

#define	ENET_TGSR_TF0_SHIFT (0U)

#define	ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)

#define	ENET_TGSR_TF1_MASK (0x2U)

#define	ENET_TGSR_TF1_SHIFT (1U)

#define	ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)

#define	ENET_TGSR_TF2_MASK (0x4U)

#define	ENET_TGSR_TF2_SHIFT (2U)

#define	ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)

#define	ENET_TGSR_TF3_MASK (0x8U)

#define	ENET_TGSR_TF3_SHIFT (3U)

#define	ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)

TCSR - Timer Control Status Register
#define	ENET_TCSR_TDRE_MASK (0x1U)

#define	ENET_TCSR_TDRE_SHIFT (0U)

#define	ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

#define	ENET_TCSR_TMODE_MASK (0x3CU)

#define	ENET_TCSR_TMODE_SHIFT (2U)

#define	ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

#define	ENET_TCSR_TIE_MASK (0x40U)

#define	ENET_TCSR_TIE_SHIFT (6U)

#define	ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

#define	ENET_TCSR_TF_MASK (0x80U)

#define	ENET_TCSR_TF_SHIFT (7U)

#define	ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

#define	ENET_TCSR_TPWC_MASK (0xF800U)

#define	ENET_TCSR_TPWC_SHIFT (11U)

#define	ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)

TCCR - Timer Compare Capture Register
#define	ENET_TCCR_TCC_MASK (0xFFFFFFFFU)

#define	ENET_TCCR_TCC_SHIFT (0U)

#define	ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)

EIR - Interrupt Event Register
#define	ENET_EIR_RXB1_MASK (0x1U)

#define	ENET_EIR_RXB1_SHIFT (0U)

#define	ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)

#define	ENET_EIR_RXF1_MASK (0x2U)

#define	ENET_EIR_RXF1_SHIFT (1U)

#define	ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)

#define	ENET_EIR_TXB1_MASK (0x4U)

#define	ENET_EIR_TXB1_SHIFT (2U)

#define	ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)

#define	ENET_EIR_TXF1_MASK (0x8U)

#define	ENET_EIR_TXF1_SHIFT (3U)

#define	ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)

#define	ENET_EIR_RXB2_MASK (0x10U)

#define	ENET_EIR_RXB2_SHIFT (4U)

#define	ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)

#define	ENET_EIR_RXF2_MASK (0x20U)

#define	ENET_EIR_RXF2_SHIFT (5U)

#define	ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)

#define	ENET_EIR_TXB2_MASK (0x40U)

#define	ENET_EIR_TXB2_SHIFT (6U)

#define	ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)

#define	ENET_EIR_TXF2_MASK (0x80U)

#define	ENET_EIR_TXF2_SHIFT (7U)

#define	ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)

#define	ENET_EIR_RXFLUSH_0_MASK (0x1000U)

#define	ENET_EIR_RXFLUSH_0_SHIFT (12U)

#define	ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)

#define	ENET_EIR_RXFLUSH_1_MASK (0x2000U)

#define	ENET_EIR_RXFLUSH_1_SHIFT (13U)

#define	ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)

#define	ENET_EIR_RXFLUSH_2_MASK (0x4000U)

#define	ENET_EIR_RXFLUSH_2_SHIFT (14U)

#define	ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)

#define	ENET_EIR_TS_TIMER_MASK (0x8000U)

#define	ENET_EIR_TS_TIMER_SHIFT (15U)

#define	ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)

#define	ENET_EIR_TS_AVAIL_MASK (0x10000U)

#define	ENET_EIR_TS_AVAIL_SHIFT (16U)

#define	ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)

#define	ENET_EIR_WAKEUP_MASK (0x20000U)

#define	ENET_EIR_WAKEUP_SHIFT (17U)

#define	ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)

#define	ENET_EIR_PLR_MASK (0x40000U)

#define	ENET_EIR_PLR_SHIFT (18U)

#define	ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)

#define	ENET_EIR_UN_MASK (0x80000U)

#define	ENET_EIR_UN_SHIFT (19U)

#define	ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)

#define	ENET_EIR_RL_MASK (0x100000U)

#define	ENET_EIR_RL_SHIFT (20U)

#define	ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)

#define	ENET_EIR_LC_MASK (0x200000U)

#define	ENET_EIR_LC_SHIFT (21U)

#define	ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)

#define	ENET_EIR_EBERR_MASK (0x400000U)

#define	ENET_EIR_EBERR_SHIFT (22U)

#define	ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)

#define	ENET_EIR_MII_MASK (0x800000U)

#define	ENET_EIR_MII_SHIFT (23U)

#define	ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)

#define	ENET_EIR_RXB_MASK (0x1000000U)

#define	ENET_EIR_RXB_SHIFT (24U)

#define	ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)

#define	ENET_EIR_RXF_MASK (0x2000000U)

#define	ENET_EIR_RXF_SHIFT (25U)

#define	ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)

#define	ENET_EIR_TXB_MASK (0x4000000U)

#define	ENET_EIR_TXB_SHIFT (26U)

#define	ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)

#define	ENET_EIR_TXF_MASK (0x8000000U)

#define	ENET_EIR_TXF_SHIFT (27U)

#define	ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)

#define	ENET_EIR_GRA_MASK (0x10000000U)

#define	ENET_EIR_GRA_SHIFT (28U)

#define	ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)

#define	ENET_EIR_BABT_MASK (0x20000000U)

#define	ENET_EIR_BABT_SHIFT (29U)

#define	ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)

#define	ENET_EIR_BABR_MASK (0x40000000U)

#define	ENET_EIR_BABR_SHIFT (30U)

#define	ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)

EIMR - Interrupt Mask Register
#define	ENET_EIMR_RXB1_MASK (0x1U)

#define	ENET_EIMR_RXB1_SHIFT (0U)

#define	ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)

#define	ENET_EIMR_RXF1_MASK (0x2U)

#define	ENET_EIMR_RXF1_SHIFT (1U)

#define	ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)

#define	ENET_EIMR_TXB1_MASK (0x4U)

#define	ENET_EIMR_TXB1_SHIFT (2U)

#define	ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)

#define	ENET_EIMR_TXF1_MASK (0x8U)

#define	ENET_EIMR_TXF1_SHIFT (3U)

#define	ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)

#define	ENET_EIMR_RXB2_MASK (0x10U)

#define	ENET_EIMR_RXB2_SHIFT (4U)

#define	ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)

#define	ENET_EIMR_RXF2_MASK (0x20U)

#define	ENET_EIMR_RXF2_SHIFT (5U)

#define	ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)

#define	ENET_EIMR_TXB2_MASK (0x40U)

#define	ENET_EIMR_TXB2_SHIFT (6U)

#define	ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)

#define	ENET_EIMR_TXF2_MASK (0x80U)

#define	ENET_EIMR_TXF2_SHIFT (7U)

#define	ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)

#define	ENET_EIMR_RXFLUSH_0_MASK (0x1000U)

#define	ENET_EIMR_RXFLUSH_0_SHIFT (12U)

#define	ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)

#define	ENET_EIMR_RXFLUSH_1_MASK (0x2000U)

#define	ENET_EIMR_RXFLUSH_1_SHIFT (13U)

#define	ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)

#define	ENET_EIMR_RXFLUSH_2_MASK (0x4000U)

#define	ENET_EIMR_RXFLUSH_2_SHIFT (14U)

#define	ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)

#define	ENET_EIMR_TS_TIMER_MASK (0x8000U)

#define	ENET_EIMR_TS_TIMER_SHIFT (15U)

#define	ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)

#define	ENET_EIMR_TS_AVAIL_MASK (0x10000U)

#define	ENET_EIMR_TS_AVAIL_SHIFT (16U)

#define	ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)

#define	ENET_EIMR_WAKEUP_MASK (0x20000U)

#define	ENET_EIMR_WAKEUP_SHIFT (17U)

#define	ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)

#define	ENET_EIMR_PLR_MASK (0x40000U)

#define	ENET_EIMR_PLR_SHIFT (18U)

#define	ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)

#define	ENET_EIMR_UN_MASK (0x80000U)

#define	ENET_EIMR_UN_SHIFT (19U)

#define	ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)

#define	ENET_EIMR_RL_MASK (0x100000U)

#define	ENET_EIMR_RL_SHIFT (20U)

#define	ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)

#define	ENET_EIMR_LC_MASK (0x200000U)

#define	ENET_EIMR_LC_SHIFT (21U)

#define	ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)

#define	ENET_EIMR_EBERR_MASK (0x400000U)

#define	ENET_EIMR_EBERR_SHIFT (22U)

#define	ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)

#define	ENET_EIMR_MII_MASK (0x800000U)

#define	ENET_EIMR_MII_SHIFT (23U)

#define	ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)

#define	ENET_EIMR_RXB_MASK (0x1000000U)

#define	ENET_EIMR_RXB_SHIFT (24U)

#define	ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)

#define	ENET_EIMR_RXF_MASK (0x2000000U)

#define	ENET_EIMR_RXF_SHIFT (25U)

#define	ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)

#define	ENET_EIMR_TXB_MASK (0x4000000U)

#define	ENET_EIMR_TXB_SHIFT (26U)

#define	ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

#define	ENET_EIMR_TXF_MASK (0x8000000U)

#define	ENET_EIMR_TXF_SHIFT (27U)

#define	ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

#define	ENET_EIMR_GRA_MASK (0x10000000U)

#define	ENET_EIMR_GRA_SHIFT (28U)

#define	ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

#define	ENET_EIMR_BABT_MASK (0x20000000U)

#define	ENET_EIMR_BABT_SHIFT (29U)

#define	ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

#define	ENET_EIMR_BABR_MASK (0x40000000U)

#define	ENET_EIMR_BABR_SHIFT (30U)

#define	ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

RDAR - Receive Descriptor Active Register - Ring 0
#define	ENET_RDAR_RDAR_MASK (0x1000000U)

#define	ENET_RDAR_RDAR_SHIFT (24U)

#define	ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)

TDAR - Transmit Descriptor Active Register - Ring 0
#define	ENET_TDAR_TDAR_MASK (0x1000000U)

#define	ENET_TDAR_TDAR_SHIFT (24U)

#define	ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)

ECR - Ethernet Control Register
#define	ENET_ECR_RESET_MASK (0x1U)

#define	ENET_ECR_RESET_SHIFT (0U)

#define	ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)

#define	ENET_ECR_ETHEREN_MASK (0x2U)

#define	ENET_ECR_ETHEREN_SHIFT (1U)

#define	ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

#define	ENET_ECR_MAGICEN_MASK (0x4U)

#define	ENET_ECR_MAGICEN_SHIFT (2U)

#define	ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

#define	ENET_ECR_SLEEP_MASK (0x8U)

#define	ENET_ECR_SLEEP_SHIFT (3U)

#define	ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

#define	ENET_ECR_EN1588_MASK (0x10U)

#define	ENET_ECR_EN1588_SHIFT (4U)

#define	ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

#define	ENET_ECR_SPEED_MASK (0x20U)

#define	ENET_ECR_SPEED_SHIFT (5U)

#define	ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)

#define	ENET_ECR_DBGEN_MASK (0x40U)

#define	ENET_ECR_DBGEN_SHIFT (6U)

#define	ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

#define	ENET_ECR_DBSWP_MASK (0x100U)

#define	ENET_ECR_DBSWP_SHIFT (8U)

#define	ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

#define	ENET_ECR_SVLANEN_MASK (0x200U)

#define	ENET_ECR_SVLANEN_SHIFT (9U)

#define	ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)

#define	ENET_ECR_VLANUSE2ND_MASK (0x400U)

#define	ENET_ECR_VLANUSE2ND_SHIFT (10U)

#define	ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)

#define	ENET_ECR_SVLANDBL_MASK (0x800U)

#define	ENET_ECR_SVLANDBL_SHIFT (11U)

#define	ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)

#define	ENET_ECR_TXC_DLY_MASK (0x10000U)

#define	ENET_ECR_TXC_DLY_SHIFT (16U)

#define	ENET_ECR_TXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)

MMFR - MII Management Frame Register
#define	ENET_MMFR_DATA_MASK (0xFFFFU)

#define	ENET_MMFR_DATA_SHIFT (0U)

#define	ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)

#define	ENET_MMFR_TA_MASK (0x30000U)

#define	ENET_MMFR_TA_SHIFT (16U)

#define	ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)

#define	ENET_MMFR_RA_MASK (0x7C0000U)

#define	ENET_MMFR_RA_SHIFT (18U)

#define	ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)

#define	ENET_MMFR_PA_MASK (0xF800000U)

#define	ENET_MMFR_PA_SHIFT (23U)

#define	ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)

#define	ENET_MMFR_OP_MASK (0x30000000U)

#define	ENET_MMFR_OP_SHIFT (28U)

#define	ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)

#define	ENET_MMFR_ST_MASK (0xC0000000U)

#define	ENET_MMFR_ST_SHIFT (30U)

#define	ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)

MSCR - MII Speed Control Register
#define	ENET_MSCR_MII_SPEED_MASK (0x7EU)

#define	ENET_MSCR_MII_SPEED_SHIFT (1U)

#define	ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)

#define	ENET_MSCR_DIS_PRE_MASK (0x80U)

#define	ENET_MSCR_DIS_PRE_SHIFT (7U)

#define	ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

#define	ENET_MSCR_HOLDTIME_MASK (0x700U)

#define	ENET_MSCR_HOLDTIME_SHIFT (8U)

#define	ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

MIBC - MIB Control Register
#define	ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)

#define	ENET_MIBC_MIB_CLEAR_SHIFT (29U)

#define	ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

#define	ENET_MIBC_MIB_IDLE_MASK (0x40000000U)

#define	ENET_MIBC_MIB_IDLE_SHIFT (30U)

#define	ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

#define	ENET_MIBC_MIB_DIS_MASK (0x80000000U)

#define	ENET_MIBC_MIB_DIS_SHIFT (31U)

#define	ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

RCR - Receive Control Register
#define	ENET_RCR_LOOP_MASK (0x1U)

#define	ENET_RCR_LOOP_SHIFT (0U)

#define	ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

#define	ENET_RCR_DRT_MASK (0x2U)

#define	ENET_RCR_DRT_SHIFT (1U)

#define	ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

#define	ENET_RCR_MII_MODE_MASK (0x4U)

#define	ENET_RCR_MII_MODE_SHIFT (2U)

#define	ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

#define	ENET_RCR_PROM_MASK (0x8U)

#define	ENET_RCR_PROM_SHIFT (3U)

#define	ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

#define	ENET_RCR_BC_REJ_MASK (0x10U)

#define	ENET_RCR_BC_REJ_SHIFT (4U)

#define	ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)

#define	ENET_RCR_FCE_MASK (0x20U)

#define	ENET_RCR_FCE_SHIFT (5U)

#define	ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)

#define	ENET_RCR_RGMII_EN_MASK (0x40U)

#define	ENET_RCR_RGMII_EN_SHIFT (6U)

#define	ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)

#define	ENET_RCR_RMII_MODE_MASK (0x100U)

#define	ENET_RCR_RMII_MODE_SHIFT (8U)

#define	ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

#define	ENET_RCR_RMII_10T_MASK (0x200U)

#define	ENET_RCR_RMII_10T_SHIFT (9U)

#define	ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

#define	ENET_RCR_PADEN_MASK (0x1000U)

#define	ENET_RCR_PADEN_SHIFT (12U)

#define	ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

#define	ENET_RCR_PAUFWD_MASK (0x2000U)

#define	ENET_RCR_PAUFWD_SHIFT (13U)

#define	ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

#define	ENET_RCR_CRCFWD_MASK (0x4000U)

#define	ENET_RCR_CRCFWD_SHIFT (14U)

#define	ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

#define	ENET_RCR_CFEN_MASK (0x8000U)

#define	ENET_RCR_CFEN_SHIFT (15U)

#define	ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

#define	ENET_RCR_MAX_FL_MASK (0x3FFF0000U)

#define	ENET_RCR_MAX_FL_SHIFT (16U)

#define	ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)

#define	ENET_RCR_NLC_MASK (0x40000000U)

#define	ENET_RCR_NLC_SHIFT (30U)

#define	ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

#define	ENET_RCR_GRS_MASK (0x80000000U)

#define	ENET_RCR_GRS_SHIFT (31U)

#define	ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)

TCR - Transmit Control Register
#define	ENET_TCR_GTS_MASK (0x1U)

#define	ENET_TCR_GTS_SHIFT (0U)

#define	ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)

#define	ENET_TCR_FDEN_MASK (0x4U)

#define	ENET_TCR_FDEN_SHIFT (2U)

#define	ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)

#define	ENET_TCR_TFC_PAUSE_MASK (0x8U)

#define	ENET_TCR_TFC_PAUSE_SHIFT (3U)

#define	ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

#define	ENET_TCR_RFC_PAUSE_MASK (0x10U)

#define	ENET_TCR_RFC_PAUSE_SHIFT (4U)

#define	ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)

#define	ENET_TCR_ADDSEL_MASK (0xE0U)

#define	ENET_TCR_ADDSEL_SHIFT (5U)

#define	ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

#define	ENET_TCR_ADDINS_MASK (0x100U)

#define	ENET_TCR_ADDINS_SHIFT (8U)

#define	ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

#define	ENET_TCR_CRCFWD_MASK (0x200U)

#define	ENET_TCR_CRCFWD_SHIFT (9U)

#define	ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

PALR - Physical Address Lower Register
#define	ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)

#define	ENET_PALR_PADDR1_SHIFT (0U)

#define	ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)

PAUR - Physical Address Upper Register
#define	ENET_PAUR_TYPE_MASK (0xFFFFU)

#define	ENET_PAUR_TYPE_SHIFT (0U)

#define	ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)

#define	ENET_PAUR_PADDR2_MASK (0xFFFF0000U)

#define	ENET_PAUR_PADDR2_SHIFT (16U)

#define	ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)

OPD - Opcode/Pause Duration Register
#define	ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)

#define	ENET_OPD_PAUSE_DUR_SHIFT (0U)

#define	ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)

#define	ENET_OPD_OPCODE_MASK (0xFFFF0000U)

#define	ENET_OPD_OPCODE_SHIFT (16U)

#define	ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)

TXIC - Transmit Interrupt Coalescing Register
#define	ENET_TXIC_ICTT_MASK (0xFFFFU)

#define	ENET_TXIC_ICTT_SHIFT (0U)

#define	ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)

#define	ENET_TXIC_ICFT_MASK (0xFF00000U)

#define	ENET_TXIC_ICFT_SHIFT (20U)

#define	ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)

#define	ENET_TXIC_ICCS_MASK (0x40000000U)

#define	ENET_TXIC_ICCS_SHIFT (30U)

#define	ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)

#define	ENET_TXIC_ICEN_MASK (0x80000000U)

#define	ENET_TXIC_ICEN_SHIFT (31U)

#define	ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)

RXIC - Receive Interrupt Coalescing Register
#define	ENET_RXIC_ICTT_MASK (0xFFFFU)

#define	ENET_RXIC_ICTT_SHIFT (0U)

#define	ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)

#define	ENET_RXIC_ICFT_MASK (0xFF00000U)

#define	ENET_RXIC_ICFT_SHIFT (20U)

#define	ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)

#define	ENET_RXIC_ICCS_MASK (0x40000000U)

#define	ENET_RXIC_ICCS_SHIFT (30U)

#define	ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)

#define	ENET_RXIC_ICEN_MASK (0x80000000U)

#define	ENET_RXIC_ICEN_SHIFT (31U)

#define	ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)

IAUR - Descriptor Individual Upper Address Register
#define	ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)

#define	ENET_IAUR_IADDR1_SHIFT (0U)

#define	ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)

IALR - Descriptor Individual Lower Address Register
#define	ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)

#define	ENET_IALR_IADDR2_SHIFT (0U)

#define	ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)

GAUR - Descriptor Group Upper Address Register
#define	ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)

#define	ENET_GAUR_GADDR1_SHIFT (0U)

#define	ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)

GALR - Descriptor Group Lower Address Register
#define	ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)

#define	ENET_GALR_GADDR2_SHIFT (0U)

#define	ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)

TFWR - Transmit FIFO Watermark Register
#define	ENET_TFWR_TFWR_MASK (0x3FU)

#define	ENET_TFWR_TFWR_SHIFT (0U)

#define	ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)

#define	ENET_TFWR_STRFWD_MASK (0x100U)

#define	ENET_TFWR_STRFWD_SHIFT (8U)

#define	ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)

RDSR1 - Receive Descriptor Ring 1 Start Register
#define	ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_RDSR1_R_DES_START_SHIFT (3U)

#define	ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)

TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register
#define	ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_TDSR1_X_DES_START_SHIFT (3U)

#define	ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)

MRBR1 - Maximum Receive Buffer Size Register - Ring 1
#define	ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U)

#define	ENET_MRBR1_R_BUF_SIZE_SHIFT (4U)

#define	ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)

RDSR2 - Receive Descriptor Ring 2 Start Register
#define	ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_RDSR2_R_DES_START_SHIFT (3U)

#define	ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)

TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register
#define	ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_TDSR2_X_DES_START_SHIFT (3U)

#define	ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)

MRBR2 - Maximum Receive Buffer Size Register - Ring 2
#define	ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U)

#define	ENET_MRBR2_R_BUF_SIZE_SHIFT (4U)

#define	ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)

RDSR - Receive Descriptor Ring 0 Start Register
#define	ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_RDSR_R_DES_START_SHIFT (3U)

#define	ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)

TDSR - Transmit Buffer Descriptor Ring 0 Start Register
#define	ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)

#define	ENET_TDSR_X_DES_START_SHIFT (3U)

#define	ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)

MRBR - Maximum Receive Buffer Size Register - Ring 0
#define	ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */

#define	ENET_MRBR_R_BUF_SIZE_SHIFT (4U)

#define	ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */

RSFL - Receive FIFO Section Full Threshold
#define	ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)

#define	ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RSEM - Receive FIFO Section Empty Threshold
#define	ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)

#define	ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)

#define	ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)

#define	ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)

RAEM - Receive FIFO Almost Empty Threshold
#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)

#define	ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RAFL - Receive FIFO Almost Full Threshold
#define	ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)

#define	ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TSEM - Transmit FIFO Section Empty Threshold
#define	ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)

#define	ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TAEM - Transmit FIFO Almost Empty Threshold
#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)

#define	ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TAFL - Transmit FIFO Almost Full Threshold
#define	ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)

#define	ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TIPG - Transmit Inter-Packet Gap
#define	ENET_TIPG_IPG_MASK (0x1FU)

#define	ENET_TIPG_IPG_SHIFT (0U)

#define	ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)

FTRL - Frame Truncation Length
#define	ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)

#define	ENET_FTRL_TRUNC_FL_SHIFT (0U)

#define	ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)

TACC - Transmit Accelerator Function Configuration
#define	ENET_TACC_SHIFT16_MASK (0x1U)

#define	ENET_TACC_SHIFT16_SHIFT (0U)

#define	ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

#define	ENET_TACC_IPCHK_MASK (0x8U)

#define	ENET_TACC_IPCHK_SHIFT (3U)

#define	ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

#define	ENET_TACC_PROCHK_MASK (0x10U)

#define	ENET_TACC_PROCHK_SHIFT (4U)

#define	ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

RACC - Receive Accelerator Function Configuration
#define	ENET_RACC_PADREM_MASK (0x1U)

#define	ENET_RACC_PADREM_SHIFT (0U)

#define	ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

#define	ENET_RACC_IPDIS_MASK (0x2U)

#define	ENET_RACC_IPDIS_SHIFT (1U)

#define	ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

#define	ENET_RACC_PRODIS_MASK (0x4U)

#define	ENET_RACC_PRODIS_SHIFT (2U)

#define	ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

#define	ENET_RACC_LINEDIS_MASK (0x40U)

#define	ENET_RACC_LINEDIS_SHIFT (6U)

#define	ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

#define	ENET_RACC_SHIFT16_MASK (0x80U)

#define	ENET_RACC_SHIFT16_SHIFT (7U)

#define	ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

RCMR - Receive Classification Match Register for Class n
#define	ENET_RCMR_CMP0_MASK (0x7U)

#define	ENET_RCMR_CMP0_SHIFT (0U)

#define	ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)

#define	ENET_RCMR_CMP1_MASK (0x70U)

#define	ENET_RCMR_CMP1_SHIFT (4U)

#define	ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)

#define	ENET_RCMR_CMP2_MASK (0x700U)

#define	ENET_RCMR_CMP2_SHIFT (8U)

#define	ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)

#define	ENET_RCMR_CMP3_MASK (0x7000U)

#define	ENET_RCMR_CMP3_SHIFT (12U)

#define	ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)

#define	ENET_RCMR_MATCHEN_MASK (0x10000U)

#define	ENET_RCMR_MATCHEN_SHIFT (16U)

#define	ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)

DMACFG - DMA Class Based Configuration
#define	ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU)

#define	ENET_DMACFG_IDLE_SLOPE_SHIFT (0U)

#define	ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)

#define	ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U)

#define	ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U)

#define	ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)

#define	ENET_DMACFG_CALC_NOIPG_MASK (0x20000U)

#define	ENET_DMACFG_CALC_NOIPG_SHIFT (17U)

#define	ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)

RDAR1 - Receive Descriptor Active Register - Ring 1
#define	ENET_RDAR1_RDAR_MASK (0x1000000U)

#define	ENET_RDAR1_RDAR_SHIFT (24U)

#define	ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)

TDAR1 - Transmit Descriptor Active Register - Ring 1
#define	ENET_TDAR1_TDAR_MASK (0x1000000U)

#define	ENET_TDAR1_TDAR_SHIFT (24U)

#define	ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)

RDAR2 - Receive Descriptor Active Register - Ring 2
#define	ENET_RDAR2_RDAR_MASK (0x1000000U)

#define	ENET_RDAR2_RDAR_SHIFT (24U)

#define	ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)

TDAR2 - Transmit Descriptor Active Register - Ring 2
#define	ENET_TDAR2_TDAR_MASK (0x1000000U)

#define	ENET_TDAR2_TDAR_SHIFT (24U)

#define	ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)

QOS - QOS Scheme
#define	ENET_QOS_TX_SCHEME_MASK (0x7U)

#define	ENET_QOS_TX_SCHEME_SHIFT (0U)

#define	ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)

#define	ENET_QOS_RX_FLUSH0_MASK (0x8U)

#define	ENET_QOS_RX_FLUSH0_SHIFT (3U)

#define	ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)

#define	ENET_QOS_RX_FLUSH1_MASK (0x10U)

#define	ENET_QOS_RX_FLUSH1_SHIFT (4U)

#define	ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)

#define	ENET_QOS_RX_FLUSH2_MASK (0x20U)

#define	ENET_QOS_RX_FLUSH2_SHIFT (5U)

#define	ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)

RMON_T_PACKETS - Tx Packet Count Statistic Register
#define	ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)

RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
#define	ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)

RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
#define	ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)

RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)

RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)

RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
#define	ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)

RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)

RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)

RMON_T_COL - Tx Collision Count Statistic Register
#define	ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_COL_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)

RMON_T_P64 - Tx 64-Byte Packets Statistic Register
#define	ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P64_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)

RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
#define	ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)

RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
#define	ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)

RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
#define	ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)

RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
#define	ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)

RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
#define	ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)

RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
#define	ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)

#define	ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)

#define	ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)

RMON_T_OCTETS - Tx Octets Statistic Register
#define	ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)

#define	ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)

#define	ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)

IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
#define	ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)

IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
#define	ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_1COL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)

IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
#define	ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)

IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
#define	ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_DEF_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)

IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
#define	ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)

IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
#define	ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)

IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
#define	ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)

IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
#define	ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)

IEEE_T_SQE - Reserved Statistic Register
#define	ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_SQE_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)

IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
#define	ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)

IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
#define	ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)

#define	ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)

RMON_R_PACKETS - Rx Packet Count Statistic Register
#define	ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)

#define	ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)

RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
#define	ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)

#define	ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)

RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
#define	ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)

#define	ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)

RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)

#define	ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)

RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
#define	ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)

#define	ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)

RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
#define	ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)

#define	ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)

RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_FRAG_COUNT_SHIFT (0U)

#define	ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)

RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_JAB_COUNT_SHIFT (0U)

#define	ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)

RMON_R_P64 - Rx 64-Byte Packets Statistic Register
#define	ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P64_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)

RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
#define	ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)

RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
#define	ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)

RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
#define	ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)

RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
#define	ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)

RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
#define	ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)

RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
#define	ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)

#define	ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)

#define	ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)

RMON_R_OCTETS - Rx Octets Statistic Register
#define	ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)

#define	ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)

#define	ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)

IEEE_R_DROP - Frames not Counted Correctly Statistic Register
#define	ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_DROP_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)

IEEE_R_FRAME_OK - Frames Received OK Statistic Register
#define	ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)

IEEE_R_CRC - Frames Received with CRC Error Statistic Register
#define	ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_CRC_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)

IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
#define	ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)

IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
#define	ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)

IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
#define	ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)

#define	ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)

IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
#define	ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)

#define	ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)

#define	ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)

ATCR - Adjustable Timer Control Register
#define	ENET_ATCR_EN_MASK (0x1U)

#define	ENET_ATCR_EN_SHIFT (0U)

#define	ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

#define	ENET_ATCR_OFFEN_MASK (0x4U)

#define	ENET_ATCR_OFFEN_SHIFT (2U)

#define	ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

#define	ENET_ATCR_OFFRST_MASK (0x8U)

#define	ENET_ATCR_OFFRST_SHIFT (3U)

#define	ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

#define	ENET_ATCR_PEREN_MASK (0x10U)

#define	ENET_ATCR_PEREN_SHIFT (4U)

#define	ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

#define	ENET_ATCR_PINPER_MASK (0x80U)

#define	ENET_ATCR_PINPER_SHIFT (7U)

#define	ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

#define	ENET_ATCR_RESTART_MASK (0x200U)

#define	ENET_ATCR_RESTART_SHIFT (9U)

#define	ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)

#define	ENET_ATCR_CAPTURE_MASK (0x800U)

#define	ENET_ATCR_CAPTURE_SHIFT (11U)

#define	ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

#define	ENET_ATCR_SLAVE_MASK (0x2000U)

#define	ENET_ATCR_SLAVE_SHIFT (13U)

#define	ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

ATVR - Timer Value Register
#define	ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)

#define	ENET_ATVR_ATIME_SHIFT (0U)

#define	ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)

ATOFF - Timer Offset Register
#define	ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)

#define	ENET_ATOFF_OFFSET_SHIFT (0U)

#define	ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)

ATPER - Timer Period Register
#define	ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)

#define	ENET_ATPER_PERIOD_SHIFT (0U)

#define	ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)

ATCOR - Timer Correction Register
#define	ENET_ATCOR_COR_MASK (0x7FFFFFFFU)

#define	ENET_ATCOR_COR_SHIFT (0U)

#define	ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)

ATINC - Time-Stamping Clock Period Register
#define	ENET_ATINC_INC_MASK (0x7FU)

#define	ENET_ATINC_INC_SHIFT (0U)

#define	ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)

#define	ENET_ATINC_INC_CORR_MASK (0x7F00U)

#define	ENET_ATINC_INC_CORR_SHIFT (8U)

#define	ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)

ATSTMP - Timestamp of Last Transmitted Frame
#define	ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)

#define	ENET_ATSTMP_TIMESTAMP_SHIFT (0U)

#define	ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)

TGSR - Timer Global Status Register
#define	ENET_TGSR_TF0_MASK (0x1U)

#define	ENET_TGSR_TF0_SHIFT (0U)

#define	ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)

#define	ENET_TGSR_TF1_MASK (0x2U)

#define	ENET_TGSR_TF1_SHIFT (1U)

#define	ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)

#define	ENET_TGSR_TF2_MASK (0x4U)

#define	ENET_TGSR_TF2_SHIFT (2U)

#define	ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)

#define	ENET_TGSR_TF3_MASK (0x8U)

#define	ENET_TGSR_TF3_SHIFT (3U)

#define	ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)

TCSR - Timer Control Status Register
#define	ENET_TCSR_TDRE_MASK (0x1U)

#define	ENET_TCSR_TDRE_SHIFT (0U)

#define	ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

#define	ENET_TCSR_TMODE_MASK (0x3CU)

#define	ENET_TCSR_TMODE_SHIFT (2U)

#define	ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

#define	ENET_TCSR_TIE_MASK (0x40U)

#define	ENET_TCSR_TIE_SHIFT (6U)

#define	ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

#define	ENET_TCSR_TF_MASK (0x80U)

#define	ENET_TCSR_TF_SHIFT (7U)

#define	ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

#define	ENET_TCSR_TPWC_MASK (0xF800U)

#define	ENET_TCSR_TPWC_SHIFT (11U)

#define	ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)

TCCR - Timer Compare Capture Register
#define	ENET_TCCR_TCC_MASK (0xFFFFFFFFU)

#define	ENET_TCCR_TCC_SHIFT (0U)

#define	ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)

Detailed Description

Macro Definition Documentation

◆ ENET_ATCOR_COR [1/3]

#define ENET_ATCOR_COR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)

COR - Correction Counter Wrap-Around Value

◆ ENET_ATCOR_COR [2/3]

#define ENET_ATCOR_COR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)

COR - Correction Counter Wrap-Around Value

◆ ENET_ATCOR_COR [3/3]

#define ENET_ATCOR_COR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)

COR - Correction Counter Wrap-Around Value

◆ ENET_ATCR_CAPTURE [1/3]

#define ENET_ATCR_CAPTURE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.

◆ ENET_ATCR_CAPTURE [2/3]

#define ENET_ATCR_CAPTURE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.

◆ ENET_ATCR_CAPTURE [3/3]

#define ENET_ATCR_CAPTURE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.

◆ ENET_ATCR_EN [1/3]

#define ENET_ATCR_EN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.

◆ ENET_ATCR_EN [2/3]

#define ENET_ATCR_EN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.

◆ ENET_ATCR_EN [3/3]

#define ENET_ATCR_EN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.

◆ ENET_ATCR_OFFEN [1/3]

#define ENET_ATCR_OFFEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.

◆ ENET_ATCR_OFFEN [2/3]

#define ENET_ATCR_OFFEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.

◆ ENET_ATCR_OFFEN [3/3]

#define ENET_ATCR_OFFEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.

◆ ENET_ATCR_OFFRST [1/3]

#define ENET_ATCR_OFFRST ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.

◆ ENET_ATCR_OFFRST [2/3]

#define ENET_ATCR_OFFRST ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.

◆ ENET_ATCR_OFFRST [3/3]

#define ENET_ATCR_OFFRST ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.

◆ ENET_ATCR_PEREN [1/3]

#define ENET_ATCR_PEREN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.

◆ ENET_ATCR_PEREN [2/3]

#define ENET_ATCR_PEREN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.

◆ ENET_ATCR_PEREN [3/3]

#define ENET_ATCR_PEREN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.

◆ ENET_ATCR_PINPER [1/3]

#define ENET_ATCR_PINPER ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

PINPER - Enables event signal output external pin frc_evt_period assertion on period event 0b0..Disable. 0b1..Enable.

◆ ENET_ATCR_PINPER [2/3]

#define ENET_ATCR_PINPER ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

PINPER - Enables event signal output external pin frc_evt_period assertion on period event 0b0..Disable. 0b1..Enable.

◆ ENET_ATCR_PINPER [3/3]

#define ENET_ATCR_PINPER ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

PINPER - Enables event signal output external pin frc_evt_period assertion on period event 0b0..Disable. 0b1..Enable.

◆ ENET_ATCR_RESTART [1/3]

#define ENET_ATCR_RESTART ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)

RESTART - Reset Timer

◆ ENET_ATCR_RESTART [2/3]

#define ENET_ATCR_RESTART ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)

RESTART - Reset Timer

◆ ENET_ATCR_RESTART [3/3]

#define ENET_ATCR_RESTART ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)

RESTART - Reset Timer

◆ ENET_ATCR_SLAVE [1/3]

#define ENET_ATCR_SLAVE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.

◆ ENET_ATCR_SLAVE [2/3]

#define ENET_ATCR_SLAVE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.

◆ ENET_ATCR_SLAVE [3/3]

#define ENET_ATCR_SLAVE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.

◆ ENET_ATINC_INC [1/3]

#define ENET_ATINC_INC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)

INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds

◆ ENET_ATINC_INC [2/3]

#define ENET_ATINC_INC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)

INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds

◆ ENET_ATINC_INC [3/3]

#define ENET_ATINC_INC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)

INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds

◆ ENET_ATINC_INC_CORR [1/3]

#define ENET_ATINC_INC_CORR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)

INC_CORR - Correction Increment Value

◆ ENET_ATINC_INC_CORR [2/3]

#define ENET_ATINC_INC_CORR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)

INC_CORR - Correction Increment Value

◆ ENET_ATINC_INC_CORR [3/3]

#define ENET_ATINC_INC_CORR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)

INC_CORR - Correction Increment Value

◆ ENET_ATPER_PERIOD [1/3]

#define ENET_ATPER_PERIOD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)

PERIOD - Value for generating periodic events

◆ ENET_ATPER_PERIOD [2/3]

#define ENET_ATPER_PERIOD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)

PERIOD - Value for generating periodic events

◆ ENET_ATPER_PERIOD [3/3]

#define ENET_ATPER_PERIOD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)

PERIOD - Value for generating periodic events

◆ ENET_ATSTMP_TIMESTAMP [1/3]

#define ENET_ATSTMP_TIMESTAMP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)

TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the ff_tx_ts_frm signal asserted from the user application

◆ ENET_ATSTMP_TIMESTAMP [2/3]

#define ENET_ATSTMP_TIMESTAMP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)

TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the ff_tx_ts_frm signal asserted from the user application

◆ ENET_ATSTMP_TIMESTAMP [3/3]

#define ENET_ATSTMP_TIMESTAMP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)

TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the ff_tx_ts_frm signal asserted from the user application

◆ ENET_DMACFG_CALC_NOIPG [1/2]

#define ENET_DMACFG_CALC_NOIPG ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)

CALC_NOIPG - Calculate no IPG 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations. This is the default. 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping, when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames will become more bandwidth than large frames due to the relation of data to IPG overhead).

◆ ENET_DMACFG_CALC_NOIPG [2/2]

#define ENET_DMACFG_CALC_NOIPG ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)

CALC_NOIPG - Calculate no IPG 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred for a frame when doing bandwidth calculations. This is the default. 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping, when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames will become more bandwidth than large frames due to the relation of data to IPG overhead).

◆ ENET_DMACFG_DMA_CLASS_EN [1/2]

#define ENET_DMACFG_DMA_CLASS_EN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)

DMA_CLASS_EN - DMA class enable 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2 queues are disabled then their frames will be placed in queue 0. 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.

◆ ENET_DMACFG_DMA_CLASS_EN [2/2]

#define ENET_DMACFG_DMA_CLASS_EN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)

DMA_CLASS_EN - DMA class enable 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2 queues are disabled then their frames will be placed in queue 0. 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.

◆ ENET_DMACFG_IDLE_SLOPE [1/2]

#define ENET_DMACFG_IDLE_SLOPE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)

IDLE_SLOPE - Idle slope

◆ ENET_DMACFG_IDLE_SLOPE [2/2]

#define ENET_DMACFG_IDLE_SLOPE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)

IDLE_SLOPE - Idle slope

◆ ENET_ECR_DBGEN [1/3]

#define ENET_ECR_DBGEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.

◆ ENET_ECR_DBGEN [2/3]

#define ENET_ECR_DBGEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.

◆ ENET_ECR_DBGEN [3/3]

#define ENET_ECR_DBGEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.

◆ ENET_ECR_DBSWP [1/3]

#define ENET_ECR_DBSWP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.

◆ ENET_ECR_DBSWP [2/3]

#define ENET_ECR_DBSWP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.

◆ ENET_ECR_DBSWP [3/3]

#define ENET_ECR_DBSWP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.

◆ ENET_ECR_EN1588 [1/3]

#define ENET_ECR_EN1588 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.

◆ ENET_ECR_EN1588 [2/3]

#define ENET_ECR_EN1588 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.

◆ ENET_ECR_EN1588 [3/3]

#define ENET_ECR_EN1588 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.

◆ ENET_ECR_ETHEREN [1/3]

#define ENET_ECR_ETHEREN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.

◆ ENET_ECR_ETHEREN [2/3]

#define ENET_ECR_ETHEREN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.

◆ ENET_ECR_ETHEREN [3/3]

#define ENET_ECR_ETHEREN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.

◆ ENET_ECR_MAGICEN [1/3]

#define ENET_ECR_MAGICEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.

◆ ENET_ECR_MAGICEN [2/3]

#define ENET_ECR_MAGICEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.

◆ ENET_ECR_MAGICEN [3/3]

#define ENET_ECR_MAGICEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.

◆ ENET_ECR_RESET [1/3]

#define ENET_ECR_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)

RESET - Ethernet MAC Reset

◆ ENET_ECR_RESET [2/3]

#define ENET_ECR_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)

RESET - Ethernet MAC Reset

◆ ENET_ECR_RESET [3/3]

#define ENET_ECR_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)

RESET - Ethernet MAC Reset

◆ ENET_ECR_SLEEP [1/3]

#define ENET_ECR_SLEEP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.

◆ ENET_ECR_SLEEP [2/3]

#define ENET_ECR_SLEEP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.

◆ ENET_ECR_SLEEP [3/3]

#define ENET_ECR_SLEEP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.

◆ ENET_ECR_SPEED [1/2]

#define ENET_ECR_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)

SPEED 0b0..10/100-Mbit/s mode 0b1..1000-Mbit/s mode

◆ ENET_ECR_SPEED [2/2]

#define ENET_ECR_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)

SPEED 0b0..10/100-Mbit/s mode 0b1..1000-Mbit/s mode

◆ ENET_ECR_SVLANDBL [1/2]

#define ENET_ECR_SVLANDBL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)

SVLANDBL - S-VLAN double tag 0b0..Disable S-VLAN double tag 0b1..Enable S-VLAN double tag

◆ ENET_ECR_SVLANDBL [2/2]

#define ENET_ECR_SVLANDBL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)

SVLANDBL - S-VLAN double tag 0b0..Disable S-VLAN double tag 0b1..Enable S-VLAN double tag

◆ ENET_ECR_SVLANEN [1/2]

#define ENET_ECR_SVLANEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)

SVLANEN - S-VLAN enable 0b0..Only the EtherType 0x8100 will be considered for VLAN detection. 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the classification match comparators, RCMRn.

◆ ENET_ECR_SVLANEN [2/2]

#define ENET_ECR_SVLANEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)

SVLANEN - S-VLAN enable 0b0..Only the EtherType 0x8100 will be considered for VLAN detection. 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the classification match comparators, RCMRn.

◆ ENET_ECR_TXC_DLY [1/2]

#define ENET_ECR_TXC_DLY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)

TXC_DLY - Transmit clock delay 0b0..RGMII_TXC is not delayed. 0b1..Generate delayed version of RGMII_TXC.

◆ ENET_ECR_TXC_DLY [2/2]

#define ENET_ECR_TXC_DLY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)

TXC_DLY - Transmit clock delay 0b0..RGMII_TXC is not delayed. 0b1..Generate delayed version of RGMII_TXC.

◆ ENET_ECR_VLANUSE2ND [1/2]

#define ENET_ECR_VLANUSE2ND ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)

VLANUSE2ND - VLAN use second tag 0b0..Always extract data from the first VLAN tag if it exists. 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The second tag must be a C-VLAN

◆ ENET_ECR_VLANUSE2ND [2/2]

#define ENET_ECR_VLANUSE2ND ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)

VLANUSE2ND - VLAN use second tag 0b0..Always extract data from the first VLAN tag if it exists. 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The second tag must be a C-VLAN

◆ ENET_EIMR_BABR [1/3]

#define ENET_EIMR_BABR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_BABR [2/3]

#define ENET_EIMR_BABR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_BABR [3/3]

#define ENET_EIMR_BABR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_BABT [1/3]

#define ENET_EIMR_BABT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_BABT [2/3]

#define ENET_EIMR_BABT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_BABT [3/3]

#define ENET_EIMR_BABT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_EBERR [1/3]

#define ENET_EIMR_EBERR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)

EBERR - EBERR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_EBERR [2/3]

#define ENET_EIMR_EBERR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)

EBERR - EBERR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_EBERR [3/3]

#define ENET_EIMR_EBERR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)

EBERR - EBERR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_GRA [1/3]

#define ENET_EIMR_GRA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_GRA [2/3]

#define ENET_EIMR_GRA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_GRA [3/3]

#define ENET_EIMR_GRA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_LC [1/3]

#define ENET_EIMR_LC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)

LC - LC Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_LC [2/3]

#define ENET_EIMR_LC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)

LC - LC Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_LC [3/3]

#define ENET_EIMR_LC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)

LC - LC Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_MII [1/3]

#define ENET_EIMR_MII ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)

MII - MII Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_MII [2/3]

#define ENET_EIMR_MII ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)

MII - MII Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_MII [3/3]

#define ENET_EIMR_MII ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)

MII - MII Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_PLR [1/3]

#define ENET_EIMR_PLR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)

PLR - PLR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_PLR [2/3]

#define ENET_EIMR_PLR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)

PLR - PLR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_PLR [3/3]

#define ENET_EIMR_PLR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)

PLR - PLR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RL [1/3]

#define ENET_EIMR_RL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)

RL - RL Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RL [2/3]

#define ENET_EIMR_RL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)

RL - RL Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RL [3/3]

#define ENET_EIMR_RL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)

RL - RL Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXB [1/3]

#define ENET_EIMR_RXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)

RXB - RXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXB [2/3]

#define ENET_EIMR_RXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)

RXB - RXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXB [3/3]

#define ENET_EIMR_RXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)

RXB - RXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXB1 [1/2]

#define ENET_EIMR_RXB1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)

RXB1 - Receive buffer interrupt, class 1 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXB1 [2/2]

#define ENET_EIMR_RXB1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)

RXB1 - Receive buffer interrupt, class 1 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXB2 [1/2]

#define ENET_EIMR_RXB2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)

RXB2 - Receive buffer interrupt, class 2 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXB2 [2/2]

#define ENET_EIMR_RXB2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)

RXB2 - Receive buffer interrupt, class 2 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXF [1/3]

#define ENET_EIMR_RXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)

RXF - RXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXF [2/3]

#define ENET_EIMR_RXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)

RXF - RXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXF [3/3]

#define ENET_EIMR_RXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)

RXF - RXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXF1 [1/2]

#define ENET_EIMR_RXF1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)

RXF1 - Receive frame interrupt, class 1 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXF1 [2/2]

#define ENET_EIMR_RXF1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)

RXF1 - Receive frame interrupt, class 1 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXF2 [1/2]

#define ENET_EIMR_RXF2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)

RXF2 - Receive frame interrupt, class 2 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXF2 [2/2]

#define ENET_EIMR_RXF2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)

RXF2 - Receive frame interrupt, class 2 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXFLUSH_0 [1/2]

#define ENET_EIMR_RXFLUSH_0 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)

RXFLUSH_0 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXFLUSH_0 [2/2]

#define ENET_EIMR_RXFLUSH_0 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)

RXFLUSH_0 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXFLUSH_1 [1/2]

#define ENET_EIMR_RXFLUSH_1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)

RXFLUSH_1 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXFLUSH_1 [2/2]

#define ENET_EIMR_RXFLUSH_1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)

RXFLUSH_1 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXFLUSH_2 [1/2]

#define ENET_EIMR_RXFLUSH_2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)

RXFLUSH_2 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_RXFLUSH_2 [2/2]

#define ENET_EIMR_RXFLUSH_2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)

RXFLUSH_2 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TS_AVAIL [1/3]

#define ENET_EIMR_TS_AVAIL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)

TS_AVAIL - TS_AVAIL Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TS_AVAIL [2/3]

#define ENET_EIMR_TS_AVAIL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)

TS_AVAIL - TS_AVAIL Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TS_AVAIL [3/3]

#define ENET_EIMR_TS_AVAIL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)

TS_AVAIL - TS_AVAIL Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TS_TIMER [1/3]

#define ENET_EIMR_TS_TIMER ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)

TS_TIMER - TS_TIMER Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TS_TIMER [2/3]

#define ENET_EIMR_TS_TIMER ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)

TS_TIMER - TS_TIMER Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TS_TIMER [3/3]

#define ENET_EIMR_TS_TIMER ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)

TS_TIMER - TS_TIMER Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXB [1/3]

#define ENET_EIMR_TXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXB [2/3]

#define ENET_EIMR_TXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXB [3/3]

#define ENET_EIMR_TXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXB1 [1/2]

#define ENET_EIMR_TXB1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)

TXB1 - Transmit buffer interrupt, class 1 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXB1 [2/2]

#define ENET_EIMR_TXB1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)

TXB1 - Transmit buffer interrupt, class 1 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXB2 [1/2]

#define ENET_EIMR_TXB2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)

TXB2 - Transmit buffer interrupt, class 2 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXB2 [2/2]

#define ENET_EIMR_TXB2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)

TXB2 - Transmit buffer interrupt, class 2 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXF [1/3]

#define ENET_EIMR_TXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXF [2/3]

#define ENET_EIMR_TXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXF [3/3]

#define ENET_EIMR_TXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXF1 [1/2]

#define ENET_EIMR_TXF1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)

TXF1 - Transmit frame interrupt, class 1 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXF1 [2/2]

#define ENET_EIMR_TXF1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)

TXF1 - Transmit frame interrupt, class 1 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXF2 [1/2]

#define ENET_EIMR_TXF2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)

TXF2 - Transmit frame interrupt, class 2 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_TXF2 [2/2]

#define ENET_EIMR_TXF2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)

TXF2 - Transmit frame interrupt, class 2 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_UN [1/3]

#define ENET_EIMR_UN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)

UN - UN Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_UN [2/3]

#define ENET_EIMR_UN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)

UN - UN Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_UN [3/3]

#define ENET_EIMR_UN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)

UN - UN Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_WAKEUP [1/3]

#define ENET_EIMR_WAKEUP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)

WAKEUP - WAKEUP Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_WAKEUP [2/3]

#define ENET_EIMR_WAKEUP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)

WAKEUP - WAKEUP Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIMR_WAKEUP [3/3]

#define ENET_EIMR_WAKEUP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)

WAKEUP - WAKEUP Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

◆ ENET_EIR_BABR [1/3]

#define ENET_EIR_BABR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)

BABR - Babbling Receive Error

◆ ENET_EIR_BABR [2/3]

#define ENET_EIR_BABR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)

BABR - Babbling Receive Error

◆ ENET_EIR_BABR [3/3]

#define ENET_EIR_BABR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)

BABR - Babbling Receive Error

◆ ENET_EIR_BABT [1/3]

#define ENET_EIR_BABT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)

BABT - Babbling Transmit Error

◆ ENET_EIR_BABT [2/3]

#define ENET_EIR_BABT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)

BABT - Babbling Transmit Error

◆ ENET_EIR_BABT [3/3]

#define ENET_EIR_BABT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)

BABT - Babbling Transmit Error

◆ ENET_EIR_EBERR [1/3]

#define ENET_EIR_EBERR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)

EBERR - Ethernet Bus Error

◆ ENET_EIR_EBERR [2/3]

#define ENET_EIR_EBERR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)

EBERR - Ethernet Bus Error

◆ ENET_EIR_EBERR [3/3]

#define ENET_EIR_EBERR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)

EBERR - Ethernet Bus Error

◆ ENET_EIR_GRA [1/3]

#define ENET_EIR_GRA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)

GRA - Graceful Stop Complete

◆ ENET_EIR_GRA [2/3]

#define ENET_EIR_GRA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)

GRA - Graceful Stop Complete

◆ ENET_EIR_GRA [3/3]

#define ENET_EIR_GRA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)

GRA - Graceful Stop Complete

◆ ENET_EIR_LC [1/3]

#define ENET_EIR_LC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)

LC - Late Collision

◆ ENET_EIR_LC [2/3]

#define ENET_EIR_LC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)

LC - Late Collision

◆ ENET_EIR_LC [3/3]

#define ENET_EIR_LC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)

LC - Late Collision

◆ ENET_EIR_MII [1/3]

#define ENET_EIR_MII ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)

MII - MII Interrupt.

◆ ENET_EIR_MII [2/3]

#define ENET_EIR_MII ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)

MII - MII Interrupt.

◆ ENET_EIR_MII [3/3]

#define ENET_EIR_MII ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)

MII - MII Interrupt.

◆ ENET_EIR_PLR [1/3]

#define ENET_EIR_PLR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)

PLR - Payload Receive Error

◆ ENET_EIR_PLR [2/3]

#define ENET_EIR_PLR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)

PLR - Payload Receive Error

◆ ENET_EIR_PLR [3/3]

#define ENET_EIR_PLR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)

PLR - Payload Receive Error

◆ ENET_EIR_RL [1/3]

#define ENET_EIR_RL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)

RL - Collision Retry Limit

◆ ENET_EIR_RL [2/3]

#define ENET_EIR_RL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)

RL - Collision Retry Limit

◆ ENET_EIR_RL [3/3]

#define ENET_EIR_RL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)

RL - Collision Retry Limit

◆ ENET_EIR_RXB [1/3]

#define ENET_EIR_RXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)

RXB - Receive Buffer Interrupt

◆ ENET_EIR_RXB [2/3]

#define ENET_EIR_RXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)

RXB - Receive Buffer Interrupt

◆ ENET_EIR_RXB [3/3]

#define ENET_EIR_RXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)

RXB - Receive Buffer Interrupt

◆ ENET_EIR_RXB1 [1/2]

#define ENET_EIR_RXB1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)

RXB1 - Receive buffer interrupt, class 1

◆ ENET_EIR_RXB1 [2/2]

#define ENET_EIR_RXB1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)

RXB1 - Receive buffer interrupt, class 1

◆ ENET_EIR_RXB2 [1/2]

#define ENET_EIR_RXB2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)

RXB2 - Receive buffer interrupt, class 2

◆ ENET_EIR_RXB2 [2/2]

#define ENET_EIR_RXB2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)

RXB2 - Receive buffer interrupt, class 2

◆ ENET_EIR_RXF [1/3]

#define ENET_EIR_RXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)

RXF - Receive Frame Interrupt

◆ ENET_EIR_RXF [2/3]

#define ENET_EIR_RXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)

RXF - Receive Frame Interrupt

◆ ENET_EIR_RXF [3/3]

#define ENET_EIR_RXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)

RXF - Receive Frame Interrupt

◆ ENET_EIR_RXF1 [1/2]

#define ENET_EIR_RXF1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)

RXF1 - Receive frame interrupt, class 1

◆ ENET_EIR_RXF1 [2/2]

#define ENET_EIR_RXF1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)

RXF1 - Receive frame interrupt, class 1

◆ ENET_EIR_RXF2 [1/2]

#define ENET_EIR_RXF2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)

RXF2 - Receive frame interrupt, class 2

◆ ENET_EIR_RXF2 [2/2]

#define ENET_EIR_RXF2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)

RXF2 - Receive frame interrupt, class 2

◆ ENET_EIR_TS_AVAIL [1/3]

#define ENET_EIR_TS_AVAIL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)

TS_AVAIL - Transmit Timestamp Available

◆ ENET_EIR_TS_AVAIL [2/3]

#define ENET_EIR_TS_AVAIL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)

TS_AVAIL - Transmit Timestamp Available

◆ ENET_EIR_TS_AVAIL [3/3]

#define ENET_EIR_TS_AVAIL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)

TS_AVAIL - Transmit Timestamp Available

◆ ENET_EIR_TS_TIMER [1/3]

#define ENET_EIR_TS_TIMER ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)

TS_TIMER - Timestamp Timer

◆ ENET_EIR_TS_TIMER [2/3]

#define ENET_EIR_TS_TIMER ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)

TS_TIMER - Timestamp Timer

◆ ENET_EIR_TS_TIMER [3/3]

#define ENET_EIR_TS_TIMER ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)

TS_TIMER - Timestamp Timer

◆ ENET_EIR_TXB [1/3]

#define ENET_EIR_TXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)

TXB - Transmit Buffer Interrupt

◆ ENET_EIR_TXB [2/3]

#define ENET_EIR_TXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)

TXB - Transmit Buffer Interrupt

◆ ENET_EIR_TXB [3/3]

#define ENET_EIR_TXB ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)

TXB - Transmit Buffer Interrupt

◆ ENET_EIR_TXB1 [1/2]

#define ENET_EIR_TXB1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)

TXB1 - Transmit buffer interrupt, class 1

◆ ENET_EIR_TXB1 [2/2]

#define ENET_EIR_TXB1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)

TXB1 - Transmit buffer interrupt, class 1

◆ ENET_EIR_TXB2 [1/2]

#define ENET_EIR_TXB2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)

TXB2 - Transmit buffer interrupt, class 2

◆ ENET_EIR_TXB2 [2/2]

#define ENET_EIR_TXB2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)

TXB2 - Transmit buffer interrupt, class 2

◆ ENET_EIR_TXF [1/3]

#define ENET_EIR_TXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)

TXF - Transmit Frame Interrupt

◆ ENET_EIR_TXF [2/3]

#define ENET_EIR_TXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)

TXF - Transmit Frame Interrupt

◆ ENET_EIR_TXF [3/3]

#define ENET_EIR_TXF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)

TXF - Transmit Frame Interrupt

◆ ENET_EIR_TXF1 [1/2]

#define ENET_EIR_TXF1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)

TXF1 - Transmit frame interrupt, class 1

◆ ENET_EIR_TXF1 [2/2]

#define ENET_EIR_TXF1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)

TXF1 - Transmit frame interrupt, class 1

◆ ENET_EIR_TXF2 [1/2]

#define ENET_EIR_TXF2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)

TXF2 - Transmit frame interrupt, class 2

◆ ENET_EIR_TXF2 [2/2]

#define ENET_EIR_TXF2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)

TXF2 - Transmit frame interrupt, class 2

◆ ENET_EIR_UN [1/3]

#define ENET_EIR_UN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)

UN - Transmit FIFO Underrun

◆ ENET_EIR_UN [2/3]

#define ENET_EIR_UN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)

UN - Transmit FIFO Underrun

◆ ENET_EIR_UN [3/3]

#define ENET_EIR_UN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)

UN - Transmit FIFO Underrun

◆ ENET_EIR_WAKEUP [1/3]

#define ENET_EIR_WAKEUP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)

WAKEUP - Node Wakeup Request Indication

◆ ENET_EIR_WAKEUP [2/3]

#define ENET_EIR_WAKEUP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)

WAKEUP - Node Wakeup Request Indication

◆ ENET_EIR_WAKEUP [3/3]

#define ENET_EIR_WAKEUP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)

WAKEUP - Node Wakeup Request Indication

◆ ENET_FTRL_TRUNC_FL [1/3]

#define ENET_FTRL_TRUNC_FL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)

TRUNC_FL - Frame Truncation Length

◆ ENET_FTRL_TRUNC_FL [2/3]

#define ENET_FTRL_TRUNC_FL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)

TRUNC_FL - Frame Truncation Length

◆ ENET_FTRL_TRUNC_FL [3/3]

#define ENET_FTRL_TRUNC_FL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)

TRUNC_FL - Frame Truncation Length

◆ ENET_IEEE_R_ALIGN_COUNT [1/3]

#define ENET_IEEE_R_ALIGN_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)

COUNT - Number of frames received with alignment error

◆ ENET_IEEE_R_ALIGN_COUNT [2/3]

#define ENET_IEEE_R_ALIGN_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)

COUNT - Number of frames received with alignment error

◆ ENET_IEEE_R_ALIGN_COUNT [3/3]

#define ENET_IEEE_R_ALIGN_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)

COUNT - Number of frames received with alignment error

◆ ENET_IEEE_R_CRC_COUNT [1/3]

#define ENET_IEEE_R_CRC_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)

COUNT - Number of frames received with CRC error

◆ ENET_IEEE_R_CRC_COUNT [2/3]

#define ENET_IEEE_R_CRC_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)

COUNT - Number of frames received with CRC error

◆ ENET_IEEE_R_CRC_COUNT [3/3]

#define ENET_IEEE_R_CRC_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)

COUNT - Number of frames received with CRC error

◆ ENET_IEEE_R_DROP_COUNT [1/3]

#define ENET_IEEE_R_DROP_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)

COUNT - Frame count

◆ ENET_IEEE_R_DROP_COUNT [2/3]

#define ENET_IEEE_R_DROP_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)

COUNT - Frame count

◆ ENET_IEEE_R_DROP_COUNT [3/3]

#define ENET_IEEE_R_DROP_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)

COUNT - Frame count

◆ ENET_IEEE_R_FDXFC_COUNT [1/3]

#define ENET_IEEE_R_FDXFC_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)

COUNT - Number of flow-control pause frames received

◆ ENET_IEEE_R_FDXFC_COUNT [2/3]

#define ENET_IEEE_R_FDXFC_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)

COUNT - Number of flow-control pause frames received

◆ ENET_IEEE_R_FDXFC_COUNT [3/3]

#define ENET_IEEE_R_FDXFC_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)

COUNT - Number of flow-control pause frames received

◆ ENET_IEEE_R_FRAME_OK_COUNT [1/3]

#define ENET_IEEE_R_FRAME_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)

COUNT - Number of frames received OK

◆ ENET_IEEE_R_FRAME_OK_COUNT [2/3]

#define ENET_IEEE_R_FRAME_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)

COUNT - Number of frames received OK

◆ ENET_IEEE_R_FRAME_OK_COUNT [3/3]

#define ENET_IEEE_R_FRAME_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)

COUNT - Number of frames received OK

◆ ENET_IEEE_R_MACERR_COUNT [1/3]

#define ENET_IEEE_R_MACERR_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)

COUNT - Receive FIFO overflow count

◆ ENET_IEEE_R_MACERR_COUNT [2/3]

#define ENET_IEEE_R_MACERR_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)

COUNT - Receive FIFO overflow count

◆ ENET_IEEE_R_MACERR_COUNT [3/3]

#define ENET_IEEE_R_MACERR_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)

COUNT - Receive FIFO overflow count

◆ ENET_IEEE_R_OCTETS_OK_COUNT [1/3]

#define ENET_IEEE_R_OCTETS_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)

COUNT - Number of octets for frames received without error

◆ ENET_IEEE_R_OCTETS_OK_COUNT [2/3]

#define ENET_IEEE_R_OCTETS_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)

COUNT - Number of octets for frames received without error

◆ ENET_IEEE_R_OCTETS_OK_COUNT [3/3]

#define ENET_IEEE_R_OCTETS_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)

COUNT - Number of octets for frames received without error

◆ ENET_IEEE_T_1COL_COUNT [1/3]

#define ENET_IEEE_T_1COL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)

COUNT - Number of frames transmitted with one collision

◆ ENET_IEEE_T_1COL_COUNT [2/3]

#define ENET_IEEE_T_1COL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)

COUNT - Number of frames transmitted with one collision

◆ ENET_IEEE_T_1COL_COUNT [3/3]

#define ENET_IEEE_T_1COL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)

COUNT - Number of frames transmitted with one collision

◆ ENET_IEEE_T_CSERR_COUNT [1/3]

#define ENET_IEEE_T_CSERR_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)

COUNT - Number of frames transmitted with carrier sense error

◆ ENET_IEEE_T_CSERR_COUNT [2/3]

#define ENET_IEEE_T_CSERR_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)

COUNT - Number of frames transmitted with carrier sense error

◆ ENET_IEEE_T_CSERR_COUNT [3/3]

#define ENET_IEEE_T_CSERR_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)

COUNT - Number of frames transmitted with carrier sense error

◆ ENET_IEEE_T_DEF_COUNT [1/3]

#define ENET_IEEE_T_DEF_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)

COUNT - Number of frames transmitted with deferral delay

◆ ENET_IEEE_T_DEF_COUNT [2/3]

#define ENET_IEEE_T_DEF_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)

COUNT - Number of frames transmitted with deferral delay

◆ ENET_IEEE_T_DEF_COUNT [3/3]

#define ENET_IEEE_T_DEF_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)

COUNT - Number of frames transmitted with deferral delay

◆ ENET_IEEE_T_EXCOL_COUNT [1/3]

#define ENET_IEEE_T_EXCOL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)

COUNT - Number of frames transmitted with excessive collisions

◆ ENET_IEEE_T_EXCOL_COUNT [2/3]

#define ENET_IEEE_T_EXCOL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)

COUNT - Number of frames transmitted with excessive collisions

◆ ENET_IEEE_T_EXCOL_COUNT [3/3]

#define ENET_IEEE_T_EXCOL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)

COUNT - Number of frames transmitted with excessive collisions

◆ ENET_IEEE_T_FDXFC_COUNT [1/3]

#define ENET_IEEE_T_FDXFC_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)

COUNT - Number of flow-control pause frames transmitted

◆ ENET_IEEE_T_FDXFC_COUNT [2/3]

#define ENET_IEEE_T_FDXFC_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)

COUNT - Number of flow-control pause frames transmitted

◆ ENET_IEEE_T_FDXFC_COUNT [3/3]

#define ENET_IEEE_T_FDXFC_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)

COUNT - Number of flow-control pause frames transmitted

◆ ENET_IEEE_T_FRAME_OK_COUNT [1/3]

#define ENET_IEEE_T_FRAME_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)

COUNT - Number of frames transmitted OK

◆ ENET_IEEE_T_FRAME_OK_COUNT [2/3]

#define ENET_IEEE_T_FRAME_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)

COUNT - Number of frames transmitted OK

◆ ENET_IEEE_T_FRAME_OK_COUNT [3/3]

#define ENET_IEEE_T_FRAME_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)

COUNT - Number of frames transmitted OK

◆ ENET_IEEE_T_LCOL_COUNT [1/3]

#define ENET_IEEE_T_LCOL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)

COUNT - Number of frames transmitted with late collision

◆ ENET_IEEE_T_LCOL_COUNT [2/3]

#define ENET_IEEE_T_LCOL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)

COUNT - Number of frames transmitted with late collision

◆ ENET_IEEE_T_LCOL_COUNT [3/3]

#define ENET_IEEE_T_LCOL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)

COUNT - Number of frames transmitted with late collision

◆ ENET_IEEE_T_MACERR_COUNT [1/3]

#define ENET_IEEE_T_MACERR_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)

COUNT - Number of frames transmitted with transmit FIFO underrun

◆ ENET_IEEE_T_MACERR_COUNT [2/3]

#define ENET_IEEE_T_MACERR_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)

COUNT - Number of frames transmitted with transmit FIFO underrun

◆ ENET_IEEE_T_MACERR_COUNT [3/3]

#define ENET_IEEE_T_MACERR_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)

COUNT - Number of frames transmitted with transmit FIFO underrun

◆ ENET_IEEE_T_MCOL_COUNT [1/3]

#define ENET_IEEE_T_MCOL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)

COUNT - Number of frames transmitted with multiple collisions

◆ ENET_IEEE_T_MCOL_COUNT [2/3]

#define ENET_IEEE_T_MCOL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)

COUNT - Number of frames transmitted with multiple collisions

◆ ENET_IEEE_T_MCOL_COUNT [3/3]

#define ENET_IEEE_T_MCOL_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)

COUNT - Number of frames transmitted with multiple collisions

◆ ENET_IEEE_T_OCTETS_OK_COUNT [1/3]

#define ENET_IEEE_T_OCTETS_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)

COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).

◆ ENET_IEEE_T_OCTETS_OK_COUNT [2/3]

#define ENET_IEEE_T_OCTETS_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)

COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).

◆ ENET_IEEE_T_OCTETS_OK_COUNT [3/3]

#define ENET_IEEE_T_OCTETS_OK_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)

COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).

◆ ENET_IEEE_T_SQE_COUNT [1/3]

#define ENET_IEEE_T_SQE_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)

COUNT - This read-only field is reserved and always has the value 0

◆ ENET_IEEE_T_SQE_COUNT [2/3]

#define ENET_IEEE_T_SQE_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)

COUNT - This read-only field is reserved and always has the value 0

◆ ENET_IEEE_T_SQE_COUNT [3/3]

#define ENET_IEEE_T_SQE_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)

COUNT - This read-only field is reserved and always has the value 0

◆ ENET_MIBC_MIB_CLEAR [1/3]

#define ENET_MIBC_MIB_CLEAR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.

◆ ENET_MIBC_MIB_CLEAR [2/3]

#define ENET_MIBC_MIB_CLEAR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.

◆ ENET_MIBC_MIB_CLEAR [3/3]

#define ENET_MIBC_MIB_CLEAR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.

◆ ENET_MIBC_MIB_DIS [1/3]

#define ENET_MIBC_MIB_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.

◆ ENET_MIBC_MIB_DIS [2/3]

#define ENET_MIBC_MIB_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.

◆ ENET_MIBC_MIB_DIS [3/3]

#define ENET_MIBC_MIB_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.

◆ ENET_MIBC_MIB_IDLE [1/3]

#define ENET_MIBC_MIB_IDLE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.

◆ ENET_MIBC_MIB_IDLE [2/3]

#define ENET_MIBC_MIB_IDLE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.

◆ ENET_MIBC_MIB_IDLE [3/3]

#define ENET_MIBC_MIB_IDLE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.

◆ ENET_MMFR_DATA [1/3]

#define ENET_MMFR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)

DATA - Management Frame Data

◆ ENET_MMFR_DATA [2/3]

#define ENET_MMFR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)

DATA - Management Frame Data

◆ ENET_MMFR_DATA [3/3]

#define ENET_MMFR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)

DATA - Management Frame Data

◆ ENET_MMFR_OP [1/3]

#define ENET_MMFR_OP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)

OP - Operation Code

◆ ENET_MMFR_OP [2/3]

#define ENET_MMFR_OP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)

OP - Operation Code

◆ ENET_MMFR_OP [3/3]

#define ENET_MMFR_OP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)

OP - Operation Code

◆ ENET_MMFR_PA [1/3]

#define ENET_MMFR_PA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)

PA - PHY Address

◆ ENET_MMFR_PA [2/3]

#define ENET_MMFR_PA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)

PA - PHY Address

◆ ENET_MMFR_PA [3/3]

#define ENET_MMFR_PA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)

PA - PHY Address

◆ ENET_MMFR_RA [1/3]

#define ENET_MMFR_RA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)

RA - Register Address

◆ ENET_MMFR_RA [2/3]

#define ENET_MMFR_RA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)

RA - Register Address

◆ ENET_MMFR_RA [3/3]

#define ENET_MMFR_RA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)

RA - Register Address

◆ ENET_MMFR_ST [1/3]

#define ENET_MMFR_ST ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)

ST - Start Of Frame Delimiter

◆ ENET_MMFR_ST [2/3]

#define ENET_MMFR_ST ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)

ST - Start Of Frame Delimiter

◆ ENET_MMFR_ST [3/3]

#define ENET_MMFR_ST ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)

ST - Start Of Frame Delimiter

◆ ENET_MMFR_TA [1/3]

#define ENET_MMFR_TA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)

TA - Turn Around

◆ ENET_MMFR_TA [2/3]

#define ENET_MMFR_TA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)

TA - Turn Around

◆ ENET_MMFR_TA [3/3]

#define ENET_MMFR_TA ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)

TA - Turn Around

◆ ENET_MSCR_DIS_PRE [1/3]

#define ENET_MSCR_DIS_PRE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.

◆ ENET_MSCR_DIS_PRE [2/3]

#define ENET_MSCR_DIS_PRE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.

◆ ENET_MSCR_DIS_PRE [3/3]

#define ENET_MSCR_DIS_PRE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.

◆ ENET_MSCR_HOLDTIME [1/3]

#define ENET_MSCR_HOLDTIME ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles

◆ ENET_MSCR_HOLDTIME [2/3]

#define ENET_MSCR_HOLDTIME ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles

◆ ENET_MSCR_HOLDTIME [3/3]

#define ENET_MSCR_HOLDTIME ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles

◆ ENET_MSCR_MII_SPEED [1/3]

#define ENET_MSCR_MII_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)

MII_SPEED - MII Speed

◆ ENET_MSCR_MII_SPEED [2/3]

#define ENET_MSCR_MII_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)

MII_SPEED - MII Speed

◆ ENET_MSCR_MII_SPEED [3/3]

#define ENET_MSCR_MII_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)

MII_SPEED - MII Speed

◆ ENET_OPD_OPCODE [1/3]

#define ENET_OPD_OPCODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)

OPCODE - Opcode Field In PAUSE Frames

◆ ENET_OPD_OPCODE [2/3]

#define ENET_OPD_OPCODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)

OPCODE - Opcode Field In PAUSE Frames

◆ ENET_OPD_OPCODE [3/3]

#define ENET_OPD_OPCODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)

OPCODE - Opcode Field In PAUSE Frames

◆ ENET_OPD_PAUSE_DUR [1/3]

#define ENET_OPD_PAUSE_DUR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)

PAUSE_DUR - Pause Duration

◆ ENET_OPD_PAUSE_DUR [2/3]

#define ENET_OPD_PAUSE_DUR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)

PAUSE_DUR - Pause Duration

◆ ENET_OPD_PAUSE_DUR [3/3]

#define ENET_OPD_PAUSE_DUR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)

PAUSE_DUR - Pause Duration

◆ ENET_PALR_PADDR1 [1/3]

#define ENET_PALR_PADDR1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)

PADDR1 - Pause Address

◆ ENET_PALR_PADDR1 [2/3]

#define ENET_PALR_PADDR1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)

PADDR1 - Pause Address

◆ ENET_PALR_PADDR1 [3/3]

#define ENET_PALR_PADDR1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)

PADDR1 - Pause Address

◆ ENET_PAUR_TYPE [1/3]

#define ENET_PAUR_TYPE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)

TYPE - Type Field In PAUSE Frames

◆ ENET_PAUR_TYPE [2/3]

#define ENET_PAUR_TYPE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)

TYPE - Type Field In PAUSE Frames

◆ ENET_PAUR_TYPE [3/3]

#define ENET_PAUR_TYPE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)

TYPE - Type Field In PAUSE Frames

◆ ENET_QOS_RX_FLUSH0 [1/2]

#define ENET_QOS_RX_FLUSH0 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)

RX_FLUSH0 - RX Flush Ring 0 0b0..Disable 0b1..Enable

◆ ENET_QOS_RX_FLUSH0 [2/2]

#define ENET_QOS_RX_FLUSH0 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)

RX_FLUSH0 - RX Flush Ring 0 0b0..Disable 0b1..Enable

◆ ENET_QOS_RX_FLUSH1 [1/2]

#define ENET_QOS_RX_FLUSH1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)

RX_FLUSH1 - RX Flush Ring 1 0b0..Disable 0b1..Enable

◆ ENET_QOS_RX_FLUSH1 [2/2]

#define ENET_QOS_RX_FLUSH1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)

RX_FLUSH1 - RX Flush Ring 1 0b0..Disable 0b1..Enable

◆ ENET_QOS_RX_FLUSH2 [1/2]

#define ENET_QOS_RX_FLUSH2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)

RX_FLUSH2 - RX Flush Ring 2 0b0..Disable 0b1..Enable

◆ ENET_QOS_RX_FLUSH2 [2/2]

#define ENET_QOS_RX_FLUSH2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)

RX_FLUSH2 - RX Flush Ring 2 0b0..Disable 0b1..Enable

◆ ENET_QOS_TX_SCHEME [1/2]

#define ENET_QOS_TX_SCHEME ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)

TX_SCHEME - TX scheme configuration 0b000..Credit-based scheme 0b001..Round-robin scheme 0b010-0b111..Reserved

◆ ENET_QOS_TX_SCHEME [2/2]

#define ENET_QOS_TX_SCHEME ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)

TX_SCHEME - TX scheme configuration 0b000..Credit-based scheme 0b001..Round-robin scheme 0b010-0b111..Reserved

◆ ENET_RACC_IPDIS [1/3]

#define ENET_RACC_IPDIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

◆ ENET_RACC_IPDIS [2/3]

#define ENET_RACC_IPDIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

◆ ENET_RACC_IPDIS [3/3]

#define ENET_RACC_IPDIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

◆ ENET_RACC_LINEDIS [1/3]

#define ENET_RACC_LINEDIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.

◆ ENET_RACC_LINEDIS [2/3]

#define ENET_RACC_LINEDIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.

◆ ENET_RACC_LINEDIS [3/3]

#define ENET_RACC_LINEDIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.

◆ ENET_RACC_PADREM [1/3]

#define ENET_RACC_PADREM ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.

◆ ENET_RACC_PADREM [2/3]

#define ENET_RACC_PADREM ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.

◆ ENET_RACC_PADREM [3/3]

#define ENET_RACC_PADREM ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.

◆ ENET_RACC_PRODIS [1/3]

#define ENET_RACC_PRODIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

◆ ENET_RACC_PRODIS [2/3]

#define ENET_RACC_PRODIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

◆ ENET_RACC_PRODIS [3/3]

#define ENET_RACC_PRODIS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

◆ ENET_RACC_SHIFT16 [1/3]

#define ENET_RACC_SHIFT16 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.

◆ ENET_RACC_SHIFT16 [2/3]

#define ENET_RACC_SHIFT16 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.

◆ ENET_RACC_SHIFT16 [3/3]

#define ENET_RACC_SHIFT16 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.

◆ ENET_RAEM_RX_ALMOST_EMPTY [1/3]

#define ENET_RAEM_RX_ALMOST_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)

RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold

◆ ENET_RAEM_RX_ALMOST_EMPTY [2/3]

#define ENET_RAEM_RX_ALMOST_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold

◆ ENET_RAEM_RX_ALMOST_EMPTY [3/3]

#define ENET_RAEM_RX_ALMOST_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold

◆ ENET_RAFL_RX_ALMOST_FULL [1/3]

#define ENET_RAFL_RX_ALMOST_FULL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)

RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold

◆ ENET_RAFL_RX_ALMOST_FULL [2/3]

#define ENET_RAFL_RX_ALMOST_FULL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold

◆ ENET_RAFL_RX_ALMOST_FULL [3/3]

#define ENET_RAFL_RX_ALMOST_FULL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold

◆ ENET_RCMR_CMP0 [1/2]

#define ENET_RCMR_CMP0 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)

CMP0 - Compare 0

◆ ENET_RCMR_CMP0 [2/2]

#define ENET_RCMR_CMP0 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)

CMP0 - Compare 0

◆ ENET_RCMR_CMP1 [1/2]

#define ENET_RCMR_CMP1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)

CMP1 - Compare 1

◆ ENET_RCMR_CMP1 [2/2]

#define ENET_RCMR_CMP1 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)

CMP1 - Compare 1

◆ ENET_RCMR_CMP2 [1/2]

#define ENET_RCMR_CMP2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)

CMP2 - Compare 2

◆ ENET_RCMR_CMP2 [2/2]

#define ENET_RCMR_CMP2 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)

CMP2 - Compare 2

◆ ENET_RCMR_CMP3 [1/2]

#define ENET_RCMR_CMP3 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)

CMP3 - Compare 3

◆ ENET_RCMR_CMP3 [2/2]

#define ENET_RCMR_CMP3 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)

CMP3 - Compare 3

◆ ENET_RCMR_MATCHEN [1/2]

#define ENET_RCMR_MATCHEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)

MATCHEN - Match Enable 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert. 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.

◆ ENET_RCMR_MATCHEN [2/2]

#define ENET_RCMR_MATCHEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)

MATCHEN - Match Enable 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert. 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.

◆ ENET_RCR_BC_REJ [1/3]

#define ENET_RCR_BC_REJ ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)

BC_REJ - Broadcast Frame Reject 0b0..Will not reject frames as described above 0b1..Will reject frames as described above

◆ ENET_RCR_BC_REJ [2/3]

#define ENET_RCR_BC_REJ ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)

BC_REJ - Broadcast Frame Reject 0b0..Will not reject frames as described above 0b1..Will reject frames as described above

◆ ENET_RCR_BC_REJ [3/3]

#define ENET_RCR_BC_REJ ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)

BC_REJ - Broadcast Frame Reject 0b0..Will not reject frames as described above 0b1..Will reject frames as described above

◆ ENET_RCR_CFEN [1/3]

#define ENET_RCR_CFEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.

◆ ENET_RCR_CFEN [2/3]

#define ENET_RCR_CFEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.

◆ ENET_RCR_CFEN [3/3]

#define ENET_RCR_CFEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.

◆ ENET_RCR_CRCFWD [1/3]

#define ENET_RCR_CRCFWD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.

◆ ENET_RCR_CRCFWD [2/3]

#define ENET_RCR_CRCFWD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.

◆ ENET_RCR_CRCFWD [3/3]

#define ENET_RCR_CRCFWD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.

◆ ENET_RCR_DRT [1/3]

#define ENET_RCR_DRT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)

◆ ENET_RCR_DRT [2/3]

#define ENET_RCR_DRT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)

◆ ENET_RCR_DRT [3/3]

#define ENET_RCR_DRT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)

◆ ENET_RCR_FCE [1/3]

#define ENET_RCR_FCE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)

FCE - Flow Control Enable 0b0..Disable flow control 0b1..Enable flow control

◆ ENET_RCR_FCE [2/3]

#define ENET_RCR_FCE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)

FCE - Flow Control Enable 0b0..Disable flow control 0b1..Enable flow control

◆ ENET_RCR_FCE [3/3]

#define ENET_RCR_FCE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)

FCE - Flow Control Enable 0b0..Disable flow control 0b1..Enable flow control

◆ ENET_RCR_GRS [1/3]

#define ENET_RCR_GRS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)

GRS - Graceful Receive Stopped 0b0..Receive not stopped 0b1..Receive stopped

◆ ENET_RCR_GRS [2/3]

#define ENET_RCR_GRS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)

GRS - Graceful Receive Stopped 0b0..Receive not stopped 0b1..Receive stopped

◆ ENET_RCR_GRS [3/3]

#define ENET_RCR_GRS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)

GRS - Graceful Receive Stopped 0b0..Receive not stopped 0b1..Receive stopped

◆ ENET_RCR_LOOP [1/3]

#define ENET_RCR_LOOP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.

◆ ENET_RCR_LOOP [2/3]

#define ENET_RCR_LOOP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.

◆ ENET_RCR_LOOP [3/3]

#define ENET_RCR_LOOP ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.

◆ ENET_RCR_MAX_FL [1/3]

#define ENET_RCR_MAX_FL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)

MAX_FL - Maximum Frame Length

◆ ENET_RCR_MAX_FL [2/3]

#define ENET_RCR_MAX_FL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)

MAX_FL - Maximum Frame Length

◆ ENET_RCR_MAX_FL [3/3]

#define ENET_RCR_MAX_FL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)

MAX_FL - Maximum Frame Length

◆ ENET_RCR_MII_MODE [1/3]

#define ENET_RCR_MII_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.

◆ ENET_RCR_MII_MODE [2/3]

#define ENET_RCR_MII_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.

◆ ENET_RCR_MII_MODE [3/3]

#define ENET_RCR_MII_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.

◆ ENET_RCR_NLC [1/3]

#define ENET_RCR_NLC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.

◆ ENET_RCR_NLC [2/3]

#define ENET_RCR_NLC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.

◆ ENET_RCR_NLC [3/3]

#define ENET_RCR_NLC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.

◆ ENET_RCR_PADEN [1/3]

#define ENET_RCR_PADEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.

◆ ENET_RCR_PADEN [2/3]

#define ENET_RCR_PADEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.

◆ ENET_RCR_PADEN [3/3]

#define ENET_RCR_PADEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.

◆ ENET_RCR_PAUFWD [1/3]

#define ENET_RCR_PAUFWD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.

◆ ENET_RCR_PAUFWD [2/3]

#define ENET_RCR_PAUFWD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.

◆ ENET_RCR_PAUFWD [3/3]

#define ENET_RCR_PAUFWD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.

◆ ENET_RCR_PROM [1/3]

#define ENET_RCR_PROM ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.

◆ ENET_RCR_PROM [2/3]

#define ENET_RCR_PROM ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.

◆ ENET_RCR_PROM [3/3]

#define ENET_RCR_PROM ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.

◆ ENET_RCR_RGMII_EN [1/2]

#define ENET_RCR_RGMII_EN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)

RGMII_EN - RGMII Mode Enable 0b0..MAC configured for non-RGMII operation 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.

◆ ENET_RCR_RGMII_EN [2/2]

#define ENET_RCR_RGMII_EN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)

RGMII_EN - RGMII Mode Enable 0b0..MAC configured for non-RGMII operation 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.

◆ ENET_RCR_RMII_10T [1/3]

#define ENET_RCR_RMII_10T ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.

◆ ENET_RCR_RMII_10T [2/3]

#define ENET_RCR_RMII_10T ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

RMII_10T 0b0..100-Mbit/s or 1-Gbit/s operation. 0b1..10-Mbit/s operation.

◆ ENET_RCR_RMII_10T [3/3]

#define ENET_RCR_RMII_10T ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

RMII_10T 0b0..100-Mbit/s or 1-Gbit/s operation. 0b1..10-Mbit/s operation.

◆ ENET_RCR_RMII_MODE [1/3]

#define ENET_RCR_RMII_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.

◆ ENET_RCR_RMII_MODE [2/3]

#define ENET_RCR_RMII_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.

◆ ENET_RCR_RMII_MODE [3/3]

#define ENET_RCR_RMII_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.

◆ ENET_RDAR1_RDAR [1/2]

#define ENET_RDAR1_RDAR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)

RDAR - Receive Descriptor Active

◆ ENET_RDAR1_RDAR [2/2]

#define ENET_RDAR1_RDAR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)

RDAR - Receive Descriptor Active

◆ ENET_RDAR2_RDAR [1/2]

#define ENET_RDAR2_RDAR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)

RDAR - Receive Descriptor Active

◆ ENET_RDAR2_RDAR [2/2]

#define ENET_RDAR2_RDAR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)

RDAR - Receive Descriptor Active

◆ ENET_RDAR_RDAR [1/3]

#define ENET_RDAR_RDAR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)

RDAR - Receive Descriptor Active

◆ ENET_RDAR_RDAR [2/3]

#define ENET_RDAR_RDAR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)

RDAR - Receive Descriptor Active

◆ ENET_RDAR_RDAR [3/3]

#define ENET_RDAR_RDAR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)

RDAR - Receive Descriptor Active

◆ ENET_RMON_R_BC_PKT_COUNT [1/3]

#define ENET_RMON_R_BC_PKT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)

COUNT - Number of receive broadcast packets

◆ ENET_RMON_R_BC_PKT_COUNT [2/3]

#define ENET_RMON_R_BC_PKT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)

COUNT - Number of receive broadcast packets

◆ ENET_RMON_R_BC_PKT_COUNT [3/3]

#define ENET_RMON_R_BC_PKT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)

COUNT - Number of receive broadcast packets

◆ ENET_RMON_R_CRC_ALIGN_COUNT [1/3]

#define ENET_RMON_R_CRC_ALIGN_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)

COUNT - Number of receive packets with CRC or align error

◆ ENET_RMON_R_CRC_ALIGN_COUNT [2/3]

#define ENET_RMON_R_CRC_ALIGN_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)

COUNT - Number of receive packets with CRC or align error

◆ ENET_RMON_R_CRC_ALIGN_COUNT [3/3]

#define ENET_RMON_R_CRC_ALIGN_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)

COUNT - Number of receive packets with CRC or align error

◆ ENET_RMON_R_FRAG_COUNT [1/3]

#define ENET_RMON_R_FRAG_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)

COUNT - Number of receive packets with less than 64 bytes and bad CRC

◆ ENET_RMON_R_FRAG_COUNT [2/3]

#define ENET_RMON_R_FRAG_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)

COUNT - Number of receive packets with less than 64 bytes and bad CRC

◆ ENET_RMON_R_FRAG_COUNT [3/3]

#define ENET_RMON_R_FRAG_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)

COUNT - Number of receive packets with less than 64 bytes and bad CRC

◆ ENET_RMON_R_JAB_COUNT [1/3]

#define ENET_RMON_R_JAB_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)

COUNT - Number of receive packets greater than MAX_FL and bad CRC

◆ ENET_RMON_R_JAB_COUNT [2/3]

#define ENET_RMON_R_JAB_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)

COUNT - Number of receive packets greater than MAX_FL and bad CRC

◆ ENET_RMON_R_JAB_COUNT [3/3]

#define ENET_RMON_R_JAB_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)

COUNT - Number of receive packets greater than MAX_FL and bad CRC

◆ ENET_RMON_R_MC_PKT_COUNT [1/3]

#define ENET_RMON_R_MC_PKT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)

COUNT - Number of receive multicast packets

◆ ENET_RMON_R_MC_PKT_COUNT [2/3]

#define ENET_RMON_R_MC_PKT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)

COUNT - Number of receive multicast packets

◆ ENET_RMON_R_MC_PKT_COUNT [3/3]

#define ENET_RMON_R_MC_PKT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)

COUNT - Number of receive multicast packets

◆ ENET_RMON_R_OCTETS_COUNT [1/3]

#define ENET_RMON_R_OCTETS_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)

COUNT - Number of receive octets

◆ ENET_RMON_R_OCTETS_COUNT [2/3]

#define ENET_RMON_R_OCTETS_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)

COUNT - Number of receive octets

◆ ENET_RMON_R_OCTETS_COUNT [3/3]

#define ENET_RMON_R_OCTETS_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)

COUNT - Number of receive octets

◆ ENET_RMON_R_OVERSIZE_COUNT [1/3]

#define ENET_RMON_R_OVERSIZE_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)

COUNT - Number of receive packets greater than MAX_FL and good CRC

◆ ENET_RMON_R_OVERSIZE_COUNT [2/3]

#define ENET_RMON_R_OVERSIZE_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)

COUNT - Number of receive packets greater than MAX_FL and good CRC

◆ ENET_RMON_R_OVERSIZE_COUNT [3/3]

#define ENET_RMON_R_OVERSIZE_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)

COUNT - Number of receive packets greater than MAX_FL and good CRC

◆ ENET_RMON_R_P1024TO2047_COUNT [1/3]

#define ENET_RMON_R_P1024TO2047_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)

COUNT - Number of 1024- to 2047-byte recieve packets

◆ ENET_RMON_R_P1024TO2047_COUNT [2/3]

#define ENET_RMON_R_P1024TO2047_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)

COUNT - Number of 1024- to 2047-byte recieve packets

◆ ENET_RMON_R_P1024TO2047_COUNT [3/3]

#define ENET_RMON_R_P1024TO2047_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)

COUNT - Number of 1024- to 2047-byte recieve packets

◆ ENET_RMON_R_P128TO255_COUNT [1/3]

#define ENET_RMON_R_P128TO255_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)

COUNT - Number of 128- to 255-byte recieve packets

◆ ENET_RMON_R_P128TO255_COUNT [2/3]

#define ENET_RMON_R_P128TO255_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)

COUNT - Number of 128- to 255-byte recieve packets

◆ ENET_RMON_R_P128TO255_COUNT [3/3]

#define ENET_RMON_R_P128TO255_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)

COUNT - Number of 128- to 255-byte recieve packets

◆ ENET_RMON_R_P256TO511_COUNT [1/3]

#define ENET_RMON_R_P256TO511_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)

COUNT - Number of 256- to 511-byte recieve packets

◆ ENET_RMON_R_P256TO511_COUNT [2/3]

#define ENET_RMON_R_P256TO511_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)

COUNT - Number of 256- to 511-byte recieve packets

◆ ENET_RMON_R_P256TO511_COUNT [3/3]

#define ENET_RMON_R_P256TO511_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)

COUNT - Number of 256- to 511-byte recieve packets

◆ ENET_RMON_R_P512TO1023_COUNT [1/3]

#define ENET_RMON_R_P512TO1023_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)

COUNT - Number of 512- to 1023-byte recieve packets

◆ ENET_RMON_R_P512TO1023_COUNT [2/3]

#define ENET_RMON_R_P512TO1023_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)

COUNT - Number of 512- to 1023-byte recieve packets

◆ ENET_RMON_R_P512TO1023_COUNT [3/3]

#define ENET_RMON_R_P512TO1023_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)

COUNT - Number of 512- to 1023-byte recieve packets

◆ ENET_RMON_R_P64_COUNT [1/3]

#define ENET_RMON_R_P64_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)

COUNT - Number of 64-byte receive packets

◆ ENET_RMON_R_P64_COUNT [2/3]

#define ENET_RMON_R_P64_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)

COUNT - Number of 64-byte receive packets

◆ ENET_RMON_R_P64_COUNT [3/3]

#define ENET_RMON_R_P64_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)

COUNT - Number of 64-byte receive packets

◆ ENET_RMON_R_P65TO127_COUNT [1/3]

#define ENET_RMON_R_P65TO127_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)

COUNT - Number of 65- to 127-byte recieve packets

◆ ENET_RMON_R_P65TO127_COUNT [2/3]

#define ENET_RMON_R_P65TO127_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)

COUNT - Number of 65- to 127-byte recieve packets

◆ ENET_RMON_R_P65TO127_COUNT [3/3]

#define ENET_RMON_R_P65TO127_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)

COUNT - Number of 65- to 127-byte recieve packets

◆ ENET_RMON_R_P_GTE2048_COUNT [1/3]

#define ENET_RMON_R_P_GTE2048_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)

COUNT - Number of greater-than-2048-byte recieve packets

◆ ENET_RMON_R_P_GTE2048_COUNT [2/3]

#define ENET_RMON_R_P_GTE2048_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)

COUNT - Number of greater-than-2048-byte recieve packets

◆ ENET_RMON_R_P_GTE2048_COUNT [3/3]

#define ENET_RMON_R_P_GTE2048_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)

COUNT - Number of greater-than-2048-byte recieve packets

◆ ENET_RMON_R_PACKETS_COUNT [1/3]

#define ENET_RMON_R_PACKETS_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)

COUNT - Number of packets received

◆ ENET_RMON_R_PACKETS_COUNT [2/3]

#define ENET_RMON_R_PACKETS_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)

COUNT - Number of packets received

◆ ENET_RMON_R_PACKETS_COUNT [3/3]

#define ENET_RMON_R_PACKETS_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)

COUNT - Number of packets received

◆ ENET_RMON_R_UNDERSIZE_COUNT [1/3]

#define ENET_RMON_R_UNDERSIZE_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)

COUNT - Number of receive packets with less than 64 bytes and good CRC

◆ ENET_RMON_R_UNDERSIZE_COUNT [2/3]

#define ENET_RMON_R_UNDERSIZE_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)

COUNT - Number of receive packets with less than 64 bytes and good CRC

◆ ENET_RMON_R_UNDERSIZE_COUNT [3/3]

#define ENET_RMON_R_UNDERSIZE_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)

COUNT - Number of receive packets with less than 64 bytes and good CRC

◆ ENET_RMON_T_BC_PKT_TXPKTS [1/3]

#define ENET_RMON_T_BC_PKT_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)

TXPKTS - Number of broadcast packets

◆ ENET_RMON_T_BC_PKT_TXPKTS [2/3]

#define ENET_RMON_T_BC_PKT_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)

TXPKTS - Broadcast packets

◆ ENET_RMON_T_BC_PKT_TXPKTS [3/3]

#define ENET_RMON_T_BC_PKT_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)

TXPKTS - Broadcast packets

◆ ENET_RMON_T_COL_TXPKTS [1/3]

#define ENET_RMON_T_COL_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)

TXPKTS - Number of transmit collisions

◆ ENET_RMON_T_COL_TXPKTS [2/3]

#define ENET_RMON_T_COL_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)

TXPKTS - Number of transmit collisions

◆ ENET_RMON_T_COL_TXPKTS [3/3]

#define ENET_RMON_T_COL_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)

TXPKTS - Number of transmit collisions

◆ ENET_RMON_T_CRC_ALIGN_TXPKTS [1/3]

#define ENET_RMON_T_CRC_ALIGN_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)

TXPKTS - Number of packets with CRC/align error

◆ ENET_RMON_T_CRC_ALIGN_TXPKTS [2/3]

#define ENET_RMON_T_CRC_ALIGN_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)

TXPKTS - Packets with CRC/align error

◆ ENET_RMON_T_CRC_ALIGN_TXPKTS [3/3]

#define ENET_RMON_T_CRC_ALIGN_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)

TXPKTS - Packets with CRC/align error

◆ ENET_RMON_T_FRAG_TXPKTS [1/3]

#define ENET_RMON_T_FRAG_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)

TXPKTS - Number of packets less than 64 bytes with bad CRC

◆ ENET_RMON_T_FRAG_TXPKTS [2/3]

#define ENET_RMON_T_FRAG_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)

TXPKTS - Number of packets less than 64 bytes with bad CRC

◆ ENET_RMON_T_FRAG_TXPKTS [3/3]

#define ENET_RMON_T_FRAG_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)

TXPKTS - Number of packets less than 64 bytes with bad CRC

◆ ENET_RMON_T_JAB_TXPKTS [1/3]

#define ENET_RMON_T_JAB_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC

◆ ENET_RMON_T_JAB_TXPKTS [2/3]

#define ENET_RMON_T_JAB_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC

◆ ENET_RMON_T_JAB_TXPKTS [3/3]

#define ENET_RMON_T_JAB_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC

◆ ENET_RMON_T_MC_PKT_TXPKTS [1/3]

#define ENET_RMON_T_MC_PKT_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)

TXPKTS - Number of multicast packets

◆ ENET_RMON_T_MC_PKT_TXPKTS [2/3]

#define ENET_RMON_T_MC_PKT_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)

TXPKTS - Multicast packets

◆ ENET_RMON_T_MC_PKT_TXPKTS [3/3]

#define ENET_RMON_T_MC_PKT_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)

TXPKTS - Multicast packets

◆ ENET_RMON_T_OCTETS_TXOCTS [1/3]

#define ENET_RMON_T_OCTETS_TXOCTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)

TXOCTS - Number of transmit octets

◆ ENET_RMON_T_OCTETS_TXOCTS [2/3]

#define ENET_RMON_T_OCTETS_TXOCTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)

TXOCTS - Number of transmit octets

◆ ENET_RMON_T_OCTETS_TXOCTS [3/3]

#define ENET_RMON_T_OCTETS_TXOCTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)

TXOCTS - Number of transmit octets

◆ ENET_RMON_T_OVERSIZE_TXPKTS [1/3]

#define ENET_RMON_T_OVERSIZE_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC

◆ ENET_RMON_T_OVERSIZE_TXPKTS [2/3]

#define ENET_RMON_T_OVERSIZE_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC

◆ ENET_RMON_T_OVERSIZE_TXPKTS [3/3]

#define ENET_RMON_T_OVERSIZE_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC

◆ ENET_RMON_T_P1024TO2047_TXPKTS [1/3]

#define ENET_RMON_T_P1024TO2047_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)

TXPKTS - Number of 1024- to 2047-byte transmit packets

◆ ENET_RMON_T_P1024TO2047_TXPKTS [2/3]

#define ENET_RMON_T_P1024TO2047_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)

TXPKTS - Number of 1024- to 2047-byte transmit packets

◆ ENET_RMON_T_P1024TO2047_TXPKTS [3/3]

#define ENET_RMON_T_P1024TO2047_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)

TXPKTS - Number of 1024- to 2047-byte transmit packets

◆ ENET_RMON_T_P128TO255_TXPKTS [1/3]

#define ENET_RMON_T_P128TO255_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)

TXPKTS - Number of 128- to 255-byte transmit packets

◆ ENET_RMON_T_P128TO255_TXPKTS [2/3]

#define ENET_RMON_T_P128TO255_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)

TXPKTS - Number of 128- to 255-byte transmit packets

◆ ENET_RMON_T_P128TO255_TXPKTS [3/3]

#define ENET_RMON_T_P128TO255_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)

TXPKTS - Number of 128- to 255-byte transmit packets

◆ ENET_RMON_T_P256TO511_TXPKTS [1/3]

#define ENET_RMON_T_P256TO511_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)

TXPKTS - Number of 256- to 511-byte transmit packets

◆ ENET_RMON_T_P256TO511_TXPKTS [2/3]

#define ENET_RMON_T_P256TO511_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)

TXPKTS - Number of 256- to 511-byte transmit packets

◆ ENET_RMON_T_P256TO511_TXPKTS [3/3]

#define ENET_RMON_T_P256TO511_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)

TXPKTS - Number of 256- to 511-byte transmit packets

◆ ENET_RMON_T_P512TO1023_TXPKTS [1/3]

#define ENET_RMON_T_P512TO1023_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)

TXPKTS - Number of 512- to 1023-byte transmit packets

◆ ENET_RMON_T_P512TO1023_TXPKTS [2/3]

#define ENET_RMON_T_P512TO1023_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)

TXPKTS - Number of 512- to 1023-byte transmit packets

◆ ENET_RMON_T_P512TO1023_TXPKTS [3/3]

#define ENET_RMON_T_P512TO1023_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)

TXPKTS - Number of 512- to 1023-byte transmit packets

◆ ENET_RMON_T_P64_TXPKTS [1/3]

#define ENET_RMON_T_P64_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)

TXPKTS - Number of 64-byte transmit packets

◆ ENET_RMON_T_P64_TXPKTS [2/3]

#define ENET_RMON_T_P64_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)

TXPKTS - Number of 64-byte transmit packets

◆ ENET_RMON_T_P64_TXPKTS [3/3]

#define ENET_RMON_T_P64_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)

TXPKTS - Number of 64-byte transmit packets

◆ ENET_RMON_T_P65TO127_TXPKTS [1/3]

#define ENET_RMON_T_P65TO127_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)

TXPKTS - Number of 65- to 127-byte transmit packets

◆ ENET_RMON_T_P65TO127_TXPKTS [2/3]

#define ENET_RMON_T_P65TO127_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)

TXPKTS - Number of 65- to 127-byte transmit packets

◆ ENET_RMON_T_P65TO127_TXPKTS [3/3]

#define ENET_RMON_T_P65TO127_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)

TXPKTS - Number of 65- to 127-byte transmit packets

◆ ENET_RMON_T_P_GTE2048_TXPKTS [1/3]

#define ENET_RMON_T_P_GTE2048_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than 2048 bytes

◆ ENET_RMON_T_P_GTE2048_TXPKTS [2/3]

#define ENET_RMON_T_P_GTE2048_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than 2048 bytes

◆ ENET_RMON_T_P_GTE2048_TXPKTS [3/3]

#define ENET_RMON_T_P_GTE2048_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)

TXPKTS - Number of transmit packets greater than 2048 bytes

◆ ENET_RMON_T_PACKETS_TXPKTS [1/3]

#define ENET_RMON_T_PACKETS_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)

TXPKTS - Packet count

◆ ENET_RMON_T_PACKETS_TXPKTS [2/3]

#define ENET_RMON_T_PACKETS_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)

TXPKTS - Packet count

◆ ENET_RMON_T_PACKETS_TXPKTS [3/3]

#define ENET_RMON_T_PACKETS_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)

TXPKTS - Packet count

◆ ENET_RMON_T_UNDERSIZE_TXPKTS [1/3]

#define ENET_RMON_T_UNDERSIZE_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)

TXPKTS - Number of transmit packets less than 64 bytes with good CRC

◆ ENET_RMON_T_UNDERSIZE_TXPKTS [2/3]

#define ENET_RMON_T_UNDERSIZE_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)

TXPKTS - Number of transmit packets less than 64 bytes with good CRC

◆ ENET_RMON_T_UNDERSIZE_TXPKTS [3/3]

#define ENET_RMON_T_UNDERSIZE_TXPKTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)

TXPKTS - Number of transmit packets less than 64 bytes with good CRC

◆ ENET_RSEM_RX_SECTION_EMPTY [1/3]

#define ENET_RSEM_RX_SECTION_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)

RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold

◆ ENET_RSEM_RX_SECTION_EMPTY [2/3]

#define ENET_RSEM_RX_SECTION_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold

◆ ENET_RSEM_RX_SECTION_EMPTY [3/3]

#define ENET_RSEM_RX_SECTION_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold

◆ ENET_RSEM_STAT_SECTION_EMPTY [1/3]

#define ENET_RSEM_STAT_SECTION_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)

STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold

◆ ENET_RSEM_STAT_SECTION_EMPTY [2/3]

#define ENET_RSEM_STAT_SECTION_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)

STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold

◆ ENET_RSEM_STAT_SECTION_EMPTY [3/3]

#define ENET_RSEM_STAT_SECTION_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)

STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold

◆ ENET_RSFL_RX_SECTION_FULL [1/3]

#define ENET_RSFL_RX_SECTION_FULL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)

RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold

◆ ENET_RSFL_RX_SECTION_FULL [2/3]

#define ENET_RSFL_RX_SECTION_FULL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold

◆ ENET_RSFL_RX_SECTION_FULL [3/3]

#define ENET_RSFL_RX_SECTION_FULL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold

◆ ENET_RXIC_ICCS [1/3]

#define ENET_RXIC_ICCS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)

ICCS - Interrupt Coalescing Timer Clock Source Select 0b0..Use MII/GMII TX clocks. 0b1..Use ENET system clock.

◆ ENET_RXIC_ICCS [2/3]

#define ENET_RXIC_ICCS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)

ICCS - Interrupt Coalescing Timer Clock Source Select 0b0..Use MII/GMII TX clocks. 0b1..Use ENET system clock.

◆ ENET_RXIC_ICCS [3/3]

#define ENET_RXIC_ICCS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)

ICCS - Interrupt Coalescing Timer Clock Source Select 0b0..Use MII/GMII TX clocks. 0b1..Use ENET system clock.

◆ ENET_RXIC_ICEN [1/3]

#define ENET_RXIC_ICEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)

ICEN - Interrupt Coalescing Enable 0b0..Disable Interrupt coalescing. 0b1..Enable Interrupt coalescing.

◆ ENET_RXIC_ICEN [2/3]

#define ENET_RXIC_ICEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)

ICEN - Interrupt Coalescing Enable 0b0..Disable Interrupt coalescing. 0b1..Enable Interrupt coalescing.

◆ ENET_RXIC_ICEN [3/3]

#define ENET_RXIC_ICEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)

ICEN - Interrupt Coalescing Enable 0b0..Disable Interrupt coalescing. 0b1..Enable Interrupt coalescing.

◆ ENET_RXIC_ICFT [1/3]

#define ENET_RXIC_ICFT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)

ICFT - Interrupt coalescing frame count threshold

◆ ENET_RXIC_ICFT [2/3]

#define ENET_RXIC_ICFT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)

ICFT - Interrupt coalescing frame count threshold

◆ ENET_RXIC_ICFT [3/3]

#define ENET_RXIC_ICFT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)

ICFT - Interrupt coalescing frame count threshold

◆ ENET_RXIC_ICTT [1/3]

#define ENET_RXIC_ICTT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)

ICTT - Interrupt coalescing timer threshold

◆ ENET_RXIC_ICTT [2/3]

#define ENET_RXIC_ICTT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)

ICTT - Interrupt coalescing timer threshold

◆ ENET_RXIC_ICTT [3/3]

#define ENET_RXIC_ICTT ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)

ICTT - Interrupt coalescing timer threshold

◆ ENET_TACC_IPCHK [1/3]

#define ENET_TACC_IPCHK ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.

◆ ENET_TACC_IPCHK [2/3]

#define ENET_TACC_IPCHK ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.

◆ ENET_TACC_IPCHK [3/3]

#define ENET_TACC_IPCHK ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.

◆ ENET_TACC_PROCHK [1/3]

#define ENET_TACC_PROCHK ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.

◆ ENET_TACC_PROCHK [2/3]

#define ENET_TACC_PROCHK ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.

◆ ENET_TACC_PROCHK [3/3]

#define ENET_TACC_PROCHK ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.

◆ ENET_TACC_SHIFT16 [1/3]

#define ENET_TACC_SHIFT16 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.

◆ ENET_TACC_SHIFT16 [2/3]

#define ENET_TACC_SHIFT16 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.

◆ ENET_TACC_SHIFT16 [3/3]

#define ENET_TACC_SHIFT16 ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.

◆ ENET_TAEM_TX_ALMOST_EMPTY [1/3]

#define ENET_TAEM_TX_ALMOST_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)

TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold

◆ ENET_TAEM_TX_ALMOST_EMPTY [2/3]

#define ENET_TAEM_TX_ALMOST_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold

◆ ENET_TAEM_TX_ALMOST_EMPTY [3/3]

#define ENET_TAEM_TX_ALMOST_EMPTY ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold

◆ ENET_TAFL_TX_ALMOST_FULL [1/3]

#define ENET_TAFL_TX_ALMOST_FULL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)

TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold

◆ ENET_TAFL_TX_ALMOST_FULL [2/3]

#define ENET_TAFL_TX_ALMOST_FULL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold

◆ ENET_TAFL_TX_ALMOST_FULL [3/3]

#define ENET_TAFL_TX_ALMOST_FULL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */

TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold

◆ ENET_TCCR_TCC [1/3]

#define ENET_TCCR_TCC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)

TCC - Timer Capture Compare

◆ ENET_TCCR_TCC [2/3]

#define ENET_TCCR_TCC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)

TCC - Timer Capture Compare

◆ ENET_TCCR_TCC [3/3]

#define ENET_TCCR_TCC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)

TCC - Timer Capture Compare

◆ ENET_TCR_ADDINS [1/3]

#define ENET_TCR_ADDINS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.

◆ ENET_TCR_ADDINS [2/3]

#define ENET_TCR_ADDINS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.

◆ ENET_TCR_ADDINS [3/3]

#define ENET_TCR_ADDINS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.

◆ ENET_TCR_ADDSEL [1/3]

#define ENET_TCR_ADDSEL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.

◆ ENET_TCR_ADDSEL [2/3]

#define ENET_TCR_ADDSEL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.

◆ ENET_TCR_ADDSEL [3/3]

#define ENET_TCR_ADDSEL ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.

◆ ENET_TCR_CRCFWD [1/3]

#define ENET_TCR_CRCFWD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.

◆ ENET_TCR_CRCFWD [2/3]

#define ENET_TCR_CRCFWD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.

◆ ENET_TCR_CRCFWD [3/3]

#define ENET_TCR_CRCFWD ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.

◆ ENET_TCR_FDEN [1/3]

#define ENET_TCR_FDEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)

FDEN - Full-Duplex Enable 0b0..Disable full-duplex 0b1..Enable full-duplex

◆ ENET_TCR_FDEN [2/3]

#define ENET_TCR_FDEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)

FDEN - Full-Duplex Enable 0b0..Disable full-duplex 0b1..Enable full-duplex

◆ ENET_TCR_FDEN [3/3]

#define ENET_TCR_FDEN ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)

FDEN - Full-Duplex Enable 0b0..Disable full-duplex 0b1..Enable full-duplex

◆ ENET_TCR_GTS [1/3]

#define ENET_TCR_GTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)

GTS - Graceful Transmit Stop 0b0..Disable graceful transmit stop 0b1..Enable graceful transmit stop

◆ ENET_TCR_GTS [2/3]

#define ENET_TCR_GTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)

GTS - Graceful Transmit Stop 0b0..Disable graceful transmit stop 0b1..Enable graceful transmit stop

◆ ENET_TCR_GTS [3/3]

#define ENET_TCR_GTS ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)

GTS - Graceful Transmit Stop 0b0..Disable graceful transmit stop 0b1..Enable graceful transmit stop

◆ ENET_TCR_RFC_PAUSE [1/3]

#define ENET_TCR_RFC_PAUSE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)

RFC_PAUSE - Receive Frame Control Pause

◆ ENET_TCR_RFC_PAUSE [2/3]

#define ENET_TCR_RFC_PAUSE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)

RFC_PAUSE - Receive Frame Control Pause

◆ ENET_TCR_RFC_PAUSE [3/3]

#define ENET_TCR_RFC_PAUSE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)

RFC_PAUSE - Receive Frame Control Pause

◆ ENET_TCR_TFC_PAUSE [1/3]

#define ENET_TCR_TFC_PAUSE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.

◆ ENET_TCR_TFC_PAUSE [2/3]

#define ENET_TCR_TFC_PAUSE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.

◆ ENET_TCR_TFC_PAUSE [3/3]

#define ENET_TCR_TFC_PAUSE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.

◆ ENET_TCSR_TDRE [1/3]

#define ENET_TCSR_TDRE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ ENET_TCSR_TDRE [2/3]

#define ENET_TCSR_TDRE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ ENET_TCSR_TDRE [3/3]

#define ENET_TCSR_TDRE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

◆ ENET_TCSR_TF [1/3]

#define ENET_TCSR_TF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.

◆ ENET_TCSR_TF [2/3]

#define ENET_TCSR_TF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.

◆ ENET_TCSR_TF [3/3]

#define ENET_TCSR_TF ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.

◆ ENET_TCSR_TIE [1/3]

#define ENET_TCSR_TIE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled

◆ ENET_TCSR_TIE [2/3]

#define ENET_TCSR_TIE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled

◆ ENET_TCSR_TIE [3/3]

#define ENET_TCSR_TIE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled

◆ ENET_TCSR_TMODE [1/3]

#define ENET_TCSR_TMODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.

◆ ENET_TCSR_TMODE [2/3]

#define ENET_TCSR_TMODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.

◆ ENET_TCSR_TMODE [3/3]

#define ENET_TCSR_TMODE ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.

◆ ENET_TCSR_TPWC [1/3]

#define ENET_TCSR_TPWC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)

TPWC - Timer PulseWidth Control 0b00000..Pulse width is one 1588-clock cycle. 0b00001..Pulse width is two 1588-clock cycles. 0b00010..Pulse width is three 1588-clock cycles. 0b00011..Pulse width is four 1588-clock cycles. 0b11111..Pulse width is 32 1588-clock cycles.

◆ ENET_TCSR_TPWC [2/3]

#define ENET_TCSR_TPWC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)

TPWC - Timer PulseWidth Control 0b00000..Pulse width is one 1588-clock cycle. 0b00001..Pulse width is two 1588-clock cycles. 0b00010..Pulse width is three 1588-clock cycles. 0b00011..Pulse width is four 1588-clock cycles. 0b11111..Pulse width is 32 1588-clock cycles.

◆ ENET_TCSR_TPWC [3/3]

#define ENET_TCSR_TPWC ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)

TPWC - Timer PulseWidth Control 0b00000..Pulse width is one 1588-clock cycle. 0b00001..Pulse width is two 1588-clock cycles. 0b00010..Pulse width is three 1588-clock cycles. 0b00011..Pulse width is four 1588-clock cycles. 0b11111..Pulse width is 32 1588-clock cycles.

◆ ENET_TDAR1_TDAR [1/2]

#define ENET_TDAR1_TDAR ( x ) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)