RTEMS 6.1-rc4
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CMSIS Peripheral Access Layer for MIMXRT1166_cm4. More...
Go to the source code of this file.
Macros | |
#define | _MIMXRT1166_CM4_H_ |
#define | MCU_MEM_MAP_VERSION 0x0000U |
#define | MCU_MEM_MAP_VERSION_MINOR 0x0001U |
#define | XRDC2_MAKE_MEM(mrc, mrgd) (((mrc) << 5U) | (mrgd)) |
#define | XRDC2_GET_MRC(mem) ((mem) >> 5U) |
#define | XRDC2_GET_MRGD(mem) ((mem) & 31U) |
#define | XRDC2_MAKE_PERIPH(pac, pdac) (((pac) << 8U) | (pdac)) |
#define | XRDC2_GET_PAC(periph) ((periph) >> 8U) |
#define | XRDC2_GET_PDAC(periph) ((periph) & 255U) |
#define | NUMBER_OF_INT_VECTORS 234 |
#define | __MPU_PRESENT 1 |
#define | __NVIC_PRIO_BITS 4 |
#define | __Vendor_SysTickConfig 0 |
#define | __FPU_PRESENT 1 |
#define | ADC_TCTRL_COUNT (8U) |
#define | ADC_CMDL_COUNT (15U) |
#define | ADC_CMDH_COUNT (15U) |
#define | ADC_CV_COUNT (4U) |
#define | LPADC1_BASE (0x40050000u) |
#define | LPADC1 ((ADC_Type *)LPADC1_BASE) |
#define | LPADC2_BASE (0x40054000u) |
#define | LPADC2 ((ADC_Type *)LPADC2_BASE) |
#define | ADC_BASE_ADDRS { 0u, LPADC1_BASE, LPADC2_BASE } |
#define | ADC_BASE_PTRS { (ADC_Type *)0u, LPADC1, LPADC2 } |
#define | ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } |
#define | ADC_ETC_TRIGn_CTRL_COUNT (8U) |
#define | ADC_ETC_TRIGn_COUNTER_COUNT (8U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) |
#define | ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) |
#define | ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) |
#define | ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) |
#define | ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) |
#define | ADC_ETC_BASE (0x40048000u) |
#define | ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) |
#define | ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } |
#define | ADC_ETC_BASE_PTRS { ADC_ETC } |
#define | ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn, ADC_ETC_IRQ3_IRQn } } |
#define | ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } |
#define | ANADIG_LDO_SNVS_BASE (0x40C84000u) |
#define | ANADIG_LDO_SNVS ((ANADIG_LDO_SNVS_Type *)ANADIG_LDO_SNVS_BASE) |
#define | ANADIG_LDO_SNVS_BASE_ADDRS { ANADIG_LDO_SNVS_BASE } |
#define | ANADIG_LDO_SNVS_BASE_PTRS { ANADIG_LDO_SNVS } |
#define | ANADIG_LDO_SNVS_DIG_BASE (0x40C84000u) |
#define | ANADIG_LDO_SNVS_DIG ((ANADIG_LDO_SNVS_DIG_Type *)ANADIG_LDO_SNVS_DIG_BASE) |
#define | ANADIG_LDO_SNVS_DIG_BASE_ADDRS { ANADIG_LDO_SNVS_DIG_BASE } |
#define | ANADIG_LDO_SNVS_DIG_BASE_PTRS { ANADIG_LDO_SNVS_DIG } |
#define | ANADIG_MISC_BASE (0x40C84000u) |
#define | ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE) |
#define | ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE } |
#define | ANADIG_MISC_BASE_PTRS { ANADIG_MISC } |
#define | ANADIG_OSC_BASE (0x40C84000u) |
#define | ANADIG_OSC ((ANADIG_OSC_Type *)ANADIG_OSC_BASE) |
#define | ANADIG_OSC_BASE_ADDRS { ANADIG_OSC_BASE } |
#define | ANADIG_OSC_BASE_PTRS { ANADIG_OSC } |
#define | ANADIG_PLL_BASE (0x40C84000u) |
#define | ANADIG_PLL ((ANADIG_PLL_Type *)ANADIG_PLL_BASE) |
#define | ANADIG_PLL_BASE_ADDRS { ANADIG_PLL_BASE } |
#define | ANADIG_PLL_BASE_PTRS { ANADIG_PLL } |
#define | ANADIG_PMU_BASE (0x40C84000u) |
#define | ANADIG_PMU ((ANADIG_PMU_Type *)ANADIG_PMU_BASE) |
#define | ANADIG_PMU_BASE_ADDRS { ANADIG_PMU_BASE } |
#define | ANADIG_PMU_BASE_PTRS { ANADIG_PMU } |
#define | ANADIG_TEMPSENSOR_BASE (0x40C84000u) |
#define | ANADIG_TEMPSENSOR ((ANADIG_TEMPSENSOR_Type *)ANADIG_TEMPSENSOR_BASE) |
#define | ANADIG_TEMPSENSOR_BASE_ADDRS { ANADIG_TEMPSENSOR_BASE } |
#define | ANADIG_TEMPSENSOR_BASE_PTRS { ANADIG_TEMPSENSOR } |
#define | AOI_BFCRT01_COUNT (4U) |
#define | AOI_BFCRT23_COUNT (4U) |
#define | AOI1_BASE (0x400B8000u) |
#define | AOI1 ((AOI_Type *)AOI1_BASE) |
#define | AOI2_BASE (0x400BC000u) |
#define | AOI2 ((AOI_Type *)AOI2_BASE) |
#define | AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE } |
#define | AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 } |
#define | ASRC_ASRPM_COUNT (5U) |
#define | ASRC_ASRMCR1_COUNT (3U) |
#define | ASRC_BASE (0x40414000u) |
#define | ASRC ((ASRC_Type *)ASRC_BASE) |
#define | ASRC_BASE_ADDRS { ASRC_BASE } |
#define | ASRC_BASE_PTRS { ASRC } |
#define | ASRC_IRQS { ASRC_IRQn } |
#define | AUDIO_PLL_BASE (0u) |
#define | AUDIO_PLL ((AUDIO_PLL_Type *)AUDIO_PLL_BASE) |
#define | AUDIO_PLL_BASE_ADDRS { AUDIO_PLL_BASE } |
#define | AUDIO_PLL_BASE_PTRS { AUDIO_PLL } |
#define | CAAM_JRDID_MS_COUNT (4U) |
#define | CAAM_JRDID_LS_COUNT (4U) |
#define | CAAM_RTIC_DID_COUNT (4U) |
#define | CAAM_DECODID_MS_COUNT (1U) |
#define | CAAM_DECODID_LS_COUNT (1U) |
#define | CAAM_JRSMVBAR_COUNT (4U) |
#define | CAAM_DMA_AIDL_MAP_MS_COUNT (1U) |
#define | CAAM_DMA_AIDL_MAP_LS_COUNT (1U) |
#define | CAAM_DMA_AIDM_MAP_MS_COUNT (1U) |
#define | CAAM_DMA_AIDM_MAP_LS_COUNT (1U) |
#define | CAAM_MPPKR_COUNT (64U) |
#define | CAAM_MPMR_COUNT (32U) |
#define | CAAM_MPTESTR_COUNT (32U) |
#define | CAAM_JDKEKR_COUNT (8U) |
#define | CAAM_TDKEKR_COUNT (8U) |
#define | CAAM_TDSKR_COUNT (8U) |
#define | CAAM_RTENT_COUNT (16U) |
#define | CAAM_PX_SDID_PG0_COUNT (16U) |
#define | CAAM_PX_SMAPR_PG0_COUNT (16U) |
#define | CAAM_PX_SMAG2_PG0_COUNT (16U) |
#define | CAAM_PX_SMAG1_PG0_COUNT (16U) |
#define | CAAM_SMWPJRR_COUNT (4U) |
#define | CAAM_HT_JD_ADDR_COUNT (1U) |
#define | CAAM_HT_SD_ADDR_COUNT (1U) |
#define | CAAM_HT_JQ_CTRL_MS_COUNT (1U) |
#define | CAAM_HT_JQ_CTRL_LS_COUNT (1U) |
#define | CAAM_HT_STATUS_COUNT (1U) |
#define | CAAM_JRJDDA_COUNT (1U) |
#define | CAAM_IRBAR_JR_COUNT (4U) |
#define | CAAM_IRSR_JR_COUNT (4U) |
#define | CAAM_IRSAR_JR_COUNT (4U) |
#define | CAAM_IRJAR_JR_COUNT (4U) |
#define | CAAM_ORBAR_JR_COUNT (4U) |
#define | CAAM_ORSR_JR_COUNT (4U) |
#define | CAAM_ORJRR_JR_COUNT (4U) |
#define | CAAM_ORSFR_JR_COUNT (4U) |
#define | CAAM_JRSTAR_JR_COUNT (4U) |
#define | CAAM_JRINTR_JR_COUNT (4U) |
#define | CAAM_JRCFGR_JR_MS_COUNT (4U) |
#define | CAAM_JRCFGR_JR_LS_COUNT (4U) |
#define | CAAM_IRRIR_JR_COUNT (4U) |
#define | CAAM_ORWIR_JR_COUNT (4U) |
#define | CAAM_JRCR_JR_COUNT (4U) |
#define | CAAM_JRAAV_COUNT (4U) |
#define | CAAM_JRAAA_COUNT (4U) |
#define | CAAM_JRAAA_COUNT2 (4U) |
#define | CAAM_PX_SDID_JR_COUNT (4U) |
#define | CAAM_PX_SDID_JR_COUNT2 (16U) |
#define | CAAM_PX_SMAPR_JR_COUNT (4U) |
#define | CAAM_PX_SMAPR_JR_COUNT2 (16U) |
#define | CAAM_PX_SMAG2_JR_COUNT (4U) |
#define | CAAM_PX_SMAG2_JR_COUNT2 (16U) |
#define | CAAM_PX_SMAG1_JR_COUNT (4U) |
#define | CAAM_PX_SMAG1_JR_COUNT2 (16U) |
#define | CAAM_SMCR_JR_COUNT (4U) |
#define | CAAM_SMCSR_JR_COUNT (4U) |
#define | CAAM_REIR0JR_COUNT (4U) |
#define | CAAM_REIR2JR_COUNT (4U) |
#define | CAAM_REIR4JR_COUNT (4U) |
#define | CAAM_REIR5JR_COUNT (4U) |
#define | CAAM_RMA_COUNT (4U) |
#define | CAAM_RMA_COUNT2 (2U) |
#define | CAAM_RML_COUNT (4U) |
#define | CAAM_RML_COUNT2 (2U) |
#define | CAAM_RMD_COUNT (4U) |
#define | CAAM_RMD_COUNT2 (2U) |
#define | CAAM_RMD_COUNT3 (32U) |
#define | CAAM_CC1MR_COUNT (1U) |
#define | CAAM_CC1MR_PK_COUNT (1U) |
#define | CAAM_CC1MR_RNG_COUNT (1U) |
#define | CAAM_CC1KSR_COUNT (1U) |
#define | CAAM_CC1DSR_COUNT (1U) |
#define | CAAM_CC1ICVSR_COUNT (1U) |
#define | CAAM_CCCTRL_COUNT (1U) |
#define | CAAM_CICTL_COUNT (1U) |
#define | CAAM_CCWR_COUNT (1U) |
#define | CAAM_CCSTA_MS_COUNT (1U) |
#define | CAAM_CCSTA_LS_COUNT (1U) |
#define | CAAM_CC1AADSZR_COUNT (1U) |
#define | CAAM_CC1IVSZR_COUNT (1U) |
#define | CAAM_CPKASZR_COUNT (1U) |
#define | CAAM_CPKBSZR_COUNT (1U) |
#define | CAAM_CPKNSZR_COUNT (1U) |
#define | CAAM_CPKESZR_COUNT (1U) |
#define | CAAM_CC1CTXR_COUNT (1U) |
#define | CAAM_CC1CTXR_COUNT2 (16U) |
#define | CAAM_CC1KR_COUNT (1U) |
#define | CAAM_CC1KR_COUNT2 (8U) |
#define | CAAM_CC2MR_COUNT (1U) |
#define | CAAM_CC2KSR_COUNT (1U) |
#define | CAAM_CC2DSR_COUNT (1U) |
#define | CAAM_CC2ICVSZR_COUNT (1U) |
#define | CAAM_CC2CTXR_COUNT (1U) |
#define | CAAM_CC2CTXR_COUNT2 (18U) |
#define | CAAM_CC2KEYR_COUNT (1U) |
#define | CAAM_CC2KEYR_COUNT2 (32U) |
#define | CAAM_CFIFOSTA_COUNT (1U) |
#define | CAAM_CNFIFO_COUNT (1U) |
#define | CAAM_CNFIFO_2_COUNT (1U) |
#define | CAAM_CIFIFO_COUNT (1U) |
#define | CAAM_COFIFO_COUNT (1U) |
#define | CAAM_DJQCR_MS_COUNT (1U) |
#define | CAAM_DJQCR_LS_COUNT (1U) |
#define | CAAM_DDAR_COUNT (1U) |
#define | CAAM_DOPSTA_MS_COUNT (1U) |
#define | CAAM_DOPSTA_LS_COUNT (1U) |
#define | CAAM_DPDIDSR_COUNT (1U) |
#define | CAAM_DODIDSR_COUNT (1U) |
#define | CAAM_DMTH_MS_COUNT (1U) |
#define | CAAM_DMTH_MS_COUNT2 (4U) |
#define | CAAM_DMTH_LS_COUNT (1U) |
#define | CAAM_DMTH_LS_COUNT2 (4U) |
#define | CAAM_DGTR_0_COUNT (1U) |
#define | CAAM_DGTR_0_COUNT2 (1U) |
#define | CAAM_DGTR_1_COUNT (1U) |
#define | CAAM_DGTR_1_COUNT2 (1U) |
#define | CAAM_DGTR_2_COUNT (1U) |
#define | CAAM_DGTR_2_COUNT2 (1U) |
#define | CAAM_DGTR_3_COUNT (1U) |
#define | CAAM_DGTR_3_COUNT2 (1U) |
#define | CAAM_DSTR_0_COUNT (1U) |
#define | CAAM_DSTR_0_COUNT2 (1U) |
#define | CAAM_DSTR_1_COUNT (1U) |
#define | CAAM_DSTR_1_COUNT2 (1U) |
#define | CAAM_DSTR_2_COUNT (1U) |
#define | CAAM_DSTR_2_COUNT2 (1U) |
#define | CAAM_DSTR_3_COUNT (1U) |
#define | CAAM_DSTR_3_COUNT2 (1U) |
#define | CAAM_DDESB_COUNT (1U) |
#define | CAAM_DDESB_COUNT2 (64U) |
#define | CAAM_DDJR_COUNT (1U) |
#define | CAAM_DDDR_COUNT (1U) |
#define | CAAM_DDJP_COUNT (1U) |
#define | CAAM_DSDP_COUNT (1U) |
#define | CAAM_DDDR_MS_COUNT (1U) |
#define | CAAM_DDDR_LS_COUNT (1U) |
#define | CAAM_SOL_COUNT (1U) |
#define | CAAM_VSOL_COUNT (1U) |
#define | CAAM_SIL_COUNT (1U) |
#define | CAAM_VSIL_COUNT (1U) |
#define | CAAM_DPOVRD_COUNT (1U) |
#define | CAAM_UVSOL_COUNT (1U) |
#define | CAAM_UVSIL_COUNT (1U) |
#define | CAAM_BASE (0x40440000u) |
#define | CAAM ((CAAM_Type *)CAAM_BASE) |
#define | CAAM_BASE_ADDRS { CAAM_BASE } |
#define | CAAM_BASE_PTRS { CAAM } |
#define | CAN_CS_COUNT_MB8B (64U) |
#define | CAN_ID_COUNT_MB8B (64U) |
#define | CAN_WORD_COUNT_MB8B (64U) |
#define | CAN_WORD_COUNT_MB8B2 (2U) |
#define | CAN_CS_COUNT_MB16B_L (21U) |
#define | CAN_ID_COUNT_MB16B_L (21U) |
#define | CAN_WORD_COUNT_MB16B_L (21U) |
#define | CAN_WORD_COUNT_MB16B_L2 (4U) |
#define | CAN_CS_COUNT_MB16B_H (21U) |
#define | CAN_ID_COUNT_MB16B_H (21U) |
#define | CAN_WORD_COUNT_MB16B_H (21U) |
#define | CAN_WORD_COUNT_MB16B_H2 (4U) |
#define | CAN_CS_COUNT_MB32B_L (12U) |
#define | CAN_ID_COUNT_MB32B_L (12U) |
#define | CAN_WORD_COUNT_MB32B_L (12U) |
#define | CAN_WORD_COUNT_MB32B_L2 (8U) |
#define | CAN_CS_COUNT_MB32B_H (12U) |
#define | CAN_ID_COUNT_MB32B_H (12U) |
#define | CAN_WORD_COUNT_MB32B_H (12U) |
#define | CAN_WORD_COUNT_MB32B_H2 (8U) |
#define | CAN_CS_COUNT_MB64B_L (7U) |
#define | CAN_ID_COUNT_MB64B_L (7U) |
#define | CAN_WORD_COUNT_MB64B_L (7U) |
#define | CAN_WORD_COUNT_MB64B_L2 (16U) |
#define | CAN_CS_COUNT_MB64B_H (7U) |
#define | CAN_ID_COUNT_MB64B_H (7U) |
#define | CAN_WORD_COUNT_MB64B_H (7U) |
#define | CAN_WORD_COUNT_MB64B_H2 (16U) |
#define | CAN_CS_COUNT (64U) |
#define | CAN_ID_COUNT (64U) |
#define | CAN_WORD0_COUNT (64U) |
#define | CAN_WORD1_COUNT (64U) |
#define | CAN_RXIMR_COUNT (64U) |
#define | CAN1_BASE (0x400C4000u) |
#define | CAN1 ((CAN_Type *)CAN1_BASE) |
#define | CAN2_BASE (0x400C8000u) |
#define | CAN2 ((CAN_Type *)CAN2_BASE) |
#define | CAN3_BASE (0x40C3C000u) |
#define | CAN3 ((CAN_Type *)CAN3_BASE) |
#define | CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE } |
#define | CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2, CAN3 } |
#define | CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } |
#define | CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } |
#define | CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } |
#define | CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } |
#define | CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } |
#define | CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } |
#define | CAN1_WRAPPER_BASE (0x400C4000u) |
#define | CAN1_WRAPPER ((CAN_WRAPPER_Type *)CAN1_WRAPPER_BASE) |
#define | CAN2_WRAPPER_BASE (0x400C8000u) |
#define | CAN2_WRAPPER ((CAN_WRAPPER_Type *)CAN2_WRAPPER_BASE) |
#define | CAN3_WRAPPER_BASE (0x40C3C000u) |
#define | CAN3_WRAPPER ((CAN_WRAPPER_Type *)CAN3_WRAPPER_BASE) |
#define | CAN_WRAPPER_BASE_ADDRS { 0u, CAN1_WRAPPER_BASE, CAN2_WRAPPER_BASE, CAN3_WRAPPER_BASE } |
#define | CAN_WRAPPER_BASE_PTRS { (CAN_WRAPPER_Type *)0u, CAN1_WRAPPER, CAN2_WRAPPER, CAN3_WRAPPER } |
#define | CCM_CLOCK_ROOT_CONTROL_COUNT (79U) |
#define | CCM_CLOCK_ROOT_CONTROL_SET_COUNT (79U) |
#define | CCM_CLOCK_ROOT_CONTROL_CLR_COUNT (79U) |
#define | CCM_CLOCK_ROOT_CONTROL_TOG_COUNT (79U) |
#define | CCM_CLOCK_ROOT_STATUS0_COUNT (79U) |
#define | CCM_CLOCK_ROOT_STATUS1_COUNT (79U) |
#define | CCM_CLOCK_ROOT_CONFIG_COUNT (79U) |
#define | CCM_CLOCK_ROOT_AUTHEN_COUNT (79U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_COUNT (79U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_COUNT (79U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_COUNT (79U) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT (79U) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT2 (16U) |
#define | CCM_CLOCK_GROUP_CONTROL_COUNT (2U) |
#define | CCM_CLOCK_GROUP_CONTROL_SET_COUNT (2U) |
#define | CCM_CLOCK_GROUP_CONTROL_CLR_COUNT (2U) |
#define | CCM_CLOCK_GROUP_CONTROL_TOG_COUNT (2U) |
#define | CCM_CLOCK_GROUP_STATUS0_COUNT (2U) |
#define | CCM_CLOCK_GROUP_STATUS1_COUNT (2U) |
#define | CCM_CLOCK_GROUP_CONFIG_COUNT (2U) |
#define | CCM_CLOCK_GROUP_AUTHEN_COUNT (2U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_COUNT (2U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_COUNT (2U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_COUNT (2U) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT (2U) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT2 (16U) |
#define | CCM_GPR_SHARED_COUNT (8U) |
#define | CCM_GPR_SHARED_SET_COUNT (8U) |
#define | CCM_GPR_SHARED_CLR_COUNT (8U) |
#define | CCM_GPR_SHARED_TOG_COUNT (8U) |
#define | CCM_GPR_SHARED_AUTHEN_COUNT (8U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_COUNT (8U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_COUNT (8U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_COUNT (8U) |
#define | CCM_OSCPLL_DIRECT_COUNT (29U) |
#define | CCM_OSCPLL_DOMAIN_COUNT (29U) |
#define | CCM_OSCPLL_SETPOINT_COUNT (29U) |
#define | CCM_OSCPLL_STATUS0_COUNT (29U) |
#define | CCM_OSCPLL_STATUS1_COUNT (29U) |
#define | CCM_OSCPLL_CONFIG_COUNT (29U) |
#define | CCM_OSCPLL_AUTHEN_COUNT (29U) |
#define | CCM_LPCG_DIRECT_COUNT (138U) |
#define | CCM_LPCG_DOMAIN_COUNT (138U) |
#define | CCM_LPCG_SETPOINT_COUNT (138U) |
#define | CCM_LPCG_STATUS0_COUNT (138U) |
#define | CCM_LPCG_STATUS1_COUNT (138U) |
#define | CCM_LPCG_CONFIG_COUNT (138U) |
#define | CCM_LPCG_AUTHEN_COUNT (138U) |
#define | CCM_BASE (0x40CC0000u) |
#define | CCM ((CCM_Type *)CCM_BASE) |
#define | CCM_BASE_ADDRS { CCM_BASE } |
#define | CCM_BASE_PTRS { CCM } |
#define | CCM_OBS_OBSERVE_CONTROL_COUNT (6U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_COUNT (6U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_COUNT (6U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_COUNT (6U) |
#define | CCM_OBS_OBSERVE_STATUS0_COUNT (6U) |
#define | CCM_OBS_OBSERVE_AUTHEN_COUNT (6U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_COUNT (6U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_COUNT (6U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_COUNT (6U) |
#define | CCM_OBS_OBSERVE_FREQUENCY_CURRENT_COUNT (6U) |
#define | CCM_OBS_OBSERVE_FREQUENCY_MIN_COUNT (6U) |
#define | CCM_OBS_OBSERVE_FREQUENCY_MAX_COUNT (6U) |
#define | CCM_OBS_BASE (0x40150000u) |
#define | CCM_OBS ((CCM_OBS_Type *)CCM_OBS_BASE) |
#define | CCM_OBS_BASE_ADDRS { CCM_OBS_BASE } |
#define | CCM_OBS_BASE_PTRS { CCM_OBS } |
#define | CDOG_BASE (0x41900000u) |
#define | CDOG ((CDOG_Type *)CDOG_BASE) |
#define | CDOG_BASE_ADDRS { CDOG_BASE } |
#define | CDOG_BASE_PTRS { CDOG } |
#define | CMP1_BASE (0x401A4000u) |
#define | CMP1 ((CMP_Type *)CMP1_BASE) |
#define | CMP2_BASE (0x401A8000u) |
#define | CMP2 ((CMP_Type *)CMP2_BASE) |
#define | CMP3_BASE (0x401AC000u) |
#define | CMP3 ((CMP_Type *)CMP3_BASE) |
#define | CMP4_BASE (0x401B0000u) |
#define | CMP4 ((CMP_Type *)CMP4_BASE) |
#define | CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE } |
#define | CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 } |
#define | CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn } |
#define | CSI_CR_COUNT (256U) |
#define | CSI_BASE (0x40800000u) |
#define | CSI ((CSI_Type *)CSI_BASE) |
#define | CSI_BASE_ADDRS { CSI_BASE } |
#define | CSI_BASE_PTRS { CSI } |
#define | CSI_IRQS { CSI_IRQn } |
#define | CSI_CSICR1_PIXEL_BIT_MASK CSI_CR1_PIXEL_BIT_MASK |
#define | CSI_CSICR1_PIXEL_BIT_SHIFT CSI_CR1_PIXEL_BIT_SHIFT |
#define | CSI_CSICR1_PIXEL_BIT(x) CSI_CR1_PIXEL_BIT(x) |
#define | CSI_CSICR1_REDGE_MASK CSI_CR1_REDGE_MASK |
#define | CSI_CSICR1_REDGE_SHIFT CSI_CR1_REDGE_SHIFT |
#define | CSI_CSICR1_REDGE(x) CSI_CR1_REDGE(x) |
#define | CSI_CSICR1_INV_PCLK_MASK CSI_CR1_INV_PCLK_MASK |
#define | CSI_CSICR1_INV_PCLK_SHIFT CSI_CR1_INV_PCLK_SHIFT |
#define | CSI_CSICR1_INV_PCLK(x) CSI_CR1_INV_PCLK(x) |
#define | CSI_CSICR1_INV_DATA_MASK CSI_CR1_INV_DATA_MASK |
#define | CSI_CSICR1_INV_DATA_SHIFT CSI_CR1_INV_DATA_SHIFT |
#define | CSI_CSICR1_INV_DATA(x) CSI_CR1_INV_DATA(x) |
#define | CSI_CSICR1_GCLK_MODE_MASK CSI_CR1_GCLK_MODE_MASK |
#define | CSI_CSICR1_GCLK_MODE_SHIFT CSI_CR1_GCLK_MODE_SHIFT |
#define | CSI_CSICR1_GCLK_MODE(x) CSI_CR1_GCLK_MODE(x) |
#define | CSI_CSICR1_CLR_RXFIFO_MASK CSI_CR1_CLR_RXFIFO_MASK |
#define | CSI_CSICR1_CLR_RXFIFO_SHIFT CSI_CR1_CLR_RXFIFO_SHIFT |
#define | CSI_CSICR1_CLR_RXFIFO(x) CSI_CR1_CLR_RXFIFO(x) |
#define | CSI_CSICR1_CLR_STATFIFO_MASK CSI_CR1_CLR_STATFIFO_MASK |
#define | CSI_CSICR1_CLR_STATFIFO_SHIFT CSI_CR1_CLR_STATFIFO_SHIFT |
#define | CSI_CSICR1_CLR_STATFIFO(x) CSI_CR1_CLR_STATFIFO(x) |
#define | CSI_CSICR1_PACK_DIR_MASK CSI_CR1_PACK_DIR_MASK |
#define | CSI_CSICR1_PACK_DIR_SHIFT CSI_CR1_PACK_DIR_SHIFT |
#define | CSI_CSICR1_PACK_DIR(x) CSI_CR1_PACK_DIR(x) |
#define | CSI_CSICR1_FCC_MASK CSI_CR1_FCC_MASK |
#define | CSI_CSICR1_FCC_SHIFT CSI_CR1_FCC_SHIFT |
#define | CSI_CSICR1_FCC(x) CSI_CR1_FCC(x) |
#define | CSI_CSICR1_CCIR_EN_MASK CSI_CR1_CCIR_EN_MASK |
#define | CSI_CSICR1_CCIR_EN_SHIFT CSI_CR1_CCIR_EN_SHIFT |
#define | CSI_CSICR1_CCIR_EN(x) CSI_CR1_CCIR_EN(x) |
#define | CSI_CSICR1_HSYNC_POL_MASK CSI_CR1_HSYNC_POL_MASK |
#define | CSI_CSICR1_HSYNC_POL_SHIFT CSI_CR1_HSYNC_POL_SHIFT |
#define | CSI_CSICR1_HSYNC_POL(x) CSI_CR1_HSYNC_POL(x) |
#define | CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_MASK CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK |
#define | CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_SHIFT CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT |
#define | CSI_CSICR1_HISTOGRAM_CALC_DONE_IE(x) CSI_CR1_HISTOGRAM_CALC_DONE_IE(x) |
#define | CSI_CSICR1_SOF_INTEN_MASK CSI_CR1_SOF_INTEN_MASK |
#define | CSI_CSICR1_SOF_INTEN_SHIFT CSI_CR1_SOF_INTEN_SHIFT |
#define | CSI_CSICR1_SOF_INTEN(x) CSI_CR1_SOF_INTEN(x) |
#define | CSI_CSICR1_SOF_POL_MASK CSI_CR1_SOF_POL_MASK |
#define | CSI_CSICR1_SOF_POL_SHIFT CSI_CR1_SOF_POL_SHIFT |
#define | CSI_CSICR1_SOF_POL(x) CSI_CR1_SOF_POL(x) |
#define | CSI_CSICR1_RXFF_INTEN_MASK CSI_CR1_RXFF_INTEN_MASK |
#define | CSI_CSICR1_RXFF_INTEN_SHIFT CSI_CR1_RXFF_INTEN_SHIFT |
#define | CSI_CSICR1_RXFF_INTEN(x) CSI_CR1_RXFF_INTEN(x) |
#define | CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK CSI_CR1_FB1_DMA_DONE_INTEN_MASK |
#define | CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT |
#define | CSI_CSICR1_FB1_DMA_DONE_INTEN(x) CSI_CR1_FB1_DMA_DONE_INTEN(x) |
#define | CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK CSI_CR1_FB2_DMA_DONE_INTEN_MASK |
#define | CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT |
#define | CSI_CSICR1_FB2_DMA_DONE_INTEN(x) CSI_CR1_FB2_DMA_DONE_INTEN(x) |
#define | CSI_CSICR1_STATFF_INTEN_MASK CSI_CR1_STATFF_INTEN_MASK |
#define | CSI_CSICR1_STATFF_INTEN_SHIFT CSI_CR1_STATFF_INTEN_SHIFT |
#define | CSI_CSICR1_STATFF_INTEN(x) CSI_CR1_STATFF_INTEN(x) |
#define | CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK CSI_CR1_SFF_DMA_DONE_INTEN_MASK |
#define | CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT |
#define | CSI_CSICR1_SFF_DMA_DONE_INTEN(x) CSI_CR1_SFF_DMA_DONE_INTEN(x) |
#define | CSI_CSICR1_RF_OR_INTEN_MASK CSI_CR1_RF_OR_INTEN_MASK |
#define | CSI_CSICR1_RF_OR_INTEN_SHIFT CSI_CR1_RF_OR_INTEN_SHIFT |
#define | CSI_CSICR1_RF_OR_INTEN(x) CSI_CR1_RF_OR_INTEN(x) |
#define | CSI_CSICR1_SF_OR_INTEN_MASK CSI_CR1_SF_OR_INTEN_MASK |
#define | CSI_CSICR1_SF_OR_INTEN_SHIFT CSI_CR1_SF_OR_INTEN_SHIFT |
#define | CSI_CSICR1_SF_OR_INTEN(x) CSI_CR1_SF_OR_INTEN(x) |
#define | CSI_CSICR1_COF_INT_EN_MASK CSI_CR1_COF_INT_EN_MASK |
#define | CSI_CSICR1_COF_INT_EN_SHIFT CSI_CR1_COF_INT_EN_SHIFT |
#define | CSI_CSICR1_COF_INT_EN(x) CSI_CR1_COF_INT_EN(x) |
#define | CSI_CSICR1_VIDEO_MODE_MASK CSI_CR1_VIDEO_MODE_MASK |
#define | CSI_CSICR1_VIDEO_MODE_SHIFT CSI_CR1_VIDEO_MODE_SHIFT |
#define | CSI_CSICR1_VIDEO_MODE(x) CSI_CR1_VIDEO_MODE(x) |
#define | CSI_CSICR1_EOF_INT_EN_MASK CSI_CR1_EOF_INT_EN_MASK |
#define | CSI_CSICR1_EOF_INT_EN_SHIFT CSI_CR1_EOF_INT_EN_SHIFT |
#define | CSI_CSICR1_EOF_INT_EN(x) CSI_CR1_EOF_INT_EN(x) |
#define | CSI_CSICR1_EXT_VSYNC_MASK CSI_CR1_EXT_VSYNC_MASK |
#define | CSI_CSICR1_EXT_VSYNC_SHIFT CSI_CR1_EXT_VSYNC_SHIFT |
#define | CSI_CSICR1_EXT_VSYNC(x) CSI_CR1_EXT_VSYNC(x) |
#define | CSI_CSICR1_SWAP16_EN_MASK CSI_CR1_SWAP16_EN_MASK |
#define | CSI_CSICR1_SWAP16_EN_SHIFT CSI_CR1_SWAP16_EN_SHIFT |
#define | CSI_CSICR1_SWAP16_EN(x) CSI_CR1_SWAP16_EN(x) |
#define | CSI_CSICR2_HSC_MASK CSI_CR2_HSC_MASK |
#define | CSI_CSICR2_HSC_SHIFT CSI_CR2_HSC_SHIFT |
#define | CSI_CSICR2_HSC(x) CSI_CR2_HSC(x) |
#define | CSI_CSICR2_VSC_MASK CSI_CR2_VSC_MASK |
#define | CSI_CSICR2_VSC_SHIFT CSI_CR2_VSC_SHIFT |
#define | CSI_CSICR2_VSC(x) CSI_CR2_VSC(x) |
#define | CSI_CSICR2_LVRM_MASK CSI_CR2_LVRM_MASK |
#define | CSI_CSICR2_LVRM_SHIFT CSI_CR2_LVRM_SHIFT |
#define | CSI_CSICR2_LVRM(x) CSI_CR2_LVRM(x) |
#define | CSI_CSICR2_BTS_MASK CSI_CR2_BTS_MASK |
#define | CSI_CSICR2_BTS_SHIFT CSI_CR2_BTS_SHIFT |
#define | CSI_CSICR2_BTS(x) CSI_CR2_BTS(x) |
#define | CSI_CSICR2_SCE_MASK CSI_CR2_SCE_MASK |
#define | CSI_CSICR2_SCE_SHIFT CSI_CR2_SCE_SHIFT |
#define | CSI_CSICR2_SCE(x) CSI_CR2_SCE(x) |
#define | CSI_CSICR2_AFS_MASK CSI_CR2_AFS_MASK |
#define | CSI_CSICR2_AFS_SHIFT CSI_CR2_AFS_SHIFT |
#define | CSI_CSICR2_AFS(x) CSI_CR2_AFS(x) |
#define | CSI_CSICR2_DRM_MASK CSI_CR2_DRM_MASK |
#define | CSI_CSICR2_DRM_SHIFT CSI_CR2_DRM_SHIFT |
#define | CSI_CSICR2_DRM(x) CSI_CR2_DRM(x) |
#define | CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK CSI_CR2_DMA_BURST_TYPE_SFF_MASK |
#define | CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT |
#define | CSI_CSICR2_DMA_BURST_TYPE_SFF(x) CSI_CR2_DMA_BURST_TYPE_SFF(x) |
#define | CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK CSI_CR2_DMA_BURST_TYPE_RFF_MASK |
#define | CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT |
#define | CSI_CSICR2_DMA_BURST_TYPE_RFF(x) CSI_CR2_DMA_BURST_TYPE_RFF(x) |
#define | CSI_CSICR3_ECC_AUTO_EN_MASK CSI_CR3_ECC_AUTO_EN_MASK |
#define | CSI_CSICR3_ECC_AUTO_EN_SHIFT CSI_CR3_ECC_AUTO_EN_SHIFT |
#define | CSI_CSICR3_ECC_AUTO_EN(x) CSI_CR3_ECC_AUTO_EN(x) |
#define | CSI_CSICR3_ECC_INT_EN_MASK CSI_CR3_ECC_INT_EN_MASK |
#define | CSI_CSICR3_ECC_INT_EN_SHIFT CSI_CR3_ECC_INT_EN_SHIFT |
#define | CSI_CSICR3_ECC_INT_EN(x) CSI_CR3_ECC_INT_EN(x) |
#define | CSI_CSICR3_ZERO_PACK_EN_MASK CSI_CR3_ZERO_PACK_EN_MASK |
#define | CSI_CSICR3_ZERO_PACK_EN_SHIFT CSI_CR3_ZERO_PACK_EN_SHIFT |
#define | CSI_CSICR3_ZERO_PACK_EN(x) CSI_CR3_ZERO_PACK_EN(x) |
#define | CSI_CSICR3_SENSOR_16BITS_MASK CSI_CR3_SENSOR_16BITS_MASK |
#define | CSI_CSICR3_SENSOR_16BITS_SHIFT CSI_CR3_SENSOR_16BITS_SHIFT |
#define | CSI_CSICR3_SENSOR_16BITS(x) CSI_CR3_SENSOR_16BITS(x) |
#define | CSI_CSICR3_RxFF_LEVEL_MASK CSI_CR3_RxFF_LEVEL_MASK |
#define | CSI_CSICR3_RxFF_LEVEL_SHIFT CSI_CR3_RxFF_LEVEL_SHIFT |
#define | CSI_CSICR3_RxFF_LEVEL(x) CSI_CR3_RxFF_LEVEL(x) |
#define | CSI_CSICR3_HRESP_ERR_EN_MASK CSI_CR3_HRESP_ERR_EN_MASK |
#define | CSI_CSICR3_HRESP_ERR_EN_SHIFT CSI_CR3_HRESP_ERR_EN_SHIFT |
#define | CSI_CSICR3_HRESP_ERR_EN(x) CSI_CR3_HRESP_ERR_EN(x) |
#define | CSI_CSICR3_STATFF_LEVEL_MASK CSI_CR3_STATFF_LEVEL_MASK |
#define | CSI_CSICR3_STATFF_LEVEL_SHIFT CSI_CR3_STATFF_LEVEL_SHIFT |
#define | CSI_CSICR3_STATFF_LEVEL(x) CSI_CR3_STATFF_LEVEL(x) |
#define | CSI_CSICR3_DMA_REQ_EN_SFF_MASK CSI_CR3_DMA_REQ_EN_SFF_MASK |
#define | CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT CSI_CR3_DMA_REQ_EN_SFF_SHIFT |
#define | CSI_CSICR3_DMA_REQ_EN_SFF(x) CSI_CR3_DMA_REQ_EN_SFF(x) |
#define | CSI_CSICR3_DMA_REQ_EN_RFF_MASK CSI_CR3_DMA_REQ_EN_RFF_MASK |
#define | CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT CSI_CR3_DMA_REQ_EN_RFF_SHIFT |
#define | CSI_CSICR3_DMA_REQ_EN_RFF(x) CSI_CR3_DMA_REQ_EN_RFF(x) |
#define | CSI_CSICR3_DMA_REFLASH_SFF_MASK CSI_CR3_DMA_REFLASH_SFF_MASK |
#define | CSI_CSICR3_DMA_REFLASH_SFF_SHIFT CSI_CR3_DMA_REFLASH_SFF_SHIFT |
#define | CSI_CSICR3_DMA_REFLASH_SFF(x) CSI_CR3_DMA_REFLASH_SFF(x) |
#define | CSI_CSICR3_DMA_REFLASH_RFF_MASK CSI_CR3_DMA_REFLASH_RFF_MASK |
#define | CSI_CSICR3_DMA_REFLASH_RFF_SHIFT CSI_CR3_DMA_REFLASH_RFF_SHIFT |
#define | CSI_CSICR3_DMA_REFLASH_RFF(x) CSI_CR3_DMA_REFLASH_RFF(x) |
#define | CSI_CSICR3_FRMCNT_RST_MASK CSI_CR3_FRMCNT_RST_MASK |
#define | CSI_CSICR3_FRMCNT_RST_SHIFT CSI_CR3_FRMCNT_RST_SHIFT |
#define | CSI_CSICR3_FRMCNT_RST(x) CSI_CR3_FRMCNT_RST(x) |
#define | CSI_CSICR3_FRMCNT_MASK CSI_CR3_FRMCNT_MASK |
#define | CSI_CSICR3_FRMCNT_SHIFT CSI_CR3_FRMCNT_SHIFT |
#define | CSI_CSICR3_FRMCNT(x) CSI_CR3_FRMCNT(x) |
#define | CSI_CSISTATFIFO_STAT_MASK CSI_STATFIFO_STAT_MASK |
#define | CSI_CSISTATFIFO_STAT_SHIFT CSI_STATFIFO_STAT_SHIFT |
#define | CSI_CSISTATFIFO_STAT(x) CSI_STATFIFO_STAT(x) |
#define | CSI_CSIRFIFO_IMAGE_MASK CSI_RFIFO_IMAGE_MASK |
#define | CSI_CSIRFIFO_IMAGE_SHIFT CSI_RFIFO_IMAGE_SHIFT |
#define | CSI_CSIRFIFO_IMAGE(x) CSI_RFIFO_IMAGE(x) |
#define | CSI_CSIRXCNT_RXCNT_MASK CSI_RXCNT_RXCNT_MASK |
#define | CSI_CSIRXCNT_RXCNT_SHIFT CSI_RXCNT_RXCNT_SHIFT |
#define | CSI_CSIRXCNT_RXCNT(x) CSI_RXCNT_RXCNT(x) |
#define | CSI_CSISR_DRDY_MASK CSI_SR_DRDY_MASK |
#define | CSI_CSISR_DRDY_SHIFT CSI_SR_DRDY_SHIFT |
#define | CSI_CSISR_DRDY(x) CSI_SR_DRDY(x) |
#define | CSI_CSISR_ECC_INT_MASK CSI_SR_ECC_INT_MASK |
#define | CSI_CSISR_ECC_INT_SHIFT CSI_SR_ECC_INT_SHIFT |
#define | CSI_CSISR_ECC_INT(x) CSI_SR_ECC_INT(x) |
#define | CSI_CSISR_HISTOGRAM_CALC_DONE_INT_MASK CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK |
#define | CSI_CSISR_HISTOGRAM_CALC_DONE_INT_SHIFT CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT |
#define | CSI_CSISR_HISTOGRAM_CALC_DONE_INT(x) CSI_SR_HISTOGRAM_CALC_DONE_INT(x) |
#define | CSI_CSISR_HRESP_ERR_INT_MASK CSI_SR_HRESP_ERR_INT_MASK |
#define | CSI_CSISR_HRESP_ERR_INT_SHIFT CSI_SR_HRESP_ERR_INT_SHIFT |
#define | CSI_CSISR_HRESP_ERR_INT(x) CSI_SR_HRESP_ERR_INT(x) |
#define | CSI_CSISR_COF_INT_MASK CSI_SR_COF_INT_MASK |
#define | CSI_CSISR_COF_INT_SHIFT CSI_SR_COF_INT_SHIFT |
#define | CSI_CSISR_COF_INT(x) CSI_SR_COF_INT(x) |
#define | CSI_CSISR_F1_INT_MASK CSI_SR_F1_INT_MASK |
#define | CSI_CSISR_F1_INT_SHIFT CSI_SR_F1_INT_SHIFT |
#define | CSI_CSISR_F1_INT(x) CSI_SR_F1_INT(x) |
#define | CSI_CSISR_F2_INT_MASK CSI_SR_F2_INT_MASK |
#define | CSI_CSISR_F2_INT_SHIFT CSI_SR_F2_INT_SHIFT |
#define | CSI_CSISR_F2_INT(x) CSI_SR_F2_INT(x) |
#define | CSI_CSISR_SOF_INT_MASK CSI_SR_SOF_INT_MASK |
#define | CSI_CSISR_SOF_INT_SHIFT CSI_SR_SOF_INT_SHIFT |
#define | CSI_CSISR_SOF_INT(x) CSI_SR_SOF_INT(x) |
#define | CSI_CSISR_EOF_INT_MASK CSI_SR_EOF_INT_MASK |
#define | CSI_CSISR_EOF_INT_SHIFT CSI_SR_EOF_INT_SHIFT |
#define | CSI_CSISR_EOF_INT(x) CSI_SR_EOF_INT(x) |
#define | CSI_CSISR_RxFF_INT_MASK CSI_SR_RxFF_INT_MASK |
#define | CSI_CSISR_RxFF_INT_SHIFT CSI_SR_RxFF_INT_SHIFT |
#define | CSI_CSISR_RxFF_INT(x) CSI_SR_RxFF_INT(x) |
#define | CSI_CSISR_DMA_TSF_DONE_FB1_MASK CSI_SR_DMA_TSF_DONE_FB1_MASK |
#define | CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT CSI_SR_DMA_TSF_DONE_FB1_SHIFT |
#define | CSI_CSISR_DMA_TSF_DONE_FB1(x) CSI_SR_DMA_TSF_DONE_FB1(x) |
#define | CSI_CSISR_DMA_TSF_DONE_FB2_MASK CSI_SR_DMA_TSF_DONE_FB2_MASK |
#define | CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT CSI_SR_DMA_TSF_DONE_FB2_SHIFT |
#define | CSI_CSISR_DMA_TSF_DONE_FB2(x) CSI_SR_DMA_TSF_DONE_FB2(x) |
#define | CSI_CSISR_STATFF_INT_MASK CSI_SR_STATFF_INT_MASK |
#define | CSI_CSISR_STATFF_INT_SHIFT CSI_SR_STATFF_INT_SHIFT |
#define | CSI_CSISR_STATFF_INT(x) CSI_SR_STATFF_INT(x) |
#define | CSI_CSISR_DMA_TSF_DONE_SFF_MASK CSI_SR_DMA_TSF_DONE_SFF_MASK |
#define | CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT CSI_SR_DMA_TSF_DONE_SFF_SHIFT |
#define | CSI_CSISR_DMA_TSF_DONE_SFF(x) CSI_SR_DMA_TSF_DONE_SFF(x) |
#define | CSI_CSISR_RF_OR_INT_MASK CSI_SR_RF_OR_INT_MASK |
#define | CSI_CSISR_RF_OR_INT_SHIFT CSI_SR_RF_OR_INT_SHIFT |
#define | CSI_CSISR_RF_OR_INT(x) CSI_SR_RF_OR_INT(x) |
#define | CSI_CSISR_SF_OR_INT_MASK CSI_SR_SF_OR_INT_MASK |
#define | CSI_CSISR_SF_OR_INT_SHIFT CSI_SR_SF_OR_INT_SHIFT |
#define | CSI_CSISR_SF_OR_INT(x) CSI_SR_SF_OR_INT(x) |
#define | CSI_CSISR_DMA_FIELD1_DONE_MASK CSI_SR_DMA_FIELD1_DONE_MASK |
#define | CSI_CSISR_DMA_FIELD1_DONE_SHIFT CSI_SR_DMA_FIELD1_DONE_SHIFT |
#define | CSI_CSISR_DMA_FIELD1_DONE(x) CSI_SR_DMA_FIELD1_DONE(x) |
#define | CSI_CSISR_DMA_FIELD0_DONE_MASK CSI_SR_DMA_FIELD0_DONE_MASK |
#define | CSI_CSISR_DMA_FIELD0_DONE_SHIFT CSI_SR_DMA_FIELD0_DONE_SHIFT |
#define | CSI_CSISR_DMA_FIELD0_DONE(x) CSI_SR_DMA_FIELD0_DONE(x) |
#define | CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK CSI_SR_BASEADDR_CHHANGE_ERROR_MASK |
#define | CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT |
#define | CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) CSI_SR_BASEADDR_CHHANGE_ERROR(x) |
#define | CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK |
#define | CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT |
#define | CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) |
#define | CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK |
#define | CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT |
#define | CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) |
#define | CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK |
#define | CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT |
#define | CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) CSI_DMASA_FB1_DMA_START_ADDR_FB1(x) |
#define | CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK |
#define | CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT |
#define | CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) CSI_DMASA_FB2_DMA_START_ADDR_FB2(x) |
#define | CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK CSI_FBUF_PARA_FBUF_STRIDE_MASK |
#define | CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT CSI_FBUF_PARA_FBUF_STRIDE_SHIFT |
#define | CSI_CSIFBUF_PARA_FBUF_STRIDE(x) CSI_FBUF_PARA_FBUF_STRIDE(x) |
#define | CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK |
#define | CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT |
#define | CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) CSI_FBUF_PARA_DEINTERLACE_STRIDE(x) |
#define | CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK CSI_IMAG_PARA_IMAGE_HEIGHT_MASK |
#define | CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT |
#define | CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) CSI_IMAG_PARA_IMAGE_HEIGHT(x) |
#define | CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK CSI_IMAG_PARA_IMAGE_WIDTH_MASK |
#define | CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT |
#define | CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) CSI_IMAG_PARA_IMAGE_WIDTH(x) |
#define | CSI_CSICR18_NTSC_EN_MASK CSI_CR18_NTSC_EN_MASK |
#define | CSI_CSICR18_NTSC_EN_SHIFT CSI_CR18_NTSC_EN_SHIFT |
#define | CSI_CSICR18_NTSC_EN(x) CSI_CR18_NTSC_EN(x) |
#define | CSI_CSICR18_TVDECODER_IN_EN_MASK CSI_CR18_TVDECODER_IN_EN_MASK |
#define | CSI_CSICR18_TVDECODER_IN_EN_SHIFT CSI_CR18_TVDECODER_IN_EN_SHIFT |
#define | CSI_CSICR18_TVDECODER_IN_EN(x) CSI_CR18_TVDECODER_IN_EN(x) |
#define | CSI_CSICR18_DEINTERLACE_EN_MASK CSI_CR18_DEINTERLACE_EN_MASK |
#define | CSI_CSICR18_DEINTERLACE_EN_SHIFT CSI_CR18_DEINTERLACE_EN_SHIFT |
#define | CSI_CSICR18_DEINTERLACE_EN(x) CSI_CR18_DEINTERLACE_EN(x) |
#define | CSI_CSICR18_PARALLEL24_EN_MASK CSI_CR18_PARALLEL24_EN_MASK |
#define | CSI_CSICR18_PARALLEL24_EN_SHIFT CSI_CR18_PARALLEL24_EN_SHIFT |
#define | CSI_CSICR18_PARALLEL24_EN(x) CSI_CR18_PARALLEL24_EN(x) |
#define | CSI_CSICR18_BASEADDR_SWITCH_EN_MASK CSI_CR18_BASEADDR_SWITCH_EN_MASK |
#define | CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT CSI_CR18_BASEADDR_SWITCH_EN_SHIFT |
#define | CSI_CSICR18_BASEADDR_SWITCH_EN(x) CSI_CR18_BASEADDR_SWITCH_EN(x) |
#define | CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK CSI_CR18_BASEADDR_SWITCH_SEL_MASK |
#define | CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT |
#define | CSI_CSICR18_BASEADDR_SWITCH_SEL(x) CSI_CR18_BASEADDR_SWITCH_SEL(x) |
#define | CSI_CSICR18_FIELD0_DONE_IE_MASK CSI_CR18_FIELD0_DONE_IE_MASK |
#define | CSI_CSICR18_FIELD0_DONE_IE_SHIFT CSI_CR18_FIELD0_DONE_IE_SHIFT |
#define | CSI_CSICR18_FIELD0_DONE_IE(x) CSI_CR18_FIELD0_DONE_IE(x) |
#define | CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK CSI_CR18_DMA_FIELD1_DONE_IE_MASK |
#define | CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT |
#define | CSI_CSICR18_DMA_FIELD1_DONE_IE(x) CSI_CR18_DMA_FIELD1_DONE_IE(x) |
#define | CSI_CSICR18_LAST_DMA_REQ_SEL_MASK CSI_CR18_LAST_DMA_REQ_SEL_MASK |
#define | CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT CSI_CR18_LAST_DMA_REQ_SEL_SHIFT |
#define | CSI_CSICR18_LAST_DMA_REQ_SEL(x) CSI_CR18_LAST_DMA_REQ_SEL(x) |
#define | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK |
#define | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT |
#define | CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x) |
#define | CSI_CSICR18_RGB888A_FORMAT_SEL_MASK CSI_CR18_RGB888A_FORMAT_SEL_MASK |
#define | CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT CSI_CR18_RGB888A_FORMAT_SEL_SHIFT |
#define | CSI_CSICR18_RGB888A_FORMAT_SEL(x) CSI_CR18_RGB888A_FORMAT_SEL(x) |
#define | CSI_CSICR18_AHB_HPROT_MASK CSI_CR18_AHB_HPROT_MASK |
#define | CSI_CSICR18_AHB_HPROT_SHIFT CSI_CR18_AHB_HPROT_SHIFT |
#define | CSI_CSICR18_AHB_HPROT(x) CSI_CR18_AHB_HPROT(x) |
#define | CSI_CSICR18_MASK_OPTION_MASK CSI_CR18_MASK_OPTION_MASK |
#define | CSI_CSICR18_MASK_OPTION_SHIFT CSI_CR18_MASK_OPTION_SHIFT |
#define | CSI_CSICR18_MASK_OPTION(x) CSI_CR18_MASK_OPTION(x) |
#define | CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK CSI_CR18_MIPI_DOUBLE_CMPNT_MASK |
#define | CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT |
#define | CSI_CSICR18_MIPI_DOUBLE_CMPNT(x) CSI_CR18_MIPI_DOUBLE_CMPNT(x) |
#define | CSI_CSICR18_MIPI_YU_SWAP_MASK CSI_CR18_MIPI_YU_SWAP_MASK |
#define | CSI_CSICR18_MIPI_YU_SWAP_SHIFT CSI_CR18_MIPI_YU_SWAP_SHIFT |
#define | CSI_CSICR18_MIPI_YU_SWAP(x) CSI_CR18_MIPI_YU_SWAP(x) |
#define | CSI_CSICR18_DATA_FROM_MIPI_MASK CSI_CR18_DATA_FROM_MIPI_MASK |
#define | CSI_CSICR18_DATA_FROM_MIPI_SHIFT CSI_CR18_DATA_FROM_MIPI_SHIFT |
#define | CSI_CSICR18_DATA_FROM_MIPI(x) CSI_CR18_DATA_FROM_MIPI(x) |
#define | CSI_CSICR18_LINE_STRIDE_EN_MASK CSI_CR18_LINE_STRIDE_EN_MASK |
#define | CSI_CSICR18_LINE_STRIDE_EN_SHIFT CSI_CR18_LINE_STRIDE_EN_SHIFT |
#define | CSI_CSICR18_LINE_STRIDE_EN(x) CSI_CR18_LINE_STRIDE_EN(x) |
#define | CSI_CSICR18_MIPI_DATA_FORMAT_MASK CSI_CR18_MIPI_DATA_FORMAT_MASK |
#define | CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT CSI_CR18_MIPI_DATA_FORMAT_SHIFT |
#define | CSI_CSICR18_MIPI_DATA_FORMAT(x) CSI_CR18_MIPI_DATA_FORMAT(x) |
#define | CSI_CSICR18_CSI_ENABLE_MASK CSI_CR18_CSI_ENABLE_MASK |
#define | CSI_CSICR18_CSI_ENABLE_SHIFT CSI_CR18_CSI_ENABLE_SHIFT |
#define | CSI_CSICR18_CSI_ENABLE(x) CSI_CR18_CSI_ENABLE(x) |
#define | CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK |
#define | CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT |
#define | CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) |
#define | CSI_CSICR20_THRESHOLD_MASK CSI_CR20_THRESHOLD_MASK |
#define | CSI_CSICR20_THRESHOLD_SHIFT CSI_CR20_THRESHOLD_SHIFT |
#define | CSI_CSICR20_THRESHOLD(x) CSI_CR20_THRESHOLD(x) |
#define | CSI_CSICR20_BINARY_EN_MASK CSI_CR20_BINARY_EN_MASK |
#define | CSI_CSICR20_BINARY_EN_SHIFT CSI_CR20_BINARY_EN_SHIFT |
#define | CSI_CSICR20_BINARY_EN(x) CSI_CR20_BINARY_EN(x) |
#define | CSI_CSICR20_QR_DATA_FORMAT_MASK CSI_CR20_QR_DATA_FORMAT_MASK |
#define | CSI_CSICR20_QR_DATA_FORMAT_SHIFT CSI_CR20_QR_DATA_FORMAT_SHIFT |
#define | CSI_CSICR20_QR_DATA_FORMAT(x) CSI_CR20_QR_DATA_FORMAT(x) |
#define | CSI_CSICR20_BIG_END_MASK CSI_CR20_BIG_END_MASK |
#define | CSI_CSICR20_BIG_END_SHIFT CSI_CR20_BIG_END_SHIFT |
#define | CSI_CSICR20_BIG_END(x) CSI_CR20_BIG_END(x) |
#define | CSI_CSICR20_10BIT_NEW_EN_MASK CSI_CR20_10BIT_NEW_EN_MASK |
#define | CSI_CSICR20_10BIT_NEW_EN_SHIFT CSI_CR20_10BIT_NEW_EN_SHIFT |
#define | CSI_CSICR20_10BIT_NEW_EN(x) CSI_CR20_10BIT_NEW_EN(x) |
#define | CSI_CSICR20_HISTOGRAM_EN_MASK CSI_CR20_HISTOGRAM_EN_MASK |
#define | CSI_CSICR20_HISTOGRAM_EN_SHIFT CSI_CR20_HISTOGRAM_EN_SHIFT |
#define | CSI_CSICR20_HISTOGRAM_EN(x) CSI_CR20_HISTOGRAM_EN(x) |
#define | CSI_CSICR20_QRCODE_EN_MASK CSI_CR20_QRCODE_EN_MASK |
#define | CSI_CSICR20_QRCODE_EN_SHIFT CSI_CR20_QRCODE_EN_SHIFT |
#define | CSI_CSICR20_QRCODE_EN(x) CSI_CR20_QRCODE_EN(x) |
#define | CSI_CSICR21_PIXEL_COUNTERS_MASK CSI_CR21_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR21_PIXEL_COUNTERS_SHIFT CSI_CR21_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR21_PIXEL_COUNTERS(x) CSI_CR21_PIXEL_COUNTERS(x) |
#define | CSI_CSICR22_PIXEL_COUNTERS_MASK CSI_CR22_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR22_PIXEL_COUNTERS_SHIFT CSI_CR22_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR22_PIXEL_COUNTERS(x) CSI_CR22_PIXEL_COUNTERS(x) |
#define | CSI_CSICR23_PIXEL_COUNTERS_MASK CSI_CR23_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR23_PIXEL_COUNTERS_SHIFT CSI_CR23_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR23_PIXEL_COUNTERS(x) CSI_CR23_PIXEL_COUNTERS(x) |
#define | CSI_CSICR24_PIXEL_COUNTERS_MASK CSI_CR24_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR24_PIXEL_COUNTERS_SHIFT CSI_CR24_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR24_PIXEL_COUNTERS(x) CSI_CR24_PIXEL_COUNTERS(x) |
#define | CSI_CSICR25_PIXEL_COUNTERS_MASK CSI_CR25_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR25_PIXEL_COUNTERS_SHIFT CSI_CR25_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR25_PIXEL_COUNTERS(x) CSI_CR25_PIXEL_COUNTERS(x) |
#define | CSI_CSICR26_PIXEL_COUNTERS_MASK CSI_CR26_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR26_PIXEL_COUNTERS_SHIFT CSI_CR26_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR26_PIXEL_COUNTERS(x) CSI_CR26_PIXEL_COUNTERS(x) |
#define | CSI_CSICR27_PIXEL_COUNTERS_MASK CSI_CR27_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR27_PIXEL_COUNTERS_SHIFT CSI_CR27_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR27_PIXEL_COUNTERS(x) CSI_CR27_PIXEL_COUNTERS(x) |
#define | CSI_CSICR28_PIXEL_COUNTERS_MASK CSI_CR28_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR28_PIXEL_COUNTERS_SHIFT CSI_CR28_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR28_PIXEL_COUNTERS(x) CSI_CR28_PIXEL_COUNTERS(x) |
#define | CSI_CSICR29_PIXEL_COUNTERS_MASK CSI_CR29_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR29_PIXEL_COUNTERS_SHIFT CSI_CR29_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR29_PIXEL_COUNTERS(x) CSI_CR29_PIXEL_COUNTERS(x) |
#define | CSI_CSICR30_PIXEL_COUNTERS_MASK CSI_CR30_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR30_PIXEL_COUNTERS_SHIFT CSI_CR30_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR30_PIXEL_COUNTERS(x) CSI_CR30_PIXEL_COUNTERS(x) |
#define | CSI_CSICR31_PIXEL_COUNTERS_MASK CSI_CR31_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR31_PIXEL_COUNTERS_SHIFT CSI_CR31_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR31_PIXEL_COUNTERS(x) CSI_CR31_PIXEL_COUNTERS(x) |
#define | CSI_CSICR32_PIXEL_COUNTERS_MASK CSI_CR32_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR32_PIXEL_COUNTERS_SHIFT CSI_CR32_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR32_PIXEL_COUNTERS(x) CSI_CR32_PIXEL_COUNTERS(x) |
#define | CSI_CSICR33_PIXEL_COUNTERS_MASK CSI_CR33_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR33_PIXEL_COUNTERS_SHIFT CSI_CR33_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR33_PIXEL_COUNTERS(x) CSI_CR33_PIXEL_COUNTERS(x) |
#define | CSI_CSICR34_PIXEL_COUNTERS_MASK CSI_CR34_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR34_PIXEL_COUNTERS_SHIFT CSI_CR34_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR34_PIXEL_COUNTERS(x) CSI_CR34_PIXEL_COUNTERS(x) |
#define | CSI_CSICR35_PIXEL_COUNTERS_MASK CSI_CR35_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR35_PIXEL_COUNTERS_SHIFT CSI_CR35_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR35_PIXEL_COUNTERS(x) CSI_CR35_PIXEL_COUNTERS(x) |
#define | CSI_CSICR36_PIXEL_COUNTERS_MASK CSI_CR36_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR36_PIXEL_COUNTERS_SHIFT CSI_CR36_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR36_PIXEL_COUNTERS(x) CSI_CR36_PIXEL_COUNTERS(x) |
#define | CSI_CSICR37_PIXEL_COUNTERS_MASK CSI_CR37_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR37_PIXEL_COUNTERS_SHIFT CSI_CR37_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR37_PIXEL_COUNTERS(x) CSI_CR37_PIXEL_COUNTERS(x) |
#define | CSI_CSICR38_PIXEL_COUNTERS_MASK CSI_CR38_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR38_PIXEL_COUNTERS_SHIFT CSI_CR38_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR38_PIXEL_COUNTERS(x) CSI_CR38_PIXEL_COUNTERS(x) |
#define | CSI_CSICR39_PIXEL_COUNTERS_MASK CSI_CR39_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR39_PIXEL_COUNTERS_SHIFT CSI_CR39_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR39_PIXEL_COUNTERS(x) CSI_CR39_PIXEL_COUNTERS(x) |
#define | CSI_CSICR40_PIXEL_COUNTERS_MASK CSI_CR40_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR40_PIXEL_COUNTERS_SHIFT CSI_CR40_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR40_PIXEL_COUNTERS(x) CSI_CR40_PIXEL_COUNTERS(x) |
#define | CSI_CSICR41_PIXEL_COUNTERS_MASK CSI_CR41_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR41_PIXEL_COUNTERS_SHIFT CSI_CR41_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR41_PIXEL_COUNTERS(x) CSI_CR41_PIXEL_COUNTERS(x) |
#define | CSI_CSICR42_PIXEL_COUNTERS_MASK CSI_CR42_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR42_PIXEL_COUNTERS_SHIFT CSI_CR42_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR42_PIXEL_COUNTERS(x) CSI_CR42_PIXEL_COUNTERS(x) |
#define | CSI_CSICR43_PIXEL_COUNTERS_MASK CSI_CR43_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR43_PIXEL_COUNTERS_SHIFT CSI_CR43_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR43_PIXEL_COUNTERS(x) CSI_CR43_PIXEL_COUNTERS(x) |
#define | CSI_CSICR44_PIXEL_COUNTERS_MASK CSI_CR44_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR44_PIXEL_COUNTERS_SHIFT CSI_CR44_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR44_PIXEL_COUNTERS(x) CSI_CR44_PIXEL_COUNTERS(x) |
#define | CSI_CSICR45_PIXEL_COUNTERS_MASK CSI_CR45_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR45_PIXEL_COUNTERS_SHIFT CSI_CR45_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR45_PIXEL_COUNTERS(x) CSI_CR45_PIXEL_COUNTERS(x) |
#define | CSI_CSICR46_PIXEL_COUNTERS_MASK CSI_CR46_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR46_PIXEL_COUNTERS_SHIFT CSI_CR46_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR46_PIXEL_COUNTERS(x) CSI_CR46_PIXEL_COUNTERS(x) |
#define | CSI_CSICR47_PIXEL_COUNTERS_MASK CSI_CR47_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR47_PIXEL_COUNTERS_SHIFT CSI_CR47_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR47_PIXEL_COUNTERS(x) CSI_CR47_PIXEL_COUNTERS(x) |
#define | CSI_CSICR48_PIXEL_COUNTERS_MASK CSI_CR48_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR48_PIXEL_COUNTERS_SHIFT CSI_CR48_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR48_PIXEL_COUNTERS(x) CSI_CR48_PIXEL_COUNTERS(x) |
#define | CSI_CSICR49_PIXEL_COUNTERS_MASK CSI_CR49_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR49_PIXEL_COUNTERS_SHIFT CSI_CR49_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR49_PIXEL_COUNTERS(x) CSI_CR49_PIXEL_COUNTERS(x) |
#define | CSI_CSICR50_PIXEL_COUNTERS_MASK CSI_CR50_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR50_PIXEL_COUNTERS_SHIFT CSI_CR50_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR50_PIXEL_COUNTERS(x) CSI_CR50_PIXEL_COUNTERS(x) |
#define | CSI_CSICR51_PIXEL_COUNTERS_MASK CSI_CR51_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR51_PIXEL_COUNTERS_SHIFT CSI_CR51_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR51_PIXEL_COUNTERS(x) CSI_CR51_PIXEL_COUNTERS(x) |
#define | CSI_CSICR52_PIXEL_COUNTERS_MASK CSI_CR52_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR52_PIXEL_COUNTERS_SHIFT CSI_CR52_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR52_PIXEL_COUNTERS(x) CSI_CR52_PIXEL_COUNTERS(x) |
#define | CSI_CSICR53_PIXEL_COUNTERS_MASK CSI_CR53_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR53_PIXEL_COUNTERS_SHIFT CSI_CR53_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR53_PIXEL_COUNTERS(x) CSI_CR53_PIXEL_COUNTERS(x) |
#define | CSI_CSICR54_PIXEL_COUNTERS_MASK CSI_CR54_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR54_PIXEL_COUNTERS_SHIFT CSI_CR54_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR54_PIXEL_COUNTERS(x) CSI_CR54_PIXEL_COUNTERS(x) |
#define | CSI_CSICR55_PIXEL_COUNTERS_MASK CSI_CR55_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR55_PIXEL_COUNTERS_SHIFT CSI_CR55_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR55_PIXEL_COUNTERS(x) CSI_CR55_PIXEL_COUNTERS(x) |
#define | CSI_CSICR56_PIXEL_COUNTERS_MASK CSI_CR56_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR56_PIXEL_COUNTERS_SHIFT CSI_CR56_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR56_PIXEL_COUNTERS(x) CSI_CR56_PIXEL_COUNTERS(x) |
#define | CSI_CSICR57_PIXEL_COUNTERS_MASK CSI_CR57_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR57_PIXEL_COUNTERS_SHIFT CSI_CR57_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR57_PIXEL_COUNTERS(x) CSI_CR57_PIXEL_COUNTERS(x) |
#define | CSI_CSICR58_PIXEL_COUNTERS_MASK CSI_CR58_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR58_PIXEL_COUNTERS_SHIFT CSI_CR58_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR58_PIXEL_COUNTERS(x) CSI_CR58_PIXEL_COUNTERS(x) |
#define | CSI_CSICR59_PIXEL_COUNTERS_MASK CSI_CR59_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR59_PIXEL_COUNTERS_SHIFT CSI_CR59_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR59_PIXEL_COUNTERS(x) CSI_CR59_PIXEL_COUNTERS(x) |
#define | CSI_CSICR60_PIXEL_COUNTERS_MASK CSI_CR60_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR60_PIXEL_COUNTERS_SHIFT CSI_CR60_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR60_PIXEL_COUNTERS(x) CSI_CR60_PIXEL_COUNTERS(x) |
#define | CSI_CSICR61_PIXEL_COUNTERS_MASK CSI_CR61_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR61_PIXEL_COUNTERS_SHIFT CSI_CR61_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR61_PIXEL_COUNTERS(x) CSI_CR61_PIXEL_COUNTERS(x) |
#define | CSI_CSICR62_PIXEL_COUNTERS_MASK CSI_CR62_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR62_PIXEL_COUNTERS_SHIFT CSI_CR62_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR62_PIXEL_COUNTERS(x) CSI_CR62_PIXEL_COUNTERS(x) |
#define | CSI_CSICR63_PIXEL_COUNTERS_MASK CSI_CR63_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR63_PIXEL_COUNTERS_SHIFT CSI_CR63_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR63_PIXEL_COUNTERS(x) CSI_CR63_PIXEL_COUNTERS(x) |
#define | CSI_CSICR64_PIXEL_COUNTERS_MASK CSI_CR64_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR64_PIXEL_COUNTERS_SHIFT CSI_CR64_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR64_PIXEL_COUNTERS(x) CSI_CR64_PIXEL_COUNTERS(x) |
#define | CSI_CSICR65_PIXEL_COUNTERS_MASK CSI_CR65_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR65_PIXEL_COUNTERS_SHIFT CSI_CR65_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR65_PIXEL_COUNTERS(x) CSI_CR65_PIXEL_COUNTERS(x) |
#define | CSI_CSICR66_PIXEL_COUNTERS_MASK CSI_CR66_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR66_PIXEL_COUNTERS_SHIFT CSI_CR66_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR66_PIXEL_COUNTERS(x) CSI_CR66_PIXEL_COUNTERS(x) |
#define | CSI_CSICR67_PIXEL_COUNTERS_MASK CSI_CR67_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR67_PIXEL_COUNTERS_SHIFT CSI_CR67_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR67_PIXEL_COUNTERS(x) CSI_CR67_PIXEL_COUNTERS(x) |
#define | CSI_CSICR68_PIXEL_COUNTERS_MASK CSI_CR68_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR68_PIXEL_COUNTERS_SHIFT CSI_CR68_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR68_PIXEL_COUNTERS(x) CSI_CR68_PIXEL_COUNTERS(x) |
#define | CSI_CSICR69_PIXEL_COUNTERS_MASK CSI_CR69_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR69_PIXEL_COUNTERS_SHIFT CSI_CR69_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR69_PIXEL_COUNTERS(x) CSI_CR69_PIXEL_COUNTERS(x) |
#define | CSI_CSICR70_PIXEL_COUNTERS_MASK CSI_CR70_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR70_PIXEL_COUNTERS_SHIFT CSI_CR70_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR70_PIXEL_COUNTERS(x) CSI_CR70_PIXEL_COUNTERS(x) |
#define | CSI_CSICR71_PIXEL_COUNTERS_MASK CSI_CR71_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR71_PIXEL_COUNTERS_SHIFT CSI_CR71_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR71_PIXEL_COUNTERS(x) CSI_CR71_PIXEL_COUNTERS(x) |
#define | CSI_CSICR72_PIXEL_COUNTERS_MASK CSI_CR72_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR72_PIXEL_COUNTERS_SHIFT CSI_CR72_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR72_PIXEL_COUNTERS(x) CSI_CR72_PIXEL_COUNTERS(x) |
#define | CSI_CSICR73_PIXEL_COUNTERS_MASK CSI_CR73_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR73_PIXEL_COUNTERS_SHIFT CSI_CR73_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR73_PIXEL_COUNTERS(x) CSI_CR73_PIXEL_COUNTERS(x) |
#define | CSI_CSICR74_PIXEL_COUNTERS_MASK CSI_CR74_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR74_PIXEL_COUNTERS_SHIFT CSI_CR74_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR74_PIXEL_COUNTERS(x) CSI_CR74_PIXEL_COUNTERS(x) |
#define | CSI_CSICR75_PIXEL_COUNTERS_MASK CSI_CR75_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR75_PIXEL_COUNTERS_SHIFT CSI_CR75_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR75_PIXEL_COUNTERS(x) CSI_CR75_PIXEL_COUNTERS(x) |
#define | CSI_CSICR76_PIXEL_COUNTERS_MASK CSI_CR76_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR76_PIXEL_COUNTERS_SHIFT CSI_CR76_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR76_PIXEL_COUNTERS(x) CSI_CR76_PIXEL_COUNTERS(x) |
#define | CSI_CSICR77_PIXEL_COUNTERS_MASK CSI_CR77_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR77_PIXEL_COUNTERS_SHIFT CSI_CR77_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR77_PIXEL_COUNTERS(x) CSI_CR77_PIXEL_COUNTERS(x) |
#define | CSI_CSICR78_PIXEL_COUNTERS_MASK CSI_CR78_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR78_PIXEL_COUNTERS_SHIFT CSI_CR78_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR78_PIXEL_COUNTERS(x) CSI_CR78_PIXEL_COUNTERS(x) |
#define | CSI_CSICR79_PIXEL_COUNTERS_MASK CSI_CR79_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR79_PIXEL_COUNTERS_SHIFT CSI_CR79_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR79_PIXEL_COUNTERS(x) CSI_CR79_PIXEL_COUNTERS(x) |
#define | CSI_CSICR80_PIXEL_COUNTERS_MASK CSI_CR80_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR80_PIXEL_COUNTERS_SHIFT CSI_CR80_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR80_PIXEL_COUNTERS(x) CSI_CR80_PIXEL_COUNTERS(x) |
#define | CSI_CSICR81_PIXEL_COUNTERS_MASK CSI_CR81_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR81_PIXEL_COUNTERS_SHIFT CSI_CR81_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR81_PIXEL_COUNTERS(x) CSI_CR81_PIXEL_COUNTERS(x) |
#define | CSI_CSICR82_PIXEL_COUNTERS_MASK CSI_CR82_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR82_PIXEL_COUNTERS_SHIFT CSI_CR82_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR82_PIXEL_COUNTERS(x) CSI_CR82_PIXEL_COUNTERS(x) |
#define | CSI_CSICR83_PIXEL_COUNTERS_MASK CSI_CR83_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR83_PIXEL_COUNTERS_SHIFT CSI_CR83_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR83_PIXEL_COUNTERS(x) CSI_CR83_PIXEL_COUNTERS(x) |
#define | CSI_CSICR84_PIXEL_COUNTERS_MASK CSI_CR84_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR84_PIXEL_COUNTERS_SHIFT CSI_CR84_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR84_PIXEL_COUNTERS(x) CSI_CR84_PIXEL_COUNTERS(x) |
#define | CSI_CSICR85_PIXEL_COUNTERS_MASK CSI_CR85_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR85_PIXEL_COUNTERS_SHIFT CSI_CR85_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR85_PIXEL_COUNTERS(x) CSI_CR85_PIXEL_COUNTERS(x) |
#define | CSI_CSICR86_PIXEL_COUNTERS_MASK CSI_CR86_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR86_PIXEL_COUNTERS_SHIFT CSI_CR86_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR86_PIXEL_COUNTERS(x) CSI_CR86_PIXEL_COUNTERS(x) |
#define | CSI_CSICR87_PIXEL_COUNTERS_MASK CSI_CR87_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR87_PIXEL_COUNTERS_SHIFT CSI_CR87_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR87_PIXEL_COUNTERS(x) CSI_CR87_PIXEL_COUNTERS(x) |
#define | CSI_CSICR88_PIXEL_COUNTERS_MASK CSI_CR88_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR88_PIXEL_COUNTERS_SHIFT CSI_CR88_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR88_PIXEL_COUNTERS(x) CSI_CR88_PIXEL_COUNTERS(x) |
#define | CSI_CSICR89_PIXEL_COUNTERS_MASK CSI_CR89_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR89_PIXEL_COUNTERS_SHIFT CSI_CR89_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR89_PIXEL_COUNTERS(x) CSI_CR89_PIXEL_COUNTERS(x) |
#define | CSI_CSICR90_PIXEL_COUNTERS_MASK CSI_CR90_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR90_PIXEL_COUNTERS_SHIFT CSI_CR90_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR90_PIXEL_COUNTERS(x) CSI_CR90_PIXEL_COUNTERS(x) |
#define | CSI_CSICR91_PIXEL_COUNTERS_MASK CSI_CR91_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR91_PIXEL_COUNTERS_SHIFT CSI_CR91_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR91_PIXEL_COUNTERS(x) CSI_CR91_PIXEL_COUNTERS(x) |
#define | CSI_CSICR92_PIXEL_COUNTERS_MASK CSI_CR92_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR92_PIXEL_COUNTERS_SHIFT CSI_CR92_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR92_PIXEL_COUNTERS(x) CSI_CR92_PIXEL_COUNTERS(x) |
#define | CSI_CSICR93_PIXEL_COUNTERS_MASK CSI_CR93_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR93_PIXEL_COUNTERS_SHIFT CSI_CR93_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR93_PIXEL_COUNTERS(x) CSI_CR93_PIXEL_COUNTERS(x) |
#define | CSI_CSICR94_PIXEL_COUNTERS_MASK CSI_CR94_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR94_PIXEL_COUNTERS_SHIFT CSI_CR94_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR94_PIXEL_COUNTERS(x) CSI_CR94_PIXEL_COUNTERS(x) |
#define | CSI_CSICR95_PIXEL_COUNTERS_MASK CSI_CR95_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR95_PIXEL_COUNTERS_SHIFT CSI_CR95_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR95_PIXEL_COUNTERS(x) CSI_CR95_PIXEL_COUNTERS(x) |
#define | CSI_CSICR96_PIXEL_COUNTERS_MASK CSI_CR96_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR96_PIXEL_COUNTERS_SHIFT CSI_CR96_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR96_PIXEL_COUNTERS(x) CSI_CR96_PIXEL_COUNTERS(x) |
#define | CSI_CSICR97_PIXEL_COUNTERS_MASK CSI_CR97_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR97_PIXEL_COUNTERS_SHIFT CSI_CR97_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR97_PIXEL_COUNTERS(x) CSI_CR97_PIXEL_COUNTERS(x) |
#define | CSI_CSICR98_PIXEL_COUNTERS_MASK CSI_CR98_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR98_PIXEL_COUNTERS_SHIFT CSI_CR98_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR98_PIXEL_COUNTERS(x) CSI_CR98_PIXEL_COUNTERS(x) |
#define | CSI_CSICR99_PIXEL_COUNTERS_MASK CSI_CR99_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR99_PIXEL_COUNTERS_SHIFT CSI_CR99_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR99_PIXEL_COUNTERS(x) CSI_CR99_PIXEL_COUNTERS(x) |
#define | CSI_CSICR100_PIXEL_COUNTERS_MASK CSI_CR100_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR100_PIXEL_COUNTERS_SHIFT CSI_CR100_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR100_PIXEL_COUNTERS(x) CSI_CR100_PIXEL_COUNTERS(x) |
#define | CSI_CSICR101_PIXEL_COUNTERS_MASK CSI_CR101_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR101_PIXEL_COUNTERS_SHIFT CSI_CR101_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR101_PIXEL_COUNTERS(x) CSI_CR101_PIXEL_COUNTERS(x) |
#define | CSI_CSICR102_PIXEL_COUNTERS_MASK CSI_CR102_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR102_PIXEL_COUNTERS_SHIFT CSI_CR102_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR102_PIXEL_COUNTERS(x) CSI_CR102_PIXEL_COUNTERS(x) |
#define | CSI_CSICR103_PIXEL_COUNTERS_MASK CSI_CR103_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR103_PIXEL_COUNTERS_SHIFT CSI_CR103_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR103_PIXEL_COUNTERS(x) CSI_CR103_PIXEL_COUNTERS(x) |
#define | CSI_CSICR104_PIXEL_COUNTERS_MASK CSI_CR104_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR104_PIXEL_COUNTERS_SHIFT CSI_CR104_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR104_PIXEL_COUNTERS(x) CSI_CR104_PIXEL_COUNTERS(x) |
#define | CSI_CSICR105_PIXEL_COUNTERS_MASK CSI_CR105_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR105_PIXEL_COUNTERS_SHIFT CSI_CR105_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR105_PIXEL_COUNTERS(x) CSI_CR105_PIXEL_COUNTERS(x) |
#define | CSI_CSICR106_PIXEL_COUNTERS_MASK CSI_CR106_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR106_PIXEL_COUNTERS_SHIFT CSI_CR106_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR106_PIXEL_COUNTERS(x) CSI_CR106_PIXEL_COUNTERS(x) |
#define | CSI_CSICR107_PIXEL_COUNTERS_MASK CSI_CR107_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR107_PIXEL_COUNTERS_SHIFT CSI_CR107_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR107_PIXEL_COUNTERS(x) CSI_CR107_PIXEL_COUNTERS(x) |
#define | CSI_CSICR108_PIXEL_COUNTERS_MASK CSI_CR108_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR108_PIXEL_COUNTERS_SHIFT CSI_CR108_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR108_PIXEL_COUNTERS(x) CSI_CR108_PIXEL_COUNTERS(x) |
#define | CSI_CSICR109_PIXEL_COUNTERS_MASK CSI_CR109_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR109_PIXEL_COUNTERS_SHIFT CSI_CR109_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR109_PIXEL_COUNTERS(x) CSI_CR109_PIXEL_COUNTERS(x) |
#define | CSI_CSICR110_PIXEL_COUNTERS_MASK CSI_CR110_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR110_PIXEL_COUNTERS_SHIFT CSI_CR110_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR110_PIXEL_COUNTERS(x) CSI_CR110_PIXEL_COUNTERS(x) |
#define | CSI_CSICR111_PIXEL_COUNTERS_MASK CSI_CR111_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR111_PIXEL_COUNTERS_SHIFT CSI_CR111_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR111_PIXEL_COUNTERS(x) CSI_CR111_PIXEL_COUNTERS(x) |
#define | CSI_CSICR112_PIXEL_COUNTERS_MASK CSI_CR112_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR112_PIXEL_COUNTERS_SHIFT CSI_CR112_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR112_PIXEL_COUNTERS(x) CSI_CR112_PIXEL_COUNTERS(x) |
#define | CSI_CSICR113_PIXEL_COUNTERS_MASK CSI_CR113_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR113_PIXEL_COUNTERS_SHIFT CSI_CR113_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR113_PIXEL_COUNTERS(x) CSI_CR113_PIXEL_COUNTERS(x) |
#define | CSI_CSICR114_PIXEL_COUNTERS_MASK CSI_CR114_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR114_PIXEL_COUNTERS_SHIFT CSI_CR114_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR114_PIXEL_COUNTERS(x) CSI_CR114_PIXEL_COUNTERS(x) |
#define | CSI_CSICR115_PIXEL_COUNTERS_MASK CSI_CR115_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR115_PIXEL_COUNTERS_SHIFT CSI_CR115_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR115_PIXEL_COUNTERS(x) CSI_CR115_PIXEL_COUNTERS(x) |
#define | CSI_CSICR116_PIXEL_COUNTERS_MASK CSI_CR116_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR116_PIXEL_COUNTERS_SHIFT CSI_CR116_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR116_PIXEL_COUNTERS(x) CSI_CR116_PIXEL_COUNTERS(x) |
#define | CSI_CSICR117_PIXEL_COUNTERS_MASK CSI_CR117_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR117_PIXEL_COUNTERS_SHIFT CSI_CR117_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR117_PIXEL_COUNTERS(x) CSI_CR117_PIXEL_COUNTERS(x) |
#define | CSI_CSICR118_PIXEL_COUNTERS_MASK CSI_CR118_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR118_PIXEL_COUNTERS_SHIFT CSI_CR118_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR118_PIXEL_COUNTERS(x) CSI_CR118_PIXEL_COUNTERS(x) |
#define | CSI_CSICR119_PIXEL_COUNTERS_MASK CSI_CR119_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR119_PIXEL_COUNTERS_SHIFT CSI_CR119_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR119_PIXEL_COUNTERS(x) CSI_CR119_PIXEL_COUNTERS(x) |
#define | CSI_CSICR120_PIXEL_COUNTERS_MASK CSI_CR120_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR120_PIXEL_COUNTERS_SHIFT CSI_CR120_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR120_PIXEL_COUNTERS(x) CSI_CR120_PIXEL_COUNTERS(x) |
#define | CSI_CSICR121_PIXEL_COUNTERS_MASK CSI_CR121_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR121_PIXEL_COUNTERS_SHIFT CSI_CR121_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR121_PIXEL_COUNTERS(x) CSI_CR121_PIXEL_COUNTERS(x) |
#define | CSI_CSICR122_PIXEL_COUNTERS_MASK CSI_CR122_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR122_PIXEL_COUNTERS_SHIFT CSI_CR122_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR122_PIXEL_COUNTERS(x) CSI_CR122_PIXEL_COUNTERS(x) |
#define | CSI_CSICR123_PIXEL_COUNTERS_MASK CSI_CR123_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR123_PIXEL_COUNTERS_SHIFT CSI_CR123_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR123_PIXEL_COUNTERS(x) CSI_CR123_PIXEL_COUNTERS(x) |
#define | CSI_CSICR124_PIXEL_COUNTERS_MASK CSI_CR124_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR124_PIXEL_COUNTERS_SHIFT CSI_CR124_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR124_PIXEL_COUNTERS(x) CSI_CR124_PIXEL_COUNTERS(x) |
#define | CSI_CSICR125_PIXEL_COUNTERS_MASK CSI_CR125_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR125_PIXEL_COUNTERS_SHIFT CSI_CR125_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR125_PIXEL_COUNTERS(x) CSI_CR125_PIXEL_COUNTERS(x) |
#define | CSI_CSICR126_PIXEL_COUNTERS_MASK CSI_CR126_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR126_PIXEL_COUNTERS_SHIFT CSI_CR126_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR126_PIXEL_COUNTERS(x) CSI_CR126_PIXEL_COUNTERS(x) |
#define | CSI_CSICR127_PIXEL_COUNTERS_MASK CSI_CR127_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR127_PIXEL_COUNTERS_SHIFT CSI_CR127_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR127_PIXEL_COUNTERS(x) CSI_CR127_PIXEL_COUNTERS(x) |
#define | CSI_CSICR128_PIXEL_COUNTERS_MASK CSI_CR128_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR128_PIXEL_COUNTERS_SHIFT CSI_CR128_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR128_PIXEL_COUNTERS(x) CSI_CR128_PIXEL_COUNTERS(x) |
#define | CSI_CSICR129_PIXEL_COUNTERS_MASK CSI_CR129_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR129_PIXEL_COUNTERS_SHIFT CSI_CR129_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR129_PIXEL_COUNTERS(x) CSI_CR129_PIXEL_COUNTERS(x) |
#define | CSI_CSICR130_PIXEL_COUNTERS_MASK CSI_CR130_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR130_PIXEL_COUNTERS_SHIFT CSI_CR130_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR130_PIXEL_COUNTERS(x) CSI_CR130_PIXEL_COUNTERS(x) |
#define | CSI_CSICR131_PIXEL_COUNTERS_MASK CSI_CR131_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR131_PIXEL_COUNTERS_SHIFT CSI_CR131_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR131_PIXEL_COUNTERS(x) CSI_CR131_PIXEL_COUNTERS(x) |
#define | CSI_CSICR132_PIXEL_COUNTERS_MASK CSI_CR132_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR132_PIXEL_COUNTERS_SHIFT CSI_CR132_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR132_PIXEL_COUNTERS(x) CSI_CR132_PIXEL_COUNTERS(x) |
#define | CSI_CSICR133_PIXEL_COUNTERS_MASK CSI_CR133_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR133_PIXEL_COUNTERS_SHIFT CSI_CR133_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR133_PIXEL_COUNTERS(x) CSI_CR133_PIXEL_COUNTERS(x) |
#define | CSI_CSICR134_PIXEL_COUNTERS_MASK CSI_CR134_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR134_PIXEL_COUNTERS_SHIFT CSI_CR134_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR134_PIXEL_COUNTERS(x) CSI_CR134_PIXEL_COUNTERS(x) |
#define | CSI_CSICR135_PIXEL_COUNTERS_MASK CSI_CR135_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR135_PIXEL_COUNTERS_SHIFT CSI_CR135_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR135_PIXEL_COUNTERS(x) CSI_CR135_PIXEL_COUNTERS(x) |
#define | CSI_CSICR136_PIXEL_COUNTERS_MASK CSI_CR136_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR136_PIXEL_COUNTERS_SHIFT CSI_CR136_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR136_PIXEL_COUNTERS(x) CSI_CR136_PIXEL_COUNTERS(x) |
#define | CSI_CSICR137_PIXEL_COUNTERS_MASK CSI_CR137_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR137_PIXEL_COUNTERS_SHIFT CSI_CR137_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR137_PIXEL_COUNTERS(x) CSI_CR137_PIXEL_COUNTERS(x) |
#define | CSI_CSICR138_PIXEL_COUNTERS_MASK CSI_CR138_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR138_PIXEL_COUNTERS_SHIFT CSI_CR138_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR138_PIXEL_COUNTERS(x) CSI_CR138_PIXEL_COUNTERS(x) |
#define | CSI_CSICR139_PIXEL_COUNTERS_MASK CSI_CR139_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR139_PIXEL_COUNTERS_SHIFT CSI_CR139_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR139_PIXEL_COUNTERS(x) CSI_CR139_PIXEL_COUNTERS(x) |
#define | CSI_CSICR140_PIXEL_COUNTERS_MASK CSI_CR140_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR140_PIXEL_COUNTERS_SHIFT CSI_CR140_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR140_PIXEL_COUNTERS(x) CSI_CR140_PIXEL_COUNTERS(x) |
#define | CSI_CSICR141_PIXEL_COUNTERS_MASK CSI_CR141_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR141_PIXEL_COUNTERS_SHIFT CSI_CR141_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR141_PIXEL_COUNTERS(x) CSI_CR141_PIXEL_COUNTERS(x) |
#define | CSI_CSICR142_PIXEL_COUNTERS_MASK CSI_CR142_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR142_PIXEL_COUNTERS_SHIFT CSI_CR142_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR142_PIXEL_COUNTERS(x) CSI_CR142_PIXEL_COUNTERS(x) |
#define | CSI_CSICR143_PIXEL_COUNTERS_MASK CSI_CR143_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR143_PIXEL_COUNTERS_SHIFT CSI_CR143_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR143_PIXEL_COUNTERS(x) CSI_CR143_PIXEL_COUNTERS(x) |
#define | CSI_CSICR144_PIXEL_COUNTERS_MASK CSI_CR144_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR144_PIXEL_COUNTERS_SHIFT CSI_CR144_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR144_PIXEL_COUNTERS(x) CSI_CR144_PIXEL_COUNTERS(x) |
#define | CSI_CSICR145_PIXEL_COUNTERS_MASK CSI_CR145_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR145_PIXEL_COUNTERS_SHIFT CSI_CR145_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR145_PIXEL_COUNTERS(x) CSI_CR145_PIXEL_COUNTERS(x) |
#define | CSI_CSICR146_PIXEL_COUNTERS_MASK CSI_CR146_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR146_PIXEL_COUNTERS_SHIFT CSI_CR146_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR146_PIXEL_COUNTERS(x) CSI_CR146_PIXEL_COUNTERS(x) |
#define | CSI_CSICR147_PIXEL_COUNTERS_MASK CSI_CR147_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR147_PIXEL_COUNTERS_SHIFT CSI_CR147_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR147_PIXEL_COUNTERS(x) CSI_CR147_PIXEL_COUNTERS(x) |
#define | CSI_CSICR148_PIXEL_COUNTERS_MASK CSI_CR148_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR148_PIXEL_COUNTERS_SHIFT CSI_CR148_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR148_PIXEL_COUNTERS(x) CSI_CR148_PIXEL_COUNTERS(x) |
#define | CSI_CSICR149_PIXEL_COUNTERS_MASK CSI_CR149_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR149_PIXEL_COUNTERS_SHIFT CSI_CR149_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR149_PIXEL_COUNTERS(x) CSI_CR149_PIXEL_COUNTERS(x) |
#define | CSI_CSICR150_PIXEL_COUNTERS_MASK CSI_CR150_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR150_PIXEL_COUNTERS_SHIFT CSI_CR150_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR150_PIXEL_COUNTERS(x) CSI_CR150_PIXEL_COUNTERS(x) |
#define | CSI_CSICR151_PIXEL_COUNTERS_MASK CSI_CR151_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR151_PIXEL_COUNTERS_SHIFT CSI_CR151_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR151_PIXEL_COUNTERS(x) CSI_CR151_PIXEL_COUNTERS(x) |
#define | CSI_CSICR152_PIXEL_COUNTERS_MASK CSI_CR152_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR152_PIXEL_COUNTERS_SHIFT CSI_CR152_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR152_PIXEL_COUNTERS(x) CSI_CR152_PIXEL_COUNTERS(x) |
#define | CSI_CSICR153_PIXEL_COUNTERS_MASK CSI_CR153_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR153_PIXEL_COUNTERS_SHIFT CSI_CR153_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR153_PIXEL_COUNTERS(x) CSI_CR153_PIXEL_COUNTERS(x) |
#define | CSI_CSICR154_PIXEL_COUNTERS_MASK CSI_CR154_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR154_PIXEL_COUNTERS_SHIFT CSI_CR154_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR154_PIXEL_COUNTERS(x) CSI_CR154_PIXEL_COUNTERS(x) |
#define | CSI_CSICR155_PIXEL_COUNTERS_MASK CSI_CR155_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR155_PIXEL_COUNTERS_SHIFT CSI_CR155_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR155_PIXEL_COUNTERS(x) CSI_CR155_PIXEL_COUNTERS(x) |
#define | CSI_CSICR156_PIXEL_COUNTERS_MASK CSI_CR156_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR156_PIXEL_COUNTERS_SHIFT CSI_CR156_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR156_PIXEL_COUNTERS(x) CSI_CR156_PIXEL_COUNTERS(x) |
#define | CSI_CSICR157_PIXEL_COUNTERS_MASK CSI_CR157_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR157_PIXEL_COUNTERS_SHIFT CSI_CR157_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR157_PIXEL_COUNTERS(x) CSI_CR157_PIXEL_COUNTERS(x) |
#define | CSI_CSICR158_PIXEL_COUNTERS_MASK CSI_CR158_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR158_PIXEL_COUNTERS_SHIFT CSI_CR158_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR158_PIXEL_COUNTERS(x) CSI_CR158_PIXEL_COUNTERS(x) |
#define | CSI_CSICR159_PIXEL_COUNTERS_MASK CSI_CR159_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR159_PIXEL_COUNTERS_SHIFT CSI_CR159_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR159_PIXEL_COUNTERS(x) CSI_CR159_PIXEL_COUNTERS(x) |
#define | CSI_CSICR160_PIXEL_COUNTERS_MASK CSI_CR160_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR160_PIXEL_COUNTERS_SHIFT CSI_CR160_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR160_PIXEL_COUNTERS(x) CSI_CR160_PIXEL_COUNTERS(x) |
#define | CSI_CSICR161_PIXEL_COUNTERS_MASK CSI_CR161_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR161_PIXEL_COUNTERS_SHIFT CSI_CR161_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR161_PIXEL_COUNTERS(x) CSI_CR161_PIXEL_COUNTERS(x) |
#define | CSI_CSICR162_PIXEL_COUNTERS_MASK CSI_CR162_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR162_PIXEL_COUNTERS_SHIFT CSI_CR162_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR162_PIXEL_COUNTERS(x) CSI_CR162_PIXEL_COUNTERS(x) |
#define | CSI_CSICR163_PIXEL_COUNTERS_MASK CSI_CR163_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR163_PIXEL_COUNTERS_SHIFT CSI_CR163_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR163_PIXEL_COUNTERS(x) CSI_CR163_PIXEL_COUNTERS(x) |
#define | CSI_CSICR164_PIXEL_COUNTERS_MASK CSI_CR164_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR164_PIXEL_COUNTERS_SHIFT CSI_CR164_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR164_PIXEL_COUNTERS(x) CSI_CR164_PIXEL_COUNTERS(x) |
#define | CSI_CSICR165_PIXEL_COUNTERS_MASK CSI_CR165_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR165_PIXEL_COUNTERS_SHIFT CSI_CR165_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR165_PIXEL_COUNTERS(x) CSI_CR165_PIXEL_COUNTERS(x) |
#define | CSI_CSICR166_PIXEL_COUNTERS_MASK CSI_CR166_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR166_PIXEL_COUNTERS_SHIFT CSI_CR166_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR166_PIXEL_COUNTERS(x) CSI_CR166_PIXEL_COUNTERS(x) |
#define | CSI_CSICR167_PIXEL_COUNTERS_MASK CSI_CR167_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR167_PIXEL_COUNTERS_SHIFT CSI_CR167_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR167_PIXEL_COUNTERS(x) CSI_CR167_PIXEL_COUNTERS(x) |
#define | CSI_CSICR168_PIXEL_COUNTERS_MASK CSI_CR168_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR168_PIXEL_COUNTERS_SHIFT CSI_CR168_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR168_PIXEL_COUNTERS(x) CSI_CR168_PIXEL_COUNTERS(x) |
#define | CSI_CSICR169_PIXEL_COUNTERS_MASK CSI_CR169_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR169_PIXEL_COUNTERS_SHIFT CSI_CR169_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR169_PIXEL_COUNTERS(x) CSI_CR169_PIXEL_COUNTERS(x) |
#define | CSI_CSICR170_PIXEL_COUNTERS_MASK CSI_CR170_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR170_PIXEL_COUNTERS_SHIFT CSI_CR170_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR170_PIXEL_COUNTERS(x) CSI_CR170_PIXEL_COUNTERS(x) |
#define | CSI_CSICR171_PIXEL_COUNTERS_MASK CSI_CR171_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR171_PIXEL_COUNTERS_SHIFT CSI_CR171_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR171_PIXEL_COUNTERS(x) CSI_CR171_PIXEL_COUNTERS(x) |
#define | CSI_CSICR172_PIXEL_COUNTERS_MASK CSI_CR172_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR172_PIXEL_COUNTERS_SHIFT CSI_CR172_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR172_PIXEL_COUNTERS(x) CSI_CR172_PIXEL_COUNTERS(x) |
#define | CSI_CSICR173_PIXEL_COUNTERS_MASK CSI_CR173_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR173_PIXEL_COUNTERS_SHIFT CSI_CR173_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR173_PIXEL_COUNTERS(x) CSI_CR173_PIXEL_COUNTERS(x) |
#define | CSI_CSICR174_PIXEL_COUNTERS_MASK CSI_CR174_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR174_PIXEL_COUNTERS_SHIFT CSI_CR174_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR174_PIXEL_COUNTERS(x) CSI_CR174_PIXEL_COUNTERS(x) |
#define | CSI_CSICR175_PIXEL_COUNTERS_MASK CSI_CR175_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR175_PIXEL_COUNTERS_SHIFT CSI_CR175_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR175_PIXEL_COUNTERS(x) CSI_CR175_PIXEL_COUNTERS(x) |
#define | CSI_CSICR176_PIXEL_COUNTERS_MASK CSI_CR176_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR176_PIXEL_COUNTERS_SHIFT CSI_CR176_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR176_PIXEL_COUNTERS(x) CSI_CR176_PIXEL_COUNTERS(x) |
#define | CSI_CSICR177_PIXEL_COUNTERS_MASK CSI_CR177_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR177_PIXEL_COUNTERS_SHIFT CSI_CR177_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR177_PIXEL_COUNTERS(x) CSI_CR177_PIXEL_COUNTERS(x) |
#define | CSI_CSICR178_PIXEL_COUNTERS_MASK CSI_CR178_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR178_PIXEL_COUNTERS_SHIFT CSI_CR178_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR178_PIXEL_COUNTERS(x) CSI_CR178_PIXEL_COUNTERS(x) |
#define | CSI_CSICR179_PIXEL_COUNTERS_MASK CSI_CR179_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR179_PIXEL_COUNTERS_SHIFT CSI_CR179_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR179_PIXEL_COUNTERS(x) CSI_CR179_PIXEL_COUNTERS(x) |
#define | CSI_CSICR180_PIXEL_COUNTERS_MASK CSI_CR180_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR180_PIXEL_COUNTERS_SHIFT CSI_CR180_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR180_PIXEL_COUNTERS(x) CSI_CR180_PIXEL_COUNTERS(x) |
#define | CSI_CSICR181_PIXEL_COUNTERS_MASK CSI_CR181_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR181_PIXEL_COUNTERS_SHIFT CSI_CR181_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR181_PIXEL_COUNTERS(x) CSI_CR181_PIXEL_COUNTERS(x) |
#define | CSI_CSICR182_PIXEL_COUNTERS_MASK CSI_CR182_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR182_PIXEL_COUNTERS_SHIFT CSI_CR182_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR182_PIXEL_COUNTERS(x) CSI_CR182_PIXEL_COUNTERS(x) |
#define | CSI_CSICR183_PIXEL_COUNTERS_MASK CSI_CR183_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR183_PIXEL_COUNTERS_SHIFT CSI_CR183_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR183_PIXEL_COUNTERS(x) CSI_CR183_PIXEL_COUNTERS(x) |
#define | CSI_CSICR184_PIXEL_COUNTERS_MASK CSI_CR184_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR184_PIXEL_COUNTERS_SHIFT CSI_CR184_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR184_PIXEL_COUNTERS(x) CSI_CR184_PIXEL_COUNTERS(x) |
#define | CSI_CSICR185_PIXEL_COUNTERS_MASK CSI_CR185_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR185_PIXEL_COUNTERS_SHIFT CSI_CR185_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR185_PIXEL_COUNTERS(x) CSI_CR185_PIXEL_COUNTERS(x) |
#define | CSI_CSICR186_PIXEL_COUNTERS_MASK CSI_CR186_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR186_PIXEL_COUNTERS_SHIFT CSI_CR186_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR186_PIXEL_COUNTERS(x) CSI_CR186_PIXEL_COUNTERS(x) |
#define | CSI_CSICR187_PIXEL_COUNTERS_MASK CSI_CR187_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR187_PIXEL_COUNTERS_SHIFT CSI_CR187_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR187_PIXEL_COUNTERS(x) CSI_CR187_PIXEL_COUNTERS(x) |
#define | CSI_CSICR188_PIXEL_COUNTERS_MASK CSI_CR188_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR188_PIXEL_COUNTERS_SHIFT CSI_CR188_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR188_PIXEL_COUNTERS(x) CSI_CR188_PIXEL_COUNTERS(x) |
#define | CSI_CSICR189_PIXEL_COUNTERS_MASK CSI_CR189_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR189_PIXEL_COUNTERS_SHIFT CSI_CR189_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR189_PIXEL_COUNTERS(x) CSI_CR189_PIXEL_COUNTERS(x) |
#define | CSI_CSICR190_PIXEL_COUNTERS_MASK CSI_CR190_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR190_PIXEL_COUNTERS_SHIFT CSI_CR190_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR190_PIXEL_COUNTERS(x) CSI_CR190_PIXEL_COUNTERS(x) |
#define | CSI_CSICR191_PIXEL_COUNTERS_MASK CSI_CR191_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR191_PIXEL_COUNTERS_SHIFT CSI_CR191_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR191_PIXEL_COUNTERS(x) CSI_CR191_PIXEL_COUNTERS(x) |
#define | CSI_CSICR192_PIXEL_COUNTERS_MASK CSI_CR192_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR192_PIXEL_COUNTERS_SHIFT CSI_CR192_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR192_PIXEL_COUNTERS(x) CSI_CR192_PIXEL_COUNTERS(x) |
#define | CSI_CSICR193_PIXEL_COUNTERS_MASK CSI_CR193_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR193_PIXEL_COUNTERS_SHIFT CSI_CR193_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR193_PIXEL_COUNTERS(x) CSI_CR193_PIXEL_COUNTERS(x) |
#define | CSI_CSICR194_PIXEL_COUNTERS_MASK CSI_CR194_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR194_PIXEL_COUNTERS_SHIFT CSI_CR194_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR194_PIXEL_COUNTERS(x) CSI_CR194_PIXEL_COUNTERS(x) |
#define | CSI_CSICR195_PIXEL_COUNTERS_MASK CSI_CR195_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR195_PIXEL_COUNTERS_SHIFT CSI_CR195_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR195_PIXEL_COUNTERS(x) CSI_CR195_PIXEL_COUNTERS(x) |
#define | CSI_CSICR196_PIXEL_COUNTERS_MASK CSI_CR196_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR196_PIXEL_COUNTERS_SHIFT CSI_CR196_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR196_PIXEL_COUNTERS(x) CSI_CR196_PIXEL_COUNTERS(x) |
#define | CSI_CSICR197_PIXEL_COUNTERS_MASK CSI_CR197_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR197_PIXEL_COUNTERS_SHIFT CSI_CR197_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR197_PIXEL_COUNTERS(x) CSI_CR197_PIXEL_COUNTERS(x) |
#define | CSI_CSICR198_PIXEL_COUNTERS_MASK CSI_CR198_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR198_PIXEL_COUNTERS_SHIFT CSI_CR198_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR198_PIXEL_COUNTERS(x) CSI_CR198_PIXEL_COUNTERS(x) |
#define | CSI_CSICR199_PIXEL_COUNTERS_MASK CSI_CR199_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR199_PIXEL_COUNTERS_SHIFT CSI_CR199_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR199_PIXEL_COUNTERS(x) CSI_CR199_PIXEL_COUNTERS(x) |
#define | CSI_CSICR200_PIXEL_COUNTERS_MASK CSI_CR200_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR200_PIXEL_COUNTERS_SHIFT CSI_CR200_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR200_PIXEL_COUNTERS(x) CSI_CR200_PIXEL_COUNTERS(x) |
#define | CSI_CSICR201_PIXEL_COUNTERS_MASK CSI_CR201_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR201_PIXEL_COUNTERS_SHIFT CSI_CR201_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR201_PIXEL_COUNTERS(x) CSI_CR201_PIXEL_COUNTERS(x) |
#define | CSI_CSICR202_PIXEL_COUNTERS_MASK CSI_CR202_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR202_PIXEL_COUNTERS_SHIFT CSI_CR202_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR202_PIXEL_COUNTERS(x) CSI_CR202_PIXEL_COUNTERS(x) |
#define | CSI_CSICR203_PIXEL_COUNTERS_MASK CSI_CR203_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR203_PIXEL_COUNTERS_SHIFT CSI_CR203_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR203_PIXEL_COUNTERS(x) CSI_CR203_PIXEL_COUNTERS(x) |
#define | CSI_CSICR204_PIXEL_COUNTERS_MASK CSI_CR204_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR204_PIXEL_COUNTERS_SHIFT CSI_CR204_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR204_PIXEL_COUNTERS(x) CSI_CR204_PIXEL_COUNTERS(x) |
#define | CSI_CSICR205_PIXEL_COUNTERS_MASK CSI_CR205_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR205_PIXEL_COUNTERS_SHIFT CSI_CR205_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR205_PIXEL_COUNTERS(x) CSI_CR205_PIXEL_COUNTERS(x) |
#define | CSI_CSICR206_PIXEL_COUNTERS_MASK CSI_CR206_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR206_PIXEL_COUNTERS_SHIFT CSI_CR206_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR206_PIXEL_COUNTERS(x) CSI_CR206_PIXEL_COUNTERS(x) |
#define | CSI_CSICR207_PIXEL_COUNTERS_MASK CSI_CR207_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR207_PIXEL_COUNTERS_SHIFT CSI_CR207_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR207_PIXEL_COUNTERS(x) CSI_CR207_PIXEL_COUNTERS(x) |
#define | CSI_CSICR208_PIXEL_COUNTERS_MASK CSI_CR208_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR208_PIXEL_COUNTERS_SHIFT CSI_CR208_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR208_PIXEL_COUNTERS(x) CSI_CR208_PIXEL_COUNTERS(x) |
#define | CSI_CSICR209_PIXEL_COUNTERS_MASK CSI_CR209_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR209_PIXEL_COUNTERS_SHIFT CSI_CR209_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR209_PIXEL_COUNTERS(x) CSI_CR209_PIXEL_COUNTERS(x) |
#define | CSI_CSICR210_PIXEL_COUNTERS_MASK CSI_CR210_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR210_PIXEL_COUNTERS_SHIFT CSI_CR210_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR210_PIXEL_COUNTERS(x) CSI_CR210_PIXEL_COUNTERS(x) |
#define | CSI_CSICR211_PIXEL_COUNTERS_MASK CSI_CR211_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR211_PIXEL_COUNTERS_SHIFT CSI_CR211_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR211_PIXEL_COUNTERS(x) CSI_CR211_PIXEL_COUNTERS(x) |
#define | CSI_CSICR212_PIXEL_COUNTERS_MASK CSI_CR212_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR212_PIXEL_COUNTERS_SHIFT CSI_CR212_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR212_PIXEL_COUNTERS(x) CSI_CR212_PIXEL_COUNTERS(x) |
#define | CSI_CSICR213_PIXEL_COUNTERS_MASK CSI_CR213_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR213_PIXEL_COUNTERS_SHIFT CSI_CR213_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR213_PIXEL_COUNTERS(x) CSI_CR213_PIXEL_COUNTERS(x) |
#define | CSI_CSICR214_PIXEL_COUNTERS_MASK CSI_CR214_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR214_PIXEL_COUNTERS_SHIFT CSI_CR214_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR214_PIXEL_COUNTERS(x) CSI_CR214_PIXEL_COUNTERS(x) |
#define | CSI_CSICR215_PIXEL_COUNTERS_MASK CSI_CR215_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR215_PIXEL_COUNTERS_SHIFT CSI_CR215_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR215_PIXEL_COUNTERS(x) CSI_CR215_PIXEL_COUNTERS(x) |
#define | CSI_CSICR216_PIXEL_COUNTERS_MASK CSI_CR216_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR216_PIXEL_COUNTERS_SHIFT CSI_CR216_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR216_PIXEL_COUNTERS(x) CSI_CR216_PIXEL_COUNTERS(x) |
#define | CSI_CSICR217_PIXEL_COUNTERS_MASK CSI_CR217_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR217_PIXEL_COUNTERS_SHIFT CSI_CR217_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR217_PIXEL_COUNTERS(x) CSI_CR217_PIXEL_COUNTERS(x) |
#define | CSI_CSICR218_PIXEL_COUNTERS_MASK CSI_CR218_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR218_PIXEL_COUNTERS_SHIFT CSI_CR218_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR218_PIXEL_COUNTERS(x) CSI_CR218_PIXEL_COUNTERS(x) |
#define | CSI_CSICR219_PIXEL_COUNTERS_MASK CSI_CR219_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR219_PIXEL_COUNTERS_SHIFT CSI_CR219_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR219_PIXEL_COUNTERS(x) CSI_CR219_PIXEL_COUNTERS(x) |
#define | CSI_CSICR220_PIXEL_COUNTERS_MASK CSI_CR220_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR220_PIXEL_COUNTERS_SHIFT CSI_CR220_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR220_PIXEL_COUNTERS(x) CSI_CR220_PIXEL_COUNTERS(x) |
#define | CSI_CSICR221_PIXEL_COUNTERS_MASK CSI_CR221_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR221_PIXEL_COUNTERS_SHIFT CSI_CR221_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR221_PIXEL_COUNTERS(x) CSI_CR221_PIXEL_COUNTERS(x) |
#define | CSI_CSICR222_PIXEL_COUNTERS_MASK CSI_CR222_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR222_PIXEL_COUNTERS_SHIFT CSI_CR222_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR222_PIXEL_COUNTERS(x) CSI_CR222_PIXEL_COUNTERS(x) |
#define | CSI_CSICR223_PIXEL_COUNTERS_MASK CSI_CR223_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR223_PIXEL_COUNTERS_SHIFT CSI_CR223_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR223_PIXEL_COUNTERS(x) CSI_CR223_PIXEL_COUNTERS(x) |
#define | CSI_CSICR224_PIXEL_COUNTERS_MASK CSI_CR224_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR224_PIXEL_COUNTERS_SHIFT CSI_CR224_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR224_PIXEL_COUNTERS(x) CSI_CR224_PIXEL_COUNTERS(x) |
#define | CSI_CSICR225_PIXEL_COUNTERS_MASK CSI_CR225_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR225_PIXEL_COUNTERS_SHIFT CSI_CR225_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR225_PIXEL_COUNTERS(x) CSI_CR225_PIXEL_COUNTERS(x) |
#define | CSI_CSICR226_PIXEL_COUNTERS_MASK CSI_CR226_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR226_PIXEL_COUNTERS_SHIFT CSI_CR226_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR226_PIXEL_COUNTERS(x) CSI_CR226_PIXEL_COUNTERS(x) |
#define | CSI_CSICR227_PIXEL_COUNTERS_MASK CSI_CR227_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR227_PIXEL_COUNTERS_SHIFT CSI_CR227_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR227_PIXEL_COUNTERS(x) CSI_CR227_PIXEL_COUNTERS(x) |
#define | CSI_CSICR228_PIXEL_COUNTERS_MASK CSI_CR228_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR228_PIXEL_COUNTERS_SHIFT CSI_CR228_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR228_PIXEL_COUNTERS(x) CSI_CR228_PIXEL_COUNTERS(x) |
#define | CSI_CSICR229_PIXEL_COUNTERS_MASK CSI_CR229_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR229_PIXEL_COUNTERS_SHIFT CSI_CR229_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR229_PIXEL_COUNTERS(x) CSI_CR229_PIXEL_COUNTERS(x) |
#define | CSI_CSICR230_PIXEL_COUNTERS_MASK CSI_CR230_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR230_PIXEL_COUNTERS_SHIFT CSI_CR230_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR230_PIXEL_COUNTERS(x) CSI_CR230_PIXEL_COUNTERS(x) |
#define | CSI_CSICR231_PIXEL_COUNTERS_MASK CSI_CR231_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR231_PIXEL_COUNTERS_SHIFT CSI_CR231_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR231_PIXEL_COUNTERS(x) CSI_CR231_PIXEL_COUNTERS(x) |
#define | CSI_CSICR232_PIXEL_COUNTERS_MASK CSI_CR232_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR232_PIXEL_COUNTERS_SHIFT CSI_CR232_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR232_PIXEL_COUNTERS(x) CSI_CR232_PIXEL_COUNTERS(x) |
#define | CSI_CSICR233_PIXEL_COUNTERS_MASK CSI_CR233_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR233_PIXEL_COUNTERS_SHIFT CSI_CR233_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR233_PIXEL_COUNTERS(x) CSI_CR233_PIXEL_COUNTERS(x) |
#define | CSI_CSICR234_PIXEL_COUNTERS_MASK CSI_CR234_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR234_PIXEL_COUNTERS_SHIFT CSI_CR234_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR234_PIXEL_COUNTERS(x) CSI_CR234_PIXEL_COUNTERS(x) |
#define | CSI_CSICR235_PIXEL_COUNTERS_MASK CSI_CR235_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR235_PIXEL_COUNTERS_SHIFT CSI_CR235_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR235_PIXEL_COUNTERS(x) CSI_CR235_PIXEL_COUNTERS(x) |
#define | CSI_CSICR236_PIXEL_COUNTERS_MASK CSI_CR236_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR236_PIXEL_COUNTERS_SHIFT CSI_CR236_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR236_PIXEL_COUNTERS(x) CSI_CR236_PIXEL_COUNTERS(x) |
#define | CSI_CSICR237_PIXEL_COUNTERS_MASK CSI_CR237_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR237_PIXEL_COUNTERS_SHIFT CSI_CR237_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR237_PIXEL_COUNTERS(x) CSI_CR237_PIXEL_COUNTERS(x) |
#define | CSI_CSICR238_PIXEL_COUNTERS_MASK CSI_CR238_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR238_PIXEL_COUNTERS_SHIFT CSI_CR238_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR238_PIXEL_COUNTERS(x) CSI_CR238_PIXEL_COUNTERS(x) |
#define | CSI_CSICR239_PIXEL_COUNTERS_MASK CSI_CR239_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR239_PIXEL_COUNTERS_SHIFT CSI_CR239_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR239_PIXEL_COUNTERS(x) CSI_CR239_PIXEL_COUNTERS(x) |
#define | CSI_CSICR240_PIXEL_COUNTERS_MASK CSI_CR240_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR240_PIXEL_COUNTERS_SHIFT CSI_CR240_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR240_PIXEL_COUNTERS(x) CSI_CR240_PIXEL_COUNTERS(x) |
#define | CSI_CSICR241_PIXEL_COUNTERS_MASK CSI_CR241_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR241_PIXEL_COUNTERS_SHIFT CSI_CR241_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR241_PIXEL_COUNTERS(x) CSI_CR241_PIXEL_COUNTERS(x) |
#define | CSI_CSICR242_PIXEL_COUNTERS_MASK CSI_CR242_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR242_PIXEL_COUNTERS_SHIFT CSI_CR242_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR242_PIXEL_COUNTERS(x) CSI_CR242_PIXEL_COUNTERS(x) |
#define | CSI_CSICR243_PIXEL_COUNTERS_MASK CSI_CR243_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR243_PIXEL_COUNTERS_SHIFT CSI_CR243_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR243_PIXEL_COUNTERS(x) CSI_CR243_PIXEL_COUNTERS(x) |
#define | CSI_CSICR244_PIXEL_COUNTERS_MASK CSI_CR244_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR244_PIXEL_COUNTERS_SHIFT CSI_CR244_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR244_PIXEL_COUNTERS(x) CSI_CR244_PIXEL_COUNTERS(x) |
#define | CSI_CSICR245_PIXEL_COUNTERS_MASK CSI_CR245_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR245_PIXEL_COUNTERS_SHIFT CSI_CR245_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR245_PIXEL_COUNTERS(x) CSI_CR245_PIXEL_COUNTERS(x) |
#define | CSI_CSICR246_PIXEL_COUNTERS_MASK CSI_CR246_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR246_PIXEL_COUNTERS_SHIFT CSI_CR246_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR246_PIXEL_COUNTERS(x) CSI_CR246_PIXEL_COUNTERS(x) |
#define | CSI_CSICR247_PIXEL_COUNTERS_MASK CSI_CR247_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR247_PIXEL_COUNTERS_SHIFT CSI_CR247_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR247_PIXEL_COUNTERS(x) CSI_CR247_PIXEL_COUNTERS(x) |
#define | CSI_CSICR248_PIXEL_COUNTERS_MASK CSI_CR248_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR248_PIXEL_COUNTERS_SHIFT CSI_CR248_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR248_PIXEL_COUNTERS(x) CSI_CR248_PIXEL_COUNTERS(x) |
#define | CSI_CSICR249_PIXEL_COUNTERS_MASK CSI_CR249_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR249_PIXEL_COUNTERS_SHIFT CSI_CR249_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR249_PIXEL_COUNTERS(x) CSI_CR249_PIXEL_COUNTERS(x) |
#define | CSI_CSICR250_PIXEL_COUNTERS_MASK CSI_CR250_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR250_PIXEL_COUNTERS_SHIFT CSI_CR250_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR250_PIXEL_COUNTERS(x) CSI_CR250_PIXEL_COUNTERS(x) |
#define | CSI_CSICR251_PIXEL_COUNTERS_MASK CSI_CR251_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR251_PIXEL_COUNTERS_SHIFT CSI_CR251_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR251_PIXEL_COUNTERS(x) CSI_CR251_PIXEL_COUNTERS(x) |
#define | CSI_CSICR252_PIXEL_COUNTERS_MASK CSI_CR252_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR252_PIXEL_COUNTERS_SHIFT CSI_CR252_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR252_PIXEL_COUNTERS(x) CSI_CR252_PIXEL_COUNTERS(x) |
#define | CSI_CSICR253_PIXEL_COUNTERS_MASK CSI_CR253_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR253_PIXEL_COUNTERS_SHIFT CSI_CR253_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR253_PIXEL_COUNTERS(x) CSI_CR253_PIXEL_COUNTERS(x) |
#define | CSI_CSICR254_PIXEL_COUNTERS_MASK CSI_CR254_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR254_PIXEL_COUNTERS_SHIFT CSI_CR254_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR254_PIXEL_COUNTERS(x) CSI_CR254_PIXEL_COUNTERS(x) |
#define | CSI_CSICR255_PIXEL_COUNTERS_MASK CSI_CR255_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR255_PIXEL_COUNTERS_SHIFT CSI_CR255_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR255_PIXEL_COUNTERS(x) CSI_CR255_PIXEL_COUNTERS(x) |
#define | CSI_CSICR256_PIXEL_COUNTERS_MASK CSI_CR256_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR256_PIXEL_COUNTERS_SHIFT CSI_CR256_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR256_PIXEL_COUNTERS(x) CSI_CR256_PIXEL_COUNTERS(x) |
#define | CSI_CSICR257_PIXEL_COUNTERS_MASK CSI_CR257_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR257_PIXEL_COUNTERS_SHIFT CSI_CR257_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR257_PIXEL_COUNTERS(x) CSI_CR257_PIXEL_COUNTERS(x) |
#define | CSI_CSICR258_PIXEL_COUNTERS_MASK CSI_CR258_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR258_PIXEL_COUNTERS_SHIFT CSI_CR258_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR258_PIXEL_COUNTERS(x) CSI_CR258_PIXEL_COUNTERS(x) |
#define | CSI_CSICR259_PIXEL_COUNTERS_MASK CSI_CR259_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR259_PIXEL_COUNTERS_SHIFT CSI_CR259_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR259_PIXEL_COUNTERS(x) CSI_CR259_PIXEL_COUNTERS(x) |
#define | CSI_CSICR260_PIXEL_COUNTERS_MASK CSI_CR260_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR260_PIXEL_COUNTERS_SHIFT CSI_CR260_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR260_PIXEL_COUNTERS(x) CSI_CR260_PIXEL_COUNTERS(x) |
#define | CSI_CSICR261_PIXEL_COUNTERS_MASK CSI_CR261_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR261_PIXEL_COUNTERS_SHIFT CSI_CR261_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR261_PIXEL_COUNTERS(x) CSI_CR261_PIXEL_COUNTERS(x) |
#define | CSI_CSICR262_PIXEL_COUNTERS_MASK CSI_CR262_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR262_PIXEL_COUNTERS_SHIFT CSI_CR262_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR262_PIXEL_COUNTERS(x) CSI_CR262_PIXEL_COUNTERS(x) |
#define | CSI_CSICR263_PIXEL_COUNTERS_MASK CSI_CR263_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR263_PIXEL_COUNTERS_SHIFT CSI_CR263_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR263_PIXEL_COUNTERS(x) CSI_CR263_PIXEL_COUNTERS(x) |
#define | CSI_CSICR264_PIXEL_COUNTERS_MASK CSI_CR264_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR264_PIXEL_COUNTERS_SHIFT CSI_CR264_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR264_PIXEL_COUNTERS(x) CSI_CR264_PIXEL_COUNTERS(x) |
#define | CSI_CSICR265_PIXEL_COUNTERS_MASK CSI_CR265_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR265_PIXEL_COUNTERS_SHIFT CSI_CR265_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR265_PIXEL_COUNTERS(x) CSI_CR265_PIXEL_COUNTERS(x) |
#define | CSI_CSICR266_PIXEL_COUNTERS_MASK CSI_CR266_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR266_PIXEL_COUNTERS_SHIFT CSI_CR266_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR266_PIXEL_COUNTERS(x) CSI_CR266_PIXEL_COUNTERS(x) |
#define | CSI_CSICR267_PIXEL_COUNTERS_MASK CSI_CR267_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR267_PIXEL_COUNTERS_SHIFT CSI_CR267_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR267_PIXEL_COUNTERS(x) CSI_CR267_PIXEL_COUNTERS(x) |
#define | CSI_CSICR268_PIXEL_COUNTERS_MASK CSI_CR268_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR268_PIXEL_COUNTERS_SHIFT CSI_CR268_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR268_PIXEL_COUNTERS(x) CSI_CR268_PIXEL_COUNTERS(x) |
#define | CSI_CSICR269_PIXEL_COUNTERS_MASK CSI_CR269_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR269_PIXEL_COUNTERS_SHIFT CSI_CR269_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR269_PIXEL_COUNTERS(x) CSI_CR269_PIXEL_COUNTERS(x) |
#define | CSI_CSICR270_PIXEL_COUNTERS_MASK CSI_CR270_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR270_PIXEL_COUNTERS_SHIFT CSI_CR270_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR270_PIXEL_COUNTERS(x) CSI_CR270_PIXEL_COUNTERS(x) |
#define | CSI_CSICR271_PIXEL_COUNTERS_MASK CSI_CR271_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR271_PIXEL_COUNTERS_SHIFT CSI_CR271_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR271_PIXEL_COUNTERS(x) CSI_CR271_PIXEL_COUNTERS(x) |
#define | CSI_CSICR272_PIXEL_COUNTERS_MASK CSI_CR272_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR272_PIXEL_COUNTERS_SHIFT CSI_CR272_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR272_PIXEL_COUNTERS(x) CSI_CR272_PIXEL_COUNTERS(x) |
#define | CSI_CSICR273_PIXEL_COUNTERS_MASK CSI_CR273_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR273_PIXEL_COUNTERS_SHIFT CSI_CR273_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR273_PIXEL_COUNTERS(x) CSI_CR273_PIXEL_COUNTERS(x) |
#define | CSI_CSICR274_PIXEL_COUNTERS_MASK CSI_CR274_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR274_PIXEL_COUNTERS_SHIFT CSI_CR274_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR274_PIXEL_COUNTERS(x) CSI_CR274_PIXEL_COUNTERS(x) |
#define | CSI_CSICR275_PIXEL_COUNTERS_MASK CSI_CR275_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR275_PIXEL_COUNTERS_SHIFT CSI_CR275_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR275_PIXEL_COUNTERS(x) CSI_CR275_PIXEL_COUNTERS(x) |
#define | CSI_CSICR276_PIXEL_COUNTERS_MASK CSI_CR276_PIXEL_COUNTERS_MASK |
#define | CSI_CSICR276_PIXEL_COUNTERS_SHIFT CSI_CR276_PIXEL_COUNTERS_SHIFT |
#define | CSI_CSICR276_PIXEL_COUNTERS(x) CSI_CR276_PIXEL_COUNTERS(x) |
#define | DAC_BASE (0x40064000u) |
#define | DAC ((DAC_Type *)DAC_BASE) |
#define | DAC_BASE_ADDRS { DAC_BASE } |
#define | DAC_BASE_PTRS { DAC } |
#define | DAC_IRQS { DAC_IRQn } |
#define | DCDC_BASE (0x40CA8000u) |
#define | DCDC ((DCDC_Type *)DCDC_BASE) |
#define | DCDC_BASE_ADDRS { DCDC_BASE } |
#define | DCDC_BASE_PTRS { DCDC } |
#define | DCIC_DCICRC_COUNT (16U) |
#define | DCIC_DCICRS_COUNT (16U) |
#define | DCIC_DCICRRS_COUNT (16U) |
#define | DCIC_DCICRCS_COUNT (16U) |
#define | DCIC1_BASE (0x40819000u) |
#define | DCIC1 ((DCIC_Type *)DCIC1_BASE) |
#define | DCIC2_BASE (0x4081A000u) |
#define | DCIC2 ((DCIC_Type *)DCIC2_BASE) |
#define | DCIC_BASE_ADDRS { 0u, DCIC1_BASE, DCIC2_BASE } |
#define | DCIC_BASE_PTRS { (DCIC_Type *)0u, DCIC1, DCIC2 } |
#define | DMA_SADDR_COUNT (32U) |
#define | DMA_SOFF_COUNT (32U) |
#define | DMA_ATTR_COUNT (32U) |
#define | DMA_NBYTES_MLNO_COUNT (32U) |
#define | DMA_NBYTES_MLOFFNO_COUNT (32U) |
#define | DMA_NBYTES_MLOFFYES_COUNT (32U) |
#define | DMA_SLAST_COUNT (32U) |
#define | DMA_DADDR_COUNT (32U) |
#define | DMA_DOFF_COUNT (32U) |
#define | DMA_CITER_ELINKNO_COUNT (32U) |
#define | DMA_CITER_ELINKYES_COUNT (32U) |
#define | DMA_DLAST_SGA_COUNT (32U) |
#define | DMA_CSR_COUNT (32U) |
#define | DMA_BITER_ELINKNO_COUNT (32U) |
#define | DMA_BITER_ELINKYES_COUNT (32U) |
#define | DMA1_BASE (0x40C14000u) |
#define | DMA1 ((DMA_Type *)DMA1_BASE) |
#define | DMA_BASE_ADDRS { 0u, DMA1_BASE } |
#define | DMA_BASE_PTRS { (DMA_Type *)0u, DMA1 } |
#define | DMA_CHN_IRQS |
#define | DMA_ERROR_IRQS { NotAvail_IRQn, DMA_ERROR_IRQn } |
#define | DMAMUX_CHCFG_COUNT (32U) |
#define | DMAMUX1_BASE (0x40C18000u) |
#define | DMAMUX1 ((DMAMUX_Type *)DMAMUX1_BASE) |
#define | DMAMUX_BASE_ADDRS { 0u, DMAMUX1_BASE } |
#define | DMAMUX_BASE_PTRS { (DMAMUX_Type *)0u, DMAMUX1 } |
#define | DSI_HOST_BASE (0x4080C000u) |
#define | DSI_HOST ((DSI_HOST_Type *)DSI_HOST_BASE) |
#define | DSI_HOST_BASE_ADDRS { DSI_HOST_BASE } |
#define | DSI_HOST_BASE_PTRS { DSI_HOST } |
#define | DSI_HOST_DSI_IRQS { MIPI_DSI_IRQn } |
#define | DSI_HOST_APB_PKT_IF_BASE (0x4080C280u) |
#define | DSI_HOST_APB_PKT_IF ((DSI_HOST_APB_PKT_IF_Type *)DSI_HOST_APB_PKT_IF_BASE) |
#define | DSI_HOST_APB_PKT_IF_BASE_ADDRS { DSI_HOST_APB_PKT_IF_BASE } |
#define | DSI_HOST_APB_PKT_IF_BASE_PTRS { DSI_HOST_APB_PKT_IF } |
#define | DSI_HOST_DPI_INTFC_BASE (0x4080C200u) |
#define | DSI_HOST_DPI_INTFC ((DSI_HOST_DPI_INTFC_Type *)DSI_HOST_DPI_INTFC_BASE) |
#define | DSI_HOST_DPI_INTFC_BASE_ADDRS { DSI_HOST_DPI_INTFC_BASE } |
#define | DSI_HOST_DPI_INTFC_BASE_PTRS { DSI_HOST_DPI_INTFC } |
#define | DSI_HOST_DPHY_INTFC_BASE (0x4080C300u) |
#define | DSI_HOST_DPHY_INTFC ((DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *)DSI_HOST_DPHY_INTFC_BASE) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_ADDRS { DSI_HOST_DPHY_INTFC_BASE } |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_PTRS { DSI_HOST_DPHY_INTFC } |
#define | EMVSIM1_BASE (0x40154000u) |
#define | EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) |
#define | EMVSIM2_BASE (0x40158000u) |
#define | EMVSIM2 ((EMVSIM_Type *)EMVSIM2_BASE) |
#define | EMVSIM_BASE_ADDRS { 0u, EMVSIM1_BASE, EMVSIM2_BASE } |
#define | EMVSIM_BASE_PTRS { (EMVSIM_Type *)0u, EMVSIM1, EMVSIM2 } |
#define | EMVSIM_IRQS { NotAvail_IRQn, EMVSIM1_IRQn, EMVSIM2_IRQn } |
#define | ENC1_BASE (0x40174000u) |
#define | ENC1 ((ENC_Type *)ENC1_BASE) |
#define | ENC2_BASE (0x40178000u) |
#define | ENC2 ((ENC_Type *)ENC2_BASE) |
#define | ENC3_BASE (0x4017C000u) |
#define | ENC3 ((ENC_Type *)ENC3_BASE) |
#define | ENC4_BASE (0x40180000u) |
#define | ENC4 ((ENC_Type *)ENC4_BASE) |
#define | ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE } |
#define | ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 } |
#define | ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } |
#define | ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } |
#define | ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } |
#define | ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } |
#define | ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } |
#define | ENET_TXIC_COUNT (3U) |
#define | ENET_RXIC_COUNT (3U) |
#define | ENET_RCMR_COUNT (2U) |
#define | ENET_DMACFG_COUNT (2U) |
#define | ENET_TCSR_COUNT (4U) |
#define | ENET_TCCR_COUNT (4U) |
#define | ENET_BASE (0x40424000u) |
#define | ENET ((ENET_Type *)ENET_BASE) |
#define | ENET_1G_BASE (0x40420000u) |
#define | ENET_1G ((ENET_Type *)ENET_1G_BASE) |
#define | ENET_BASE_ADDRS { ENET_BASE, ENET_1G_BASE } |
#define | ENET_BASE_PTRS { ENET, ENET_1G } |
#define | ENET_Transmit_IRQS { ENET_IRQn, ENET_1G_IRQn } |
#define | ENET_Receive_IRQS { ENET_IRQn, ENET_1G_IRQn } |
#define | ENET_Error_IRQS { ENET_IRQn, ENET_1G_IRQn } |
#define | ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, ENET_1G_1588_Timer_IRQn } |
#define | ENET_Ts_IRQS { ENET_IRQn, ENET_1G_IRQn } |
#define | ENET_BUFF_ALIGNMENT (64U) |
#define | ETHERNET_PLL_BASE (0u) |
#define | ETHERNET_PLL ((ETHERNET_PLL_Type *)ETHERNET_PLL_BASE) |
#define | ETHERNET_PLL_BASE_ADDRS { ETHERNET_PLL_BASE } |
#define | ETHERNET_PLL_BASE_PTRS { ETHERNET_PLL } |
#define | EWM_BASE (0x4002C000u) |
#define | EWM ((EWM_Type *)EWM_BASE) |
#define | EWM_BASE_ADDRS { EWM_BASE } |
#define | EWM_BASE_PTRS { EWM } |
#define | EWM_IRQS { EWM_IRQn } |
#define | FLEXIO_SHIFTCTL_COUNT (8U) |
#define | FLEXIO_SHIFTCFG_COUNT (8U) |
#define | FLEXIO_SHIFTBUF_COUNT (8U) |
#define | FLEXIO_SHIFTBUFBIS_COUNT (8U) |
#define | FLEXIO_SHIFTBUFBYS_COUNT (8U) |
#define | FLEXIO_SHIFTBUFBBS_COUNT (8U) |
#define | FLEXIO_TIMCTL_COUNT (8U) |
#define | FLEXIO_TIMCFG_COUNT (8U) |
#define | FLEXIO_TIMCMP_COUNT (8U) |
#define | FLEXIO_SHIFTBUFNBS_COUNT (8U) |
#define | FLEXIO_SHIFTBUFHWS_COUNT (8U) |
#define | FLEXIO_SHIFTBUFNIS_COUNT (8U) |
#define | FLEXIO_SHIFTBUFOES_COUNT (8U) |
#define | FLEXIO_SHIFTBUFEOS_COUNT (8U) |
#define | FLEXIO1_BASE (0x400AC000u) |
#define | FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE) |
#define | FLEXIO2_BASE (0x400B0000u) |
#define | FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE) |
#define | FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE } |
#define | FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 } |
#define | FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn } |
#define | FLEXRAM_BASE (0x40028000u) |
#define | FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE) |
#define | FLEXRAM_BASE_ADDRS { FLEXRAM_BASE } |
#define | FLEXRAM_BASE_PTRS { FLEXRAM } |
#define | FLEXRAM_ECC_IRQS { FLEXRAM_ECC_IRQn } |
#define | FLEXSPI_AHBRXBUFCR0_COUNT (8U) |
#define | FLEXSPI_FLSHCR0_COUNT (4U) |
#define | FLEXSPI_FLSHCR1_COUNT (4U) |
#define | FLEXSPI_FLSHCR2_COUNT (4U) |
#define | FLEXSPI_DLLCR_COUNT (2U) |
#define | FLEXSPI_RFDR_COUNT (32U) |
#define | FLEXSPI_TFDR_COUNT (32U) |
#define | FLEXSPI_LUT_COUNT (64U) |
#define | FLEXSPI_HMSTRCR_COUNT (8U) |
#define | FLEXSPI1_BASE (0x400CC000u) |
#define | FLEXSPI1 ((FLEXSPI_Type *)FLEXSPI1_BASE) |
#define | FLEXSPI2_BASE (0x400D0000u) |
#define | FLEXSPI2 ((FLEXSPI_Type *)FLEXSPI2_BASE) |
#define | FLEXSPI_BASE_ADDRS { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE } |
#define | FLEXSPI_BASE_PTRS { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 } |
#define | FLEXSPI_IRQS { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn } |
#define | FlexSPI1_AMBA_BASE (0x30000000U) |
#define | FlexSPI1_ASFM_BASE (0x30000000U) |
#define | FlexSPI1_ARDF_BASE (0x2FC00000U) |
#define | FlexSPI1_ATDF_BASE (0x2F800000U) |
#define | FlexSPI1_ALIAS_BASE (0x8000000U) |
#define | FlexSPI2_AMBA_BASE (0x60000000U) |
#define | FlexSPI2_ASFM_BASE (0x60000000U) |
#define | FlexSPI2_ARDF_BASE (0x7FC00000U) |
#define | FlexSPI2_ATDF_BASE (0x7F800000U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_COUNT (8U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_COUNT (8U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_COUNT (16U) |
#define | GPC_CPU_MODE_CTRL_0_BASE (0x40C00000u) |
#define | GPC_CPU_MODE_CTRL_0 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_0_BASE) |
#define | GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) |
#define | GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE) |
#define | GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE } |
#define | GPC_CPU_MODE_CTRL_BASE_PTRS { GPC_CPU_MODE_CTRL_0, GPC_CPU_MODE_CTRL_1 } |
#define | GPC_SET_POINT_CTRL_BASE (0x40C02000u) |
#define | GPC_SET_POINT_CTRL ((GPC_SET_POINT_CTRL_Type *)GPC_SET_POINT_CTRL_BASE) |
#define | GPC_SET_POINT_CTRL_BASE_ADDRS { GPC_SET_POINT_CTRL_BASE } |
#define | GPC_SET_POINT_CTRL_BASE_PTRS { GPC_SET_POINT_CTRL } |
#define | GPC_STBY_CTRL_BASE (0x40C02800u) |
#define | GPC_STBY_CTRL ((GPC_STBY_CTRL_Type *)GPC_STBY_CTRL_BASE) |
#define | GPC_STBY_CTRL_BASE_ADDRS { GPC_STBY_CTRL_BASE } |
#define | GPC_STBY_CTRL_BASE_PTRS { GPC_STBY_CTRL } |
#define | GPIO1_BASE (0x4012C000u) |
#define | GPIO1 ((GPIO_Type *)GPIO1_BASE) |
#define | GPIO2_BASE (0x40130000u) |
#define | GPIO2 ((GPIO_Type *)GPIO2_BASE) |
#define | GPIO3_BASE (0x40134000u) |
#define | GPIO3 ((GPIO_Type *)GPIO3_BASE) |
#define | GPIO4_BASE (0x40138000u) |
#define | GPIO4 ((GPIO_Type *)GPIO4_BASE) |
#define | GPIO5_BASE (0x4013C000u) |
#define | GPIO5 ((GPIO_Type *)GPIO5_BASE) |
#define | GPIO6_BASE (0x40140000u) |
#define | GPIO6 ((GPIO_Type *)GPIO6_BASE) |
#define | GPIO7_BASE (0x40C5C000u) |
#define | GPIO7 ((GPIO_Type *)GPIO7_BASE) |
#define | GPIO8_BASE (0x40C60000u) |
#define | GPIO8 ((GPIO_Type *)GPIO8_BASE) |
#define | GPIO9_BASE (0x40C64000u) |
#define | GPIO9 ((GPIO_Type *)GPIO9_BASE) |
#define | GPIO10_BASE (0x40C68000u) |
#define | GPIO10 ((GPIO_Type *)GPIO10_BASE) |
#define | GPIO11_BASE (0x40C6C000u) |
#define | GPIO11 ((GPIO_Type *)GPIO11_BASE) |
#define | GPIO12_BASE (0x40C70000u) |
#define | GPIO12 ((GPIO_Type *)GPIO12_BASE) |
#define | GPIO13_BASE (0x40CA0000u) |
#define | GPIO13 ((GPIO_Type *)GPIO13_BASE) |
#define | CM7_GPIO2_BASE (0x42008000u) |
#define | CM7_GPIO2 ((GPIO_Type *)CM7_GPIO2_BASE) |
#define | CM7_GPIO3_BASE (0x4200C000u) |
#define | CM7_GPIO3 ((GPIO_Type *)CM7_GPIO3_BASE) |
#define | GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE, GPIO10_BASE, GPIO11_BASE, GPIO12_BASE, GPIO13_BASE, CM7_GPIO2_BASE, CM7_GPIO3_BASE } |
#define | GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, CM7_GPIO2, CM7_GPIO3 } |
#define | GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, NotAvail_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO12_Combined_0_15_IRQn, GPIO13_Combined_0_31_IRQn, NotAvail_IRQn, NotAvail_IRQn } |
#define | GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, NotAvail_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO7_8_9_10_11_IRQn, GPIO12_Combined_16_31_IRQn, GPIO13_Combined_0_31_IRQn, NotAvail_IRQn, NotAvail_IRQn } |
#define | GPT_OCR_COUNT (3U) |
#define | GPT_ICR_COUNT (2U) |
#define | GPT1_BASE (0x400EC000u) |
#define | GPT1 ((GPT_Type *)GPT1_BASE) |
#define | GPT2_BASE (0x400F0000u) |
#define | GPT2 ((GPT_Type *)GPT2_BASE) |
#define | GPT3_BASE (0x400F4000u) |
#define | GPT3 ((GPT_Type *)GPT3_BASE) |
#define | GPT4_BASE (0x400F8000u) |
#define | GPT4 ((GPT_Type *)GPT4_BASE) |
#define | GPT5_BASE (0x400FC000u) |
#define | GPT5 ((GPT_Type *)GPT5_BASE) |
#define | GPT6_BASE (0x40100000u) |
#define | GPT6 ((GPT_Type *)GPT6_BASE) |
#define | GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE } |
#define | GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 } |
#define | GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn } |
#define | I2S_TDR_COUNT (4U) |
#define | I2S_TFR_COUNT (4U) |
#define | I2S_RDR_COUNT (4U) |
#define | I2S_RFR_COUNT (4U) |
#define | SAI1_BASE (0x40404000u) |
#define | SAI1 ((I2S_Type *)SAI1_BASE) |
#define | SAI2_BASE (0x40408000u) |
#define | SAI2 ((I2S_Type *)SAI2_BASE) |
#define | SAI3_BASE (0x4040C000u) |
#define | SAI3 ((I2S_Type *)SAI3_BASE) |
#define | SAI4_BASE (0x40C40000u) |
#define | SAI4 ((I2S_Type *)SAI4_BASE) |
#define | I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE } |
#define | I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 } |
#define | I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn, SAI4_RX_IRQn } |
#define | I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn, SAI4_TX_IRQn } |
#define | IEE_REGATTR_COUNT (8U) |
#define | IEE_REGPO_COUNT (8U) |
#define | IEE_REGKEY1_COUNT (8U) |
#define | IEE_REGKEY1_COUNT2 (8U) |
#define | IEE_REGKEY2_COUNT (8U) |
#define | IEE_REGKEY2_COUNT2 (8U) |
#define | IEE_AES_TST_DB_COUNT (32U) |
#define | IEE__IEE_RT1170_BASE (0x4006C000u) |
#define | IEE__IEE_RT1170 ((IEE_Type *)IEE__IEE_RT1170_BASE) |
#define | IEE_BASE_ADDRS { IEE__IEE_RT1170_BASE } |
#define | IEE_BASE_PTRS { IEE__IEE_RT1170 } |
#define | IEE_APC_BASE (0x40068000u) |
#define | IEE_APC ((IEE_APC_Type *)IEE_APC_BASE) |
#define | IEE_APC_BASE_ADDRS { IEE_APC_BASE } |
#define | IEE_APC_BASE_PTRS { IEE_APC } |
#define | IOMUXC_SW_MUX_CTL_PAD_COUNT (145U) |
#define | IOMUXC_SW_PAD_CTL_PAD_COUNT (145U) |
#define | IOMUXC_SELECT_INPUT_COUNT (160U) |
#define | IOMUXC_BASE (0x400E8000u) |
#define | IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) |
#define | IOMUXC_BASE_ADDRS { IOMUXC_BASE } |
#define | IOMUXC_BASE_PTRS { IOMUXC } |
#define | IOMUXC_GPR_BASE (0x400E4000u) |
#define | IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) |
#define | IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } |
#define | IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } |
#define | IOMUXC_LPSR_SW_MUX_CTL_PAD_COUNT (16U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_COUNT (16U) |
#define | IOMUXC_LPSR_SELECT_INPUT_COUNT (24U) |
#define | IOMUXC_LPSR_BASE (0x40C08000u) |
#define | IOMUXC_LPSR ((IOMUXC_LPSR_Type *)IOMUXC_LPSR_BASE) |
#define | IOMUXC_LPSR_BASE_ADDRS { IOMUXC_LPSR_BASE } |
#define | IOMUXC_LPSR_BASE_PTRS { IOMUXC_LPSR } |
#define | IOMUXC_LPSR_GPR_BASE (0x40C0C000u) |
#define | IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) |
#define | IOMUXC_LPSR_GPR_BASE_ADDRS { IOMUXC_LPSR_GPR_BASE } |
#define | IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR } |
#define | IOMUXC_SNVS_BASE (0x40C94000u) |
#define | IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE) |
#define | IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE } |
#define | IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS } |
#define | IOMUXC_SNVS_GPR_GPR_COUNT (32U) |
#define | IOMUXC_SNVS_GPR_BASE (0x40C98000u) |
#define | IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE) |
#define | IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE } |
#define | IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR } |
#define | IPS_DOMAIN_SLOT_CTRL_COUNT (38U) |
#define | IPS_DOMAIN_BASE (0x40C87C00u) |
#define | IPS_DOMAIN ((IPS_DOMAIN_Type *)IPS_DOMAIN_BASE) |
#define | IPS_DOMAIN_BASE_ADDRS { IPS_DOMAIN_BASE } |
#define | IPS_DOMAIN_BASE_PTRS { IPS_DOMAIN } |
#define | KEY_MANAGER_BASE (0x40C80000u) |
#define | KEY_MANAGER ((KEY_MANAGER_Type *)KEY_MANAGER_BASE) |
#define | KEY_MANAGER_BASE_ADDRS { KEY_MANAGER_BASE } |
#define | KEY_MANAGER_BASE_PTRS { KEY_MANAGER } |
#define | KPP_BASE (0x400E0000u) |
#define | KPP ((KPP_Type *)KPP_BASE) |
#define | KPP_BASE_ADDRS { KPP_BASE } |
#define | KPP_BASE_PTRS { KPP } |
#define | KPP_IRQS { KPP_IRQn } |
#define | LCDIF_PIGEON_0_COUNT (12U) |
#define | LCDIF_PIGEON_1_COUNT (12U) |
#define | LCDIF_PIGEON_2_COUNT (12U) |
#define | LCDIF_BASE (0x40804000u) |
#define | LCDIF ((LCDIF_Type *)LCDIF_BASE) |
#define | LCDIF_BASE_ADDRS { LCDIF_BASE } |
#define | LCDIF_BASE_PTRS { LCDIF } |
#define | LCDIF_IRQ0_IRQS { eLCDIF_IRQn } |
#define | LCDIFV2_INT_STATUS_COUNT (2U) |
#define | LCDIFV2_INT_ENABLE_COUNT (2U) |
#define | LCDIFV2_CTRLDESCL1_COUNT (8U) |
#define | LCDIFV2_CTRLDESCL2_COUNT (8U) |
#define | LCDIFV2_CTRLDESCL3_COUNT (8U) |
#define | LCDIFV2_CTRLDESCL4_COUNT (8U) |
#define | LCDIFV2_CTRLDESCL5_COUNT (8U) |
#define | LCDIFV2_CTRLDESCL6_COUNT (8U) |
#define | LCDIFV2_CSC_COEF0_COUNT (8U) |
#define | LCDIFV2_CSC_COEF1_COUNT (8U) |
#define | LCDIFV2_CSC_COEF2_COUNT (8U) |
#define | LCDIFV2_BASE (0x40808000u) |
#define | LCDIFV2 ((LCDIFV2_Type *)LCDIFV2_BASE) |
#define | LCDIFV2_BASE_ADDRS { LCDIFV2_BASE } |
#define | LCDIFV2_BASE_PTRS { LCDIFV2 } |
#define | LMEM_BASE (0xE0082000u) |
#define | LMEM ((LMEM_Type *)LMEM_BASE) |
#define | LMEM_BASE_ADDRS { LMEM_BASE } |
#define | LMEM_BASE_PTRS { LMEM } |
#define | LPI2C1_BASE (0x40104000u) |
#define | LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) |
#define | LPI2C2_BASE (0x40108000u) |
#define | LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) |
#define | LPI2C3_BASE (0x4010C000u) |
#define | LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) |
#define | LPI2C4_BASE (0x40110000u) |
#define | LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) |
#define | LPI2C5_BASE (0x40C34000u) |
#define | LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) |
#define | LPI2C6_BASE (0x40C38000u) |
#define | LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) |
#define | LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE } |
#define | LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6 } |
#define | LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn, LPI2C5_IRQn, LPI2C6_IRQn } |
#define | LPSPI1_BASE (0x40114000u) |
#define | LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) |
#define | LPSPI2_BASE (0x40118000u) |
#define | LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) |
#define | LPSPI3_BASE (0x4011C000u) |
#define | LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) |
#define | LPSPI4_BASE (0x40120000u) |
#define | LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) |
#define | LPSPI5_BASE (0x40C2C000u) |
#define | LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) |
#define | LPSPI6_BASE (0x40C30000u) |
#define | LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) |
#define | LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE } |
#define | LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6 } |
#define | LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn, LPSPI5_IRQn, LPSPI6_IRQn } |
#define | LPUART1_BASE (0x4007C000u) |
#define | LPUART1 ((LPUART_Type *)LPUART1_BASE) |
#define | LPUART2_BASE (0x40080000u) |
#define | LPUART2 ((LPUART_Type *)LPUART2_BASE) |
#define | LPUART3_BASE (0x40084000u) |
#define | LPUART3 ((LPUART_Type *)LPUART3_BASE) |
#define | LPUART4_BASE (0x40088000u) |
#define | LPUART4 ((LPUART_Type *)LPUART4_BASE) |
#define | LPUART5_BASE (0x4008C000u) |
#define | LPUART5 ((LPUART_Type *)LPUART5_BASE) |
#define | LPUART6_BASE (0x40090000u) |
#define | LPUART6 ((LPUART_Type *)LPUART6_BASE) |
#define | LPUART7_BASE (0x40094000u) |
#define | LPUART7 ((LPUART_Type *)LPUART7_BASE) |
#define | LPUART8_BASE (0x40098000u) |
#define | LPUART8 ((LPUART_Type *)LPUART8_BASE) |
#define | LPUART9_BASE (0x4009C000u) |
#define | LPUART9 ((LPUART_Type *)LPUART9_BASE) |
#define | LPUART10_BASE (0x400A0000u) |
#define | LPUART10 ((LPUART_Type *)LPUART10_BASE) |
#define | LPUART11_BASE (0x40C24000u) |
#define | LPUART11 ((LPUART_Type *)LPUART11_BASE) |
#define | LPUART12_BASE (0x40C28000u) |
#define | LPUART12 ((LPUART_Type *)LPUART12_BASE) |
#define | LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE, LPUART10_BASE, LPUART11_BASE, LPUART12_BASE } |
#define | LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LPUART10, LPUART11, LPUART12 } |
#define | LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn, LPUART9_IRQn, LPUART10_IRQn, LPUART11_IRQn, LPUART12_IRQn } |
#define | MCM_LMDR_COUNT (4U) |
#define | MCM_BASE (0xE0080000u) |
#define | MCM ((MCM_Type *)MCM_BASE) |
#define | MCM_BASE_ADDRS { MCM_BASE } |
#define | MCM_BASE_PTRS { MCM } |
#define | MECC1_BASE (0x40014000u) |
#define | MECC1 ((MECC_Type *)MECC1_BASE) |
#define | MECC2_BASE (0x40018000u) |
#define | MECC2 ((MECC_Type *)MECC2_BASE) |
#define | MECC_BASE_ADDRS { 0u, MECC1_BASE, MECC2_BASE } |
#define | MECC_BASE_PTRS { (MECC_Type *)0u, MECC1, MECC2 } |
#define | MIPI_CSI2RX_BASE (0x40810000u) |
#define | MIPI_CSI2RX ((MIPI_CSI2RX_Type *)MIPI_CSI2RX_BASE) |
#define | MIPI_CSI2RX_BASE_ADDRS { MIPI_CSI2RX_BASE } |
#define | MIPI_CSI2RX_BASE_PTRS { MIPI_CSI2RX } |
#define | MMCAU_CA_COUNT (9U) |
#define | MMCAU_BASE (0xE0081000u) |
#define | MMCAU ((MMCAU_Type *)MMCAU_BASE) |
#define | MMCAU_BASE_ADDRS { MMCAU_BASE } |
#define | MMCAU_BASE_PTRS { MMCAU } |
#define | MU_TR_COUNT (4U) |
#define | MU_RR_COUNT (4U) |
#define | MUB_BASE (0x40C4C000u) |
#define | MUB ((MU_Type *)MUB_BASE) |
#define | MU_BASE_ADDRS { MUB_BASE } |
#define | MU_BASE_PTRS { MUB } |
#define | MU_IRQS { MUB_IRQn } |
#define | OCOTP_READ_FUSE_DATA_COUNT (4U) |
#define | OCOTP_FUSE_COUNT (144U) |
#define | OCOTP_BASE (0x40CAC000u) |
#define | OCOTP ((OCOTP_Type *)OCOTP_BASE) |
#define | OCOTP_BASE_ADDRS { OCOTP_BASE } |
#define | OCOTP_BASE_PTRS { OCOTP } |
#define | OSC_RC_400M_BASE (0u) |
#define | OSC_RC_400M ((OSC_RC_400M_Type *)OSC_RC_400M_BASE) |
#define | OSC_RC_400M_BASE_ADDRS { OSC_RC_400M_BASE } |
#define | OSC_RC_400M_BASE_PTRS { OSC_RC_400M } |
#define | OTFAD_KEY_COUNT (4U) |
#define | OTFAD_KEY_COUNT2 (4U) |
#define | OTFAD_CTR_COUNT (4U) |
#define | OTFAD_CTR_COUNT2 (2U) |
#define | OTFAD_RGD_W0_COUNT (4U) |
#define | OTFAD_RGD_W1_COUNT (4U) |
#define | OTFAD1_BASE (0x400CC000u) |
#define | OTFAD1 ((OTFAD_Type *)OTFAD1_BASE) |
#define | OTFAD2_BASE (0x400D0000u) |
#define | OTFAD2 ((OTFAD_Type *)OTFAD2_BASE) |
#define | OTFAD_BASE_ADDRS { 0u, OTFAD1_BASE, OTFAD2_BASE } |
#define | OTFAD_BASE_PTRS { (OTFAD_Type *)0u, OTFAD1, OTFAD2 } |
#define | PDM_DATACH_COUNT (8U) |
#define | PDM_BASE (0x40C20000u) |
#define | PDM ((PDM_Type *)PDM_BASE) |
#define | PDM_BASE_ADDRS { PDM_BASE } |
#define | PDM_BASE_PTRS { PDM } |
#define | PGMC_BPC0_BASE (0x40C88000u) |
#define | PGMC_BPC0 ((PGMC_BPC_Type *)PGMC_BPC0_BASE) |
#define | PGMC_BPC1_BASE (0x40C88200u) |
#define | PGMC_BPC1 ((PGMC_BPC_Type *)PGMC_BPC1_BASE) |
#define | PGMC_BPC2_BASE (0x40C88400u) |
#define | PGMC_BPC2 ((PGMC_BPC_Type *)PGMC_BPC2_BASE) |
#define | PGMC_BPC3_BASE (0x40C88600u) |
#define | PGMC_BPC3 ((PGMC_BPC_Type *)PGMC_BPC3_BASE) |
#define | PGMC_BPC4_BASE (0x40C88800u) |
#define | PGMC_BPC4 ((PGMC_BPC_Type *)PGMC_BPC4_BASE) |
#define | PGMC_BPC5_BASE (0x40C88A00u) |
#define | PGMC_BPC5 ((PGMC_BPC_Type *)PGMC_BPC5_BASE) |
#define | PGMC_BPC6_BASE (0x40C88C00u) |
#define | PGMC_BPC6 ((PGMC_BPC_Type *)PGMC_BPC6_BASE) |
#define | PGMC_BPC7_BASE (0x40C88E00u) |
#define | PGMC_BPC7 ((PGMC_BPC_Type *)PGMC_BPC7_BASE) |
#define | PGMC_BPC_BASE_ADDRS { PGMC_BPC0_BASE, PGMC_BPC1_BASE, PGMC_BPC2_BASE, PGMC_BPC3_BASE, PGMC_BPC4_BASE, PGMC_BPC5_BASE, PGMC_BPC6_BASE, PGMC_BPC7_BASE } |
#define | PGMC_BPC_BASE_PTRS { PGMC_BPC0, PGMC_BPC1, PGMC_BPC2, PGMC_BPC3, PGMC_BPC4, PGMC_BPC5, PGMC_BPC6, PGMC_BPC7 } |
#define | PGMC_CPC0_BASE (0x40C89000u) |
#define | PGMC_CPC0 ((PGMC_CPC_Type *)PGMC_CPC0_BASE) |
#define | PGMC_CPC1_BASE (0x40C89400u) |
#define | PGMC_CPC1 ((PGMC_CPC_Type *)PGMC_CPC1_BASE) |
#define | PGMC_CPC_BASE_ADDRS { PGMC_CPC0_BASE, PGMC_CPC1_BASE } |
#define | PGMC_CPC_BASE_PTRS { PGMC_CPC0, PGMC_CPC1 } |
#define | PGMC_CPC0_MIF0_BASE (0x40C89100u) |
#define | PGMC_CPC0_MIF0 ((PGMC_MIF_Type *)PGMC_CPC0_MIF0_BASE) |
#define | PGMC_CPC0_MIF1_BASE (0x40C89200u) |
#define | PGMC_CPC0_MIF1 ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE) |
#define | PGMC_CPC1_MIF0_BASE (0x40C89500u) |
#define | PGMC_CPC1_MIF0 ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE) |
#define | PGMC_CPC1_MIF1_BASE (0x40C89600u) |
#define | PGMC_CPC1_MIF1 ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE) |
#define | PGMC_MIF_BASE_ADDRS { PGMC_CPC0_MIF0_BASE, PGMC_CPC0_MIF1_BASE, PGMC_CPC1_MIF0_BASE, PGMC_CPC1_MIF1_BASE } |
#define | PGMC_MIF_BASE_PTRS { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 } |
#define | PGMC_PPC0_BASE (0x40C8B000u) |
#define | PGMC_PPC0 ((PGMC_PPC_Type *)PGMC_PPC0_BASE) |
#define | PGMC_PPC_BASE_ADDRS { PGMC_PPC0_BASE } |
#define | PGMC_PPC_BASE_PTRS { PGMC_PPC0 } |
#define | PHY_LDO_BASE (0u) |
#define | PHY_LDO ((PHY_LDO_Type *)PHY_LDO_BASE) |
#define | PHY_LDO_BASE_ADDRS { PHY_LDO_BASE } |
#define | PHY_LDO_BASE_PTRS { PHY_LDO } |
#define | PIT_LDVAL_COUNT (4U) |
#define | PIT_CVAL_COUNT (4U) |
#define | PIT_TCTRL_COUNT (4U) |
#define | PIT_TFLG_COUNT (4U) |
#define | PIT1_BASE (0x400D8000u) |
#define | PIT1 ((PIT_Type *)PIT1_BASE) |
#define | PIT2_BASE (0x40CB0000u) |
#define | PIT2 ((PIT_Type *)PIT2_BASE) |
#define | PIT_BASE_ADDRS { 0u, PIT1_BASE, PIT2_BASE } |
#define | PIT_BASE_PTRS { (PIT_Type *)0u, PIT1, PIT2 } |
#define | PIT_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PIT1_IRQn, PIT1_IRQn, PIT1_IRQn, PIT1_IRQn }, { PIT2_IRQn, PIT2_IRQn, PIT2_IRQn, PIT2_IRQn } } |
#define | PUF_KEYMASK_COUNT (2U) |
#define | KEY_MANAGER__PUF_BASE (0x40C82000u) |
#define | KEY_MANAGER__PUF ((PUF_Type *)KEY_MANAGER__PUF_BASE) |
#define | PUF_BASE_ADDRS { KEY_MANAGER__PUF_BASE } |
#define | PUF_BASE_PTRS { KEY_MANAGER__PUF } |
#define | PWM_CNT_COUNT (4U) |
#define | PWM_INIT_COUNT (4U) |
#define | PWM_CTRL2_COUNT (4U) |
#define | PWM_CTRL_COUNT (4U) |
#define | PWM_VAL0_COUNT (4U) |
#define | PWM_FRACVAL1_COUNT (4U) |
#define | PWM_VAL1_COUNT (4U) |
#define | PWM_FRACVAL2_COUNT (4U) |
#define | PWM_VAL2_COUNT (4U) |
#define | PWM_FRACVAL3_COUNT (4U) |
#define | PWM_VAL3_COUNT (4U) |
#define | PWM_FRACVAL4_COUNT (4U) |
#define | PWM_VAL4_COUNT (4U) |
#define | PWM_FRACVAL5_COUNT (4U) |
#define | PWM_VAL5_COUNT (4U) |
#define | PWM_FRCTRL_COUNT (4U) |
#define | PWM_OCTRL_COUNT (4U) |
#define | PWM_STS_COUNT (4U) |
#define | PWM_INTEN_COUNT (4U) |
#define | PWM_DMAEN_COUNT (4U) |
#define | PWM_TCTRL_COUNT (4U) |
#define | PWM_DISMAP_COUNT (4U) |
#define | PWM_DISMAP_COUNT2 (1U) |
#define | PWM_DTCNT0_COUNT (4U) |
#define | PWM_DTCNT1_COUNT (4U) |
#define | PWM_CAPTCTRLA_COUNT (4U) |
#define | PWM_CAPTCOMPA_COUNT (4U) |
#define | PWM_CAPTCTRLB_COUNT (4U) |
#define | PWM_CAPTCOMPB_COUNT (4U) |
#define | PWM_CAPTCTRLX_COUNT (4U) |
#define | PWM_CAPTCOMPX_COUNT (4U) |
#define | PWM_CVAL0_COUNT (4U) |
#define | PWM_CVAL0CYC_COUNT (4U) |
#define | PWM_CVAL1_COUNT (4U) |
#define | PWM_CVAL1CYC_COUNT (4U) |
#define | PWM_CVAL2_COUNT (4U) |
#define | PWM_CVAL2CYC_COUNT (4U) |
#define | PWM_CVAL3_COUNT (4U) |
#define | PWM_CVAL3CYC_COUNT (4U) |
#define | PWM_CVAL4_COUNT (4U) |
#define | PWM_CVAL4CYC_COUNT (4U) |
#define | PWM_CVAL5_COUNT (4U) |
#define | PWM_CVAL5CYC_COUNT (4U) |
#define | PWM1_BASE (0x4018C000u) |
#define | PWM1 ((PWM_Type *)PWM1_BASE) |
#define | PWM2_BASE (0x40190000u) |
#define | PWM2 ((PWM_Type *)PWM2_BASE) |
#define | PWM3_BASE (0x40194000u) |
#define | PWM3 ((PWM_Type *)PWM3_BASE) |
#define | PWM4_BASE (0x40198000u) |
#define | PWM4 ((PWM_Type *)PWM4_BASE) |
#define | PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE } |
#define | PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 } |
#define | PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } |
#define | PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } |
#define | PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } |
#define | PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } |
#define | PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } |
#define | PXP_BASE (0x40814000u) |
#define | PXP ((PXP_Type *)PXP_BASE) |
#define | PXP_BASE_ADDRS { PXP_BASE } |
#define | PXP_BASE_PTRS { PXP } |
#define | PXP_IRQ0_IRQS { PXP_IRQn } |
#define | RDC_MDA_COUNT (12U) |
#define | RDC_PDAP_COUNT (128U) |
#define | RDC_MRSA_COUNT (59U) |
#define | RDC_MREA_COUNT (59U) |
#define | RDC_MRC_COUNT (59U) |
#define | RDC_MRVS_COUNT (59U) |
#define | RDC_BASE (0x40C78000u) |
#define | RDC ((RDC_Type *)RDC_BASE) |
#define | RDC_BASE_ADDRS { RDC_BASE } |
#define | RDC_BASE_PTRS { RDC } |
#define | RDC_IRQS { RDC_IRQn } |
#define | RDC_SEMAPHORE_GATE_COUNT (64U) |
#define | RDC_SEMAPHORE1_BASE (0x40C44000u) |
#define | RDC_SEMAPHORE1 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE) |
#define | RDC_SEMAPHORE2_BASE (0x40CCC000u) |
#define | RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE) |
#define | RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE } |
#define | RDC_SEMAPHORE_BASE_PTRS { RDC_SEMAPHORE1, RDC_SEMAPHORE2 } |
#define | RTWDOG3_BASE (0x40038000u) |
#define | RTWDOG3 ((RTWDOG_Type *)RTWDOG3_BASE) |
#define | RTWDOG4_BASE (0x40C10000u) |
#define | RTWDOG4 ((RTWDOG_Type *)RTWDOG4_BASE) |
#define | RTWDOG_BASE_ADDRS { 0u, 0u, 0u, RTWDOG3_BASE, RTWDOG4_BASE } |
#define | RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 } |
#define | RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG4_IRQn } |
#define | RTWDOG_UPDATE_KEY (0xD928C520U) |
#define | RTWDOG_REFRESH_KEY (0xB480A602U) |
#define | SEMA4_GATE_COUNT (16U) |
#define | SEMA4_CPINE_COUNT (2U) |
#define | SEMA4_CPNTF_COUNT (2U) |
#define | SEMA4_BASE (0x40CC8000u) |
#define | SEMA4 ((SEMA4_Type *)SEMA4_BASE) |
#define | SEMA4_BASE_ADDRS { SEMA4_BASE } |
#define | SEMA4_BASE_PTRS { SEMA4 } |
#define | SEMC_BR_COUNT (9U) |
#define | SEMC_BASE (0x400D4000u) |
#define | SEMC ((SEMC_Type *)SEMC_BASE) |
#define | SEMC_BASE_ADDRS { SEMC_BASE } |
#define | SEMC_BASE_PTRS { SEMC } |
#define | SEMC_IRQS { SEMC_IRQn } |
#define | SNVS_LPZMKR_COUNT (8U) |
#define | SNVS_LPGPR_ALIAS_COUNT (4U) |
#define | SNVS_LPATCR_COUNT (5U) |
#define | SNVS_LPGPR_COUNT (4U) |
#define | SNVS_BASE (0x40C90000u) |
#define | SNVS ((SNVS_Type *)SNVS_BASE) |
#define | SNVS_BASE_ADDRS { SNVS_BASE } |
#define | SNVS_BASE_PTRS { SNVS } |
#define | SNVS_IRQS { SNVS_PULSE_EVENT_IRQn } |
#define | SNVS_CONSOLIDATED_IRQS { SNVS_HP_NON_TZ_IRQn } |
#define | SNVS_SECURITY_IRQS { SNVS_HP_TZ_IRQn } |
#define | SPDIF_BASE (0x40400000u) |
#define | SPDIF ((SPDIF_Type *)SPDIF_BASE) |
#define | SPDIF_BASE_ADDRS { SPDIF_BASE } |
#define | SPDIF_BASE_PTRS { SPDIF } |
#define | SPDIF_IRQS { SPDIF_IRQn } |
#define | SRAM_BASE (0x40C9C000u) |
#define | SRAM ((SRAM_Type *)SRAM_BASE) |
#define | SRAM_BASE_ADDRS { SRAM_BASE } |
#define | SRAM_BASE_PTRS { SRAM } |
#define | SRC_GPR_COUNT (20U) |
#define | SRC_BASE (0x40C04000u) |
#define | SRC ((SRC_Type *)SRC_BASE) |
#define | SRC_BASE_ADDRS { SRC_BASE } |
#define | SRC_BASE_PTRS { SRC } |
#define | SSARC_HP_SRAM0_COUNT (1024U) |
#define | SSARC_HP_SRAM1_COUNT (1024U) |
#define | SSARC_HP_SRAM2_COUNT (1024U) |
#define | SSARC_HP_BASE (0x40CB4000u) |
#define | SSARC_HP ((SSARC_HP_Type *)SSARC_HP_BASE) |
#define | SSARC_HP_BASE_ADDRS { SSARC_HP_BASE } |
#define | SSARC_HP_BASE_PTRS { SSARC_HP } |
#define | SSARC_LP_DESC_CTRL0_COUNT (16U) |
#define | SSARC_LP_DESC_CTRL1_COUNT (16U) |
#define | SSARC_LP_DESC_ADDR_UP_COUNT (16U) |
#define | SSARC_LP_DESC_ADDR_DOWN_COUNT (16U) |
#define | SSARC_LP_BASE (0x40CB8000u) |
#define | SSARC_LP ((SSARC_LP_Type *)SSARC_LP_BASE) |
#define | SSARC_LP_BASE_ADDRS { SSARC_LP_BASE } |
#define | SSARC_LP_BASE_PTRS { SSARC_LP } |
#define | TMPSNS_BASE (0u) |
#define | TMPSNS ((TMPSNS_Type *)TMPSNS_BASE) |
#define | TMPSNS_BASE_ADDRS { TMPSNS_BASE } |
#define | TMPSNS_BASE_PTRS { TMPSNS } |
#define | TMR_COMP1_COUNT (4U) |
#define | TMR_COMP2_COUNT (4U) |
#define | TMR_CAPT_COUNT (4U) |
#define | TMR_LOAD_COUNT (4U) |
#define | TMR_HOLD_COUNT (4U) |
#define | TMR_CNTR_COUNT (4U) |
#define | TMR_CTRL_COUNT (4U) |
#define | TMR_SCTRL_COUNT (4U) |
#define | TMR_CMPLD1_COUNT (4U) |
#define | TMR_CMPLD2_COUNT (4U) |
#define | TMR_CSCTRL_COUNT (4U) |
#define | TMR_FILT_COUNT (4U) |
#define | TMR_DMA_COUNT (4U) |
#define | TMR_ENBL_COUNT (4U) |
#define | TMR1_BASE (0x4015C000u) |
#define | TMR1 ((TMR_Type *)TMR1_BASE) |
#define | TMR2_BASE (0x40160000u) |
#define | TMR2 ((TMR_Type *)TMR2_BASE) |
#define | TMR3_BASE (0x40164000u) |
#define | TMR3 ((TMR_Type *)TMR3_BASE) |
#define | TMR4_BASE (0x40168000u) |
#define | TMR4 ((TMR_Type *)TMR4_BASE) |
#define | TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE } |
#define | TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 } |
#define | TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn } |
#define | USB_ENDPTCTRL_COUNT (7U) |
#define | USB_OTG1_BASE (0x40430000u) |
#define | USB_OTG1 ((USB_Type *)USB_OTG1_BASE) |
#define | USB_OTG2_BASE (0x4042C000u) |
#define | USB_OTG2 ((USB_Type *)USB_OTG2_BASE) |
#define | USB_BASE_ADDRS { 0u, USB_OTG1_BASE, USB_OTG2_BASE } |
#define | USB_BASE_PTRS { (USB_Type *)0u, USB_OTG1, USB_OTG2 } |
#define | USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn } |
#define | GPTIMER0CTL GPTIMER0CTRL |
#define | GPTIMER1CTL GPTIMER1CTRL |
#define | USB_SBUSCFG SBUSCFG |
#define | EPLISTADDR ENDPTLISTADDR |
#define | EPSETUPSR ENDPTSETUPSTAT |
#define | EPPRIME ENDPTPRIME |
#define | EPFLUSH ENDPTFLUSH |
#define | EPSR ENDPTSTAT |
#define | EPCOMPLETE ENDPTCOMPLETE |
#define | EPCR ENDPTCTRL |
#define | EPCR0 ENDPTCTRL0 |
#define | USBHS_ID_ID_MASK USB_ID_ID_MASK |
#define | USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT |
#define | USBHS_ID_ID(x) USB_ID_ID(x) |
#define | USBHS_ID_NID_MASK USB_ID_NID_MASK |
#define | USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT |
#define | USBHS_ID_NID(x) USB_ID_NID(x) |
#define | USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK |
#define | USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT |
#define | USBHS_ID_REVISION(x) USB_ID_REVISION(x) |
#define | USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK |
#define | USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT |
#define | USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) |
#define | USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK |
#define | USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT |
#define | USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) |
#define | USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK |
#define | USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT |
#define | USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) |
#define | USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK |
#define | USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT |
#define | USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) |
#define | USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK |
#define | USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT |
#define | USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) |
#define | USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK |
#define | USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT |
#define | USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) |
#define | USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK |
#define | USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT |
#define | USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) |
#define | USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK |
#define | USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT |
#define | USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) |
#define | USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK |
#define | USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT |
#define | USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) |
#define | USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK |
#define | USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT |
#define | USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) |
#define | USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK |
#define | USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT |
#define | USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) |
#define | USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK |
#define | USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT |
#define | USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) |
#define | USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK |
#define | USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT |
#define | USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) |
#define | USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK |
#define | USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT |
#define | USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) |
#define | USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK |
#define | USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT |
#define | USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) |
#define | USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK |
#define | USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT |
#define | USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) |
#define | USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK |
#define | USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT |
#define | USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) |
#define | USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK |
#define | USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT |
#define | USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) |
#define | USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK |
#define | USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT |
#define | USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) |
#define | USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK |
#define | USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT |
#define | USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) |
#define | USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK |
#define | USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT |
#define | USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) |
#define | USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK |
#define | USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT |
#define | USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) |
#define | USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) |
#define | USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK |
#define | USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT |
#define | USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) |
#define | USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK |
#define | USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT |
#define | USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) |
#define | USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK |
#define | USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT |
#define | USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) |
#define | USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK |
#define | USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT |
#define | USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) |
#define | USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK |
#define | USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT |
#define | USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) |
#define | USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK |
#define | USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT |
#define | USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) |
#define | USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK |
#define | USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT |
#define | USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) |
#define | USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK |
#define | USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT |
#define | USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) |
#define | USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK |
#define | USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT |
#define | USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) |
#define | USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK |
#define | USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT |
#define | USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) |
#define | USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK |
#define | USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT |
#define | USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) |
#define | USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK |
#define | USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT |
#define | USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) |
#define | USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK |
#define | USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT |
#define | USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) |
#define | USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK |
#define | USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT |
#define | USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) |
#define | USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK |
#define | USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT |
#define | USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) |
#define | USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK |
#define | USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT |
#define | USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) |
#define | USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK |
#define | USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT |
#define | USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) |
#define | USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK |
#define | USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT |
#define | USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) |
#define | USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK |
#define | USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT |
#define | USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) |
#define | USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK |
#define | USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT |
#define | USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) |
#define | USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK |
#define | USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT |
#define | USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) |
#define | USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK |
#define | USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT |
#define | USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) |
#define | USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK |
#define | USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT |
#define | USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) |
#define | USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK |
#define | USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT |
#define | USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) |
#define | USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK |
#define | USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT |
#define | USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) |
#define | USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK |
#define | USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT |
#define | USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) |
#define | USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK |
#define | USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT |
#define | USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) |
#define | USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK |
#define | USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT |
#define | USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) |
#define | USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK |
#define | USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT |
#define | USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) |
#define | USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK |
#define | USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT |
#define | USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) |
#define | USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK |
#define | USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT |
#define | USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) |
#define | USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK |
#define | USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT |
#define | USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) |
#define | USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK |
#define | USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT |
#define | USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) |
#define | USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK |
#define | USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT |
#define | USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) |
#define | USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK |
#define | USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT |
#define | USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) |
#define | USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK |
#define | USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT |
#define | USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) |
#define | USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK |
#define | USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT |
#define | USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) |
#define | USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK |
#define | USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT |
#define | USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) |
#define | USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK |
#define | USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT |
#define | USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) |
#define | USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK |
#define | USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT |
#define | USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) |
#define | USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK |
#define | USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT |
#define | USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) |
#define | USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK |
#define | USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT |
#define | USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) |
#define | USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK |
#define | USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT |
#define | USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) |
#define | USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK |
#define | USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT |
#define | USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) |
#define | USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK |
#define | USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT |
#define | USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) |
#define | USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK |
#define | USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT |
#define | USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) |
#define | USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK |
#define | USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT |
#define | USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) |
#define | USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK |
#define | USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT |
#define | USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) |
#define | USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK |
#define | USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT |
#define | USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) |
#define | USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK |
#define | USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT |
#define | USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) |
#define | USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK |
#define | USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT |
#define | USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) |
#define | USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK |
#define | USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT |
#define | USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) |
#define | USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK |
#define | USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT |
#define | USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) |
#define | USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK |
#define | USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT |
#define | USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) |
#define | USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK |
#define | USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT |
#define | USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) |
#define | USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK |
#define | USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT |
#define | USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) |
#define | USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK |
#define | USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT |
#define | USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) |
#define | USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK |
#define | USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT |
#define | USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) |
#define | USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK |
#define | USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT |
#define | USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) |
#define | USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK |
#define | USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT |
#define | USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) |
#define | USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK |
#define | USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT |
#define | USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) |
#define | USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK |
#define | USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT |
#define | USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) |
#define | USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK |
#define | USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT |
#define | USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) |
#define | USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK |
#define | USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT |
#define | USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) |
#define | USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK |
#define | USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT |
#define | USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) |
#define | USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK |
#define | USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT |
#define | USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) |
#define | USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK |
#define | USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT |
#define | USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) |
#define | USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK |
#define | USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT |
#define | USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) |
#define | USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK |
#define | USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT |
#define | USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) |
#define | USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK |
#define | USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT |
#define | USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) |
#define | USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK |
#define | USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT |
#define | USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) |
#define | USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK |
#define | USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT |
#define | USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) |
#define | USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK |
#define | USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT |
#define | USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) |
#define | USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK |
#define | USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT |
#define | USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) |
#define | USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK |
#define | USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT |
#define | USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) |
#define | USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK |
#define | USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT |
#define | USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) |
#define | USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK |
#define | USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT |
#define | USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) |
#define | USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK |
#define | USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT |
#define | USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) |
#define | USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK |
#define | USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT |
#define | USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) |
#define | USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK |
#define | USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT |
#define | USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) |
#define | USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK |
#define | USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT |
#define | USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) |
#define | USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK |
#define | USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT |
#define | USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) |
#define | USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK |
#define | USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT |
#define | USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) |
#define | USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK |
#define | USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT |
#define | USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) |
#define | USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK |
#define | USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT |
#define | USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) |
#define | USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK |
#define | USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT |
#define | USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) |
#define | USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK |
#define | USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT |
#define | USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) |
#define | USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK |
#define | USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT |
#define | USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) |
#define | USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK |
#define | USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT |
#define | USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) |
#define | USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK |
#define | USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT |
#define | USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) |
#define | USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK |
#define | USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT |
#define | USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) |
#define | USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK |
#define | USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT |
#define | USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) |
#define | USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK |
#define | USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT |
#define | USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) |
#define | USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK |
#define | USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT |
#define | USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) |
#define | USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK |
#define | USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT |
#define | USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) |
#define | USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK |
#define | USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT |
#define | USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) |
#define | USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK |
#define | USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT |
#define | USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) |
#define | USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK |
#define | USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT |
#define | USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) |
#define | USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK |
#define | USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT |
#define | USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) |
#define | USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK |
#define | USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT |
#define | USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) |
#define | USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK |
#define | USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT |
#define | USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) |
#define | USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK |
#define | USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT |
#define | USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) |
#define | USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK |
#define | USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT |
#define | USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) |
#define | USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK |
#define | USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT |
#define | USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) |
#define | USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK |
#define | USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT |
#define | USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) |
#define | USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK |
#define | USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT |
#define | USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) |
#define | USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK |
#define | USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT |
#define | USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) |
#define | USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK |
#define | USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT |
#define | USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) |
#define | USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK |
#define | USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT |
#define | USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) |
#define | USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK |
#define | USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT |
#define | USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) |
#define | USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK |
#define | USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT |
#define | USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) |
#define | USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK |
#define | USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT |
#define | USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) |
#define | USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK |
#define | USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT |
#define | USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) |
#define | USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK |
#define | USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT |
#define | USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) |
#define | USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK |
#define | USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT |
#define | USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) |
#define | USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK |
#define | USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT |
#define | USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) |
#define | USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK |
#define | USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT |
#define | USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) |
#define | USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK |
#define | USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT |
#define | USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) |
#define | USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK |
#define | USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT |
#define | USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) |
#define | USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK |
#define | USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT |
#define | USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) |
#define | USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK |
#define | USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT |
#define | USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) |
#define | USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK |
#define | USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT |
#define | USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) |
#define | USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK |
#define | USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT |
#define | USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) |
#define | USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK |
#define | USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT |
#define | USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) |
#define | USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK |
#define | USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT |
#define | USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) |
#define | USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK |
#define | USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT |
#define | USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) |
#define | USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK |
#define | USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT |
#define | USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) |
#define | USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK |
#define | USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT |
#define | USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) |
#define | USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK |
#define | USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT |
#define | USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) |
#define | USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK |
#define | USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT |
#define | USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) |
#define | USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK |
#define | USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT |
#define | USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) |
#define | USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK |
#define | USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT |
#define | USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) |
#define | USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK |
#define | USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT |
#define | USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) |
#define | USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK |
#define | USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT |
#define | USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) |
#define | USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK |
#define | USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT |
#define | USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) |
#define | USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK |
#define | USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT |
#define | USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) |
#define | USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK |
#define | USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT |
#define | USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) |
#define | USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK |
#define | USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT |
#define | USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) |
#define | USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK |
#define | USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT |
#define | USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) |
#define | USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK |
#define | USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT |
#define | USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) |
#define | USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK |
#define | USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT |
#define | USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) |
#define | USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK |
#define | USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT |
#define | USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) |
#define | USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK |
#define | USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT |
#define | USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) |
#define | USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK |
#define | USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT |
#define | USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) |
#define | USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK |
#define | USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT |
#define | USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) |
#define | USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK |
#define | USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT |
#define | USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) |
#define | USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK |
#define | USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT |
#define | USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) |
#define | USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK |
#define | USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT |
#define | USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) |
#define | USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK |
#define | USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT |
#define | USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) |
#define | USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK |
#define | USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT |
#define | USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) |
#define | USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK |
#define | USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT |
#define | USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) |
#define | USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK |
#define | USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT |
#define | USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) |
#define | USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK |
#define | USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT |
#define | USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) |
#define | USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK |
#define | USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT |
#define | USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) |
#define | USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK |
#define | USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT |
#define | USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) |
#define | USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK |
#define | USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT |
#define | USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) |
#define | USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK |
#define | USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT |
#define | USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) |
#define | USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK |
#define | USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT |
#define | USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) |
#define | USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK |
#define | USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT |
#define | USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) |
#define | USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT |
#define | USBHS_Type USB_Type |
#define | USBHS_BASE_ADDRS USB_BASE_ADDRS |
#define | USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } |
#define | USBHS_IRQHandler USB_OTG1_IRQHandler |
#define | USBHS_STACK_BASE_ADDRS { USB_OTG1_BASE, USB_OTG2_BASE } |
#define | USBHSDCD1_BASE (0x40434800u) |
#define | USBHSDCD1 ((USBHSDCD_Type *)USBHSDCD1_BASE) |
#define | USBHSDCD2_BASE (0x40438800u) |
#define | USBHSDCD2 ((USBHSDCD_Type *)USBHSDCD2_BASE) |
#define | USBHSDCD_BASE_ADDRS { 0u, USBHSDCD1_BASE, USBHSDCD2_BASE } |
#define | USBHSDCD_BASE_PTRS { (USBHSDCD_Type *)0u, USBHSDCD1, USBHSDCD2 } |
#define | USBHSDCD_STACK_BASE_ADDRS { USBHSDCD1_BASE, USBHSDCD2_BASE } |
#define | USBNC_OTG1_BASE (0x40430200u) |
#define | USBNC_OTG1 ((USBNC_Type *)USBNC_OTG1_BASE) |
#define | USBNC_OTG2_BASE (0x4042C200u) |
#define | USBNC_OTG2 ((USBNC_Type *)USBNC_OTG2_BASE) |
#define | USBNC_BASE_ADDRS { 0u, USBNC_OTG1_BASE, USBNC_OTG2_BASE } |
#define | USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC_OTG1, USBNC_OTG2 } |
#define | USB_OTGn_CTRL CTRL1 |
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK USBNC_CTRL1_OVER_CUR_DIS_MASK |
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT USBNC_CTRL1_OVER_CUR_DIS_SHIFT |
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) USBNC_CTRL1_OVER_CUR_DIS(x) |
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK USBNC_CTRL1_OVER_CUR_POL_MASK |
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT USBNC_CTRL1_OVER_CUR_POL_SHIFT |
#define | USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) USBNC_CTRL1_OVER_CUR_POL(x) |
#define | USBNC_USB_OTGn_CTRL_PWR_POL_MASK USBNC_CTRL1_PWR_POL_MASK |
#define | USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT USBNC_CTRL1_PWR_POL_SHIFT |
#define | USBNC_USB_OTGn_CTRL_PWR_POL(x) USBNC_CTRL1_PWR_POL(x) |
#define | USBNC_USB_OTGn_CTRL_WIE_MASK USBNC_CTRL1_WIE_MASK |
#define | USBNC_USB_OTGn_CTRL_WIE_SHIFT USBNC_CTRL1_WIE_SHIFT |
#define | USBNC_USB_OTGn_CTRL_WIE(x) USBNC_CTRL1_WIE(x) |
#define | USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK USBNC_CTRL1_WKUP_SW_EN_MASK |
#define | USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT USBNC_CTRL1_WKUP_SW_EN_SHIFT |
#define | USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) USBNC_CTRL1_WKUP_SW_EN(x) |
#define | USBNC_USB_OTGn_CTRL_WKUP_SW_MASK USBNC_CTRL1_WKUP_SW_MASK |
#define | USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT USBNC_CTRL1_WKUP_SW_SHIFT |
#define | USBNC_USB_OTGn_CTRL_WKUP_SW(x) USBNC_CTRL1_WKUP_SW(x) |
#define | USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK USBNC_CTRL1_WKUP_ID_EN_MASK |
#define | USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT USBNC_CTRL1_WKUP_ID_EN_SHIFT |
#define | USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) USBNC_CTRL1_WKUP_ID_EN(x) |
#define | USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK USBNC_CTRL1_WKUP_VBUS_EN_MASK |
#define | USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT USBNC_CTRL1_WKUP_VBUS_EN_SHIFT |
#define | USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) USBNC_CTRL1_WKUP_VBUS_EN(x) |
#define | USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK USBNC_CTRL1_WKUP_DPDM_EN_MASK |
#define | USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT USBNC_CTRL1_WKUP_DPDM_EN_SHIFT |
#define | USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) USBNC_CTRL1_WKUP_DPDM_EN(x) |
#define | USBNC_USB_OTGn_CTRL_WIR_MASK USBNC_CTRL1_WIR_MASK |
#define | USBNC_USB_OTGn_CTRL_WIR_SHIFT USBNC_CTRL1_WIR_SHIFT |
#define | USBNC_USB_OTGn_CTRL_WIR(x) USBNC_CTRL1_WIR(x) |
#define | USBNC_STACK_BASE_ADDRS { USBNC_OTG1_BASE, USBNC_OTG2_BASE } |
#define | USBPHY1_BASE (0x40434000u) |
#define | USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) |
#define | USBPHY2_BASE (0x40438000u) |
#define | USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) |
#define | USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE } |
#define | USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 } |
#define | USBPHY_IRQS { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn } |
#define | USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK |
#define | USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT |
#define | USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) |
#define | USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK |
#define | USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT |
#define | USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) |
#define | USBPHY_STACK_BASE_ADDRS { USBPHY1_BASE, USBPHY2_BASE } |
#define | USDHC1_BASE (0x40418000u) |
#define | USDHC1 ((USDHC_Type *)USDHC1_BASE) |
#define | USDHC2_BASE (0x4041C000u) |
#define | USDHC2 ((USDHC_Type *)USDHC2_BASE) |
#define | USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE } |
#define | USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 } |
#define | USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } |
#define | VIDEO_MUX_BASE (0x40818000u) |
#define | VIDEO_MUX ((VIDEO_MUX_Type *)VIDEO_MUX_BASE) |
#define | VIDEO_MUX_BASE_ADDRS { VIDEO_MUX_BASE } |
#define | VIDEO_MUX_BASE_PTRS { VIDEO_MUX } |
#define | VIDEO_PLL_BASE (0u) |
#define | VIDEO_PLL ((VIDEO_PLL_Type *)VIDEO_PLL_BASE) |
#define | VIDEO_PLL_BASE_ADDRS { VIDEO_PLL_BASE } |
#define | VIDEO_PLL_BASE_PTRS { VIDEO_PLL } |
#define | VMBANDGAP_BASE (0u) |
#define | VMBANDGAP ((VMBANDGAP_Type *)VMBANDGAP_BASE) |
#define | VMBANDGAP_BASE_ADDRS { VMBANDGAP_BASE } |
#define | VMBANDGAP_BASE_PTRS { VMBANDGAP } |
#define | WDOG1_BASE (0x40030000u) |
#define | WDOG1 ((WDOG_Type *)WDOG1_BASE) |
#define | WDOG2_BASE (0x40034000u) |
#define | WDOG2 ((WDOG_Type *)WDOG2_BASE) |
#define | WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE } |
#define | WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 } |
#define | WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn } |
#define | XBARA1_BASE (0x4003C000u) |
#define | XBARA1 ((XBARA_Type *)XBARA1_BASE) |
#define | XBARA_BASE_ADDRS { 0u, XBARA1_BASE } |
#define | XBARA_BASE_PTRS { (XBARA_Type *)0u, XBARA1 } |
#define | XBARB2_BASE (0x40040000u) |
#define | XBARB2 ((XBARB_Type *)XBARB2_BASE) |
#define | XBARB3_BASE (0x40044000u) |
#define | XBARB3 ((XBARB_Type *)XBARB3_BASE) |
#define | XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE } |
#define | XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 } |
#define | XECC_FLEXSPI1_BASE (0x4001C000u) |
#define | XECC_FLEXSPI1 ((XECC_Type *)XECC_FLEXSPI1_BASE) |
#define | XECC_FLEXSPI2_BASE (0x40020000u) |
#define | XECC_FLEXSPI2 ((XECC_Type *)XECC_FLEXSPI2_BASE) |
#define | XECC_SEMC_BASE (0x40024000u) |
#define | XECC_SEMC ((XECC_Type *)XECC_SEMC_BASE) |
#define | XECC_BASE_ADDRS { 0u, XECC_FLEXSPI1_BASE, XECC_FLEXSPI2_BASE, XECC_SEMC_BASE } |
#define | XECC_BASE_PTRS { (XECC_Type *)0u, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC } |
#define | XRDC2_MSC_MSAC_W0_COUNT (128U) |
#define | XRDC2_MSC_MSAC_W1_COUNT (128U) |
#define | XRDC2_MDAC_MDA_W0_COUNT (32U) |
#define | XRDC2_MDAC_MDA_W0_COUNT2 (32U) |
#define | XRDC2_MDAC_MDA_W1_COUNT (32U) |
#define | XRDC2_MDAC_MDA_W1_COUNT2 (32U) |
#define | XRDC2_PAC_PDAC_W0_COUNT (8U) |
#define | XRDC2_PAC_PDAC_W0_COUNT2 (256U) |
#define | XRDC2_PAC_PDAC_W1_COUNT (8U) |
#define | XRDC2_PAC_PDAC_W1_COUNT2 (256U) |
#define | XRDC2_MRC_MRGD_W0_COUNT (32U) |
#define | XRDC2_MRC_MRGD_W0_COUNT2 (32U) |
#define | XRDC2_MRC_MRGD_W1_COUNT (32U) |
#define | XRDC2_MRC_MRGD_W1_COUNT2 (32U) |
#define | XRDC2_MRC_MRGD_W2_COUNT (32U) |
#define | XRDC2_MRC_MRGD_W2_COUNT2 (32U) |
#define | XRDC2_MRC_MRGD_W3_COUNT (32U) |
#define | XRDC2_MRC_MRGD_W3_COUNT2 (32U) |
#define | XRDC2_MRC_MRGD_W5_COUNT (32U) |
#define | XRDC2_MRC_MRGD_W5_COUNT2 (32U) |
#define | XRDC2_MRC_MRGD_W6_COUNT (32U) |
#define | XRDC2_MRC_MRGD_W6_COUNT2 (32U) |
#define | XRDC2_D0_BASE (0x40CE0000u) |
#define | XRDC2_D0 ((XRDC2_Type *)XRDC2_D0_BASE) |
#define | XRDC2_D1_BASE (0x40CD0000u) |
#define | XRDC2_D1 ((XRDC2_Type *)XRDC2_D1_BASE) |
#define | XRDC2_BASE_ADDRS { XRDC2_D0_BASE, XRDC2_D1_BASE } |
#define | XRDC2_BASE_PTRS { XRDC2_D0, XRDC2_D1 } |
#define | NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) |
Mask and left-shift a bit field value for use in a register bit range. | |
#define | NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) |
Mask and right-shift a register value to extract a bit field value. | |
VERID - Version ID Register | |
#define | ADC_VERID_RES_MASK (0x1U) |
#define | ADC_VERID_RES_SHIFT (0U) |
#define | ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) |
#define | ADC_VERID_DIFFEN_MASK (0x2U) |
#define | ADC_VERID_DIFFEN_SHIFT (1U) |
#define | ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) |
#define | ADC_VERID_MVI_MASK (0x8U) |
#define | ADC_VERID_MVI_SHIFT (3U) |
#define | ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) |
#define | ADC_VERID_CSW_MASK (0x70U) |
#define | ADC_VERID_CSW_SHIFT (4U) |
#define | ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) |
#define | ADC_VERID_VR1RNGI_MASK (0x100U) |
#define | ADC_VERID_VR1RNGI_SHIFT (8U) |
#define | ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) |
#define | ADC_VERID_IADCKI_MASK (0x200U) |
#define | ADC_VERID_IADCKI_SHIFT (9U) |
#define | ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) |
#define | ADC_VERID_CALOFSI_MASK (0x400U) |
#define | ADC_VERID_CALOFSI_SHIFT (10U) |
#define | ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) |
#define | ADC_VERID_MINOR_MASK (0xFF0000U) |
#define | ADC_VERID_MINOR_SHIFT (16U) |
#define | ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) |
#define | ADC_VERID_MAJOR_MASK (0xFF000000U) |
#define | ADC_VERID_MAJOR_SHIFT (24U) |
#define | ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) |
#define | CMP_VERID_FEATURE_MASK (0xFFFFU) |
#define | CMP_VERID_FEATURE_SHIFT (0U) |
#define | CMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK) |
#define | CMP_VERID_MINOR_MASK (0xFF0000U) |
#define | CMP_VERID_MINOR_SHIFT (16U) |
#define | CMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK) |
#define | CMP_VERID_MAJOR_MASK (0xFF000000U) |
#define | CMP_VERID_MAJOR_SHIFT (24U) |
#define | CMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK) |
#define | FLEXIO_VERID_FEATURE_MASK (0xFFFFU) |
#define | FLEXIO_VERID_FEATURE_SHIFT (0U) |
#define | FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) |
#define | FLEXIO_VERID_MINOR_MASK (0xFF0000U) |
#define | FLEXIO_VERID_MINOR_SHIFT (16U) |
#define | FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) |
#define | FLEXIO_VERID_MAJOR_MASK (0xFF000000U) |
#define | FLEXIO_VERID_MAJOR_SHIFT (24U) |
#define | FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) |
#define | LPUART_VERID_FEATURE_MASK (0xFFFFU) |
#define | LPUART_VERID_FEATURE_SHIFT (0U) |
#define | LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) |
#define | LPUART_VERID_MINOR_MASK (0xFF0000U) |
#define | LPUART_VERID_MINOR_SHIFT (16U) |
#define | LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) |
#define | LPUART_VERID_MAJOR_MASK (0xFF000000U) |
#define | LPUART_VERID_MAJOR_SHIFT (24U) |
#define | LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) |
PARAM - Parameter Register | |
#define | ADC_PARAM_TRIG_NUM_MASK (0xFFU) |
#define | ADC_PARAM_TRIG_NUM_SHIFT (0U) |
#define | ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) |
#define | ADC_PARAM_FIFOSIZE_MASK (0xFF00U) |
#define | ADC_PARAM_FIFOSIZE_SHIFT (8U) |
#define | ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) |
#define | ADC_PARAM_CV_NUM_MASK (0xFF0000U) |
#define | ADC_PARAM_CV_NUM_SHIFT (16U) |
#define | ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) |
#define | ADC_PARAM_CMD_NUM_MASK (0xFF000000U) |
#define | ADC_PARAM_CMD_NUM_SHIFT (24U) |
#define | ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) |
#define | CMP_PARAM_PARAM_MASK (0xFFFFFFFFU) |
#define | CMP_PARAM_PARAM_SHIFT (0U) |
#define | CMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK) |
#define | DAC_PARAM_FIFOSZ_MASK (0x7U) |
#define | DAC_PARAM_FIFOSZ_SHIFT (0U) |
#define | DAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK) |
#define | EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU) |
#define | EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U) |
#define | EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK) |
#define | EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U) |
#define | EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U) |
#define | EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) |
#define | FLEXIO_PARAM_SHIFTER_MASK (0xFFU) |
#define | FLEXIO_PARAM_SHIFTER_SHIFT (0U) |
#define | FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) |
#define | FLEXIO_PARAM_TIMER_MASK (0xFF00U) |
#define | FLEXIO_PARAM_TIMER_SHIFT (8U) |
#define | FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) |
#define | FLEXIO_PARAM_PIN_MASK (0xFF0000U) |
#define | FLEXIO_PARAM_PIN_SHIFT (16U) |
#define | FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) |
#define | FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) |
#define | FLEXIO_PARAM_TRIGGER_SHIFT (24U) |
#define | FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) |
#define | LPUART_PARAM_TXFIFO_MASK (0xFFU) |
#define | LPUART_PARAM_TXFIFO_SHIFT (0U) |
#define | LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) |
#define | LPUART_PARAM_RXFIFO_MASK (0xFF00U) |
#define | LPUART_PARAM_RXFIFO_SHIFT (8U) |
#define | LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) |
CTRL - LPADC Control Register | |
#define | ADC_CTRL_ADCEN_MASK (0x1U) |
#define | ADC_CTRL_ADCEN_SHIFT (0U) |
#define | ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) |
#define | ADC_CTRL_RST_MASK (0x2U) |
#define | ADC_CTRL_RST_SHIFT (1U) |
#define | ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) |
#define | ADC_CTRL_DOZEN_MASK (0x4U) |
#define | ADC_CTRL_DOZEN_SHIFT (2U) |
#define | ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) |
#define | ADC_CTRL_TRIG_SRC_MASK (0x18U) |
#define | ADC_CTRL_TRIG_SRC_SHIFT (3U) |
#define | ADC_CTRL_TRIG_SRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIG_SRC_SHIFT)) & ADC_CTRL_TRIG_SRC_MASK) |
#define | ADC_CTRL_RSTFIFO_MASK (0x100U) |
#define | ADC_CTRL_RSTFIFO_SHIFT (8U) |
#define | ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK) |
STAT - LPADC Status Register | |
#define | ADC_STAT_RDY_MASK (0x1U) |
#define | ADC_STAT_RDY_SHIFT (0U) |
#define | ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK) |
#define | ADC_STAT_FOF_MASK (0x2U) |
#define | ADC_STAT_FOF_SHIFT (1U) |
#define | ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK) |
#define | ADC_STAT_ADC_ACTIVE_MASK (0x100U) |
#define | ADC_STAT_ADC_ACTIVE_SHIFT (8U) |
#define | ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) |
#define | ADC_STAT_TRGACT_MASK (0x70000U) |
#define | ADC_STAT_TRGACT_SHIFT (16U) |
#define | ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) |
#define | ADC_STAT_CMDACT_MASK (0xF000000U) |
#define | ADC_STAT_CMDACT_SHIFT (24U) |
#define | ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) |
IE - Interrupt Enable Register | |
#define | ADC_IE_FWMIE_MASK (0x1U) |
#define | ADC_IE_FWMIE_SHIFT (0U) |
#define | ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK) |
#define | ADC_IE_FOFIE_MASK (0x2U) |
#define | ADC_IE_FOFIE_SHIFT (1U) |
#define | ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK) |
DE - DMA Enable Register | |
#define | ADC_DE_FWMDE_MASK (0x1U) |
#define | ADC_DE_FWMDE_SHIFT (0U) |
#define | ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK) |
CFG - LPADC Configuration Register | |
#define | ADC_CFG_TPRICTRL_MASK (0x1U) |
#define | ADC_CFG_TPRICTRL_SHIFT (0U) |
#define | ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) |
#define | ADC_CFG_PWRSEL_MASK (0x30U) |
#define | ADC_CFG_PWRSEL_SHIFT (4U) |
#define | ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) |
#define | ADC_CFG_REFSEL_MASK (0xC0U) |
#define | ADC_CFG_REFSEL_SHIFT (6U) |
#define | ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) |
#define | ADC_CFG_PUDLY_MASK (0xFF0000U) |
#define | ADC_CFG_PUDLY_SHIFT (16U) |
#define | ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) |
#define | ADC_CFG_PWREN_MASK (0x10000000U) |
#define | ADC_CFG_PWREN_SHIFT (28U) |
#define | ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) |
PAUSE - LPADC Pause Register | |
#define | ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) |
#define | ADC_PAUSE_PAUSEDLY_SHIFT (0U) |
#define | ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) |
#define | ADC_PAUSE_PAUSEEN_MASK (0x80000000U) |
#define | ADC_PAUSE_PAUSEEN_SHIFT (31U) |
#define | ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) |
FCTRL - LPADC FIFO Control Register | |
#define | ADC_FCTRL_FCOUNT_MASK (0x1FU) |
#define | ADC_FCTRL_FCOUNT_SHIFT (0U) |
#define | ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) |
#define | ADC_FCTRL_FWMARK_MASK (0xF0000U) |
#define | ADC_FCTRL_FWMARK_SHIFT (16U) |
#define | ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) |
SWTRIG - Software Trigger Register | |
#define | ADC_SWTRIG_SWT0_MASK (0x1U) |
#define | ADC_SWTRIG_SWT0_SHIFT (0U) |
#define | ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) |
#define | ADC_SWTRIG_SWT1_MASK (0x2U) |
#define | ADC_SWTRIG_SWT1_SHIFT (1U) |
#define | ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) |
#define | ADC_SWTRIG_SWT2_MASK (0x4U) |
#define | ADC_SWTRIG_SWT2_SHIFT (2U) |
#define | ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) |
#define | ADC_SWTRIG_SWT3_MASK (0x8U) |
#define | ADC_SWTRIG_SWT3_SHIFT (3U) |
#define | ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) |
#define | ADC_SWTRIG_SWT4_MASK (0x10U) |
#define | ADC_SWTRIG_SWT4_SHIFT (4U) |
#define | ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) |
#define | ADC_SWTRIG_SWT5_MASK (0x20U) |
#define | ADC_SWTRIG_SWT5_SHIFT (5U) |
#define | ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) |
#define | ADC_SWTRIG_SWT6_MASK (0x40U) |
#define | ADC_SWTRIG_SWT6_SHIFT (6U) |
#define | ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) |
#define | ADC_SWTRIG_SWT7_MASK (0x80U) |
#define | ADC_SWTRIG_SWT7_SHIFT (7U) |
#define | ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) |
TCTRL - Trigger Control Register | |
#define | ADC_TCTRL_HTEN_MASK (0x1U) |
#define | ADC_TCTRL_HTEN_SHIFT (0U) |
#define | ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) |
#define | ADC_TCTRL_CMD_SEL_MASK (0x2U) |
#define | ADC_TCTRL_CMD_SEL_SHIFT (1U) |
#define | ADC_TCTRL_CMD_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_CMD_SEL_SHIFT)) & ADC_TCTRL_CMD_SEL_MASK) |
#define | ADC_TCTRL_TPRI_MASK (0x700U) |
#define | ADC_TCTRL_TPRI_SHIFT (8U) |
#define | ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) |
#define | ADC_TCTRL_TDLY_MASK (0xF0000U) |
#define | ADC_TCTRL_TDLY_SHIFT (16U) |
#define | ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) |
#define | ADC_TCTRL_TCMD_MASK (0xF000000U) |
#define | ADC_TCTRL_TCMD_SHIFT (24U) |
#define | ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) |
CMDL - LPADC Command Low Buffer Register | |
#define | ADC_CMDL_ADCH_MASK (0x1FU) |
#define | ADC_CMDL_ADCH_SHIFT (0U) |
#define | ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) |
#define | ADC_CMDL_ABSEL_MASK (0x20U) |
#define | ADC_CMDL_ABSEL_SHIFT (5U) |
#define | ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK) |
#define | ADC_CMDL_DIFF_MASK (0x40U) |
#define | ADC_CMDL_DIFF_SHIFT (6U) |
#define | ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK) |
#define | ADC_CMDL_CSCALE_MASK (0x2000U) |
#define | ADC_CMDL_CSCALE_SHIFT (13U) |
#define | ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK) |
CMDH - LPADC Command High Buffer Register | |
#define | ADC_CMDH_CMPEN_MASK (0x3U) |
#define | ADC_CMDH_CMPEN_SHIFT (0U) |
#define | ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) |
#define | ADC_CMDH_LWI_MASK (0x80U) |
#define | ADC_CMDH_LWI_SHIFT (7U) |
#define | ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) |
#define | ADC_CMDH_STS_MASK (0x700U) |
#define | ADC_CMDH_STS_SHIFT (8U) |
#define | ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) |
#define | ADC_CMDH_AVGS_MASK (0x7000U) |
#define | ADC_CMDH_AVGS_SHIFT (12U) |
#define | ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) |
#define | ADC_CMDH_LOOP_MASK (0xF0000U) |
#define | ADC_CMDH_LOOP_SHIFT (16U) |
#define | ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) |
#define | ADC_CMDH_NEXT_MASK (0xF000000U) |
#define | ADC_CMDH_NEXT_SHIFT (24U) |
#define | ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) |
CV - Compare Value Register | |
#define | ADC_CV_CVL_MASK (0xFFFFU) |
#define | ADC_CV_CVL_SHIFT (0U) |
#define | ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) |
#define | ADC_CV_CVH_MASK (0xFFFF0000U) |
#define | ADC_CV_CVH_SHIFT (16U) |
#define | ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) |
RESFIFO - LPADC Data Result FIFO Register | |
#define | ADC_RESFIFO_D_MASK (0xFFFFU) |
#define | ADC_RESFIFO_D_SHIFT (0U) |
#define | ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) |
#define | ADC_RESFIFO_TSRC_MASK (0x70000U) |
#define | ADC_RESFIFO_TSRC_SHIFT (16U) |
#define | ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) |
#define | ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) |
#define | ADC_RESFIFO_LOOPCNT_SHIFT (20U) |
#define | ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) |
#define | ADC_RESFIFO_CMDSRC_MASK (0xF000000U) |
#define | ADC_RESFIFO_CMDSRC_SHIFT (24U) |
#define | ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) |
#define | ADC_RESFIFO_VALID_MASK (0x80000000U) |
#define | ADC_RESFIFO_VALID_SHIFT (31U) |
#define | ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) |
CTRL - ADC_ETC Global Control Register | |
#define | ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) |
#define | ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) |
#define | ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) |
#define | ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) |
#define | ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) |
#define | ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) |
#define | ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) |
#define | ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) |
#define | ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) |
#define | ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) |
#define | ADC_ETC_CTRL_SOFTRST_SHIFT (31U) |
#define | ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) |
DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register | |
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) |
#define | ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) |
DONE2_3_ERR_IRQ - ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register | |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK (0x100U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT (8U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK (0x200U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT (9U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK (0x400U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT (10U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK (0x800U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT (11U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK (0x1000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT (12U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK (0x2000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT (13U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK (0x4000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT (14U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK (0x8000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT (15U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT (16U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT (17U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT (18U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT (19U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT (20U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT (21U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT (22U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT (23U) |
#define | ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK) |
DMA_CTRL - ETC DMA control Register | |
#define | ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) |
#define | ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) |
#define | ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) |
#define | ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) |
#define | ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) |
#define | ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) |
#define | ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) |
#define | ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) |
#define | ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) |
#define | ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) |
#define | ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) |
#define | ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) |
#define | ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) |
#define | ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) |
#define | ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) |
#define | ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) |
#define | ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) |
#define | ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) |
#define | ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) |
#define | ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) |
#define | ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) |
#define | ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) |
#define | ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) |
#define | ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) |
#define | ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) |
#define | ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) |
#define | ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) |
#define | ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) |
#define | ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) |
#define | ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) |
#define | ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) |
#define | ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) |
#define | ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) |
#define | ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) |
TRIGn_CTRL - ETC_TRIG Control Register | |
#define | ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) |
#define | ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) |
#define | ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) |
#define | ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) |
#define | ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) |
#define | ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) |
#define | ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) |
#define | ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) |
#define | ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) |
#define | ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) |
#define | ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) |
#define | ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) |
#define | ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) |
#define | ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) |
#define | ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) |
#define | ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK (0xFF000000U) |
#define | ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT (24U) |
#define | ADC_ETC_TRIGn_CTRL_CHAINx_DONE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT)) & ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK) |
TRIGn_COUNTER - ETC_TRIG Counter Register | |
#define | ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) |
#define | ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) |
#define | ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) |
#define | ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) |
#define | ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) |
#define | ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) |
TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register | |
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK (0x8000U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT (15U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK (0x80000000U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT (31U) |
#define | ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK) |
TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register | |
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK (0x8000U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT (15U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK (0x80000000U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT (31U) |
#define | ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK) |
TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register | |
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK (0x8000U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT (15U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK (0x80000000U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT (31U) |
#define | ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK) |
TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register | |
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK (0x8000U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT (15U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK (0x80000000U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT (31U) |
#define | ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK) |
TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register | |
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) |
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) |
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) |
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) |
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) |
#define | ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) |
TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register | |
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) |
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) |
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) |
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) |
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) |
#define | ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) |
TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register | |
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) |
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) |
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) |
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) |
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) |
#define | ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) |
TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register | |
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) |
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) |
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) |
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) |
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) |
#define | ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) |
PMU_LDO_LPSR_ANA - PMU_LDO_LPSR_ANA_REGISTER | |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK (0x1U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT (0U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK (0x4U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT (2U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK (0x8U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT (3U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK (0x10U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT (4U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK (0x20U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT (5U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK (0x40U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT (6U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK (0x100U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT (8U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK (0x80000U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT (19U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK (0x100000U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT (20U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK) |
PMU_LDO_LPSR_DIG_2 - PMU_LDO_LPSR_DIG_2_REGISTER | |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK (0x3U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT (0U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK) |
PMU_LDO_LPSR_DIG - PMU_LDO_LPSR_DIG_REGISTER | |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK (0x4U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT (2U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK (0x20U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT (5U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK (0x40U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT (6U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK (0x20000U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT (17U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK (0x40000U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT (18U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK (0x1F00000U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT (20U) |
#define | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK) |
PMU_LDO_SNVS_DIG - PMU_LDO_SNVS_DIG_REGISTER | |
#define | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK (0x1U) |
#define | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT (0U) |
#define | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK) |
#define | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK (0x2U) |
#define | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT (1U) |
#define | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK) |
#define | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK (0x4U) |
#define | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT (2U) |
#define | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK) |
MISC_DIFPROG - Chip Silicon Version Register | |
#define | ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT (0U) |
#define | ANADIG_MISC_MISC_DIFPROG_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK) |
VDDSOC_AI_CTRL - VDDSOC_AI_CTRL_REGISTER | |
#define | ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK (0xFFU) |
#define | ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK) |
#define | ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK (0x10000U) |
#define | ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT (16U) |
#define | ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK) |
VDDSOC_AI_WDATA - VDDSOC_AI_WDATA_REGISTER | |
#define | ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK) |
VDDSOC_AI_RDATA - VDDSOC_AI_RDATA_REGISTER | |
#define | ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK) |
VDDSOC2PLL_AI_CTRL_1G - VDDSOC2PLL_AI_CTRL_1G_REGISTER | |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK (0xFFU) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK (0x100U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT (8U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK (0x200U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT (9U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK (0x10000U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT (16U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK) |
VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G_REGISTER | |
#define | ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK) |
VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G_REGISTER | |
#define | ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK) |
VDDSOC2PLL_AI_CTRL_AUDIO - VDDSOC_AI_CTRL_AUDIO_REGISTER | |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK (0xFFU) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK (0x100U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT (8U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK (0x200U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT (9U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK (0x10000U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT (16U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK) |
VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC_AI_WDATA_AUDIO_REGISTER | |
#define | ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK) |
VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_REGISTER | |
#define | ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK) |
VDDSOC2PLL_AI_CTRL_VIDEO - VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER | |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK (0xFFU) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK (0x100U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT (8U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK (0x200U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT (9U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK (0x10000U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT (16U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK) |
VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER | |
#define | ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK) |
VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER | |
#define | ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT (0U) |
#define | ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK) |
VDDLPSR_AI_CTRL - VDDSOC_AI_CTRL_REGISTER | |
#define | ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK (0xFFU) |
#define | ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT (0U) |
#define | ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK) |
#define | ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK (0x10000U) |
#define | ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT (16U) |
#define | ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK) |
VDDLPSR_AI_WDATA - VDDLPSR_AI_WDATA_REGISTER | |
#define | ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT (0U) |
#define | ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK) |
VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP_REGISTER | |
#define | ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT (0U) |
#define | ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK) |
VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS_REGISTER | |
#define | ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT (0U) |
#define | ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK) |
VDDLPSR_AI400M_CTRL - VDDLPSR_AI400M_CTRL_REGISTER | |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK (0xFFU) |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT (0U) |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK) |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK (0x100U) |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT (8U) |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK) |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK (0x200U) |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT (9U) |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK) |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK (0x10000U) |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT (16U) |
#define | ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK) |
VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA_REGISTER | |
#define | ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT (0U) |
#define | ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK) |
VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA_REGISTER | |
#define | ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK (0xFFFFFFFFU) |
#define | ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT (0U) |
#define | ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK) |
OSC_48M_CTRL - 48MHz RCOSC Control Register | |
#define | ANADIG_OSC_OSC_48M_CTRL_TEN_MASK (0x2U) |
#define | ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT (1U) |
#define | ANADIG_OSC_OSC_48M_CTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TEN_MASK) |
#define | ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK (0x1000000U) |
#define | ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT (24U) |
#define | ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK) |
#define | ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK (0x40000000U) |
#define | ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT (30U) |
#define | ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK) |
#define | ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK (0x80000000U) |
#define | ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT (31U) |
#define | ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK) |
OSC_24M_CTRL - 24MHz OSC Control Register | |
#define | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK (0x1U) |
#define | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT (0U) |
#define | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK) |
#define | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK (0x2U) |
#define | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT (1U) |
#define | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK) |
#define | ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK (0x4U) |
#define | ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT (2U) |
#define | ANADIG_OSC_OSC_24M_CTRL_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK (0x8U) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT (3U) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK (0x10U) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT (4U) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK (0x80U) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT (7U) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK (0x40000000U) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT (30U) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK (0x80000000U) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT (31U) |
#define | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK) |
OSC_400M_CTRL0 - 400MHz RCOSC Control0 Register | |
#define | ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK (0x80000000U) |
#define | ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT (31U) |
#define | ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK) |
OSC_400M_CTRL1 - 400MHz RCOSC Control1 Register | |
#define | ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK (0x1U) |
#define | ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT (0U) |
#define | ANADIG_OSC_OSC_400M_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK) |
#define | ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK (0x2U) |
#define | ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT (1U) |
#define | ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK) |
#define | ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK (0x80000000U) |
#define | ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT (31U) |
#define | ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK) |
OSC_400M_CTRL2 - 400MHz RCOSC Control2 Register | |
#define | ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK (0x1U) |
#define | ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT (0U) |
#define | ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK) |
#define | ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK (0x400U) |
#define | ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT (10U) |
#define | ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK) |
#define | ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) |
#define | ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U) |
#define | ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK) |
OSC_16M_CTRL - 16MHz RCOSC Control Register | |
#define | ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK (0x2U) |
#define | ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT (1U) |
#define | ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK) |
#define | ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK (0x8U) |
#define | ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT (3U) |
#define | ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK) |
#define | ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK (0x100U) |
#define | ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT (8U) |
#define | ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK) |
#define | ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK (0x80000000U) |
#define | ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT (31U) |
#define | ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK) |
ARM_PLL_CTRL - ARM_PLL_CTRL_REGISTER | |
#define | ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK (0xFFU) |
#define | ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT (0U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) |
#define | ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK (0x1000U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT (12U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK) |
#define | ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK (0x2000U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT (13U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK (0x4000U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT (14U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) |
#define | ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK (0x18000U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT (15U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) |
#define | ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK (0x20000U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT (17U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK (0x20000000U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT (29U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK (0x40000000U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT (30U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK (0x80000000U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT (31U) |
#define | ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK) |
SYS_PLL3_CTRL - SYS_PLL3_CTRL_REGISTER | |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK (0x8U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT (3U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK (0x10U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT (4U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK (0x800U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT (11U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK (0x2000U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT (13U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK (0x10000U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT (16U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK (0x200000U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT (21U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK (0x10000000U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT (28U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK (0x20000000U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT (29U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK (0x40000000U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT (30U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK (0x80000000U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT (31U) |
#define | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK) |
SYS_PLL3_UPDATE - SYS_PLL3_UPDATE_REGISTER | |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK (0x2U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT (1U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK (0x4U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT (2U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK (0x8U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT (3U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK (0x10U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT (4U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK (0x80U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT (7U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U) |
#define | ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK) |
SYS_PLL3_PFD - SYS_PLL3_PFD_REGISTER | |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK (0x3FU) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT (0U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK (0x40U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT (6U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK (0x3F00U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT (8U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK (0x4000U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT (14U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK (0x3F0000U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT (16U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK (0x400000U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT (22U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK (0x3F000000U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT (24U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK (0x40000000U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT (30U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U) |
#define | ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK) |
SYS_PLL2_CTRL - SYS_PLL2_CTRL_REGISTER | |
#define | ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK (0x8U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT (3U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK (0x800U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT (11U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK (0x2000U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT (13U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK (0x10000U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT (16U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK (0x20000U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT (17U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK (0x40000U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT (18U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK (0x80000U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT (19U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK (0x800000U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT (23U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK (0x20000000U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT (29U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK (0x40000000U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT (30U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK (0x80000000U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT (31U) |
#define | ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK) |
SYS_PLL2_UPDATE - SYS_PLL2_UPDATE_REGISTER | |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK (0x2U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT (1U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK (0x4U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT (2U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK (0x8U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT (3U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK (0x10U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT (4U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U) |
#define | ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK) |
SYS_PLL2_SS - SYS_PLL2_SS_REGISTER | |
#define | ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) |
#define | ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT (0U) |
#define | ANADIG_PLL_SYS_PLL2_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK) |
#define | ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK (0x8000U) |
#define | ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT (15U) |
#define | ANADIG_PLL_SYS_PLL2_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_SS_STOP_MASK (0xFFFF0000U) |
#define | ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT (16U) |
#define | ANADIG_PLL_SYS_PLL2_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STOP_MASK) |
SYS_PLL2_PFD - SYS_PLL2_PFD_REGISTER | |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK (0x3FU) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT (0U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK (0x40U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT (6U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK (0x3F00U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT (8U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK (0x4000U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT (14U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK (0x3F0000U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT (16U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK (0x400000U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT (22U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK (0x3F000000U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT (24U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK (0x40000000U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT (30U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U) |
#define | ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK) |
SYS_PLL2_MFD - SYS_PLL2_MFD_REGISTER | |
#define | ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK (0x3FFFFFFFU) |
#define | ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT (0U) |
#define | ANADIG_PLL_SYS_PLL2_MFD_MFD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK) |
SYS_PLL1_SS - SYS_PLL1_SS_REGISTER | |
#define | ANADIG_PLL_SYS_PLL1_SS_STEP_MASK (0x7FFFU) |
#define | ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT (0U) |
#define | ANADIG_PLL_SYS_PLL1_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STEP_MASK) |
#define | ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK (0x8000U) |
#define | ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT (15U) |
#define | ANADIG_PLL_SYS_PLL1_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL1_SS_STOP_MASK (0xFFFF0000U) |
#define | ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT (16U) |
#define | ANADIG_PLL_SYS_PLL1_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STOP_MASK) |
SYS_PLL1_CTRL - SYS_PLL1_CTRL_REGISTER | |
#define | ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK (0x2000U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT (13U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK (0x4000U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT (14U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK (0x2000000U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT (25U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK (0x4000000U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT (26U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK (0x8000000U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT (27U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK (0x10000000U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT (28U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK (0x20000000U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT (29U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK (0x40000000U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT (30U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK (0x80000000U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT (31U) |
#define | ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK) |
SYS_PLL1_DENOMINATOR - SYS_PLL1_DENOMINATOR_REGISTER | |
#define | ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) |
#define | ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT (0U) |
#define | ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK) |
SYS_PLL1_NUMERATOR - SYS_PLL1_NUMERATOR_REGISTER | |
#define | ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK (0x3FFFFFFFU) |
#define | ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT (0U) |
#define | ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK) |
SYS_PLL1_DIV_SELECT - SYS_PLL1_DIV_SELECT_REGISTER | |
#define | ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK (0x7FU) |
#define | ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT (0U) |
#define | ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK) |
PLL_AUDIO_CTRL - PLL_AUDIO_CTRL_REGISTER | |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK (0x2000U) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT (13U) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK (0x4000U) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT (14U) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK (0x20000000U) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT (29U) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK (0x40000000U) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT (30U) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK (0x80000000U) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT (31U) |
#define | ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK) |
PLL_AUDIO_SS - PLL_AUDIO_SS_REGISTER | |
#define | ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK (0x7FFFU) |
#define | ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT (0U) |
#define | ANADIG_PLL_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK) |
#define | ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK (0x8000U) |
#define | ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT (15U) |
#define | ANADIG_PLL_PLL_AUDIO_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK) |
#define | ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK (0xFFFF0000U) |
#define | ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT (16U) |
#define | ANADIG_PLL_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK) |
PLL_AUDIO_DENOMINATOR - PLL_AUDIO_DENOMINATOR_REGISTER | |
#define | ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) |
#define | ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT (0U) |
#define | ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK) |
PLL_AUDIO_NUMERATOR - PLL_AUDIO_NUMERATOR_REGISTER | |
#define | ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK (0x3FFFFFFFU) |
#define | ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT (0U) |
#define | ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK) |
PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT_REGISTER | |
#define | ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) |
#define | ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT (0U) |
#define | ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK) |
PLL_VIDEO_CTRL - PLL_VIDEO_CTRL_REGISTER | |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK (0x2000U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT (13U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK (0x4000U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT (14U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK (0x1000000U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT (24U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK (0x20000000U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT (29U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK (0x40000000U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT (30U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK (0x80000000U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT (31U) |
#define | ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK) |
PLL_VIDEO_SS - PLL_VIDEO_SS_REGISTER | |
#define | ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK (0x7FFFU) |
#define | ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT (0U) |
#define | ANADIG_PLL_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK) |
#define | ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK (0x8000U) |
#define | ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT (15U) |
#define | ANADIG_PLL_PLL_VIDEO_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK) |
#define | ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK (0xFFFF0000U) |
#define | ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT (16U) |
#define | ANADIG_PLL_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK) |
PLL_VIDEO_DENOMINATOR - PLL_VIDEO_DENOMINATOR_REGISTER | |
#define | ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) |
#define | ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT (0U) |
#define | ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK) |
PLL_VIDEO_NUMERATOR - PLL_VIDEO_NUMERATOR_REGISTER | |
#define | ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK (0x3FFFFFFFU) |
#define | ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT (0U) |
#define | ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK) |
PLL_VIDEO_DIV_SELECT - PLL_VIDEO_DIV_SELECT_REGISTER | |
#define | ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK (0x7FU) |
#define | ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT (0U) |
#define | ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK) |
PMU_LDO_PLL - PMU_LDO_PLL_REGISTER | |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK (0x1U) |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT (0U) |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK) |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK (0x2U) |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT (1U) |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK) |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK (0x10000U) |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT (16U) |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK) |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK (0x40000000U) |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT (30U) |
#define | ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK) |
PMU_BIAS_CTRL - PMU_BIAS_CTRL_REGISTER | |
#define | ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK (0x1FFFU) |
#define | ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT (0U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK) |
#define | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK (0x4000U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT (14U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK) |
PMU_BIAS_CTRL2 - PMU_BIAS_CTRL2_REGISTER | |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK (0x3FEU) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT (1U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK (0x1C00U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT (10U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK (0x1FE000U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT (13U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK (0x400000U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT (22U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK (0x800000U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT (23U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK (0x1000000U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT (24U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK (0x2000000U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT (25U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK (0x4000000U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT (26U) |
#define | ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) |
PMU_REF_CTRL - PMU_REF_CTRL_REGISTER | |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK (0x1U) |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT (0U) |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK) |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK (0x2U) |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT (1U) |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK) |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK (0x4U) |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT (2U) |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK) |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK (0x8U) |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT (3U) |
#define | ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK) |
#define | ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK (0x10U) |
#define | ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT (4U) |
#define | ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK) |
PMU_POWER_DETECT_CTRL - PMU_POWER_DETECT_CTRL_REGISTER | |
#define | ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK (0x100U) |
#define | ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT (8U) |
#define | ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT)) & ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK) |
LDO_PLL_ENABLE_SP - LDO_PLL_ENABLE_SP_REGISTER | |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK) |
LDO_LPSR_ANA_ENABLE_SP - LDO_LPSR_ANA_ENABLE_SP_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK) |
LDO_LPSR_ANA_LP_MODE_SP - LDO_LPSR_ANA_LP_MODE_SP_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK (0x4U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT (2U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK (0x8U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT (3U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK (0x10U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT (4U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK (0x20U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT (5U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK (0x40U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT (6U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK (0x80U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT (7U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK (0x100U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK (0x200U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT (9U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK (0x400U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT (10U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK (0x800U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT (11U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK (0x1000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT (12U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK (0x2000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT (13U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK (0x4000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT (14U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK (0x8000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT (15U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK) |
LDO_LPSR_ANA_TRACKING_EN_SP - LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK) |
LDO_LPSR_ANA_BYPASS_EN_SP - LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK) |
LDO_LPSR_ANA_STBY_EN_SP - LDO_LPSR_ANA_STBY_EN_SP_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) |
LDO_LPSR_DIG_ENABLE_SP - LDO_LPSR_DIG_ENABLE_SP_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK) |
LDO_LPSR_DIG_TRG_SP0 - LDO_LPSR_DIG_TRG_SP0_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK (0xFFU) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK (0xFF00U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK (0xFF0000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT (16U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK (0xFF000000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT (24U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK) |
LDO_LPSR_DIG_TRG_SP1 - LDO_LPSR_DIG_TRG_SP1_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK (0xFFU) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK (0xFF00U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK (0xFF0000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT (16U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK (0xFF000000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT (24U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK) |
LDO_LPSR_DIG_TRG_SP2 - LDO_LPSR_DIG_TRG_SP2_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK (0xFFU) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK (0xFF00U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK (0xFF0000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT (16U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK (0xFF000000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT (24U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK) |
LDO_LPSR_DIG_TRG_SP3 - LDO_LPSR_DIG_TRG_SP3_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK (0xFFU) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK (0xFF00U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK (0xFF0000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT (16U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK (0xFF000000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT (24U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK) |
LDO_LPSR_DIG_LP_MODE_SP - LDO_LPSR_DIG_LP_MODE_SP_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK) |
LDO_LPSR_DIG_TRACKING_EN_SP - LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK) |
LDO_LPSR_DIG_BYPASS_EN_SP - LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK) |
LDO_LPSR_DIG_STBY_EN_SP - LDO_LPSR_DIG_STBY_EN_SP_REGISTER | |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) |
BANDGAP_ENABLE_SP - BANDGAP_ENABLE_SP_REGISTER | |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK) |
RBB_SOC_ENABLE_SP - RBB_SOC_ENABLE_SP_REGISTER | |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK) |
RBB_LPSR_ENABLE_SP - RBB_LPSR_ENABLE_SP_REGISTER | |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK) |
BANDGAP_STBY_EN_SP - BANDGAP_STBY_EN_SP_REGISTER | |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) |
PLL_LDO_STBY_EN_SP - PLL_LDO_STBY_EN_SP_REGISTER | |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) |
RBB_SOC_STBY_EN_SP - RBB_SOC_STBY_EN_SP_REGISTER | |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) |
RBB_LPSR_STBY_EN_SP - RBB_LPSR_STBY_EN_SP_REGISTER | |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) |
#define | ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) |
RBB_LPSR_CONFIGURE - RBB_LPSR_CONFIGURE_REGISTER | |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK (0xFU) |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT (0U) |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK) |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK (0xF0U) |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT (4U) |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK) |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U) |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U) |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK) |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U) |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U) |
#define | ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK) |
RBB_SOC_CONFIGURE - RBB_SOC_CONFIGURE_REGISTER | |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK (0xFU) |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT (0U) |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK) |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK (0xF0U) |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT (4U) |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK) |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U) |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U) |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK) |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U) |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U) |
#define | ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK) |
REFTOP_OTP_TRIM_VALUE - REFTOP_OTP_TRIM_VALUE_REGISTER | |
#define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK (0x7U) |
#define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT (0U) |
#define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK) |
#define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK (0x38U) |
#define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT (3U) |
#define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK) |
#define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK (0x40U) |
#define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT (6U) |
#define | ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK) |
LPSR_1P8_LDO_OTP_TRIM_VALUE - LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER | |
#define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK (0x3U) |
#define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT (0U) |
#define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK) |
#define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK (0x4U) |
#define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT (2U) |
#define | ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK) |
TEMPSENSOR - Tempsensor Register | |
#define | ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK (0x8000U) |
#define | ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT (15U) |
#define | ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK) |
#define | ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK (0x10000U) |
#define | ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT (16U) |
#define | ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK) |
TEMPSNS_OTP_TRIM_VALUE - TEMPSNS_OTP_TRIM_VALUE_REGISTER | |
#define | ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK (0x3FFC00U) |
#define | ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT (10U) |
#define | ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK) |
BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn | |
#define | AOI_BFCRT01_PT1_DC_MASK (0x3U) |
#define | AOI_BFCRT01_PT1_DC_SHIFT (0U) |
#define | AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) |
#define | AOI_BFCRT01_PT1_CC_MASK (0xCU) |
#define | AOI_BFCRT01_PT1_CC_SHIFT (2U) |
#define | AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) |
#define | AOI_BFCRT01_PT1_BC_MASK (0x30U) |
#define | AOI_BFCRT01_PT1_BC_SHIFT (4U) |
#define | AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) |
#define | AOI_BFCRT01_PT1_AC_MASK (0xC0U) |
#define | AOI_BFCRT01_PT1_AC_SHIFT (6U) |
#define | AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) |
#define | AOI_BFCRT01_PT0_DC_MASK (0x300U) |
#define | AOI_BFCRT01_PT0_DC_SHIFT (8U) |
#define | AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) |
#define | AOI_BFCRT01_PT0_CC_MASK (0xC00U) |
#define | AOI_BFCRT01_PT0_CC_SHIFT (10U) |
#define | AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) |
#define | AOI_BFCRT01_PT0_BC_MASK (0x3000U) |
#define | AOI_BFCRT01_PT0_BC_SHIFT (12U) |
#define | AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) |
#define | AOI_BFCRT01_PT0_AC_MASK (0xC000U) |
#define | AOI_BFCRT01_PT0_AC_SHIFT (14U) |
#define | AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) |
BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn | |
#define | AOI_BFCRT23_PT3_DC_MASK (0x3U) |
#define | AOI_BFCRT23_PT3_DC_SHIFT (0U) |
#define | AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) |
#define | AOI_BFCRT23_PT3_CC_MASK (0xCU) |
#define | AOI_BFCRT23_PT3_CC_SHIFT (2U) |
#define | AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) |
#define | AOI_BFCRT23_PT3_BC_MASK (0x30U) |
#define | AOI_BFCRT23_PT3_BC_SHIFT (4U) |
#define | AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) |
#define | AOI_BFCRT23_PT3_AC_MASK (0xC0U) |
#define | AOI_BFCRT23_PT3_AC_SHIFT (6U) |
#define | AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) |
#define | AOI_BFCRT23_PT2_DC_MASK (0x300U) |
#define | AOI_BFCRT23_PT2_DC_SHIFT (8U) |
#define | AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) |
#define | AOI_BFCRT23_PT2_CC_MASK (0xC00U) |
#define | AOI_BFCRT23_PT2_CC_SHIFT (10U) |
#define | AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) |
#define | AOI_BFCRT23_PT2_BC_MASK (0x3000U) |
#define | AOI_BFCRT23_PT2_BC_SHIFT (12U) |
#define | AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) |
#define | AOI_BFCRT23_PT2_AC_MASK (0xC000U) |
#define | AOI_BFCRT23_PT2_AC_SHIFT (14U) |
#define | AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) |
ASRCTR - ASRC Control Register | |
#define | ASRC_ASRCTR_ASRCEN_MASK (0x1U) |
#define | ASRC_ASRCTR_ASRCEN_SHIFT (0U) |
#define | ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK) |
#define | ASRC_ASRCTR_ASREA_MASK (0x2U) |
#define | ASRC_ASRCTR_ASREA_SHIFT (1U) |
#define | ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK) |
#define | ASRC_ASRCTR_ASREB_MASK (0x4U) |
#define | ASRC_ASRCTR_ASREB_SHIFT (2U) |
#define | ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK) |
#define | ASRC_ASRCTR_ASREC_MASK (0x8U) |
#define | ASRC_ASRCTR_ASREC_SHIFT (3U) |
#define | ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK) |
#define | ASRC_ASRCTR_SRST_MASK (0x10U) |
#define | ASRC_ASRCTR_SRST_SHIFT (4U) |
#define | ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK) |
#define | ASRC_ASRCTR_IDRA_MASK (0x2000U) |
#define | ASRC_ASRCTR_IDRA_SHIFT (13U) |
#define | ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK) |
#define | ASRC_ASRCTR_USRA_MASK (0x4000U) |
#define | ASRC_ASRCTR_USRA_SHIFT (14U) |
#define | ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK) |
#define | ASRC_ASRCTR_IDRB_MASK (0x8000U) |
#define | ASRC_ASRCTR_IDRB_SHIFT (15U) |
#define | ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK) |
#define | ASRC_ASRCTR_USRB_MASK (0x10000U) |
#define | ASRC_ASRCTR_USRB_SHIFT (16U) |
#define | ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK) |
#define | ASRC_ASRCTR_IDRC_MASK (0x20000U) |
#define | ASRC_ASRCTR_IDRC_SHIFT (17U) |
#define | ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK) |
#define | ASRC_ASRCTR_USRC_MASK (0x40000U) |
#define | ASRC_ASRCTR_USRC_SHIFT (18U) |
#define | ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK) |
#define | ASRC_ASRCTR_ATSA_MASK (0x100000U) |
#define | ASRC_ASRCTR_ATSA_SHIFT (20U) |
#define | ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK) |
#define | ASRC_ASRCTR_ATSB_MASK (0x200000U) |
#define | ASRC_ASRCTR_ATSB_SHIFT (21U) |
#define | ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK) |
#define | ASRC_ASRCTR_ATSC_MASK (0x400000U) |
#define | ASRC_ASRCTR_ATSC_SHIFT (22U) |
#define | ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK) |
ASRIER - ASRC Interrupt Enable Register | |
#define | ASRC_ASRIER_ADIEA_MASK (0x1U) |
#define | ASRC_ASRIER_ADIEA_SHIFT (0U) |
#define | ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK) |
#define | ASRC_ASRIER_ADIEB_MASK (0x2U) |
#define | ASRC_ASRIER_ADIEB_SHIFT (1U) |
#define | ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK) |
#define | ASRC_ASRIER_ADIEC_MASK (0x4U) |
#define | ASRC_ASRIER_ADIEC_SHIFT (2U) |
#define | ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK) |
#define | ASRC_ASRIER_ADOEA_MASK (0x8U) |
#define | ASRC_ASRIER_ADOEA_SHIFT (3U) |
#define | ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK) |
#define | ASRC_ASRIER_ADOEB_MASK (0x10U) |
#define | ASRC_ASRIER_ADOEB_SHIFT (4U) |
#define | ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK) |
#define | ASRC_ASRIER_ADOEC_MASK (0x20U) |
#define | ASRC_ASRIER_ADOEC_SHIFT (5U) |
#define | ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK) |
#define | ASRC_ASRIER_AOLIE_MASK (0x40U) |
#define | ASRC_ASRIER_AOLIE_SHIFT (6U) |
#define | ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK) |
#define | ASRC_ASRIER_AFPWE_MASK (0x80U) |
#define | ASRC_ASRIER_AFPWE_SHIFT (7U) |
#define | ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK) |
ASRCNCR - ASRC Channel Number Configuration Register | |
#define | ASRC_ASRCNCR_ANCA_MASK (0xFU) |
#define | ASRC_ASRCNCR_ANCA_SHIFT (0U) |
#define | ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK) |
#define | ASRC_ASRCNCR_ANCB_MASK (0xF0U) |
#define | ASRC_ASRCNCR_ANCB_SHIFT (4U) |
#define | ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK) |
#define | ASRC_ASRCNCR_ANCC_MASK (0xF00U) |
#define | ASRC_ASRCNCR_ANCC_SHIFT (8U) |
#define | ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK) |
ASRCFG - ASRC Filter Configuration Status Register | |
#define | ASRC_ASRCFG_PREMODA_MASK (0xC0U) |
#define | ASRC_ASRCFG_PREMODA_SHIFT (6U) |
#define | ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK) |
#define | ASRC_ASRCFG_POSTMODA_MASK (0x300U) |
#define | ASRC_ASRCFG_POSTMODA_SHIFT (8U) |
#define | ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK) |
#define | ASRC_ASRCFG_PREMODB_MASK (0xC00U) |
#define | ASRC_ASRCFG_PREMODB_SHIFT (10U) |
#define | ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK) |
#define | ASRC_ASRCFG_POSTMODB_MASK (0x3000U) |
#define | ASRC_ASRCFG_POSTMODB_SHIFT (12U) |
#define | ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK) |
#define | ASRC_ASRCFG_PREMODC_MASK (0xC000U) |
#define | ASRC_ASRCFG_PREMODC_SHIFT (14U) |
#define | ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK) |
#define | ASRC_ASRCFG_POSTMODC_MASK (0x30000U) |
#define | ASRC_ASRCFG_POSTMODC_SHIFT (16U) |
#define | ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK) |
#define | ASRC_ASRCFG_NDPRA_MASK (0x40000U) |
#define | ASRC_ASRCFG_NDPRA_SHIFT (18U) |
#define | ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK) |
#define | ASRC_ASRCFG_NDPRB_MASK (0x80000U) |
#define | ASRC_ASRCFG_NDPRB_SHIFT (19U) |
#define | ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK) |
#define | ASRC_ASRCFG_NDPRC_MASK (0x100000U) |
#define | ASRC_ASRCFG_NDPRC_SHIFT (20U) |
#define | ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK) |
#define | ASRC_ASRCFG_INIRQA_MASK (0x200000U) |
#define | ASRC_ASRCFG_INIRQA_SHIFT (21U) |
#define | ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK) |
#define | ASRC_ASRCFG_INIRQB_MASK (0x400000U) |
#define | ASRC_ASRCFG_INIRQB_SHIFT (22U) |
#define | ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK) |
#define | ASRC_ASRCFG_INIRQC_MASK (0x800000U) |
#define | ASRC_ASRCFG_INIRQC_SHIFT (23U) |
#define | ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK) |
ASRCSR - ASRC Clock Source Register | |
#define | ASRC_ASRCSR_AICSA_MASK (0xFU) |
#define | ASRC_ASRCSR_AICSA_SHIFT (0U) |
#define | ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK) |
#define | ASRC_ASRCSR_AICSB_MASK (0xF0U) |
#define | ASRC_ASRCSR_AICSB_SHIFT (4U) |
#define | ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK) |
#define | ASRC_ASRCSR_AICSC_MASK (0xF00U) |
#define | ASRC_ASRCSR_AICSC_SHIFT (8U) |
#define | ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK) |
#define | ASRC_ASRCSR_AOCSA_MASK (0xF000U) |
#define | ASRC_ASRCSR_AOCSA_SHIFT (12U) |
#define | ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK) |
#define | ASRC_ASRCSR_AOCSB_MASK (0xF0000U) |
#define | ASRC_ASRCSR_AOCSB_SHIFT (16U) |
#define | ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK) |
#define | ASRC_ASRCSR_AOCSC_MASK (0xF00000U) |
#define | ASRC_ASRCSR_AOCSC_SHIFT (20U) |
#define | ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK) |
ASRCDR1 - ASRC Clock Divider Register 1 | |
#define | ASRC_ASRCDR1_AICPA_MASK (0x7U) |
#define | ASRC_ASRCDR1_AICPA_SHIFT (0U) |
#define | ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK) |
#define | ASRC_ASRCDR1_AICDA_MASK (0x38U) |
#define | ASRC_ASRCDR1_AICDA_SHIFT (3U) |
#define | ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK) |
#define | ASRC_ASRCDR1_AICPB_MASK (0x1C0U) |
#define | ASRC_ASRCDR1_AICPB_SHIFT (6U) |
#define | ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK) |
#define | ASRC_ASRCDR1_AICDB_MASK (0xE00U) |
#define | ASRC_ASRCDR1_AICDB_SHIFT (9U) |
#define | ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK) |
#define | ASRC_ASRCDR1_AOCPA_MASK (0x7000U) |
#define | ASRC_ASRCDR1_AOCPA_SHIFT (12U) |
#define | ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK) |
#define | ASRC_ASRCDR1_AOCDA_MASK (0x38000U) |
#define | ASRC_ASRCDR1_AOCDA_SHIFT (15U) |
#define | ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK) |
#define | ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U) |
#define | ASRC_ASRCDR1_AOCPB_SHIFT (18U) |
#define | ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK) |
#define | ASRC_ASRCDR1_AOCDB_MASK (0xE00000U) |
#define | ASRC_ASRCDR1_AOCDB_SHIFT (21U) |
#define | ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK) |
ASRCDR2 - ASRC Clock Divider Register 2 | |
#define | ASRC_ASRCDR2_AICPC_MASK (0x7U) |
#define | ASRC_ASRCDR2_AICPC_SHIFT (0U) |
#define | ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK) |
#define | ASRC_ASRCDR2_AICDC_MASK (0x38U) |
#define | ASRC_ASRCDR2_AICDC_SHIFT (3U) |
#define | ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK) |
#define | ASRC_ASRCDR2_AOCPC_MASK (0x1C0U) |
#define | ASRC_ASRCDR2_AOCPC_SHIFT (6U) |
#define | ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK) |
#define | ASRC_ASRCDR2_AOCDC_MASK (0xE00U) |
#define | ASRC_ASRCDR2_AOCDC_SHIFT (9U) |
#define | ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK) |
ASRSTR - ASRC Status Register | |
#define | ASRC_ASRSTR_AIDEA_MASK (0x1U) |
#define | ASRC_ASRSTR_AIDEA_SHIFT (0U) |
#define | ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK) |
#define | ASRC_ASRSTR_AIDEB_MASK (0x2U) |
#define | ASRC_ASRSTR_AIDEB_SHIFT (1U) |
#define | ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK) |
#define | ASRC_ASRSTR_AIDEC_MASK (0x4U) |
#define | ASRC_ASRSTR_AIDEC_SHIFT (2U) |
#define | ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK) |
#define | ASRC_ASRSTR_AODFA_MASK (0x8U) |
#define | ASRC_ASRSTR_AODFA_SHIFT (3U) |
#define | ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK) |
#define | ASRC_ASRSTR_AODFB_MASK (0x10U) |
#define | ASRC_ASRSTR_AODFB_SHIFT (4U) |
#define | ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK) |
#define | ASRC_ASRSTR_AODFC_MASK (0x20U) |
#define | ASRC_ASRSTR_AODFC_SHIFT (5U) |
#define | ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK) |
#define | ASRC_ASRSTR_AOLE_MASK (0x40U) |
#define | ASRC_ASRSTR_AOLE_SHIFT (6U) |
#define | ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK) |
#define | ASRC_ASRSTR_FPWT_MASK (0x80U) |
#define | ASRC_ASRSTR_FPWT_SHIFT (7U) |
#define | ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK) |
#define | ASRC_ASRSTR_AIDUA_MASK (0x100U) |
#define | ASRC_ASRSTR_AIDUA_SHIFT (8U) |
#define | ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK) |
#define | ASRC_ASRSTR_AIDUB_MASK (0x200U) |
#define | ASRC_ASRSTR_AIDUB_SHIFT (9U) |
#define | ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK) |
#define | ASRC_ASRSTR_AIDUC_MASK (0x400U) |
#define | ASRC_ASRSTR_AIDUC_SHIFT (10U) |
#define | ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK) |
#define | ASRC_ASRSTR_AODOA_MASK (0x800U) |
#define | ASRC_ASRSTR_AODOA_SHIFT (11U) |
#define | ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK) |
#define | ASRC_ASRSTR_AODOB_MASK (0x1000U) |
#define | ASRC_ASRSTR_AODOB_SHIFT (12U) |
#define | ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK) |
#define | ASRC_ASRSTR_AODOC_MASK (0x2000U) |
#define | ASRC_ASRSTR_AODOC_SHIFT (13U) |
#define | ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK) |
#define | ASRC_ASRSTR_AIOLA_MASK (0x4000U) |
#define | ASRC_ASRSTR_AIOLA_SHIFT (14U) |
#define | ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK) |
#define | ASRC_ASRSTR_AIOLB_MASK (0x8000U) |
#define | ASRC_ASRSTR_AIOLB_SHIFT (15U) |
#define | ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK) |
#define | ASRC_ASRSTR_AIOLC_MASK (0x10000U) |
#define | ASRC_ASRSTR_AIOLC_SHIFT (16U) |
#define | ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK) |
#define | ASRC_ASRSTR_AOOLA_MASK (0x20000U) |
#define | ASRC_ASRSTR_AOOLA_SHIFT (17U) |
#define | ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK) |
#define | ASRC_ASRSTR_AOOLB_MASK (0x40000U) |
#define | ASRC_ASRSTR_AOOLB_SHIFT (18U) |
#define | ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK) |
#define | ASRC_ASRSTR_AOOLC_MASK (0x80000U) |
#define | ASRC_ASRSTR_AOOLC_SHIFT (19U) |
#define | ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK) |
#define | ASRC_ASRSTR_ATQOL_MASK (0x100000U) |
#define | ASRC_ASRSTR_ATQOL_SHIFT (20U) |
#define | ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK) |
#define | ASRC_ASRSTR_DSLCNT_MASK (0x200000U) |
#define | ASRC_ASRSTR_DSLCNT_SHIFT (21U) |
#define | ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK) |
ASRPM - ASRC Parameter Register n | |
#define | ASRC_ASRPM_PARAMETER_VALUE_MASK (0xFFFFFFU) |
#define | ASRC_ASRPM_PARAMETER_VALUE_SHIFT (0U) |
#define | ASRC_ASRPM_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK) |
ASRTFR1 - ASRC Task Queue FIFO Register 1 | |
#define | ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U) |
#define | ASRC_ASRTFR1_TF_BASE_SHIFT (6U) |
#define | ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK) |
#define | ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U) |
#define | ASRC_ASRTFR1_TF_FILL_SHIFT (13U) |
#define | ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK) |
ASRCCR - ASRC Channel Counter Register | |
#define | ASRC_ASRCCR_ACIA_MASK (0xFU) |
#define | ASRC_ASRCCR_ACIA_SHIFT (0U) |
#define | ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK) |
#define | ASRC_ASRCCR_ACIB_MASK (0xF0U) |
#define | ASRC_ASRCCR_ACIB_SHIFT (4U) |
#define | ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK) |
#define | ASRC_ASRCCR_ACIC_MASK (0xF00U) |
#define | ASRC_ASRCCR_ACIC_SHIFT (8U) |
#define | ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK) |
#define | ASRC_ASRCCR_ACOA_MASK (0xF000U) |
#define | ASRC_ASRCCR_ACOA_SHIFT (12U) |
#define | ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK) |
#define | ASRC_ASRCCR_ACOB_MASK (0xF0000U) |
#define | ASRC_ASRCCR_ACOB_SHIFT (16U) |
#define | ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK) |
#define | ASRC_ASRCCR_ACOC_MASK (0xF00000U) |
#define | ASRC_ASRCCR_ACOC_SHIFT (20U) |
#define | ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK) |
ASRDIA - ASRC Data Input Register for Pair x | |
#define | ASRC_ASRDIA_DATA_MASK (0xFFFFFFU) |
#define | ASRC_ASRDIA_DATA_SHIFT (0U) |
#define | ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK) |
ASRDOA - ASRC Data Output Register for Pair x | |
#define | ASRC_ASRDOA_DATA_MASK (0xFFFFFFU) |
#define | ASRC_ASRDOA_DATA_SHIFT (0U) |
#define | ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK) |
ASRDIB - ASRC Data Input Register for Pair x | |
#define | ASRC_ASRDIB_DATA_MASK (0xFFFFFFU) |
#define | ASRC_ASRDIB_DATA_SHIFT (0U) |
#define | ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK) |
ASRDOB - ASRC Data Output Register for Pair x | |
#define | ASRC_ASRDOB_DATA_MASK (0xFFFFFFU) |
#define | ASRC_ASRDOB_DATA_SHIFT (0U) |
#define | ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK) |
ASRDIC - ASRC Data Input Register for Pair x | |
#define | ASRC_ASRDIC_DATA_MASK (0xFFFFFFU) |
#define | ASRC_ASRDIC_DATA_SHIFT (0U) |
#define | ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK) |
ASRDOC - ASRC Data Output Register for Pair x | |
#define | ASRC_ASRDOC_DATA_MASK (0xFFFFFFU) |
#define | ASRC_ASRDOC_DATA_SHIFT (0U) |
#define | ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK) |
ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part | |
#define | ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU) |
#define | ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U) |
#define | ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK) |
ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part | |
#define | ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU) |
#define | ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U) |
#define | ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK) |
ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part | |
#define | ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU) |
#define | ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U) |
#define | ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK) |
ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part | |
#define | ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU) |
#define | ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U) |
#define | ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK) |
ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part | |
#define | ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU) |
#define | ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U) |
#define | ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK) |
ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part | |
#define | ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU) |
#define | ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U) |
#define | ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK) |
ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock | |
#define | ASRC_ASR76K_ASR76K_MASK (0x1FFFFU) |
#define | ASRC_ASR76K_ASR76K_SHIFT (0U) |
#define | ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK) |
ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock | |
#define | ASRC_ASR56K_ASR56K_MASK (0x1FFFFU) |
#define | ASRC_ASR56K_ASR56K_SHIFT (0U) |
#define | ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK) |
ASRMCRA - ASRC Misc Control Register for Pair A | |
#define | ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU) |
#define | ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U) |
#define | ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK) |
#define | ASRC_ASRMCRA_RSYNOFA_MASK (0x400U) |
#define | ASRC_ASRMCRA_RSYNOFA_SHIFT (10U) |
#define | ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK) |
#define | ASRC_ASRMCRA_RSYNIFA_MASK (0x800U) |
#define | ASRC_ASRMCRA_RSYNIFA_SHIFT (11U) |
#define | ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK) |
#define | ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U) |
#define | ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U) |
#define | ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK) |
#define | ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U) |
#define | ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U) |
#define | ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK) |
#define | ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U) |
#define | ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U) |
#define | ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK) |
#define | ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U) |
#define | ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U) |
#define | ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK) |
#define | ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U) |
#define | ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U) |
#define | ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK) |
ASRFSTA - ASRC FIFO Status Register for Pair A | |
#define | ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU) |
#define | ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U) |
#define | ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK) |
#define | ASRC_ASRFSTA_IAEA_MASK (0x800U) |
#define | ASRC_ASRFSTA_IAEA_SHIFT (11U) |
#define | ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK) |
#define | ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U) |
#define | ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U) |
#define | ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK) |
#define | ASRC_ASRFSTA_OAFA_MASK (0x800000U) |
#define | ASRC_ASRFSTA_OAFA_SHIFT (23U) |
#define | ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK) |
ASRMCRB - ASRC Misc Control Register for Pair B | |
#define | ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU) |
#define | ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U) |
#define | ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK) |
#define | ASRC_ASRMCRB_RSYNOFB_MASK (0x400U) |
#define | ASRC_ASRMCRB_RSYNOFB_SHIFT (10U) |
#define | ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK) |
#define | ASRC_ASRMCRB_RSYNIFB_MASK (0x800U) |
#define | ASRC_ASRMCRB_RSYNIFB_SHIFT (11U) |
#define | ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK) |
#define | ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U) |
#define | ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U) |
#define | ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK) |
#define | ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U) |
#define | ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U) |
#define | ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK) |
#define | ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U) |
#define | ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U) |
#define | ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK) |
#define | ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U) |
#define | ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U) |
#define | ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK) |
#define | ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U) |
#define | ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U) |
#define | ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK) |
ASRFSTB - ASRC FIFO Status Register for Pair B | |
#define | ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU) |
#define | ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U) |
#define | ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK) |
#define | ASRC_ASRFSTB_IAEB_MASK (0x800U) |
#define | ASRC_ASRFSTB_IAEB_SHIFT (11U) |
#define | ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK) |
#define | ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U) |
#define | ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U) |
#define | ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK) |
#define | ASRC_ASRFSTB_OAFB_MASK (0x800000U) |
#define | ASRC_ASRFSTB_OAFB_SHIFT (23U) |
#define | ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK) |
ASRMCRC - ASRC Misc Control Register for Pair C | |
#define | ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU) |
#define | ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U) |
#define | ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK) |
#define | ASRC_ASRMCRC_RSYNOFC_MASK (0x400U) |
#define | ASRC_ASRMCRC_RSYNOFC_SHIFT (10U) |
#define | ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK) |
#define | ASRC_ASRMCRC_RSYNIFC_MASK (0x800U) |
#define | ASRC_ASRMCRC_RSYNIFC_SHIFT (11U) |
#define | ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK) |
#define | ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U) |
#define | ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U) |
#define | ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK) |
#define | ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U) |
#define | ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U) |
#define | ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK) |
#define | ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U) |
#define | ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U) |
#define | ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK) |
#define | ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U) |
#define | ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U) |
#define | ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK) |
#define | ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U) |
#define | ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U) |
#define | ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK) |
ASRFSTC - ASRC FIFO Status Register for Pair C | |
#define | ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU) |
#define | ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U) |
#define | ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK) |
#define | ASRC_ASRFSTC_IAEC_MASK (0x800U) |
#define | ASRC_ASRFSTC_IAEC_SHIFT (11U) |
#define | ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK) |
#define | ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U) |
#define | ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U) |
#define | ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK) |
#define | ASRC_ASRFSTC_OAFC_MASK (0x800000U) |
#define | ASRC_ASRFSTC_OAFC_SHIFT (23U) |
#define | ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK) |
ASRMCR1 - ASRC Misc Control Register 1 for Pair X | |
#define | ASRC_ASRMCR1_OW16_MASK (0x1U) |
#define | ASRC_ASRMCR1_OW16_SHIFT (0U) |
#define | ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK) |
#define | ASRC_ASRMCR1_OSGN_MASK (0x2U) |
#define | ASRC_ASRMCR1_OSGN_SHIFT (1U) |
#define | ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK) |
#define | ASRC_ASRMCR1_OMSB_MASK (0x4U) |
#define | ASRC_ASRMCR1_OMSB_SHIFT (2U) |
#define | ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK) |
#define | ASRC_ASRMCR1_IMSB_MASK (0x100U) |
#define | ASRC_ASRMCR1_IMSB_SHIFT (8U) |
#define | ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK) |
#define | ASRC_ASRMCR1_IWD_MASK (0x600U) |
#define | ASRC_ASRMCR1_IWD_SHIFT (9U) |
#define | ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK) |
CTRL0 - Fractional PLL Control Register | |
#define | AUDIO_PLL_CTRL0_DIV_SELECT_MASK (0x7FU) |
#define | AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT (0U) |
#define | AUDIO_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_DIV_SELECT_MASK) |
#define | AUDIO_PLL_CTRL0_ENABLE_ALT_MASK (0x100U) |
#define | AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT (8U) |
#define | AUDIO_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_ALT_MASK) |
#define | AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U) |
#define | AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U) |
#define | AUDIO_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK) |
#define | AUDIO_PLL_CTRL0_POWERUP_MASK (0x4000U) |
#define | AUDIO_PLL_CTRL0_POWERUP_SHIFT (14U) |
#define | AUDIO_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POWERUP_SHIFT)) & AUDIO_PLL_CTRL0_POWERUP_MASK) |
#define | AUDIO_PLL_CTRL0_ENABLE_MASK (0x8000U) |
#define | AUDIO_PLL_CTRL0_ENABLE_SHIFT (15U) |
#define | AUDIO_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_MASK) |
#define | AUDIO_PLL_CTRL0_BYPASS_MASK (0x10000U) |
#define | AUDIO_PLL_CTRL0_BYPASS_SHIFT (16U) |
#define | AUDIO_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BYPASS_SHIFT)) & AUDIO_PLL_CTRL0_BYPASS_MASK) |
#define | AUDIO_PLL_CTRL0_DITHER_EN_MASK (0x20000U) |
#define | AUDIO_PLL_CTRL0_DITHER_EN_SHIFT (17U) |
#define | AUDIO_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DITHER_EN_SHIFT)) & AUDIO_PLL_CTRL0_DITHER_EN_MASK) |
#define | AUDIO_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U) |
#define | AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT (19U) |
#define | AUDIO_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_TRIM_MASK) |
#define | AUDIO_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U) |
#define | AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT (22U) |
#define | AUDIO_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & AUDIO_PLL_CTRL0_PLL_REG_EN_MASK) |
#define | AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) |
#define | AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U) |
#define | AUDIO_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK) |
#define | AUDIO_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U) |
#define | AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT (29U) |
#define | AUDIO_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_SELECT_MASK) |
#define | ETHERNET_PLL_CTRL0_DIV_SELECT_MASK (0x7FU) |
#define | ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT (0U) |
#define | ETHERNET_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_DIV_SELECT_MASK) |
#define | ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK (0x100U) |
#define | ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT (8U) |
#define | ETHERNET_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK) |
#define | ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U) |
#define | ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U) |
#define | ETHERNET_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK) |
#define | ETHERNET_PLL_CTRL0_POWERUP_MASK (0x4000U) |
#define | ETHERNET_PLL_CTRL0_POWERUP_SHIFT (14U) |
#define | ETHERNET_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POWERUP_SHIFT)) & ETHERNET_PLL_CTRL0_POWERUP_MASK) |
#define | ETHERNET_PLL_CTRL0_ENABLE_MASK (0x8000U) |
#define | ETHERNET_PLL_CTRL0_ENABLE_SHIFT (15U) |
#define | ETHERNET_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_MASK) |
#define | ETHERNET_PLL_CTRL0_BYPASS_MASK (0x10000U) |
#define | ETHERNET_PLL_CTRL0_BYPASS_SHIFT (16U) |
#define | ETHERNET_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BYPASS_SHIFT)) & ETHERNET_PLL_CTRL0_BYPASS_MASK) |
#define | ETHERNET_PLL_CTRL0_DITHER_EN_MASK (0x20000U) |
#define | ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT (17U) |
#define | ETHERNET_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT)) & ETHERNET_PLL_CTRL0_DITHER_EN_MASK) |
#define | ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U) |
#define | ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT (19U) |
#define | ETHERNET_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK) |
#define | ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U) |
#define | ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT (22U) |
#define | ETHERNET_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT)) & ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK) |
#define | ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) |
#define | ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U) |
#define | ETHERNET_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK) |
#define | ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U) |
#define | ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT (29U) |
#define | ETHERNET_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK) |
#define | VIDEO_PLL_CTRL0_DIV_SELECT_MASK (0x7FU) |
#define | VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT (0U) |
#define | VIDEO_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_DIV_SELECT_MASK) |
#define | VIDEO_PLL_CTRL0_ENABLE_ALT_MASK (0x100U) |
#define | VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT (8U) |
#define | VIDEO_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_ALT_MASK) |
#define | VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U) |
#define | VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U) |
#define | VIDEO_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK) |
#define | VIDEO_PLL_CTRL0_POWERUP_MASK (0x4000U) |
#define | VIDEO_PLL_CTRL0_POWERUP_SHIFT (14U) |
#define | VIDEO_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POWERUP_SHIFT)) & VIDEO_PLL_CTRL0_POWERUP_MASK) |
#define | VIDEO_PLL_CTRL0_ENABLE_MASK (0x8000U) |
#define | VIDEO_PLL_CTRL0_ENABLE_SHIFT (15U) |
#define | VIDEO_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_MASK) |
#define | VIDEO_PLL_CTRL0_BYPASS_MASK (0x10000U) |
#define | VIDEO_PLL_CTRL0_BYPASS_SHIFT (16U) |
#define | VIDEO_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BYPASS_SHIFT)) & VIDEO_PLL_CTRL0_BYPASS_MASK) |
#define | VIDEO_PLL_CTRL0_DITHER_EN_MASK (0x20000U) |
#define | VIDEO_PLL_CTRL0_DITHER_EN_SHIFT (17U) |
#define | VIDEO_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DITHER_EN_SHIFT)) & VIDEO_PLL_CTRL0_DITHER_EN_MASK) |
#define | VIDEO_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U) |
#define | VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT (19U) |
#define | VIDEO_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_TRIM_MASK) |
#define | VIDEO_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U) |
#define | VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT (22U) |
#define | VIDEO_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & VIDEO_PLL_CTRL0_PLL_REG_EN_MASK) |
#define | VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) |
#define | VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U) |
#define | VIDEO_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK) |
#define | VIDEO_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U) |
#define | VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT (29U) |
#define | VIDEO_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_SELECT_MASK) |
SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register | |
#define | AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU) |
#define | AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U) |
#define | AUDIO_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK) |
#define | AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U) |
#define | AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U) |
#define | AUDIO_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK) |
#define | AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U) |
#define | AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U) |
#define | AUDIO_PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK) |
#define | ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU) |
#define | ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U) |
#define | ETHERNET_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK) |
#define | ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U) |
#define | ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U) |
#define | ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK) |
#define | ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U) |
#define | ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U) |
#define | ETHERNET_PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK) |
#define | VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU) |
#define | VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U) |
#define | VIDEO_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK) |
#define | VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U) |
#define | VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U) |
#define | VIDEO_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK) |
#define | VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U) |
#define | VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U) |
#define | VIDEO_PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK) |
NUMERATOR - Fractional PLL Numerator Control Register | |
#define | AUDIO_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU) |
#define | AUDIO_PLL_NUMERATOR_NUM_SHIFT (0U) |
#define | AUDIO_PLL_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_NUMERATOR_NUM_SHIFT)) & AUDIO_PLL_NUMERATOR_NUM_MASK) |
#define | ETHERNET_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU) |
#define | ETHERNET_PLL_NUMERATOR_NUM_SHIFT (0U) |
#define | ETHERNET_PLL_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_NUMERATOR_NUM_SHIFT)) & ETHERNET_PLL_NUMERATOR_NUM_MASK) |
#define | VIDEO_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU) |
#define | VIDEO_PLL_NUMERATOR_NUM_SHIFT (0U) |
#define | VIDEO_PLL_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_NUMERATOR_NUM_SHIFT)) & VIDEO_PLL_NUMERATOR_NUM_MASK) |
DENOMINATOR - Fractional PLL Denominator Control Register | |
#define | AUDIO_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) |
#define | AUDIO_PLL_DENOMINATOR_DENOM_SHIFT (0U) |
#define | AUDIO_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_DENOMINATOR_DENOM_SHIFT)) & AUDIO_PLL_DENOMINATOR_DENOM_MASK) |
#define | ETHERNET_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) |
#define | ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT (0U) |
#define | ETHERNET_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT)) & ETHERNET_PLL_DENOMINATOR_DENOM_MASK) |
#define | VIDEO_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) |
#define | VIDEO_PLL_DENOMINATOR_DENOM_SHIFT (0U) |
#define | VIDEO_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_DENOMINATOR_DENOM_SHIFT)) & VIDEO_PLL_DENOMINATOR_DENOM_MASK) |
MCFGR - Master Configuration Register | |
#define | CAAM_MCFGR_NORMAL_BURST_MASK (0x1U) |
#define | CAAM_MCFGR_NORMAL_BURST_SHIFT (0U) |
#define | CAAM_MCFGR_NORMAL_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_NORMAL_BURST_SHIFT)) & CAAM_MCFGR_NORMAL_BURST_MASK) |
#define | CAAM_MCFGR_LARGE_BURST_MASK (0x4U) |
#define | CAAM_MCFGR_LARGE_BURST_SHIFT (2U) |
#define | CAAM_MCFGR_LARGE_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_LARGE_BURST_SHIFT)) & CAAM_MCFGR_LARGE_BURST_MASK) |
#define | CAAM_MCFGR_AXIPIPE_MASK (0xF0U) |
#define | CAAM_MCFGR_AXIPIPE_SHIFT (4U) |
#define | CAAM_MCFGR_AXIPIPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AXIPIPE_SHIFT)) & CAAM_MCFGR_AXIPIPE_MASK) |
#define | CAAM_MCFGR_AWCACHE_MASK (0xF00U) |
#define | CAAM_MCFGR_AWCACHE_SHIFT (8U) |
#define | CAAM_MCFGR_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AWCACHE_SHIFT)) & CAAM_MCFGR_AWCACHE_MASK) |
#define | CAAM_MCFGR_ARCACHE_MASK (0xF000U) |
#define | CAAM_MCFGR_ARCACHE_SHIFT (12U) |
#define | CAAM_MCFGR_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_ARCACHE_SHIFT)) & CAAM_MCFGR_ARCACHE_MASK) |
#define | CAAM_MCFGR_PS_MASK (0x10000U) |
#define | CAAM_MCFGR_PS_SHIFT (16U) |
#define | CAAM_MCFGR_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_PS_SHIFT)) & CAAM_MCFGR_PS_MASK) |
#define | CAAM_MCFGR_DWT_MASK (0x80000U) |
#define | CAAM_MCFGR_DWT_SHIFT (19U) |
#define | CAAM_MCFGR_DWT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DWT_SHIFT)) & CAAM_MCFGR_DWT_MASK) |
#define | CAAM_MCFGR_WRHD_MASK (0x8000000U) |
#define | CAAM_MCFGR_WRHD_SHIFT (27U) |
#define | CAAM_MCFGR_WRHD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WRHD_SHIFT)) & CAAM_MCFGR_WRHD_MASK) |
#define | CAAM_MCFGR_DMA_RST_MASK (0x10000000U) |
#define | CAAM_MCFGR_DMA_RST_SHIFT (28U) |
#define | CAAM_MCFGR_DMA_RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DMA_RST_SHIFT)) & CAAM_MCFGR_DMA_RST_MASK) |
#define | CAAM_MCFGR_WDF_MASK (0x20000000U) |
#define | CAAM_MCFGR_WDF_SHIFT (29U) |
#define | CAAM_MCFGR_WDF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDF_SHIFT)) & CAAM_MCFGR_WDF_MASK) |
#define | CAAM_MCFGR_WDE_MASK (0x40000000U) |
#define | CAAM_MCFGR_WDE_SHIFT (30U) |
#define | CAAM_MCFGR_WDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDE_SHIFT)) & CAAM_MCFGR_WDE_MASK) |
#define | CAAM_MCFGR_SWRST_MASK (0x80000000U) |
#define | CAAM_MCFGR_SWRST_SHIFT (31U) |
#define | CAAM_MCFGR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_SWRST_SHIFT)) & CAAM_MCFGR_SWRST_MASK) |
PAGE0_SDID - Page 0 SDID Register | |
#define | CAAM_PAGE0_SDID_SDID_MASK (0x7FFFU) |
#define | CAAM_PAGE0_SDID_SDID_SHIFT (0U) |
#define | CAAM_PAGE0_SDID_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PAGE0_SDID_SDID_SHIFT)) & CAAM_PAGE0_SDID_SDID_MASK) |
SCFGR - Security Configuration Register | |
#define | CAAM_SCFGR_PRIBLOB_MASK (0x3U) |
#define | CAAM_SCFGR_PRIBLOB_SHIFT (0U) |
#define | CAAM_SCFGR_PRIBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_PRIBLOB_SHIFT)) & CAAM_SCFGR_PRIBLOB_MASK) |
#define | CAAM_SCFGR_RNGSH0_MASK (0x200U) |
#define | CAAM_SCFGR_RNGSH0_SHIFT (9U) |
#define | CAAM_SCFGR_RNGSH0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_RNGSH0_SHIFT)) & CAAM_SCFGR_RNGSH0_MASK) |
#define | CAAM_SCFGR_LCK_TRNG_MASK (0x800U) |
#define | CAAM_SCFGR_LCK_TRNG_SHIFT (11U) |
#define | CAAM_SCFGR_LCK_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_LCK_TRNG_SHIFT)) & CAAM_SCFGR_LCK_TRNG_MASK) |
#define | CAAM_SCFGR_VIRT_EN_MASK (0x8000U) |
#define | CAAM_SCFGR_VIRT_EN_SHIFT (15U) |
#define | CAAM_SCFGR_VIRT_EN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_VIRT_EN_SHIFT)) & CAAM_SCFGR_VIRT_EN_MASK) |
#define | CAAM_SCFGR_MPMRL_MASK (0x4000000U) |
#define | CAAM_SCFGR_MPMRL_SHIFT (26U) |
#define | CAAM_SCFGR_MPMRL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPMRL_SHIFT)) & CAAM_SCFGR_MPMRL_MASK) |
#define | CAAM_SCFGR_MPPKRC_MASK (0x8000000U) |
#define | CAAM_SCFGR_MPPKRC_SHIFT (27U) |
#define | CAAM_SCFGR_MPPKRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPPKRC_SHIFT)) & CAAM_SCFGR_MPPKRC_MASK) |
#define | CAAM_SCFGR_MPCURVE_MASK (0xF0000000U) |
#define | CAAM_SCFGR_MPCURVE_SHIFT (28U) |
#define | CAAM_SCFGR_MPCURVE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPCURVE_SHIFT)) & CAAM_SCFGR_MPCURVE_MASK) |
JRDID_MS - Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half | |
#define | CAAM_JRDID_MS_PRIM_DID_MASK (0xFU) |
#define | CAAM_JRDID_MS_PRIM_DID_SHIFT (0U) |
#define | CAAM_JRDID_MS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_DID_SHIFT)) & CAAM_JRDID_MS_PRIM_DID_MASK) |
#define | CAAM_JRDID_MS_PRIM_TZ_MASK (0x10U) |
#define | CAAM_JRDID_MS_PRIM_TZ_SHIFT (4U) |
#define | CAAM_JRDID_MS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_TZ_SHIFT)) & CAAM_JRDID_MS_PRIM_TZ_MASK) |
#define | CAAM_JRDID_MS_SDID_MS_MASK (0x7FE0U) |
#define | CAAM_JRDID_MS_SDID_MS_SHIFT (5U) |
#define | CAAM_JRDID_MS_SDID_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_SDID_MS_SHIFT)) & CAAM_JRDID_MS_SDID_MS_MASK) |
#define | CAAM_JRDID_MS_TZ_OWN_MASK (0x8000U) |
#define | CAAM_JRDID_MS_TZ_OWN_SHIFT (15U) |
#define | CAAM_JRDID_MS_TZ_OWN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_TZ_OWN_SHIFT)) & CAAM_JRDID_MS_TZ_OWN_MASK) |
#define | CAAM_JRDID_MS_AMTD_MASK (0x10000U) |
#define | CAAM_JRDID_MS_AMTD_SHIFT (16U) |
#define | CAAM_JRDID_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_AMTD_SHIFT)) & CAAM_JRDID_MS_AMTD_MASK) |
#define | CAAM_JRDID_MS_LAMTD_MASK (0x20000U) |
#define | CAAM_JRDID_MS_LAMTD_SHIFT (17U) |
#define | CAAM_JRDID_MS_LAMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LAMTD_SHIFT)) & CAAM_JRDID_MS_LAMTD_MASK) |
#define | CAAM_JRDID_MS_PRIM_ICID_MASK (0x3FF80000U) |
#define | CAAM_JRDID_MS_PRIM_ICID_SHIFT (19U) |
#define | CAAM_JRDID_MS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_ICID_SHIFT)) & CAAM_JRDID_MS_PRIM_ICID_MASK) |
#define | CAAM_JRDID_MS_USE_OUT_MASK (0x40000000U) |
#define | CAAM_JRDID_MS_USE_OUT_SHIFT (30U) |
#define | CAAM_JRDID_MS_USE_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_USE_OUT_SHIFT)) & CAAM_JRDID_MS_USE_OUT_MASK) |
#define | CAAM_JRDID_MS_LDID_MASK (0x80000000U) |
#define | CAAM_JRDID_MS_LDID_SHIFT (31U) |
#define | CAAM_JRDID_MS_LDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LDID_SHIFT)) & CAAM_JRDID_MS_LDID_MASK) |
JRDID_LS - Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half | |
#define | CAAM_JRDID_LS_OUT_DID_MASK (0xFU) |
#define | CAAM_JRDID_LS_OUT_DID_SHIFT (0U) |
#define | CAAM_JRDID_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_DID_SHIFT)) & CAAM_JRDID_LS_OUT_DID_MASK) |
#define | CAAM_JRDID_LS_OUT_ICID_MASK (0x3FF80000U) |
#define | CAAM_JRDID_LS_OUT_ICID_SHIFT (19U) |
#define | CAAM_JRDID_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_ICID_SHIFT)) & CAAM_JRDID_LS_OUT_ICID_MASK) |
DEBUGCTL - Debug Control Register | |
#define | CAAM_DEBUGCTL_STOP_MASK (0x10000U) |
#define | CAAM_DEBUGCTL_STOP_SHIFT (16U) |
#define | CAAM_DEBUGCTL_STOP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_SHIFT)) & CAAM_DEBUGCTL_STOP_MASK) |
#define | CAAM_DEBUGCTL_STOP_ACK_MASK (0x20000U) |
#define | CAAM_DEBUGCTL_STOP_ACK_SHIFT (17U) |
#define | CAAM_DEBUGCTL_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_ACK_SHIFT)) & CAAM_DEBUGCTL_STOP_ACK_MASK) |
JRSTARTR - Job Ring Start Register | |
#define | CAAM_JRSTARTR_Start_JR0_MASK (0x1U) |
#define | CAAM_JRSTARTR_Start_JR0_SHIFT (0U) |
#define | CAAM_JRSTARTR_Start_JR0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR0_SHIFT)) & CAAM_JRSTARTR_Start_JR0_MASK) |
#define | CAAM_JRSTARTR_Start_JR1_MASK (0x2U) |
#define | CAAM_JRSTARTR_Start_JR1_SHIFT (1U) |
#define | CAAM_JRSTARTR_Start_JR1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR1_SHIFT)) & CAAM_JRSTARTR_Start_JR1_MASK) |
#define | CAAM_JRSTARTR_Start_JR2_MASK (0x4U) |
#define | CAAM_JRSTARTR_Start_JR2_SHIFT (2U) |
#define | CAAM_JRSTARTR_Start_JR2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR2_SHIFT)) & CAAM_JRSTARTR_Start_JR2_MASK) |
#define | CAAM_JRSTARTR_Start_JR3_MASK (0x8U) |
#define | CAAM_JRSTARTR_Start_JR3_SHIFT (3U) |
#define | CAAM_JRSTARTR_Start_JR3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR3_SHIFT)) & CAAM_JRSTARTR_Start_JR3_MASK) |
RTIC_OWN - RTIC OWN Register | |
#define | CAAM_RTIC_OWN_ROWN_DID_MASK (0xFU) |
#define | CAAM_RTIC_OWN_ROWN_DID_SHIFT (0U) |
#define | CAAM_RTIC_OWN_ROWN_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_DID_SHIFT)) & CAAM_RTIC_OWN_ROWN_DID_MASK) |
#define | CAAM_RTIC_OWN_ROWN_TZ_MASK (0x10U) |
#define | CAAM_RTIC_OWN_ROWN_TZ_SHIFT (4U) |
#define | CAAM_RTIC_OWN_ROWN_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_TZ_SHIFT)) & CAAM_RTIC_OWN_ROWN_TZ_MASK) |
#define | CAAM_RTIC_OWN_LCK_MASK (0x80000000U) |
#define | CAAM_RTIC_OWN_LCK_SHIFT (31U) |
#define | CAAM_RTIC_OWN_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_LCK_SHIFT)) & CAAM_RTIC_OWN_LCK_MASK) |
RTIC_DID - RTIC DID Register for Block A..RTIC DID Register for Block D | |
#define | CAAM_RTIC_DID_RTIC_DID_MASK (0xFU) |
#define | CAAM_RTIC_DID_RTIC_DID_SHIFT (0U) |
#define | CAAM_RTIC_DID_RTIC_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_DID_SHIFT)) & CAAM_RTIC_DID_RTIC_DID_MASK) |
#define | CAAM_RTIC_DID_RTIC_TZ_MASK (0x10U) |
#define | CAAM_RTIC_DID_RTIC_TZ_SHIFT (4U) |
#define | CAAM_RTIC_DID_RTIC_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_TZ_SHIFT)) & CAAM_RTIC_DID_RTIC_TZ_MASK) |
#define | CAAM_RTIC_DID_RTIC_ICID_MASK (0x3FF80000U) |
#define | CAAM_RTIC_DID_RTIC_ICID_SHIFT (19U) |
#define | CAAM_RTIC_DID_RTIC_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_ICID_SHIFT)) & CAAM_RTIC_DID_RTIC_ICID_MASK) |
DECORSR - DECO Request Source Register | |
#define | CAAM_DECORSR_JR_MASK (0x3U) |
#define | CAAM_DECORSR_JR_SHIFT (0U) |
#define | CAAM_DECORSR_JR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_JR_SHIFT)) & CAAM_DECORSR_JR_MASK) |
#define | CAAM_DECORSR_VALID_MASK (0x80000000U) |
#define | CAAM_DECORSR_VALID_SHIFT (31U) |
#define | CAAM_DECORSR_VALID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_VALID_SHIFT)) & CAAM_DECORSR_VALID_MASK) |
DECORR - DECO Request Register | |
#define | CAAM_DECORR_RQD0_MASK (0x1U) |
#define | CAAM_DECORR_RQD0_SHIFT (0U) |
#define | CAAM_DECORR_RQD0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_RQD0_SHIFT)) & CAAM_DECORR_RQD0_MASK) |
#define | CAAM_DECORR_DEN0_MASK (0x10000U) |
#define | CAAM_DECORR_DEN0_SHIFT (16U) |
#define | CAAM_DECORR_DEN0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_DEN0_SHIFT)) & CAAM_DECORR_DEN0_MASK) |
DECODID_MS - DECO0 DID Register - most significant half | |
#define | CAAM_DECODID_MS_DPRIM_DID_MASK (0xFU) |
#define | CAAM_DECODID_MS_DPRIM_DID_SHIFT (0U) |
#define | CAAM_DECODID_MS_DPRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_DPRIM_DID_SHIFT)) & CAAM_DECODID_MS_DPRIM_DID_MASK) |
#define | CAAM_DECODID_MS_D_NS_MASK (0x10U) |
#define | CAAM_DECODID_MS_D_NS_SHIFT (4U) |
#define | CAAM_DECODID_MS_D_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_D_NS_SHIFT)) & CAAM_DECODID_MS_D_NS_MASK) |
#define | CAAM_DECODID_MS_LCK_MASK (0x80000000U) |
#define | CAAM_DECODID_MS_LCK_SHIFT (31U) |
#define | CAAM_DECODID_MS_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_LCK_SHIFT)) & CAAM_DECODID_MS_LCK_MASK) |
DECODID_LS - DECO0 DID Register - least significant half | |
#define | CAAM_DECODID_LS_DSEQ_DID_MASK (0xFU) |
#define | CAAM_DECODID_LS_DSEQ_DID_SHIFT (0U) |
#define | CAAM_DECODID_LS_DSEQ_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DSEQ_DID_MASK) |
#define | CAAM_DECODID_LS_DSEQ_NS_MASK (0x10U) |
#define | CAAM_DECODID_LS_DSEQ_NS_SHIFT (4U) |
#define | CAAM_DECODID_LS_DSEQ_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DSEQ_NS_MASK) |
#define | CAAM_DECODID_LS_DNSEQ_DID_MASK (0xF0000U) |
#define | CAAM_DECODID_LS_DNSEQ_DID_SHIFT (16U) |
#define | CAAM_DECODID_LS_DNSEQ_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DNSEQ_DID_MASK) |
#define | CAAM_DECODID_LS_DNONSEQ_NS_MASK (0x100000U) |
#define | CAAM_DECODID_LS_DNONSEQ_NS_SHIFT (20U) |
#define | CAAM_DECODID_LS_DNONSEQ_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNONSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DNONSEQ_NS_MASK) |
DAR - DECO Availability Register | |
#define | CAAM_DAR_NYA0_MASK (0x1U) |
#define | CAAM_DAR_NYA0_SHIFT (0U) |
#define | CAAM_DAR_NYA0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DAR_NYA0_SHIFT)) & CAAM_DAR_NYA0_MASK) |
DRR - DECO Reset Register | |
#define | CAAM_DRR_RST0_MASK (0x1U) |
#define | CAAM_DRR_RST0_SHIFT (0U) |
#define | CAAM_DRR_RST0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DRR_RST0_SHIFT)) & CAAM_DRR_RST0_MASK) |
JRSMVBAR - Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register | |
#define | CAAM_JRSMVBAR_SMVBA_MASK (0xFFFFFFFFU) |
#define | CAAM_JRSMVBAR_SMVBA_SHIFT (0U) |
#define | CAAM_JRSMVBAR_SMVBA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSMVBAR_SMVBA_SHIFT)) & CAAM_JRSMVBAR_SMVBA_MASK) |
PBSL - Peak Bandwidth Smoothing Limit Register | |
#define | CAAM_PBSL_PBSL_MASK (0x7FU) |
#define | CAAM_PBSL_PBSL_SHIFT (0U) |
#define | CAAM_PBSL_PBSL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PBSL_PBSL_SHIFT)) & CAAM_PBSL_PBSL_MASK) |
DMA_AIDL_MAP_MS - DMA0_AIDL_MAP_MS | |
#define | CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK (0xFFU) |
#define | CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT (0U) |
#define | CAAM_DMA_AIDL_MAP_MS_AID4_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK) |
#define | CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK (0xFF00U) |
#define | CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT (8U) |
#define | CAAM_DMA_AIDL_MAP_MS_AID5_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK) |
#define | CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK (0xFF0000U) |
#define | CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT (16U) |
#define | CAAM_DMA_AIDL_MAP_MS_AID6_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK) |
#define | CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK (0xFF000000U) |
#define | CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT (24U) |
#define | CAAM_DMA_AIDL_MAP_MS_AID7_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK) |
DMA_AIDL_MAP_LS - DMA0_AIDL_MAP_LS | |
#define | CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK (0xFFU) |
#define | CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT (0U) |
#define | CAAM_DMA_AIDL_MAP_LS_AID0_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK) |
#define | CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK (0xFF00U) |
#define | CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT (8U) |
#define | CAAM_DMA_AIDL_MAP_LS_AID1_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK) |
#define | CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK (0xFF0000U) |
#define | CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT (16U) |
#define | CAAM_DMA_AIDL_MAP_LS_AID2_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK) |
#define | CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK (0xFF000000U) |
#define | CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT (24U) |
#define | CAAM_DMA_AIDL_MAP_LS_AID3_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK) |
DMA_AIDM_MAP_MS - DMA0_AIDM_MAP_MS | |
#define | CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK (0xFFU) |
#define | CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT (0U) |
#define | CAAM_DMA_AIDM_MAP_MS_AID12_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK) |
#define | CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK (0xFF00U) |
#define | CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT (8U) |
#define | CAAM_DMA_AIDM_MAP_MS_AID13_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK) |
#define | CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK (0xFF0000U) |
#define | CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT (16U) |
#define | CAAM_DMA_AIDM_MAP_MS_AID14_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK) |
#define | CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK (0xFF000000U) |
#define | CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT (24U) |
#define | CAAM_DMA_AIDM_MAP_MS_AID15_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK) |
DMA_AIDM_MAP_LS - DMA0_AIDM_MAP_LS | |
#define | CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK (0xFFU) |
#define | CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT (0U) |
#define | CAAM_DMA_AIDM_MAP_LS_AID8_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK) |
#define | CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK (0xFF00U) |
#define | CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT (8U) |
#define | CAAM_DMA_AIDM_MAP_LS_AID9_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK) |
#define | CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK (0xFF0000U) |
#define | CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT (16U) |
#define | CAAM_DMA_AIDM_MAP_LS_AID10_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK) |
#define | CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK (0xFF000000U) |
#define | CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT (24U) |
#define | CAAM_DMA_AIDM_MAP_LS_AID11_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK) |
DMA0_AID_ENB - DMA0 AXI ID Enable Register | |
#define | CAAM_DMA0_AID_ENB_AID0E_MASK (0x1U) |
#define | CAAM_DMA0_AID_ENB_AID0E_SHIFT (0U) |
#define | CAAM_DMA0_AID_ENB_AID0E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID0E_SHIFT)) & CAAM_DMA0_AID_ENB_AID0E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID1E_MASK (0x2U) |
#define | CAAM_DMA0_AID_ENB_AID1E_SHIFT (1U) |
#define | CAAM_DMA0_AID_ENB_AID1E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID1E_SHIFT)) & CAAM_DMA0_AID_ENB_AID1E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID2E_MASK (0x4U) |
#define | CAAM_DMA0_AID_ENB_AID2E_SHIFT (2U) |
#define | CAAM_DMA0_AID_ENB_AID2E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID2E_SHIFT)) & CAAM_DMA0_AID_ENB_AID2E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID3E_MASK (0x8U) |
#define | CAAM_DMA0_AID_ENB_AID3E_SHIFT (3U) |
#define | CAAM_DMA0_AID_ENB_AID3E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID3E_SHIFT)) & CAAM_DMA0_AID_ENB_AID3E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID4E_MASK (0x10U) |
#define | CAAM_DMA0_AID_ENB_AID4E_SHIFT (4U) |
#define | CAAM_DMA0_AID_ENB_AID4E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID4E_SHIFT)) & CAAM_DMA0_AID_ENB_AID4E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID5E_MASK (0x20U) |
#define | CAAM_DMA0_AID_ENB_AID5E_SHIFT (5U) |
#define | CAAM_DMA0_AID_ENB_AID5E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID5E_SHIFT)) & CAAM_DMA0_AID_ENB_AID5E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID6E_MASK (0x40U) |
#define | CAAM_DMA0_AID_ENB_AID6E_SHIFT (6U) |
#define | CAAM_DMA0_AID_ENB_AID6E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID6E_SHIFT)) & CAAM_DMA0_AID_ENB_AID6E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID7E_MASK (0x80U) |
#define | CAAM_DMA0_AID_ENB_AID7E_SHIFT (7U) |
#define | CAAM_DMA0_AID_ENB_AID7E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID7E_SHIFT)) & CAAM_DMA0_AID_ENB_AID7E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID8E_MASK (0x100U) |
#define | CAAM_DMA0_AID_ENB_AID8E_SHIFT (8U) |
#define | CAAM_DMA0_AID_ENB_AID8E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID8E_SHIFT)) & CAAM_DMA0_AID_ENB_AID8E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID9E_MASK (0x200U) |
#define | CAAM_DMA0_AID_ENB_AID9E_SHIFT (9U) |
#define | CAAM_DMA0_AID_ENB_AID9E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID9E_SHIFT)) & CAAM_DMA0_AID_ENB_AID9E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID10E_MASK (0x400U) |
#define | CAAM_DMA0_AID_ENB_AID10E_SHIFT (10U) |
#define | CAAM_DMA0_AID_ENB_AID10E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID10E_SHIFT)) & CAAM_DMA0_AID_ENB_AID10E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID11E_MASK (0x800U) |
#define | CAAM_DMA0_AID_ENB_AID11E_SHIFT (11U) |
#define | CAAM_DMA0_AID_ENB_AID11E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID11E_SHIFT)) & CAAM_DMA0_AID_ENB_AID11E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID12E_MASK (0x1000U) |
#define | CAAM_DMA0_AID_ENB_AID12E_SHIFT (12U) |
#define | CAAM_DMA0_AID_ENB_AID12E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID12E_SHIFT)) & CAAM_DMA0_AID_ENB_AID12E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID13E_MASK (0x2000U) |
#define | CAAM_DMA0_AID_ENB_AID13E_SHIFT (13U) |
#define | CAAM_DMA0_AID_ENB_AID13E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID13E_SHIFT)) & CAAM_DMA0_AID_ENB_AID13E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID14E_MASK (0x4000U) |
#define | CAAM_DMA0_AID_ENB_AID14E_SHIFT (14U) |
#define | CAAM_DMA0_AID_ENB_AID14E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID14E_SHIFT)) & CAAM_DMA0_AID_ENB_AID14E_MASK) |
#define | CAAM_DMA0_AID_ENB_AID15E_MASK (0x8000U) |
#define | CAAM_DMA0_AID_ENB_AID15E_SHIFT (15U) |
#define | CAAM_DMA0_AID_ENB_AID15E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID15E_SHIFT)) & CAAM_DMA0_AID_ENB_AID15E_MASK) |
DMA0_ARD_TC - DMA0 AXI Read Timing Check Register | |
#define | CAAM_DMA0_ARD_TC_ARSC_MASK (0xFFFFFU) |
#define | CAAM_DMA0_ARD_TC_ARSC_SHIFT (0U) |
#define | CAAM_DMA0_ARD_TC_ARSC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARSC_SHIFT)) & CAAM_DMA0_ARD_TC_ARSC_MASK) |
#define | CAAM_DMA0_ARD_TC_ARLC_MASK (0xFFFFF000000U) |
#define | CAAM_DMA0_ARD_TC_ARLC_SHIFT (24U) |
#define | CAAM_DMA0_ARD_TC_ARLC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARLC_SHIFT)) & CAAM_DMA0_ARD_TC_ARLC_MASK) |
#define | CAAM_DMA0_ARD_TC_ARL_MASK (0xFFF000000000000U) |
#define | CAAM_DMA0_ARD_TC_ARL_SHIFT (48U) |
#define | CAAM_DMA0_ARD_TC_ARL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARL_SHIFT)) & CAAM_DMA0_ARD_TC_ARL_MASK) |
#define | CAAM_DMA0_ARD_TC_ARTL_MASK (0x1000000000000000U) |
#define | CAAM_DMA0_ARD_TC_ARTL_SHIFT (60U) |
#define | CAAM_DMA0_ARD_TC_ARTL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTL_SHIFT)) & CAAM_DMA0_ARD_TC_ARTL_MASK) |
#define | CAAM_DMA0_ARD_TC_ARTT_MASK (0x2000000000000000U) |
#define | CAAM_DMA0_ARD_TC_ARTT_SHIFT (61U) |
#define | CAAM_DMA0_ARD_TC_ARTT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTT_SHIFT)) & CAAM_DMA0_ARD_TC_ARTT_MASK) |
#define | CAAM_DMA0_ARD_TC_ARCT_MASK (0x4000000000000000U) |
#define | CAAM_DMA0_ARD_TC_ARCT_SHIFT (62U) |
#define | CAAM_DMA0_ARD_TC_ARCT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARCT_SHIFT)) & CAAM_DMA0_ARD_TC_ARCT_MASK) |
#define | CAAM_DMA0_ARD_TC_ARTCE_MASK (0x8000000000000000U) |
#define | CAAM_DMA0_ARD_TC_ARTCE_SHIFT (63U) |
#define | CAAM_DMA0_ARD_TC_ARTCE(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTCE_SHIFT)) & CAAM_DMA0_ARD_TC_ARTCE_MASK) |
DMA0_ARD_LAT - DMA0 Read Timing Check Latency Register | |
#define | CAAM_DMA0_ARD_LAT_SARL_MASK (0xFFFFFFFFU) |
#define | CAAM_DMA0_ARD_LAT_SARL_SHIFT (0U) |
#define | CAAM_DMA0_ARD_LAT_SARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_ARD_LAT_SARL_SHIFT)) & CAAM_DMA0_ARD_LAT_SARL_MASK) |
DMA0_AWR_TC - DMA0 AXI Write Timing Check Register | |
#define | CAAM_DMA0_AWR_TC_AWSC_MASK (0xFFFFFU) |
#define | CAAM_DMA0_AWR_TC_AWSC_SHIFT (0U) |
#define | CAAM_DMA0_AWR_TC_AWSC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWSC_SHIFT)) & CAAM_DMA0_AWR_TC_AWSC_MASK) |
#define | CAAM_DMA0_AWR_TC_AWLC_MASK (0xFFFFF000000U) |
#define | CAAM_DMA0_AWR_TC_AWLC_SHIFT (24U) |
#define | CAAM_DMA0_AWR_TC_AWLC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWLC_SHIFT)) & CAAM_DMA0_AWR_TC_AWLC_MASK) |
#define | CAAM_DMA0_AWR_TC_AWL_MASK (0xFFF000000000000U) |
#define | CAAM_DMA0_AWR_TC_AWL_SHIFT (48U) |
#define | CAAM_DMA0_AWR_TC_AWL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWL_SHIFT)) & CAAM_DMA0_AWR_TC_AWL_MASK) |
#define | CAAM_DMA0_AWR_TC_AWTT_MASK (0x2000000000000000U) |
#define | CAAM_DMA0_AWR_TC_AWTT_SHIFT (61U) |
#define | CAAM_DMA0_AWR_TC_AWTT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTT_SHIFT)) & CAAM_DMA0_AWR_TC_AWTT_MASK) |
#define | CAAM_DMA0_AWR_TC_AWCT_MASK (0x4000000000000000U) |
#define | CAAM_DMA0_AWR_TC_AWCT_SHIFT (62U) |
#define | CAAM_DMA0_AWR_TC_AWCT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWCT_SHIFT)) & CAAM_DMA0_AWR_TC_AWCT_MASK) |
#define | CAAM_DMA0_AWR_TC_AWTCE_MASK (0x8000000000000000U) |
#define | CAAM_DMA0_AWR_TC_AWTCE_SHIFT (63U) |
#define | CAAM_DMA0_AWR_TC_AWTCE(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTCE_SHIFT)) & CAAM_DMA0_AWR_TC_AWTCE_MASK) |
DMA0_AWR_LAT - DMA0 Write Timing Check Latency Register | |
#define | CAAM_DMA0_AWR_LAT_SAWL_MASK (0xFFFFFFFFU) |
#define | CAAM_DMA0_AWR_LAT_SAWL_SHIFT (0U) |
#define | CAAM_DMA0_AWR_LAT_SAWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AWR_LAT_SAWL_SHIFT)) & CAAM_DMA0_AWR_LAT_SAWL_MASK) |
MPPKR - Manufacturing Protection Private Key Register | |
#define | CAAM_MPPKR_MPPrivK_MASK (0xFFU) |
#define | CAAM_MPPKR_MPPrivK_SHIFT (0U) |
#define | CAAM_MPPKR_MPPrivK(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPPKR_MPPrivK_SHIFT)) & CAAM_MPPKR_MPPrivK_MASK) |
MPMR - Manufacturing Protection Message Register | |
#define | CAAM_MPMR_MPMSG_MASK (0xFFU) |
#define | CAAM_MPMR_MPMSG_SHIFT (0U) |
#define | CAAM_MPMR_MPMSG(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPMR_MPMSG_SHIFT)) & CAAM_MPMR_MPMSG_MASK) |
MPTESTR - Manufacturing Protection Test Register | |
#define | CAAM_MPTESTR_TEST_VALUE_MASK (0xFFU) |
#define | CAAM_MPTESTR_TEST_VALUE_SHIFT (0U) |
#define | CAAM_MPTESTR_TEST_VALUE(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPTESTR_TEST_VALUE_SHIFT)) & CAAM_MPTESTR_TEST_VALUE_MASK) |
MPECC - Manufacturing Protection ECC Register | |
#define | CAAM_MPECC_MP_SYNDROME_MASK (0x1FF0000U) |
#define | CAAM_MPECC_MP_SYNDROME_SHIFT (16U) |
#define | CAAM_MPECC_MP_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_SYNDROME_SHIFT)) & CAAM_MPECC_MP_SYNDROME_MASK) |
#define | CAAM_MPECC_MP_ZERO_MASK (0x8000000U) |
#define | CAAM_MPECC_MP_ZERO_SHIFT (27U) |
#define | CAAM_MPECC_MP_ZERO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_ZERO_SHIFT)) & CAAM_MPECC_MP_ZERO_MASK) |
JDKEKR - Job Descriptor Key Encryption Key Register | |
#define | CAAM_JDKEKR_JDKEK_MASK (0xFFFFFFFFU) |
#define | CAAM_JDKEKR_JDKEK_SHIFT (0U) |
#define | CAAM_JDKEKR_JDKEK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JDKEKR_JDKEK_SHIFT)) & CAAM_JDKEKR_JDKEK_MASK) |
TDKEKR - Trusted Descriptor Key Encryption Key Register | |
#define | CAAM_TDKEKR_TDKEK_MASK (0xFFFFFFFFU) |
#define | CAAM_TDKEKR_TDKEK_SHIFT (0U) |
#define | CAAM_TDKEKR_TDKEK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_TDKEKR_TDKEK_SHIFT)) & CAAM_TDKEKR_TDKEK_MASK) |
TDSKR - Trusted Descriptor Signing Key Register | |
#define | CAAM_TDSKR_TDSK_MASK (0xFFFFFFFFU) |
#define | CAAM_TDSKR_TDSK_SHIFT (0U) |
#define | CAAM_TDSKR_TDSK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_TDSKR_TDSK_SHIFT)) & CAAM_TDSKR_TDSK_MASK) |
SKNR - Secure Key Nonce Register | |
#define | CAAM_SKNR_SK_NONCE_LS_MASK (0xFFFFFFFFU) |
#define | CAAM_SKNR_SK_NONCE_LS_SHIFT (0U) |
#define | CAAM_SKNR_SK_NONCE_LS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_LS_SHIFT)) & CAAM_SKNR_SK_NONCE_LS_MASK) |
#define | CAAM_SKNR_SK_NONCE_MS_MASK (0x7FFF00000000U) |
#define | CAAM_SKNR_SK_NONCE_MS_SHIFT (32U) |
#define | CAAM_SKNR_SK_NONCE_MS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_MS_SHIFT)) & CAAM_SKNR_SK_NONCE_MS_MASK) |
DMA_STA - DMA Status Register | |
#define | CAAM_DMA_STA_DMA0_ETIF_MASK (0x1FU) |
#define | CAAM_DMA_STA_DMA0_ETIF_SHIFT (0U) |
#define | CAAM_DMA_STA_DMA0_ETIF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ETIF_SHIFT)) & CAAM_DMA_STA_DMA0_ETIF_MASK) |
#define | CAAM_DMA_STA_DMA0_ITIF_MASK (0x20U) |
#define | CAAM_DMA_STA_DMA0_ITIF_SHIFT (5U) |
#define | CAAM_DMA_STA_DMA0_ITIF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ITIF_SHIFT)) & CAAM_DMA_STA_DMA0_ITIF_MASK) |
#define | CAAM_DMA_STA_DMA0_IDLE_MASK (0x80U) |
#define | CAAM_DMA_STA_DMA0_IDLE_SHIFT (7U) |
#define | CAAM_DMA_STA_DMA0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_IDLE_SHIFT)) & CAAM_DMA_STA_DMA0_IDLE_MASK) |
DMA_X_AID_7_4_MAP - DMA_X_AID_7_4_MAP | |
#define | CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK (0xFFU) |
#define | CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT (0U) |
#define | CAAM_DMA_X_AID_7_4_MAP_AID4_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK) |
#define | CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK (0xFF00U) |
#define | CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT (8U) |
#define | CAAM_DMA_X_AID_7_4_MAP_AID5_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK) |
#define | CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK (0xFF0000U) |
#define | CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT (16U) |
#define | CAAM_DMA_X_AID_7_4_MAP_AID6_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK) |
#define | CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK (0xFF000000U) |
#define | CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT (24U) |
#define | CAAM_DMA_X_AID_7_4_MAP_AID7_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK) |
DMA_X_AID_3_0_MAP - DMA_X_AID_3_0_MAP | |
#define | CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK (0xFFU) |
#define | CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT (0U) |
#define | CAAM_DMA_X_AID_3_0_MAP_AID0_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK) |
#define | CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK (0xFF00U) |
#define | CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT (8U) |
#define | CAAM_DMA_X_AID_3_0_MAP_AID1_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK) |
#define | CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK (0xFF0000U) |
#define | CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT (16U) |
#define | CAAM_DMA_X_AID_3_0_MAP_AID2_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK) |
#define | CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK (0xFF000000U) |
#define | CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT (24U) |
#define | CAAM_DMA_X_AID_3_0_MAP_AID3_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK) |
DMA_X_AID_15_12_MAP - DMA_X_AID_15_12_MAP | |
#define | CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK (0xFFU) |
#define | CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT (0U) |
#define | CAAM_DMA_X_AID_15_12_MAP_AID12_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK) |
#define | CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK (0xFF00U) |
#define | CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT (8U) |
#define | CAAM_DMA_X_AID_15_12_MAP_AID13_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK) |
#define | CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK (0xFF0000U) |
#define | CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT (16U) |
#define | CAAM_DMA_X_AID_15_12_MAP_AID14_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK) |
#define | CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK (0xFF000000U) |
#define | CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT (24U) |
#define | CAAM_DMA_X_AID_15_12_MAP_AID15_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK) |
DMA_X_AID_11_8_MAP - DMA_X_AID_11_8_MAP | |
#define | CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK (0xFFU) |
#define | CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT (0U) |
#define | CAAM_DMA_X_AID_11_8_MAP_AID8_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK) |
#define | CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK (0xFF00U) |
#define | CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT (8U) |
#define | CAAM_DMA_X_AID_11_8_MAP_AID9_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK) |
#define | CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK (0xFF0000U) |
#define | CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT (16U) |
#define | CAAM_DMA_X_AID_11_8_MAP_AID10_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK) |
#define | CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK (0xFF000000U) |
#define | CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT (24U) |
#define | CAAM_DMA_X_AID_11_8_MAP_AID11_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK) |
DMA_X_AID_15_0_EN - DMA_X AXI ID Map Enable Register | |
#define | CAAM_DMA_X_AID_15_0_EN_AID0E_MASK (0x1U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT (0U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID0E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID0E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID1E_MASK (0x2U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT (1U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID1E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID1E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID2E_MASK (0x4U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT (2U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID2E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID2E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID3E_MASK (0x8U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT (3U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID3E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID3E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID4E_MASK (0x10U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT (4U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID4E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID4E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID5E_MASK (0x20U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT (5U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID5E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID5E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID6E_MASK (0x40U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT (6U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID6E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID6E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID7E_MASK (0x80U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT (7U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID7E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID7E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID8E_MASK (0x100U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT (8U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID8E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID8E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID9E_MASK (0x200U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT (9U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID9E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID9E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID10E_MASK (0x400U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT (10U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID10E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID10E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID11E_MASK (0x800U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT (11U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID11E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID11E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID12E_MASK (0x1000U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT (12U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID12E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID12E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID13E_MASK (0x2000U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT (13U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID13E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID13E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID14E_MASK (0x4000U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT (14U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID14E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID14E_MASK) |
#define | CAAM_DMA_X_AID_15_0_EN_AID15E_MASK (0x8000U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT (15U) |
#define | CAAM_DMA_X_AID_15_0_EN_AID15E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID15E_MASK) |
DMA_X_ARTC_CTL - DMA_X AXI Read Timing Check Control Register | |
#define | CAAM_DMA_X_ARTC_CTL_ART_MASK (0xFFFU) |
#define | CAAM_DMA_X_ARTC_CTL_ART_SHIFT (0U) |
#define | CAAM_DMA_X_ARTC_CTL_ART(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ART_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ART_MASK) |
#define | CAAM_DMA_X_ARTC_CTL_ARL_MASK (0xFFF0000U) |
#define | CAAM_DMA_X_ARTC_CTL_ARL_SHIFT (16U) |
#define | CAAM_DMA_X_ARTC_CTL_ARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARL_MASK) |
#define | CAAM_DMA_X_ARTC_CTL_ARTL_MASK (0x10000000U) |
#define | CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT (28U) |
#define | CAAM_DMA_X_ARTC_CTL_ARTL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTL_MASK) |
#define | CAAM_DMA_X_ARTC_CTL_ARTT_MASK (0x20000000U) |
#define | CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT (29U) |
#define | CAAM_DMA_X_ARTC_CTL_ARTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTT_MASK) |
#define | CAAM_DMA_X_ARTC_CTL_ARCT_MASK (0x40000000U) |
#define | CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT (30U) |
#define | CAAM_DMA_X_ARTC_CTL_ARCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARCT_MASK) |
#define | CAAM_DMA_X_ARTC_CTL_ARTCE_MASK (0x80000000U) |
#define | CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT (31U) |
#define | CAAM_DMA_X_ARTC_CTL_ARTCE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTCE_MASK) |
DMA_X_ARTC_LC - DMA_X AXI Read Timing Check Late Count Register | |
#define | CAAM_DMA_X_ARTC_LC_ARLC_MASK (0xFFFFFU) |
#define | CAAM_DMA_X_ARTC_LC_ARLC_SHIFT (0U) |
#define | CAAM_DMA_X_ARTC_LC_ARLC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LC_ARLC_SHIFT)) & CAAM_DMA_X_ARTC_LC_ARLC_MASK) |
DMA_X_ARTC_SC - DMA_X AXI Read Timing Check Sample Count Register | |
#define | CAAM_DMA_X_ARTC_SC_ARSC_MASK (0xFFFFFU) |
#define | CAAM_DMA_X_ARTC_SC_ARSC_SHIFT (0U) |
#define | CAAM_DMA_X_ARTC_SC_ARSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_SC_ARSC_SHIFT)) & CAAM_DMA_X_ARTC_SC_ARSC_MASK) |
DMA_X_ARTC_LAT - DMA_X Read Timing Check Latency Register | |
#define | CAAM_DMA_X_ARTC_LAT_SARL_MASK (0xFFFFFFFFU) |
#define | CAAM_DMA_X_ARTC_LAT_SARL_SHIFT (0U) |
#define | CAAM_DMA_X_ARTC_LAT_SARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LAT_SARL_SHIFT)) & CAAM_DMA_X_ARTC_LAT_SARL_MASK) |
DMA_X_AWTC_CTL - DMA_X AXI Write Timing Check Control Register | |
#define | CAAM_DMA_X_AWTC_CTL_AWT_MASK (0xFFFU) |
#define | CAAM_DMA_X_AWTC_CTL_AWT_SHIFT (0U) |
#define | CAAM_DMA_X_AWTC_CTL_AWT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWT_MASK) |
#define | CAAM_DMA_X_AWTC_CTL_AWL_MASK (0xFFF0000U) |
#define | CAAM_DMA_X_AWTC_CTL_AWL_SHIFT (16U) |
#define | CAAM_DMA_X_AWTC_CTL_AWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWL_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWL_MASK) |
#define | CAAM_DMA_X_AWTC_CTL_AWTT_MASK (0x20000000U) |
#define | CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT (29U) |
#define | CAAM_DMA_X_AWTC_CTL_AWTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTT_MASK) |
#define | CAAM_DMA_X_AWTC_CTL_AWCT_MASK (0x40000000U) |
#define | CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT (30U) |
#define | CAAM_DMA_X_AWTC_CTL_AWCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWCT_MASK) |
#define | CAAM_DMA_X_AWTC_CTL_AWTCE_MASK (0x80000000U) |
#define | CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT (31U) |
#define | CAAM_DMA_X_AWTC_CTL_AWTCE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTCE_MASK) |
DMA_X_AWTC_LC - DMA_X AXI Write Timing Check Late Count Register | |
#define | CAAM_DMA_X_AWTC_LC_AWLC_MASK (0xFFFFFU) |
#define | CAAM_DMA_X_AWTC_LC_AWLC_SHIFT (0U) |
#define | CAAM_DMA_X_AWTC_LC_AWLC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LC_AWLC_SHIFT)) & CAAM_DMA_X_AWTC_LC_AWLC_MASK) |
DMA_X_AWTC_SC - DMA_X AXI Write Timing Check Sample Count Register | |
#define | CAAM_DMA_X_AWTC_SC_AWSC_MASK (0xFFFFFU) |
#define | CAAM_DMA_X_AWTC_SC_AWSC_SHIFT (0U) |
#define | CAAM_DMA_X_AWTC_SC_AWSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_SC_AWSC_SHIFT)) & CAAM_DMA_X_AWTC_SC_AWSC_MASK) |
DMA_X_AWTC_LAT - DMA_X Write Timing Check Latency Register | |
#define | CAAM_DMA_X_AWTC_LAT_SAWL_MASK (0xFFFFFFFFU) |
#define | CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT (0U) |
#define | CAAM_DMA_X_AWTC_LAT_SAWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT)) & CAAM_DMA_X_AWTC_LAT_SAWL_MASK) |
RTMCTL - RNG TRNG Miscellaneous Control Register | |
#define | CAAM_RTMCTL_SAMP_MODE_MASK (0x3U) |
#define | CAAM_RTMCTL_SAMP_MODE_SHIFT (0U) |
#define | CAAM_RTMCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_SAMP_MODE_SHIFT)) & CAAM_RTMCTL_SAMP_MODE_MASK) |
#define | CAAM_RTMCTL_OSC_DIV_MASK (0xCU) |
#define | CAAM_RTMCTL_OSC_DIV_SHIFT (2U) |
#define | CAAM_RTMCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_OSC_DIV_SHIFT)) & CAAM_RTMCTL_OSC_DIV_MASK) |
#define | CAAM_RTMCTL_CLK_OUT_EN_MASK (0x10U) |
#define | CAAM_RTMCTL_CLK_OUT_EN_SHIFT (4U) |
#define | CAAM_RTMCTL_CLK_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_CLK_OUT_EN_SHIFT)) & CAAM_RTMCTL_CLK_OUT_EN_MASK) |
#define | CAAM_RTMCTL_TRNG_ACC_MASK (0x20U) |
#define | CAAM_RTMCTL_TRNG_ACC_SHIFT (5U) |
#define | CAAM_RTMCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TRNG_ACC_SHIFT)) & CAAM_RTMCTL_TRNG_ACC_MASK) |
#define | CAAM_RTMCTL_RST_DEF_MASK (0x40U) |
#define | CAAM_RTMCTL_RST_DEF_SHIFT (6U) |
#define | CAAM_RTMCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_RST_DEF_SHIFT)) & CAAM_RTMCTL_RST_DEF_MASK) |
#define | CAAM_RTMCTL_FORCE_SYSCLK_MASK (0x80U) |
#define | CAAM_RTMCTL_FORCE_SYSCLK_SHIFT (7U) |
#define | CAAM_RTMCTL_FORCE_SYSCLK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FORCE_SYSCLK_SHIFT)) & CAAM_RTMCTL_FORCE_SYSCLK_MASK) |
#define | CAAM_RTMCTL_FCT_FAIL_MASK (0x100U) |
#define | CAAM_RTMCTL_FCT_FAIL_SHIFT (8U) |
#define | CAAM_RTMCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_FAIL_SHIFT)) & CAAM_RTMCTL_FCT_FAIL_MASK) |
#define | CAAM_RTMCTL_FCT_VAL_MASK (0x200U) |
#define | CAAM_RTMCTL_FCT_VAL_SHIFT (9U) |
#define | CAAM_RTMCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_VAL_SHIFT)) & CAAM_RTMCTL_FCT_VAL_MASK) |
#define | CAAM_RTMCTL_ENT_VAL_MASK (0x400U) |
#define | CAAM_RTMCTL_ENT_VAL_SHIFT (10U) |
#define | CAAM_RTMCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ENT_VAL_SHIFT)) & CAAM_RTMCTL_ENT_VAL_MASK) |
#define | CAAM_RTMCTL_TST_OUT_MASK (0x800U) |
#define | CAAM_RTMCTL_TST_OUT_SHIFT (11U) |
#define | CAAM_RTMCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TST_OUT_SHIFT)) & CAAM_RTMCTL_TST_OUT_MASK) |
#define | CAAM_RTMCTL_ERR_MASK (0x1000U) |
#define | CAAM_RTMCTL_ERR_SHIFT (12U) |
#define | CAAM_RTMCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ERR_SHIFT)) & CAAM_RTMCTL_ERR_MASK) |
#define | CAAM_RTMCTL_TSTOP_OK_MASK (0x2000U) |
#define | CAAM_RTMCTL_TSTOP_OK_SHIFT (13U) |
#define | CAAM_RTMCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TSTOP_OK_SHIFT)) & CAAM_RTMCTL_TSTOP_OK_MASK) |
#define | CAAM_RTMCTL_PRGM_MASK (0x10000U) |
#define | CAAM_RTMCTL_PRGM_SHIFT (16U) |
#define | CAAM_RTMCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_PRGM_SHIFT)) & CAAM_RTMCTL_PRGM_MASK) |
RTSCMISC - RNG TRNG Statistical Check Miscellaneous Register | |
#define | CAAM_RTSCMISC_LRUN_MAX_MASK (0xFFU) |
#define | CAAM_RTSCMISC_LRUN_MAX_SHIFT (0U) |
#define | CAAM_RTSCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_LRUN_MAX_SHIFT)) & CAAM_RTSCMISC_LRUN_MAX_MASK) |
#define | CAAM_RTSCMISC_RTY_CNT_MASK (0xF0000U) |
#define | CAAM_RTSCMISC_RTY_CNT_SHIFT (16U) |
#define | CAAM_RTSCMISC_RTY_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_RTY_CNT_SHIFT)) & CAAM_RTSCMISC_RTY_CNT_MASK) |
RTPKRRNG - RNG TRNG Poker Range Register | |
#define | CAAM_RTPKRRNG_PKR_RNG_MASK (0xFFFFU) |
#define | CAAM_RTPKRRNG_PKR_RNG_SHIFT (0U) |
#define | CAAM_RTPKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRRNG_PKR_RNG_SHIFT)) & CAAM_RTPKRRNG_PKR_RNG_MASK) |
RTPKRMAX - RNG TRNG Poker Maximum Limit Register | |
#define | CAAM_RTPKRMAX_PKR_MAX_MASK (0xFFFFFFU) |
#define | CAAM_RTPKRMAX_PKR_MAX_SHIFT (0U) |
#define | CAAM_RTPKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRMAX_PKR_MAX_SHIFT)) & CAAM_RTPKRMAX_PKR_MAX_MASK) |
RTPKRSQ - RNG TRNG Poker Square Calculation Result Register | |
#define | CAAM_RTPKRSQ_PKR_SQ_MASK (0xFFFFFFU) |
#define | CAAM_RTPKRSQ_PKR_SQ_SHIFT (0U) |
#define | CAAM_RTPKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRSQ_PKR_SQ_SHIFT)) & CAAM_RTPKRSQ_PKR_SQ_MASK) |
RTSDCTL - RNG TRNG Seed Control Register | |
#define | CAAM_RTSDCTL_SAMP_SIZE_MASK (0xFFFFU) |
#define | CAAM_RTSDCTL_SAMP_SIZE_SHIFT (0U) |
#define | CAAM_RTSDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_SAMP_SIZE_SHIFT)) & CAAM_RTSDCTL_SAMP_SIZE_MASK) |
#define | CAAM_RTSDCTL_ENT_DLY_MASK (0xFFFF0000U) |
#define | CAAM_RTSDCTL_ENT_DLY_SHIFT (16U) |
#define | CAAM_RTSDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_ENT_DLY_SHIFT)) & CAAM_RTSDCTL_ENT_DLY_MASK) |
RTSBLIM - RNG TRNG Sparse Bit Limit Register | |
#define | CAAM_RTSBLIM_SB_LIM_MASK (0x3FFU) |
#define | CAAM_RTSBLIM_SB_LIM_SHIFT (0U) |
#define | CAAM_RTSBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSBLIM_SB_LIM_SHIFT)) & CAAM_RTSBLIM_SB_LIM_MASK) |
RTTOTSAM - RNG TRNG Total Samples Register | |
#define | CAAM_RTTOTSAM_TOT_SAM_MASK (0xFFFFFU) |
#define | CAAM_RTTOTSAM_TOT_SAM_SHIFT (0U) |
#define | CAAM_RTTOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTTOTSAM_TOT_SAM_SHIFT)) & CAAM_RTTOTSAM_TOT_SAM_MASK) |
RTFRQMIN - RNG TRNG Frequency Count Minimum Limit Register | |
#define | CAAM_RTFRQMIN_FRQ_MIN_MASK (0x3FFFFFU) |
#define | CAAM_RTFRQMIN_FRQ_MIN_SHIFT (0U) |
#define | CAAM_RTFRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMIN_FRQ_MIN_SHIFT)) & CAAM_RTFRQMIN_FRQ_MIN_MASK) |
RTFRQCNT - RNG TRNG Frequency Count Register | |
#define | CAAM_RTFRQCNT_FRQ_CNT_MASK (0x3FFFFFU) |
#define | CAAM_RTFRQCNT_FRQ_CNT_SHIFT (0U) |
#define | CAAM_RTFRQCNT_FRQ_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQCNT_FRQ_CNT_SHIFT)) & CAAM_RTFRQCNT_FRQ_CNT_MASK) |
RTSCMC - RNG TRNG Statistical Check Monobit Count Register | |
#define | CAAM_RTSCMC_MONO_CNT_MASK (0xFFFFU) |
#define | CAAM_RTSCMC_MONO_CNT_SHIFT (0U) |
#define | CAAM_RTSCMC_MONO_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMC_MONO_CNT_SHIFT)) & CAAM_RTSCMC_MONO_CNT_MASK) |
RTSCR1C - RNG TRNG Statistical Check Run Length 1 Count Register | |
#define | CAAM_RTSCR1C_R1_0_COUNT_MASK (0x7FFFU) |
#define | CAAM_RTSCR1C_R1_0_COUNT_SHIFT (0U) |
#define | CAAM_RTSCR1C_R1_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_0_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_0_COUNT_MASK) |
#define | CAAM_RTSCR1C_R1_1_COUNT_MASK (0x7FFF0000U) |
#define | CAAM_RTSCR1C_R1_1_COUNT_SHIFT (16U) |
#define | CAAM_RTSCR1C_R1_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_1_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_1_COUNT_MASK) |
RTSCR2C - RNG TRNG Statistical Check Run Length 2 Count Register | |
#define | CAAM_RTSCR2C_R2_0_COUNT_MASK (0x3FFFU) |
#define | CAAM_RTSCR2C_R2_0_COUNT_SHIFT (0U) |
#define | CAAM_RTSCR2C_R2_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_0_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_0_COUNT_MASK) |
#define | CAAM_RTSCR2C_R2_1_COUNT_MASK (0x3FFF0000U) |
#define | CAAM_RTSCR2C_R2_1_COUNT_SHIFT (16U) |
#define | CAAM_RTSCR2C_R2_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_1_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_1_COUNT_MASK) |
RTSCR3C - RNG TRNG Statistical Check Run Length 3 Count Register | |
#define | CAAM_RTSCR3C_R3_0_COUNT_MASK (0x1FFFU) |
#define | CAAM_RTSCR3C_R3_0_COUNT_SHIFT (0U) |
#define | CAAM_RTSCR3C_R3_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_0_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_0_COUNT_MASK) |
#define | CAAM_RTSCR3C_R3_1_COUNT_MASK (0x1FFF0000U) |
#define | CAAM_RTSCR3C_R3_1_COUNT_SHIFT (16U) |
#define | CAAM_RTSCR3C_R3_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_1_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_1_COUNT_MASK) |
RTSCR4C - RNG TRNG Statistical Check Run Length 4 Count Register | |
#define | CAAM_RTSCR4C_R4_0_COUNT_MASK (0xFFFU) |
#define | CAAM_RTSCR4C_R4_0_COUNT_SHIFT (0U) |
#define | CAAM_RTSCR4C_R4_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_0_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_0_COUNT_MASK) |
#define | CAAM_RTSCR4C_R4_1_COUNT_MASK (0xFFF0000U) |
#define | CAAM_RTSCR4C_R4_1_COUNT_SHIFT (16U) |
#define | CAAM_RTSCR4C_R4_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_1_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_1_COUNT_MASK) |
RTSCR5C - RNG TRNG Statistical Check Run Length 5 Count Register | |
#define | CAAM_RTSCR5C_R5_0_COUNT_MASK (0x7FFU) |
#define | CAAM_RTSCR5C_R5_0_COUNT_SHIFT (0U) |
#define | CAAM_RTSCR5C_R5_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_0_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_0_COUNT_MASK) |
#define | CAAM_RTSCR5C_R5_1_COUNT_MASK (0x7FF0000U) |
#define | CAAM_RTSCR5C_R5_1_COUNT_SHIFT (16U) |
#define | CAAM_RTSCR5C_R5_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_1_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_1_COUNT_MASK) |
RTSCR6PC - RNG TRNG Statistical Check Run Length 6+ Count Register | |
#define | CAAM_RTSCR6PC_R6P_0_COUNT_MASK (0x7FFU) |
#define | CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT (0U) |
#define | CAAM_RTSCR6PC_R6P_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_0_COUNT_MASK) |
#define | CAAM_RTSCR6PC_R6P_1_COUNT_MASK (0x7FF0000U) |
#define | CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT (16U) |
#define | CAAM_RTSCR6PC_R6P_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_1_COUNT_MASK) |
RTFRQMAX - RNG TRNG Frequency Count Maximum Limit Register | |
#define | CAAM_RTFRQMAX_FRQ_MAX_MASK (0x3FFFFFU) |
#define | CAAM_RTFRQMAX_FRQ_MAX_SHIFT (0U) |
#define | CAAM_RTFRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMAX_FRQ_MAX_SHIFT)) & CAAM_RTFRQMAX_FRQ_MAX_MASK) |
RTSCML - RNG TRNG Statistical Check Monobit Limit Register | |
#define | CAAM_RTSCML_MONO_MAX_MASK (0xFFFFU) |
#define | CAAM_RTSCML_MONO_MAX_SHIFT (0U) |
#define | CAAM_RTSCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_MAX_SHIFT)) & CAAM_RTSCML_MONO_MAX_MASK) |
#define | CAAM_RTSCML_MONO_RNG_MASK (0xFFFF0000U) |
#define | CAAM_RTSCML_MONO_RNG_SHIFT (16U) |
#define | CAAM_RTSCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_RNG_SHIFT)) & CAAM_RTSCML_MONO_RNG_MASK) |
RTSCR1L - RNG TRNG Statistical Check Run Length 1 Limit Register | |
#define | CAAM_RTSCR1L_RUN1_MAX_MASK (0x7FFFU) |
#define | CAAM_RTSCR1L_RUN1_MAX_SHIFT (0U) |
#define | CAAM_RTSCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_MAX_SHIFT)) & CAAM_RTSCR1L_RUN1_MAX_MASK) |
#define | CAAM_RTSCR1L_RUN1_RNG_MASK (0x7FFF0000U) |
#define | CAAM_RTSCR1L_RUN1_RNG_SHIFT (16U) |
#define | CAAM_RTSCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_RNG_SHIFT)) & CAAM_RTSCR1L_RUN1_RNG_MASK) |
RTSCR2L - RNG TRNG Statistical Check Run Length 2 Limit Register | |
#define | CAAM_RTSCR2L_RUN2_MAX_MASK (0x3FFFU) |
#define | CAAM_RTSCR2L_RUN2_MAX_SHIFT (0U) |
#define | CAAM_RTSCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_MAX_SHIFT)) & CAAM_RTSCR2L_RUN2_MAX_MASK) |
#define | CAAM_RTSCR2L_RUN2_RNG_MASK (0x3FFF0000U) |
#define | CAAM_RTSCR2L_RUN2_RNG_SHIFT (16U) |
#define | CAAM_RTSCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_RNG_SHIFT)) & CAAM_RTSCR2L_RUN2_RNG_MASK) |
RTSCR3L - RNG TRNG Statistical Check Run Length 3 Limit Register | |
#define | CAAM_RTSCR3L_RUN3_MAX_MASK (0x1FFFU) |
#define | CAAM_RTSCR3L_RUN3_MAX_SHIFT (0U) |
#define | CAAM_RTSCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_MAX_SHIFT)) & CAAM_RTSCR3L_RUN3_MAX_MASK) |
#define | CAAM_RTSCR3L_RUN3_RNG_MASK (0x1FFF0000U) |
#define | CAAM_RTSCR3L_RUN3_RNG_SHIFT (16U) |
#define | CAAM_RTSCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_RNG_SHIFT)) & CAAM_RTSCR3L_RUN3_RNG_MASK) |
RTSCR4L - RNG TRNG Statistical Check Run Length 4 Limit Register | |
#define | CAAM_RTSCR4L_RUN4_MAX_MASK (0xFFFU) |
#define | CAAM_RTSCR4L_RUN4_MAX_SHIFT (0U) |
#define | CAAM_RTSCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_MAX_SHIFT)) & CAAM_RTSCR4L_RUN4_MAX_MASK) |
#define | CAAM_RTSCR4L_RUN4_RNG_MASK (0xFFF0000U) |
#define | CAAM_RTSCR4L_RUN4_RNG_SHIFT (16U) |
#define | CAAM_RTSCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_RNG_SHIFT)) & CAAM_RTSCR4L_RUN4_RNG_MASK) |
RTSCR5L - RNG TRNG Statistical Check Run Length 5 Limit Register | |
#define | CAAM_RTSCR5L_RUN5_MAX_MASK (0x7FFU) |
#define | CAAM_RTSCR5L_RUN5_MAX_SHIFT (0U) |
#define | CAAM_RTSCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_MAX_SHIFT)) & CAAM_RTSCR5L_RUN5_MAX_MASK) |
#define | CAAM_RTSCR5L_RUN5_RNG_MASK (0x7FF0000U) |
#define | CAAM_RTSCR5L_RUN5_RNG_SHIFT (16U) |
#define | CAAM_RTSCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_RNG_SHIFT)) & CAAM_RTSCR5L_RUN5_RNG_MASK) |
RTSCR6PL - RNG TRNG Statistical Check Run Length 6+ Limit Register | |
#define | CAAM_RTSCR6PL_RUN6P_MAX_MASK (0x7FFU) |
#define | CAAM_RTSCR6PL_RUN6P_MAX_SHIFT (0U) |
#define | CAAM_RTSCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_MAX_SHIFT)) & CAAM_RTSCR6PL_RUN6P_MAX_MASK) |
#define | CAAM_RTSCR6PL_RUN6P_RNG_MASK (0x7FF0000U) |
#define | CAAM_RTSCR6PL_RUN6P_RNG_SHIFT (16U) |
#define | CAAM_RTSCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_RNG_SHIFT)) & CAAM_RTSCR6PL_RUN6P_RNG_MASK) |
RTSTATUS - RNG TRNG Status Register | |
#define | CAAM_RTSTATUS_F1BR0TF_MASK (0x1U) |
#define | CAAM_RTSTATUS_F1BR0TF_SHIFT (0U) |
#define | CAAM_RTSTATUS_F1BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR0TF_SHIFT)) & CAAM_RTSTATUS_F1BR0TF_MASK) |
#define | CAAM_RTSTATUS_F1BR1TF_MASK (0x2U) |
#define | CAAM_RTSTATUS_F1BR1TF_SHIFT (1U) |
#define | CAAM_RTSTATUS_F1BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR1TF_SHIFT)) & CAAM_RTSTATUS_F1BR1TF_MASK) |
#define | CAAM_RTSTATUS_F2BR0TF_MASK (0x4U) |
#define | CAAM_RTSTATUS_F2BR0TF_SHIFT (2U) |
#define | CAAM_RTSTATUS_F2BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR0TF_SHIFT)) & CAAM_RTSTATUS_F2BR0TF_MASK) |
#define | CAAM_RTSTATUS_F2BR1TF_MASK (0x8U) |
#define | CAAM_RTSTATUS_F2BR1TF_SHIFT (3U) |
#define | CAAM_RTSTATUS_F2BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR1TF_SHIFT)) & CAAM_RTSTATUS_F2BR1TF_MASK) |
#define | CAAM_RTSTATUS_F3BR01TF_MASK (0x10U) |
#define | CAAM_RTSTATUS_F3BR01TF_SHIFT (4U) |
#define | CAAM_RTSTATUS_F3BR01TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR01TF_SHIFT)) & CAAM_RTSTATUS_F3BR01TF_MASK) |
#define | CAAM_RTSTATUS_F3BR1TF_MASK (0x20U) |
#define | CAAM_RTSTATUS_F3BR1TF_SHIFT (5U) |
#define | CAAM_RTSTATUS_F3BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR1TF_SHIFT)) & CAAM_RTSTATUS_F3BR1TF_MASK) |
#define | CAAM_RTSTATUS_F4BR0TF_MASK (0x40U) |
#define | CAAM_RTSTATUS_F4BR0TF_SHIFT (6U) |
#define | CAAM_RTSTATUS_F4BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR0TF_SHIFT)) & CAAM_RTSTATUS_F4BR0TF_MASK) |
#define | CAAM_RTSTATUS_F4BR1TF_MASK (0x80U) |
#define | CAAM_RTSTATUS_F4BR1TF_SHIFT (7U) |
#define | CAAM_RTSTATUS_F4BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR1TF_SHIFT)) & CAAM_RTSTATUS_F4BR1TF_MASK) |
#define | CAAM_RTSTATUS_F5BR0TF_MASK (0x100U) |
#define | CAAM_RTSTATUS_F5BR0TF_SHIFT (8U) |
#define | CAAM_RTSTATUS_F5BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR0TF_SHIFT)) & CAAM_RTSTATUS_F5BR0TF_MASK) |
#define | CAAM_RTSTATUS_F5BR1TF_MASK (0x200U) |
#define | CAAM_RTSTATUS_F5BR1TF_SHIFT (9U) |
#define | CAAM_RTSTATUS_F5BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR1TF_SHIFT)) & CAAM_RTSTATUS_F5BR1TF_MASK) |
#define | CAAM_RTSTATUS_F6PBR0TF_MASK (0x400U) |
#define | CAAM_RTSTATUS_F6PBR0TF_SHIFT (10U) |
#define | CAAM_RTSTATUS_F6PBR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR0TF_SHIFT)) & CAAM_RTSTATUS_F6PBR0TF_MASK) |
#define | CAAM_RTSTATUS_F6PBR1TF_MASK (0x800U) |
#define | CAAM_RTSTATUS_F6PBR1TF_SHIFT (11U) |
#define | CAAM_RTSTATUS_F6PBR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR1TF_SHIFT)) & CAAM_RTSTATUS_F6PBR1TF_MASK) |
#define | CAAM_RTSTATUS_FSBTF_MASK (0x1000U) |
#define | CAAM_RTSTATUS_FSBTF_SHIFT (12U) |
#define | CAAM_RTSTATUS_FSBTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FSBTF_SHIFT)) & CAAM_RTSTATUS_FSBTF_MASK) |
#define | CAAM_RTSTATUS_FLRTF_MASK (0x2000U) |
#define | CAAM_RTSTATUS_FLRTF_SHIFT (13U) |
#define | CAAM_RTSTATUS_FLRTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FLRTF_SHIFT)) & CAAM_RTSTATUS_FLRTF_MASK) |
#define | CAAM_RTSTATUS_FPTF_MASK (0x4000U) |
#define | CAAM_RTSTATUS_FPTF_SHIFT (14U) |
#define | CAAM_RTSTATUS_FPTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FPTF_SHIFT)) & CAAM_RTSTATUS_FPTF_MASK) |
#define | CAAM_RTSTATUS_FMBTF_MASK (0x8000U) |
#define | CAAM_RTSTATUS_FMBTF_SHIFT (15U) |
#define | CAAM_RTSTATUS_FMBTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FMBTF_SHIFT)) & CAAM_RTSTATUS_FMBTF_MASK) |
#define | CAAM_RTSTATUS_RETRY_COUNT_MASK (0xF0000U) |
#define | CAAM_RTSTATUS_RETRY_COUNT_SHIFT (16U) |
#define | CAAM_RTSTATUS_RETRY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_RETRY_COUNT_SHIFT)) & CAAM_RTSTATUS_RETRY_COUNT_MASK) |
RTENT - RNG TRNG Entropy Read Register | |
#define | CAAM_RTENT_ENT_MASK (0xFFFFFFFFU) |
#define | CAAM_RTENT_ENT_SHIFT (0U) |
#define | CAAM_RTENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTENT_ENT_SHIFT)) & CAAM_RTENT_ENT_MASK) |
RTPKRCNT10 - RNG TRNG Statistical Check Poker Count 1 and 0 Register | |
#define | CAAM_RTPKRCNT10_PKR_0_CNT_MASK (0xFFFFU) |
#define | CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT (0U) |
#define | CAAM_RTPKRCNT10_PKR_0_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_0_CNT_MASK) |
#define | CAAM_RTPKRCNT10_PKR_1_CNT_MASK (0xFFFF0000U) |
#define | CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT (16U) |
#define | CAAM_RTPKRCNT10_PKR_1_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_1_CNT_MASK) |
RTPKRCNT32 - RNG TRNG Statistical Check Poker Count 3 and 2 Register | |
#define | CAAM_RTPKRCNT32_PKR_2_CNT_MASK (0xFFFFU) |
#define | CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT (0U) |
#define | CAAM_RTPKRCNT32_PKR_2_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_2_CNT_MASK) |
#define | CAAM_RTPKRCNT32_PKR_3_CNT_MASK (0xFFFF0000U) |
#define | CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT (16U) |
#define | CAAM_RTPKRCNT32_PKR_3_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_3_CNT_MASK) |
RTPKRCNT54 - RNG TRNG Statistical Check Poker Count 5 and 4 Register | |
#define | CAAM_RTPKRCNT54_PKR_4_CNT_MASK (0xFFFFU) |
#define | CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT (0U) |
#define | CAAM_RTPKRCNT54_PKR_4_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_4_CNT_MASK) |
#define | CAAM_RTPKRCNT54_PKR_5_CNT_MASK (0xFFFF0000U) |
#define | CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT (16U) |
#define | CAAM_RTPKRCNT54_PKR_5_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_5_CNT_MASK) |
RTPKRCNT76 - RNG TRNG Statistical Check Poker Count 7 and 6 Register | |
#define | CAAM_RTPKRCNT76_PKR_6_CNT_MASK (0xFFFFU) |
#define | CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT (0U) |
#define | CAAM_RTPKRCNT76_PKR_6_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_6_CNT_MASK) |
#define | CAAM_RTPKRCNT76_PKR_7_CNT_MASK (0xFFFF0000U) |
#define | CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT (16U) |
#define | CAAM_RTPKRCNT76_PKR_7_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_7_CNT_MASK) |
RTPKRCNT98 - RNG TRNG Statistical Check Poker Count 9 and 8 Register | |
#define | CAAM_RTPKRCNT98_PKR_8_CNT_MASK (0xFFFFU) |
#define | CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT (0U) |
#define | CAAM_RTPKRCNT98_PKR_8_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_8_CNT_MASK) |
#define | CAAM_RTPKRCNT98_PKR_9_CNT_MASK (0xFFFF0000U) |
#define | CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT (16U) |
#define | CAAM_RTPKRCNT98_PKR_9_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_9_CNT_MASK) |
RTPKRCNTBA - RNG TRNG Statistical Check Poker Count B and A Register | |
#define | CAAM_RTPKRCNTBA_PKR_A_CNT_MASK (0xFFFFU) |
#define | CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT (0U) |
#define | CAAM_RTPKRCNTBA_PKR_A_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_A_CNT_MASK) |
#define | CAAM_RTPKRCNTBA_PKR_B_CNT_MASK (0xFFFF0000U) |
#define | CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT (16U) |
#define | CAAM_RTPKRCNTBA_PKR_B_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_B_CNT_MASK) |
RTPKRCNTDC - RNG TRNG Statistical Check Poker Count D and C Register | |
#define | CAAM_RTPKRCNTDC_PKR_C_CNT_MASK (0xFFFFU) |
#define | CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT (0U) |
#define | CAAM_RTPKRCNTDC_PKR_C_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_C_CNT_MASK) |
#define | CAAM_RTPKRCNTDC_PKR_D_CNT_MASK (0xFFFF0000U) |
#define | CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT (16U) |
#define | CAAM_RTPKRCNTDC_PKR_D_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_D_CNT_MASK) |
RTPKRCNTFE - RNG TRNG Statistical Check Poker Count F and E Register | |
#define | CAAM_RTPKRCNTFE_PKR_E_CNT_MASK (0xFFFFU) |
#define | CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT (0U) |
#define | CAAM_RTPKRCNTFE_PKR_E_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_E_CNT_MASK) |
#define | CAAM_RTPKRCNTFE_PKR_F_CNT_MASK (0xFFFF0000U) |
#define | CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT (16U) |
#define | CAAM_RTPKRCNTFE_PKR_F_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_F_CNT_MASK) |
RDSTA - RNG DRNG Status Register | |
#define | CAAM_RDSTA_IF0_MASK (0x1U) |
#define | CAAM_RDSTA_IF0_SHIFT (0U) |
#define | CAAM_RDSTA_IF0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF0_SHIFT)) & CAAM_RDSTA_IF0_MASK) |
#define | CAAM_RDSTA_IF1_MASK (0x2U) |
#define | CAAM_RDSTA_IF1_SHIFT (1U) |
#define | CAAM_RDSTA_IF1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF1_SHIFT)) & CAAM_RDSTA_IF1_MASK) |
#define | CAAM_RDSTA_PR0_MASK (0x10U) |
#define | CAAM_RDSTA_PR0_SHIFT (4U) |
#define | CAAM_RDSTA_PR0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR0_SHIFT)) & CAAM_RDSTA_PR0_MASK) |
#define | CAAM_RDSTA_PR1_MASK (0x20U) |
#define | CAAM_RDSTA_PR1_SHIFT (5U) |
#define | CAAM_RDSTA_PR1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR1_SHIFT)) & CAAM_RDSTA_PR1_MASK) |
#define | CAAM_RDSTA_TF0_MASK (0x100U) |
#define | CAAM_RDSTA_TF0_SHIFT (8U) |
#define | CAAM_RDSTA_TF0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF0_SHIFT)) & CAAM_RDSTA_TF0_MASK) |
#define | CAAM_RDSTA_TF1_MASK (0x200U) |
#define | CAAM_RDSTA_TF1_SHIFT (9U) |
#define | CAAM_RDSTA_TF1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF1_SHIFT)) & CAAM_RDSTA_TF1_MASK) |
#define | CAAM_RDSTA_ERRCODE_MASK (0xF0000U) |
#define | CAAM_RDSTA_ERRCODE_SHIFT (16U) |
#define | CAAM_RDSTA_ERRCODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_ERRCODE_SHIFT)) & CAAM_RDSTA_ERRCODE_MASK) |
#define | CAAM_RDSTA_CE_MASK (0x100000U) |
#define | CAAM_RDSTA_CE_SHIFT (20U) |
#define | CAAM_RDSTA_CE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_CE_SHIFT)) & CAAM_RDSTA_CE_MASK) |
#define | CAAM_RDSTA_SKVN_MASK (0x40000000U) |
#define | CAAM_RDSTA_SKVN_SHIFT (30U) |
#define | CAAM_RDSTA_SKVN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVN_SHIFT)) & CAAM_RDSTA_SKVN_MASK) |
#define | CAAM_RDSTA_SKVT_MASK (0x80000000U) |
#define | CAAM_RDSTA_SKVT_SHIFT (31U) |
#define | CAAM_RDSTA_SKVT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVT_SHIFT)) & CAAM_RDSTA_SKVT_MASK) |
RDINT0 - RNG DRNG State Handle 0 Reseed Interval Register | |
#define | CAAM_RDINT0_RESINT0_MASK (0xFFFFFFFFU) |
#define | CAAM_RDINT0_RESINT0_SHIFT (0U) |
#define | CAAM_RDINT0_RESINT0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT0_RESINT0_SHIFT)) & CAAM_RDINT0_RESINT0_MASK) |
RDINT1 - RNG DRNG State Handle 1 Reseed Interval Register | |
#define | CAAM_RDINT1_RESINT1_MASK (0xFFFFFFFFU) |
#define | CAAM_RDINT1_RESINT1_SHIFT (0U) |
#define | CAAM_RDINT1_RESINT1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT1_RESINT1_SHIFT)) & CAAM_RDINT1_RESINT1_MASK) |
RDHCNTL - RNG DRNG Hash Control Register | |
#define | CAAM_RDHCNTL_HD_MASK (0x1U) |
#define | CAAM_RDHCNTL_HD_SHIFT (0U) |
#define | CAAM_RDHCNTL_HD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HD_SHIFT)) & CAAM_RDHCNTL_HD_MASK) |
#define | CAAM_RDHCNTL_HB_MASK (0x2U) |
#define | CAAM_RDHCNTL_HB_SHIFT (1U) |
#define | CAAM_RDHCNTL_HB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HB_SHIFT)) & CAAM_RDHCNTL_HB_MASK) |
#define | CAAM_RDHCNTL_HI_MASK (0x4U) |
#define | CAAM_RDHCNTL_HI_SHIFT (2U) |
#define | CAAM_RDHCNTL_HI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HI_SHIFT)) & CAAM_RDHCNTL_HI_MASK) |
#define | CAAM_RDHCNTL_HTM_MASK (0x8U) |
#define | CAAM_RDHCNTL_HTM_SHIFT (3U) |
#define | CAAM_RDHCNTL_HTM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTM_SHIFT)) & CAAM_RDHCNTL_HTM_MASK) |
#define | CAAM_RDHCNTL_HTC_MASK (0x10U) |
#define | CAAM_RDHCNTL_HTC_SHIFT (4U) |
#define | CAAM_RDHCNTL_HTC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTC_SHIFT)) & CAAM_RDHCNTL_HTC_MASK) |
RDHDIG - RNG DRNG Hash Digest Register | |
#define | CAAM_RDHDIG_HASHMD_MASK (0xFFFFFFFFU) |
#define | CAAM_RDHDIG_HASHMD_SHIFT (0U) |
#define | CAAM_RDHDIG_HASHMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHDIG_HASHMD_SHIFT)) & CAAM_RDHDIG_HASHMD_MASK) |
RDHBUF - RNG DRNG Hash Buffer Register | |
#define | CAAM_RDHBUF_HASHBUF_MASK (0xFFFFFFFFU) |
#define | CAAM_RDHBUF_HASHBUF_SHIFT (0U) |
#define | CAAM_RDHBUF_HASHBUF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHBUF_HASHBUF_SHIFT)) & CAAM_RDHBUF_HASHBUF_MASK) |
PX_SDID_PG0 - Partition 0 SDID register..Partition 15 SDID register | |
#define | CAAM_PX_SDID_PG0_SDID_MASK (0xFFFFU) |
#define | CAAM_PX_SDID_PG0_SDID_SHIFT (0U) |
#define | CAAM_PX_SDID_PG0_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_PG0_SDID_SHIFT)) & CAAM_PX_SDID_PG0_SDID_MASK) |
PX_SMAPR_PG0 - Secure Memory Access Permissions register | |
#define | CAAM_PX_SMAPR_PG0_G1_READ_MASK (0x1U) |
#define | CAAM_PX_SMAPR_PG0_G1_READ_SHIFT (0U) |
#define | CAAM_PX_SMAPR_PG0_G1_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_READ_MASK) |
#define | CAAM_PX_SMAPR_PG0_G1_WRITE_MASK (0x2U) |
#define | CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT (1U) |
#define | CAAM_PX_SMAPR_PG0_G1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_WRITE_MASK) |
#define | CAAM_PX_SMAPR_PG0_G1_TDO_MASK (0x4U) |
#define | CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT (2U) |
#define | CAAM_PX_SMAPR_PG0_G1_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_TDO_MASK) |
#define | CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK (0x8U) |
#define | CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT (3U) |
#define | CAAM_PX_SMAPR_PG0_G1_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK) |
#define | CAAM_PX_SMAPR_PG0_G2_READ_MASK (0x10U) |
#define | CAAM_PX_SMAPR_PG0_G2_READ_SHIFT (4U) |
#define | CAAM_PX_SMAPR_PG0_G2_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_READ_MASK) |
#define | CAAM_PX_SMAPR_PG0_G2_WRITE_MASK (0x20U) |
#define | CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT (5U) |
#define | CAAM_PX_SMAPR_PG0_G2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_WRITE_MASK) |
#define | CAAM_PX_SMAPR_PG0_G2_TDO_MASK (0x40U) |
#define | CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT (6U) |
#define | CAAM_PX_SMAPR_PG0_G2_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_TDO_MASK) |
#define | CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK (0x80U) |
#define | CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT (7U) |
#define | CAAM_PX_SMAPR_PG0_G2_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK) |
#define | CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK (0x1000U) |
#define | CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT (12U) |
#define | CAAM_PX_SMAPR_PG0_SMAG_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK) |
#define | CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK (0x2000U) |
#define | CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT (13U) |
#define | CAAM_PX_SMAPR_PG0_SMAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK) |
#define | CAAM_PX_SMAPR_PG0_PSP_MASK (0x4000U) |
#define | CAAM_PX_SMAPR_PG0_PSP_SHIFT (14U) |
#define | CAAM_PX_SMAPR_PG0_PSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PSP_SHIFT)) & CAAM_PX_SMAPR_PG0_PSP_MASK) |
#define | CAAM_PX_SMAPR_PG0_CSP_MASK (0x8000U) |
#define | CAAM_PX_SMAPR_PG0_CSP_SHIFT (15U) |
#define | CAAM_PX_SMAPR_PG0_CSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_CSP_SHIFT)) & CAAM_PX_SMAPR_PG0_CSP_MASK) |
#define | CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK (0xFFFF0000U) |
#define | CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT (16U) |
#define | CAAM_PX_SMAPR_PG0_PARTITION_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK) |
PX_SMAG2_PG0 - Secure Memory Access Group Registers | |
#define | CAAM_PX_SMAG2_PG0_Gx_ID00_MASK (0x1U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT (0U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID00_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID01_MASK (0x2U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT (1U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID01_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID02_MASK (0x4U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT (2U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID02_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID03_MASK (0x8U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT (3U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID03_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID04_MASK (0x10U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT (4U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID04_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID05_MASK (0x20U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT (5U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID05_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID06_MASK (0x40U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT (6U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID06_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID07_MASK (0x80U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT (7U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID07_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID08_MASK (0x100U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT (8U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID08_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID09_MASK (0x200U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT (9U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID09_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID10_MASK (0x400U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT (10U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID10_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID11_MASK (0x800U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT (11U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID11_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID12_MASK (0x1000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT (12U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID12_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID13_MASK (0x2000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT (13U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID13_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID14_MASK (0x4000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT (14U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID14_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID15_MASK (0x8000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT (15U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID15_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID16_MASK (0x10000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT (16U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID16_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID17_MASK (0x20000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT (17U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID17_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID18_MASK (0x40000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT (18U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID18_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID19_MASK (0x80000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT (19U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID19_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID20_MASK (0x100000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT (20U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID20_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID21_MASK (0x200000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT (21U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID21_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID22_MASK (0x400000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT (22U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID22_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID23_MASK (0x800000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT (23U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID23_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID24_MASK (0x1000000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT (24U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID24_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID25_MASK (0x2000000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT (25U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID25_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID26_MASK (0x4000000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT (26U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID26_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID27_MASK (0x8000000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT (27U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID27_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID28_MASK (0x10000000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT (28U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID28_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID29_MASK (0x20000000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT (29U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID29_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID30_MASK (0x40000000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT (30U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID30_MASK) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID31_MASK (0x80000000U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT (31U) |
#define | CAAM_PX_SMAG2_PG0_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID31_MASK) |
PX_SMAG1_PG0 - Secure Memory Access Group Registers | |
#define | CAAM_PX_SMAG1_PG0_Gx_ID00_MASK (0x1U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT (0U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID00_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID01_MASK (0x2U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT (1U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID01_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID02_MASK (0x4U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT (2U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID02_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID03_MASK (0x8U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT (3U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID03_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID04_MASK (0x10U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT (4U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID04_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID05_MASK (0x20U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT (5U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID05_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID06_MASK (0x40U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT (6U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID06_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID07_MASK (0x80U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT (7U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID07_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID08_MASK (0x100U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT (8U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID08_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID09_MASK (0x200U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT (9U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID09_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID10_MASK (0x400U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT (10U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID10_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID11_MASK (0x800U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT (11U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID11_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID12_MASK (0x1000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT (12U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID12_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID13_MASK (0x2000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT (13U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID13_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID14_MASK (0x4000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT (14U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID14_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID15_MASK (0x8000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT (15U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID15_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID16_MASK (0x10000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT (16U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID16_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID17_MASK (0x20000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT (17U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID17_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID18_MASK (0x40000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT (18U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID18_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID19_MASK (0x80000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT (19U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID19_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID20_MASK (0x100000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT (20U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID20_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID21_MASK (0x200000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT (21U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID21_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID22_MASK (0x400000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT (22U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID22_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID23_MASK (0x800000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT (23U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID23_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID24_MASK (0x1000000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT (24U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID24_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID25_MASK (0x2000000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT (25U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID25_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID26_MASK (0x4000000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT (26U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID26_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID27_MASK (0x8000000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT (27U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID27_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID28_MASK (0x10000000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT (28U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID28_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID29_MASK (0x20000000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT (29U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID29_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID30_MASK (0x40000000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT (30U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID30_MASK) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID31_MASK (0x80000000U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT (31U) |
#define | CAAM_PX_SMAG1_PG0_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID31_MASK) |
REIS - Recoverable Error Interrupt Status | |
#define | CAAM_REIS_CWDE_MASK (0x1U) |
#define | CAAM_REIS_CWDE_SHIFT (0U) |
#define | CAAM_REIS_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_CWDE_SHIFT)) & CAAM_REIS_CWDE_MASK) |
#define | CAAM_REIS_RBAE_MASK (0x10000U) |
#define | CAAM_REIS_RBAE_SHIFT (16U) |
#define | CAAM_REIS_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_RBAE_SHIFT)) & CAAM_REIS_RBAE_MASK) |
#define | CAAM_REIS_JBAE0_MASK (0x1000000U) |
#define | CAAM_REIS_JBAE0_SHIFT (24U) |
#define | CAAM_REIS_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE0_SHIFT)) & CAAM_REIS_JBAE0_MASK) |
#define | CAAM_REIS_JBAE1_MASK (0x2000000U) |
#define | CAAM_REIS_JBAE1_SHIFT (25U) |
#define | CAAM_REIS_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE1_SHIFT)) & CAAM_REIS_JBAE1_MASK) |
#define | CAAM_REIS_JBAE2_MASK (0x4000000U) |
#define | CAAM_REIS_JBAE2_SHIFT (26U) |
#define | CAAM_REIS_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE2_SHIFT)) & CAAM_REIS_JBAE2_MASK) |
#define | CAAM_REIS_JBAE3_MASK (0x8000000U) |
#define | CAAM_REIS_JBAE3_SHIFT (27U) |
#define | CAAM_REIS_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE3_SHIFT)) & CAAM_REIS_JBAE3_MASK) |
REIE - Recoverable Error Interrupt Enable | |
#define | CAAM_REIE_CWDE_MASK (0x1U) |
#define | CAAM_REIE_CWDE_SHIFT (0U) |
#define | CAAM_REIE_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_CWDE_SHIFT)) & CAAM_REIE_CWDE_MASK) |
#define | CAAM_REIE_RBAE_MASK (0x10000U) |
#define | CAAM_REIE_RBAE_SHIFT (16U) |
#define | CAAM_REIE_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_RBAE_SHIFT)) & CAAM_REIE_RBAE_MASK) |
#define | CAAM_REIE_JBAE0_MASK (0x1000000U) |
#define | CAAM_REIE_JBAE0_SHIFT (24U) |
#define | CAAM_REIE_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE0_SHIFT)) & CAAM_REIE_JBAE0_MASK) |
#define | CAAM_REIE_JBAE1_MASK (0x2000000U) |
#define | CAAM_REIE_JBAE1_SHIFT (25U) |
#define | CAAM_REIE_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE1_SHIFT)) & CAAM_REIE_JBAE1_MASK) |
#define | CAAM_REIE_JBAE2_MASK (0x4000000U) |
#define | CAAM_REIE_JBAE2_SHIFT (26U) |
#define | CAAM_REIE_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE2_SHIFT)) & CAAM_REIE_JBAE2_MASK) |
#define | CAAM_REIE_JBAE3_MASK (0x8000000U) |
#define | CAAM_REIE_JBAE3_SHIFT (27U) |
#define | CAAM_REIE_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE3_SHIFT)) & CAAM_REIE_JBAE3_MASK) |
REIF - Recoverable Error Interrupt Force | |
#define | CAAM_REIF_CWDE_MASK (0x1U) |
#define | CAAM_REIF_CWDE_SHIFT (0U) |
#define | CAAM_REIF_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_CWDE_SHIFT)) & CAAM_REIF_CWDE_MASK) |
#define | CAAM_REIF_RBAE_MASK (0x10000U) |
#define | CAAM_REIF_RBAE_SHIFT (16U) |
#define | CAAM_REIF_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_RBAE_SHIFT)) & CAAM_REIF_RBAE_MASK) |
#define | CAAM_REIF_JBAE0_MASK (0x1000000U) |
#define | CAAM_REIF_JBAE0_SHIFT (24U) |
#define | CAAM_REIF_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE0_SHIFT)) & CAAM_REIF_JBAE0_MASK) |
#define | CAAM_REIF_JBAE1_MASK (0x2000000U) |
#define | CAAM_REIF_JBAE1_SHIFT (25U) |
#define | CAAM_REIF_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE1_SHIFT)) & CAAM_REIF_JBAE1_MASK) |
#define | CAAM_REIF_JBAE2_MASK (0x4000000U) |
#define | CAAM_REIF_JBAE2_SHIFT (26U) |
#define | CAAM_REIF_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE2_SHIFT)) & CAAM_REIF_JBAE2_MASK) |
#define | CAAM_REIF_JBAE3_MASK (0x8000000U) |
#define | CAAM_REIF_JBAE3_SHIFT (27U) |
#define | CAAM_REIF_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE3_SHIFT)) & CAAM_REIF_JBAE3_MASK) |
REIH - Recoverable Error Interrupt Halt | |
#define | CAAM_REIH_CWDE_MASK (0x1U) |
#define | CAAM_REIH_CWDE_SHIFT (0U) |
#define | CAAM_REIH_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_CWDE_SHIFT)) & CAAM_REIH_CWDE_MASK) |
#define | CAAM_REIH_RBAE_MASK (0x10000U) |
#define | CAAM_REIH_RBAE_SHIFT (16U) |
#define | CAAM_REIH_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_RBAE_SHIFT)) & CAAM_REIH_RBAE_MASK) |
#define | CAAM_REIH_JBAE0_MASK (0x1000000U) |
#define | CAAM_REIH_JBAE0_SHIFT (24U) |
#define | CAAM_REIH_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE0_SHIFT)) & CAAM_REIH_JBAE0_MASK) |
#define | CAAM_REIH_JBAE1_MASK (0x2000000U) |
#define | CAAM_REIH_JBAE1_SHIFT (25U) |
#define | CAAM_REIH_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE1_SHIFT)) & CAAM_REIH_JBAE1_MASK) |
#define | CAAM_REIH_JBAE2_MASK (0x4000000U) |
#define | CAAM_REIH_JBAE2_SHIFT (26U) |
#define | CAAM_REIH_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE2_SHIFT)) & CAAM_REIH_JBAE2_MASK) |
#define | CAAM_REIH_JBAE3_MASK (0x8000000U) |
#define | CAAM_REIH_JBAE3_SHIFT (27U) |
#define | CAAM_REIH_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE3_SHIFT)) & CAAM_REIH_JBAE3_MASK) |
SMWPJRR - Secure Memory Write Protect Job Ring Register | |
#define | CAAM_SMWPJRR_SMR_WP_JRa_MASK (0x1U) |
#define | CAAM_SMWPJRR_SMR_WP_JRa_SHIFT (0U) |
#define | CAAM_SMWPJRR_SMR_WP_JRa(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMWPJRR_SMR_WP_JRa_SHIFT)) & CAAM_SMWPJRR_SMR_WP_JRa_MASK) |
SMCR_PG0 - Secure Memory Command Register | |
#define | CAAM_SMCR_PG0_CMD_MASK (0xFU) |
#define | CAAM_SMCR_PG0_CMD_SHIFT (0U) |
#define | CAAM_SMCR_PG0_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_CMD_SHIFT)) & CAAM_SMCR_PG0_CMD_MASK) |
#define | CAAM_SMCR_PG0_PRTN_MASK (0xF00U) |
#define | CAAM_SMCR_PG0_PRTN_SHIFT (8U) |
#define | CAAM_SMCR_PG0_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PRTN_SHIFT)) & CAAM_SMCR_PG0_PRTN_MASK) |
#define | CAAM_SMCR_PG0_PAGE_MASK (0xFFFF0000U) |
#define | CAAM_SMCR_PG0_PAGE_SHIFT (16U) |
#define | CAAM_SMCR_PG0_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PAGE_SHIFT)) & CAAM_SMCR_PG0_PAGE_MASK) |
SMCSR_PG0 - Secure Memory Command Status Register | |
#define | CAAM_SMCSR_PG0_PRTN_MASK (0xFU) |
#define | CAAM_SMCSR_PG0_PRTN_SHIFT (0U) |
#define | CAAM_SMCSR_PG0_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PRTN_SHIFT)) & CAAM_SMCSR_PG0_PRTN_MASK) |
#define | CAAM_SMCSR_PG0_PO_MASK (0xC0U) |
#define | CAAM_SMCSR_PG0_PO_SHIFT (6U) |
#define | CAAM_SMCSR_PG0_PO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PO_SHIFT)) & CAAM_SMCSR_PG0_PO_MASK) |
#define | CAAM_SMCSR_PG0_AERR_MASK (0x3000U) |
#define | CAAM_SMCSR_PG0_AERR_SHIFT (12U) |
#define | CAAM_SMCSR_PG0_AERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_AERR_SHIFT)) & CAAM_SMCSR_PG0_AERR_MASK) |
#define | CAAM_SMCSR_PG0_CERR_MASK (0xC000U) |
#define | CAAM_SMCSR_PG0_CERR_SHIFT (14U) |
#define | CAAM_SMCSR_PG0_CERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_CERR_SHIFT)) & CAAM_SMCSR_PG0_CERR_MASK) |
#define | CAAM_SMCSR_PG0_PAGE_MASK (0xFFF0000U) |
#define | CAAM_SMCSR_PG0_PAGE_SHIFT (16U) |
#define | CAAM_SMCSR_PG0_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PAGE_SHIFT)) & CAAM_SMCSR_PG0_PAGE_MASK) |
CAAMVID_MS_TRAD - CAAM Version ID Register, most-significant half | |
#define | CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK (0xFFU) |
#define | CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT (0U) |
#define | CAAM_CAAMVID_MS_TRAD_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK) |
#define | CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK (0xFF00U) |
#define | CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT (8U) |
#define | CAAM_CAAMVID_MS_TRAD_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK) |
#define | CAAM_CAAMVID_MS_TRAD_IP_ID_MASK (0xFFFF0000U) |
#define | CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT (16U) |
#define | CAAM_CAAMVID_MS_TRAD_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT)) & CAAM_CAAMVID_MS_TRAD_IP_ID_MASK) |
CAAMVID_LS_TRAD - CAAM Version ID Register, least-significant half | |
#define | CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK (0xFFU) |
#define | CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT (0U) |
#define | CAAM_CAAMVID_LS_TRAD_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK) |
#define | CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK (0xFF00U) |
#define | CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT (8U) |
#define | CAAM_CAAMVID_LS_TRAD_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT)) & CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK) |
#define | CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK (0xFF0000U) |
#define | CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT (16U) |
#define | CAAM_CAAMVID_LS_TRAD_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK) |
#define | CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK (0xFF000000U) |
#define | CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT (24U) |
#define | CAAM_CAAMVID_LS_TRAD_COMPILE_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK) |
HT_JD_ADDR - Holding Tank 0 Job Descriptor Address | |
#define | CAAM_HT_JD_ADDR_JD_ADDR_MASK (0xFFFFFFFFFU) |
#define | CAAM_HT_JD_ADDR_JD_ADDR_SHIFT (0U) |
#define | CAAM_HT_JD_ADDR_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_HT_JD_ADDR_JD_ADDR_SHIFT)) & CAAM_HT_JD_ADDR_JD_ADDR_MASK) |
HT_SD_ADDR - Holding Tank 0 Shared Descriptor Address | |
#define | CAAM_HT_SD_ADDR_SD_ADDR_MASK (0xFFFFFFFFFU) |
#define | CAAM_HT_SD_ADDR_SD_ADDR_SHIFT (0U) |
#define | CAAM_HT_SD_ADDR_SD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_HT_SD_ADDR_SD_ADDR_SHIFT)) & CAAM_HT_SD_ADDR_SD_ADDR_MASK) |
HT_JQ_CTRL_MS - Holding Tank 0 Job Queue Control, most-significant half | |
#define | CAAM_HT_JQ_CTRL_MS_ID_MASK (0x7U) |
#define | CAAM_HT_JQ_CTRL_MS_ID_SHIFT (0U) |
#define | CAAM_HT_JQ_CTRL_MS_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ID_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ID_MASK) |
#define | CAAM_HT_JQ_CTRL_MS_SRC_MASK (0x700U) |
#define | CAAM_HT_JQ_CTRL_MS_SRC_SHIFT (8U) |
#define | CAAM_HT_JQ_CTRL_MS_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SRC_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SRC_MASK) |
#define | CAAM_HT_JQ_CTRL_MS_JDDS_MASK (0x4000U) |
#define | CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT (14U) |
#define | CAAM_HT_JQ_CTRL_MS_JDDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT)) & CAAM_HT_JQ_CTRL_MS_JDDS_MASK) |
#define | CAAM_HT_JQ_CTRL_MS_AMTD_MASK (0x8000U) |
#define | CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT (15U) |
#define | CAAM_HT_JQ_CTRL_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT)) & CAAM_HT_JQ_CTRL_MS_AMTD_MASK) |
#define | CAAM_HT_JQ_CTRL_MS_SOB_MASK (0x10000U) |
#define | CAAM_HT_JQ_CTRL_MS_SOB_SHIFT (16U) |
#define | CAAM_HT_JQ_CTRL_MS_SOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SOB_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SOB_MASK) |
#define | CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK (0x60000U) |
#define | CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT (17U) |
#define | CAAM_HT_JQ_CTRL_MS_HT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK) |
#define | CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK (0x80000U) |
#define | CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT (19U) |
#define | CAAM_HT_JQ_CTRL_MS_DWORD_SWAP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT)) & CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK) |
#define | CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK (0x7C00000U) |
#define | CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT (22U) |
#define | CAAM_HT_JQ_CTRL_MS_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK) |
#define | CAAM_HT_JQ_CTRL_MS_ILE_MASK (0x8000000U) |
#define | CAAM_HT_JQ_CTRL_MS_ILE_SHIFT (27U) |
#define | CAAM_HT_JQ_CTRL_MS_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ILE_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ILE_MASK) |
#define | CAAM_HT_JQ_CTRL_MS_FOUR_MASK (0x10000000U) |
#define | CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT (28U) |
#define | CAAM_HT_JQ_CTRL_MS_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_FOUR_MASK) |
#define | CAAM_HT_JQ_CTRL_MS_WHL_MASK (0x20000000U) |
#define | CAAM_HT_JQ_CTRL_MS_WHL_SHIFT (29U) |
#define | CAAM_HT_JQ_CTRL_MS_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_WHL_SHIFT)) & CAAM_HT_JQ_CTRL_MS_WHL_MASK) |
HT_JQ_CTRL_LS - Holding Tank 0 Job Queue Control, least-significant half | |
#define | CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK (0xFU) |
#define | CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT (0U) |
#define | CAAM_HT_JQ_CTRL_LS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK) |
#define | CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK (0x10U) |
#define | CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT (4U) |
#define | CAAM_HT_JQ_CTRL_LS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK) |
#define | CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK (0xFFE0U) |
#define | CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT (5U) |
#define | CAAM_HT_JQ_CTRL_LS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK) |
#define | CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK (0xF0000U) |
#define | CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT (16U) |
#define | CAAM_HT_JQ_CTRL_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK) |
#define | CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK (0xFFE00000U) |
#define | CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT (21U) |
#define | CAAM_HT_JQ_CTRL_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK) |
HT_STATUS - Holding Tank Status | |
#define | CAAM_HT_STATUS_PEND_0_MASK (0x1U) |
#define | CAAM_HT_STATUS_PEND_0_SHIFT (0U) |
#define | CAAM_HT_STATUS_PEND_0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_PEND_0_SHIFT)) & CAAM_HT_STATUS_PEND_0_MASK) |
#define | CAAM_HT_STATUS_IN_USE_MASK (0x40000000U) |
#define | CAAM_HT_STATUS_IN_USE_SHIFT (30U) |
#define | CAAM_HT_STATUS_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_IN_USE_SHIFT)) & CAAM_HT_STATUS_IN_USE_MASK) |
#define | CAAM_HT_STATUS_BC_MASK (0x80000000U) |
#define | CAAM_HT_STATUS_BC_SHIFT (31U) |
#define | CAAM_HT_STATUS_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_BC_SHIFT)) & CAAM_HT_STATUS_BC_MASK) |
JQ_DEBUG_SEL - Job Queue Debug Select Register | |
#define | CAAM_JQ_DEBUG_SEL_HT_SEL_MASK (0x1U) |
#define | CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT (0U) |
#define | CAAM_JQ_DEBUG_SEL_HT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT)) & CAAM_JQ_DEBUG_SEL_HT_SEL_MASK) |
#define | CAAM_JQ_DEBUG_SEL_JOB_ID_MASK (0x70000U) |
#define | CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT (16U) |
#define | CAAM_JQ_DEBUG_SEL_JOB_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT)) & CAAM_JQ_DEBUG_SEL_JOB_ID_MASK) |
JRJIDU_LS - Job Ring Job IDs in Use Register, least-significant half | |
#define | CAAM_JRJIDU_LS_JID00_MASK (0x1U) |
#define | CAAM_JRJIDU_LS_JID00_SHIFT (0U) |
#define | CAAM_JRJIDU_LS_JID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID00_SHIFT)) & CAAM_JRJIDU_LS_JID00_MASK) |
#define | CAAM_JRJIDU_LS_JID01_MASK (0x2U) |
#define | CAAM_JRJIDU_LS_JID01_SHIFT (1U) |
#define | CAAM_JRJIDU_LS_JID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID01_SHIFT)) & CAAM_JRJIDU_LS_JID01_MASK) |
#define | CAAM_JRJIDU_LS_JID02_MASK (0x4U) |
#define | CAAM_JRJIDU_LS_JID02_SHIFT (2U) |
#define | CAAM_JRJIDU_LS_JID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID02_SHIFT)) & CAAM_JRJIDU_LS_JID02_MASK) |
#define | CAAM_JRJIDU_LS_JID03_MASK (0x8U) |
#define | CAAM_JRJIDU_LS_JID03_SHIFT (3U) |
#define | CAAM_JRJIDU_LS_JID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID03_SHIFT)) & CAAM_JRJIDU_LS_JID03_MASK) |
JRJDJIFBC - Job Ring Job-Done Job ID FIFO BC | |
#define | CAAM_JRJDJIFBC_BC_MASK (0x80000000U) |
#define | CAAM_JRJDJIFBC_BC_SHIFT (31U) |
#define | CAAM_JRJDJIFBC_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIFBC_BC_SHIFT)) & CAAM_JRJDJIFBC_BC_MASK) |
JRJDJIF - Job Ring Job-Done Job ID FIFO | |
#define | CAAM_JRJDJIF_JOB_ID_ENTRY_MASK (0x7U) |
#define | CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT (0U) |
#define | CAAM_JRJDJIF_JOB_ID_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT)) & CAAM_JRJDJIF_JOB_ID_ENTRY_MASK) |
JRJDS1 - Job Ring Job-Done Source 1 | |
#define | CAAM_JRJDS1_SRC_MASK (0x3U) |
#define | CAAM_JRJDS1_SRC_SHIFT (0U) |
#define | CAAM_JRJDS1_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_SRC_SHIFT)) & CAAM_JRJDS1_SRC_MASK) |
#define | CAAM_JRJDS1_VALID_MASK (0x80000000U) |
#define | CAAM_JRJDS1_VALID_SHIFT (31U) |
#define | CAAM_JRJDS1_VALID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_VALID_SHIFT)) & CAAM_JRJDS1_VALID_MASK) |
JRJDDA - Job Ring Job-Done Descriptor Address 0 Register | |
#define | CAAM_JRJDDA_JD_ADDR_MASK (0xFFFFFFFFFU) |
#define | CAAM_JRJDDA_JD_ADDR_SHIFT (0U) |
#define | CAAM_JRJDDA_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_JRJDDA_JD_ADDR_SHIFT)) & CAAM_JRJDDA_JD_ADDR_MASK) |
CRNR_MS - CHA Revision Number Register, most-significant half | |
#define | CAAM_CRNR_MS_CRCRN_MASK (0xFU) |
#define | CAAM_CRNR_MS_CRCRN_SHIFT (0U) |
#define | CAAM_CRNR_MS_CRCRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_CRCRN_SHIFT)) & CAAM_CRNR_MS_CRCRN_MASK) |
#define | CAAM_CRNR_MS_SNW9RN_MASK (0xF0U) |
#define | CAAM_CRNR_MS_SNW9RN_SHIFT (4U) |
#define | CAAM_CRNR_MS_SNW9RN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_SNW9RN_SHIFT)) & CAAM_CRNR_MS_SNW9RN_MASK) |
#define | CAAM_CRNR_MS_ZERN_MASK (0xF00U) |
#define | CAAM_CRNR_MS_ZERN_SHIFT (8U) |
#define | CAAM_CRNR_MS_ZERN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZERN_SHIFT)) & CAAM_CRNR_MS_ZERN_MASK) |
#define | CAAM_CRNR_MS_ZARN_MASK (0xF000U) |
#define | CAAM_CRNR_MS_ZARN_SHIFT (12U) |
#define | CAAM_CRNR_MS_ZARN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZARN_SHIFT)) & CAAM_CRNR_MS_ZARN_MASK) |
#define | CAAM_CRNR_MS_DECORN_MASK (0xF000000U) |
#define | CAAM_CRNR_MS_DECORN_SHIFT (24U) |
#define | CAAM_CRNR_MS_DECORN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_DECORN_SHIFT)) & CAAM_CRNR_MS_DECORN_MASK) |
#define | CAAM_CRNR_MS_JRRN_MASK (0xF0000000U) |
#define | CAAM_CRNR_MS_JRRN_SHIFT (28U) |
#define | CAAM_CRNR_MS_JRRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_JRRN_SHIFT)) & CAAM_CRNR_MS_JRRN_MASK) |
CRNR_LS - CHA Revision Number Register, least-significant half | |
#define | CAAM_CRNR_LS_AESRN_MASK (0xFU) |
#define | CAAM_CRNR_LS_AESRN_SHIFT (0U) |
#define | CAAM_CRNR_LS_AESRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_AESRN_SHIFT)) & CAAM_CRNR_LS_AESRN_MASK) |
#define | CAAM_CRNR_LS_DESRN_MASK (0xF0U) |
#define | CAAM_CRNR_LS_DESRN_SHIFT (4U) |
#define | CAAM_CRNR_LS_DESRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_DESRN_SHIFT)) & CAAM_CRNR_LS_DESRN_MASK) |
#define | CAAM_CRNR_LS_MDRN_MASK (0xF000U) |
#define | CAAM_CRNR_LS_MDRN_SHIFT (12U) |
#define | CAAM_CRNR_LS_MDRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_MDRN_SHIFT)) & CAAM_CRNR_LS_MDRN_MASK) |
#define | CAAM_CRNR_LS_RNGRN_MASK (0xF0000U) |
#define | CAAM_CRNR_LS_RNGRN_SHIFT (16U) |
#define | CAAM_CRNR_LS_RNGRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_RNGRN_SHIFT)) & CAAM_CRNR_LS_RNGRN_MASK) |
#define | CAAM_CRNR_LS_SNW8RN_MASK (0xF00000U) |
#define | CAAM_CRNR_LS_SNW8RN_SHIFT (20U) |
#define | CAAM_CRNR_LS_SNW8RN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_SNW8RN_SHIFT)) & CAAM_CRNR_LS_SNW8RN_MASK) |
#define | CAAM_CRNR_LS_KASRN_MASK (0xF000000U) |
#define | CAAM_CRNR_LS_KASRN_SHIFT (24U) |
#define | CAAM_CRNR_LS_KASRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_KASRN_SHIFT)) & CAAM_CRNR_LS_KASRN_MASK) |
#define | CAAM_CRNR_LS_PKRN_MASK (0xF0000000U) |
#define | CAAM_CRNR_LS_PKRN_SHIFT (28U) |
#define | CAAM_CRNR_LS_PKRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_PKRN_SHIFT)) & CAAM_CRNR_LS_PKRN_MASK) |
CTPR_MS - Compile Time Parameters Register, most-significant half | |
#define | CAAM_CTPR_MS_VIRT_EN_INCL_MASK (0x1U) |
#define | CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT (0U) |
#define | CAAM_CTPR_MS_VIRT_EN_INCL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_INCL_MASK) |
#define | CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK (0x2U) |
#define | CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT (1U) |
#define | CAAM_CTPR_MS_VIRT_EN_POR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK) |
#define | CAAM_CTPR_MS_REG_PG_SIZE_MASK (0x10U) |
#define | CAAM_CTPR_MS_REG_PG_SIZE_SHIFT (4U) |
#define | CAAM_CTPR_MS_REG_PG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_REG_PG_SIZE_SHIFT)) & CAAM_CTPR_MS_REG_PG_SIZE_MASK) |
#define | CAAM_CTPR_MS_RNG_I_MASK (0x700U) |
#define | CAAM_CTPR_MS_RNG_I_SHIFT (8U) |
#define | CAAM_CTPR_MS_RNG_I(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_RNG_I_SHIFT)) & CAAM_CTPR_MS_RNG_I_MASK) |
#define | CAAM_CTPR_MS_AI_INCL_MASK (0x800U) |
#define | CAAM_CTPR_MS_AI_INCL_SHIFT (11U) |
#define | CAAM_CTPR_MS_AI_INCL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AI_INCL_SHIFT)) & CAAM_CTPR_MS_AI_INCL_MASK) |
#define | CAAM_CTPR_MS_DPAA2_MASK (0x2000U) |
#define | CAAM_CTPR_MS_DPAA2_SHIFT (13U) |
#define | CAAM_CTPR_MS_DPAA2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DPAA2_SHIFT)) & CAAM_CTPR_MS_DPAA2_MASK) |
#define | CAAM_CTPR_MS_IP_CLK_MASK (0x4000U) |
#define | CAAM_CTPR_MS_IP_CLK_SHIFT (14U) |
#define | CAAM_CTPR_MS_IP_CLK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_IP_CLK_SHIFT)) & CAAM_CTPR_MS_IP_CLK_MASK) |
#define | CAAM_CTPR_MS_MCFG_BURST_MASK (0x10000U) |
#define | CAAM_CTPR_MS_MCFG_BURST_SHIFT (16U) |
#define | CAAM_CTPR_MS_MCFG_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_BURST_SHIFT)) & CAAM_CTPR_MS_MCFG_BURST_MASK) |
#define | CAAM_CTPR_MS_MCFG_PS_MASK (0x20000U) |
#define | CAAM_CTPR_MS_MCFG_PS_SHIFT (17U) |
#define | CAAM_CTPR_MS_MCFG_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_PS_SHIFT)) & CAAM_CTPR_MS_MCFG_PS_MASK) |
#define | CAAM_CTPR_MS_SG8_MASK (0x40000U) |
#define | CAAM_CTPR_MS_SG8_SHIFT (18U) |
#define | CAAM_CTPR_MS_SG8(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_SG8_SHIFT)) & CAAM_CTPR_MS_SG8_MASK) |
#define | CAAM_CTPR_MS_PM_EVT_BUS_MASK (0x80000U) |
#define | CAAM_CTPR_MS_PM_EVT_BUS_SHIFT (19U) |
#define | CAAM_CTPR_MS_PM_EVT_BUS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PM_EVT_BUS_SHIFT)) & CAAM_CTPR_MS_PM_EVT_BUS_MASK) |
#define | CAAM_CTPR_MS_DECO_WD_MASK (0x100000U) |
#define | CAAM_CTPR_MS_DECO_WD_SHIFT (20U) |
#define | CAAM_CTPR_MS_DECO_WD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DECO_WD_SHIFT)) & CAAM_CTPR_MS_DECO_WD_MASK) |
#define | CAAM_CTPR_MS_PC_MASK (0x200000U) |
#define | CAAM_CTPR_MS_PC_SHIFT (21U) |
#define | CAAM_CTPR_MS_PC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PC_SHIFT)) & CAAM_CTPR_MS_PC_MASK) |
#define | CAAM_CTPR_MS_C1C2_MASK (0x800000U) |
#define | CAAM_CTPR_MS_C1C2_SHIFT (23U) |
#define | CAAM_CTPR_MS_C1C2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_C1C2_SHIFT)) & CAAM_CTPR_MS_C1C2_MASK) |
#define | CAAM_CTPR_MS_ACC_CTL_MASK (0x1000000U) |
#define | CAAM_CTPR_MS_ACC_CTL_SHIFT (24U) |
#define | CAAM_CTPR_MS_ACC_CTL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_ACC_CTL_SHIFT)) & CAAM_CTPR_MS_ACC_CTL_MASK) |
#define | CAAM_CTPR_MS_QI_MASK (0x2000000U) |
#define | CAAM_CTPR_MS_QI_SHIFT (25U) |
#define | CAAM_CTPR_MS_QI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_QI_SHIFT)) & CAAM_CTPR_MS_QI_MASK) |
#define | CAAM_CTPR_MS_AXI_PRI_MASK (0x4000000U) |
#define | CAAM_CTPR_MS_AXI_PRI_SHIFT (26U) |
#define | CAAM_CTPR_MS_AXI_PRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PRI_SHIFT)) & CAAM_CTPR_MS_AXI_PRI_MASK) |
#define | CAAM_CTPR_MS_AXI_LIODN_MASK (0x8000000U) |
#define | CAAM_CTPR_MS_AXI_LIODN_SHIFT (27U) |
#define | CAAM_CTPR_MS_AXI_LIODN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_LIODN_SHIFT)) & CAAM_CTPR_MS_AXI_LIODN_MASK) |
#define | CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK (0xF0000000U) |
#define | CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT (28U) |
#define | CAAM_CTPR_MS_AXI_PIPE_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT)) & CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK) |
CTPR_LS - Compile Time Parameters Register, least-significant half | |
#define | CAAM_CTPR_LS_KG_DS_MASK (0x1U) |
#define | CAAM_CTPR_LS_KG_DS_SHIFT (0U) |
#define | CAAM_CTPR_LS_KG_DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_KG_DS_SHIFT)) & CAAM_CTPR_LS_KG_DS_MASK) |
#define | CAAM_CTPR_LS_BLOB_MASK (0x2U) |
#define | CAAM_CTPR_LS_BLOB_SHIFT (1U) |
#define | CAAM_CTPR_LS_BLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_BLOB_SHIFT)) & CAAM_CTPR_LS_BLOB_MASK) |
#define | CAAM_CTPR_LS_WIFI_MASK (0x4U) |
#define | CAAM_CTPR_LS_WIFI_SHIFT (2U) |
#define | CAAM_CTPR_LS_WIFI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIFI_SHIFT)) & CAAM_CTPR_LS_WIFI_MASK) |
#define | CAAM_CTPR_LS_WIMAX_MASK (0x8U) |
#define | CAAM_CTPR_LS_WIMAX_SHIFT (3U) |
#define | CAAM_CTPR_LS_WIMAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIMAX_SHIFT)) & CAAM_CTPR_LS_WIMAX_MASK) |
#define | CAAM_CTPR_LS_SRTP_MASK (0x10U) |
#define | CAAM_CTPR_LS_SRTP_SHIFT (4U) |
#define | CAAM_CTPR_LS_SRTP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SRTP_SHIFT)) & CAAM_CTPR_LS_SRTP_MASK) |
#define | CAAM_CTPR_LS_IPSEC_MASK (0x20U) |
#define | CAAM_CTPR_LS_IPSEC_SHIFT (5U) |
#define | CAAM_CTPR_LS_IPSEC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IPSEC_SHIFT)) & CAAM_CTPR_LS_IPSEC_MASK) |
#define | CAAM_CTPR_LS_IKE_MASK (0x40U) |
#define | CAAM_CTPR_LS_IKE_SHIFT (6U) |
#define | CAAM_CTPR_LS_IKE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IKE_SHIFT)) & CAAM_CTPR_LS_IKE_MASK) |
#define | CAAM_CTPR_LS_SSL_TLS_MASK (0x80U) |
#define | CAAM_CTPR_LS_SSL_TLS_SHIFT (7U) |
#define | CAAM_CTPR_LS_SSL_TLS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SSL_TLS_SHIFT)) & CAAM_CTPR_LS_SSL_TLS_MASK) |
#define | CAAM_CTPR_LS_TLS_PRF_MASK (0x100U) |
#define | CAAM_CTPR_LS_TLS_PRF_SHIFT (8U) |
#define | CAAM_CTPR_LS_TLS_PRF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_TLS_PRF_SHIFT)) & CAAM_CTPR_LS_TLS_PRF_MASK) |
#define | CAAM_CTPR_LS_MACSEC_MASK (0x200U) |
#define | CAAM_CTPR_LS_MACSEC_SHIFT (9U) |
#define | CAAM_CTPR_LS_MACSEC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MACSEC_SHIFT)) & CAAM_CTPR_LS_MACSEC_MASK) |
#define | CAAM_CTPR_LS_RSA_MASK (0x400U) |
#define | CAAM_CTPR_LS_RSA_SHIFT (10U) |
#define | CAAM_CTPR_LS_RSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_RSA_SHIFT)) & CAAM_CTPR_LS_RSA_MASK) |
#define | CAAM_CTPR_LS_P3G_LTE_MASK (0x800U) |
#define | CAAM_CTPR_LS_P3G_LTE_SHIFT (11U) |
#define | CAAM_CTPR_LS_P3G_LTE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_P3G_LTE_SHIFT)) & CAAM_CTPR_LS_P3G_LTE_MASK) |
#define | CAAM_CTPR_LS_DBL_CRC_MASK (0x1000U) |
#define | CAAM_CTPR_LS_DBL_CRC_SHIFT (12U) |
#define | CAAM_CTPR_LS_DBL_CRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DBL_CRC_SHIFT)) & CAAM_CTPR_LS_DBL_CRC_MASK) |
#define | CAAM_CTPR_LS_MAN_PROT_MASK (0x2000U) |
#define | CAAM_CTPR_LS_MAN_PROT_SHIFT (13U) |
#define | CAAM_CTPR_LS_MAN_PROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MAN_PROT_SHIFT)) & CAAM_CTPR_LS_MAN_PROT_MASK) |
#define | CAAM_CTPR_LS_DKP_MASK (0x4000U) |
#define | CAAM_CTPR_LS_DKP_SHIFT (14U) |
#define | CAAM_CTPR_LS_DKP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DKP_SHIFT)) & CAAM_CTPR_LS_DKP_MASK) |
SMSTA - Secure Memory Status Register | |
#define | CAAM_SMSTA_STATE_MASK (0xFU) |
#define | CAAM_SMSTA_STATE_SHIFT (0U) |
#define | CAAM_SMSTA_STATE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_STATE_SHIFT)) & CAAM_SMSTA_STATE_MASK) |
#define | CAAM_SMSTA_ACCERR_MASK (0xF0U) |
#define | CAAM_SMSTA_ACCERR_SHIFT (4U) |
#define | CAAM_SMSTA_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_ACCERR_SHIFT)) & CAAM_SMSTA_ACCERR_MASK) |
#define | CAAM_SMSTA_DID_MASK (0xF00U) |
#define | CAAM_SMSTA_DID_SHIFT (8U) |
#define | CAAM_SMSTA_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_DID_SHIFT)) & CAAM_SMSTA_DID_MASK) |
#define | CAAM_SMSTA_NS_MASK (0x1000U) |
#define | CAAM_SMSTA_NS_SHIFT (12U) |
#define | CAAM_SMSTA_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_NS_SHIFT)) & CAAM_SMSTA_NS_MASK) |
#define | CAAM_SMSTA_SMR_WP_MASK (0x8000U) |
#define | CAAM_SMSTA_SMR_WP_SHIFT (15U) |
#define | CAAM_SMSTA_SMR_WP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_SMR_WP_SHIFT)) & CAAM_SMSTA_SMR_WP_MASK) |
#define | CAAM_SMSTA_PAGE_MASK (0x7FF0000U) |
#define | CAAM_SMSTA_PAGE_SHIFT (16U) |
#define | CAAM_SMSTA_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PAGE_SHIFT)) & CAAM_SMSTA_PAGE_MASK) |
#define | CAAM_SMSTA_PART_MASK (0xF0000000U) |
#define | CAAM_SMSTA_PART_SHIFT (28U) |
#define | CAAM_SMSTA_PART(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PART_SHIFT)) & CAAM_SMSTA_PART_MASK) |
SMPO - Secure Memory Partition Owners Register | |
#define | CAAM_SMPO_PO0_MASK (0x3U) |
#define | CAAM_SMPO_PO0_SHIFT (0U) |
#define | CAAM_SMPO_PO0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO0_SHIFT)) & CAAM_SMPO_PO0_MASK) |
#define | CAAM_SMPO_PO1_MASK (0xCU) |
#define | CAAM_SMPO_PO1_SHIFT (2U) |
#define | CAAM_SMPO_PO1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO1_SHIFT)) & CAAM_SMPO_PO1_MASK) |
#define | CAAM_SMPO_PO2_MASK (0x30U) |
#define | CAAM_SMPO_PO2_SHIFT (4U) |
#define | CAAM_SMPO_PO2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO2_SHIFT)) & CAAM_SMPO_PO2_MASK) |
#define | CAAM_SMPO_PO3_MASK (0xC0U) |
#define | CAAM_SMPO_PO3_SHIFT (6U) |
#define | CAAM_SMPO_PO3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO3_SHIFT)) & CAAM_SMPO_PO3_MASK) |
#define | CAAM_SMPO_PO4_MASK (0x300U) |
#define | CAAM_SMPO_PO4_SHIFT (8U) |
#define | CAAM_SMPO_PO4(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO4_SHIFT)) & CAAM_SMPO_PO4_MASK) |
#define | CAAM_SMPO_PO5_MASK (0xC00U) |
#define | CAAM_SMPO_PO5_SHIFT (10U) |
#define | CAAM_SMPO_PO5(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO5_SHIFT)) & CAAM_SMPO_PO5_MASK) |
#define | CAAM_SMPO_PO6_MASK (0x3000U) |
#define | CAAM_SMPO_PO6_SHIFT (12U) |
#define | CAAM_SMPO_PO6(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO6_SHIFT)) & CAAM_SMPO_PO6_MASK) |
#define | CAAM_SMPO_PO7_MASK (0xC000U) |
#define | CAAM_SMPO_PO7_SHIFT (14U) |
#define | CAAM_SMPO_PO7(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO7_SHIFT)) & CAAM_SMPO_PO7_MASK) |
#define | CAAM_SMPO_PO8_MASK (0x30000U) |
#define | CAAM_SMPO_PO8_SHIFT (16U) |
#define | CAAM_SMPO_PO8(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO8_SHIFT)) & CAAM_SMPO_PO8_MASK) |
#define | CAAM_SMPO_PO9_MASK (0xC0000U) |
#define | CAAM_SMPO_PO9_SHIFT (18U) |
#define | CAAM_SMPO_PO9(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO9_SHIFT)) & CAAM_SMPO_PO9_MASK) |
#define | CAAM_SMPO_PO10_MASK (0x300000U) |
#define | CAAM_SMPO_PO10_SHIFT (20U) |
#define | CAAM_SMPO_PO10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO10_SHIFT)) & CAAM_SMPO_PO10_MASK) |
#define | CAAM_SMPO_PO11_MASK (0xC00000U) |
#define | CAAM_SMPO_PO11_SHIFT (22U) |
#define | CAAM_SMPO_PO11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO11_SHIFT)) & CAAM_SMPO_PO11_MASK) |
#define | CAAM_SMPO_PO12_MASK (0x3000000U) |
#define | CAAM_SMPO_PO12_SHIFT (24U) |
#define | CAAM_SMPO_PO12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO12_SHIFT)) & CAAM_SMPO_PO12_MASK) |
#define | CAAM_SMPO_PO13_MASK (0xC000000U) |
#define | CAAM_SMPO_PO13_SHIFT (26U) |
#define | CAAM_SMPO_PO13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO13_SHIFT)) & CAAM_SMPO_PO13_MASK) |
#define | CAAM_SMPO_PO14_MASK (0x30000000U) |
#define | CAAM_SMPO_PO14_SHIFT (28U) |
#define | CAAM_SMPO_PO14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO14_SHIFT)) & CAAM_SMPO_PO14_MASK) |
#define | CAAM_SMPO_PO15_MASK (0xC0000000U) |
#define | CAAM_SMPO_PO15_SHIFT (30U) |
#define | CAAM_SMPO_PO15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO15_SHIFT)) & CAAM_SMPO_PO15_MASK) |
FAR - Fault Address Register | |
#define | CAAM_FAR_FAR_MASK (0xFFFFFFFFFU) |
#define | CAAM_FAR_FAR_SHIFT (0U) |
#define | CAAM_FAR_FAR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_FAR_FAR_SHIFT)) & CAAM_FAR_FAR_MASK) |
FADID - Fault Address DID Register | |
#define | CAAM_FADID_FDID_MASK (0xFU) |
#define | CAAM_FADID_FDID_SHIFT (0U) |
#define | CAAM_FADID_FDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FDID_SHIFT)) & CAAM_FADID_FDID_MASK) |
#define | CAAM_FADID_FNS_MASK (0x10U) |
#define | CAAM_FADID_FNS_SHIFT (4U) |
#define | CAAM_FADID_FNS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FNS_SHIFT)) & CAAM_FADID_FNS_MASK) |
#define | CAAM_FADID_FICID_MASK (0xFFE0U) |
#define | CAAM_FADID_FICID_SHIFT (5U) |
#define | CAAM_FADID_FICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FICID_SHIFT)) & CAAM_FADID_FICID_MASK) |
FADR - Fault Address Detail Register | |
#define | CAAM_FADR_FSZ_MASK (0x7FU) |
#define | CAAM_FADR_FSZ_SHIFT (0U) |
#define | CAAM_FADR_FSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_SHIFT)) & CAAM_FADR_FSZ_MASK) |
#define | CAAM_FADR_TYP_MASK (0x80U) |
#define | CAAM_FADR_TYP_SHIFT (7U) |
#define | CAAM_FADR_TYP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_TYP_SHIFT)) & CAAM_FADR_TYP_MASK) |
#define | CAAM_FADR_BLKID_MASK (0xF00U) |
#define | CAAM_FADR_BLKID_SHIFT (8U) |
#define | CAAM_FADR_BLKID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_BLKID_SHIFT)) & CAAM_FADR_BLKID_MASK) |
#define | CAAM_FADR_JSRC_MASK (0x7000U) |
#define | CAAM_FADR_JSRC_SHIFT (12U) |
#define | CAAM_FADR_JSRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_JSRC_SHIFT)) & CAAM_FADR_JSRC_MASK) |
#define | CAAM_FADR_DTYP_MASK (0x8000U) |
#define | CAAM_FADR_DTYP_SHIFT (15U) |
#define | CAAM_FADR_DTYP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_DTYP_SHIFT)) & CAAM_FADR_DTYP_MASK) |
#define | CAAM_FADR_FSZ_EXT_MASK (0x70000U) |
#define | CAAM_FADR_FSZ_EXT_SHIFT (16U) |
#define | CAAM_FADR_FSZ_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_EXT_SHIFT)) & CAAM_FADR_FSZ_EXT_MASK) |
#define | CAAM_FADR_FKMOD_MASK (0x1000000U) |
#define | CAAM_FADR_FKMOD_SHIFT (24U) |
#define | CAAM_FADR_FKMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKMOD_SHIFT)) & CAAM_FADR_FKMOD_MASK) |
#define | CAAM_FADR_FKEY_MASK (0x2000000U) |
#define | CAAM_FADR_FKEY_SHIFT (25U) |
#define | CAAM_FADR_FKEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKEY_SHIFT)) & CAAM_FADR_FKEY_MASK) |
#define | CAAM_FADR_FTDSC_MASK (0x4000000U) |
#define | CAAM_FADR_FTDSC_SHIFT (26U) |
#define | CAAM_FADR_FTDSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FTDSC_SHIFT)) & CAAM_FADR_FTDSC_MASK) |
#define | CAAM_FADR_FBNDG_MASK (0x8000000U) |
#define | CAAM_FADR_FBNDG_SHIFT (27U) |
#define | CAAM_FADR_FBNDG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FBNDG_SHIFT)) & CAAM_FADR_FBNDG_MASK) |
#define | CAAM_FADR_FNS_MASK (0x10000000U) |
#define | CAAM_FADR_FNS_SHIFT (28U) |
#define | CAAM_FADR_FNS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FNS_SHIFT)) & CAAM_FADR_FNS_MASK) |
#define | CAAM_FADR_FERR_MASK (0xC0000000U) |
#define | CAAM_FADR_FERR_SHIFT (30U) |
#define | CAAM_FADR_FERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FERR_SHIFT)) & CAAM_FADR_FERR_MASK) |
CSTA - CAAM Status Register | |
#define | CAAM_CSTA_BSY_MASK (0x1U) |
#define | CAAM_CSTA_BSY_SHIFT (0U) |
#define | CAAM_CSTA_BSY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_BSY_SHIFT)) & CAAM_CSTA_BSY_MASK) |
#define | CAAM_CSTA_IDLE_MASK (0x2U) |
#define | CAAM_CSTA_IDLE_SHIFT (1U) |
#define | CAAM_CSTA_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_IDLE_SHIFT)) & CAAM_CSTA_IDLE_MASK) |
#define | CAAM_CSTA_TRNG_IDLE_MASK (0x4U) |
#define | CAAM_CSTA_TRNG_IDLE_SHIFT (2U) |
#define | CAAM_CSTA_TRNG_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_TRNG_IDLE_SHIFT)) & CAAM_CSTA_TRNG_IDLE_MASK) |
#define | CAAM_CSTA_MOO_MASK (0x300U) |
#define | CAAM_CSTA_MOO_SHIFT (8U) |
#define | CAAM_CSTA_MOO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_MOO_SHIFT)) & CAAM_CSTA_MOO_MASK) |
#define | CAAM_CSTA_PLEND_MASK (0x400U) |
#define | CAAM_CSTA_PLEND_SHIFT (10U) |
#define | CAAM_CSTA_PLEND(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_PLEND_SHIFT)) & CAAM_CSTA_PLEND_MASK) |
SMVID_MS - Secure Memory Version ID Register, most-significant half | |
#define | CAAM_SMVID_MS_NPAG_MASK (0x3FFU) |
#define | CAAM_SMVID_MS_NPAG_SHIFT (0U) |
#define | CAAM_SMVID_MS_NPAG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPAG_SHIFT)) & CAAM_SMVID_MS_NPAG_MASK) |
#define | CAAM_SMVID_MS_NPRT_MASK (0xF000U) |
#define | CAAM_SMVID_MS_NPRT_SHIFT (12U) |
#define | CAAM_SMVID_MS_NPRT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPRT_SHIFT)) & CAAM_SMVID_MS_NPRT_MASK) |
#define | CAAM_SMVID_MS_MAX_NPAG_MASK (0x3FF0000U) |
#define | CAAM_SMVID_MS_MAX_NPAG_SHIFT (16U) |
#define | CAAM_SMVID_MS_MAX_NPAG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_MAX_NPAG_SHIFT)) & CAAM_SMVID_MS_MAX_NPAG_MASK) |
SMVID_LS - Secure Memory Version ID Register, least-significant half | |
#define | CAAM_SMVID_LS_SMNV_MASK (0xFFU) |
#define | CAAM_SMVID_LS_SMNV_SHIFT (0U) |
#define | CAAM_SMVID_LS_SMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMNV_SHIFT)) & CAAM_SMVID_LS_SMNV_MASK) |
#define | CAAM_SMVID_LS_SMJV_MASK (0xFF00U) |
#define | CAAM_SMVID_LS_SMJV_SHIFT (8U) |
#define | CAAM_SMVID_LS_SMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMJV_SHIFT)) & CAAM_SMVID_LS_SMJV_MASK) |
#define | CAAM_SMVID_LS_PSIZ_MASK (0x70000U) |
#define | CAAM_SMVID_LS_PSIZ_SHIFT (16U) |
#define | CAAM_SMVID_LS_PSIZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_PSIZ_SHIFT)) & CAAM_SMVID_LS_PSIZ_MASK) |
RVID - RTIC Version ID Register | |
#define | CAAM_RVID_RMNV_MASK (0xFFU) |
#define | CAAM_RVID_RMNV_SHIFT (0U) |
#define | CAAM_RVID_RMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMNV_SHIFT)) & CAAM_RVID_RMNV_MASK) |
#define | CAAM_RVID_RMJV_MASK (0xFF00U) |
#define | CAAM_RVID_RMJV_SHIFT (8U) |
#define | CAAM_RVID_RMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMJV_SHIFT)) & CAAM_RVID_RMJV_MASK) |
#define | CAAM_RVID_SHA_256_MASK (0x20000U) |
#define | CAAM_RVID_SHA_256_SHIFT (17U) |
#define | CAAM_RVID_SHA_256(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_256_SHIFT)) & CAAM_RVID_SHA_256_MASK) |
#define | CAAM_RVID_SHA_512_MASK (0x80000U) |
#define | CAAM_RVID_SHA_512_SHIFT (19U) |
#define | CAAM_RVID_SHA_512(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_512_SHIFT)) & CAAM_RVID_SHA_512_MASK) |
#define | CAAM_RVID_MA_MASK (0x1000000U) |
#define | CAAM_RVID_MA_SHIFT (24U) |
#define | CAAM_RVID_MA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MA_SHIFT)) & CAAM_RVID_MA_MASK) |
#define | CAAM_RVID_MB_MASK (0x2000000U) |
#define | CAAM_RVID_MB_SHIFT (25U) |
#define | CAAM_RVID_MB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MB_SHIFT)) & CAAM_RVID_MB_MASK) |
#define | CAAM_RVID_MC_MASK (0x4000000U) |
#define | CAAM_RVID_MC_SHIFT (26U) |
#define | CAAM_RVID_MC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MC_SHIFT)) & CAAM_RVID_MC_MASK) |
#define | CAAM_RVID_MD_MASK (0x8000000U) |
#define | CAAM_RVID_MD_SHIFT (27U) |
#define | CAAM_RVID_MD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MD_SHIFT)) & CAAM_RVID_MD_MASK) |
CCBVID - CHA Cluster Block Version ID Register | |
#define | CAAM_CCBVID_AMNV_MASK (0xFFU) |
#define | CAAM_CCBVID_AMNV_SHIFT (0U) |
#define | CAAM_CCBVID_AMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMNV_SHIFT)) & CAAM_CCBVID_AMNV_MASK) |
#define | CAAM_CCBVID_AMJV_MASK (0xFF00U) |
#define | CAAM_CCBVID_AMJV_SHIFT (8U) |
#define | CAAM_CCBVID_AMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMJV_SHIFT)) & CAAM_CCBVID_AMJV_MASK) |
#define | CAAM_CCBVID_CAAM_ERA_MASK (0xFF000000U) |
#define | CAAM_CCBVID_CAAM_ERA_SHIFT (24U) |
#define | CAAM_CCBVID_CAAM_ERA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_CAAM_ERA_SHIFT)) & CAAM_CCBVID_CAAM_ERA_MASK) |
CHAVID_MS - CHA Version ID Register, most-significant half | |
#define | CAAM_CHAVID_MS_CRCVID_MASK (0xFU) |
#define | CAAM_CHAVID_MS_CRCVID_SHIFT (0U) |
#define | CAAM_CHAVID_MS_CRCVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_CRCVID_SHIFT)) & CAAM_CHAVID_MS_CRCVID_MASK) |
#define | CAAM_CHAVID_MS_SNW9VID_MASK (0xF0U) |
#define | CAAM_CHAVID_MS_SNW9VID_SHIFT (4U) |
#define | CAAM_CHAVID_MS_SNW9VID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_SNW9VID_SHIFT)) & CAAM_CHAVID_MS_SNW9VID_MASK) |
#define | CAAM_CHAVID_MS_ZEVID_MASK (0xF00U) |
#define | CAAM_CHAVID_MS_ZEVID_SHIFT (8U) |
#define | CAAM_CHAVID_MS_ZEVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZEVID_SHIFT)) & CAAM_CHAVID_MS_ZEVID_MASK) |
#define | CAAM_CHAVID_MS_ZAVID_MASK (0xF000U) |
#define | CAAM_CHAVID_MS_ZAVID_SHIFT (12U) |
#define | CAAM_CHAVID_MS_ZAVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZAVID_SHIFT)) & CAAM_CHAVID_MS_ZAVID_MASK) |
#define | CAAM_CHAVID_MS_DECOVID_MASK (0xF000000U) |
#define | CAAM_CHAVID_MS_DECOVID_SHIFT (24U) |
#define | CAAM_CHAVID_MS_DECOVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_DECOVID_SHIFT)) & CAAM_CHAVID_MS_DECOVID_MASK) |
#define | CAAM_CHAVID_MS_JRVID_MASK (0xF0000000U) |
#define | CAAM_CHAVID_MS_JRVID_SHIFT (28U) |
#define | CAAM_CHAVID_MS_JRVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_JRVID_SHIFT)) & CAAM_CHAVID_MS_JRVID_MASK) |
CHAVID_LS - CHA Version ID Register, least-significant half | |
#define | CAAM_CHAVID_LS_AESVID_MASK (0xFU) |
#define | CAAM_CHAVID_LS_AESVID_SHIFT (0U) |
#define | CAAM_CHAVID_LS_AESVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_AESVID_SHIFT)) & CAAM_CHAVID_LS_AESVID_MASK) |
#define | CAAM_CHAVID_LS_DESVID_MASK (0xF0U) |
#define | CAAM_CHAVID_LS_DESVID_SHIFT (4U) |
#define | CAAM_CHAVID_LS_DESVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_DESVID_SHIFT)) & CAAM_CHAVID_LS_DESVID_MASK) |
#define | CAAM_CHAVID_LS_MDVID_MASK (0xF000U) |
#define | CAAM_CHAVID_LS_MDVID_SHIFT (12U) |
#define | CAAM_CHAVID_LS_MDVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_MDVID_SHIFT)) & CAAM_CHAVID_LS_MDVID_MASK) |
#define | CAAM_CHAVID_LS_RNGVID_MASK (0xF0000U) |
#define | CAAM_CHAVID_LS_RNGVID_SHIFT (16U) |
#define | CAAM_CHAVID_LS_RNGVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_RNGVID_SHIFT)) & CAAM_CHAVID_LS_RNGVID_MASK) |
#define | CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) |
#define | CAAM_CHAVID_LS_SNW8VID_SHIFT (20U) |
#define | CAAM_CHAVID_LS_SNW8VID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK) |
#define | CAAM_CHAVID_LS_KASVID_MASK (0xF000000U) |
#define | CAAM_CHAVID_LS_KASVID_SHIFT (24U) |
#define | CAAM_CHAVID_LS_KASVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_KASVID_SHIFT)) & CAAM_CHAVID_LS_KASVID_MASK) |
#define | CAAM_CHAVID_LS_PKVID_MASK (0xF0000000U) |
#define | CAAM_CHAVID_LS_PKVID_SHIFT (28U) |
#define | CAAM_CHAVID_LS_PKVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_PKVID_SHIFT)) & CAAM_CHAVID_LS_PKVID_MASK) |
CHANUM_MS - CHA Number Register, most-significant half | |
#define | CAAM_CHANUM_MS_CRCNUM_MASK (0xFU) |
#define | CAAM_CHANUM_MS_CRCNUM_SHIFT (0U) |
#define | CAAM_CHANUM_MS_CRCNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_CRCNUM_SHIFT)) & CAAM_CHANUM_MS_CRCNUM_MASK) |
#define | CAAM_CHANUM_MS_SNW9NUM_MASK (0xF0U) |
#define | CAAM_CHANUM_MS_SNW9NUM_SHIFT (4U) |
#define | CAAM_CHANUM_MS_SNW9NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_SNW9NUM_SHIFT)) & CAAM_CHANUM_MS_SNW9NUM_MASK) |
#define | CAAM_CHANUM_MS_ZENUM_MASK (0xF00U) |
#define | CAAM_CHANUM_MS_ZENUM_SHIFT (8U) |
#define | CAAM_CHANUM_MS_ZENUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZENUM_SHIFT)) & CAAM_CHANUM_MS_ZENUM_MASK) |
#define | CAAM_CHANUM_MS_ZANUM_MASK (0xF000U) |
#define | CAAM_CHANUM_MS_ZANUM_SHIFT (12U) |
#define | CAAM_CHANUM_MS_ZANUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZANUM_SHIFT)) & CAAM_CHANUM_MS_ZANUM_MASK) |
#define | CAAM_CHANUM_MS_DECONUM_MASK (0xF000000U) |
#define | CAAM_CHANUM_MS_DECONUM_SHIFT (24U) |
#define | CAAM_CHANUM_MS_DECONUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_DECONUM_SHIFT)) & CAAM_CHANUM_MS_DECONUM_MASK) |
#define | CAAM_CHANUM_MS_JRNUM_MASK (0xF0000000U) |
#define | CAAM_CHANUM_MS_JRNUM_SHIFT (28U) |
#define | CAAM_CHANUM_MS_JRNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_JRNUM_SHIFT)) & CAAM_CHANUM_MS_JRNUM_MASK) |
CHANUM_LS - CHA Number Register, least-significant half | |
#define | CAAM_CHANUM_LS_AESNUM_MASK (0xFU) |
#define | CAAM_CHANUM_LS_AESNUM_SHIFT (0U) |
#define | CAAM_CHANUM_LS_AESNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_AESNUM_SHIFT)) & CAAM_CHANUM_LS_AESNUM_MASK) |
#define | CAAM_CHANUM_LS_DESNUM_MASK (0xF0U) |
#define | CAAM_CHANUM_LS_DESNUM_SHIFT (4U) |
#define | CAAM_CHANUM_LS_DESNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_DESNUM_SHIFT)) & CAAM_CHANUM_LS_DESNUM_MASK) |
#define | CAAM_CHANUM_LS_ARC4NUM_MASK (0xF00U) |
#define | CAAM_CHANUM_LS_ARC4NUM_SHIFT (8U) |
#define | CAAM_CHANUM_LS_ARC4NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_ARC4NUM_SHIFT)) & CAAM_CHANUM_LS_ARC4NUM_MASK) |
#define | CAAM_CHANUM_LS_MDNUM_MASK (0xF000U) |
#define | CAAM_CHANUM_LS_MDNUM_SHIFT (12U) |
#define | CAAM_CHANUM_LS_MDNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_MDNUM_SHIFT)) & CAAM_CHANUM_LS_MDNUM_MASK) |
#define | CAAM_CHANUM_LS_RNGNUM_MASK (0xF0000U) |
#define | CAAM_CHANUM_LS_RNGNUM_SHIFT (16U) |
#define | CAAM_CHANUM_LS_RNGNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_RNGNUM_SHIFT)) & CAAM_CHANUM_LS_RNGNUM_MASK) |
#define | CAAM_CHANUM_LS_SNW8NUM_MASK (0xF00000U) |
#define | CAAM_CHANUM_LS_SNW8NUM_SHIFT (20U) |
#define | CAAM_CHANUM_LS_SNW8NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_SNW8NUM_SHIFT)) & CAAM_CHANUM_LS_SNW8NUM_MASK) |
#define | CAAM_CHANUM_LS_KASNUM_MASK (0xF000000U) |
#define | CAAM_CHANUM_LS_KASNUM_SHIFT (24U) |
#define | CAAM_CHANUM_LS_KASNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_KASNUM_SHIFT)) & CAAM_CHANUM_LS_KASNUM_MASK) |
#define | CAAM_CHANUM_LS_PKNUM_MASK (0xF0000000U) |
#define | CAAM_CHANUM_LS_PKNUM_SHIFT (28U) |
#define | CAAM_CHANUM_LS_PKNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_PKNUM_SHIFT)) & CAAM_CHANUM_LS_PKNUM_MASK) |
IRBAR_JR - Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3 | |
#define | CAAM_IRBAR_JR_IRBA_MASK (0xFFFFFFFFFU) |
#define | CAAM_IRBAR_JR_IRBA_SHIFT (0U) |
#define | CAAM_IRBAR_JR_IRBA(x) (((uint64_t)(((uint64_t)(x)) << CAAM_IRBAR_JR_IRBA_SHIFT)) & CAAM_IRBAR_JR_IRBA_MASK) |
IRSR_JR - Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3 | |
#define | CAAM_IRSR_JR_IRS_MASK (0x3FFU) |
#define | CAAM_IRSR_JR_IRS_SHIFT (0U) |
#define | CAAM_IRSR_JR_IRS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRSR_JR_IRS_SHIFT)) & CAAM_IRSR_JR_IRS_MASK) |
IRSAR_JR - Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3 | |
#define | CAAM_IRSAR_JR_IRSA_MASK (0x3FFU) |
#define | CAAM_IRSAR_JR_IRSA_SHIFT (0U) |
#define | CAAM_IRSAR_JR_IRSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRSAR_JR_IRSA_SHIFT)) & CAAM_IRSAR_JR_IRSA_MASK) |
IRJAR_JR - Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3 | |
#define | CAAM_IRJAR_JR_IRJA_MASK (0x3FFU) |
#define | CAAM_IRJAR_JR_IRJA_SHIFT (0U) |
#define | CAAM_IRJAR_JR_IRJA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRJAR_JR_IRJA_SHIFT)) & CAAM_IRJAR_JR_IRJA_MASK) |
ORBAR_JR - Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3 | |
#define | CAAM_ORBAR_JR_ORBA_MASK (0xFFFFFFFFFU) |
#define | CAAM_ORBAR_JR_ORBA_SHIFT (0U) |
#define | CAAM_ORBAR_JR_ORBA(x) (((uint64_t)(((uint64_t)(x)) << CAAM_ORBAR_JR_ORBA_SHIFT)) & CAAM_ORBAR_JR_ORBA_MASK) |
ORSR_JR - Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3 | |
#define | CAAM_ORSR_JR_ORS_MASK (0x3FFU) |
#define | CAAM_ORSR_JR_ORS_SHIFT (0U) |
#define | CAAM_ORSR_JR_ORS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORSR_JR_ORS_SHIFT)) & CAAM_ORSR_JR_ORS_MASK) |
ORJRR_JR - Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3 | |
#define | CAAM_ORJRR_JR_ORJR_MASK (0x3FFU) |
#define | CAAM_ORJRR_JR_ORJR_SHIFT (0U) |
#define | CAAM_ORJRR_JR_ORJR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORJRR_JR_ORJR_SHIFT)) & CAAM_ORJRR_JR_ORJR_MASK) |
ORSFR_JR - Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3 | |
#define | CAAM_ORSFR_JR_ORSF_MASK (0x3FFU) |
#define | CAAM_ORSFR_JR_ORSF_SHIFT (0U) |
#define | CAAM_ORSFR_JR_ORSF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORSFR_JR_ORSF_SHIFT)) & CAAM_ORSFR_JR_ORSF_MASK) |
JRSTAR_JR - Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3 | |
#define | CAAM_JRSTAR_JR_SSED_MASK (0xFFFFFFFU) |
#define | CAAM_JRSTAR_JR_SSED_SHIFT (0U) |
#define | CAAM_JRSTAR_JR_SSED(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSED_SHIFT)) & CAAM_JRSTAR_JR_SSED_MASK) |
#define | CAAM_JRSTAR_JR_SSRC_MASK (0xF0000000U) |
#define | CAAM_JRSTAR_JR_SSRC_SHIFT (28U) |
#define | CAAM_JRSTAR_JR_SSRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSRC_SHIFT)) & CAAM_JRSTAR_JR_SSRC_MASK) |
JRINTR_JR - Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3 | |
#define | CAAM_JRINTR_JR_JRI_MASK (0x1U) |
#define | CAAM_JRINTR_JR_JRI_SHIFT (0U) |
#define | CAAM_JRINTR_JR_JRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRI_SHIFT)) & CAAM_JRINTR_JR_JRI_MASK) |
#define | CAAM_JRINTR_JR_JRE_MASK (0x2U) |
#define | CAAM_JRINTR_JR_JRE_SHIFT (1U) |
#define | CAAM_JRINTR_JR_JRE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRE_SHIFT)) & CAAM_JRINTR_JR_JRE_MASK) |
#define | CAAM_JRINTR_JR_HALT_MASK (0xCU) |
#define | CAAM_JRINTR_JR_HALT_SHIFT (2U) |
#define | CAAM_JRINTR_JR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_HALT_SHIFT)) & CAAM_JRINTR_JR_HALT_MASK) |
#define | CAAM_JRINTR_JR_ENTER_FAIL_MASK (0x10U) |
#define | CAAM_JRINTR_JR_ENTER_FAIL_SHIFT (4U) |
#define | CAAM_JRINTR_JR_ENTER_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ENTER_FAIL_SHIFT)) & CAAM_JRINTR_JR_ENTER_FAIL_MASK) |
#define | CAAM_JRINTR_JR_EXIT_FAIL_MASK (0x20U) |
#define | CAAM_JRINTR_JR_EXIT_FAIL_SHIFT (5U) |
#define | CAAM_JRINTR_JR_EXIT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_EXIT_FAIL_SHIFT)) & CAAM_JRINTR_JR_EXIT_FAIL_MASK) |
#define | CAAM_JRINTR_JR_ERR_TYPE_MASK (0x1F00U) |
#define | CAAM_JRINTR_JR_ERR_TYPE_SHIFT (8U) |
#define | CAAM_JRINTR_JR_ERR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_TYPE_SHIFT)) & CAAM_JRINTR_JR_ERR_TYPE_MASK) |
#define | CAAM_JRINTR_JR_ERR_ORWI_MASK (0x3FFF0000U) |
#define | CAAM_JRINTR_JR_ERR_ORWI_SHIFT (16U) |
#define | CAAM_JRINTR_JR_ERR_ORWI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_ORWI_SHIFT)) & CAAM_JRINTR_JR_ERR_ORWI_MASK) |
JRCFGR_JR_MS - Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half | |
#define | CAAM_JRCFGR_JR_MS_MBSI_MASK (0x1U) |
#define | CAAM_JRCFGR_JR_MS_MBSI_SHIFT (0U) |
#define | CAAM_JRCFGR_JR_MS_MBSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSI_MASK) |
#define | CAAM_JRCFGR_JR_MS_MHWSI_MASK (0x2U) |
#define | CAAM_JRCFGR_JR_MS_MHWSI_SHIFT (1U) |
#define | CAAM_JRCFGR_JR_MS_MHWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSI_MASK) |
#define | CAAM_JRCFGR_JR_MS_MWSI_MASK (0x4U) |
#define | CAAM_JRCFGR_JR_MS_MWSI_SHIFT (2U) |
#define | CAAM_JRCFGR_JR_MS_MWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSI_MASK) |
#define | CAAM_JRCFGR_JR_MS_CBSI_MASK (0x10U) |
#define | CAAM_JRCFGR_JR_MS_CBSI_SHIFT (4U) |
#define | CAAM_JRCFGR_JR_MS_CBSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSI_MASK) |
#define | CAAM_JRCFGR_JR_MS_CHWSI_MASK (0x20U) |
#define | CAAM_JRCFGR_JR_MS_CHWSI_SHIFT (5U) |
#define | CAAM_JRCFGR_JR_MS_CHWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSI_MASK) |
#define | CAAM_JRCFGR_JR_MS_CWSI_MASK (0x40U) |
#define | CAAM_JRCFGR_JR_MS_CWSI_SHIFT (6U) |
#define | CAAM_JRCFGR_JR_MS_CWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSI_MASK) |
#define | CAAM_JRCFGR_JR_MS_MBSO_MASK (0x100U) |
#define | CAAM_JRCFGR_JR_MS_MBSO_SHIFT (8U) |
#define | CAAM_JRCFGR_JR_MS_MBSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSO_MASK) |
#define | CAAM_JRCFGR_JR_MS_MHWSO_MASK (0x200U) |
#define | CAAM_JRCFGR_JR_MS_MHWSO_SHIFT (9U) |
#define | CAAM_JRCFGR_JR_MS_MHWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSO_MASK) |
#define | CAAM_JRCFGR_JR_MS_MWSO_MASK (0x400U) |
#define | CAAM_JRCFGR_JR_MS_MWSO_SHIFT (10U) |
#define | CAAM_JRCFGR_JR_MS_MWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSO_MASK) |
#define | CAAM_JRCFGR_JR_MS_CBSO_MASK (0x1000U) |
#define | CAAM_JRCFGR_JR_MS_CBSO_SHIFT (12U) |
#define | CAAM_JRCFGR_JR_MS_CBSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSO_MASK) |
#define | CAAM_JRCFGR_JR_MS_CHWSO_MASK (0x2000U) |
#define | CAAM_JRCFGR_JR_MS_CHWSO_SHIFT (13U) |
#define | CAAM_JRCFGR_JR_MS_CHWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSO_MASK) |
#define | CAAM_JRCFGR_JR_MS_CWSO_MASK (0x4000U) |
#define | CAAM_JRCFGR_JR_MS_CWSO_SHIFT (14U) |
#define | CAAM_JRCFGR_JR_MS_CWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSO_MASK) |
#define | CAAM_JRCFGR_JR_MS_DMBS_MASK (0x10000U) |
#define | CAAM_JRCFGR_JR_MS_DMBS_SHIFT (16U) |
#define | CAAM_JRCFGR_JR_MS_DMBS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DMBS_SHIFT)) & CAAM_JRCFGR_JR_MS_DMBS_MASK) |
#define | CAAM_JRCFGR_JR_MS_PEO_MASK (0x20000U) |
#define | CAAM_JRCFGR_JR_MS_PEO_SHIFT (17U) |
#define | CAAM_JRCFGR_JR_MS_PEO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_PEO_SHIFT)) & CAAM_JRCFGR_JR_MS_PEO_MASK) |
#define | CAAM_JRCFGR_JR_MS_DWSO_MASK (0x40000U) |
#define | CAAM_JRCFGR_JR_MS_DWSO_SHIFT (18U) |
#define | CAAM_JRCFGR_JR_MS_DWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_DWSO_MASK) |
#define | CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK (0x20000000U) |
#define | CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT (29U) |
#define | CAAM_JRCFGR_JR_MS_FAIL_MODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT)) & CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK) |
#define | CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK (0x40000000U) |
#define | CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT (30U) |
#define | CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT)) & CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK) |
JRCFGR_JR_LS - Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half | |
#define | CAAM_JRCFGR_JR_LS_IMSK_MASK (0x1U) |
#define | CAAM_JRCFGR_JR_LS_IMSK_SHIFT (0U) |
#define | CAAM_JRCFGR_JR_LS_IMSK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_IMSK_SHIFT)) & CAAM_JRCFGR_JR_LS_IMSK_MASK) |
#define | CAAM_JRCFGR_JR_LS_ICEN_MASK (0x2U) |
#define | CAAM_JRCFGR_JR_LS_ICEN_SHIFT (1U) |
#define | CAAM_JRCFGR_JR_LS_ICEN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICEN_SHIFT)) & CAAM_JRCFGR_JR_LS_ICEN_MASK) |
#define | CAAM_JRCFGR_JR_LS_ICDCT_MASK (0xFF00U) |
#define | CAAM_JRCFGR_JR_LS_ICDCT_SHIFT (8U) |
#define | CAAM_JRCFGR_JR_LS_ICDCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICDCT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICDCT_MASK) |
#define | CAAM_JRCFGR_JR_LS_ICTT_MASK (0xFFFF0000U) |
#define | CAAM_JRCFGR_JR_LS_ICTT_SHIFT (16U) |
#define | CAAM_JRCFGR_JR_LS_ICTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICTT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICTT_MASK) |
IRRIR_JR - Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3 | |
#define | CAAM_IRRIR_JR_IRRI_MASK (0x1FFFU) |
#define | CAAM_IRRIR_JR_IRRI_SHIFT (0U) |
#define | CAAM_IRRIR_JR_IRRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRRIR_JR_IRRI_SHIFT)) & CAAM_IRRIR_JR_IRRI_MASK) |
ORWIR_JR - Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3 | |
#define | CAAM_ORWIR_JR_ORWI_MASK (0x3FFFU) |
#define | CAAM_ORWIR_JR_ORWI_SHIFT (0U) |
#define | CAAM_ORWIR_JR_ORWI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORWIR_JR_ORWI_SHIFT)) & CAAM_ORWIR_JR_ORWI_MASK) |
JRCR_JR - Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3 | |
#define | CAAM_JRCR_JR_RESET_MASK (0x1U) |
#define | CAAM_JRCR_JR_RESET_SHIFT (0U) |
#define | CAAM_JRCR_JR_RESET(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_RESET_SHIFT)) & CAAM_JRCR_JR_RESET_MASK) |
#define | CAAM_JRCR_JR_PARK_MASK (0x2U) |
#define | CAAM_JRCR_JR_PARK_SHIFT (1U) |
#define | CAAM_JRCR_JR_PARK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_PARK_SHIFT)) & CAAM_JRCR_JR_PARK_MASK) |
JRAAV - Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register | |
#define | CAAM_JRAAV_V0_MASK (0x1U) |
#define | CAAM_JRAAV_V0_SHIFT (0U) |
#define | CAAM_JRAAV_V0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V0_SHIFT)) & CAAM_JRAAV_V0_MASK) |
#define | CAAM_JRAAV_V1_MASK (0x2U) |
#define | CAAM_JRAAV_V1_SHIFT (1U) |
#define | CAAM_JRAAV_V1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V1_SHIFT)) & CAAM_JRAAV_V1_MASK) |
#define | CAAM_JRAAV_V2_MASK (0x4U) |
#define | CAAM_JRAAV_V2_SHIFT (2U) |
#define | CAAM_JRAAV_V2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V2_SHIFT)) & CAAM_JRAAV_V2_MASK) |
#define | CAAM_JRAAV_V3_MASK (0x8U) |
#define | CAAM_JRAAV_V3_SHIFT (3U) |
#define | CAAM_JRAAV_V3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V3_SHIFT)) & CAAM_JRAAV_V3_MASK) |
#define | CAAM_JRAAV_BC_MASK (0x80000000U) |
#define | CAAM_JRAAV_BC_SHIFT (31U) |
#define | CAAM_JRAAV_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_BC_SHIFT)) & CAAM_JRAAV_BC_MASK) |
JRAAA - Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register | |
#define | CAAM_JRAAA_JD_ADDR_MASK (0xFFFFFFFFFU) |
#define | CAAM_JRAAA_JD_ADDR_SHIFT (0U) |
#define | CAAM_JRAAA_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_JRAAA_JD_ADDR_SHIFT)) & CAAM_JRAAA_JD_ADDR_MASK) |
PX_SDID_JR - Partition 0 SDID register..Partition 15 SDID register | |
#define | CAAM_PX_SDID_JR_SDID_MASK (0xFFFFU) |
#define | CAAM_PX_SDID_JR_SDID_SHIFT (0U) |
#define | CAAM_PX_SDID_JR_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_JR_SDID_SHIFT)) & CAAM_PX_SDID_JR_SDID_MASK) |
PX_SMAPR_JR - Secure Memory Access Permissions register | |
#define | CAAM_PX_SMAPR_JR_G1_READ_MASK (0x1U) |
#define | CAAM_PX_SMAPR_JR_G1_READ_SHIFT (0U) |
#define | CAAM_PX_SMAPR_JR_G1_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G1_READ_MASK) |
#define | CAAM_PX_SMAPR_JR_G1_WRITE_MASK (0x2U) |
#define | CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT (1U) |
#define | CAAM_PX_SMAPR_JR_G1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G1_WRITE_MASK) |
#define | CAAM_PX_SMAPR_JR_G1_TDO_MASK (0x4U) |
#define | CAAM_PX_SMAPR_JR_G1_TDO_SHIFT (2U) |
#define | CAAM_PX_SMAPR_JR_G1_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G1_TDO_MASK) |
#define | CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK (0x8U) |
#define | CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT (3U) |
#define | CAAM_PX_SMAPR_JR_G1_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK) |
#define | CAAM_PX_SMAPR_JR_G2_READ_MASK (0x10U) |
#define | CAAM_PX_SMAPR_JR_G2_READ_SHIFT (4U) |
#define | CAAM_PX_SMAPR_JR_G2_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G2_READ_MASK) |
#define | CAAM_PX_SMAPR_JR_G2_WRITE_MASK (0x20U) |
#define | CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT (5U) |
#define | CAAM_PX_SMAPR_JR_G2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G2_WRITE_MASK) |
#define | CAAM_PX_SMAPR_JR_G2_TDO_MASK (0x40U) |
#define | CAAM_PX_SMAPR_JR_G2_TDO_SHIFT (6U) |
#define | CAAM_PX_SMAPR_JR_G2_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G2_TDO_MASK) |
#define | CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK (0x80U) |
#define | CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT (7U) |
#define | CAAM_PX_SMAPR_JR_G2_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK) |
#define | CAAM_PX_SMAPR_JR_SMAG_LCK_MASK (0x1000U) |
#define | CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT (12U) |
#define | CAAM_PX_SMAPR_JR_SMAG_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAG_LCK_MASK) |
#define | CAAM_PX_SMAPR_JR_SMAP_LCK_MASK (0x2000U) |
#define | CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT (13U) |
#define | CAAM_PX_SMAPR_JR_SMAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAP_LCK_MASK) |
#define | CAAM_PX_SMAPR_JR_PSP_MASK (0x4000U) |
#define | CAAM_PX_SMAPR_JR_PSP_SHIFT (14U) |
#define | CAAM_PX_SMAPR_JR_PSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PSP_SHIFT)) & CAAM_PX_SMAPR_JR_PSP_MASK) |
#define | CAAM_PX_SMAPR_JR_CSP_MASK (0x8000U) |
#define | CAAM_PX_SMAPR_JR_CSP_SHIFT (15U) |
#define | CAAM_PX_SMAPR_JR_CSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_CSP_SHIFT)) & CAAM_PX_SMAPR_JR_CSP_MASK) |
#define | CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK (0xFFFF0000U) |
#define | CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT (16U) |
#define | CAAM_PX_SMAPR_JR_PARTITION_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK) |
PX_SMAG2_JR - Secure Memory Access Group Registers | |
#define | CAAM_PX_SMAG2_JR_Gx_ID00_MASK (0x1U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT (0U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID00_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID01_MASK (0x2U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT (1U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID01_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID02_MASK (0x4U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT (2U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID02_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID03_MASK (0x8U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT (3U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID03_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID04_MASK (0x10U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT (4U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID04_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID05_MASK (0x20U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT (5U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID05_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID06_MASK (0x40U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT (6U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID06_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID07_MASK (0x80U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT (7U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID07_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID08_MASK (0x100U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT (8U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID08_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID09_MASK (0x200U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT (9U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID09_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID10_MASK (0x400U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT (10U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID10_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID11_MASK (0x800U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT (11U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID11_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID12_MASK (0x1000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT (12U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID12_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID13_MASK (0x2000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT (13U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID13_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID14_MASK (0x4000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT (14U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID14_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID15_MASK (0x8000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT (15U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID15_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID16_MASK (0x10000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT (16U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID16_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID17_MASK (0x20000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT (17U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID17_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID18_MASK (0x40000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT (18U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID18_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID19_MASK (0x80000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT (19U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID19_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID20_MASK (0x100000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT (20U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID20_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID21_MASK (0x200000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT (21U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID21_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID22_MASK (0x400000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT (22U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID22_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID23_MASK (0x800000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT (23U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID23_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID24_MASK (0x1000000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT (24U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID24_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID25_MASK (0x2000000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT (25U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID25_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID26_MASK (0x4000000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT (26U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID26_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID27_MASK (0x8000000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT (27U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID27_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID28_MASK (0x10000000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT (28U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID28_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID29_MASK (0x20000000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT (29U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID29_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID30_MASK (0x40000000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT (30U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID30_MASK) |
#define | CAAM_PX_SMAG2_JR_Gx_ID31_MASK (0x80000000U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT (31U) |
#define | CAAM_PX_SMAG2_JR_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID31_MASK) |
PX_SMAG1_JR - Secure Memory Access Group Registers | |
#define | CAAM_PX_SMAG1_JR_Gx_ID00_MASK (0x1U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT (0U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID00_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID01_MASK (0x2U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT (1U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID01_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID02_MASK (0x4U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT (2U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID02_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID03_MASK (0x8U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT (3U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID03_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID04_MASK (0x10U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT (4U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID04_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID05_MASK (0x20U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT (5U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID05_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID06_MASK (0x40U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT (6U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID06_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID07_MASK (0x80U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT (7U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID07_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID08_MASK (0x100U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT (8U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID08_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID09_MASK (0x200U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT (9U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID09_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID10_MASK (0x400U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT (10U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID10_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID11_MASK (0x800U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT (11U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID11_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID12_MASK (0x1000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT (12U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID12_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID13_MASK (0x2000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT (13U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID13_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID14_MASK (0x4000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT (14U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID14_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID15_MASK (0x8000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT (15U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID15_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID16_MASK (0x10000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT (16U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID16_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID17_MASK (0x20000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT (17U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID17_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID18_MASK (0x40000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT (18U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID18_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID19_MASK (0x80000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT (19U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID19_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID20_MASK (0x100000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT (20U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID20_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID21_MASK (0x200000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT (21U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID21_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID22_MASK (0x400000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT (22U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID22_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID23_MASK (0x800000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT (23U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID23_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID24_MASK (0x1000000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT (24U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID24_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID25_MASK (0x2000000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT (25U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID25_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID26_MASK (0x4000000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT (26U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID26_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID27_MASK (0x8000000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT (27U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID27_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID28_MASK (0x10000000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT (28U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID28_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID29_MASK (0x20000000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT (29U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID29_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID30_MASK (0x40000000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT (30U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID30_MASK) |
#define | CAAM_PX_SMAG1_JR_Gx_ID31_MASK (0x80000000U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT (31U) |
#define | CAAM_PX_SMAG1_JR_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID31_MASK) |
SMCR_JR - Secure Memory Command Register | |
#define | CAAM_SMCR_JR_CMD_MASK (0xFU) |
#define | CAAM_SMCR_JR_CMD_SHIFT (0U) |
#define | CAAM_SMCR_JR_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_CMD_SHIFT)) & CAAM_SMCR_JR_CMD_MASK) |
#define | CAAM_SMCR_JR_PRTN_MASK (0xF00U) |
#define | CAAM_SMCR_JR_PRTN_SHIFT (8U) |
#define | CAAM_SMCR_JR_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PRTN_SHIFT)) & CAAM_SMCR_JR_PRTN_MASK) |
#define | CAAM_SMCR_JR_PAGE_MASK (0xFFFF0000U) |
#define | CAAM_SMCR_JR_PAGE_SHIFT (16U) |
#define | CAAM_SMCR_JR_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PAGE_SHIFT)) & CAAM_SMCR_JR_PAGE_MASK) |
SMCSR_JR - Secure Memory Command Status Register | |
#define | CAAM_SMCSR_JR_PRTN_MASK (0xFU) |
#define | CAAM_SMCSR_JR_PRTN_SHIFT (0U) |
#define | CAAM_SMCSR_JR_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PRTN_SHIFT)) & CAAM_SMCSR_JR_PRTN_MASK) |
#define | CAAM_SMCSR_JR_PO_MASK (0xC0U) |
#define | CAAM_SMCSR_JR_PO_SHIFT (6U) |
#define | CAAM_SMCSR_JR_PO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PO_SHIFT)) & CAAM_SMCSR_JR_PO_MASK) |
#define | CAAM_SMCSR_JR_AERR_MASK (0x3000U) |
#define | CAAM_SMCSR_JR_AERR_SHIFT (12U) |
#define | CAAM_SMCSR_JR_AERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_AERR_SHIFT)) & CAAM_SMCSR_JR_AERR_MASK) |
#define | CAAM_SMCSR_JR_CERR_MASK (0xC000U) |
#define | CAAM_SMCSR_JR_CERR_SHIFT (14U) |
#define | CAAM_SMCSR_JR_CERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_CERR_SHIFT)) & CAAM_SMCSR_JR_CERR_MASK) |
#define | CAAM_SMCSR_JR_PAGE_MASK (0xFFF0000U) |
#define | CAAM_SMCSR_JR_PAGE_SHIFT (16U) |
#define | CAAM_SMCSR_JR_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PAGE_SHIFT)) & CAAM_SMCSR_JR_PAGE_MASK) |
REIR0JR - Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3 | |
#define | CAAM_REIR0JR_TYPE_MASK (0x3000000U) |
#define | CAAM_REIR0JR_TYPE_SHIFT (24U) |
#define | CAAM_REIR0JR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_TYPE_SHIFT)) & CAAM_REIR0JR_TYPE_MASK) |
#define | CAAM_REIR0JR_MISS_MASK (0x80000000U) |
#define | CAAM_REIR0JR_MISS_SHIFT (31U) |
#define | CAAM_REIR0JR_MISS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_MISS_SHIFT)) & CAAM_REIR0JR_MISS_MASK) |
REIR2JR - Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3 | |
#define | CAAM_REIR2JR_ADDR_MASK (0xFFFFFFFFFU) |
#define | CAAM_REIR2JR_ADDR_SHIFT (0U) |
#define | CAAM_REIR2JR_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2JR_ADDR_SHIFT)) & CAAM_REIR2JR_ADDR_MASK) |
REIR4JR - Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3 | |
#define | CAAM_REIR4JR_ICID_MASK (0x7FFU) |
#define | CAAM_REIR4JR_ICID_SHIFT (0U) |
#define | CAAM_REIR4JR_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ICID_SHIFT)) & CAAM_REIR4JR_ICID_MASK) |
#define | CAAM_REIR4JR_DID_MASK (0x7800U) |
#define | CAAM_REIR4JR_DID_SHIFT (11U) |
#define | CAAM_REIR4JR_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_DID_SHIFT)) & CAAM_REIR4JR_DID_MASK) |
#define | CAAM_REIR4JR_AXCACHE_MASK (0xF0000U) |
#define | CAAM_REIR4JR_AXCACHE_SHIFT (16U) |
#define | CAAM_REIR4JR_AXCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXCACHE_SHIFT)) & CAAM_REIR4JR_AXCACHE_MASK) |
#define | CAAM_REIR4JR_AXPROT_MASK (0x700000U) |
#define | CAAM_REIR4JR_AXPROT_SHIFT (20U) |
#define | CAAM_REIR4JR_AXPROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXPROT_SHIFT)) & CAAM_REIR4JR_AXPROT_MASK) |
#define | CAAM_REIR4JR_RWB_MASK (0x800000U) |
#define | CAAM_REIR4JR_RWB_SHIFT (23U) |
#define | CAAM_REIR4JR_RWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_RWB_SHIFT)) & CAAM_REIR4JR_RWB_MASK) |
#define | CAAM_REIR4JR_ERR_MASK (0x30000000U) |
#define | CAAM_REIR4JR_ERR_SHIFT (28U) |
#define | CAAM_REIR4JR_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ERR_SHIFT)) & CAAM_REIR4JR_ERR_MASK) |
#define | CAAM_REIR4JR_MIX_MASK (0xC0000000U) |
#define | CAAM_REIR4JR_MIX_SHIFT (30U) |
#define | CAAM_REIR4JR_MIX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_MIX_SHIFT)) & CAAM_REIR4JR_MIX_MASK) |
REIR5JR - Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3 | |
#define | CAAM_REIR5JR_BID_MASK (0xF0000U) |
#define | CAAM_REIR5JR_BID_SHIFT (16U) |
#define | CAAM_REIR5JR_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BID_SHIFT)) & CAAM_REIR5JR_BID_MASK) |
#define | CAAM_REIR5JR_BNDG_MASK (0x2000000U) |
#define | CAAM_REIR5JR_BNDG_SHIFT (25U) |
#define | CAAM_REIR5JR_BNDG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BNDG_SHIFT)) & CAAM_REIR5JR_BNDG_MASK) |
#define | CAAM_REIR5JR_TDSC_MASK (0x4000000U) |
#define | CAAM_REIR5JR_TDSC_SHIFT (26U) |
#define | CAAM_REIR5JR_TDSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_TDSC_SHIFT)) & CAAM_REIR5JR_TDSC_MASK) |
#define | CAAM_REIR5JR_KMOD_MASK (0x8000000U) |
#define | CAAM_REIR5JR_KMOD_SHIFT (27U) |
#define | CAAM_REIR5JR_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KMOD_SHIFT)) & CAAM_REIR5JR_KMOD_MASK) |
#define | CAAM_REIR5JR_KEY_MASK (0x10000000U) |
#define | CAAM_REIR5JR_KEY_SHIFT (28U) |
#define | CAAM_REIR5JR_KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KEY_SHIFT)) & CAAM_REIR5JR_KEY_MASK) |
#define | CAAM_REIR5JR_SMA_MASK (0x20000000U) |
#define | CAAM_REIR5JR_SMA_SHIFT (29U) |
#define | CAAM_REIR5JR_SMA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_SMA_SHIFT)) & CAAM_REIR5JR_SMA_MASK) |
RSTA - RTIC Status Register | |
#define | CAAM_RSTA_BSY_MASK (0x1U) |
#define | CAAM_RSTA_BSY_SHIFT (0U) |
#define | CAAM_RSTA_BSY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_BSY_SHIFT)) & CAAM_RSTA_BSY_MASK) |
#define | CAAM_RSTA_HD_MASK (0x2U) |
#define | CAAM_RSTA_HD_SHIFT (1U) |
#define | CAAM_RSTA_HD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HD_SHIFT)) & CAAM_RSTA_HD_MASK) |
#define | CAAM_RSTA_SV_MASK (0x4U) |
#define | CAAM_RSTA_SV_SHIFT (2U) |
#define | CAAM_RSTA_SV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_SV_SHIFT)) & CAAM_RSTA_SV_MASK) |
#define | CAAM_RSTA_HE_MASK (0x8U) |
#define | CAAM_RSTA_HE_SHIFT (3U) |
#define | CAAM_RSTA_HE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HE_SHIFT)) & CAAM_RSTA_HE_MASK) |
#define | CAAM_RSTA_MIS_MASK (0xF0U) |
#define | CAAM_RSTA_MIS_SHIFT (4U) |
#define | CAAM_RSTA_MIS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_MIS_SHIFT)) & CAAM_RSTA_MIS_MASK) |
#define | CAAM_RSTA_AE_MASK (0xF00U) |
#define | CAAM_RSTA_AE_SHIFT (8U) |
#define | CAAM_RSTA_AE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_AE_SHIFT)) & CAAM_RSTA_AE_MASK) |
#define | CAAM_RSTA_WE_MASK (0x10000U) |
#define | CAAM_RSTA_WE_SHIFT (16U) |
#define | CAAM_RSTA_WE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_WE_SHIFT)) & CAAM_RSTA_WE_MASK) |
#define | CAAM_RSTA_ABH_MASK (0x20000U) |
#define | CAAM_RSTA_ABH_SHIFT (17U) |
#define | CAAM_RSTA_ABH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_ABH_SHIFT)) & CAAM_RSTA_ABH_MASK) |
#define | CAAM_RSTA_HOD_MASK (0x40000U) |
#define | CAAM_RSTA_HOD_SHIFT (18U) |
#define | CAAM_RSTA_HOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HOD_SHIFT)) & CAAM_RSTA_HOD_MASK) |
#define | CAAM_RSTA_RTD_MASK (0x80000U) |
#define | CAAM_RSTA_RTD_SHIFT (19U) |
#define | CAAM_RSTA_RTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_RTD_SHIFT)) & CAAM_RSTA_RTD_MASK) |
#define | CAAM_RSTA_CS_MASK (0x6000000U) |
#define | CAAM_RSTA_CS_SHIFT (25U) |
#define | CAAM_RSTA_CS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_CS_SHIFT)) & CAAM_RSTA_CS_MASK) |
RCMD - RTIC Command Register | |
#define | CAAM_RCMD_CINT_MASK (0x1U) |
#define | CAAM_RCMD_CINT_SHIFT (0U) |
#define | CAAM_RCMD_CINT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_CINT_SHIFT)) & CAAM_RCMD_CINT_MASK) |
#define | CAAM_RCMD_HO_MASK (0x2U) |
#define | CAAM_RCMD_HO_SHIFT (1U) |
#define | CAAM_RCMD_HO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_HO_SHIFT)) & CAAM_RCMD_HO_MASK) |
#define | CAAM_RCMD_RTC_MASK (0x4U) |
#define | CAAM_RCMD_RTC_SHIFT (2U) |
#define | CAAM_RCMD_RTC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTC_SHIFT)) & CAAM_RCMD_RTC_MASK) |
#define | CAAM_RCMD_RTD_MASK (0x8U) |
#define | CAAM_RCMD_RTD_SHIFT (3U) |
#define | CAAM_RCMD_RTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTD_SHIFT)) & CAAM_RCMD_RTD_MASK) |
RCTL - RTIC Control Register | |
#define | CAAM_RCTL_IE_MASK (0x1U) |
#define | CAAM_RCTL_IE_SHIFT (0U) |
#define | CAAM_RCTL_IE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_IE_SHIFT)) & CAAM_RCTL_IE_MASK) |
#define | CAAM_RCTL_RREQS_MASK (0xEU) |
#define | CAAM_RCTL_RREQS_SHIFT (1U) |
#define | CAAM_RCTL_RREQS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RREQS_SHIFT)) & CAAM_RCTL_RREQS_MASK) |
#define | CAAM_RCTL_HOME_MASK (0xF0U) |
#define | CAAM_RCTL_HOME_SHIFT (4U) |
#define | CAAM_RCTL_HOME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_HOME_SHIFT)) & CAAM_RCTL_HOME_MASK) |
#define | CAAM_RCTL_RTME_MASK (0xF00U) |
#define | CAAM_RCTL_RTME_SHIFT (8U) |
#define | CAAM_RCTL_RTME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTME_SHIFT)) & CAAM_RCTL_RTME_MASK) |
#define | CAAM_RCTL_RTMU_MASK (0xF000U) |
#define | CAAM_RCTL_RTMU_SHIFT (12U) |
#define | CAAM_RCTL_RTMU(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTMU_SHIFT)) & CAAM_RCTL_RTMU_MASK) |
#define | CAAM_RCTL_RALG_MASK (0xF0000U) |
#define | CAAM_RCTL_RALG_SHIFT (16U) |
#define | CAAM_RCTL_RALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RALG_SHIFT)) & CAAM_RCTL_RALG_MASK) |
#define | CAAM_RCTL_RIDLE_MASK (0x100000U) |
#define | CAAM_RCTL_RIDLE_SHIFT (20U) |
#define | CAAM_RCTL_RIDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RIDLE_SHIFT)) & CAAM_RCTL_RIDLE_MASK) |
RTHR - RTIC Throttle Register | |
#define | CAAM_RTHR_RTHR_MASK (0xFFFFU) |
#define | CAAM_RTHR_RTHR_SHIFT (0U) |
#define | CAAM_RTHR_RTHR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTHR_RTHR_SHIFT)) & CAAM_RTHR_RTHR_MASK) |
RWDOG - RTIC Watchdog Timer | |
#define | CAAM_RWDOG_RWDOG_MASK (0xFFFFFFFFU) |
#define | CAAM_RWDOG_RWDOG_SHIFT (0U) |
#define | CAAM_RWDOG_RWDOG(x) (((uint64_t)(((uint64_t)(x)) << CAAM_RWDOG_RWDOG_SHIFT)) & CAAM_RWDOG_RWDOG_MASK) |
REND - RTIC Endian Register | |
#define | CAAM_REND_REPO_MASK (0xFU) |
#define | CAAM_REND_REPO_SHIFT (0U) |
#define | CAAM_REND_REPO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_REPO_SHIFT)) & CAAM_REND_REPO_MASK) |
#define | CAAM_REND_RBS_MASK (0xF0U) |
#define | CAAM_REND_RBS_SHIFT (4U) |
#define | CAAM_REND_RBS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RBS_SHIFT)) & CAAM_REND_RBS_MASK) |
#define | CAAM_REND_RHWS_MASK (0xF00U) |
#define | CAAM_REND_RHWS_SHIFT (8U) |
#define | CAAM_REND_RHWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RHWS_SHIFT)) & CAAM_REND_RHWS_MASK) |
#define | CAAM_REND_RWS_MASK (0xF000U) |
#define | CAAM_REND_RWS_SHIFT (12U) |
#define | CAAM_REND_RWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RWS_SHIFT)) & CAAM_REND_RWS_MASK) |
RMA - RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register | |
#define | CAAM_RMA_MEMBLKADDR_MASK (0xFFFFFFFFFU) |
#define | CAAM_RMA_MEMBLKADDR_SHIFT (0U) |
#define | CAAM_RMA_MEMBLKADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_RMA_MEMBLKADDR_SHIFT)) & CAAM_RMA_MEMBLKADDR_MASK) |
RML - RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register | |
#define | CAAM_RML_MEMBLKLEN_MASK (0xFFFFFFFFU) |
#define | CAAM_RML_MEMBLKLEN_SHIFT (0U) |
#define | CAAM_RML_MEMBLKLEN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RML_MEMBLKLEN_SHIFT)) & CAAM_RML_MEMBLKLEN_MASK) |
RMD - RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31 | |
#define | CAAM_RMD_RTIC_Hash_Result_MASK (0xFFFFFFFFU) |
#define | CAAM_RMD_RTIC_Hash_Result_SHIFT (0U) |
#define | CAAM_RMD_RTIC_Hash_Result(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RMD_RTIC_Hash_Result_SHIFT)) & CAAM_RMD_RTIC_Hash_Result_MASK) |
REIR0RTIC - Recoverable Error Interrupt Record 0 for RTIC | |
#define | CAAM_REIR0RTIC_TYPE_MASK (0x3000000U) |
#define | CAAM_REIR0RTIC_TYPE_SHIFT (24U) |
#define | CAAM_REIR0RTIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_TYPE_SHIFT)) & CAAM_REIR0RTIC_TYPE_MASK) |
#define | CAAM_REIR0RTIC_MISS_MASK (0x80000000U) |
#define | CAAM_REIR0RTIC_MISS_SHIFT (31U) |
#define | CAAM_REIR0RTIC_MISS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_MISS_SHIFT)) & CAAM_REIR0RTIC_MISS_MASK) |
REIR2RTIC - Recoverable Error Interrupt Record 2 for RTIC | |
#define | CAAM_REIR2RTIC_ADDR_MASK (0xFFFFFFFFFFFFFFFFU) |
#define | CAAM_REIR2RTIC_ADDR_SHIFT (0U) |
#define | CAAM_REIR2RTIC_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2RTIC_ADDR_SHIFT)) & CAAM_REIR2RTIC_ADDR_MASK) |
REIR4RTIC - Recoverable Error Interrupt Record 4 for RTIC | |
#define | CAAM_REIR4RTIC_ICID_MASK (0x7FFU) |
#define | CAAM_REIR4RTIC_ICID_SHIFT (0U) |
#define | CAAM_REIR4RTIC_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ICID_SHIFT)) & CAAM_REIR4RTIC_ICID_MASK) |
#define | CAAM_REIR4RTIC_DID_MASK (0x7800U) |
#define | CAAM_REIR4RTIC_DID_SHIFT (11U) |
#define | CAAM_REIR4RTIC_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_DID_SHIFT)) & CAAM_REIR4RTIC_DID_MASK) |
#define | CAAM_REIR4RTIC_AXCACHE_MASK (0xF0000U) |
#define | CAAM_REIR4RTIC_AXCACHE_SHIFT (16U) |
#define | CAAM_REIR4RTIC_AXCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXCACHE_SHIFT)) & CAAM_REIR4RTIC_AXCACHE_MASK) |
#define | CAAM_REIR4RTIC_AXPROT_MASK (0x700000U) |
#define | CAAM_REIR4RTIC_AXPROT_SHIFT (20U) |
#define | CAAM_REIR4RTIC_AXPROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXPROT_SHIFT)) & CAAM_REIR4RTIC_AXPROT_MASK) |
#define | CAAM_REIR4RTIC_RWB_MASK (0x800000U) |
#define | CAAM_REIR4RTIC_RWB_SHIFT (23U) |
#define | CAAM_REIR4RTIC_RWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_RWB_SHIFT)) & CAAM_REIR4RTIC_RWB_MASK) |
#define | CAAM_REIR4RTIC_ERR_MASK (0x30000000U) |
#define | CAAM_REIR4RTIC_ERR_SHIFT (28U) |
#define | CAAM_REIR4RTIC_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ERR_SHIFT)) & CAAM_REIR4RTIC_ERR_MASK) |
#define | CAAM_REIR4RTIC_MIX_MASK (0xC0000000U) |
#define | CAAM_REIR4RTIC_MIX_SHIFT (30U) |
#define | CAAM_REIR4RTIC_MIX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_MIX_SHIFT)) & CAAM_REIR4RTIC_MIX_MASK) |
REIR5RTIC - Recoverable Error Interrupt Record 5 for RTIC | |
#define | CAAM_REIR5RTIC_BID_MASK (0xF0000U) |
#define | CAAM_REIR5RTIC_BID_SHIFT (16U) |
#define | CAAM_REIR5RTIC_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_BID_SHIFT)) & CAAM_REIR5RTIC_BID_MASK) |
#define | CAAM_REIR5RTIC_SAFE_MASK (0x1000000U) |
#define | CAAM_REIR5RTIC_SAFE_SHIFT (24U) |
#define | CAAM_REIR5RTIC_SAFE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SAFE_SHIFT)) & CAAM_REIR5RTIC_SAFE_MASK) |
#define | CAAM_REIR5RTIC_SMA_MASK (0x2000000U) |
#define | CAAM_REIR5RTIC_SMA_SHIFT (25U) |
#define | CAAM_REIR5RTIC_SMA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SMA_SHIFT)) & CAAM_REIR5RTIC_SMA_MASK) |
CC1MR - CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms | |
#define | CAAM_CC1MR_ENC_MASK (0x1U) |
#define | CAAM_CC1MR_ENC_SHIFT (0U) |
#define | CAAM_CC1MR_ENC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ENC_SHIFT)) & CAAM_CC1MR_ENC_MASK) |
#define | CAAM_CC1MR_ICV_TEST_MASK (0x2U) |
#define | CAAM_CC1MR_ICV_TEST_SHIFT (1U) |
#define | CAAM_CC1MR_ICV_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ICV_TEST_SHIFT)) & CAAM_CC1MR_ICV_TEST_MASK) |
#define | CAAM_CC1MR_AS_MASK (0xCU) |
#define | CAAM_CC1MR_AS_SHIFT (2U) |
#define | CAAM_CC1MR_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AS_SHIFT)) & CAAM_CC1MR_AS_MASK) |
#define | CAAM_CC1MR_AAI_MASK (0x1FF0U) |
#define | CAAM_CC1MR_AAI_SHIFT (4U) |
#define | CAAM_CC1MR_AAI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AAI_SHIFT)) & CAAM_CC1MR_AAI_MASK) |
#define | CAAM_CC1MR_ALG_MASK (0xFF0000U) |
#define | CAAM_CC1MR_ALG_SHIFT (16U) |
#define | CAAM_CC1MR_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ALG_SHIFT)) & CAAM_CC1MR_ALG_MASK) |
CC1MR_PK - CCB 0 Class 1 Mode Register Format for Public Key Algorithms | |
#define | CAAM_CC1MR_PK_PKHA_MODE_LS_MASK (0xFFFU) |
#define | CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT (0U) |
#define | CAAM_CC1MR_PK_PKHA_MODE_LS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_LS_MASK) |
#define | CAAM_CC1MR_PK_PKHA_MODE_MS_MASK (0xF0000U) |
#define | CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT (16U) |
#define | CAAM_CC1MR_PK_PKHA_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_MS_MASK) |
CC1MR_RNG - CCB 0 Class 1 Mode Register Format for RNG4 | |
#define | CAAM_CC1MR_RNG_TST_MASK (0x1U) |
#define | CAAM_CC1MR_RNG_TST_SHIFT (0U) |
#define | CAAM_CC1MR_RNG_TST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_TST_SHIFT)) & CAAM_CC1MR_RNG_TST_MASK) |
#define | CAAM_CC1MR_RNG_PR_MASK (0x2U) |
#define | CAAM_CC1MR_RNG_PR_SHIFT (1U) |
#define | CAAM_CC1MR_RNG_PR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PR_SHIFT)) & CAAM_CC1MR_RNG_PR_MASK) |
#define | CAAM_CC1MR_RNG_AS_MASK (0xCU) |
#define | CAAM_CC1MR_RNG_AS_SHIFT (2U) |
#define | CAAM_CC1MR_RNG_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AS_SHIFT)) & CAAM_CC1MR_RNG_AS_MASK) |
#define | CAAM_CC1MR_RNG_SH_MASK (0x30U) |
#define | CAAM_CC1MR_RNG_SH_SHIFT (4U) |
#define | CAAM_CC1MR_RNG_SH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SH_SHIFT)) & CAAM_CC1MR_RNG_SH_MASK) |
#define | CAAM_CC1MR_RNG_NZB_MASK (0x100U) |
#define | CAAM_CC1MR_RNG_NZB_SHIFT (8U) |
#define | CAAM_CC1MR_RNG_NZB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_NZB_SHIFT)) & CAAM_CC1MR_RNG_NZB_MASK) |
#define | CAAM_CC1MR_RNG_OBP_MASK (0x200U) |
#define | CAAM_CC1MR_RNG_OBP_SHIFT (9U) |
#define | CAAM_CC1MR_RNG_OBP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_OBP_SHIFT)) & CAAM_CC1MR_RNG_OBP_MASK) |
#define | CAAM_CC1MR_RNG_PS_MASK (0x400U) |
#define | CAAM_CC1MR_RNG_PS_SHIFT (10U) |
#define | CAAM_CC1MR_RNG_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PS_SHIFT)) & CAAM_CC1MR_RNG_PS_MASK) |
#define | CAAM_CC1MR_RNG_AI_MASK (0x800U) |
#define | CAAM_CC1MR_RNG_AI_SHIFT (11U) |
#define | CAAM_CC1MR_RNG_AI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AI_SHIFT)) & CAAM_CC1MR_RNG_AI_MASK) |
#define | CAAM_CC1MR_RNG_SK_MASK (0x1000U) |
#define | CAAM_CC1MR_RNG_SK_SHIFT (12U) |
#define | CAAM_CC1MR_RNG_SK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SK_SHIFT)) & CAAM_CC1MR_RNG_SK_MASK) |
#define | CAAM_CC1MR_RNG_ALG_MASK (0xFF0000U) |
#define | CAAM_CC1MR_RNG_ALG_SHIFT (16U) |
#define | CAAM_CC1MR_RNG_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_ALG_SHIFT)) & CAAM_CC1MR_RNG_ALG_MASK) |
CC1KSR - CCB 0 Class 1 Key Size Register | |
#define | CAAM_CC1KSR_C1KS_MASK (0x7FU) |
#define | CAAM_CC1KSR_C1KS_SHIFT (0U) |
#define | CAAM_CC1KSR_C1KS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KSR_C1KS_SHIFT)) & CAAM_CC1KSR_C1KS_MASK) |
CC1DSR - CCB 0 Class 1 Data Size Register | |
#define | CAAM_CC1DSR_C1DS_MASK (0xFFFFFFFFU) |
#define | CAAM_CC1DSR_C1DS_SHIFT (0U) |
#define | CAAM_CC1DSR_C1DS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1DS_SHIFT)) & CAAM_CC1DSR_C1DS_MASK) |
#define | CAAM_CC1DSR_C1CY_MASK (0x100000000U) |
#define | CAAM_CC1DSR_C1CY_SHIFT (32U) |
#define | CAAM_CC1DSR_C1CY(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1CY_SHIFT)) & CAAM_CC1DSR_C1CY_MASK) |
#define | CAAM_CC1DSR_NUMBITS_MASK (0xE000000000000000U) |
#define | CAAM_CC1DSR_NUMBITS_SHIFT (61U) |
#define | CAAM_CC1DSR_NUMBITS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_NUMBITS_SHIFT)) & CAAM_CC1DSR_NUMBITS_MASK) |
CC1ICVSR - CCB 0 Class 1 ICV Size Register | |
#define | CAAM_CC1ICVSR_C1ICVS_MASK (0x1FU) |
#define | CAAM_CC1ICVSR_C1ICVS_SHIFT (0U) |
#define | CAAM_CC1ICVSR_C1ICVS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1ICVSR_C1ICVS_SHIFT)) & CAAM_CC1ICVSR_C1ICVS_MASK) |
CCCTRL - CCB 0 CHA Control Register | |
#define | CAAM_CCCTRL_CCB_MASK (0x1U) |
#define | CAAM_CCCTRL_CCB_SHIFT (0U) |
#define | CAAM_CCCTRL_CCB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CCB_SHIFT)) & CAAM_CCCTRL_CCB_MASK) |
#define | CAAM_CCCTRL_AES_MASK (0x2U) |
#define | CAAM_CCCTRL_AES_SHIFT (1U) |
#define | CAAM_CCCTRL_AES(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_AES_SHIFT)) & CAAM_CCCTRL_AES_MASK) |
#define | CAAM_CCCTRL_DES_MASK (0x4U) |
#define | CAAM_CCCTRL_DES_SHIFT (2U) |
#define | CAAM_CCCTRL_DES(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_DES_SHIFT)) & CAAM_CCCTRL_DES_MASK) |
#define | CAAM_CCCTRL_PK_MASK (0x40U) |
#define | CAAM_CCCTRL_PK_SHIFT (6U) |
#define | CAAM_CCCTRL_PK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_PK_SHIFT)) & CAAM_CCCTRL_PK_MASK) |
#define | CAAM_CCCTRL_MD_MASK (0x80U) |
#define | CAAM_CCCTRL_MD_SHIFT (7U) |
#define | CAAM_CCCTRL_MD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_MD_SHIFT)) & CAAM_CCCTRL_MD_MASK) |
#define | CAAM_CCCTRL_CRC_MASK (0x100U) |
#define | CAAM_CCCTRL_CRC_SHIFT (8U) |
#define | CAAM_CCCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CRC_SHIFT)) & CAAM_CCCTRL_CRC_MASK) |
#define | CAAM_CCCTRL_RNG_MASK (0x200U) |
#define | CAAM_CCCTRL_RNG_SHIFT (9U) |
#define | CAAM_CCCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_RNG_SHIFT)) & CAAM_CCCTRL_RNG_MASK) |
#define | CAAM_CCCTRL_UA0_MASK (0x10000U) |
#define | CAAM_CCCTRL_UA0_SHIFT (16U) |
#define | CAAM_CCCTRL_UA0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA0_SHIFT)) & CAAM_CCCTRL_UA0_MASK) |
#define | CAAM_CCCTRL_UA1_MASK (0x20000U) |
#define | CAAM_CCCTRL_UA1_SHIFT (17U) |
#define | CAAM_CCCTRL_UA1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA1_SHIFT)) & CAAM_CCCTRL_UA1_MASK) |
#define | CAAM_CCCTRL_UA2_MASK (0x40000U) |
#define | CAAM_CCCTRL_UA2_SHIFT (18U) |
#define | CAAM_CCCTRL_UA2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA2_SHIFT)) & CAAM_CCCTRL_UA2_MASK) |
#define | CAAM_CCCTRL_UA3_MASK (0x80000U) |
#define | CAAM_CCCTRL_UA3_SHIFT (19U) |
#define | CAAM_CCCTRL_UA3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA3_SHIFT)) & CAAM_CCCTRL_UA3_MASK) |
#define | CAAM_CCCTRL_UB0_MASK (0x100000U) |
#define | CAAM_CCCTRL_UB0_SHIFT (20U) |
#define | CAAM_CCCTRL_UB0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB0_SHIFT)) & CAAM_CCCTRL_UB0_MASK) |
#define | CAAM_CCCTRL_UB1_MASK (0x200000U) |
#define | CAAM_CCCTRL_UB1_SHIFT (21U) |
#define | CAAM_CCCTRL_UB1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB1_SHIFT)) & CAAM_CCCTRL_UB1_MASK) |
#define | CAAM_CCCTRL_UB2_MASK (0x400000U) |
#define | CAAM_CCCTRL_UB2_SHIFT (22U) |
#define | CAAM_CCCTRL_UB2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB2_SHIFT)) & CAAM_CCCTRL_UB2_MASK) |
#define | CAAM_CCCTRL_UB3_MASK (0x800000U) |
#define | CAAM_CCCTRL_UB3_SHIFT (23U) |
#define | CAAM_CCCTRL_UB3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB3_SHIFT)) & CAAM_CCCTRL_UB3_MASK) |
#define | CAAM_CCCTRL_UN_MASK (0x1000000U) |
#define | CAAM_CCCTRL_UN_SHIFT (24U) |
#define | CAAM_CCCTRL_UN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UN_SHIFT)) & CAAM_CCCTRL_UN_MASK) |
#define | CAAM_CCCTRL_UA_MASK (0x4000000U) |
#define | CAAM_CCCTRL_UA_SHIFT (26U) |
#define | CAAM_CCCTRL_UA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA_SHIFT)) & CAAM_CCCTRL_UA_MASK) |
#define | CAAM_CCCTRL_UB_MASK (0x8000000U) |
#define | CAAM_CCCTRL_UB_SHIFT (27U) |
#define | CAAM_CCCTRL_UB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB_SHIFT)) & CAAM_CCCTRL_UB_MASK) |
CICTL - CCB 0 Interrupt Control Register | |
#define | CAAM_CICTL_ADI_MASK (0x2U) |
#define | CAAM_CICTL_ADI_SHIFT (1U) |
#define | CAAM_CICTL_ADI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_ADI_SHIFT)) & CAAM_CICTL_ADI_MASK) |
#define | CAAM_CICTL_DDI_MASK (0x4U) |
#define | CAAM_CICTL_DDI_SHIFT (2U) |
#define | CAAM_CICTL_DDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DDI_SHIFT)) & CAAM_CICTL_DDI_MASK) |
#define | CAAM_CICTL_PDI_MASK (0x40U) |
#define | CAAM_CICTL_PDI_SHIFT (6U) |
#define | CAAM_CICTL_PDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PDI_SHIFT)) & CAAM_CICTL_PDI_MASK) |
#define | CAAM_CICTL_MDI_MASK (0x80U) |
#define | CAAM_CICTL_MDI_SHIFT (7U) |
#define | CAAM_CICTL_MDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MDI_SHIFT)) & CAAM_CICTL_MDI_MASK) |
#define | CAAM_CICTL_CDI_MASK (0x100U) |
#define | CAAM_CICTL_CDI_SHIFT (8U) |
#define | CAAM_CICTL_CDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CDI_SHIFT)) & CAAM_CICTL_CDI_MASK) |
#define | CAAM_CICTL_RNDI_MASK (0x200U) |
#define | CAAM_CICTL_RNDI_SHIFT (9U) |
#define | CAAM_CICTL_RNDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNDI_SHIFT)) & CAAM_CICTL_RNDI_MASK) |
#define | CAAM_CICTL_AEI_MASK (0x20000U) |
#define | CAAM_CICTL_AEI_SHIFT (17U) |
#define | CAAM_CICTL_AEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_AEI_SHIFT)) & CAAM_CICTL_AEI_MASK) |
#define | CAAM_CICTL_DEI_MASK (0x40000U) |
#define | CAAM_CICTL_DEI_SHIFT (18U) |
#define | CAAM_CICTL_DEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DEI_SHIFT)) & CAAM_CICTL_DEI_MASK) |
#define | CAAM_CICTL_PEI_MASK (0x400000U) |
#define | CAAM_CICTL_PEI_SHIFT (22U) |
#define | CAAM_CICTL_PEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PEI_SHIFT)) & CAAM_CICTL_PEI_MASK) |
#define | CAAM_CICTL_MEI_MASK (0x800000U) |
#define | CAAM_CICTL_MEI_SHIFT (23U) |
#define | CAAM_CICTL_MEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MEI_SHIFT)) & CAAM_CICTL_MEI_MASK) |
#define | CAAM_CICTL_CEI_MASK (0x1000000U) |
#define | CAAM_CICTL_CEI_SHIFT (24U) |
#define | CAAM_CICTL_CEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CEI_SHIFT)) & CAAM_CICTL_CEI_MASK) |
#define | CAAM_CICTL_RNEI_MASK (0x2000000U) |
#define | CAAM_CICTL_RNEI_SHIFT (25U) |
#define | CAAM_CICTL_RNEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNEI_SHIFT)) & CAAM_CICTL_RNEI_MASK) |
CCWR - CCB 0 Clear Written Register | |
#define | CAAM_CCWR_C1M_MASK (0x1U) |
#define | CAAM_CCWR_C1M_SHIFT (0U) |
#define | CAAM_CCWR_C1M(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1M_SHIFT)) & CAAM_CCWR_C1M_MASK) |
#define | CAAM_CCWR_C1DS_MASK (0x4U) |
#define | CAAM_CCWR_C1DS_SHIFT (2U) |
#define | CAAM_CCWR_C1DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1DS_SHIFT)) & CAAM_CCWR_C1DS_MASK) |
#define | CAAM_CCWR_C1ICV_MASK (0x8U) |
#define | CAAM_CCWR_C1ICV_SHIFT (3U) |
#define | CAAM_CCWR_C1ICV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1ICV_SHIFT)) & CAAM_CCWR_C1ICV_MASK) |
#define | CAAM_CCWR_C1C_MASK (0x20U) |
#define | CAAM_CCWR_C1C_SHIFT (5U) |
#define | CAAM_CCWR_C1C(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1C_SHIFT)) & CAAM_CCWR_C1C_MASK) |
#define | CAAM_CCWR_C1K_MASK (0x40U) |
#define | CAAM_CCWR_C1K_SHIFT (6U) |
#define | CAAM_CCWR_C1K(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1K_SHIFT)) & CAAM_CCWR_C1K_MASK) |
#define | CAAM_CCWR_CPKA_MASK (0x1000U) |
#define | CAAM_CCWR_CPKA_SHIFT (12U) |
#define | CAAM_CCWR_CPKA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKA_SHIFT)) & CAAM_CCWR_CPKA_MASK) |
#define | CAAM_CCWR_CPKB_MASK (0x2000U) |
#define | CAAM_CCWR_CPKB_SHIFT (13U) |
#define | CAAM_CCWR_CPKB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKB_SHIFT)) & CAAM_CCWR_CPKB_MASK) |
#define | CAAM_CCWR_CPKN_MASK (0x4000U) |
#define | CAAM_CCWR_CPKN_SHIFT (14U) |
#define | CAAM_CCWR_CPKN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKN_SHIFT)) & CAAM_CCWR_CPKN_MASK) |
#define | CAAM_CCWR_CPKE_MASK (0x8000U) |
#define | CAAM_CCWR_CPKE_SHIFT (15U) |
#define | CAAM_CCWR_CPKE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKE_SHIFT)) & CAAM_CCWR_CPKE_MASK) |
#define | CAAM_CCWR_C2M_MASK (0x10000U) |
#define | CAAM_CCWR_C2M_SHIFT (16U) |
#define | CAAM_CCWR_C2M(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2M_SHIFT)) & CAAM_CCWR_C2M_MASK) |
#define | CAAM_CCWR_C2DS_MASK (0x40000U) |
#define | CAAM_CCWR_C2DS_SHIFT (18U) |
#define | CAAM_CCWR_C2DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2DS_SHIFT)) & CAAM_CCWR_C2DS_MASK) |
#define | CAAM_CCWR_C2C_MASK (0x200000U) |
#define | CAAM_CCWR_C2C_SHIFT (21U) |
#define | CAAM_CCWR_C2C(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2C_SHIFT)) & CAAM_CCWR_C2C_MASK) |
#define | CAAM_CCWR_C2K_MASK (0x400000U) |
#define | CAAM_CCWR_C2K_SHIFT (22U) |
#define | CAAM_CCWR_C2K(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2K_SHIFT)) & CAAM_CCWR_C2K_MASK) |
#define | CAAM_CCWR_CDS_MASK (0x2000000U) |
#define | CAAM_CCWR_CDS_SHIFT (25U) |
#define | CAAM_CCWR_CDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CDS_SHIFT)) & CAAM_CCWR_CDS_MASK) |
#define | CAAM_CCWR_C2D_MASK (0x4000000U) |
#define | CAAM_CCWR_C2D_SHIFT (26U) |
#define | CAAM_CCWR_C2D(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2D_SHIFT)) & CAAM_CCWR_C2D_MASK) |
#define | CAAM_CCWR_C1D_MASK (0x8000000U) |
#define | CAAM_CCWR_C1D_SHIFT (27U) |
#define | CAAM_CCWR_C1D(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1D_SHIFT)) & CAAM_CCWR_C1D_MASK) |
#define | CAAM_CCWR_C2RST_MASK (0x10000000U) |
#define | CAAM_CCWR_C2RST_SHIFT (28U) |
#define | CAAM_CCWR_C2RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2RST_SHIFT)) & CAAM_CCWR_C2RST_MASK) |
#define | CAAM_CCWR_C1RST_MASK (0x20000000U) |
#define | CAAM_CCWR_C1RST_SHIFT (29U) |
#define | CAAM_CCWR_C1RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1RST_SHIFT)) & CAAM_CCWR_C1RST_MASK) |
#define | CAAM_CCWR_COF_MASK (0x40000000U) |
#define | CAAM_CCWR_COF_SHIFT (30U) |
#define | CAAM_CCWR_COF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_COF_SHIFT)) & CAAM_CCWR_COF_MASK) |
#define | CAAM_CCWR_CIF_MASK (0x80000000U) |
#define | CAAM_CCWR_CIF_SHIFT (31U) |
#define | CAAM_CCWR_CIF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CIF_SHIFT)) & CAAM_CCWR_CIF_MASK) |
CCSTA_MS - CCB 0 Status and Error Register, most-significant half | |
#define | CAAM_CCSTA_MS_ERRID1_MASK (0xFU) |
#define | CAAM_CCSTA_MS_ERRID1_SHIFT (0U) |
#define | CAAM_CCSTA_MS_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID1_SHIFT)) & CAAM_CCSTA_MS_ERRID1_MASK) |
#define | CAAM_CCSTA_MS_CL1_MASK (0xF000U) |
#define | CAAM_CCSTA_MS_CL1_SHIFT (12U) |
#define | CAAM_CCSTA_MS_CL1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL1_SHIFT)) & CAAM_CCSTA_MS_CL1_MASK) |
#define | CAAM_CCSTA_MS_ERRID2_MASK (0xF0000U) |
#define | CAAM_CCSTA_MS_ERRID2_SHIFT (16U) |
#define | CAAM_CCSTA_MS_ERRID2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID2_SHIFT)) & CAAM_CCSTA_MS_ERRID2_MASK) |
#define | CAAM_CCSTA_MS_CL2_MASK (0xF0000000U) |
#define | CAAM_CCSTA_MS_CL2_SHIFT (28U) |
#define | CAAM_CCSTA_MS_CL2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL2_SHIFT)) & CAAM_CCSTA_MS_CL2_MASK) |
CCSTA_LS - CCB 0 Status and Error Register, least-significant half | |
#define | CAAM_CCSTA_LS_AB_MASK (0x2U) |
#define | CAAM_CCSTA_LS_AB_SHIFT (1U) |
#define | CAAM_CCSTA_LS_AB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_AB_SHIFT)) & CAAM_CCSTA_LS_AB_MASK) |
#define | CAAM_CCSTA_LS_DB_MASK (0x4U) |
#define | CAAM_CCSTA_LS_DB_SHIFT (2U) |
#define | CAAM_CCSTA_LS_DB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_DB_SHIFT)) & CAAM_CCSTA_LS_DB_MASK) |
#define | CAAM_CCSTA_LS_PB_MASK (0x40U) |
#define | CAAM_CCSTA_LS_PB_SHIFT (6U) |
#define | CAAM_CCSTA_LS_PB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PB_SHIFT)) & CAAM_CCSTA_LS_PB_MASK) |
#define | CAAM_CCSTA_LS_MB_MASK (0x80U) |
#define | CAAM_CCSTA_LS_MB_SHIFT (7U) |
#define | CAAM_CCSTA_LS_MB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_MB_SHIFT)) & CAAM_CCSTA_LS_MB_MASK) |
#define | CAAM_CCSTA_LS_CB_MASK (0x100U) |
#define | CAAM_CCSTA_LS_CB_SHIFT (8U) |
#define | CAAM_CCSTA_LS_CB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_CB_SHIFT)) & CAAM_CCSTA_LS_CB_MASK) |
#define | CAAM_CCSTA_LS_RNB_MASK (0x200U) |
#define | CAAM_CCSTA_LS_RNB_SHIFT (9U) |
#define | CAAM_CCSTA_LS_RNB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_RNB_SHIFT)) & CAAM_CCSTA_LS_RNB_MASK) |
#define | CAAM_CCSTA_LS_PDI_MASK (0x10000U) |
#define | CAAM_CCSTA_LS_PDI_SHIFT (16U) |
#define | CAAM_CCSTA_LS_PDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PDI_SHIFT)) & CAAM_CCSTA_LS_PDI_MASK) |
#define | CAAM_CCSTA_LS_SDI_MASK (0x20000U) |
#define | CAAM_CCSTA_LS_SDI_SHIFT (17U) |
#define | CAAM_CCSTA_LS_SDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SDI_SHIFT)) & CAAM_CCSTA_LS_SDI_MASK) |
#define | CAAM_CCSTA_LS_PEI_MASK (0x100000U) |
#define | CAAM_CCSTA_LS_PEI_SHIFT (20U) |
#define | CAAM_CCSTA_LS_PEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PEI_SHIFT)) & CAAM_CCSTA_LS_PEI_MASK) |
#define | CAAM_CCSTA_LS_SEI_MASK (0x200000U) |
#define | CAAM_CCSTA_LS_SEI_SHIFT (21U) |
#define | CAAM_CCSTA_LS_SEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SEI_SHIFT)) & CAAM_CCSTA_LS_SEI_MASK) |
#define | CAAM_CCSTA_LS_PRM_MASK (0x10000000U) |
#define | CAAM_CCSTA_LS_PRM_SHIFT (28U) |
#define | CAAM_CCSTA_LS_PRM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PRM_SHIFT)) & CAAM_CCSTA_LS_PRM_MASK) |
#define | CAAM_CCSTA_LS_GCD_MASK (0x20000000U) |
#define | CAAM_CCSTA_LS_GCD_SHIFT (29U) |
#define | CAAM_CCSTA_LS_GCD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_GCD_SHIFT)) & CAAM_CCSTA_LS_GCD_MASK) |
#define | CAAM_CCSTA_LS_PIZ_MASK (0x40000000U) |
#define | CAAM_CCSTA_LS_PIZ_SHIFT (30U) |
#define | CAAM_CCSTA_LS_PIZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PIZ_SHIFT)) & CAAM_CCSTA_LS_PIZ_MASK) |
CC1AADSZR - CCB 0 Class 1 AAD Size Register | |
#define | CAAM_CC1AADSZR_AASZ_MASK (0xFU) |
#define | CAAM_CC1AADSZR_AASZ_SHIFT (0U) |
#define | CAAM_CC1AADSZR_AASZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1AADSZR_AASZ_SHIFT)) & CAAM_CC1AADSZR_AASZ_MASK) |
CC1IVSZR - CCB 0 Class 1 IV Size Register | |
#define | CAAM_CC1IVSZR_IVSZ_MASK (0xFU) |
#define | CAAM_CC1IVSZR_IVSZ_SHIFT (0U) |
#define | CAAM_CC1IVSZR_IVSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1IVSZR_IVSZ_SHIFT)) & CAAM_CC1IVSZR_IVSZ_MASK) |
CPKASZR - PKHA A Size Register | |
#define | CAAM_CPKASZR_PKASZ_MASK (0x3FFU) |
#define | CAAM_CPKASZR_PKASZ_SHIFT (0U) |
#define | CAAM_CPKASZR_PKASZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKASZR_PKASZ_SHIFT)) & CAAM_CPKASZR_PKASZ_MASK) |
CPKBSZR - PKHA B Size Register | |
#define | CAAM_CPKBSZR_PKBSZ_MASK (0x3FFU) |
#define | CAAM_CPKBSZR_PKBSZ_SHIFT (0U) |
#define | CAAM_CPKBSZR_PKBSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKBSZR_PKBSZ_SHIFT)) & CAAM_CPKBSZR_PKBSZ_MASK) |
CPKNSZR - PKHA N Size Register | |
#define | CAAM_CPKNSZR_PKNSZ_MASK (0x3FFU) |
#define | CAAM_CPKNSZR_PKNSZ_SHIFT (0U) |
#define | CAAM_CPKNSZR_PKNSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKNSZR_PKNSZ_SHIFT)) & CAAM_CPKNSZR_PKNSZ_MASK) |
CPKESZR - PKHA E Size Register | |
#define | CAAM_CPKESZR_PKESZ_MASK (0x3FFU) |
#define | CAAM_CPKESZR_PKESZ_SHIFT (0U) |
#define | CAAM_CPKESZR_PKESZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKESZR_PKESZ_SHIFT)) & CAAM_CPKESZR_PKESZ_MASK) |
CC1CTXR - CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15 | |
#define | CAAM_CC1CTXR_C1CTX_MASK (0xFFFFFFFFU) |
#define | CAAM_CC1CTXR_C1CTX_SHIFT (0U) |
#define | CAAM_CC1CTXR_C1CTX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1CTXR_C1CTX_SHIFT)) & CAAM_CC1CTXR_C1CTX_MASK) |
CC1KR - CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7 | |
#define | CAAM_CC1KR_C1KEY_MASK (0xFFFFFFFFU) |
#define | CAAM_CC1KR_C1KEY_SHIFT (0U) |
#define | CAAM_CC1KR_C1KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KR_C1KEY_SHIFT)) & CAAM_CC1KR_C1KEY_MASK) |
CC2MR - CCB 0 Class 2 Mode Register | |
#define | CAAM_CC2MR_AP_MASK (0x1U) |
#define | CAAM_CC2MR_AP_SHIFT (0U) |
#define | CAAM_CC2MR_AP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AP_SHIFT)) & CAAM_CC2MR_AP_MASK) |
#define | CAAM_CC2MR_ICV_MASK (0x2U) |
#define | CAAM_CC2MR_ICV_SHIFT (1U) |
#define | CAAM_CC2MR_ICV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ICV_SHIFT)) & CAAM_CC2MR_ICV_MASK) |
#define | CAAM_CC2MR_AS_MASK (0xCU) |
#define | CAAM_CC2MR_AS_SHIFT (2U) |
#define | CAAM_CC2MR_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AS_SHIFT)) & CAAM_CC2MR_AS_MASK) |
#define | CAAM_CC2MR_AAI_MASK (0x1FF0U) |
#define | CAAM_CC2MR_AAI_SHIFT (4U) |
#define | CAAM_CC2MR_AAI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AAI_SHIFT)) & CAAM_CC2MR_AAI_MASK) |
#define | CAAM_CC2MR_ALG_MASK (0xFF0000U) |
#define | CAAM_CC2MR_ALG_SHIFT (16U) |
#define | CAAM_CC2MR_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ALG_SHIFT)) & CAAM_CC2MR_ALG_MASK) |
CC2KSR - CCB 0 Class 2 Key Size Register | |
#define | CAAM_CC2KSR_C2KS_MASK (0xFFU) |
#define | CAAM_CC2KSR_C2KS_SHIFT (0U) |
#define | CAAM_CC2KSR_C2KS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KSR_C2KS_SHIFT)) & CAAM_CC2KSR_C2KS_MASK) |
CC2DSR - CCB 0 Class 2 Data Size Register | |
#define | CAAM_CC2DSR_C2DS_MASK (0xFFFFFFFFU) |
#define | CAAM_CC2DSR_C2DS_SHIFT (0U) |
#define | CAAM_CC2DSR_C2DS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2DS_SHIFT)) & CAAM_CC2DSR_C2DS_MASK) |
#define | CAAM_CC2DSR_C2CY_MASK (0x100000000U) |
#define | CAAM_CC2DSR_C2CY_SHIFT (32U) |
#define | CAAM_CC2DSR_C2CY(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2CY_SHIFT)) & CAAM_CC2DSR_C2CY_MASK) |
#define | CAAM_CC2DSR_NUMBITS_MASK (0xE000000000000000U) |
#define | CAAM_CC2DSR_NUMBITS_SHIFT (61U) |
#define | CAAM_CC2DSR_NUMBITS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_NUMBITS_SHIFT)) & CAAM_CC2DSR_NUMBITS_MASK) |
CC2ICVSZR - CCB 0 Class 2 ICV Size Register | |
#define | CAAM_CC2ICVSZR_ICVSZ_MASK (0xFU) |
#define | CAAM_CC2ICVSZR_ICVSZ_SHIFT (0U) |
#define | CAAM_CC2ICVSZR_ICVSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2ICVSZR_ICVSZ_SHIFT)) & CAAM_CC2ICVSZR_ICVSZ_MASK) |
CC2CTXR - CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17 | |
#define | CAAM_CC2CTXR_C2CTXR_MASK (0xFFFFFFFFU) |
#define | CAAM_CC2CTXR_C2CTXR_SHIFT (0U) |
#define | CAAM_CC2CTXR_C2CTXR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2CTXR_C2CTXR_SHIFT)) & CAAM_CC2CTXR_C2CTXR_MASK) |
CC2KEYR - CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31 | |
#define | CAAM_CC2KEYR_C2KEY_MASK (0xFFFFFFFFU) |
#define | CAAM_CC2KEYR_C2KEY_SHIFT (0U) |
#define | CAAM_CC2KEYR_C2KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KEYR_C2KEY_SHIFT)) & CAAM_CC2KEYR_C2KEY_MASK) |
CFIFOSTA - CCB 0 FIFO Status Register | |
#define | CAAM_CFIFOSTA_DECOOQHEAD_MASK (0xFFU) |
#define | CAAM_CFIFOSTA_DECOOQHEAD_SHIFT (0U) |
#define | CAAM_CFIFOSTA_DECOOQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DECOOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DECOOQHEAD_MASK) |
#define | CAAM_CFIFOSTA_DMAOQHEAD_MASK (0xFF00U) |
#define | CAAM_CFIFOSTA_DMAOQHEAD_SHIFT (8U) |
#define | CAAM_CFIFOSTA_DMAOQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DMAOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DMAOQHEAD_MASK) |
#define | CAAM_CFIFOSTA_C2IQHEAD_MASK (0xFF0000U) |
#define | CAAM_CFIFOSTA_C2IQHEAD_SHIFT (16U) |
#define | CAAM_CFIFOSTA_C2IQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C2IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C2IQHEAD_MASK) |
#define | CAAM_CFIFOSTA_C1IQHEAD_MASK (0xFF000000U) |
#define | CAAM_CFIFOSTA_C1IQHEAD_SHIFT (24U) |
#define | CAAM_CFIFOSTA_C1IQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C1IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C1IQHEAD_MASK) |
CNFIFO - CCB 0 iNformation FIFO When STYPE != 10b | |
#define | CAAM_CNFIFO_DL_MASK (0xFFFU) |
#define | CAAM_CNFIFO_DL_SHIFT (0U) |
#define | CAAM_CNFIFO_DL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DL_SHIFT)) & CAAM_CNFIFO_DL_MASK) |
#define | CAAM_CNFIFO_AST_MASK (0x4000U) |
#define | CAAM_CNFIFO_AST_SHIFT (14U) |
#define | CAAM_CNFIFO_AST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_AST_SHIFT)) & CAAM_CNFIFO_AST_MASK) |
#define | CAAM_CNFIFO_OC_MASK (0x8000U) |
#define | CAAM_CNFIFO_OC_SHIFT (15U) |
#define | CAAM_CNFIFO_OC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_OC_SHIFT)) & CAAM_CNFIFO_OC_MASK) |
#define | CAAM_CNFIFO_PTYPE_MASK (0x70000U) |
#define | CAAM_CNFIFO_PTYPE_SHIFT (16U) |
#define | CAAM_CNFIFO_PTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_PTYPE_SHIFT)) & CAAM_CNFIFO_PTYPE_MASK) |
#define | CAAM_CNFIFO_BND_MASK (0x80000U) |
#define | CAAM_CNFIFO_BND_SHIFT (19U) |
#define | CAAM_CNFIFO_BND(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_BND_SHIFT)) & CAAM_CNFIFO_BND_MASK) |
#define | CAAM_CNFIFO_DTYPE_MASK (0xF00000U) |
#define | CAAM_CNFIFO_DTYPE_SHIFT (20U) |
#define | CAAM_CNFIFO_DTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DTYPE_SHIFT)) & CAAM_CNFIFO_DTYPE_MASK) |
#define | CAAM_CNFIFO_STYPE_MASK (0x3000000U) |
#define | CAAM_CNFIFO_STYPE_SHIFT (24U) |
#define | CAAM_CNFIFO_STYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_STYPE_SHIFT)) & CAAM_CNFIFO_STYPE_MASK) |
#define | CAAM_CNFIFO_FC1_MASK (0x4000000U) |
#define | CAAM_CNFIFO_FC1_SHIFT (26U) |
#define | CAAM_CNFIFO_FC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC1_SHIFT)) & CAAM_CNFIFO_FC1_MASK) |
#define | CAAM_CNFIFO_FC2_MASK (0x8000000U) |
#define | CAAM_CNFIFO_FC2_SHIFT (27U) |
#define | CAAM_CNFIFO_FC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC2_SHIFT)) & CAAM_CNFIFO_FC2_MASK) |
#define | CAAM_CNFIFO_LC1_MASK (0x10000000U) |
#define | CAAM_CNFIFO_LC1_SHIFT (28U) |
#define | CAAM_CNFIFO_LC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC1_SHIFT)) & CAAM_CNFIFO_LC1_MASK) |
#define | CAAM_CNFIFO_LC2_MASK (0x20000000U) |
#define | CAAM_CNFIFO_LC2_SHIFT (29U) |
#define | CAAM_CNFIFO_LC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC2_SHIFT)) & CAAM_CNFIFO_LC2_MASK) |
#define | CAAM_CNFIFO_DEST_MASK (0xC0000000U) |
#define | CAAM_CNFIFO_DEST_SHIFT (30U) |
#define | CAAM_CNFIFO_DEST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DEST_SHIFT)) & CAAM_CNFIFO_DEST_MASK) |
CNFIFO_2 - CCB 0 iNformation FIFO When STYPE == 10b | |
#define | CAAM_CNFIFO_2_PL_MASK (0x7FU) |
#define | CAAM_CNFIFO_2_PL_SHIFT (0U) |
#define | CAAM_CNFIFO_2_PL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PL_SHIFT)) & CAAM_CNFIFO_2_PL_MASK) |
#define | CAAM_CNFIFO_2_PS_MASK (0x400U) |
#define | CAAM_CNFIFO_2_PS_SHIFT (10U) |
#define | CAAM_CNFIFO_2_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PS_SHIFT)) & CAAM_CNFIFO_2_PS_MASK) |
#define | CAAM_CNFIFO_2_BM_MASK (0x800U) |
#define | CAAM_CNFIFO_2_BM_SHIFT (11U) |
#define | CAAM_CNFIFO_2_BM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BM_SHIFT)) & CAAM_CNFIFO_2_BM_MASK) |
#define | CAAM_CNFIFO_2_PR_MASK (0x8000U) |
#define | CAAM_CNFIFO_2_PR_SHIFT (15U) |
#define | CAAM_CNFIFO_2_PR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PR_SHIFT)) & CAAM_CNFIFO_2_PR_MASK) |
#define | CAAM_CNFIFO_2_PTYPE_MASK (0x70000U) |
#define | CAAM_CNFIFO_2_PTYPE_SHIFT (16U) |
#define | CAAM_CNFIFO_2_PTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PTYPE_SHIFT)) & CAAM_CNFIFO_2_PTYPE_MASK) |
#define | CAAM_CNFIFO_2_BND_MASK (0x80000U) |
#define | CAAM_CNFIFO_2_BND_SHIFT (19U) |
#define | CAAM_CNFIFO_2_BND(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BND_SHIFT)) & CAAM_CNFIFO_2_BND_MASK) |
#define | CAAM_CNFIFO_2_DTYPE_MASK (0xF00000U) |
#define | CAAM_CNFIFO_2_DTYPE_SHIFT (20U) |
#define | CAAM_CNFIFO_2_DTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DTYPE_SHIFT)) & CAAM_CNFIFO_2_DTYPE_MASK) |
#define | CAAM_CNFIFO_2_STYPE_MASK (0x3000000U) |
#define | CAAM_CNFIFO_2_STYPE_SHIFT (24U) |
#define | CAAM_CNFIFO_2_STYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_STYPE_SHIFT)) & CAAM_CNFIFO_2_STYPE_MASK) |
#define | CAAM_CNFIFO_2_FC1_MASK (0x4000000U) |
#define | CAAM_CNFIFO_2_FC1_SHIFT (26U) |
#define | CAAM_CNFIFO_2_FC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC1_SHIFT)) & CAAM_CNFIFO_2_FC1_MASK) |
#define | CAAM_CNFIFO_2_FC2_MASK (0x8000000U) |
#define | CAAM_CNFIFO_2_FC2_SHIFT (27U) |
#define | CAAM_CNFIFO_2_FC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC2_SHIFT)) & CAAM_CNFIFO_2_FC2_MASK) |
#define | CAAM_CNFIFO_2_LC1_MASK (0x10000000U) |
#define | CAAM_CNFIFO_2_LC1_SHIFT (28U) |
#define | CAAM_CNFIFO_2_LC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC1_SHIFT)) & CAAM_CNFIFO_2_LC1_MASK) |
#define | CAAM_CNFIFO_2_LC2_MASK (0x20000000U) |
#define | CAAM_CNFIFO_2_LC2_SHIFT (29U) |
#define | CAAM_CNFIFO_2_LC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC2_SHIFT)) & CAAM_CNFIFO_2_LC2_MASK) |
#define | CAAM_CNFIFO_2_DEST_MASK (0xC0000000U) |
#define | CAAM_CNFIFO_2_DEST_SHIFT (30U) |
#define | CAAM_CNFIFO_2_DEST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DEST_SHIFT)) & CAAM_CNFIFO_2_DEST_MASK) |
CIFIFO - CCB 0 Input Data FIFO | |
#define | CAAM_CIFIFO_IFIFO_MASK (0xFFFFFFFFU) |
#define | CAAM_CIFIFO_IFIFO_SHIFT (0U) |
#define | CAAM_CIFIFO_IFIFO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CIFIFO_IFIFO_SHIFT)) & CAAM_CIFIFO_IFIFO_MASK) |
COFIFO - CCB 0 Output Data FIFO | |
#define | CAAM_COFIFO_OFIFO_MASK (0xFFFFFFFFFFFFFFFFU) |
#define | CAAM_COFIFO_OFIFO_SHIFT (0U) |
#define | CAAM_COFIFO_OFIFO(x) (((uint64_t)(((uint64_t)(x)) << CAAM_COFIFO_OFIFO_SHIFT)) & CAAM_COFIFO_OFIFO_MASK) |
DJQCR_MS - DECO0 Job Queue Control Register, most-significant half | |
#define | CAAM_DJQCR_MS_ID_MASK (0x7U) |
#define | CAAM_DJQCR_MS_ID_SHIFT (0U) |
#define | CAAM_DJQCR_MS_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ID_SHIFT)) & CAAM_DJQCR_MS_ID_MASK) |
#define | CAAM_DJQCR_MS_SRC_MASK (0x700U) |
#define | CAAM_DJQCR_MS_SRC_SHIFT (8U) |
#define | CAAM_DJQCR_MS_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SRC_SHIFT)) & CAAM_DJQCR_MS_SRC_MASK) |
#define | CAAM_DJQCR_MS_AMTD_MASK (0x8000U) |
#define | CAAM_DJQCR_MS_AMTD_SHIFT (15U) |
#define | CAAM_DJQCR_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_AMTD_SHIFT)) & CAAM_DJQCR_MS_AMTD_MASK) |
#define | CAAM_DJQCR_MS_SOB_MASK (0x10000U) |
#define | CAAM_DJQCR_MS_SOB_SHIFT (16U) |
#define | CAAM_DJQCR_MS_SOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SOB_SHIFT)) & CAAM_DJQCR_MS_SOB_MASK) |
#define | CAAM_DJQCR_MS_DWS_MASK (0x80000U) |
#define | CAAM_DJQCR_MS_DWS_SHIFT (19U) |
#define | CAAM_DJQCR_MS_DWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_DWS_SHIFT)) & CAAM_DJQCR_MS_DWS_MASK) |
#define | CAAM_DJQCR_MS_SHR_FROM_MASK (0x7000000U) |
#define | CAAM_DJQCR_MS_SHR_FROM_SHIFT (24U) |
#define | CAAM_DJQCR_MS_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SHR_FROM_SHIFT)) & CAAM_DJQCR_MS_SHR_FROM_MASK) |
#define | CAAM_DJQCR_MS_ILE_MASK (0x8000000U) |
#define | CAAM_DJQCR_MS_ILE_SHIFT (27U) |
#define | CAAM_DJQCR_MS_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ILE_SHIFT)) & CAAM_DJQCR_MS_ILE_MASK) |
#define | CAAM_DJQCR_MS_FOUR_MASK (0x10000000U) |
#define | CAAM_DJQCR_MS_FOUR_SHIFT (28U) |
#define | CAAM_DJQCR_MS_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_FOUR_SHIFT)) & CAAM_DJQCR_MS_FOUR_MASK) |
#define | CAAM_DJQCR_MS_WHL_MASK (0x20000000U) |
#define | CAAM_DJQCR_MS_WHL_SHIFT (29U) |
#define | CAAM_DJQCR_MS_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_WHL_SHIFT)) & CAAM_DJQCR_MS_WHL_MASK) |
#define | CAAM_DJQCR_MS_SING_MASK (0x40000000U) |
#define | CAAM_DJQCR_MS_SING_SHIFT (30U) |
#define | CAAM_DJQCR_MS_SING(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SING_SHIFT)) & CAAM_DJQCR_MS_SING_MASK) |
#define | CAAM_DJQCR_MS_STEP_MASK (0x80000000U) |
#define | CAAM_DJQCR_MS_STEP_SHIFT (31U) |
#define | CAAM_DJQCR_MS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_STEP_SHIFT)) & CAAM_DJQCR_MS_STEP_MASK) |
DJQCR_LS - DECO0 Job Queue Control Register, least-significant half | |
#define | CAAM_DJQCR_LS_CMD_MASK (0xFFFFFFFFU) |
#define | CAAM_DJQCR_LS_CMD_SHIFT (0U) |
#define | CAAM_DJQCR_LS_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_LS_CMD_SHIFT)) & CAAM_DJQCR_LS_CMD_MASK) |
DDAR - DECO0 Descriptor Address Register | |
#define | CAAM_DDAR_DPTR_MASK (0xFFFFFFFFFU) |
#define | CAAM_DDAR_DPTR_SHIFT (0U) |
#define | CAAM_DDAR_DPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DDAR_DPTR_SHIFT)) & CAAM_DDAR_DPTR_MASK) |
DOPSTA_MS - DECO0 Operation Status Register, most-significant half | |
#define | CAAM_DOPSTA_MS_STATUS_MASK (0xFFU) |
#define | CAAM_DOPSTA_MS_STATUS_SHIFT (0U) |
#define | CAAM_DOPSTA_MS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_SHIFT)) & CAAM_DOPSTA_MS_STATUS_MASK) |
#define | CAAM_DOPSTA_MS_COMMAND_INDEX_MASK (0x7F00U) |
#define | CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT (8U) |
#define | CAAM_DOPSTA_MS_COMMAND_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT)) & CAAM_DOPSTA_MS_COMMAND_INDEX_MASK) |
#define | CAAM_DOPSTA_MS_NLJ_MASK (0x8000000U) |
#define | CAAM_DOPSTA_MS_NLJ_SHIFT (27U) |
#define | CAAM_DOPSTA_MS_NLJ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_NLJ_SHIFT)) & CAAM_DOPSTA_MS_NLJ_MASK) |
#define | CAAM_DOPSTA_MS_STATUS_TYPE_MASK (0xF0000000U) |
#define | CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT (28U) |
#define | CAAM_DOPSTA_MS_STATUS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT)) & CAAM_DOPSTA_MS_STATUS_TYPE_MASK) |
DOPSTA_LS - DECO0 Operation Status Register, least-significant half | |
#define | CAAM_DOPSTA_LS_OUT_CT_MASK (0xFFFFFFFFU) |
#define | CAAM_DOPSTA_LS_OUT_CT_SHIFT (0U) |
#define | CAAM_DOPSTA_LS_OUT_CT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_LS_OUT_CT_SHIFT)) & CAAM_DOPSTA_LS_OUT_CT_MASK) |
DPDIDSR - DECO0 Primary DID Status Register | |
#define | CAAM_DPDIDSR_PRIM_DID_MASK (0xFU) |
#define | CAAM_DPDIDSR_PRIM_DID_SHIFT (0U) |
#define | CAAM_DPDIDSR_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_DID_SHIFT)) & CAAM_DPDIDSR_PRIM_DID_MASK) |
#define | CAAM_DPDIDSR_PRIM_ICID_MASK (0x3FF80000U) |
#define | CAAM_DPDIDSR_PRIM_ICID_SHIFT (19U) |
#define | CAAM_DPDIDSR_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_ICID_SHIFT)) & CAAM_DPDIDSR_PRIM_ICID_MASK) |
DODIDSR - DECO0 Output DID Status Register | |
#define | CAAM_DODIDSR_OUT_DID_MASK (0xFU) |
#define | CAAM_DODIDSR_OUT_DID_SHIFT (0U) |
#define | CAAM_DODIDSR_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_DID_SHIFT)) & CAAM_DODIDSR_OUT_DID_MASK) |
#define | CAAM_DODIDSR_OUT_ICID_MASK (0x3FF80000U) |
#define | CAAM_DODIDSR_OUT_ICID_SHIFT (19U) |
#define | CAAM_DODIDSR_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_ICID_SHIFT)) & CAAM_DODIDSR_OUT_ICID_MASK) |
DMTH_MS - DECO0 Math Register 0_MS..DECO0 Math Register 3_MS | |
#define | CAAM_DMTH_MS_MATH_MS_MASK (0xFFFFFFFFU) |
#define | CAAM_DMTH_MS_MATH_MS_SHIFT (0U) |
#define | CAAM_DMTH_MS_MATH_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_MS_MATH_MS_SHIFT)) & CAAM_DMTH_MS_MATH_MS_MASK) |
DMTH_LS - DECO0 Math Register 0_LS..DECO0 Math Register 3_LS | |
#define | CAAM_DMTH_LS_MATH_LS_MASK (0xFFFFFFFFU) |
#define | CAAM_DMTH_LS_MATH_LS_SHIFT (0U) |
#define | CAAM_DMTH_LS_MATH_LS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_LS_MATH_LS_SHIFT)) & CAAM_DMTH_LS_MATH_LS_MASK) |
DGTR_0 - DECO0 Gather Table Register 0 Word 0 | |
#define | CAAM_DGTR_0_ADDRESS_POINTER_MASK (0xFU) |
#define | CAAM_DGTR_0_ADDRESS_POINTER_SHIFT (0U) |
#define | CAAM_DGTR_0_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_0_ADDRESS_POINTER_MASK) |
DGTR_1 - DECO0 Gather Table Register 0 Word 1 | |
#define | CAAM_DGTR_1_ADDRESS_POINTER_MASK (0xFFFFFFFFU) |
#define | CAAM_DGTR_1_ADDRESS_POINTER_SHIFT (0U) |
#define | CAAM_DGTR_1_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_1_ADDRESS_POINTER_MASK) |
DGTR_2 - DECO0 Gather Table Register 0 Word 2 | |
#define | CAAM_DGTR_2_Length_MASK (0x3FFFFFFFU) |
#define | CAAM_DGTR_2_Length_SHIFT (0U) |
#define | CAAM_DGTR_2_Length(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_Length_SHIFT)) & CAAM_DGTR_2_Length_MASK) |
#define | CAAM_DGTR_2_F_MASK (0x40000000U) |
#define | CAAM_DGTR_2_F_SHIFT (30U) |
#define | CAAM_DGTR_2_F(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_F_SHIFT)) & CAAM_DGTR_2_F_MASK) |
#define | CAAM_DGTR_2_E_MASK (0x80000000U) |
#define | CAAM_DGTR_2_E_SHIFT (31U) |
#define | CAAM_DGTR_2_E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_E_SHIFT)) & CAAM_DGTR_2_E_MASK) |
DGTR_3 - DECO0 Gather Table Register 0 Word 3 | |
#define | CAAM_DGTR_3_Offset_MASK (0x1FFFU) |
#define | CAAM_DGTR_3_Offset_SHIFT (0U) |
#define | CAAM_DGTR_3_Offset(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_3_Offset_SHIFT)) & CAAM_DGTR_3_Offset_MASK) |
DSTR_0 - DECO0 Scatter Table Register 0 Word 0 | |
#define | CAAM_DSTR_0_ADDRESS_POINTER_MASK (0xFU) |
#define | CAAM_DSTR_0_ADDRESS_POINTER_SHIFT (0U) |
#define | CAAM_DSTR_0_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_0_ADDRESS_POINTER_MASK) |
DSTR_1 - DECO0 Scatter Table Register 0 Word 1 | |
#define | CAAM_DSTR_1_ADDRESS_POINTER_MASK (0xFFFFFFFFU) |
#define | CAAM_DSTR_1_ADDRESS_POINTER_SHIFT (0U) |
#define | CAAM_DSTR_1_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_1_ADDRESS_POINTER_MASK) |
DSTR_2 - DECO0 Scatter Table Register 0 Word 2 | |
#define | CAAM_DSTR_2_Length_MASK (0x3FFFFFFFU) |
#define | CAAM_DSTR_2_Length_SHIFT (0U) |
#define | CAAM_DSTR_2_Length(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_Length_SHIFT)) & CAAM_DSTR_2_Length_MASK) |
#define | CAAM_DSTR_2_F_MASK (0x40000000U) |
#define | CAAM_DSTR_2_F_SHIFT (30U) |
#define | CAAM_DSTR_2_F(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_F_SHIFT)) & CAAM_DSTR_2_F_MASK) |
#define | CAAM_DSTR_2_E_MASK (0x80000000U) |
#define | CAAM_DSTR_2_E_SHIFT (31U) |
#define | CAAM_DSTR_2_E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_E_SHIFT)) & CAAM_DSTR_2_E_MASK) |
DSTR_3 - DECO0 Scatter Table Register 0 Word 3 | |
#define | CAAM_DSTR_3_Offset_MASK (0x1FFFU) |
#define | CAAM_DSTR_3_Offset_SHIFT (0U) |
#define | CAAM_DSTR_3_Offset(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_3_Offset_SHIFT)) & CAAM_DSTR_3_Offset_MASK) |
DDESB - DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63 | |
#define | CAAM_DDESB_DESBW_MASK (0xFFFFFFFFU) |
#define | CAAM_DDESB_DESBW_SHIFT (0U) |
#define | CAAM_DDESB_DESBW(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDESB_DESBW_SHIFT)) & CAAM_DDESB_DESBW_MASK) |
DDJR - DECO0 Debug Job Register | |
#define | CAAM_DDJR_ID_MASK (0x7U) |
#define | CAAM_DDJR_ID_SHIFT (0U) |
#define | CAAM_DDJR_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ID_SHIFT)) & CAAM_DDJR_ID_MASK) |
#define | CAAM_DDJR_SRC_MASK (0x700U) |
#define | CAAM_DDJR_SRC_SHIFT (8U) |
#define | CAAM_DDJR_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SRC_SHIFT)) & CAAM_DDJR_SRC_MASK) |
#define | CAAM_DDJR_JDDS_MASK (0x4000U) |
#define | CAAM_DDJR_JDDS_SHIFT (14U) |
#define | CAAM_DDJR_JDDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_JDDS_SHIFT)) & CAAM_DDJR_JDDS_MASK) |
#define | CAAM_DDJR_AMTD_MASK (0x8000U) |
#define | CAAM_DDJR_AMTD_SHIFT (15U) |
#define | CAAM_DDJR_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_AMTD_SHIFT)) & CAAM_DDJR_AMTD_MASK) |
#define | CAAM_DDJR_GSD_MASK (0x10000U) |
#define | CAAM_DDJR_GSD_SHIFT (16U) |
#define | CAAM_DDJR_GSD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_GSD_SHIFT)) & CAAM_DDJR_GSD_MASK) |
#define | CAAM_DDJR_DWS_MASK (0x80000U) |
#define | CAAM_DDJR_DWS_SHIFT (19U) |
#define | CAAM_DDJR_DWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_DWS_SHIFT)) & CAAM_DDJR_DWS_MASK) |
#define | CAAM_DDJR_SHR_FROM_MASK (0x7000000U) |
#define | CAAM_DDJR_SHR_FROM_SHIFT (24U) |
#define | CAAM_DDJR_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SHR_FROM_SHIFT)) & CAAM_DDJR_SHR_FROM_MASK) |
#define | CAAM_DDJR_ILE_MASK (0x8000000U) |
#define | CAAM_DDJR_ILE_SHIFT (27U) |
#define | CAAM_DDJR_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ILE_SHIFT)) & CAAM_DDJR_ILE_MASK) |
#define | CAAM_DDJR_FOUR_MASK (0x10000000U) |
#define | CAAM_DDJR_FOUR_SHIFT (28U) |
#define | CAAM_DDJR_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_FOUR_SHIFT)) & CAAM_DDJR_FOUR_MASK) |
#define | CAAM_DDJR_WHL_MASK (0x20000000U) |
#define | CAAM_DDJR_WHL_SHIFT (29U) |
#define | CAAM_DDJR_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_WHL_SHIFT)) & CAAM_DDJR_WHL_MASK) |
#define | CAAM_DDJR_SING_MASK (0x40000000U) |
#define | CAAM_DDJR_SING_SHIFT (30U) |
#define | CAAM_DDJR_SING(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SING_SHIFT)) & CAAM_DDJR_SING_MASK) |
#define | CAAM_DDJR_STEP_MASK (0x80000000U) |
#define | CAAM_DDJR_STEP_SHIFT (31U) |
#define | CAAM_DDJR_STEP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_STEP_SHIFT)) & CAAM_DDJR_STEP_MASK) |
DDDR - DECO0 Debug DECO Register | |
#define | CAAM_DDDR_CT_MASK (0x1U) |
#define | CAAM_DDDR_CT_SHIFT (0U) |
#define | CAAM_DDDR_CT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CT_SHIFT)) & CAAM_DDDR_CT_MASK) |
#define | CAAM_DDDR_BRB_MASK (0x2U) |
#define | CAAM_DDDR_BRB_SHIFT (1U) |
#define | CAAM_DDDR_BRB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BRB_SHIFT)) & CAAM_DDDR_BRB_MASK) |
#define | CAAM_DDDR_BWB_MASK (0x4U) |
#define | CAAM_DDDR_BWB_SHIFT (2U) |
#define | CAAM_DDDR_BWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BWB_SHIFT)) & CAAM_DDDR_BWB_MASK) |
#define | CAAM_DDDR_NC_MASK (0x8U) |
#define | CAAM_DDDR_NC_SHIFT (3U) |
#define | CAAM_DDDR_NC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NC_SHIFT)) & CAAM_DDDR_NC_MASK) |
#define | CAAM_DDDR_CSA_MASK (0x10U) |
#define | CAAM_DDDR_CSA_SHIFT (4U) |
#define | CAAM_DDDR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CSA_SHIFT)) & CAAM_DDDR_CSA_MASK) |
#define | CAAM_DDDR_CMD_STAGE_MASK (0xE0U) |
#define | CAAM_DDDR_CMD_STAGE_SHIFT (5U) |
#define | CAAM_DDDR_CMD_STAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_STAGE_SHIFT)) & CAAM_DDDR_CMD_STAGE_MASK) |
#define | CAAM_DDDR_CMD_INDEX_MASK (0x3F00U) |
#define | CAAM_DDDR_CMD_INDEX_SHIFT (8U) |
#define | CAAM_DDDR_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_INDEX_SHIFT)) & CAAM_DDDR_CMD_INDEX_MASK) |
#define | CAAM_DDDR_NLJ_MASK (0x4000U) |
#define | CAAM_DDDR_NLJ_SHIFT (14U) |
#define | CAAM_DDDR_NLJ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NLJ_SHIFT)) & CAAM_DDDR_NLJ_MASK) |
#define | CAAM_DDDR_PTCL_RUN_MASK (0x8000U) |
#define | CAAM_DDDR_PTCL_RUN_SHIFT (15U) |
#define | CAAM_DDDR_PTCL_RUN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PTCL_RUN_SHIFT)) & CAAM_DDDR_PTCL_RUN_MASK) |
#define | CAAM_DDDR_PDB_STALL_MASK (0x30000U) |
#define | CAAM_DDDR_PDB_STALL_SHIFT (16U) |
#define | CAAM_DDDR_PDB_STALL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_STALL_SHIFT)) & CAAM_DDDR_PDB_STALL_MASK) |
#define | CAAM_DDDR_PDB_WB_ST_MASK (0xC0000U) |
#define | CAAM_DDDR_PDB_WB_ST_SHIFT (18U) |
#define | CAAM_DDDR_PDB_WB_ST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_WB_ST_SHIFT)) & CAAM_DDDR_PDB_WB_ST_MASK) |
#define | CAAM_DDDR_DECO_STATE_MASK (0xF00000U) |
#define | CAAM_DDDR_DECO_STATE_SHIFT (20U) |
#define | CAAM_DDDR_DECO_STATE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_DECO_STATE_SHIFT)) & CAAM_DDDR_DECO_STATE_MASK) |
#define | CAAM_DDDR_NSEQLSEL_MASK (0x3000000U) |
#define | CAAM_DDDR_NSEQLSEL_SHIFT (24U) |
#define | CAAM_DDDR_NSEQLSEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NSEQLSEL_SHIFT)) & CAAM_DDDR_NSEQLSEL_MASK) |
#define | CAAM_DDDR_SEQLSEL_MASK (0xC000000U) |
#define | CAAM_DDDR_SEQLSEL_SHIFT (26U) |
#define | CAAM_DDDR_SEQLSEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SEQLSEL_SHIFT)) & CAAM_DDDR_SEQLSEL_MASK) |
#define | CAAM_DDDR_TRCT_MASK (0x30000000U) |
#define | CAAM_DDDR_TRCT_SHIFT (28U) |
#define | CAAM_DDDR_TRCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_TRCT_SHIFT)) & CAAM_DDDR_TRCT_MASK) |
#define | CAAM_DDDR_SD_MASK (0x40000000U) |
#define | CAAM_DDDR_SD_SHIFT (30U) |
#define | CAAM_DDDR_SD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SD_SHIFT)) & CAAM_DDDR_SD_MASK) |
#define | CAAM_DDDR_VALID_MASK (0x80000000U) |
#define | CAAM_DDDR_VALID_SHIFT (31U) |
#define | CAAM_DDDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_VALID_SHIFT)) & CAAM_DDDR_VALID_MASK) |
DDJP - DECO0 Debug Job Pointer | |
#define | CAAM_DDJP_JDPTR_MASK (0xFFFFFFFFFU) |
#define | CAAM_DDJP_JDPTR_SHIFT (0U) |
#define | CAAM_DDJP_JDPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DDJP_JDPTR_SHIFT)) & CAAM_DDJP_JDPTR_MASK) |
DSDP - DECO0 Debug Shared Pointer | |
#define | CAAM_DSDP_SDPTR_MASK (0xFFFFFFFFFU) |
#define | CAAM_DSDP_SDPTR_SHIFT (0U) |
#define | CAAM_DSDP_SDPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DSDP_SDPTR_SHIFT)) & CAAM_DSDP_SDPTR_MASK) |
DDDR_MS - DECO0 Debug DID, most-significant half | |
#define | CAAM_DDDR_MS_PRIM_DID_MASK (0xFU) |
#define | CAAM_DDDR_MS_PRIM_DID_SHIFT (0U) |
#define | CAAM_DDDR_MS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_DID_SHIFT)) & CAAM_DDDR_MS_PRIM_DID_MASK) |
#define | CAAM_DDDR_MS_PRIM_TZ_MASK (0x10U) |
#define | CAAM_DDDR_MS_PRIM_TZ_SHIFT (4U) |
#define | CAAM_DDDR_MS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_TZ_SHIFT)) & CAAM_DDDR_MS_PRIM_TZ_MASK) |
#define | CAAM_DDDR_MS_PRIM_ICID_MASK (0xFFE0U) |
#define | CAAM_DDDR_MS_PRIM_ICID_SHIFT (5U) |
#define | CAAM_DDDR_MS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_ICID_SHIFT)) & CAAM_DDDR_MS_PRIM_ICID_MASK) |
#define | CAAM_DDDR_MS_OUT_DID_MASK (0xF0000U) |
#define | CAAM_DDDR_MS_OUT_DID_SHIFT (16U) |
#define | CAAM_DDDR_MS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_DID_SHIFT)) & CAAM_DDDR_MS_OUT_DID_MASK) |
#define | CAAM_DDDR_MS_OUT_ICID_MASK (0xFFE00000U) |
#define | CAAM_DDDR_MS_OUT_ICID_SHIFT (21U) |
#define | CAAM_DDDR_MS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_ICID_SHIFT)) & CAAM_DDDR_MS_OUT_ICID_MASK) |
DDDR_LS - DECO0 Debug DID, least-significant half | |
#define | CAAM_DDDR_LS_OUT_DID_MASK (0xFU) |
#define | CAAM_DDDR_LS_OUT_DID_SHIFT (0U) |
#define | CAAM_DDDR_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_DID_SHIFT)) & CAAM_DDDR_LS_OUT_DID_MASK) |
#define | CAAM_DDDR_LS_OUT_ICID_MASK (0x3FF80000U) |
#define | CAAM_DDDR_LS_OUT_ICID_SHIFT (19U) |
#define | CAAM_DDDR_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_ICID_SHIFT)) & CAAM_DDDR_LS_OUT_ICID_MASK) |
SOL - Sequence Output Length Register | |
#define | CAAM_SOL_SOL_MASK (0xFFFFFFFFU) |
#define | CAAM_SOL_SOL_SHIFT (0U) |
#define | CAAM_SOL_SOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SOL_SOL_SHIFT)) & CAAM_SOL_SOL_MASK) |
VSOL - Variable Sequence Output Length Register | |
#define | CAAM_VSOL_VSOL_MASK (0xFFFFFFFFU) |
#define | CAAM_VSOL_VSOL_SHIFT (0U) |
#define | CAAM_VSOL_VSOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_VSOL_VSOL_SHIFT)) & CAAM_VSOL_VSOL_MASK) |
SIL - Sequence Input Length Register | |
#define | CAAM_SIL_SIL_MASK (0xFFFFFFFFU) |
#define | CAAM_SIL_SIL_SHIFT (0U) |
#define | CAAM_SIL_SIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SIL_SIL_SHIFT)) & CAAM_SIL_SIL_MASK) |
VSIL - Variable Sequence Input Length Register | |
#define | CAAM_VSIL_VSIL_MASK (0xFFFFFFFFU) |
#define | CAAM_VSIL_VSIL_SHIFT (0U) |
#define | CAAM_VSIL_VSIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_VSIL_VSIL_SHIFT)) & CAAM_VSIL_VSIL_MASK) |
DPOVRD - Protocol Override Register | |
#define | CAAM_DPOVRD_DPOVRD_MASK (0xFFFFFFFFU) |
#define | CAAM_DPOVRD_DPOVRD_SHIFT (0U) |
#define | CAAM_DPOVRD_DPOVRD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPOVRD_DPOVRD_SHIFT)) & CAAM_DPOVRD_DPOVRD_MASK) |
UVSOL - Variable Sequence Output Length Register; Upper 32 bits | |
#define | CAAM_UVSOL_UVSOL_MASK (0xFFFFFFFFU) |
#define | CAAM_UVSOL_UVSOL_SHIFT (0U) |
#define | CAAM_UVSOL_UVSOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_UVSOL_UVSOL_SHIFT)) & CAAM_UVSOL_UVSOL_MASK) |
UVSIL - Variable Sequence Input Length Register; Upper 32 bits | |
#define | CAAM_UVSIL_UVSIL_MASK (0xFFFFFFFFU) |
#define | CAAM_UVSIL_UVSIL_SHIFT (0U) |
#define | CAAM_UVSIL_UVSIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_UVSIL_UVSIL_SHIFT)) & CAAM_UVSIL_UVSIL_MASK) |
MCR - Module Configuration register | |
#define | CAN_MCR_MAXMB_MASK (0x7FU) |
#define | CAN_MCR_MAXMB_SHIFT (0U) |
#define | CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) |
#define | CAN_MCR_IDAM_MASK (0x300U) |
#define | CAN_MCR_IDAM_SHIFT (8U) |
#define | CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) |
#define | CAN_MCR_FDEN_MASK (0x800U) |
#define | CAN_MCR_FDEN_SHIFT (11U) |
#define | CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) |
#define | CAN_MCR_AEN_MASK (0x1000U) |
#define | CAN_MCR_AEN_SHIFT (12U) |
#define | CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) |
#define | CAN_MCR_LPRIOEN_MASK (0x2000U) |
#define | CAN_MCR_LPRIOEN_SHIFT (13U) |
#define | CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) |
#define | CAN_MCR_DMA_MASK (0x8000U) |
#define | CAN_MCR_DMA_SHIFT (15U) |
#define | CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) |
#define | CAN_MCR_IRMQ_MASK (0x10000U) |
#define | CAN_MCR_IRMQ_SHIFT (16U) |
#define | CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) |
#define | CAN_MCR_SRXDIS_MASK (0x20000U) |
#define | CAN_MCR_SRXDIS_SHIFT (17U) |
#define | CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) |
#define | CAN_MCR_DOZE_MASK (0x40000U) |
#define | CAN_MCR_DOZE_SHIFT (18U) |
#define | CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) |
#define | CAN_MCR_WAKSRC_MASK (0x80000U) |
#define | CAN_MCR_WAKSRC_SHIFT (19U) |
#define | CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) |
#define | CAN_MCR_LPMACK_MASK (0x100000U) |
#define | CAN_MCR_LPMACK_SHIFT (20U) |
#define | CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) |
#define | CAN_MCR_WRNEN_MASK (0x200000U) |
#define | CAN_MCR_WRNEN_SHIFT (21U) |
#define | CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) |
#define | CAN_MCR_SLFWAK_MASK (0x400000U) |
#define | CAN_MCR_SLFWAK_SHIFT (22U) |
#define | CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) |
#define | CAN_MCR_SUPV_MASK (0x800000U) |
#define | CAN_MCR_SUPV_SHIFT (23U) |
#define | CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) |
#define | CAN_MCR_FRZACK_MASK (0x1000000U) |
#define | CAN_MCR_FRZACK_SHIFT (24U) |
#define | CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) |
#define | CAN_MCR_SOFTRST_MASK (0x2000000U) |
#define | CAN_MCR_SOFTRST_SHIFT (25U) |
#define | CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) |
#define | CAN_MCR_WAKMSK_MASK (0x4000000U) |
#define | CAN_MCR_WAKMSK_SHIFT (26U) |
#define | CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) |
#define | CAN_MCR_NOTRDY_MASK (0x8000000U) |
#define | CAN_MCR_NOTRDY_SHIFT (27U) |
#define | CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) |
#define | CAN_MCR_HALT_MASK (0x10000000U) |
#define | CAN_MCR_HALT_SHIFT (28U) |
#define | CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) |
#define | CAN_MCR_RFEN_MASK (0x20000000U) |
#define | CAN_MCR_RFEN_SHIFT (29U) |
#define | CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) |
#define | CAN_MCR_FRZ_MASK (0x40000000U) |
#define | CAN_MCR_FRZ_SHIFT (30U) |
#define | CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) |
#define | CAN_MCR_MDIS_MASK (0x80000000U) |
#define | CAN_MCR_MDIS_SHIFT (31U) |
#define | CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) |
CTRL1 - Control 1 register | |
#define | CAN_CTRL1_PROPSEG_MASK (0x7U) |
#define | CAN_CTRL1_PROPSEG_SHIFT (0U) |
#define | CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) |
#define | CAN_CTRL1_LOM_MASK (0x8U) |
#define | CAN_CTRL1_LOM_SHIFT (3U) |
#define | CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) |
#define | CAN_CTRL1_LBUF_MASK (0x10U) |
#define | CAN_CTRL1_LBUF_SHIFT (4U) |
#define | CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) |
#define | CAN_CTRL1_TSYN_MASK (0x20U) |
#define | CAN_CTRL1_TSYN_SHIFT (5U) |
#define | CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) |
#define | CAN_CTRL1_BOFFREC_MASK (0x40U) |
#define | CAN_CTRL1_BOFFREC_SHIFT (6U) |
#define | CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) |
#define | CAN_CTRL1_SMP_MASK (0x80U) |
#define | CAN_CTRL1_SMP_SHIFT (7U) |
#define | CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) |
#define | CAN_CTRL1_RWRNMSK_MASK (0x400U) |
#define | CAN_CTRL1_RWRNMSK_SHIFT (10U) |
#define | CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) |
#define | CAN_CTRL1_TWRNMSK_MASK (0x800U) |
#define | CAN_CTRL1_TWRNMSK_SHIFT (11U) |
#define | CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) |
#define | CAN_CTRL1_LPB_MASK (0x1000U) |
#define | CAN_CTRL1_LPB_SHIFT (12U) |
#define | CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) |
#define | CAN_CTRL1_CLKSRC_MASK (0x2000U) |
#define | CAN_CTRL1_CLKSRC_SHIFT (13U) |
#define | CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) |
#define | CAN_CTRL1_ERRMSK_MASK (0x4000U) |
#define | CAN_CTRL1_ERRMSK_SHIFT (14U) |
#define | CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) |
#define | CAN_CTRL1_BOFFMSK_MASK (0x8000U) |
#define | CAN_CTRL1_BOFFMSK_SHIFT (15U) |
#define | CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) |
#define | CAN_CTRL1_PSEG2_MASK (0x70000U) |
#define | CAN_CTRL1_PSEG2_SHIFT (16U) |
#define | CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) |
#define | CAN_CTRL1_PSEG1_MASK (0x380000U) |
#define | CAN_CTRL1_PSEG1_SHIFT (19U) |
#define | CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) |
#define | CAN_CTRL1_RJW_MASK (0xC00000U) |
#define | CAN_CTRL1_RJW_SHIFT (22U) |
#define | CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) |
#define | CAN_CTRL1_PRESDIV_MASK (0xFF000000U) |
#define | CAN_CTRL1_PRESDIV_SHIFT (24U) |
#define | CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) |
TIMER - Free Running Timer | |
#define | CAN_TIMER_TIMER_MASK (0xFFFFU) |
#define | CAN_TIMER_TIMER_SHIFT (0U) |
#define | CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) |
RXMGMASK - Rx Mailboxes Global Mask register | |
#define | CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) |
#define | CAN_RXMGMASK_MG_SHIFT (0U) |
#define | CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) |
RX14MASK - Rx 14 Mask register | |
#define | CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) |
#define | CAN_RX14MASK_RX14M_SHIFT (0U) |
#define | CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) |
RX15MASK - Rx 15 Mask register | |
#define | CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) |
#define | CAN_RX15MASK_RX15M_SHIFT (0U) |
#define | CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) |
ECR - Error Counter | |
#define | CAN_ECR_TXERRCNT_MASK (0xFFU) |
#define | CAN_ECR_TXERRCNT_SHIFT (0U) |
#define | CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) |
#define | CAN_ECR_RXERRCNT_MASK (0xFF00U) |
#define | CAN_ECR_RXERRCNT_SHIFT (8U) |
#define | CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) |
#define | CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) |
#define | CAN_ECR_TXERRCNT_FAST_SHIFT (16U) |
#define | CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) |
#define | CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) |
#define | CAN_ECR_RXERRCNT_FAST_SHIFT (24U) |
#define | CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) |
ESR1 - Error and Status 1 register | |
#define | CAN_ESR1_WAKINT_MASK (0x1U) |
#define | CAN_ESR1_WAKINT_SHIFT (0U) |
#define | CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) |
#define | CAN_ESR1_ERRINT_MASK (0x2U) |
#define | CAN_ESR1_ERRINT_SHIFT (1U) |
#define | CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) |
#define | CAN_ESR1_BOFFINT_MASK (0x4U) |
#define | CAN_ESR1_BOFFINT_SHIFT (2U) |
#define | CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) |
#define | CAN_ESR1_RX_MASK (0x8U) |
#define | CAN_ESR1_RX_SHIFT (3U) |
#define | CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) |
#define | CAN_ESR1_FLTCONF_MASK (0x30U) |
#define | CAN_ESR1_FLTCONF_SHIFT (4U) |
#define | CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) |
#define | CAN_ESR1_TX_MASK (0x40U) |
#define | CAN_ESR1_TX_SHIFT (6U) |
#define | CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) |
#define | CAN_ESR1_IDLE_MASK (0x80U) |
#define | CAN_ESR1_IDLE_SHIFT (7U) |
#define | CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) |
#define | CAN_ESR1_RXWRN_MASK (0x100U) |
#define | CAN_ESR1_RXWRN_SHIFT (8U) |
#define | CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) |
#define | CAN_ESR1_TXWRN_MASK (0x200U) |
#define | CAN_ESR1_TXWRN_SHIFT (9U) |
#define | CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) |
#define | CAN_ESR1_STFERR_MASK (0x400U) |
#define | CAN_ESR1_STFERR_SHIFT (10U) |
#define | CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) |
#define | CAN_ESR1_FRMERR_MASK (0x800U) |
#define | CAN_ESR1_FRMERR_SHIFT (11U) |
#define | CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) |
#define | CAN_ESR1_CRCERR_MASK (0x1000U) |
#define | CAN_ESR1_CRCERR_SHIFT (12U) |
#define | CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) |
#define | CAN_ESR1_ACKERR_MASK (0x2000U) |
#define | CAN_ESR1_ACKERR_SHIFT (13U) |
#define | CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) |
#define | CAN_ESR1_BIT0ERR_MASK (0x4000U) |
#define | CAN_ESR1_BIT0ERR_SHIFT (14U) |
#define | CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) |
#define | CAN_ESR1_BIT1ERR_MASK (0x8000U) |
#define | CAN_ESR1_BIT1ERR_SHIFT (15U) |
#define | CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) |
#define | CAN_ESR1_RWRNINT_MASK (0x10000U) |
#define | CAN_ESR1_RWRNINT_SHIFT (16U) |
#define | CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) |
#define | CAN_ESR1_TWRNINT_MASK (0x20000U) |
#define | CAN_ESR1_TWRNINT_SHIFT (17U) |
#define | CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) |
#define | CAN_ESR1_SYNCH_MASK (0x40000U) |
#define | CAN_ESR1_SYNCH_SHIFT (18U) |
#define | CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) |
#define | CAN_ESR1_BOFFDONEINT_MASK (0x80000U) |
#define | CAN_ESR1_BOFFDONEINT_SHIFT (19U) |
#define | CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) |
#define | CAN_ESR1_ERRINT_FAST_MASK (0x100000U) |
#define | CAN_ESR1_ERRINT_FAST_SHIFT (20U) |
#define | CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) |
#define | CAN_ESR1_ERROVR_MASK (0x200000U) |
#define | CAN_ESR1_ERROVR_SHIFT (21U) |
#define | CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) |
#define | CAN_ESR1_STFERR_FAST_MASK (0x4000000U) |
#define | CAN_ESR1_STFERR_FAST_SHIFT (26U) |
#define | CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) |
#define | CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) |
#define | CAN_ESR1_FRMERR_FAST_SHIFT (27U) |
#define | CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) |
#define | CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) |
#define | CAN_ESR1_CRCERR_FAST_SHIFT (28U) |
#define | CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) |
#define | CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) |
#define | CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) |
#define | CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) |
#define | CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) |
#define | CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) |
#define | CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) |
IMASK2 - Interrupt Masks 2 register | |
#define | CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU) |
#define | CAN_IMASK2_BUF63TO32M_SHIFT (0U) |
#define | CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK) |
IMASK1 - Interrupt Masks 1 register | |
#define | CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) |
#define | CAN_IMASK1_BUF31TO0M_SHIFT (0U) |
#define | CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) |
IFLAG2 - Interrupt Flags 2 register | |
#define | CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU) |
#define | CAN_IFLAG2_BUF63TO32I_SHIFT (0U) |
#define | CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK) |
IFLAG1 - Interrupt Flags 1 register | |
#define | CAN_IFLAG1_BUF0I_MASK (0x1U) |
#define | CAN_IFLAG1_BUF0I_SHIFT (0U) |
#define | CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) |
#define | CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) |
#define | CAN_IFLAG1_BUF4TO1I_SHIFT (1U) |
#define | CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) |
#define | CAN_IFLAG1_BUF5I_MASK (0x20U) |
#define | CAN_IFLAG1_BUF5I_SHIFT (5U) |
#define | CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) |
#define | CAN_IFLAG1_BUF6I_MASK (0x40U) |
#define | CAN_IFLAG1_BUF6I_SHIFT (6U) |
#define | CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) |
#define | CAN_IFLAG1_BUF7I_MASK (0x80U) |
#define | CAN_IFLAG1_BUF7I_SHIFT (7U) |
#define | CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) |
#define | CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) |
#define | CAN_IFLAG1_BUF31TO8I_SHIFT (8U) |
#define | CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) |
CTRL2 - Control 2 register | |
#define | CAN_CTRL2_EDFLTDIS_MASK (0x800U) |
#define | CAN_CTRL2_EDFLTDIS_SHIFT (11U) |
#define | CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) |
#define | CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) |
#define | CAN_CTRL2_ISOCANFDEN_SHIFT (12U) |
#define | CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) |
#define | CAN_CTRL2_PREXCEN_MASK (0x4000U) |
#define | CAN_CTRL2_PREXCEN_SHIFT (14U) |
#define | CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) |
#define | CAN_CTRL2_TIMER_SRC_MASK (0x8000U) |
#define | CAN_CTRL2_TIMER_SRC_SHIFT (15U) |
#define | CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK) |
#define | CAN_CTRL2_EACEN_MASK (0x10000U) |
#define | CAN_CTRL2_EACEN_SHIFT (16U) |
#define | CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) |
#define | CAN_CTRL2_RRS_MASK (0x20000U) |
#define | CAN_CTRL2_RRS_SHIFT (17U) |
#define | CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) |
#define | CAN_CTRL2_MRP_MASK (0x40000U) |
#define | CAN_CTRL2_MRP_SHIFT (18U) |
#define | CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) |
#define | CAN_CTRL2_TASD_MASK (0xF80000U) |
#define | CAN_CTRL2_TASD_SHIFT (19U) |
#define | CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) |
#define | CAN_CTRL2_RFFN_MASK (0xF000000U) |
#define | CAN_CTRL2_RFFN_SHIFT (24U) |
#define | CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) |
#define | CAN_CTRL2_WRMFRZ_MASK (0x10000000U) |
#define | CAN_CTRL2_WRMFRZ_SHIFT (28U) |
#define | CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) |
#define | CAN_CTRL2_ECRWRE_MASK (0x20000000U) |
#define | CAN_CTRL2_ECRWRE_SHIFT (29U) |
#define | CAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK) |
#define | CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) |
#define | CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) |
#define | CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) |
#define | CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) |
#define | CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) |
#define | CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) |
#define | ENC_CTRL2_UPDHLD_MASK (0x1U) |
#define | ENC_CTRL2_UPDHLD_SHIFT (0U) |
#define | ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) |
#define | ENC_CTRL2_UPDPOS_MASK (0x2U) |
#define | ENC_CTRL2_UPDPOS_SHIFT (1U) |
#define | ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) |
#define | ENC_CTRL2_MOD_MASK (0x4U) |
#define | ENC_CTRL2_MOD_SHIFT (2U) |
#define | ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) |
#define | ENC_CTRL2_DIR_MASK (0x8U) |
#define | ENC_CTRL2_DIR_SHIFT (3U) |
#define | ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) |
#define | ENC_CTRL2_RUIE_MASK (0x10U) |
#define | ENC_CTRL2_RUIE_SHIFT (4U) |
#define | ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) |
#define | ENC_CTRL2_RUIRQ_MASK (0x20U) |
#define | ENC_CTRL2_RUIRQ_SHIFT (5U) |
#define | ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) |
#define | ENC_CTRL2_ROIE_MASK (0x40U) |
#define | ENC_CTRL2_ROIE_SHIFT (6U) |
#define | ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) |
#define | ENC_CTRL2_ROIRQ_MASK (0x80U) |
#define | ENC_CTRL2_ROIRQ_SHIFT (7U) |
#define | ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) |
#define | ENC_CTRL2_REVMOD_MASK (0x100U) |
#define | ENC_CTRL2_REVMOD_SHIFT (8U) |
#define | ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) |
#define | ENC_CTRL2_OUTCTL_MASK (0x200U) |
#define | ENC_CTRL2_OUTCTL_SHIFT (9U) |
#define | ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) |
#define | ENC_CTRL2_SABIE_MASK (0x400U) |
#define | ENC_CTRL2_SABIE_SHIFT (10U) |
#define | ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) |
#define | ENC_CTRL2_SABIRQ_MASK (0x800U) |
#define | ENC_CTRL2_SABIRQ_SHIFT (11U) |
#define | ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) |
#define | PWM_CTRL2_CLK_SEL_MASK (0x3U) |
#define | PWM_CTRL2_CLK_SEL_SHIFT (0U) |
#define | PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) |
#define | PWM_CTRL2_RELOAD_SEL_MASK (0x4U) |
#define | PWM_CTRL2_RELOAD_SEL_SHIFT (2U) |
#define | PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) |
#define | PWM_CTRL2_FORCE_SEL_MASK (0x38U) |
#define | PWM_CTRL2_FORCE_SEL_SHIFT (3U) |
#define | PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) |
#define | PWM_CTRL2_FORCE_MASK (0x40U) |
#define | PWM_CTRL2_FORCE_SHIFT (6U) |
#define | PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) |
#define | PWM_CTRL2_FRCEN_MASK (0x80U) |
#define | PWM_CTRL2_FRCEN_SHIFT (7U) |
#define | PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) |
#define | PWM_CTRL2_INIT_SEL_MASK (0x300U) |
#define | PWM_CTRL2_INIT_SEL_SHIFT (8U) |
#define | PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) |
#define | PWM_CTRL2_PWMX_INIT_MASK (0x400U) |
#define | PWM_CTRL2_PWMX_INIT_SHIFT (10U) |
#define | PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) |
#define | PWM_CTRL2_PWM45_INIT_MASK (0x800U) |
#define | PWM_CTRL2_PWM45_INIT_SHIFT (11U) |
#define | PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) |
#define | PWM_CTRL2_PWM23_INIT_MASK (0x1000U) |
#define | PWM_CTRL2_PWM23_INIT_SHIFT (12U) |
#define | PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) |
#define | PWM_CTRL2_INDEP_MASK (0x2000U) |
#define | PWM_CTRL2_INDEP_SHIFT (13U) |
#define | PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) |
#define | PWM_CTRL2_WAITEN_MASK (0x4000U) |
#define | PWM_CTRL2_WAITEN_SHIFT (14U) |
#define | PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK) |
#define | PWM_CTRL2_DBGEN_MASK (0x8000U) |
#define | PWM_CTRL2_DBGEN_SHIFT (15U) |
#define | PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) |
ESR2 - Error and Status 2 register | |
#define | CAN_ESR2_IMB_MASK (0x2000U) |
#define | CAN_ESR2_IMB_SHIFT (13U) |
#define | CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) |
#define | CAN_ESR2_VPS_MASK (0x4000U) |
#define | CAN_ESR2_VPS_SHIFT (14U) |
#define | CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) |
#define | CAN_ESR2_LPTM_MASK (0x7F0000U) |
#define | CAN_ESR2_LPTM_SHIFT (16U) |
#define | CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) |
CRCR - CRC register | |
#define | CAN_CRCR_TXCRC_MASK (0x7FFFU) |
#define | CAN_CRCR_TXCRC_SHIFT (0U) |
#define | CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) |
#define | CAN_CRCR_MBCRC_MASK (0x7F0000U) |
#define | CAN_CRCR_MBCRC_SHIFT (16U) |
#define | CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) |
RXFGMASK - Rx FIFO Global Mask register | |
#define | CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) |
#define | CAN_RXFGMASK_FGM_SHIFT (0U) |
#define | CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) |
RXFIR - Rx FIFO Information register | |
#define | CAN_RXFIR_IDHIT_MASK (0x1FFU) |
#define | CAN_RXFIR_IDHIT_SHIFT (0U) |
#define | CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) |
CBT - CAN Bit Timing register | |
#define | CAN_CBT_EPSEG2_MASK (0x1FU) |
#define | CAN_CBT_EPSEG2_SHIFT (0U) |
#define | CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) |
#define | CAN_CBT_EPSEG1_MASK (0x3E0U) |
#define | CAN_CBT_EPSEG1_SHIFT (5U) |
#define | CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) |
#define | CAN_CBT_EPROPSEG_MASK (0xFC00U) |
#define | CAN_CBT_EPROPSEG_SHIFT (10U) |
#define | CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) |
#define | CAN_CBT_ERJW_MASK (0x1F0000U) |
#define | CAN_CBT_ERJW_SHIFT (16U) |
#define | CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) |
#define | CAN_CBT_EPRESDIV_MASK (0x7FE00000U) |
#define | CAN_CBT_EPRESDIV_SHIFT (21U) |
#define | CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) |
#define | CAN_CBT_BTF_MASK (0x80000000U) |
#define | CAN_CBT_BTF_SHIFT (31U) |
#define | CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) |
CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register | |
#define | CAN_CS_TIME_STAMP_MASK (0xFFFFU) |
#define | CAN_CS_TIME_STAMP_SHIFT (0U) |
#define | CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) |
#define | CAN_CS_DLC_MASK (0xF0000U) |
#define | CAN_CS_DLC_SHIFT (16U) |
#define | CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) |
#define | CAN_CS_RTR_MASK (0x100000U) |
#define | CAN_CS_RTR_SHIFT (20U) |
#define | CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) |
#define | CAN_CS_IDE_MASK (0x200000U) |
#define | CAN_CS_IDE_SHIFT (21U) |
#define | CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) |
#define | CAN_CS_SRR_MASK (0x400000U) |
#define | CAN_CS_SRR_SHIFT (22U) |
#define | CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) |
#define | CAN_CS_CODE_MASK (0xF000000U) |
#define | CAN_CS_CODE_SHIFT (24U) |
#define | CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) |
#define | CAN_CS_ESI_MASK (0x20000000U) |
#define | CAN_CS_ESI_SHIFT (29U) |
#define | CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) |
#define | CAN_CS_BRS_MASK (0x40000000U) |
#define | CAN_CS_BRS_SHIFT (30U) |
#define | CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) |
#define | CAN_CS_EDL_MASK (0x80000000U) |
#define | CAN_CS_EDL_SHIFT (31U) |
#define | CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) |
#define | CAN_CS_TIME_STAMP_MASK (0xFFFFU) |
#define | CAN_CS_TIME_STAMP_SHIFT (0U) |
#define | CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) |
#define | CAN_CS_DLC_MASK (0xF0000U) |
#define | CAN_CS_DLC_SHIFT (16U) |
#define | CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) |
#define | CAN_CS_RTR_MASK (0x100000U) |
#define | CAN_CS_RTR_SHIFT (20U) |
#define | CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) |
#define | CAN_CS_IDE_MASK (0x200000U) |
#define | CAN_CS_IDE_SHIFT (21U) |
#define | CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) |
#define | CAN_CS_SRR_MASK (0x400000U) |
#define | CAN_CS_SRR_SHIFT (22U) |
#define | CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) |
#define | CAN_CS_CODE_MASK (0xF000000U) |
#define | CAN_CS_CODE_SHIFT (24U) |
#define | CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) |
#define | CAN_CS_ESI_MASK (0x20000000U) |
#define | CAN_CS_ESI_SHIFT (29U) |
#define | CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) |
#define | CAN_CS_BRS_MASK (0x40000000U) |
#define | CAN_CS_BRS_SHIFT (30U) |
#define | CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) |
#define | CAN_CS_EDL_MASK (0x80000000U) |
#define | CAN_CS_EDL_SHIFT (31U) |
#define | CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) |
ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register | |
#define | CAN_ID_EXT_MASK (0x3FFFFU) |
#define | CAN_ID_EXT_SHIFT (0U) |
#define | CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) |
#define | CAN_ID_STD_MASK (0x1FFC0000U) |
#define | CAN_ID_STD_SHIFT (18U) |
#define | CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) |
#define | CAN_ID_PRIO_MASK (0xE0000000U) |
#define | CAN_ID_PRIO_SHIFT (29U) |
#define | CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) |
#define | CAN_ID_EXT_MASK (0x3FFFFU) |
#define | CAN_ID_EXT_SHIFT (0U) |
#define | CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) |
#define | CAN_ID_STD_MASK (0x1FFC0000U) |
#define | CAN_ID_STD_SHIFT (18U) |
#define | CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) |
#define | CAN_ID_PRIO_MASK (0xE0000000U) |
#define | CAN_ID_PRIO_SHIFT (29U) |
#define | CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) |
WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register | |
#define | CAN_WORD_DATA_BYTE_3_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_3_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) |
#define | CAN_WORD_DATA_BYTE_7_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_7_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) |
#define | CAN_WORD_DATA_BYTE_11_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_11_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) |
#define | CAN_WORD_DATA_BYTE_15_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_15_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) |
#define | CAN_WORD_DATA_BYTE_19_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_19_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) |
#define | CAN_WORD_DATA_BYTE_23_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_23_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) |
#define | CAN_WORD_DATA_BYTE_27_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_27_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) |
#define | CAN_WORD_DATA_BYTE_31_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_31_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) |
#define | CAN_WORD_DATA_BYTE_35_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_35_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) |
#define | CAN_WORD_DATA_BYTE_39_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_39_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) |
#define | CAN_WORD_DATA_BYTE_43_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_43_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) |
#define | CAN_WORD_DATA_BYTE_47_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_47_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) |
#define | CAN_WORD_DATA_BYTE_51_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_51_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) |
#define | CAN_WORD_DATA_BYTE_55_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_55_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) |
#define | CAN_WORD_DATA_BYTE_59_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_59_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) |
#define | CAN_WORD_DATA_BYTE_63_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_63_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) |
#define | CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_2_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) |
#define | CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_6_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) |
#define | CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_10_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) |
#define | CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_14_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) |
#define | CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_18_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) |
#define | CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_22_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) |
#define | CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_26_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) |
#define | CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_30_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) |
#define | CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_34_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) |
#define | CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_38_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) |
#define | CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_42_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) |
#define | CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_46_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) |
#define | CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_50_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) |
#define | CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_54_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) |
#define | CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_58_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) |
#define | CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_62_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) |
#define | CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_1_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) |
#define | CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_5_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) |
#define | CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_9_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) |
#define | CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_13_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) |
#define | CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_17_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) |
#define | CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_21_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) |
#define | CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_25_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) |
#define | CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_29_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) |
#define | CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_33_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) |
#define | CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_37_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) |
#define | CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_41_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) |
#define | CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_45_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) |
#define | CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_49_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) |
#define | CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_53_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) |
#define | CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_57_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) |
#define | CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_61_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) |
#define | CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_0_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) |
#define | CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_4_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) |
#define | CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_8_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) |
#define | CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_12_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) |
#define | CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_16_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) |
#define | CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_20_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) |
#define | CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_24_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) |
#define | CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_28_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) |
#define | CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_32_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) |
#define | CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_36_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) |
#define | CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_40_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) |
#define | CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_44_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) |
#define | CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_48_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) |
#define | CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_52_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) |
#define | CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_56_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) |
#define | CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_60_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) |
#define | CAN_WORD_DATA_BYTE_3_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_3_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) |
#define | CAN_WORD_DATA_BYTE_7_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_7_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) |
#define | CAN_WORD_DATA_BYTE_11_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_11_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) |
#define | CAN_WORD_DATA_BYTE_15_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_15_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) |
#define | CAN_WORD_DATA_BYTE_19_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_19_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) |
#define | CAN_WORD_DATA_BYTE_23_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_23_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) |
#define | CAN_WORD_DATA_BYTE_27_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_27_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) |
#define | CAN_WORD_DATA_BYTE_31_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_31_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) |
#define | CAN_WORD_DATA_BYTE_35_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_35_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) |
#define | CAN_WORD_DATA_BYTE_39_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_39_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) |
#define | CAN_WORD_DATA_BYTE_43_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_43_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) |
#define | CAN_WORD_DATA_BYTE_47_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_47_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) |
#define | CAN_WORD_DATA_BYTE_51_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_51_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) |
#define | CAN_WORD_DATA_BYTE_55_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_55_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) |
#define | CAN_WORD_DATA_BYTE_59_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_59_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) |
#define | CAN_WORD_DATA_BYTE_63_MASK (0xFFU) |
#define | CAN_WORD_DATA_BYTE_63_SHIFT (0U) |
#define | CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) |
#define | CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_2_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) |
#define | CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_6_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) |
#define | CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_10_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) |
#define | CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_14_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) |
#define | CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_18_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) |
#define | CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_22_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) |
#define | CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_26_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) |
#define | CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_30_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) |
#define | CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_34_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) |
#define | CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_38_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) |
#define | CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_42_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) |
#define | CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_46_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) |
#define | CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_50_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) |
#define | CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_54_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) |
#define | CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_58_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) |
#define | CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) |
#define | CAN_WORD_DATA_BYTE_62_SHIFT (8U) |
#define | CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) |
#define | CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_1_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) |
#define | CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_5_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) |
#define | CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_9_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) |
#define | CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_13_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) |
#define | CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_17_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) |
#define | CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_21_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) |
#define | CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_25_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) |
#define | CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_29_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) |
#define | CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_33_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) |
#define | CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_37_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) |
#define | CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_41_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) |
#define | CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_45_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) |
#define | CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_49_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) |
#define | CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_53_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) |
#define | CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_57_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) |
#define | CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) |
#define | CAN_WORD_DATA_BYTE_61_SHIFT (16U) |
#define | CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) |
#define | CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_0_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) |
#define | CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_4_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) |
#define | CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_8_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) |
#define | CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_12_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) |
#define | CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_16_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) |
#define | CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_20_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) |
#define | CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_24_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) |
#define | CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_28_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) |
#define | CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_32_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) |
#define | CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_36_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) |
#define | CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_40_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) |
#define | CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_44_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) |
#define | CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_48_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) |
#define | CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_52_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) |
#define | CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_56_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) |
#define | CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) |
#define | CAN_WORD_DATA_BYTE_60_SHIFT (24U) |
#define | CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) |
WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register | |
#define | CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) |
#define | CAN_WORD0_DATA_BYTE_3_SHIFT (0U) |
#define | CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) |
#define | CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) |
#define | CAN_WORD0_DATA_BYTE_2_SHIFT (8U) |
#define | CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) |
#define | CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) |
#define | CAN_WORD0_DATA_BYTE_1_SHIFT (16U) |
#define | CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) |
#define | CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) |
#define | CAN_WORD0_DATA_BYTE_0_SHIFT (24U) |
#define | CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) |
WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register | |
#define | CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) |
#define | CAN_WORD1_DATA_BYTE_7_SHIFT (0U) |
#define | CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) |
#define | CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) |
#define | CAN_WORD1_DATA_BYTE_6_SHIFT (8U) |
#define | CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) |
#define | CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) |
#define | CAN_WORD1_DATA_BYTE_5_SHIFT (16U) |
#define | CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) |
#define | CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) |
#define | CAN_WORD1_DATA_BYTE_4_SHIFT (24U) |
#define | CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) |
RXIMR - Rx Individual Mask registers | |
#define | CAN_RXIMR_MI_MASK (0xFFFFFFFFU) |
#define | CAN_RXIMR_MI_SHIFT (0U) |
#define | CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) |
MECR - Memory Error Control register | |
#define | CAN_MECR_NCEFAFRZ_MASK (0x80U) |
#define | CAN_MECR_NCEFAFRZ_SHIFT (7U) |
#define | CAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK) |
#define | CAN_MECR_ECCDIS_MASK (0x100U) |
#define | CAN_MECR_ECCDIS_SHIFT (8U) |
#define | CAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK) |
#define | CAN_MECR_RERRDIS_MASK (0x200U) |
#define | CAN_MECR_RERRDIS_SHIFT (9U) |
#define | CAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK) |
#define | CAN_MECR_EXTERRIE_MASK (0x2000U) |
#define | CAN_MECR_EXTERRIE_SHIFT (13U) |
#define | CAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK) |
#define | CAN_MECR_FAERRIE_MASK (0x4000U) |
#define | CAN_MECR_FAERRIE_SHIFT (14U) |
#define | CAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK) |
#define | CAN_MECR_HAERRIE_MASK (0x8000U) |
#define | CAN_MECR_HAERRIE_SHIFT (15U) |
#define | CAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK) |
#define | CAN_MECR_CEI_MSK_MASK (0x10000U) |
#define | CAN_MECR_CEI_MSK_SHIFT (16U) |
#define | CAN_MECR_CEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK) |
#define | CAN_MECR_FANCEI_MSK_MASK (0x40000U) |
#define | CAN_MECR_FANCEI_MSK_SHIFT (18U) |
#define | CAN_MECR_FANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK) |
#define | CAN_MECR_HANCEI_MSK_MASK (0x80000U) |
#define | CAN_MECR_HANCEI_MSK_SHIFT (19U) |
#define | CAN_MECR_HANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK) |
#define | CAN_MECR_ECRWRDIS_MASK (0x80000000U) |
#define | CAN_MECR_ECRWRDIS_SHIFT (31U) |
#define | CAN_MECR_ECRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK) |
ERRIAR - Error Injection Address register | |
#define | CAN_ERRIAR_INJADDR_L_MASK (0x3U) |
#define | CAN_ERRIAR_INJADDR_L_SHIFT (0U) |
#define | CAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK) |
#define | CAN_ERRIAR_INJADDR_H_MASK (0x3FFCU) |
#define | CAN_ERRIAR_INJADDR_H_SHIFT (2U) |
#define | CAN_ERRIAR_INJADDR_H(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK) |
ERRIDPR - Error Injection Data Pattern register | |
#define | CAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU) |
#define | CAN_ERRIDPR_DFLIP_SHIFT (0U) |
#define | CAN_ERRIDPR_DFLIP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK) |
ERRIPPR - Error Injection Parity Pattern register | |
#define | CAN_ERRIPPR_PFLIP0_MASK (0x1FU) |
#define | CAN_ERRIPPR_PFLIP0_SHIFT (0U) |
#define | CAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK) |
#define | CAN_ERRIPPR_PFLIP1_MASK (0x1F00U) |
#define | CAN_ERRIPPR_PFLIP1_SHIFT (8U) |
#define | CAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK) |
#define | CAN_ERRIPPR_PFLIP2_MASK (0x1F0000U) |
#define | CAN_ERRIPPR_PFLIP2_SHIFT (16U) |
#define | CAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK) |
#define | CAN_ERRIPPR_PFLIP3_MASK (0x1F000000U) |
#define | CAN_ERRIPPR_PFLIP3_SHIFT (24U) |
#define | CAN_ERRIPPR_PFLIP3(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK) |
RERRAR - Error Report Address register | |
#define | CAN_RERRAR_ERRADDR_MASK (0x3FFFU) |
#define | CAN_RERRAR_ERRADDR_SHIFT (0U) |
#define | CAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK) |
#define | CAN_RERRAR_SAID_MASK (0x70000U) |
#define | CAN_RERRAR_SAID_SHIFT (16U) |
#define | CAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK) |
#define | CAN_RERRAR_NCE_MASK (0x1000000U) |
#define | CAN_RERRAR_NCE_SHIFT (24U) |
#define | CAN_RERRAR_NCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK) |
RERRDR - Error Report Data register | |
#define | CAN_RERRDR_RDATA_MASK (0xFFFFFFFFU) |
#define | CAN_RERRDR_RDATA_SHIFT (0U) |
#define | CAN_RERRDR_RDATA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK) |
RERRSYNR - Error Report Syndrome register | |
#define | CAN_RERRSYNR_SYND0_MASK (0x1FU) |
#define | CAN_RERRSYNR_SYND0_SHIFT (0U) |
#define | CAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK) |
#define | CAN_RERRSYNR_BE0_MASK (0x80U) |
#define | CAN_RERRSYNR_BE0_SHIFT (7U) |
#define | CAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK) |
#define | CAN_RERRSYNR_SYND1_MASK (0x1F00U) |
#define | CAN_RERRSYNR_SYND1_SHIFT (8U) |
#define | CAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK) |
#define | CAN_RERRSYNR_BE1_MASK (0x8000U) |
#define | CAN_RERRSYNR_BE1_SHIFT (15U) |
#define | CAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK) |
#define | CAN_RERRSYNR_SYND2_MASK (0x1F0000U) |
#define | CAN_RERRSYNR_SYND2_SHIFT (16U) |
#define | CAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK) |
#define | CAN_RERRSYNR_BE2_MASK (0x800000U) |
#define | CAN_RERRSYNR_BE2_SHIFT (23U) |
#define | CAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK) |
#define | CAN_RERRSYNR_SYND3_MASK (0x1F000000U) |
#define | CAN_RERRSYNR_SYND3_SHIFT (24U) |
#define | CAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK) |
#define | CAN_RERRSYNR_BE3_MASK (0x80000000U) |
#define | CAN_RERRSYNR_BE3_SHIFT (31U) |
#define | CAN_RERRSYNR_BE3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK) |
ERRSR - Error Status register | |
#define | CAN_ERRSR_CEIOF_MASK (0x1U) |
#define | CAN_ERRSR_CEIOF_SHIFT (0U) |
#define | CAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK) |
#define | CAN_ERRSR_FANCEIOF_MASK (0x4U) |
#define | CAN_ERRSR_FANCEIOF_SHIFT (2U) |
#define | CAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK) |
#define | CAN_ERRSR_HANCEIOF_MASK (0x8U) |
#define | CAN_ERRSR_HANCEIOF_SHIFT (3U) |
#define | CAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK) |
#define | CAN_ERRSR_CEIF_MASK (0x10000U) |
#define | CAN_ERRSR_CEIF_SHIFT (16U) |
#define | CAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK) |
#define | CAN_ERRSR_FANCEIF_MASK (0x40000U) |
#define | CAN_ERRSR_FANCEIF_SHIFT (18U) |
#define | CAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK) |
#define | CAN_ERRSR_HANCEIF_MASK (0x80000U) |
#define | CAN_ERRSR_HANCEIF_SHIFT (19U) |
#define | CAN_ERRSR_HANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK) |
FDCTRL - CAN FD Control register | |
#define | CAN_FDCTRL_TDCVAL_MASK (0x3FU) |
#define | CAN_FDCTRL_TDCVAL_SHIFT (0U) |
#define | CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) |
#define | CAN_FDCTRL_TDCOFF_MASK (0x1F00U) |
#define | CAN_FDCTRL_TDCOFF_SHIFT (8U) |
#define | CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) |
#define | CAN_FDCTRL_TDCFAIL_MASK (0x4000U) |
#define | CAN_FDCTRL_TDCFAIL_SHIFT (14U) |
#define | CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) |
#define | CAN_FDCTRL_TDCEN_MASK (0x8000U) |
#define | CAN_FDCTRL_TDCEN_SHIFT (15U) |
#define | CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) |
#define | CAN_FDCTRL_MBDSR0_MASK (0x30000U) |
#define | CAN_FDCTRL_MBDSR0_SHIFT (16U) |
#define | CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) |
#define | CAN_FDCTRL_MBDSR1_MASK (0x180000U) |
#define | CAN_FDCTRL_MBDSR1_SHIFT (19U) |
#define | CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK) |
#define | CAN_FDCTRL_FDRATE_MASK (0x80000000U) |
#define | CAN_FDCTRL_FDRATE_SHIFT (31U) |
#define | CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) |
FDCBT - CAN FD Bit Timing register | |
#define | CAN_FDCBT_FPSEG2_MASK (0x7U) |
#define | CAN_FDCBT_FPSEG2_SHIFT (0U) |
#define | CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) |
#define | CAN_FDCBT_FPSEG1_MASK (0xE0U) |
#define | CAN_FDCBT_FPSEG1_SHIFT (5U) |
#define | CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) |
#define | CAN_FDCBT_FPROPSEG_MASK (0x7C00U) |
#define | CAN_FDCBT_FPROPSEG_SHIFT (10U) |
#define | CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) |
#define | CAN_FDCBT_FRJW_MASK (0x70000U) |
#define | CAN_FDCBT_FRJW_SHIFT (16U) |
#define | CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) |
#define | CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) |
#define | CAN_FDCBT_FPRESDIV_SHIFT (20U) |
#define | CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) |
FDCRC - CAN FD CRC register | |
#define | CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) |
#define | CAN_FDCRC_FD_TXCRC_SHIFT (0U) |
#define | CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) |
#define | CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) |
#define | CAN_FDCRC_FD_MBCRC_SHIFT (24U) |
#define | CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) |
GFWR - Glitch Filter Width Register | |
#define | CAN_WRAPPER_GFWR_GFWR_MASK (0xFFU) |
#define | CAN_WRAPPER_GFWR_GFWR_SHIFT (0U) |
#define | CAN_WRAPPER_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WRAPPER_GFWR_GFWR_SHIFT)) & CAN_WRAPPER_GFWR_GFWR_MASK) |
CLOCK_ROOT_CONTROL - Clock root control | |
#define | CCM_CLOCK_ROOT_CONTROL_DIV_MASK (0xFFU) |
#define | CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT (0U) |
#define | CCM_CLOCK_ROOT_CONTROL_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) |
#define | CCM_CLOCK_ROOT_CONTROL_MUX_MASK (0x700U) |
#define | CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT (8U) |
#define | CCM_CLOCK_ROOT_CONTROL_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) |
#define | CCM_CLOCK_ROOT_CONTROL_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT (24U) |
#define | CCM_CLOCK_ROOT_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_OFF_MASK) |
CLOCK_ROOT_CONTROL_SET - Clock root control | |
#define | CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK (0xFFU) |
#define | CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT (0U) |
#define | CCM_CLOCK_ROOT_CONTROL_SET_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK) |
#define | CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK (0x700U) |
#define | CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT (8U) |
#define | CCM_CLOCK_ROOT_CONTROL_SET_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK) |
#define | CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT (24U) |
#define | CCM_CLOCK_ROOT_CONTROL_SET_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK) |
CLOCK_ROOT_CONTROL_CLR - Clock root control | |
#define | CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK (0xFFU) |
#define | CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT (0U) |
#define | CCM_CLOCK_ROOT_CONTROL_CLR_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK) |
#define | CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK (0x700U) |
#define | CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT (8U) |
#define | CCM_CLOCK_ROOT_CONTROL_CLR_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK) |
#define | CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT (24U) |
#define | CCM_CLOCK_ROOT_CONTROL_CLR_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK) |
CLOCK_ROOT_CONTROL_TOG - Clock root control | |
#define | CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK (0xFFU) |
#define | CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT (0U) |
#define | CCM_CLOCK_ROOT_CONTROL_TOG_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK) |
#define | CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK (0x700U) |
#define | CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT (8U) |
#define | CCM_CLOCK_ROOT_CONTROL_TOG_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK) |
#define | CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT (24U) |
#define | CCM_CLOCK_ROOT_CONTROL_TOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK) |
CLOCK_ROOT_STATUS0 - Clock root working status | |
#define | CCM_CLOCK_ROOT_STATUS0_DIV_MASK (0xFFU) |
#define | CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT (0U) |
#define | CCM_CLOCK_ROOT_STATUS0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_DIV_MASK) |
#define | CCM_CLOCK_ROOT_STATUS0_MUX_MASK (0x700U) |
#define | CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT (8U) |
#define | CCM_CLOCK_ROOT_STATUS0_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MUX_MASK) |
#define | CCM_CLOCK_ROOT_STATUS0_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT (24U) |
#define | CCM_CLOCK_ROOT_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_OFF_MASK) |
#define | CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK (0x8000000U) |
#define | CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT (27U) |
#define | CCM_CLOCK_ROOT_STATUS0_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK) |
#define | CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK (0x10000000U) |
#define | CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT (28U) |
#define | CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK) |
#define | CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK (0x20000000U) |
#define | CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT (29U) |
#define | CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK) |
#define | CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK (0x40000000U) |
#define | CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT (30U) |
#define | CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK) |
#define | CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK (0x80000000U) |
#define | CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT (31U) |
#define | CCM_CLOCK_ROOT_STATUS0_CHANGING(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK) |
CLOCK_ROOT_STATUS1 - Clock root low power status | |
#define | CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK (0xF0000U) |
#define | CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT (16U) |
#define | CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK) |
#define | CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U) |
#define | CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT (20U) |
#define | CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK) |
#define | CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK (0x1000000U) |
#define | CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT (24U) |
#define | CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK) |
#define | CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK (0x2000000U) |
#define | CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT (25U) |
#define | CCM_CLOCK_ROOT_STATUS1_DOWN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK) |
#define | CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK (0x4000000U) |
#define | CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT (26U) |
#define | CCM_CLOCK_ROOT_STATUS1_UP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK) |
#define | CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK (0x8000000U) |
#define | CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT (27U) |
#define | CCM_CLOCK_ROOT_STATUS1_UP_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK) |
CLOCK_ROOT_CONFIG - Clock root configuration | |
#define | CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK (0x10U) |
#define | CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT (4U) |
#define | CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK) |
CLOCK_ROOT_AUTHEN - Clock root access control | |
#define | CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK (0x20000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT (17U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK) |
CLOCK_ROOT_AUTHEN_SET - Clock root access control | |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK (0x1U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT (0U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK (0x2U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT (1U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK (0x10U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT (4U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT (8U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT (12U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT (20U) |
#define | CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK) |
CLOCK_ROOT_AUTHEN_CLR - Clock root access control | |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK (0x1U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT (0U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK (0x2U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT (1U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) |
#define | CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK) |
CLOCK_ROOT_AUTHEN_TOG - Clock root access control | |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK (0x1U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT (0U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK (0x2U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT (1U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) |
#define | CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK) |
CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT - Setpoint setting | |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK (0xFFU) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT (0U) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK (0x700U) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT (8U) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT (24U) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT (28U) |
#define | CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK) |
CLOCK_GROUP_CONTROL - Clock group control | |
#define | CCM_CLOCK_GROUP_CONTROL_DIV0_MASK (0xFU) |
#define | CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT (0U) |
#define | CCM_CLOCK_GROUP_CONTROL_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_DIV0_MASK) |
#define | CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK (0xFF0000U) |
#define | CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT (16U) |
#define | CCM_CLOCK_GROUP_CONTROL_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK) |
#define | CCM_CLOCK_GROUP_CONTROL_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT (24U) |
#define | CCM_CLOCK_GROUP_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_OFF_MASK) |
CLOCK_GROUP_CONTROL_SET - Clock group control | |
#define | CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK (0xFU) |
#define | CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT (0U) |
#define | CCM_CLOCK_GROUP_CONTROL_SET_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK) |
#define | CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK (0xFF0000U) |
#define | CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT (16U) |
#define | CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK) |
#define | CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT (24U) |
#define | CCM_CLOCK_GROUP_CONTROL_SET_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK) |
CLOCK_GROUP_CONTROL_CLR - Clock group control | |
#define | CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK (0xFU) |
#define | CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT (0U) |
#define | CCM_CLOCK_GROUP_CONTROL_CLR_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK) |
#define | CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK (0xFF0000U) |
#define | CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT (16U) |
#define | CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK) |
#define | CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT (24U) |
#define | CCM_CLOCK_GROUP_CONTROL_CLR_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK) |
CLOCK_GROUP_CONTROL_TOG - Clock group control | |
#define | CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK (0xFU) |
#define | CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT (0U) |
#define | CCM_CLOCK_GROUP_CONTROL_TOG_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK) |
#define | CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK (0xFF0000U) |
#define | CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT (16U) |
#define | CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK) |
#define | CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT (24U) |
#define | CCM_CLOCK_GROUP_CONTROL_TOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK) |
CLOCK_GROUP_STATUS0 - Clock group working status | |
#define | CCM_CLOCK_GROUP_STATUS0_DIV0_MASK (0xFU) |
#define | CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT (0U) |
#define | CCM_CLOCK_GROUP_STATUS0_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_DIV0_MASK) |
#define | CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK (0xFF0000U) |
#define | CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT (16U) |
#define | CCM_CLOCK_GROUP_STATUS0_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK) |
#define | CCM_CLOCK_GROUP_STATUS0_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT (24U) |
#define | CCM_CLOCK_GROUP_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_OFF_MASK) |
#define | CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK (0x8000000U) |
#define | CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT (27U) |
#define | CCM_CLOCK_GROUP_STATUS0_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK) |
#define | CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK (0x10000000U) |
#define | CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT (28U) |
#define | CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK) |
#define | CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK (0x20000000U) |
#define | CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT (29U) |
#define | CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK) |
#define | CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK (0x40000000U) |
#define | CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT (30U) |
#define | CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK) |
#define | CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK (0x80000000U) |
#define | CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT (31U) |
#define | CCM_CLOCK_GROUP_STATUS0_CHANGING(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK) |
CLOCK_GROUP_STATUS1 - Clock group low power/extend status | |
#define | CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK (0xF0000U) |
#define | CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT (16U) |
#define | CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK) |
#define | CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U) |
#define | CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT (20U) |
#define | CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK) |
#define | CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK (0x1000000U) |
#define | CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT (24U) |
#define | CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK) |
#define | CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK (0x2000000U) |
#define | CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT (25U) |
#define | CCM_CLOCK_GROUP_STATUS1_DOWN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK) |
#define | CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK (0x4000000U) |
#define | CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT (26U) |
#define | CCM_CLOCK_GROUP_STATUS1_UP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK) |
#define | CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK (0x8000000U) |
#define | CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT (27U) |
#define | CCM_CLOCK_GROUP_STATUS1_UP_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK) |
CLOCK_GROUP_CONFIG - Clock group configuration | |
#define | CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK (0x10U) |
#define | CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT (4U) |
#define | CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK) |
CLOCK_GROUP_AUTHEN - Clock group access control | |
#define | CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK (0x20000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT (17U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK) |
CLOCK_GROUP_AUTHEN_SET - Clock group access control | |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK (0x1U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT (0U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK (0x2U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT (1U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK (0x10U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT (4U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT (8U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT (12U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT (20U) |
#define | CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK) |
CLOCK_GROUP_AUTHEN_CLR - Clock group access control | |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK (0x1U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT (0U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK (0x2U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT (1U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) |
#define | CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK) |
CLOCK_GROUP_AUTHEN_TOG - Clock group access control | |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK (0x1U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT (0U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK (0x2U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT (1U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) |
#define | CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK) |
CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT - Setpoint setting | |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK (0xFU) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT (0U) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK (0xFF0000U) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT (16U) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK (0x1000000U) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT (24U) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT (28U) |
#define | CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK) |
GPR_SHARED - General Purpose Register | |
#define | CCM_GPR_SHARED_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_SHARED_GPR_SHIFT (0U) |
#define | CCM_GPR_SHARED_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_GPR_SHIFT)) & CCM_GPR_SHARED_GPR_MASK) |
GPR_SHARED_SET - General Purpose Register | |
#define | CCM_GPR_SHARED_SET_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_SHARED_SET_GPR_SHIFT (0U) |
#define | CCM_GPR_SHARED_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_SET_GPR_SHIFT)) & CCM_GPR_SHARED_SET_GPR_MASK) |
GPR_SHARED_CLR - General Purpose Register | |
#define | CCM_GPR_SHARED_CLR_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_SHARED_CLR_GPR_SHIFT (0U) |
#define | CCM_GPR_SHARED_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_CLR_GPR_SHIFT)) & CCM_GPR_SHARED_CLR_GPR_MASK) |
GPR_SHARED_TOG - General Purpose Register | |
#define | CCM_GPR_SHARED_TOG_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_SHARED_TOG_GPR_SHIFT (0U) |
#define | CCM_GPR_SHARED_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TOG_GPR_SHIFT)) & CCM_GPR_SHARED_TOG_GPR_MASK) |
GPR_SHARED_AUTHEN - GPR access control | |
#define | CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_SHARED_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_SHARED_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_SHARED_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_SHARED_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_SHARED_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_SHARED_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK) |
GPR_SHARED_AUTHEN_SET - GPR access control | |
#define | CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK) |
GPR_SHARED_AUTHEN_CLR - GPR access control | |
#define | CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK) |
GPR_SHARED_AUTHEN_TOG - GPR access control | |
#define | CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK) |
GPR_PRIVATE1 - General Purpose Register | |
#define | CCM_GPR_PRIVATE1_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE1_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE1_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_GPR_SHIFT)) & CCM_GPR_PRIVATE1_GPR_MASK) |
GPR_PRIVATE1_SET - General Purpose Register | |
#define | CCM_GPR_PRIVATE1_SET_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE1_SET_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE1_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE1_SET_GPR_MASK) |
GPR_PRIVATE1_CLR - General Purpose Register | |
#define | CCM_GPR_PRIVATE1_CLR_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE1_CLR_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE1_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE1_CLR_GPR_MASK) |
GPR_PRIVATE1_TOG - General Purpose Register | |
#define | CCM_GPR_PRIVATE1_TOG_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE1_TOG_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE1_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE1_TOG_GPR_MASK) |
GPR_PRIVATE1_AUTHEN - GPR access control | |
#define | CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK) |
GPR_PRIVATE1_AUTHEN_SET - GPR access control | |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK) |
GPR_PRIVATE1_AUTHEN_CLR - GPR access control | |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK) |
GPR_PRIVATE1_AUTHEN_TOG - GPR access control | |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK) |
GPR_PRIVATE2 - General Purpose Register | |
#define | CCM_GPR_PRIVATE2_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE2_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE2_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_GPR_SHIFT)) & CCM_GPR_PRIVATE2_GPR_MASK) |
GPR_PRIVATE2_SET - General Purpose Register | |
#define | CCM_GPR_PRIVATE2_SET_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE2_SET_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE2_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE2_SET_GPR_MASK) |
GPR_PRIVATE2_CLR - General Purpose Register | |
#define | CCM_GPR_PRIVATE2_CLR_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE2_CLR_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE2_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE2_CLR_GPR_MASK) |
GPR_PRIVATE2_TOG - General Purpose Register | |
#define | CCM_GPR_PRIVATE2_TOG_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE2_TOG_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE2_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE2_TOG_GPR_MASK) |
GPR_PRIVATE2_AUTHEN - GPR access control | |
#define | CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK) |
GPR_PRIVATE2_AUTHEN_SET - GPR access control | |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK) |
GPR_PRIVATE2_AUTHEN_CLR - GPR access control | |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK) |
GPR_PRIVATE2_AUTHEN_TOG - GPR access control | |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK) |
GPR_PRIVATE3 - General Purpose Register | |
#define | CCM_GPR_PRIVATE3_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE3_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE3_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_GPR_SHIFT)) & CCM_GPR_PRIVATE3_GPR_MASK) |
GPR_PRIVATE3_SET - General Purpose Register | |
#define | CCM_GPR_PRIVATE3_SET_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE3_SET_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE3_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE3_SET_GPR_MASK) |
GPR_PRIVATE3_CLR - General Purpose Register | |
#define | CCM_GPR_PRIVATE3_CLR_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE3_CLR_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE3_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE3_CLR_GPR_MASK) |
GPR_PRIVATE3_TOG - General Purpose Register | |
#define | CCM_GPR_PRIVATE3_TOG_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE3_TOG_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE3_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE3_TOG_GPR_MASK) |
GPR_PRIVATE3_AUTHEN - GPR access control | |
#define | CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK) |
GPR_PRIVATE3_AUTHEN_SET - GPR access control | |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK) |
GPR_PRIVATE3_AUTHEN_CLR - GPR access control | |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK) |
GPR_PRIVATE3_AUTHEN_TOG - GPR access control | |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK) |
GPR_PRIVATE4 - General Purpose Register | |
#define | CCM_GPR_PRIVATE4_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE4_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE4_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_GPR_SHIFT)) & CCM_GPR_PRIVATE4_GPR_MASK) |
GPR_PRIVATE4_SET - General Purpose Register | |
#define | CCM_GPR_PRIVATE4_SET_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE4_SET_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE4_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE4_SET_GPR_MASK) |
GPR_PRIVATE4_CLR - General Purpose Register | |
#define | CCM_GPR_PRIVATE4_CLR_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE4_CLR_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE4_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE4_CLR_GPR_MASK) |
GPR_PRIVATE4_TOG - General Purpose Register | |
#define | CCM_GPR_PRIVATE4_TOG_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE4_TOG_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE4_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE4_TOG_GPR_MASK) |
GPR_PRIVATE4_AUTHEN - GPR access control | |
#define | CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK) |
GPR_PRIVATE4_AUTHEN_SET - GPR access control | |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK) |
GPR_PRIVATE4_AUTHEN_CLR - GPR access control | |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK) |
GPR_PRIVATE4_AUTHEN_TOG - GPR access control | |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK) |
GPR_PRIVATE5 - General Purpose Register | |
#define | CCM_GPR_PRIVATE5_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE5_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE5_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_GPR_SHIFT)) & CCM_GPR_PRIVATE5_GPR_MASK) |
GPR_PRIVATE5_SET - General Purpose Register | |
#define | CCM_GPR_PRIVATE5_SET_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE5_SET_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE5_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE5_SET_GPR_MASK) |
GPR_PRIVATE5_CLR - General Purpose Register | |
#define | CCM_GPR_PRIVATE5_CLR_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE5_CLR_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE5_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE5_CLR_GPR_MASK) |
GPR_PRIVATE5_TOG - General Purpose Register | |
#define | CCM_GPR_PRIVATE5_TOG_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE5_TOG_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE5_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE5_TOG_GPR_MASK) |
GPR_PRIVATE5_AUTHEN - GPR access control | |
#define | CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK) |
GPR_PRIVATE5_AUTHEN_SET - GPR access control | |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK) |
GPR_PRIVATE5_AUTHEN_CLR - GPR access control | |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK) |
GPR_PRIVATE5_AUTHEN_TOG - GPR access control | |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK) |
GPR_PRIVATE6 - General Purpose Register | |
#define | CCM_GPR_PRIVATE6_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE6_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE6_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_GPR_SHIFT)) & CCM_GPR_PRIVATE6_GPR_MASK) |
GPR_PRIVATE6_SET - General Purpose Register | |
#define | CCM_GPR_PRIVATE6_SET_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE6_SET_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE6_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE6_SET_GPR_MASK) |
GPR_PRIVATE6_CLR - General Purpose Register | |
#define | CCM_GPR_PRIVATE6_CLR_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE6_CLR_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE6_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE6_CLR_GPR_MASK) |
GPR_PRIVATE6_TOG - General Purpose Register | |
#define | CCM_GPR_PRIVATE6_TOG_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE6_TOG_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE6_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE6_TOG_GPR_MASK) |
GPR_PRIVATE6_AUTHEN - GPR access control | |
#define | CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK) |
GPR_PRIVATE6_AUTHEN_SET - GPR access control | |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK) |
GPR_PRIVATE6_AUTHEN_CLR - GPR access control | |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK) |
GPR_PRIVATE6_AUTHEN_TOG - GPR access control | |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK) |
GPR_PRIVATE7 - General Purpose Register | |
#define | CCM_GPR_PRIVATE7_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE7_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE7_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_GPR_SHIFT)) & CCM_GPR_PRIVATE7_GPR_MASK) |
GPR_PRIVATE7_SET - General Purpose Register | |
#define | CCM_GPR_PRIVATE7_SET_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE7_SET_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE7_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE7_SET_GPR_MASK) |
GPR_PRIVATE7_CLR - General Purpose Register | |
#define | CCM_GPR_PRIVATE7_CLR_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE7_CLR_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE7_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE7_CLR_GPR_MASK) |
GPR_PRIVATE7_TOG - General Purpose Register | |
#define | CCM_GPR_PRIVATE7_TOG_GPR_MASK (0xFFFFFFFFU) |
#define | CCM_GPR_PRIVATE7_TOG_GPR_SHIFT (0U) |
#define | CCM_GPR_PRIVATE7_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE7_TOG_GPR_MASK) |
GPR_PRIVATE7_AUTHEN - GPR access control | |
#define | CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK) |
GPR_PRIVATE7_AUTHEN_SET - GPR access control | |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK) |
GPR_PRIVATE7_AUTHEN_CLR - GPR access control | |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK) |
GPR_PRIVATE7_AUTHEN_TOG - GPR access control | |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK (0x1U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT (0U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK (0x2U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT (1U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) |
#define | CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK) |
OSCPLL_DIRECT - Clock source direct control | |
#define | CCM_OSCPLL_DIRECT_ON_MASK (0x1U) |
#define | CCM_OSCPLL_DIRECT_ON_SHIFT (0U) |
#define | CCM_OSCPLL_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK) |
OSCPLL_DOMAIN - Clock source domain control | |
#define | CCM_OSCPLL_DOMAIN_LEVEL_MASK (0x7U) |
#define | CCM_OSCPLL_DOMAIN_LEVEL_SHIFT (0U) |
#define | CCM_OSCPLL_DOMAIN_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL_MASK) |
#define | CCM_OSCPLL_DOMAIN_LEVEL0_MASK (0x70000U) |
#define | CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT (16U) |
#define | CCM_OSCPLL_DOMAIN_LEVEL0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL0_MASK) |
#define | CCM_OSCPLL_DOMAIN_LEVEL1_MASK (0x700000U) |
#define | CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT (20U) |
#define | CCM_OSCPLL_DOMAIN_LEVEL1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL1_MASK) |
#define | CCM_OSCPLL_DOMAIN_LEVEL2_MASK (0x7000000U) |
#define | CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT (24U) |
#define | CCM_OSCPLL_DOMAIN_LEVEL2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL2_MASK) |
#define | CCM_OSCPLL_DOMAIN_LEVEL3_MASK (0x70000000U) |
#define | CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT (28U) |
#define | CCM_OSCPLL_DOMAIN_LEVEL3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL3_MASK) |
OSCPLL_SETPOINT - Clock source Setpoint setting | |
#define | CCM_OSCPLL_SETPOINT_SETPOINT_MASK (0xFFFFU) |
#define | CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT (0U) |
#define | CCM_OSCPLL_SETPOINT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT)) & CCM_OSCPLL_SETPOINT_SETPOINT_MASK) |
#define | CCM_OSCPLL_SETPOINT_STANDBY_MASK (0xFFFF0000U) |
#define | CCM_OSCPLL_SETPOINT_STANDBY_SHIFT (16U) |
#define | CCM_OSCPLL_SETPOINT_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_STANDBY_SHIFT)) & CCM_OSCPLL_SETPOINT_STANDBY_MASK) |
OSCPLL_STATUS0 - Clock source working status | |
#define | CCM_OSCPLL_STATUS0_ON_MASK (0x1U) |
#define | CCM_OSCPLL_STATUS0_ON_SHIFT (0U) |
#define | CCM_OSCPLL_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK) |
#define | CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK (0x10U) |
#define | CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT (4U) |
#define | CCM_OSCPLL_STATUS0_STATUS_EARLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK) |
#define | CCM_OSCPLL_STATUS0_STATUS_LATE_MASK (0x20U) |
#define | CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT (5U) |
#define | CCM_OSCPLL_STATUS0_STATUS_LATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK) |
#define | CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK (0xF00U) |
#define | CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT (8U) |
#define | CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK) |
#define | CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK (0xF000U) |
#define | CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT (12U) |
#define | CCM_OSCPLL_STATUS0_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK) |
#define | CCM_OSCPLL_STATUS0_IN_USE_MASK (0x10000000U) |
#define | CCM_OSCPLL_STATUS0_IN_USE_SHIFT (28U) |
#define | CCM_OSCPLL_STATUS0_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK) |
OSCPLL_STATUS1 - Clock source low power status | |
#define | CCM_OSCPLL_STATUS1_CPU0_MODE_MASK (0x3U) |
#define | CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT (0U) |
#define | CCM_OSCPLL_STATUS1_CPU0_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_MASK) |
#define | CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U) |
#define | CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U) |
#define | CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK) |
#define | CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK (0x8U) |
#define | CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT (3U) |
#define | CCM_OSCPLL_STATUS1_CPU0_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK) |
#define | CCM_OSCPLL_STATUS1_CPU1_MODE_MASK (0x30U) |
#define | CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT (4U) |
#define | CCM_OSCPLL_STATUS1_CPU1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_MASK) |
#define | CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U) |
#define | CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U) |
#define | CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK) |
#define | CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK (0x80U) |
#define | CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT (7U) |
#define | CCM_OSCPLL_STATUS1_CPU1_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK) |
#define | CCM_OSCPLL_STATUS1_CPU2_MODE_MASK (0x300U) |
#define | CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT (8U) |
#define | CCM_OSCPLL_STATUS1_CPU2_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_MASK) |
#define | CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U) |
#define | CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U) |
#define | CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK) |
#define | CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK (0x800U) |
#define | CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT (11U) |
#define | CCM_OSCPLL_STATUS1_CPU2_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK) |
#define | CCM_OSCPLL_STATUS1_CPU3_MODE_MASK (0x3000U) |
#define | CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT (12U) |
#define | CCM_OSCPLL_STATUS1_CPU3_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_MASK) |
#define | CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U) |
#define | CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U) |
#define | CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK) |
#define | CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK (0x8000U) |
#define | CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT (15U) |
#define | CCM_OSCPLL_STATUS1_CPU3_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK) |
#define | CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK (0xF0000U) |
#define | CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT (16U) |
#define | CCM_OSCPLL_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK) |
#define | CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U) |
#define | CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT (20U) |
#define | CCM_OSCPLL_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT (27U) |
#define | CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK) |
#define | CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK (0x10000000U) |
#define | CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT (28U) |
#define | CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK) |
#define | CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK (0x20000000U) |
#define | CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT (29U) |
#define | CCM_OSCPLL_STATUS1_STANDBY_IN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK) |
#define | CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK (0x40000000U) |
#define | CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT (30U) |
#define | CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK) |
#define | CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK (0x80000000U) |
#define | CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT (31U) |
#define | CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK) |
OSCPLL_CONFIG - Clock source configuration | |
#define | CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK (0x2U) |
#define | CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT (1U) |
#define | CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK) |
#define | CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK (0x10U) |
#define | CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT (4U) |
#define | CCM_OSCPLL_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK) |
OSCPLL_AUTHEN - Clock source access control | |
#define | CCM_OSCPLL_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_OSCPLL_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK) |
#define | CCM_OSCPLL_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_OSCPLL_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK) |
#define | CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_OSCPLL_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_OSCPLL_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_OSCPLL_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_OSCPLL_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK (0x20000U) |
#define | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT (17U) |
#define | CCM_OSCPLL_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK) |
#define | CCM_OSCPLL_AUTHEN_CPULPM_MASK (0x40000U) |
#define | CCM_OSCPLL_AUTHEN_CPULPM_SHIFT (18U) |
#define | CCM_OSCPLL_AUTHEN_CPULPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_CPULPM_SHIFT)) & CCM_OSCPLL_AUTHEN_CPULPM_MASK) |
#define | CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_OSCPLL_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK) |
LPCG_DIRECT - LPCG direct control | |
#define | CCM_LPCG_DIRECT_ON_MASK (0x1U) |
#define | CCM_LPCG_DIRECT_ON_SHIFT (0U) |
#define | CCM_LPCG_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK) |
LPCG_DOMAIN - LPCG domain control | |
#define | CCM_LPCG_DOMAIN_LEVEL_MASK (0x7U) |
#define | CCM_LPCG_DOMAIN_LEVEL_SHIFT (0U) |
#define | CCM_LPCG_DOMAIN_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL_MASK) |
#define | CCM_LPCG_DOMAIN_LEVEL0_MASK (0x70000U) |
#define | CCM_LPCG_DOMAIN_LEVEL0_SHIFT (16U) |
#define | CCM_LPCG_DOMAIN_LEVEL0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL0_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL0_MASK) |
#define | CCM_LPCG_DOMAIN_LEVEL1_MASK (0x700000U) |
#define | CCM_LPCG_DOMAIN_LEVEL1_SHIFT (20U) |
#define | CCM_LPCG_DOMAIN_LEVEL1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL1_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL1_MASK) |
#define | CCM_LPCG_DOMAIN_LEVEL2_MASK (0x7000000U) |
#define | CCM_LPCG_DOMAIN_LEVEL2_SHIFT (24U) |
#define | CCM_LPCG_DOMAIN_LEVEL2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL2_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL2_MASK) |
#define | CCM_LPCG_DOMAIN_LEVEL3_MASK (0x70000000U) |
#define | CCM_LPCG_DOMAIN_LEVEL3_SHIFT (28U) |
#define | CCM_LPCG_DOMAIN_LEVEL3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL3_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL3_MASK) |
LPCG_SETPOINT - LPCG Setpoint setting | |
#define | CCM_LPCG_SETPOINT_SETPOINT_MASK (0xFFFFU) |
#define | CCM_LPCG_SETPOINT_SETPOINT_SHIFT (0U) |
#define | CCM_LPCG_SETPOINT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_SETPOINT_SHIFT)) & CCM_LPCG_SETPOINT_SETPOINT_MASK) |
#define | CCM_LPCG_SETPOINT_STANDBY_MASK (0xFFFF0000U) |
#define | CCM_LPCG_SETPOINT_STANDBY_SHIFT (16U) |
#define | CCM_LPCG_SETPOINT_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_STANDBY_SHIFT)) & CCM_LPCG_SETPOINT_STANDBY_MASK) |
LPCG_STATUS0 - LPCG working status | |
#define | CCM_LPCG_STATUS0_ON_MASK (0x1U) |
#define | CCM_LPCG_STATUS0_ON_SHIFT (0U) |
#define | CCM_LPCG_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK) |
#define | CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK (0xF00U) |
#define | CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT (8U) |
#define | CCM_LPCG_STATUS0_ACTIVE_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK) |
#define | CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK (0xF000U) |
#define | CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT (12U) |
#define | CCM_LPCG_STATUS0_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK) |
LPCG_STATUS1 - LPCG low power status | |
#define | CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) |
#define | CCM_LPCG_STATUS1_CPU0_MODE_SHIFT (0U) |
#define | CCM_LPCG_STATUS1_CPU0_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK) |
#define | CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U) |
#define | CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U) |
#define | CCM_LPCG_STATUS1_CPU0_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK) |
#define | CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK (0x8U) |
#define | CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT (3U) |
#define | CCM_LPCG_STATUS1_CPU0_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK) |
#define | CCM_LPCG_STATUS1_CPU1_MODE_MASK (0x30U) |
#define | CCM_LPCG_STATUS1_CPU1_MODE_SHIFT (4U) |
#define | CCM_LPCG_STATUS1_CPU1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_MASK) |
#define | CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U) |
#define | CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U) |
#define | CCM_LPCG_STATUS1_CPU1_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK) |
#define | CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK (0x80U) |
#define | CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT (7U) |
#define | CCM_LPCG_STATUS1_CPU1_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK) |
#define | CCM_LPCG_STATUS1_CPU2_MODE_MASK (0x300U) |
#define | CCM_LPCG_STATUS1_CPU2_MODE_SHIFT (8U) |
#define | CCM_LPCG_STATUS1_CPU2_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_MASK) |
#define | CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U) |
#define | CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U) |
#define | CCM_LPCG_STATUS1_CPU2_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK) |
#define | CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK (0x800U) |
#define | CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT (11U) |
#define | CCM_LPCG_STATUS1_CPU2_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK) |
#define | CCM_LPCG_STATUS1_CPU3_MODE_MASK (0x3000U) |
#define | CCM_LPCG_STATUS1_CPU3_MODE_SHIFT (12U) |
#define | CCM_LPCG_STATUS1_CPU3_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_MASK) |
#define | CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U) |
#define | CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U) |
#define | CCM_LPCG_STATUS1_CPU3_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK) |
#define | CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK (0x8000U) |
#define | CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT (15U) |
#define | CCM_LPCG_STATUS1_CPU3_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK) |
#define | CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK (0xF0000U) |
#define | CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT (16U) |
#define | CCM_LPCG_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK) |
#define | CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U) |
#define | CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT (20U) |
#define | CCM_LPCG_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK) |
#define | CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U) |
#define | CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U) |
#define | CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK) |
#define | CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U) |
#define | CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U) |
#define | CCM_LPCG_STATUS1_SETPOINT_OFF_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK) |
#define | CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U) |
#define | CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U) |
#define | CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK) |
#define | CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U) |
#define | CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT (27U) |
#define | CCM_LPCG_STATUS1_SETPOINT_ON_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK) |
LPCG_CONFIG - LPCG configuration | |
#define | CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK (0x10U) |
#define | CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT (4U) |
#define | CCM_LPCG_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK) |
LPCG_AUTHEN - LPCG access control | |
#define | CCM_LPCG_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_LPCG_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_LPCG_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK) |
#define | CCM_LPCG_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_LPCG_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_LPCG_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK) |
#define | CCM_LPCG_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_LPCG_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_LPCG_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_LPCG_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_LPCG_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_LPCG_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_LPCG_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK (0x20000U) |
#define | CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT (17U) |
#define | CCM_LPCG_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK) |
#define | CCM_LPCG_AUTHEN_CPULPM_MASK (0x40000U) |
#define | CCM_LPCG_AUTHEN_CPULPM_SHIFT (18U) |
#define | CCM_LPCG_AUTHEN_CPULPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_CPULPM_SHIFT)) & CCM_LPCG_AUTHEN_CPULPM_MASK) |
#define | CCM_LPCG_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_LPCG_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_MODE_MASK) |
OBSERVE_CONTROL - Observe control | |
#define | CCM_OBS_OBSERVE_CONTROL_SELECT_MASK (0x1FFU) |
#define | CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_CONTROL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SELECT_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_RAW_MASK (0x1000U) |
#define | CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT (12U) |
#define | CCM_OBS_OBSERVE_CONTROL_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RAW_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_INV_MASK (0x2000U) |
#define | CCM_OBS_OBSERVE_CONTROL_INV_SHIFT (13U) |
#define | CCM_OBS_OBSERVE_CONTROL_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_INV_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_RESET_MASK (0x8000U) |
#define | CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT (15U) |
#define | CCM_OBS_OBSERVE_CONTROL_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RESET_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK (0xFF0000U) |
#define | CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT (16U) |
#define | CCM_OBS_OBSERVE_CONTROL_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_OFF_MASK (0x1000000U) |
#define | CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT (24U) |
#define | CCM_OBS_OBSERVE_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_OFF_MASK) |
OBSERVE_CONTROL_SET - Observe control | |
#define | CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK (0x1FFU) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK (0x1000U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT (12U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK (0x2000U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT (13U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK (0x8000U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT (15U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK (0xFF0000U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT (16U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK (0x1000000U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT (24U) |
#define | CCM_OBS_OBSERVE_CONTROL_SET_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK) |
OBSERVE_CONTROL_CLR - Observe control | |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK (0x1FFU) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK (0x1000U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT (12U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK (0x2000U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT (13U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK (0x8000U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT (15U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK (0xFF0000U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT (16U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK (0x1000000U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT (24U) |
#define | CCM_OBS_OBSERVE_CONTROL_CLR_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK) |
OBSERVE_CONTROL_TOG - Observe control | |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK (0x1FFU) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK (0x1000U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT (12U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK (0x2000U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT (13U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK (0x8000U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT (15U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK (0xFF0000U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT (16U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK (0x1000000U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT (24U) |
#define | CCM_OBS_OBSERVE_CONTROL_TOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK) |
OBSERVE_STATUS0 - Observe status | |
#define | CCM_OBS_OBSERVE_STATUS0_SELECT_MASK (0x1FFU) |
#define | CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_STATUS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_SELECT_MASK) |
#define | CCM_OBS_OBSERVE_STATUS0_RAW_MASK (0x1000U) |
#define | CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT (12U) |
#define | CCM_OBS_OBSERVE_STATUS0_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RAW_MASK) |
#define | CCM_OBS_OBSERVE_STATUS0_INV_MASK (0x2000U) |
#define | CCM_OBS_OBSERVE_STATUS0_INV_SHIFT (13U) |
#define | CCM_OBS_OBSERVE_STATUS0_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_INV_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_INV_MASK) |
#define | CCM_OBS_OBSERVE_STATUS0_RESET_MASK (0x8000U) |
#define | CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT (15U) |
#define | CCM_OBS_OBSERVE_STATUS0_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RESET_MASK) |
#define | CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK (0xFF0000U) |
#define | CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT (16U) |
#define | CCM_OBS_OBSERVE_STATUS0_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK) |
#define | CCM_OBS_OBSERVE_STATUS0_OFF_MASK (0x1000000U) |
#define | CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT (24U) |
#define | CCM_OBS_OBSERVE_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_OFF_MASK) |
OBSERVE_AUTHEN - Observe access control | |
#define | CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK (0x1U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK (0x2U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT (1U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK (0x10U) |
#define | CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT (4U) |
#define | CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK (0xF00U) |
#define | CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT (8U) |
#define | CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK (0x1000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT (12U) |
#define | CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK (0x100000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT (20U) |
#define | CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK) |
OBSERVE_AUTHEN_SET - Observe access control | |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK (0x1U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK (0x2U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT (1U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK (0x10U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT (4U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT (8U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT (12U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT (20U) |
#define | CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK) |
OBSERVE_AUTHEN_CLR - Observe access control | |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK (0x1U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK (0x2U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT (1U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) |
#define | CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK) |
OBSERVE_AUTHEN_TOG - Observe access control | |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK (0x1U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK (0x2U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT (1U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) |
#define | CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK) |
OBSERVE_FREQUENCY_CURRENT - Current frequency detected | |
#define | CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK (0xFFFFFFFFU) |
#define | CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK) |
OBSERVE_FREQUENCY_MIN - Minimum frequency detected | |
#define | CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK (0xFFFFFFFFU) |
#define | CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK) |
OBSERVE_FREQUENCY_MAX - Maximum frequency detected | |
#define | CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK (0xFFFFFFFFU) |
#define | CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT (0U) |
#define | CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK) |
CONTROL - Control | |
#define | CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) |
#define | CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) |
#define | CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) |
#define | CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) |
#define | CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) |
#define | CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) |
#define | CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) |
#define | CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) |
#define | CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) |
#define | CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) |
#define | CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) |
#define | CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) |
#define | CDOG_CONTROL_CONTROL_CTRL_MASK (0x3800U) |
#define | CDOG_CONTROL_CONTROL_CTRL_SHIFT (11U) |
#define | CDOG_CONTROL_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK) |
#define | CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) |
#define | CDOG_CONTROL_STATE_CTRL_SHIFT (14U) |
#define | CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) |
#define | CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) |
#define | CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) |
#define | CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) |
#define | CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) |
#define | CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) |
#define | CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) |
#define | CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) |
#define | CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) |
#define | CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) |
RELOAD - Instruction Timer reload | |
#define | CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) |
#define | CDOG_RELOAD_RLOAD_SHIFT (0U) |
#define | CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) |
INSTRUCTION_TIMER - Instruction Timer | |
#define | CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) |
#define | CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) |
#define | CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) |
SECURE_COUNTER - Secure Counter | |
#define | CDOG_SECURE_COUNTER_SECCNT_MASK (0xFFFFFFFFU) |
#define | CDOG_SECURE_COUNTER_SECCNT_SHIFT (0U) |
#define | CDOG_SECURE_COUNTER_SECCNT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK) |
STATUS - Status 1 | |
#define | CDOG_STATUS_NUMTOF_MASK (0xFFU) |
#define | CDOG_STATUS_NUMTOF_SHIFT (0U) |
#define | CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) |
#define | CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) |
#define | CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) |
#define | CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) |
#define | CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) |
#define | CDOG_STATUS_NUMILSEQF_SHIFT (16U) |
#define | CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) |
#define | CDOG_STATUS_CURST_MASK (0xF0000000U) |
#define | CDOG_STATUS_CURST_SHIFT (28U) |
#define | CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) |
STATUS2 - Status 2 | |
#define | CDOG_STATUS2_NUMCNTF_MASK (0xFFU) |
#define | CDOG_STATUS2_NUMCNTF_SHIFT (0U) |
#define | CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) |
#define | CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) |
#define | CDOG_STATUS2_NUMILLSTF_SHIFT (8U) |
#define | CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) |
#define | CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) |
#define | CDOG_STATUS2_NUMILLA_SHIFT (16U) |
#define | CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) |
FLAGS - Flags | |
#define | CDOG_FLAGS_TO_FLAG_MASK (0x1U) |
#define | CDOG_FLAGS_TO_FLAG_SHIFT (0U) |
#define | CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) |
#define | CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) |
#define | CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) |
#define | CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) |
#define | CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) |
#define | CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) |
#define | CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) |
#define | CDOG_FLAGS_CNT_FLAG_MASK (0x8U) |
#define | CDOG_FLAGS_CNT_FLAG_SHIFT (3U) |
#define | CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) |
#define | CDOG_FLAGS_STATE_FLAG_MASK (0x10U) |
#define | CDOG_FLAGS_STATE_FLAG_SHIFT (4U) |
#define | CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) |
#define | CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) |
#define | CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) |
#define | CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) |
#define | CDOG_FLAGS_POR_FLAG_MASK (0x10000U) |
#define | CDOG_FLAGS_POR_FLAG_SHIFT (16U) |
#define | CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) |
PERSISTENT - Persistent Data Storage | |
#define | CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) |
#define | CDOG_PERSISTENT_PERSIS_SHIFT (0U) |
#define | CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) |
START - START Command | |
#define | CDOG_START_STRT_MASK (0xFFFFFFFFU) |
#define | CDOG_START_STRT_SHIFT (0U) |
#define | CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) |
STOP - STOP Command | |
#define | CDOG_STOP_STP_MASK (0xFFFFFFFFU) |
#define | CDOG_STOP_STP_SHIFT (0U) |
#define | CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) |
RESTART - RESTART Command | |
#define | CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) |
#define | CDOG_RESTART_RSTRT_SHIFT (0U) |
#define | CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) |
ADD - ADD Command | |
#define | CDOG_ADD_AD_MASK (0xFFFFFFFFU) |
#define | CDOG_ADD_AD_SHIFT (0U) |
#define | CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) |
ADD1 - ADD1 Command | |
#define | CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) |
#define | CDOG_ADD1_AD1_SHIFT (0U) |
#define | CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) |
ADD16 - ADD16 Command | |
#define | CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) |
#define | CDOG_ADD16_AD16_SHIFT (0U) |
#define | CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) |
ADD256 - ADD256 Command | |
#define | CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) |
#define | CDOG_ADD256_AD256_SHIFT (0U) |
#define | CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) |
SUB - SUB Command | |
#define | CDOG_SUB_S0B_MASK (0xFFFFFFFFU) |
#define | CDOG_SUB_S0B_SHIFT (0U) |
#define | CDOG_SUB_S0B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK) |
SUB1 - SUB1 Command | |
#define | CDOG_SUB1_S1B_MASK (0xFFFFFFFFU) |
#define | CDOG_SUB1_S1B_SHIFT (0U) |
#define | CDOG_SUB1_S1B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK) |
SUB16 - SUB16 Command | |
#define | CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) |
#define | CDOG_SUB16_SB16_SHIFT (0U) |
#define | CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) |
SUB256 - SUB256 Command | |
#define | CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) |
#define | CDOG_SUB256_SB256_SHIFT (0U) |
#define | CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) |
C0 - CMP Control Register 0 | |
#define | CMP_C0_HYSTCTR_MASK (0x3U) |
#define | CMP_C0_HYSTCTR_SHIFT (0U) |
#define | CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK) |
#define | CMP_C0_FILTER_CNT_MASK (0x70U) |
#define | CMP_C0_FILTER_CNT_SHIFT (4U) |
#define | CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK) |
#define | CMP_C0_EN_MASK (0x100U) |
#define | CMP_C0_EN_SHIFT (8U) |
#define | CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK) |
#define | CMP_C0_OPE_MASK (0x200U) |
#define | CMP_C0_OPE_SHIFT (9U) |
#define | CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK) |
#define | CMP_C0_COS_MASK (0x400U) |
#define | CMP_C0_COS_SHIFT (10U) |
#define | CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK) |
#define | CMP_C0_INVT_MASK (0x800U) |
#define | CMP_C0_INVT_SHIFT (11U) |
#define | CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK) |
#define | CMP_C0_PMODE_MASK (0x1000U) |
#define | CMP_C0_PMODE_SHIFT (12U) |
#define | CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK) |
#define | CMP_C0_WE_MASK (0x4000U) |
#define | CMP_C0_WE_SHIFT (14U) |
#define | CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK) |
#define | CMP_C0_SE_MASK (0x8000U) |
#define | CMP_C0_SE_SHIFT (15U) |
#define | CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK) |
#define | CMP_C0_FPR_MASK (0xFF0000U) |
#define | CMP_C0_FPR_SHIFT (16U) |
#define | CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK) |
#define | CMP_C0_COUT_MASK (0x1000000U) |
#define | CMP_C0_COUT_SHIFT (24U) |
#define | CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK) |
#define | CMP_C0_CFF_MASK (0x2000000U) |
#define | CMP_C0_CFF_SHIFT (25U) |
#define | CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK) |
#define | CMP_C0_CFR_MASK (0x4000000U) |
#define | CMP_C0_CFR_SHIFT (26U) |
#define | CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK) |
#define | CMP_C0_IEF_MASK (0x8000000U) |
#define | CMP_C0_IEF_SHIFT (27U) |
#define | CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK) |
#define | CMP_C0_IER_MASK (0x10000000U) |
#define | CMP_C0_IER_SHIFT (28U) |
#define | CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK) |
#define | CMP_C0_DMAEN_MASK (0x40000000U) |
#define | CMP_C0_DMAEN_SHIFT (30U) |
#define | CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK) |
#define | CMP_C0_LINKEN_MASK (0x80000000U) |
#define | CMP_C0_LINKEN_SHIFT (31U) |
#define | CMP_C0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK) |
C1 - CMP Control Register 1 | |
#define | CMP_C1_VOSEL_MASK (0xFFU) |
#define | CMP_C1_VOSEL_SHIFT (0U) |
#define | CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK) |
#define | CMP_C1_DMODE_MASK (0x100U) |
#define | CMP_C1_DMODE_SHIFT (8U) |
#define | CMP_C1_DMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK) |
#define | CMP_C1_VRSEL_MASK (0x200U) |
#define | CMP_C1_VRSEL_SHIFT (9U) |
#define | CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK) |
#define | CMP_C1_DACEN_MASK (0x400U) |
#define | CMP_C1_DACEN_SHIFT (10U) |
#define | CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK) |
#define | CMP_C1_CHN0_MASK (0x10000U) |
#define | CMP_C1_CHN0_SHIFT (16U) |
#define | CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK) |
#define | CMP_C1_CHN1_MASK (0x20000U) |
#define | CMP_C1_CHN1_SHIFT (17U) |
#define | CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK) |
#define | CMP_C1_CHN2_MASK (0x40000U) |
#define | CMP_C1_CHN2_SHIFT (18U) |
#define | CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK) |
#define | CMP_C1_CHN3_MASK (0x80000U) |
#define | CMP_C1_CHN3_SHIFT (19U) |
#define | CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK) |
#define | CMP_C1_CHN4_MASK (0x100000U) |
#define | CMP_C1_CHN4_SHIFT (20U) |
#define | CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK) |
#define | CMP_C1_CHN5_MASK (0x200000U) |
#define | CMP_C1_CHN5_SHIFT (21U) |
#define | CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK) |
#define | CMP_C1_MSEL_MASK (0x7000000U) |
#define | CMP_C1_MSEL_SHIFT (24U) |
#define | CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK) |
#define | CMP_C1_PSEL_MASK (0x70000000U) |
#define | CMP_C1_PSEL_SHIFT (28U) |
#define | CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK) |
C2 - CMP Control Register 2 | |
#define | CMP_C2_ACOn_MASK (0x3FU) |
#define | CMP_C2_ACOn_SHIFT (0U) |
#define | CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK) |
#define | CMP_C2_INITMOD_MASK (0x3F00U) |
#define | CMP_C2_INITMOD_SHIFT (8U) |
#define | CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK) |
#define | CMP_C2_NSAM_MASK (0xC000U) |
#define | CMP_C2_NSAM_SHIFT (14U) |
#define | CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK) |
#define | CMP_C2_CH0F_MASK (0x10000U) |
#define | CMP_C2_CH0F_SHIFT (16U) |
#define | CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK) |
#define | CMP_C2_CH1F_MASK (0x20000U) |
#define | CMP_C2_CH1F_SHIFT (17U) |
#define | CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK) |
#define | CMP_C2_CH2F_MASK (0x40000U) |
#define | CMP_C2_CH2F_SHIFT (18U) |
#define | CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK) |
#define | CMP_C2_CH3F_MASK (0x80000U) |
#define | CMP_C2_CH3F_SHIFT (19U) |
#define | CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK) |
#define | CMP_C2_CH4F_MASK (0x100000U) |
#define | CMP_C2_CH4F_SHIFT (20U) |
#define | CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK) |
#define | CMP_C2_CH5F_MASK (0x200000U) |
#define | CMP_C2_CH5F_SHIFT (21U) |
#define | CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK) |
#define | CMP_C2_FXMXCH_MASK (0xE000000U) |
#define | CMP_C2_FXMXCH_SHIFT (25U) |
#define | CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK) |
#define | CMP_C2_FXMP_MASK (0x20000000U) |
#define | CMP_C2_FXMP_SHIFT (29U) |
#define | CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK) |
#define | CMP_C2_RRIE_MASK (0x40000000U) |
#define | CMP_C2_RRIE_SHIFT (30U) |
#define | CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK) |
C3 - CMP Control Register 3 | |
#define | CMP_C3_ACPH2TC_MASK (0x70U) |
#define | CMP_C3_ACPH2TC_SHIFT (4U) |
#define | CMP_C3_ACPH2TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK) |
#define | CMP_C3_ACPH1TC_MASK (0x700U) |
#define | CMP_C3_ACPH1TC_SHIFT (8U) |
#define | CMP_C3_ACPH1TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK) |
#define | CMP_C3_ACSAT_MASK (0x7000U) |
#define | CMP_C3_ACSAT_SHIFT (12U) |
#define | CMP_C3_ACSAT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK) |
#define | CMP_C3_DMCS_MASK (0x10000U) |
#define | CMP_C3_DMCS_SHIFT (16U) |
#define | CMP_C3_DMCS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK) |
#define | CMP_C3_RDIVE_MASK (0x100000U) |
#define | CMP_C3_RDIVE_SHIFT (20U) |
#define | CMP_C3_RDIVE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK) |
#define | CMP_C3_NCHCTEN_MASK (0x1000000U) |
#define | CMP_C3_NCHCTEN_SHIFT (24U) |
#define | CMP_C3_NCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK) |
#define | CMP_C3_PCHCTEN_MASK (0x10000000U) |
#define | CMP_C3_PCHCTEN_SHIFT (28U) |
#define | CMP_C3_PCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK) |
CR1 - CSI Control Register 1 | |
#define | CSI_CR1_PIXEL_BIT_MASK (0x1U) |
#define | CSI_CR1_PIXEL_BIT_SHIFT (0U) |
#define | CSI_CR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PIXEL_BIT_SHIFT)) & CSI_CR1_PIXEL_BIT_MASK) |
#define | CSI_CR1_REDGE_MASK (0x2U) |
#define | CSI_CR1_REDGE_SHIFT (1U) |
#define | CSI_CR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_REDGE_SHIFT)) & CSI_CR1_REDGE_MASK) |
#define | CSI_CR1_INV_PCLK_MASK (0x4U) |
#define | CSI_CR1_INV_PCLK_SHIFT (2U) |
#define | CSI_CR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_PCLK_SHIFT)) & CSI_CR1_INV_PCLK_MASK) |
#define | CSI_CR1_INV_DATA_MASK (0x8U) |
#define | CSI_CR1_INV_DATA_SHIFT (3U) |
#define | CSI_CR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_DATA_SHIFT)) & CSI_CR1_INV_DATA_MASK) |
#define | CSI_CR1_GCLK_MODE_MASK (0x10U) |
#define | CSI_CR1_GCLK_MODE_SHIFT (4U) |
#define | CSI_CR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_GCLK_MODE_SHIFT)) & CSI_CR1_GCLK_MODE_MASK) |
#define | CSI_CR1_CLR_RXFIFO_MASK (0x20U) |
#define | CSI_CR1_CLR_RXFIFO_SHIFT (5U) |
#define | CSI_CR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_RXFIFO_SHIFT)) & CSI_CR1_CLR_RXFIFO_MASK) |
#define | CSI_CR1_CLR_STATFIFO_MASK (0x40U) |
#define | CSI_CR1_CLR_STATFIFO_SHIFT (6U) |
#define | CSI_CR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_STATFIFO_SHIFT)) & CSI_CR1_CLR_STATFIFO_MASK) |
#define | CSI_CR1_PACK_DIR_MASK (0x80U) |
#define | CSI_CR1_PACK_DIR_SHIFT (7U) |
#define | CSI_CR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PACK_DIR_SHIFT)) & CSI_CR1_PACK_DIR_MASK) |
#define | CSI_CR1_FCC_MASK (0x100U) |
#define | CSI_CR1_FCC_SHIFT (8U) |
#define | CSI_CR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FCC_SHIFT)) & CSI_CR1_FCC_MASK) |
#define | CSI_CR1_CCIR_EN_MASK (0x400U) |
#define | CSI_CR1_CCIR_EN_SHIFT (10U) |
#define | CSI_CR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CCIR_EN_SHIFT)) & CSI_CR1_CCIR_EN_MASK) |
#define | CSI_CR1_HSYNC_POL_MASK (0x800U) |
#define | CSI_CR1_HSYNC_POL_SHIFT (11U) |
#define | CSI_CR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HSYNC_POL_SHIFT)) & CSI_CR1_HSYNC_POL_MASK) |
#define | CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK (0x1000U) |
#define | CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT (12U) |
#define | CSI_CR1_HISTOGRAM_CALC_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT)) & CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK) |
#define | CSI_CR1_SOF_INTEN_MASK (0x10000U) |
#define | CSI_CR1_SOF_INTEN_SHIFT (16U) |
#define | CSI_CR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_INTEN_SHIFT)) & CSI_CR1_SOF_INTEN_MASK) |
#define | CSI_CR1_SOF_POL_MASK (0x20000U) |
#define | CSI_CR1_SOF_POL_SHIFT (17U) |
#define | CSI_CR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_POL_SHIFT)) & CSI_CR1_SOF_POL_MASK) |
#define | CSI_CR1_RXFF_INTEN_MASK (0x40000U) |
#define | CSI_CR1_RXFF_INTEN_SHIFT (18U) |
#define | CSI_CR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RXFF_INTEN_SHIFT)) & CSI_CR1_RXFF_INTEN_MASK) |
#define | CSI_CR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) |
#define | CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT (19U) |
#define | CSI_CR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB1_DMA_DONE_INTEN_MASK) |
#define | CSI_CR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) |
#define | CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT (20U) |
#define | CSI_CR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB2_DMA_DONE_INTEN_MASK) |
#define | CSI_CR1_STATFF_INTEN_MASK (0x200000U) |
#define | CSI_CR1_STATFF_INTEN_SHIFT (21U) |
#define | CSI_CR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_STATFF_INTEN_SHIFT)) & CSI_CR1_STATFF_INTEN_MASK) |
#define | CSI_CR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) |
#define | CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT (22U) |
#define | CSI_CR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_SFF_DMA_DONE_INTEN_MASK) |
#define | CSI_CR1_RF_OR_INTEN_MASK (0x1000000U) |
#define | CSI_CR1_RF_OR_INTEN_SHIFT (24U) |
#define | CSI_CR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RF_OR_INTEN_SHIFT)) & CSI_CR1_RF_OR_INTEN_MASK) |
#define | CSI_CR1_SF_OR_INTEN_MASK (0x2000000U) |
#define | CSI_CR1_SF_OR_INTEN_SHIFT (25U) |
#define | CSI_CR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SF_OR_INTEN_SHIFT)) & CSI_CR1_SF_OR_INTEN_MASK) |
#define | CSI_CR1_COF_INT_EN_MASK (0x4000000U) |
#define | CSI_CR1_COF_INT_EN_SHIFT (26U) |
#define | CSI_CR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_COF_INT_EN_SHIFT)) & CSI_CR1_COF_INT_EN_MASK) |
#define | CSI_CR1_VIDEO_MODE_MASK (0x8000000U) |
#define | CSI_CR1_VIDEO_MODE_SHIFT (27U) |
#define | CSI_CR1_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_VIDEO_MODE_SHIFT)) & CSI_CR1_VIDEO_MODE_MASK) |
#define | CSI_CR1_EOF_INT_EN_MASK (0x20000000U) |
#define | CSI_CR1_EOF_INT_EN_SHIFT (29U) |
#define | CSI_CR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EOF_INT_EN_SHIFT)) & CSI_CR1_EOF_INT_EN_MASK) |
#define | CSI_CR1_EXT_VSYNC_MASK (0x40000000U) |
#define | CSI_CR1_EXT_VSYNC_SHIFT (30U) |
#define | CSI_CR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EXT_VSYNC_SHIFT)) & CSI_CR1_EXT_VSYNC_MASK) |
#define | CSI_CR1_SWAP16_EN_MASK (0x80000000U) |
#define | CSI_CR1_SWAP16_EN_SHIFT (31U) |
#define | CSI_CR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SWAP16_EN_SHIFT)) & CSI_CR1_SWAP16_EN_MASK) |
CR2 - CSI Control Register 2 | |
#define | CSI_CR2_HSC_MASK (0xFFU) |
#define | CSI_CR2_HSC_SHIFT (0U) |
#define | CSI_CR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_HSC_SHIFT)) & CSI_CR2_HSC_MASK) |
#define | CSI_CR2_VSC_MASK (0xFF00U) |
#define | CSI_CR2_VSC_SHIFT (8U) |
#define | CSI_CR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_VSC_SHIFT)) & CSI_CR2_VSC_MASK) |
#define | CSI_CR2_LVRM_MASK (0x70000U) |
#define | CSI_CR2_LVRM_SHIFT (16U) |
#define | CSI_CR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_LVRM_SHIFT)) & CSI_CR2_LVRM_MASK) |
#define | CSI_CR2_BTS_MASK (0x180000U) |
#define | CSI_CR2_BTS_SHIFT (19U) |
#define | CSI_CR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_BTS_SHIFT)) & CSI_CR2_BTS_MASK) |
#define | CSI_CR2_SCE_MASK (0x800000U) |
#define | CSI_CR2_SCE_SHIFT (23U) |
#define | CSI_CR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_SCE_SHIFT)) & CSI_CR2_SCE_MASK) |
#define | CSI_CR2_AFS_MASK (0x3000000U) |
#define | CSI_CR2_AFS_SHIFT (24U) |
#define | CSI_CR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_AFS_SHIFT)) & CSI_CR2_AFS_MASK) |
#define | CSI_CR2_DRM_MASK (0x4000000U) |
#define | CSI_CR2_DRM_SHIFT (26U) |
#define | CSI_CR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DRM_SHIFT)) & CSI_CR2_DRM_MASK) |
#define | CSI_CR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) |
#define | CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT (28U) |
#define | CSI_CR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_SFF_MASK) |
#define | CSI_CR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) |
#define | CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT (30U) |
#define | CSI_CR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_RFF_MASK) |
CR3 - CSI Control Register 3 | |
#define | CSI_CR3_ECC_AUTO_EN_MASK (0x1U) |
#define | CSI_CR3_ECC_AUTO_EN_SHIFT (0U) |
#define | CSI_CR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_AUTO_EN_SHIFT)) & CSI_CR3_ECC_AUTO_EN_MASK) |
#define | CSI_CR3_ECC_INT_EN_MASK (0x2U) |
#define | CSI_CR3_ECC_INT_EN_SHIFT (1U) |
#define | CSI_CR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_INT_EN_SHIFT)) & CSI_CR3_ECC_INT_EN_MASK) |
#define | CSI_CR3_ZERO_PACK_EN_MASK (0x4U) |
#define | CSI_CR3_ZERO_PACK_EN_SHIFT (2U) |
#define | CSI_CR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ZERO_PACK_EN_SHIFT)) & CSI_CR3_ZERO_PACK_EN_MASK) |
#define | CSI_CR3_SENSOR_16BITS_MASK (0x8U) |
#define | CSI_CR3_SENSOR_16BITS_SHIFT (3U) |
#define | CSI_CR3_SENSOR_16BITS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_SENSOR_16BITS_SHIFT)) & CSI_CR3_SENSOR_16BITS_MASK) |
#define | CSI_CR3_RxFF_LEVEL_MASK (0x70U) |
#define | CSI_CR3_RxFF_LEVEL_SHIFT (4U) |
#define | CSI_CR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_RxFF_LEVEL_SHIFT)) & CSI_CR3_RxFF_LEVEL_MASK) |
#define | CSI_CR3_HRESP_ERR_EN_MASK (0x80U) |
#define | CSI_CR3_HRESP_ERR_EN_SHIFT (7U) |
#define | CSI_CR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_HRESP_ERR_EN_SHIFT)) & CSI_CR3_HRESP_ERR_EN_MASK) |
#define | CSI_CR3_STATFF_LEVEL_MASK (0x700U) |
#define | CSI_CR3_STATFF_LEVEL_SHIFT (8U) |
#define | CSI_CR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_STATFF_LEVEL_SHIFT)) & CSI_CR3_STATFF_LEVEL_MASK) |
#define | CSI_CR3_DMA_REQ_EN_SFF_MASK (0x800U) |
#define | CSI_CR3_DMA_REQ_EN_SFF_SHIFT (11U) |
#define | CSI_CR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_SFF_MASK) |
#define | CSI_CR3_DMA_REQ_EN_RFF_MASK (0x1000U) |
#define | CSI_CR3_DMA_REQ_EN_RFF_SHIFT (12U) |
#define | CSI_CR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_RFF_MASK) |
#define | CSI_CR3_DMA_REFLASH_SFF_MASK (0x2000U) |
#define | CSI_CR3_DMA_REFLASH_SFF_SHIFT (13U) |
#define | CSI_CR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CR3_DMA_REFLASH_SFF_MASK) |
#define | CSI_CR3_DMA_REFLASH_RFF_MASK (0x4000U) |
#define | CSI_CR3_DMA_REFLASH_RFF_SHIFT (14U) |
#define | CSI_CR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CR3_DMA_REFLASH_RFF_MASK) |
#define | CSI_CR3_FRMCNT_RST_MASK (0x8000U) |
#define | CSI_CR3_FRMCNT_RST_SHIFT (15U) |
#define | CSI_CR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_RST_SHIFT)) & CSI_CR3_FRMCNT_RST_MASK) |
#define | CSI_CR3_FRMCNT_MASK (0xFFFF0000U) |
#define | CSI_CR3_FRMCNT_SHIFT (16U) |
#define | CSI_CR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_SHIFT)) & CSI_CR3_FRMCNT_MASK) |
STATFIFO - CSI Statistic FIFO Register | |
#define | CSI_STATFIFO_STAT_MASK (0xFFFFFFFFU) |
#define | CSI_STATFIFO_STAT_SHIFT (0U) |
#define | CSI_STATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_STATFIFO_STAT_SHIFT)) & CSI_STATFIFO_STAT_MASK) |
RFIFO - CSI RX FIFO Register | |
#define | CSI_RFIFO_IMAGE_MASK (0xFFFFFFFFU) |
#define | CSI_RFIFO_IMAGE_SHIFT (0U) |
#define | CSI_RFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_RFIFO_IMAGE_SHIFT)) & CSI_RFIFO_IMAGE_MASK) |
RXCNT - CSI RX Count Register | |
#define | CSI_RXCNT_RXCNT_MASK (0x3FFFFFU) |
#define | CSI_RXCNT_RXCNT_SHIFT (0U) |
#define | CSI_RXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_RXCNT_RXCNT_SHIFT)) & CSI_RXCNT_RXCNT_MASK) |
SR - CSI Status Register | |
#define | CSI_SR_DRDY_MASK (0x1U) |
#define | CSI_SR_DRDY_SHIFT (0U) |
#define | CSI_SR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DRDY_SHIFT)) & CSI_SR_DRDY_MASK) |
#define | CSI_SR_ECC_INT_MASK (0x2U) |
#define | CSI_SR_ECC_INT_SHIFT (1U) |
#define | CSI_SR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_ECC_INT_SHIFT)) & CSI_SR_ECC_INT_MASK) |
#define | CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK (0x4U) |
#define | CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT (2U) |
#define | CSI_SR_HISTOGRAM_CALC_DONE_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT)) & CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK) |
#define | CSI_SR_HRESP_ERR_INT_MASK (0x80U) |
#define | CSI_SR_HRESP_ERR_INT_SHIFT (7U) |
#define | CSI_SR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_HRESP_ERR_INT_SHIFT)) & CSI_SR_HRESP_ERR_INT_MASK) |
#define | CSI_SR_COF_INT_MASK (0x2000U) |
#define | CSI_SR_COF_INT_SHIFT (13U) |
#define | CSI_SR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_COF_INT_SHIFT)) & CSI_SR_COF_INT_MASK) |
#define | CSI_SR_F1_INT_MASK (0x4000U) |
#define | CSI_SR_F1_INT_SHIFT (14U) |
#define | CSI_SR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_F1_INT_SHIFT)) & CSI_SR_F1_INT_MASK) |
#define | CSI_SR_F2_INT_MASK (0x8000U) |
#define | CSI_SR_F2_INT_SHIFT (15U) |
#define | CSI_SR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_F2_INT_SHIFT)) & CSI_SR_F2_INT_MASK) |
#define | CSI_SR_SOF_INT_MASK (0x10000U) |
#define | CSI_SR_SOF_INT_SHIFT (16U) |
#define | CSI_SR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_SOF_INT_SHIFT)) & CSI_SR_SOF_INT_MASK) |
#define | CSI_SR_EOF_INT_MASK (0x20000U) |
#define | CSI_SR_EOF_INT_SHIFT (17U) |
#define | CSI_SR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_EOF_INT_SHIFT)) & CSI_SR_EOF_INT_MASK) |
#define | CSI_SR_RxFF_INT_MASK (0x40000U) |
#define | CSI_SR_RxFF_INT_SHIFT (18U) |
#define | CSI_SR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_RxFF_INT_SHIFT)) & CSI_SR_RxFF_INT_MASK) |
#define | CSI_SR_DMA_TSF_DONE_FB1_MASK (0x80000U) |
#define | CSI_SR_DMA_TSF_DONE_FB1_SHIFT (19U) |
#define | CSI_SR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB1_MASK) |
#define | CSI_SR_DMA_TSF_DONE_FB2_MASK (0x100000U) |
#define | CSI_SR_DMA_TSF_DONE_FB2_SHIFT (20U) |
#define | CSI_SR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB2_MASK) |
#define | CSI_SR_STATFF_INT_MASK (0x200000U) |
#define | CSI_SR_STATFF_INT_SHIFT (21U) |
#define | CSI_SR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_STATFF_INT_SHIFT)) & CSI_SR_STATFF_INT_MASK) |
#define | CSI_SR_DMA_TSF_DONE_SFF_MASK (0x400000U) |
#define | CSI_SR_DMA_TSF_DONE_SFF_SHIFT (22U) |
#define | CSI_SR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_SR_DMA_TSF_DONE_SFF_MASK) |
#define | CSI_SR_RF_OR_INT_MASK (0x1000000U) |
#define | CSI_SR_RF_OR_INT_SHIFT (24U) |
#define | CSI_SR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_RF_OR_INT_SHIFT)) & CSI_SR_RF_OR_INT_MASK) |
#define | CSI_SR_SF_OR_INT_MASK (0x2000000U) |
#define | CSI_SR_SF_OR_INT_SHIFT (25U) |
#define | CSI_SR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_SF_OR_INT_SHIFT)) & CSI_SR_SF_OR_INT_MASK) |
#define | CSI_SR_DMA_FIELD1_DONE_MASK (0x4000000U) |
#define | CSI_SR_DMA_FIELD1_DONE_SHIFT (26U) |
#define | CSI_SR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD1_DONE_SHIFT)) & CSI_SR_DMA_FIELD1_DONE_MASK) |
#define | CSI_SR_DMA_FIELD0_DONE_MASK (0x8000000U) |
#define | CSI_SR_DMA_FIELD0_DONE_SHIFT (27U) |
#define | CSI_SR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD0_DONE_SHIFT)) & CSI_SR_DMA_FIELD0_DONE_MASK) |
#define | CSI_SR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) |
#define | CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) |
#define | CSI_SR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_SR_BASEADDR_CHHANGE_ERROR_MASK) |
DMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO | |
#define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) |
#define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) |
#define | CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) |
DMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO | |
#define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) |
#define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) |
#define | CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) |
DMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 | |
#define | CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) |
#define | CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) |
#define | CSI_DMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK) |
DMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 | |
#define | CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) |
#define | CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) |
#define | CSI_DMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK) |
FBUF_PARA - CSI Frame Buffer Parameter Register | |
#define | CSI_FBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) |
#define | CSI_FBUF_PARA_FBUF_STRIDE_SHIFT (0U) |
#define | CSI_FBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_FBUF_PARA_FBUF_STRIDE_MASK) |
#define | CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) |
#define | CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) |
#define | CSI_FBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK) |
IMAG_PARA - CSI Image Parameter Register | |
#define | CSI_IMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) |
#define | CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) |
#define | CSI_IMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_IMAG_PARA_IMAGE_HEIGHT_MASK) |
#define | CSI_IMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) |
#define | CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT (16U) |
#define | CSI_IMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_IMAG_PARA_IMAGE_WIDTH_MASK) |
CR18 - CSI Control Register 18 | |
#define | CSI_CR18_NTSC_EN_MASK (0x1U) |
#define | CSI_CR18_NTSC_EN_SHIFT (0U) |
#define | CSI_CR18_NTSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_NTSC_EN_SHIFT)) & CSI_CR18_NTSC_EN_MASK) |
#define | CSI_CR18_TVDECODER_IN_EN_MASK (0x2U) |
#define | CSI_CR18_TVDECODER_IN_EN_SHIFT (1U) |
#define | CSI_CR18_TVDECODER_IN_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_TVDECODER_IN_EN_SHIFT)) & CSI_CR18_TVDECODER_IN_EN_MASK) |
#define | CSI_CR18_DEINTERLACE_EN_MASK (0x4U) |
#define | CSI_CR18_DEINTERLACE_EN_SHIFT (2U) |
#define | CSI_CR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DEINTERLACE_EN_SHIFT)) & CSI_CR18_DEINTERLACE_EN_MASK) |
#define | CSI_CR18_PARALLEL24_EN_MASK (0x8U) |
#define | CSI_CR18_PARALLEL24_EN_SHIFT (3U) |
#define | CSI_CR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_PARALLEL24_EN_SHIFT)) & CSI_CR18_PARALLEL24_EN_MASK) |
#define | CSI_CR18_BASEADDR_SWITCH_EN_MASK (0x10U) |
#define | CSI_CR18_BASEADDR_SWITCH_EN_SHIFT (4U) |
#define | CSI_CR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_EN_MASK) |
#define | CSI_CR18_BASEADDR_SWITCH_SEL_MASK (0x20U) |
#define | CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT (5U) |
#define | CSI_CR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_SEL_MASK) |
#define | CSI_CR18_FIELD0_DONE_IE_MASK (0x40U) |
#define | CSI_CR18_FIELD0_DONE_IE_SHIFT (6U) |
#define | CSI_CR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_FIELD0_DONE_IE_SHIFT)) & CSI_CR18_FIELD0_DONE_IE_MASK) |
#define | CSI_CR18_DMA_FIELD1_DONE_IE_MASK (0x80U) |
#define | CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT (7U) |
#define | CSI_CR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CR18_DMA_FIELD1_DONE_IE_MASK) |
#define | CSI_CR18_LAST_DMA_REQ_SEL_MASK (0x100U) |
#define | CSI_CR18_LAST_DMA_REQ_SEL_SHIFT (8U) |
#define | CSI_CR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CR18_LAST_DMA_REQ_SEL_MASK) |
#define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) |
#define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) |
#define | CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK) |
#define | CSI_CR18_RGB888A_FORMAT_SEL_MASK (0x400U) |
#define | CSI_CR18_RGB888A_FORMAT_SEL_SHIFT (10U) |
#define | CSI_CR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CR18_RGB888A_FORMAT_SEL_MASK) |
#define | CSI_CR18_AHB_HPROT_MASK (0xF000U) |
#define | CSI_CR18_AHB_HPROT_SHIFT (12U) |
#define | CSI_CR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_AHB_HPROT_SHIFT)) & CSI_CR18_AHB_HPROT_MASK) |
#define | CSI_CR18_MASK_OPTION_MASK (0xC0000U) |
#define | CSI_CR18_MASK_OPTION_SHIFT (18U) |
#define | CSI_CR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MASK_OPTION_SHIFT)) & CSI_CR18_MASK_OPTION_MASK) |
#define | CSI_CR18_MIPI_DOUBLE_CMPNT_MASK (0x100000U) |
#define | CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT (20U) |
#define | CSI_CR18_MIPI_DOUBLE_CMPNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT)) & CSI_CR18_MIPI_DOUBLE_CMPNT_MASK) |
#define | CSI_CR18_MIPI_YU_SWAP_MASK (0x200000U) |
#define | CSI_CR18_MIPI_YU_SWAP_SHIFT (21U) |
#define | CSI_CR18_MIPI_YU_SWAP(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_YU_SWAP_SHIFT)) & CSI_CR18_MIPI_YU_SWAP_MASK) |
#define | CSI_CR18_DATA_FROM_MIPI_MASK (0x400000U) |
#define | CSI_CR18_DATA_FROM_MIPI_SHIFT (22U) |
#define | CSI_CR18_DATA_FROM_MIPI(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DATA_FROM_MIPI_SHIFT)) & CSI_CR18_DATA_FROM_MIPI_MASK) |
#define | CSI_CR18_LINE_STRIDE_EN_MASK (0x1000000U) |
#define | CSI_CR18_LINE_STRIDE_EN_SHIFT (24U) |
#define | CSI_CR18_LINE_STRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LINE_STRIDE_EN_SHIFT)) & CSI_CR18_LINE_STRIDE_EN_MASK) |
#define | CSI_CR18_MIPI_DATA_FORMAT_MASK (0x7E000000U) |
#define | CSI_CR18_MIPI_DATA_FORMAT_SHIFT (25U) |
#define | CSI_CR18_MIPI_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DATA_FORMAT_SHIFT)) & CSI_CR18_MIPI_DATA_FORMAT_MASK) |
#define | CSI_CR18_CSI_ENABLE_MASK (0x80000000U) |
#define | CSI_CR18_CSI_ENABLE_SHIFT (31U) |
#define | CSI_CR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_CSI_ENABLE_SHIFT)) & CSI_CR18_CSI_ENABLE_MASK) |
CR19 - CSI Control Register 19 | |
#define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) |
#define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) |
#define | CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) |
CR20 - CSI Control Register 20 | |
#define | CSI_CR20_THRESHOLD_MASK (0xFFU) |
#define | CSI_CR20_THRESHOLD_SHIFT (0U) |
#define | CSI_CR20_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_THRESHOLD_SHIFT)) & CSI_CR20_THRESHOLD_MASK) |
#define | CSI_CR20_BINARY_EN_MASK (0x100U) |
#define | CSI_CR20_BINARY_EN_SHIFT (8U) |
#define | CSI_CR20_BINARY_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BINARY_EN_SHIFT)) & CSI_CR20_BINARY_EN_MASK) |
#define | CSI_CR20_QR_DATA_FORMAT_MASK (0xE00U) |
#define | CSI_CR20_QR_DATA_FORMAT_SHIFT (9U) |
#define | CSI_CR20_QR_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QR_DATA_FORMAT_SHIFT)) & CSI_CR20_QR_DATA_FORMAT_MASK) |
#define | CSI_CR20_BIG_END_MASK (0x1000U) |
#define | CSI_CR20_BIG_END_SHIFT (12U) |
#define | CSI_CR20_BIG_END(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BIG_END_SHIFT)) & CSI_CR20_BIG_END_MASK) |
#define | CSI_CR20_10BIT_NEW_EN_MASK (0x20000000U) |
#define | CSI_CR20_10BIT_NEW_EN_SHIFT (29U) |
#define | CSI_CR20_10BIT_NEW_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_10BIT_NEW_EN_SHIFT)) & CSI_CR20_10BIT_NEW_EN_MASK) |
#define | CSI_CR20_HISTOGRAM_EN_MASK (0x40000000U) |
#define | CSI_CR20_HISTOGRAM_EN_SHIFT (30U) |
#define | CSI_CR20_HISTOGRAM_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_HISTOGRAM_EN_SHIFT)) & CSI_CR20_HISTOGRAM_EN_MASK) |
#define | CSI_CR20_QRCODE_EN_MASK (0x80000000U) |
#define | CSI_CR20_QRCODE_EN_SHIFT (31U) |
#define | CSI_CR20_QRCODE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QRCODE_EN_SHIFT)) & CSI_CR20_QRCODE_EN_MASK) |
CR - CSI Control Register | |
#define | CSI_CR_PIXEL_COUNTERS_MASK (0xFFFFFFU) |
#define | CSI_CR_PIXEL_COUNTERS_SHIFT (0U) |
#define | CSI_CR_PIXEL_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR_PIXEL_COUNTERS_SHIFT)) & CSI_CR_PIXEL_COUNTERS_MASK) |
VERID - Version Identifier Register | |
#define | DAC_VERID_FEATURE_MASK (0xFFFFU) |
#define | DAC_VERID_FEATURE_SHIFT (0U) |
#define | DAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK) |
#define | DAC_VERID_MINOR_MASK (0xFF0000U) |
#define | DAC_VERID_MINOR_SHIFT (16U) |
#define | DAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK) |
#define | DAC_VERID_MAJOR_MASK (0xFF000000U) |
#define | DAC_VERID_MAJOR_SHIFT (24U) |
#define | DAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK) |
DATA - DAC Data Register | |
#define | DAC_DATA_DATA0_MASK (0xFFFU) |
#define | DAC_DATA_DATA0_SHIFT (0U) |
#define | DAC_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK) |
CR - DAC Status and Control Register | |
#define | DAC_CR_FULLF_MASK (0x1U) |
#define | DAC_CR_FULLF_SHIFT (0U) |
#define | DAC_CR_FULLF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK) |
#define | DAC_CR_NEMPTF_MASK (0x2U) |
#define | DAC_CR_NEMPTF_SHIFT (1U) |
#define | DAC_CR_NEMPTF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK) |
#define | DAC_CR_WMF_MASK (0x4U) |
#define | DAC_CR_WMF_SHIFT (2U) |
#define | DAC_CR_WMF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK) |
#define | DAC_CR_UDFF_MASK (0x8U) |
#define | DAC_CR_UDFF_SHIFT (3U) |
#define | DAC_CR_UDFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK) |
#define | DAC_CR_OVFF_MASK (0x10U) |
#define | DAC_CR_OVFF_SHIFT (4U) |
#define | DAC_CR_OVFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK) |
#define | DAC_CR_FULLIE_MASK (0x100U) |
#define | DAC_CR_FULLIE_SHIFT (8U) |
#define | DAC_CR_FULLIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK) |
#define | DAC_CR_EMPTIE_MASK (0x200U) |
#define | DAC_CR_EMPTIE_SHIFT (9U) |
#define | DAC_CR_EMPTIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK) |
#define | DAC_CR_WTMIE_MASK (0x400U) |
#define | DAC_CR_WTMIE_SHIFT (10U) |
#define | DAC_CR_WTMIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK) |
#define | DAC_CR_SWTRG_MASK (0x1000U) |
#define | DAC_CR_SWTRG_SHIFT (12U) |
#define | DAC_CR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK) |
#define | DAC_CR_TRGSEL_MASK (0x2000U) |
#define | DAC_CR_TRGSEL_SHIFT (13U) |
#define | DAC_CR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK) |
#define | DAC_CR_DACRFS_MASK (0x4000U) |
#define | DAC_CR_DACRFS_SHIFT (14U) |
#define | DAC_CR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK) |
#define | DAC_CR_DACEN_MASK (0x8000U) |
#define | DAC_CR_DACEN_SHIFT (15U) |
#define | DAC_CR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK) |
#define | DAC_CR_FIFOEN_MASK (0x10000U) |
#define | DAC_CR_FIFOEN_SHIFT (16U) |
#define | DAC_CR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK) |
#define | DAC_CR_SWMD_MASK (0x20000U) |
#define | DAC_CR_SWMD_SHIFT (17U) |
#define | DAC_CR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK) |
#define | DAC_CR_UVIE_MASK (0x40000U) |
#define | DAC_CR_UVIE_SHIFT (18U) |
#define | DAC_CR_UVIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK) |
#define | DAC_CR_FIFORST_MASK (0x200000U) |
#define | DAC_CR_FIFORST_SHIFT (21U) |
#define | DAC_CR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK) |
#define | DAC_CR_SWRST_MASK (0x400000U) |
#define | DAC_CR_SWRST_SHIFT (22U) |
#define | DAC_CR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK) |
#define | DAC_CR_DMAEN_MASK (0x800000U) |
#define | DAC_CR_DMAEN_SHIFT (23U) |
#define | DAC_CR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK) |
#define | DAC_CR_WML_MASK (0xFF000000U) |
#define | DAC_CR_WML_SHIFT (24U) |
#define | DAC_CR_WML(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK) |
PTR - DAC FIFO Pointer Register | |
#define | DAC_PTR_DACWFP_MASK (0xFFU) |
#define | DAC_PTR_DACWFP_SHIFT (0U) |
#define | DAC_PTR_DACWFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK) |
#define | DAC_PTR_DACRFP_MASK (0xFF0000U) |
#define | DAC_PTR_DACRFP_SHIFT (16U) |
#define | DAC_PTR_DACRFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK) |
CR2 - DAC Status and Control Register 2 | |
#define | DAC_CR2_BFEN_MASK (0x1U) |
#define | DAC_CR2_BFEN_SHIFT (0U) |
#define | DAC_CR2_BFEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK) |
#define | DAC_CR2_OEN_MASK (0x2U) |
#define | DAC_CR2_OEN_SHIFT (1U) |
#define | DAC_CR2_OEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK) |
#define | DAC_CR2_BFMS_MASK (0x4U) |
#define | DAC_CR2_BFMS_SHIFT (2U) |
#define | DAC_CR2_BFMS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK) |
#define | DAC_CR2_BFHS_MASK (0x8U) |
#define | DAC_CR2_BFHS_SHIFT (3U) |
#define | DAC_CR2_BFHS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK) |
#define | DAC_CR2_IREF2_MASK (0x10U) |
#define | DAC_CR2_IREF2_SHIFT (4U) |
#define | DAC_CR2_IREF2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK) |
#define | DAC_CR2_IREF1_MASK (0x20U) |
#define | DAC_CR2_IREF1_SHIFT (5U) |
#define | DAC_CR2_IREF1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK) |
#define | DAC_CR2_IREF_MASK (0x40U) |
#define | DAC_CR2_IREF_SHIFT (6U) |
#define | DAC_CR2_IREF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK) |
CTRL0 - DCDC Control Register 0 | |
#define | DCDC_CTRL0_ENABLE_MASK (0x1U) |
#define | DCDC_CTRL0_ENABLE_SHIFT (0U) |
#define | DCDC_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK) |
#define | DCDC_CTRL0_DIG_EN_MASK (0x2U) |
#define | DCDC_CTRL0_DIG_EN_SHIFT (1U) |
#define | DCDC_CTRL0_DIG_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK) |
#define | DCDC_CTRL0_STBY_EN_MASK (0x4U) |
#define | DCDC_CTRL0_STBY_EN_SHIFT (2U) |
#define | DCDC_CTRL0_STBY_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK) |
#define | DCDC_CTRL0_LP_MODE_EN_MASK (0x8U) |
#define | DCDC_CTRL0_LP_MODE_EN_SHIFT (3U) |
#define | DCDC_CTRL0_LP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK) |
#define | DCDC_CTRL0_STBY_LP_MODE_EN_MASK (0x10U) |
#define | DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT (4U) |
#define | DCDC_CTRL0_STBY_LP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK) |
#define | DCDC_CTRL0_ENABLE_DCDC_CNT_MASK (0x20U) |
#define | DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT (5U) |
#define | DCDC_CTRL0_ENABLE_DCDC_CNT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK) |
#define | DCDC_CTRL0_TRIM_HOLD_MASK (0x40U) |
#define | DCDC_CTRL0_TRIM_HOLD_SHIFT (6U) |
#define | DCDC_CTRL0_TRIM_HOLD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK) |
#define | DCDC_CTRL0_DEBUG_BITS_MASK (0x7FF80000U) |
#define | DCDC_CTRL0_DEBUG_BITS_SHIFT (19U) |
#define | DCDC_CTRL0_DEBUG_BITS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK) |
#define | DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) |
#define | DCDC_CTRL0_CONTROL_MODE_SHIFT (31U) |
#define | DCDC_CTRL0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK) |
CTRL1 - DCDC Control Register 1 | |
#define | DCDC_CTRL1_VDD1P8CTRL_TRG_MASK (0x1FU) |
#define | DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT (0U) |
#define | DCDC_CTRL1_VDD1P8CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK) |
#define | DCDC_CTRL1_VDD1P0CTRL_TRG_MASK (0x1F00U) |
#define | DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT (8U) |
#define | DCDC_CTRL1_VDD1P0CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK) |
#define | DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK (0x1F0000U) |
#define | DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT (16U) |
#define | DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK) |
#define | DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK (0x1F000000U) |
#define | DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT (24U) |
#define | DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK) |
REG0 - DCDC Register 0 | |
#define | DCDC_REG0_PWD_ZCD_MASK (0x1U) |
#define | DCDC_REG0_PWD_ZCD_SHIFT (0U) |
#define | DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) |
#define | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) |
#define | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) |
#define | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK) |
#define | DCDC_REG0_SEL_CLK_MASK (0x4U) |
#define | DCDC_REG0_SEL_CLK_SHIFT (2U) |
#define | DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK) |
#define | DCDC_REG0_PWD_OSC_INT_MASK (0x8U) |
#define | DCDC_REG0_PWD_OSC_INT_SHIFT (3U) |
#define | DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK) |
#define | DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U) |
#define | DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U) |
#define | DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK) |
#define | DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U) |
#define | DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U) |
#define | DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK) |
#define | DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U) |
#define | DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U) |
#define | DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK) |
#define | DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK (0x800U) |
#define | DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT (11U) |
#define | DCDC_REG0_PWD_CMP_DCDC_IN_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK) |
#define | DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK (0x10000U) |
#define | DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT (16U) |
#define | DCDC_REG0_PWD_HIGH_VDD1P8_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK) |
#define | DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK (0x20000U) |
#define | DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT (17U) |
#define | DCDC_REG0_PWD_HIGH_VDD1P0_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK) |
#define | DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U) |
#define | DCDC_REG0_LP_HIGH_HYS_SHIFT (21U) |
#define | DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK) |
#define | DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) |
#define | DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) |
#define | DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) |
#define | DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U) |
#define | DCDC_REG0_XTALOK_DISABLE_SHIFT (27U) |
#define | DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK) |
#define | DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U) |
#define | DCDC_REG0_XTAL_24M_OK_SHIFT (29U) |
#define | DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK) |
#define | DCDC_REG0_STS_DC_OK_MASK (0x80000000U) |
#define | DCDC_REG0_STS_DC_OK_SHIFT (31U) |
#define | DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) |
REG1 - DCDC Register 1 | |
#define | DCDC_REG1_DM_CTRL_MASK (0x8U) |
#define | DCDC_REG1_DM_CTRL_SHIFT (3U) |
#define | DCDC_REG1_DM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DM_CTRL_SHIFT)) & DCDC_REG1_DM_CTRL_MASK) |
#define | DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) |
#define | DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT (4U) |
#define | DCDC_REG1_RLOAD_REG_EN_LPSR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK) |
#define | DCDC_REG1_VBG_TRIM_MASK (0x7C0U) |
#define | DCDC_REG1_VBG_TRIM_SHIFT (6U) |
#define | DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) |
#define | DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x1800U) |
#define | DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (11U) |
#define | DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK) |
#define | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK (0x8000000U) |
#define | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT (27U) |
#define | DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK) |
#define | DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) |
#define | DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT (28U) |
#define | DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK) |
#define | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK (0x20000000U) |
#define | DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT (29U) |
#define | DCDC_REG1_LOOPCTRL_EN_CM_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK) |
#define | DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK (0x40000000U) |
#define | DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT (30U) |
#define | DCDC_REG1_LOOPCTRL_EN_DF_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK) |
REG2 - DCDC Register 2 | |
#define | DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) |
#define | DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) |
#define | DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) |
#define | DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU) |
#define | DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U) |
#define | DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK) |
#define | DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U) |
#define | DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U) |
#define | DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK) |
#define | DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U) |
#define | DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U) |
#define | DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK) |
#define | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U) |
#define | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U) |
#define | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK) |
#define | DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U) |
#define | DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U) |
#define | DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK) |
#define | DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK (0x8000U) |
#define | DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT (15U) |
#define | DCDC_REG2_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK) |
#define | DCDC_REG2_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U) |
#define | DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT (16U) |
#define | DCDC_REG2_BATTMONITOR_BATT_VAL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_BATTMONITOR_BATT_VAL_MASK) |
#define | DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) |
#define | DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) |
#define | DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) |
#define | DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK (0x40000000U) |
#define | DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT (30U) |
#define | DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT)) & DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK) |
REG3 - DCDC Register 3 | |
#define | DCDC_REG3_IN_BROWNOUT_MASK (0x4000U) |
#define | DCDC_REG3_IN_BROWNOUT_SHIFT (14U) |
#define | DCDC_REG3_IN_BROWNOUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK) |
#define | DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK (0x8000U) |
#define | DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT (15U) |
#define | DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK) |
#define | DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK (0x10000U) |
#define | DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT (16U) |
#define | DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK) |
#define | DCDC_REG3_OVERCUR_DETECT_OUT_MASK (0x20000U) |
#define | DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT (17U) |
#define | DCDC_REG3_OVERCUR_DETECT_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK) |
#define | DCDC_REG3_ENABLE_FF_MASK (0x40000U) |
#define | DCDC_REG3_ENABLE_FF_SHIFT (18U) |
#define | DCDC_REG3_ENABLE_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK) |
#define | DCDC_REG3_DISABLE_PULSE_SKIP_MASK (0x80000U) |
#define | DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT (19U) |
#define | DCDC_REG3_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK) |
#define | DCDC_REG3_DISABLE_IDLE_SKIP_MASK (0x100000U) |
#define | DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT (20U) |
#define | DCDC_REG3_DISABLE_IDLE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK) |
#define | DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK (0x200000U) |
#define | DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT (21U) |
#define | DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK) |
#define | DCDC_REG3_REG_FBK_SEL_MASK (0xC00000U) |
#define | DCDC_REG3_REG_FBK_SEL_SHIFT (22U) |
#define | DCDC_REG3_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_REG_FBK_SEL_SHIFT)) & DCDC_REG3_REG_FBK_SEL_MASK) |
#define | DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) |
#define | DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U) |
#define | DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK) |
#define | DCDC_REG3_MINPWR_HALF_FETS_MASK (0x4000000U) |
#define | DCDC_REG3_MINPWR_HALF_FETS_SHIFT (26U) |
#define | DCDC_REG3_MINPWR_HALF_FETS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_MINPWR_HALF_FETS_MASK) |
#define | DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U) |
#define | DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U) |
#define | DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK) |
#define | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) |
#define | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT (29U) |
#define | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK) |
#define | DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) |
#define | DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT (30U) |
#define | DCDC_REG3_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK) |
REG4 - DCDC Register 4 | |
#define | DCDC_REG4_ENABLE_SP_MASK (0xFFFFU) |
#define | DCDC_REG4_ENABLE_SP_SHIFT (0U) |
#define | DCDC_REG4_ENABLE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_ENABLE_SP_SHIFT)) & DCDC_REG4_ENABLE_SP_MASK) |
REG5 - DCDC Register 5 | |
#define | DCDC_REG5_DIG_EN_SP_MASK (0xFFFFU) |
#define | DCDC_REG5_DIG_EN_SP_SHIFT (0U) |
#define | DCDC_REG5_DIG_EN_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG5_DIG_EN_SP_SHIFT)) & DCDC_REG5_DIG_EN_SP_MASK) |
REG6 - DCDC Register 6 | |
#define | DCDC_REG6_LP_MODE_SP_MASK (0xFFFFU) |
#define | DCDC_REG6_LP_MODE_SP_SHIFT (0U) |
#define | DCDC_REG6_LP_MODE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_LP_MODE_SP_SHIFT)) & DCDC_REG6_LP_MODE_SP_MASK) |
REG7 - DCDC Register 7 | |
#define | DCDC_REG7_STBY_EN_SP_MASK (0xFFFFU) |
#define | DCDC_REG7_STBY_EN_SP_SHIFT (0U) |
#define | DCDC_REG7_STBY_EN_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_STBY_EN_SP_SHIFT)) & DCDC_REG7_STBY_EN_SP_MASK) |
REG7P - DCDC Register 7 plus | |
#define | DCDC_REG7P_STBY_LP_MODE_SP_MASK (0xFFFFU) |
#define | DCDC_REG7P_STBY_LP_MODE_SP_SHIFT (0U) |
#define | DCDC_REG7P_STBY_LP_MODE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7P_STBY_LP_MODE_SP_SHIFT)) & DCDC_REG7P_STBY_LP_MODE_SP_MASK) |
REG8 - DCDC Register 8 | |
#define | DCDC_REG8_ANA_TRG_SP0_MASK (0xFFFFFFFFU) |
#define | DCDC_REG8_ANA_TRG_SP0_SHIFT (0U) |
#define | DCDC_REG8_ANA_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG8_ANA_TRG_SP0_SHIFT)) & DCDC_REG8_ANA_TRG_SP0_MASK) |
REG9 - DCDC Register 9 | |
#define | DCDC_REG9_ANA_TRG_SP1_MASK (0xFFFFFFFFU) |
#define | DCDC_REG9_ANA_TRG_SP1_SHIFT (0U) |
#define | DCDC_REG9_ANA_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG9_ANA_TRG_SP1_SHIFT)) & DCDC_REG9_ANA_TRG_SP1_MASK) |
REG10 - DCDC Register 10 | |
#define | DCDC_REG10_ANA_TRG_SP2_MASK (0xFFFFFFFFU) |
#define | DCDC_REG10_ANA_TRG_SP2_SHIFT (0U) |
#define | DCDC_REG10_ANA_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG10_ANA_TRG_SP2_SHIFT)) & DCDC_REG10_ANA_TRG_SP2_MASK) |
REG11 - DCDC Register 11 | |
#define | DCDC_REG11_ANA_TRG_SP3_MASK (0xFFFFFFFFU) |
#define | DCDC_REG11_ANA_TRG_SP3_SHIFT (0U) |
#define | DCDC_REG11_ANA_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG11_ANA_TRG_SP3_SHIFT)) & DCDC_REG11_ANA_TRG_SP3_MASK) |
REG12 - DCDC Register 12 | |
#define | DCDC_REG12_DIG_TRG_SP0_MASK (0xFFFFFFFFU) |
#define | DCDC_REG12_DIG_TRG_SP0_SHIFT (0U) |
#define | DCDC_REG12_DIG_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG12_DIG_TRG_SP0_SHIFT)) & DCDC_REG12_DIG_TRG_SP0_MASK) |
REG13 - DCDC Register 13 | |
#define | DCDC_REG13_DIG_TRG_SP1_MASK (0xFFFFFFFFU) |
#define | DCDC_REG13_DIG_TRG_SP1_SHIFT (0U) |
#define | DCDC_REG13_DIG_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG13_DIG_TRG_SP1_SHIFT)) & DCDC_REG13_DIG_TRG_SP1_MASK) |
REG14 - DCDC Register 14 | |
#define | DCDC_REG14_DIG_TRG_SP2_MASK (0xFFFFFFFFU) |
#define | DCDC_REG14_DIG_TRG_SP2_SHIFT (0U) |
#define | DCDC_REG14_DIG_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG14_DIG_TRG_SP2_SHIFT)) & DCDC_REG14_DIG_TRG_SP2_MASK) |
REG15 - DCDC Register 15 | |
#define | DCDC_REG15_DIG_TRG_SP3_MASK (0xFFFFFFFFU) |
#define | DCDC_REG15_DIG_TRG_SP3_SHIFT (0U) |
#define | DCDC_REG15_DIG_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG15_DIG_TRG_SP3_SHIFT)) & DCDC_REG15_DIG_TRG_SP3_MASK) |
REG16 - DCDC Register 16 | |
#define | DCDC_REG16_ANA_STBY_TRG_SP0_MASK (0xFFFFFFFFU) |
#define | DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT (0U) |
#define | DCDC_REG16_ANA_STBY_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT)) & DCDC_REG16_ANA_STBY_TRG_SP0_MASK) |
REG17 - DCDC Register 17 | |
#define | DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) |
#define | DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT (0U) |
#define | DCDC_REG17_ANA_STBY_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK) |
REG18 - DCDC Register 18 | |
#define | DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) |
#define | DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT (0U) |
#define | DCDC_REG18_ANA_STBY_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK) |
REG19 - DCDC Register 19 | |
#define | DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) |
#define | DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT (0U) |
#define | DCDC_REG19_ANA_STBY_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK) |
REG20 - DCDC Register 20 | |
#define | DCDC_REG20_DIG_STBY_TRG_SP0_MASK (0xFFFFFFFFU) |
#define | DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT (0U) |
#define | DCDC_REG20_DIG_STBY_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT)) & DCDC_REG20_DIG_STBY_TRG_SP0_MASK) |
REG21 - DCDC Register 21 | |
#define | DCDC_REG21_DIG_STBY_TRG_SP1_MASK (0xFFFFFFFFU) |
#define | DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT (0U) |
#define | DCDC_REG21_DIG_STBY_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT)) & DCDC_REG21_DIG_STBY_TRG_SP1_MASK) |
REG22 - DCDC Register 22 | |
#define | DCDC_REG22_DIG_STBY_TRG_SP2_MASK (0xFFFFFFFFU) |
#define | DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT (0U) |
#define | DCDC_REG22_DIG_STBY_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT)) & DCDC_REG22_DIG_STBY_TRG_SP2_MASK) |
REG23 - DCDC Register 23 | |
#define | DCDC_REG23_DIG_STBY_TRG_SP3_MASK (0xFFFFFFFFU) |
#define | DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT (0U) |
#define | DCDC_REG23_DIG_STBY_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT)) & DCDC_REG23_DIG_STBY_TRG_SP3_MASK) |
REG24 - DCDC Register 24 | |
#define | DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) |
#define | DCDC_REG24_OK_COUNT_SHIFT (0U) |
#define | DCDC_REG24_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK) |
DCICC - DCIC Control Register | |
#define | DCIC_DCICC_IC_EN_MASK (0x1U) |
#define | DCIC_DCICC_IC_EN_SHIFT (0U) |
#define | DCIC_DCICC_IC_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_IC_EN_SHIFT)) & DCIC_DCICC_IC_EN_MASK) |
#define | DCIC_DCICC_DE_POL_MASK (0x10U) |
#define | DCIC_DCICC_DE_POL_SHIFT (4U) |
#define | DCIC_DCICC_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_DE_POL_SHIFT)) & DCIC_DCICC_DE_POL_MASK) |
#define | DCIC_DCICC_HSYNC_POL_MASK (0x20U) |
#define | DCIC_DCICC_HSYNC_POL_SHIFT (5U) |
#define | DCIC_DCICC_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_HSYNC_POL_SHIFT)) & DCIC_DCICC_HSYNC_POL_MASK) |
#define | DCIC_DCICC_VSYNC_POL_MASK (0x40U) |
#define | DCIC_DCICC_VSYNC_POL_SHIFT (6U) |
#define | DCIC_DCICC_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_VSYNC_POL_SHIFT)) & DCIC_DCICC_VSYNC_POL_MASK) |
#define | DCIC_DCICC_CLK_POL_MASK (0x80U) |
#define | DCIC_DCICC_CLK_POL_SHIFT (7U) |
#define | DCIC_DCICC_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_CLK_POL_SHIFT)) & DCIC_DCICC_CLK_POL_MASK) |
DCICIC - DCIC Interrupt Control Register | |
#define | DCIC_DCICIC_EI_MASK_MASK (0x1U) |
#define | DCIC_DCICIC_EI_MASK_SHIFT (0U) |
#define | DCIC_DCICIC_EI_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EI_MASK_SHIFT)) & DCIC_DCICIC_EI_MASK_MASK) |
#define | DCIC_DCICIC_FI_MASK_MASK (0x2U) |
#define | DCIC_DCICIC_FI_MASK_SHIFT (1U) |
#define | DCIC_DCICIC_FI_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FI_MASK_SHIFT)) & DCIC_DCICIC_FI_MASK_MASK) |
#define | DCIC_DCICIC_FREEZE_MASK_MASK (0x8U) |
#define | DCIC_DCICIC_FREEZE_MASK_SHIFT (3U) |
#define | DCIC_DCICIC_FREEZE_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FREEZE_MASK_SHIFT)) & DCIC_DCICIC_FREEZE_MASK_MASK) |
#define | DCIC_DCICIC_EXT_SIG_EN_MASK (0x10000U) |
#define | DCIC_DCICIC_EXT_SIG_EN_SHIFT (16U) |
#define | DCIC_DCICIC_EXT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EXT_SIG_EN_SHIFT)) & DCIC_DCICIC_EXT_SIG_EN_MASK) |
DCICS - DCIC Status Register | |
#define | DCIC_DCICS_ROI_MATCH_STAT_MASK (0xFFFFU) |
#define | DCIC_DCICS_ROI_MATCH_STAT_SHIFT (0U) |
#define | DCIC_DCICS_ROI_MATCH_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_ROI_MATCH_STAT_SHIFT)) & DCIC_DCICS_ROI_MATCH_STAT_MASK) |
#define | DCIC_DCICS_EI_STAT_MASK (0x10000U) |
#define | DCIC_DCICS_EI_STAT_SHIFT (16U) |
#define | DCIC_DCICS_EI_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_EI_STAT_SHIFT)) & DCIC_DCICS_EI_STAT_MASK) |
#define | DCIC_DCICS_FI_STAT_MASK (0x20000U) |
#define | DCIC_DCICS_FI_STAT_SHIFT (17U) |
#define | DCIC_DCICS_FI_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_FI_STAT_SHIFT)) & DCIC_DCICS_FI_STAT_MASK) |
DCICRC - DCIC ROI Config Register | |
#define | DCIC_DCICRC_START_OFFSET_X_MASK (0x1FFFU) |
#define | DCIC_DCICRC_START_OFFSET_X_SHIFT (0U) |
#define | DCIC_DCICRC_START_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_X_SHIFT)) & DCIC_DCICRC_START_OFFSET_X_MASK) |
#define | DCIC_DCICRC_START_OFFSET_Y_MASK (0xFFF0000U) |
#define | DCIC_DCICRC_START_OFFSET_Y_SHIFT (16U) |
#define | DCIC_DCICRC_START_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_Y_SHIFT)) & DCIC_DCICRC_START_OFFSET_Y_MASK) |
#define | DCIC_DCICRC_ROI_FREEZE_MASK (0x40000000U) |
#define | DCIC_DCICRC_ROI_FREEZE_SHIFT (30U) |
#define | DCIC_DCICRC_ROI_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_FREEZE_SHIFT)) & DCIC_DCICRC_ROI_FREEZE_MASK) |
#define | DCIC_DCICRC_ROI_EN_MASK (0x80000000U) |
#define | DCIC_DCICRC_ROI_EN_SHIFT (31U) |
#define | DCIC_DCICRC_ROI_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_EN_SHIFT)) & DCIC_DCICRC_ROI_EN_MASK) |
DCICRS - DCIC ROI Size Register | |
#define | DCIC_DCICRS_END_OFFSET_X_MASK (0x1FFFU) |
#define | DCIC_DCICRS_END_OFFSET_X_SHIFT (0U) |
#define | DCIC_DCICRS_END_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_X_SHIFT)) & DCIC_DCICRS_END_OFFSET_X_MASK) |
#define | DCIC_DCICRS_END_OFFSET_Y_MASK (0xFFF0000U) |
#define | DCIC_DCICRS_END_OFFSET_Y_SHIFT (16U) |
#define | DCIC_DCICRS_END_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_Y_SHIFT)) & DCIC_DCICRS_END_OFFSET_Y_MASK) |
DCICRRS - DCIC ROI Reference Signature Register | |
#define | DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK (0xFFFFFFFFU) |
#define | DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT (0U) |
#define | DCIC_DCICRRS_REFERENCE_SIGNATURE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT)) & DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK) |
DCICRCS - DCIC ROI Calculated Signature Register | |
#define | DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK (0xFFFFFFFFU) |
#define | DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT (0U) |
#define | DCIC_DCICRCS_CALCULATED_SIGNATURE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT)) & DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK) |
CR - Control | |
#define | DMA_CR_EDBG_MASK (0x2U) |
#define | DMA_CR_EDBG_SHIFT (1U) |
#define | DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) |
#define | DMA_CR_ERCA_MASK (0x4U) |
#define | DMA_CR_ERCA_SHIFT (2U) |
#define | DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) |
#define | DMA_CR_ERGA_MASK (0x8U) |
#define | DMA_CR_ERGA_SHIFT (3U) |
#define | DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) |
#define | DMA_CR_HOE_MASK (0x10U) |
#define | DMA_CR_HOE_SHIFT (4U) |
#define | DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) |
#define | DMA_CR_HALT_MASK (0x20U) |
#define | DMA_CR_HALT_SHIFT (5U) |
#define | DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) |
#define | DMA_CR_CLM_MASK (0x40U) |
#define | DMA_CR_CLM_SHIFT (6U) |
#define | DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) |
#define | DMA_CR_EMLM_MASK (0x80U) |
#define | DMA_CR_EMLM_SHIFT (7U) |
#define | DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) |
#define | DMA_CR_GRP0PRI_MASK (0x100U) |
#define | DMA_CR_GRP0PRI_SHIFT (8U) |
#define | DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) |
#define | DMA_CR_GRP1PRI_MASK (0x400U) |
#define | DMA_CR_GRP1PRI_SHIFT (10U) |
#define | DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) |
#define | DMA_CR_ECX_MASK (0x10000U) |
#define | DMA_CR_ECX_SHIFT (16U) |
#define | DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) |
#define | DMA_CR_CX_MASK (0x20000U) |
#define | DMA_CR_CX_SHIFT (17U) |
#define | DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) |
#define | DMA_CR_VERSION_MASK (0x7F000000U) |
#define | DMA_CR_VERSION_SHIFT (24U) |
#define | DMA_CR_VERSION(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK) |
#define | DMA_CR_ACTIVE_MASK (0x80000000U) |
#define | DMA_CR_ACTIVE_SHIFT (31U) |
#define | DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) |
#define | LPSPI_CR_MEN_MASK (0x1U) |
#define | LPSPI_CR_MEN_SHIFT (0U) |
#define | LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) |
#define | LPSPI_CR_RST_MASK (0x2U) |
#define | LPSPI_CR_RST_SHIFT (1U) |
#define | LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) |
#define | LPSPI_CR_DOZEN_MASK (0x4U) |
#define | LPSPI_CR_DOZEN_SHIFT (2U) |
#define | LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) |
#define | LPSPI_CR_DBGEN_MASK (0x8U) |
#define | LPSPI_CR_DBGEN_SHIFT (3U) |
#define | LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) |
#define | LPSPI_CR_RTF_MASK (0x100U) |
#define | LPSPI_CR_RTF_SHIFT (8U) |
#define | LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) |
#define | LPSPI_CR_RRF_MASK (0x200U) |
#define | LPSPI_CR_RRF_SHIFT (9U) |
#define | LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) |
ES - Error Status | |
#define | DMA_ES_DBE_MASK (0x1U) |
#define | DMA_ES_DBE_SHIFT (0U) |
#define | DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) |
#define | DMA_ES_SBE_MASK (0x2U) |
#define | DMA_ES_SBE_SHIFT (1U) |
#define | DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) |
#define | DMA_ES_SGE_MASK (0x4U) |
#define | DMA_ES_SGE_SHIFT (2U) |
#define | DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) |
#define | DMA_ES_NCE_MASK (0x8U) |
#define | DMA_ES_NCE_SHIFT (3U) |
#define | DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) |
#define | DMA_ES_DOE_MASK (0x10U) |
#define | DMA_ES_DOE_SHIFT (4U) |
#define | DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) |
#define | DMA_ES_DAE_MASK (0x20U) |
#define | DMA_ES_DAE_SHIFT (5U) |
#define | DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) |
#define | DMA_ES_SOE_MASK (0x40U) |
#define | DMA_ES_SOE_SHIFT (6U) |
#define | DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) |
#define | DMA_ES_SAE_MASK (0x80U) |
#define | DMA_ES_SAE_SHIFT (7U) |
#define | DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) |
#define | DMA_ES_ERRCHN_MASK (0x1F00U) |
#define | DMA_ES_ERRCHN_SHIFT (8U) |
#define | DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) |
#define | DMA_ES_CPE_MASK (0x4000U) |
#define | DMA_ES_CPE_SHIFT (14U) |
#define | DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) |
#define | DMA_ES_GPE_MASK (0x8000U) |
#define | DMA_ES_GPE_SHIFT (15U) |
#define | DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) |
#define | DMA_ES_ECX_MASK (0x10000U) |
#define | DMA_ES_ECX_SHIFT (16U) |
#define | DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) |
#define | DMA_ES_VLD_MASK (0x80000000U) |
#define | DMA_ES_VLD_SHIFT (31U) |
#define | DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) |
ERQ - Enable Request | |
#define | DMA_ERQ_ERQ0_MASK (0x1U) |
#define | DMA_ERQ_ERQ0_SHIFT (0U) |
#define | DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) |
#define | DMA_ERQ_ERQ1_MASK (0x2U) |
#define | DMA_ERQ_ERQ1_SHIFT (1U) |
#define | DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) |
#define | DMA_ERQ_ERQ2_MASK (0x4U) |
#define | DMA_ERQ_ERQ2_SHIFT (2U) |
#define | DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) |
#define | DMA_ERQ_ERQ3_MASK (0x8U) |
#define | DMA_ERQ_ERQ3_SHIFT (3U) |
#define | DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) |
#define | DMA_ERQ_ERQ4_MASK (0x10U) |
#define | DMA_ERQ_ERQ4_SHIFT (4U) |
#define | DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) |
#define | DMA_ERQ_ERQ5_MASK (0x20U) |
#define | DMA_ERQ_ERQ5_SHIFT (5U) |
#define | DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) |
#define | DMA_ERQ_ERQ6_MASK (0x40U) |
#define | DMA_ERQ_ERQ6_SHIFT (6U) |
#define | DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) |
#define | DMA_ERQ_ERQ7_MASK (0x80U) |
#define | DMA_ERQ_ERQ7_SHIFT (7U) |
#define | DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) |
#define | DMA_ERQ_ERQ8_MASK (0x100U) |
#define | DMA_ERQ_ERQ8_SHIFT (8U) |
#define | DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) |
#define | DMA_ERQ_ERQ9_MASK (0x200U) |
#define | DMA_ERQ_ERQ9_SHIFT (9U) |
#define | DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) |
#define | DMA_ERQ_ERQ10_MASK (0x400U) |
#define | DMA_ERQ_ERQ10_SHIFT (10U) |
#define | DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) |
#define | DMA_ERQ_ERQ11_MASK (0x800U) |
#define | DMA_ERQ_ERQ11_SHIFT (11U) |
#define | DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) |
#define | DMA_ERQ_ERQ12_MASK (0x1000U) |
#define | DMA_ERQ_ERQ12_SHIFT (12U) |
#define | DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) |
#define | DMA_ERQ_ERQ13_MASK (0x2000U) |
#define | DMA_ERQ_ERQ13_SHIFT (13U) |
#define | DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) |
#define | DMA_ERQ_ERQ14_MASK (0x4000U) |
#define | DMA_ERQ_ERQ14_SHIFT (14U) |
#define | DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) |
#define | DMA_ERQ_ERQ15_MASK (0x8000U) |
#define | DMA_ERQ_ERQ15_SHIFT (15U) |
#define | DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) |
#define | DMA_ERQ_ERQ16_MASK (0x10000U) |
#define | DMA_ERQ_ERQ16_SHIFT (16U) |
#define | DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) |
#define | DMA_ERQ_ERQ17_MASK (0x20000U) |
#define | DMA_ERQ_ERQ17_SHIFT (17U) |
#define | DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) |
#define | DMA_ERQ_ERQ18_MASK (0x40000U) |
#define | DMA_ERQ_ERQ18_SHIFT (18U) |
#define | DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) |
#define | DMA_ERQ_ERQ19_MASK (0x80000U) |
#define | DMA_ERQ_ERQ19_SHIFT (19U) |
#define | DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) |
#define | DMA_ERQ_ERQ20_MASK (0x100000U) |
#define | DMA_ERQ_ERQ20_SHIFT (20U) |
#define | DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) |
#define | DMA_ERQ_ERQ21_MASK (0x200000U) |
#define | DMA_ERQ_ERQ21_SHIFT (21U) |
#define | DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) |
#define | DMA_ERQ_ERQ22_MASK (0x400000U) |
#define | DMA_ERQ_ERQ22_SHIFT (22U) |
#define | DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) |
#define | DMA_ERQ_ERQ23_MASK (0x800000U) |
#define | DMA_ERQ_ERQ23_SHIFT (23U) |
#define | DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) |
#define | DMA_ERQ_ERQ24_MASK (0x1000000U) |
#define | DMA_ERQ_ERQ24_SHIFT (24U) |
#define | DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) |
#define | DMA_ERQ_ERQ25_MASK (0x2000000U) |
#define | DMA_ERQ_ERQ25_SHIFT (25U) |
#define | DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) |
#define | DMA_ERQ_ERQ26_MASK (0x4000000U) |
#define | DMA_ERQ_ERQ26_SHIFT (26U) |
#define | DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) |
#define | DMA_ERQ_ERQ27_MASK (0x8000000U) |
#define | DMA_ERQ_ERQ27_SHIFT (27U) |
#define | DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) |
#define | DMA_ERQ_ERQ28_MASK (0x10000000U) |
#define | DMA_ERQ_ERQ28_SHIFT (28U) |
#define | DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) |
#define | DMA_ERQ_ERQ29_MASK (0x20000000U) |
#define | DMA_ERQ_ERQ29_SHIFT (29U) |
#define | DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) |
#define | DMA_ERQ_ERQ30_MASK (0x40000000U) |
#define | DMA_ERQ_ERQ30_SHIFT (30U) |
#define | DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) |
#define | DMA_ERQ_ERQ31_MASK (0x80000000U) |
#define | DMA_ERQ_ERQ31_SHIFT (31U) |
#define | DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) |
EEI - Enable Error Interrupt | |
#define | DMA_EEI_EEI0_MASK (0x1U) |
#define | DMA_EEI_EEI0_SHIFT (0U) |
#define | DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) |
#define | DMA_EEI_EEI1_MASK (0x2U) |
#define | DMA_EEI_EEI1_SHIFT (1U) |
#define | DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) |
#define | DMA_EEI_EEI2_MASK (0x4U) |
#define | DMA_EEI_EEI2_SHIFT (2U) |
#define | DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) |
#define | DMA_EEI_EEI3_MASK (0x8U) |
#define | DMA_EEI_EEI3_SHIFT (3U) |
#define | DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) |
#define | DMA_EEI_EEI4_MASK (0x10U) |
#define | DMA_EEI_EEI4_SHIFT (4U) |
#define | DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) |
#define | DMA_EEI_EEI5_MASK (0x20U) |
#define | DMA_EEI_EEI5_SHIFT (5U) |
#define | DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) |
#define | DMA_EEI_EEI6_MASK (0x40U) |
#define | DMA_EEI_EEI6_SHIFT (6U) |
#define | DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) |
#define | DMA_EEI_EEI7_MASK (0x80U) |
#define | DMA_EEI_EEI7_SHIFT (7U) |
#define | DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) |
#define | DMA_EEI_EEI8_MASK (0x100U) |
#define | DMA_EEI_EEI8_SHIFT (8U) |
#define | DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) |
#define | DMA_EEI_EEI9_MASK (0x200U) |
#define | DMA_EEI_EEI9_SHIFT (9U) |
#define | DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) |
#define | DMA_EEI_EEI10_MASK (0x400U) |
#define | DMA_EEI_EEI10_SHIFT (10U) |
#define | DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) |
#define | DMA_EEI_EEI11_MASK (0x800U) |
#define | DMA_EEI_EEI11_SHIFT (11U) |
#define | DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) |
#define | DMA_EEI_EEI12_MASK (0x1000U) |
#define | DMA_EEI_EEI12_SHIFT (12U) |
#define | DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) |
#define | DMA_EEI_EEI13_MASK (0x2000U) |
#define | DMA_EEI_EEI13_SHIFT (13U) |
#define | DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) |
#define | DMA_EEI_EEI14_MASK (0x4000U) |
#define | DMA_EEI_EEI14_SHIFT (14U) |
#define | DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) |
#define | DMA_EEI_EEI15_MASK (0x8000U) |
#define | DMA_EEI_EEI15_SHIFT (15U) |
#define | DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) |
#define | DMA_EEI_EEI16_MASK (0x10000U) |
#define | DMA_EEI_EEI16_SHIFT (16U) |
#define | DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) |
#define | DMA_EEI_EEI17_MASK (0x20000U) |
#define | DMA_EEI_EEI17_SHIFT (17U) |
#define | DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) |
#define | DMA_EEI_EEI18_MASK (0x40000U) |
#define | DMA_EEI_EEI18_SHIFT (18U) |
#define | DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) |
#define | DMA_EEI_EEI19_MASK (0x80000U) |
#define | DMA_EEI_EEI19_SHIFT (19U) |
#define | DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) |
#define | DMA_EEI_EEI20_MASK (0x100000U) |
#define | DMA_EEI_EEI20_SHIFT (20U) |
#define | DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) |
#define | DMA_EEI_EEI21_MASK (0x200000U) |
#define | DMA_EEI_EEI21_SHIFT (21U) |
#define | DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) |
#define | DMA_EEI_EEI22_MASK (0x400000U) |
#define | DMA_EEI_EEI22_SHIFT (22U) |
#define | DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) |
#define | DMA_EEI_EEI23_MASK (0x800000U) |
#define | DMA_EEI_EEI23_SHIFT (23U) |
#define | DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) |
#define | DMA_EEI_EEI24_MASK (0x1000000U) |
#define | DMA_EEI_EEI24_SHIFT (24U) |
#define | DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) |
#define | DMA_EEI_EEI25_MASK (0x2000000U) |
#define | DMA_EEI_EEI25_SHIFT (25U) |
#define | DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) |
#define | DMA_EEI_EEI26_MASK (0x4000000U) |
#define | DMA_EEI_EEI26_SHIFT (26U) |
#define | DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) |
#define | DMA_EEI_EEI27_MASK (0x8000000U) |
#define | DMA_EEI_EEI27_SHIFT (27U) |
#define | DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) |
#define | DMA_EEI_EEI28_MASK (0x10000000U) |
#define | DMA_EEI_EEI28_SHIFT (28U) |
#define | DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) |
#define | DMA_EEI_EEI29_MASK (0x20000000U) |
#define | DMA_EEI_EEI29_SHIFT (29U) |
#define | DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) |
#define | DMA_EEI_EEI30_MASK (0x40000000U) |
#define | DMA_EEI_EEI30_SHIFT (30U) |
#define | DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) |
#define | DMA_EEI_EEI31_MASK (0x80000000U) |
#define | DMA_EEI_EEI31_SHIFT (31U) |
#define | DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) |
CEEI - Clear Enable Error Interrupt | |
#define | DMA_CEEI_CEEI_MASK (0x1FU) |
#define | DMA_CEEI_CEEI_SHIFT (0U) |
#define | DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) |
#define | DMA_CEEI_CAEE_MASK (0x40U) |
#define | DMA_CEEI_CAEE_SHIFT (6U) |
#define | DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) |
#define | DMA_CEEI_NOP_MASK (0x80U) |
#define | DMA_CEEI_NOP_SHIFT (7U) |
#define | DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) |
SEEI - Set Enable Error Interrupt | |
#define | DMA_SEEI_SEEI_MASK (0x1FU) |
#define | DMA_SEEI_SEEI_SHIFT (0U) |
#define | DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) |
#define | DMA_SEEI_SAEE_MASK (0x40U) |
#define | DMA_SEEI_SAEE_SHIFT (6U) |
#define | DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) |
#define | DMA_SEEI_NOP_MASK (0x80U) |
#define | DMA_SEEI_NOP_SHIFT (7U) |
#define | DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) |
CERQ - Clear Enable Request | |
#define | DMA_CERQ_CERQ_MASK (0x1FU) |
#define | DMA_CERQ_CERQ_SHIFT (0U) |
#define | DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) |
#define | DMA_CERQ_CAER_MASK (0x40U) |
#define | DMA_CERQ_CAER_SHIFT (6U) |
#define | DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) |
#define | DMA_CERQ_NOP_MASK (0x80U) |
#define | DMA_CERQ_NOP_SHIFT (7U) |
#define | DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) |
SERQ - Set Enable Request | |
#define | DMA_SERQ_SERQ_MASK (0x1FU) |
#define | DMA_SERQ_SERQ_SHIFT (0U) |
#define | DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) |
#define | DMA_SERQ_SAER_MASK (0x40U) |
#define | DMA_SERQ_SAER_SHIFT (6U) |
#define | DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) |
#define | DMA_SERQ_NOP_MASK (0x80U) |
#define | DMA_SERQ_NOP_SHIFT (7U) |
#define | DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) |
CDNE - Clear DONE Status Bit | |
#define | DMA_CDNE_CDNE_MASK (0x1FU) |
#define | DMA_CDNE_CDNE_SHIFT (0U) |
#define | DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) |
#define | DMA_CDNE_CADN_MASK (0x40U) |
#define | DMA_CDNE_CADN_SHIFT (6U) |
#define | DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) |
#define | DMA_CDNE_NOP_MASK (0x80U) |
#define | DMA_CDNE_NOP_SHIFT (7U) |
#define | DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) |
SSRT - Set START Bit | |
#define | DMA_SSRT_SSRT_MASK (0x1FU) |
#define | DMA_SSRT_SSRT_SHIFT (0U) |
#define | DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) |
#define | DMA_SSRT_SAST_MASK (0x40U) |
#define | DMA_SSRT_SAST_SHIFT (6U) |
#define | DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) |
#define | DMA_SSRT_NOP_MASK (0x80U) |
#define | DMA_SSRT_NOP_SHIFT (7U) |
#define | DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) |
CERR - Clear Error | |
#define | DMA_CERR_CERR_MASK (0x1FU) |
#define | DMA_CERR_CERR_SHIFT (0U) |
#define | DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) |
#define | DMA_CERR_CAEI_MASK (0x40U) |
#define | DMA_CERR_CAEI_SHIFT (6U) |
#define | DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) |
#define | DMA_CERR_NOP_MASK (0x80U) |
#define | DMA_CERR_NOP_SHIFT (7U) |
#define | DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) |
CINT - Clear Interrupt Request | |
#define | DMA_CINT_CINT_MASK (0x1FU) |
#define | DMA_CINT_CINT_SHIFT (0U) |
#define | DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) |
#define | DMA_CINT_CAIR_MASK (0x40U) |
#define | DMA_CINT_CAIR_SHIFT (6U) |
#define | DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) |
#define | DMA_CINT_NOP_MASK (0x80U) |
#define | DMA_CINT_NOP_SHIFT (7U) |
#define | DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) |
INT - Interrupt Request | |
#define | DMA_INT_INT0_MASK (0x1U) |
#define | DMA_INT_INT0_SHIFT (0U) |
#define | DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) |
#define | DMA_INT_INT1_MASK (0x2U) |
#define | DMA_INT_INT1_SHIFT (1U) |
#define | DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) |
#define | DMA_INT_INT2_MASK (0x4U) |
#define | DMA_INT_INT2_SHIFT (2U) |
#define | DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) |
#define | DMA_INT_INT3_MASK (0x8U) |
#define | DMA_INT_INT3_SHIFT (3U) |
#define | DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) |
#define | DMA_INT_INT4_MASK (0x10U) |
#define | DMA_INT_INT4_SHIFT (4U) |
#define | DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) |
#define | DMA_INT_INT5_MASK (0x20U) |
#define | DMA_INT_INT5_SHIFT (5U) |
#define | DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) |
#define | DMA_INT_INT6_MASK (0x40U) |
#define | DMA_INT_INT6_SHIFT (6U) |
#define | DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) |
#define | DMA_INT_INT7_MASK (0x80U) |
#define | DMA_INT_INT7_SHIFT (7U) |
#define | DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) |
#define | DMA_INT_INT8_MASK (0x100U) |
#define | DMA_INT_INT8_SHIFT (8U) |
#define | DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) |
#define | DMA_INT_INT9_MASK (0x200U) |
#define | DMA_INT_INT9_SHIFT (9U) |
#define | DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) |
#define | DMA_INT_INT10_MASK (0x400U) |
#define | DMA_INT_INT10_SHIFT (10U) |
#define | DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) |
#define | DMA_INT_INT11_MASK (0x800U) |
#define | DMA_INT_INT11_SHIFT (11U) |
#define | DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) |
#define | DMA_INT_INT12_MASK (0x1000U) |
#define | DMA_INT_INT12_SHIFT (12U) |
#define | DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) |
#define | DMA_INT_INT13_MASK (0x2000U) |
#define | DMA_INT_INT13_SHIFT (13U) |
#define | DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) |
#define | DMA_INT_INT14_MASK (0x4000U) |
#define | DMA_INT_INT14_SHIFT (14U) |
#define | DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) |
#define | DMA_INT_INT15_MASK (0x8000U) |
#define | DMA_INT_INT15_SHIFT (15U) |
#define | DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) |
#define | DMA_INT_INT16_MASK (0x10000U) |
#define | DMA_INT_INT16_SHIFT (16U) |
#define | DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) |
#define | DMA_INT_INT17_MASK (0x20000U) |
#define | DMA_INT_INT17_SHIFT (17U) |
#define | DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) |
#define | DMA_INT_INT18_MASK (0x40000U) |
#define | DMA_INT_INT18_SHIFT (18U) |
#define | DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) |
#define | DMA_INT_INT19_MASK (0x80000U) |
#define | DMA_INT_INT19_SHIFT (19U) |
#define | DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) |
#define | DMA_INT_INT20_MASK (0x100000U) |
#define | DMA_INT_INT20_SHIFT (20U) |
#define | DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) |
#define | DMA_INT_INT21_MASK (0x200000U) |
#define | DMA_INT_INT21_SHIFT (21U) |
#define | DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) |
#define | DMA_INT_INT22_MASK (0x400000U) |
#define | DMA_INT_INT22_SHIFT (22U) |
#define | DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) |
#define | DMA_INT_INT23_MASK (0x800000U) |
#define | DMA_INT_INT23_SHIFT (23U) |
#define | DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) |
#define | DMA_INT_INT24_MASK (0x1000000U) |
#define | DMA_INT_INT24_SHIFT (24U) |
#define | DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) |
#define | DMA_INT_INT25_MASK (0x2000000U) |
#define | DMA_INT_INT25_SHIFT (25U) |
#define | DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) |
#define | DMA_INT_INT26_MASK (0x4000000U) |
#define | DMA_INT_INT26_SHIFT (26U) |
#define | DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) |
#define | DMA_INT_INT27_MASK (0x8000000U) |
#define | DMA_INT_INT27_SHIFT (27U) |
#define | DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) |
#define | DMA_INT_INT28_MASK (0x10000000U) |
#define | DMA_INT_INT28_SHIFT (28U) |
#define | DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) |
#define | DMA_INT_INT29_MASK (0x20000000U) |
#define | DMA_INT_INT29_SHIFT (29U) |
#define | DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) |
#define | DMA_INT_INT30_MASK (0x40000000U) |
#define | DMA_INT_INT30_SHIFT (30U) |
#define | DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) |
#define | DMA_INT_INT31_MASK (0x80000000U) |
#define | DMA_INT_INT31_SHIFT (31U) |
#define | DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) |
ERR - Error | |
#define | DMA_ERR_ERR0_MASK (0x1U) |
#define | DMA_ERR_ERR0_SHIFT (0U) |
#define | DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) |
#define | DMA_ERR_ERR1_MASK (0x2U) |
#define | DMA_ERR_ERR1_SHIFT (1U) |
#define | DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) |
#define | DMA_ERR_ERR2_MASK (0x4U) |
#define | DMA_ERR_ERR2_SHIFT (2U) |
#define | DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) |
#define | DMA_ERR_ERR3_MASK (0x8U) |
#define | DMA_ERR_ERR3_SHIFT (3U) |
#define | DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) |
#define | DMA_ERR_ERR4_MASK (0x10U) |
#define | DMA_ERR_ERR4_SHIFT (4U) |
#define | DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) |
#define | DMA_ERR_ERR5_MASK (0x20U) |
#define | DMA_ERR_ERR5_SHIFT (5U) |
#define | DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) |
#define | DMA_ERR_ERR6_MASK (0x40U) |
#define | DMA_ERR_ERR6_SHIFT (6U) |
#define | DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) |
#define | DMA_ERR_ERR7_MASK (0x80U) |
#define | DMA_ERR_ERR7_SHIFT (7U) |
#define | DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) |
#define | DMA_ERR_ERR8_MASK (0x100U) |
#define | DMA_ERR_ERR8_SHIFT (8U) |
#define | DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) |
#define | DMA_ERR_ERR9_MASK (0x200U) |
#define | DMA_ERR_ERR9_SHIFT (9U) |
#define | DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) |
#define | DMA_ERR_ERR10_MASK (0x400U) |
#define | DMA_ERR_ERR10_SHIFT (10U) |
#define | DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) |
#define | DMA_ERR_ERR11_MASK (0x800U) |
#define | DMA_ERR_ERR11_SHIFT (11U) |
#define | DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) |
#define | DMA_ERR_ERR12_MASK (0x1000U) |
#define | DMA_ERR_ERR12_SHIFT (12U) |
#define | DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) |
#define | DMA_ERR_ERR13_MASK (0x2000U) |
#define | DMA_ERR_ERR13_SHIFT (13U) |
#define | DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) |
#define | DMA_ERR_ERR14_MASK (0x4000U) |
#define | DMA_ERR_ERR14_SHIFT (14U) |
#define | DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) |
#define | DMA_ERR_ERR15_MASK (0x8000U) |
#define | DMA_ERR_ERR15_SHIFT (15U) |
#define | DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) |
#define | DMA_ERR_ERR16_MASK (0x10000U) |
#define | DMA_ERR_ERR16_SHIFT (16U) |
#define | DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) |
#define | DMA_ERR_ERR17_MASK (0x20000U) |
#define | DMA_ERR_ERR17_SHIFT (17U) |
#define | DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) |
#define | DMA_ERR_ERR18_MASK (0x40000U) |
#define | DMA_ERR_ERR18_SHIFT (18U) |
#define | DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) |
#define | DMA_ERR_ERR19_MASK (0x80000U) |
#define | DMA_ERR_ERR19_SHIFT (19U) |
#define | DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) |
#define | DMA_ERR_ERR20_MASK (0x100000U) |
#define | DMA_ERR_ERR20_SHIFT (20U) |
#define | DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) |
#define | DMA_ERR_ERR21_MASK (0x200000U) |
#define | DMA_ERR_ERR21_SHIFT (21U) |
#define | DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) |
#define | DMA_ERR_ERR22_MASK (0x400000U) |
#define | DMA_ERR_ERR22_SHIFT (22U) |
#define | DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) |
#define | DMA_ERR_ERR23_MASK (0x800000U) |
#define | DMA_ERR_ERR23_SHIFT (23U) |
#define | DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) |
#define | DMA_ERR_ERR24_MASK (0x1000000U) |
#define | DMA_ERR_ERR24_SHIFT (24U) |
#define | DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) |
#define | DMA_ERR_ERR25_MASK (0x2000000U) |
#define | DMA_ERR_ERR25_SHIFT (25U) |
#define | DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) |
#define | DMA_ERR_ERR26_MASK (0x4000000U) |
#define | DMA_ERR_ERR26_SHIFT (26U) |
#define | DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) |
#define | DMA_ERR_ERR27_MASK (0x8000000U) |
#define | DMA_ERR_ERR27_SHIFT (27U) |
#define | DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) |
#define | DMA_ERR_ERR28_MASK (0x10000000U) |
#define | DMA_ERR_ERR28_SHIFT (28U) |
#define | DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) |
#define | DMA_ERR_ERR29_MASK (0x20000000U) |
#define | DMA_ERR_ERR29_SHIFT (29U) |
#define | DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) |
#define | DMA_ERR_ERR30_MASK (0x40000000U) |
#define | DMA_ERR_ERR30_SHIFT (30U) |
#define | DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) |
#define | DMA_ERR_ERR31_MASK (0x80000000U) |
#define | DMA_ERR_ERR31_SHIFT (31U) |
#define | DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) |
HRS - Hardware Request Status | |
#define | DMA_HRS_HRS0_MASK (0x1U) |
#define | DMA_HRS_HRS0_SHIFT (0U) |
#define | DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) |
#define | DMA_HRS_HRS1_MASK (0x2U) |
#define | DMA_HRS_HRS1_SHIFT (1U) |
#define | DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) |
#define | DMA_HRS_HRS2_MASK (0x4U) |
#define | DMA_HRS_HRS2_SHIFT (2U) |
#define | DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) |
#define | DMA_HRS_HRS3_MASK (0x8U) |
#define | DMA_HRS_HRS3_SHIFT (3U) |
#define | DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) |
#define | DMA_HRS_HRS4_MASK (0x10U) |
#define | DMA_HRS_HRS4_SHIFT (4U) |
#define | DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) |
#define | DMA_HRS_HRS5_MASK (0x20U) |
#define | DMA_HRS_HRS5_SHIFT (5U) |
#define | DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) |
#define | DMA_HRS_HRS6_MASK (0x40U) |
#define | DMA_HRS_HRS6_SHIFT (6U) |
#define | DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) |
#define | DMA_HRS_HRS7_MASK (0x80U) |
#define | DMA_HRS_HRS7_SHIFT (7U) |
#define | DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) |
#define | DMA_HRS_HRS8_MASK (0x100U) |
#define | DMA_HRS_HRS8_SHIFT (8U) |
#define | DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) |
#define | DMA_HRS_HRS9_MASK (0x200U) |
#define | DMA_HRS_HRS9_SHIFT (9U) |
#define | DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) |
#define | DMA_HRS_HRS10_MASK (0x400U) |
#define | DMA_HRS_HRS10_SHIFT (10U) |
#define | DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) |
#define | DMA_HRS_HRS11_MASK (0x800U) |
#define | DMA_HRS_HRS11_SHIFT (11U) |
#define | DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) |
#define | DMA_HRS_HRS12_MASK (0x1000U) |
#define | DMA_HRS_HRS12_SHIFT (12U) |
#define | DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) |
#define | DMA_HRS_HRS13_MASK (0x2000U) |
#define | DMA_HRS_HRS13_SHIFT (13U) |
#define | DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) |
#define | DMA_HRS_HRS14_MASK (0x4000U) |
#define | DMA_HRS_HRS14_SHIFT (14U) |
#define | DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) |
#define | DMA_HRS_HRS15_MASK (0x8000U) |
#define | DMA_HRS_HRS15_SHIFT (15U) |
#define | DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) |
#define | DMA_HRS_HRS16_MASK (0x10000U) |
#define | DMA_HRS_HRS16_SHIFT (16U) |
#define | DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) |
#define | DMA_HRS_HRS17_MASK (0x20000U) |
#define | DMA_HRS_HRS17_SHIFT (17U) |
#define | DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) |
#define | DMA_HRS_HRS18_MASK (0x40000U) |
#define | DMA_HRS_HRS18_SHIFT (18U) |
#define | DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) |
#define | DMA_HRS_HRS19_MASK (0x80000U) |
#define | DMA_HRS_HRS19_SHIFT (19U) |
#define | DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) |
#define | DMA_HRS_HRS20_MASK (0x100000U) |
#define | DMA_HRS_HRS20_SHIFT (20U) |
#define | DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) |
#define | DMA_HRS_HRS21_MASK (0x200000U) |
#define | DMA_HRS_HRS21_SHIFT (21U) |
#define | DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) |
#define | DMA_HRS_HRS22_MASK (0x400000U) |
#define | DMA_HRS_HRS22_SHIFT (22U) |
#define | DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) |
#define | DMA_HRS_HRS23_MASK (0x800000U) |
#define | DMA_HRS_HRS23_SHIFT (23U) |
#define | DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) |
#define | DMA_HRS_HRS24_MASK (0x1000000U) |
#define | DMA_HRS_HRS24_SHIFT (24U) |
#define | DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) |
#define | DMA_HRS_HRS25_MASK (0x2000000U) |
#define | DMA_HRS_HRS25_SHIFT (25U) |
#define | DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) |
#define | DMA_HRS_HRS26_MASK (0x4000000U) |
#define | DMA_HRS_HRS26_SHIFT (26U) |
#define | DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) |
#define | DMA_HRS_HRS27_MASK (0x8000000U) |
#define | DMA_HRS_HRS27_SHIFT (27U) |
#define | DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) |
#define | DMA_HRS_HRS28_MASK (0x10000000U) |
#define | DMA_HRS_HRS28_SHIFT (28U) |
#define | DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) |
#define | DMA_HRS_HRS29_MASK (0x20000000U) |
#define | DMA_HRS_HRS29_SHIFT (29U) |
#define | DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) |
#define | DMA_HRS_HRS30_MASK (0x40000000U) |
#define | DMA_HRS_HRS30_SHIFT (30U) |
#define | DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) |
#define | DMA_HRS_HRS31_MASK (0x80000000U) |
#define | DMA_HRS_HRS31_SHIFT (31U) |
#define | DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) |
EARS - Enable Asynchronous Request in Stop | |
#define | DMA_EARS_EDREQ_0_MASK (0x1U) |
#define | DMA_EARS_EDREQ_0_SHIFT (0U) |
#define | DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) |
#define | DMA_EARS_EDREQ_1_MASK (0x2U) |
#define | DMA_EARS_EDREQ_1_SHIFT (1U) |
#define | DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) |
#define | DMA_EARS_EDREQ_2_MASK (0x4U) |
#define | DMA_EARS_EDREQ_2_SHIFT (2U) |
#define | DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) |
#define | DMA_EARS_EDREQ_3_MASK (0x8U) |
#define | DMA_EARS_EDREQ_3_SHIFT (3U) |
#define | DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) |
#define | DMA_EARS_EDREQ_4_MASK (0x10U) |
#define | DMA_EARS_EDREQ_4_SHIFT (4U) |
#define | DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) |
#define | DMA_EARS_EDREQ_5_MASK (0x20U) |
#define | DMA_EARS_EDREQ_5_SHIFT (5U) |
#define | DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) |
#define | DMA_EARS_EDREQ_6_MASK (0x40U) |
#define | DMA_EARS_EDREQ_6_SHIFT (6U) |
#define | DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) |
#define | DMA_EARS_EDREQ_7_MASK (0x80U) |
#define | DMA_EARS_EDREQ_7_SHIFT (7U) |
#define | DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) |
#define | DMA_EARS_EDREQ_8_MASK (0x100U) |
#define | DMA_EARS_EDREQ_8_SHIFT (8U) |
#define | DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) |
#define | DMA_EARS_EDREQ_9_MASK (0x200U) |
#define | DMA_EARS_EDREQ_9_SHIFT (9U) |
#define | DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) |
#define | DMA_EARS_EDREQ_10_MASK (0x400U) |
#define | DMA_EARS_EDREQ_10_SHIFT (10U) |
#define | DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) |
#define | DMA_EARS_EDREQ_11_MASK (0x800U) |
#define | DMA_EARS_EDREQ_11_SHIFT (11U) |
#define | DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) |
#define | DMA_EARS_EDREQ_12_MASK (0x1000U) |
#define | DMA_EARS_EDREQ_12_SHIFT (12U) |
#define | DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) |
#define | DMA_EARS_EDREQ_13_MASK (0x2000U) |
#define | DMA_EARS_EDREQ_13_SHIFT (13U) |
#define | DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) |
#define | DMA_EARS_EDREQ_14_MASK (0x4000U) |
#define | DMA_EARS_EDREQ_14_SHIFT (14U) |
#define | DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) |
#define | DMA_EARS_EDREQ_15_MASK (0x8000U) |
#define | DMA_EARS_EDREQ_15_SHIFT (15U) |
#define | DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) |
#define | DMA_EARS_EDREQ_16_MASK (0x10000U) |
#define | DMA_EARS_EDREQ_16_SHIFT (16U) |
#define | DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) |
#define | DMA_EARS_EDREQ_17_MASK (0x20000U) |
#define | DMA_EARS_EDREQ_17_SHIFT (17U) |
#define | DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) |
#define | DMA_EARS_EDREQ_18_MASK (0x40000U) |
#define | DMA_EARS_EDREQ_18_SHIFT (18U) |
#define | DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) |
#define | DMA_EARS_EDREQ_19_MASK (0x80000U) |
#define | DMA_EARS_EDREQ_19_SHIFT (19U) |
#define | DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) |
#define | DMA_EARS_EDREQ_20_MASK (0x100000U) |
#define | DMA_EARS_EDREQ_20_SHIFT (20U) |
#define | DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) |
#define | DMA_EARS_EDREQ_21_MASK (0x200000U) |
#define | DMA_EARS_EDREQ_21_SHIFT (21U) |
#define | DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) |
#define | DMA_EARS_EDREQ_22_MASK (0x400000U) |
#define | DMA_EARS_EDREQ_22_SHIFT (22U) |
#define | DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) |
#define | DMA_EARS_EDREQ_23_MASK (0x800000U) |
#define | DMA_EARS_EDREQ_23_SHIFT (23U) |
#define | DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) |
#define | DMA_EARS_EDREQ_24_MASK (0x1000000U) |
#define | DMA_EARS_EDREQ_24_SHIFT (24U) |
#define | DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) |
#define | DMA_EARS_EDREQ_25_MASK (0x2000000U) |
#define | DMA_EARS_EDREQ_25_SHIFT (25U) |
#define | DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) |
#define | DMA_EARS_EDREQ_26_MASK (0x4000000U) |
#define | DMA_EARS_EDREQ_26_SHIFT (26U) |
#define | DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) |
#define | DMA_EARS_EDREQ_27_MASK (0x8000000U) |
#define | DMA_EARS_EDREQ_27_SHIFT (27U) |
#define | DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) |
#define | DMA_EARS_EDREQ_28_MASK (0x10000000U) |
#define | DMA_EARS_EDREQ_28_SHIFT (28U) |
#define | DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) |
#define | DMA_EARS_EDREQ_29_MASK (0x20000000U) |
#define | DMA_EARS_EDREQ_29_SHIFT (29U) |
#define | DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) |
#define | DMA_EARS_EDREQ_30_MASK (0x40000000U) |
#define | DMA_EARS_EDREQ_30_SHIFT (30U) |
#define | DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) |
#define | DMA_EARS_EDREQ_31_MASK (0x80000000U) |
#define | DMA_EARS_EDREQ_31_SHIFT (31U) |
#define | DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) |
DCHPRI3 - Channel Priority | |
#define | DMA_DCHPRI3_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI3_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) |
#define | DMA_DCHPRI3_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI3_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) |
#define | DMA_DCHPRI3_DPA_MASK (0x40U) |
#define | DMA_DCHPRI3_DPA_SHIFT (6U) |
#define | DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) |
#define | DMA_DCHPRI3_ECP_MASK (0x80U) |
#define | DMA_DCHPRI3_ECP_SHIFT (7U) |
#define | DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) |
DCHPRI2 - Channel Priority | |
#define | DMA_DCHPRI2_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI2_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) |
#define | DMA_DCHPRI2_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI2_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) |
#define | DMA_DCHPRI2_DPA_MASK (0x40U) |
#define | DMA_DCHPRI2_DPA_SHIFT (6U) |
#define | DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) |
#define | DMA_DCHPRI2_ECP_MASK (0x80U) |
#define | DMA_DCHPRI2_ECP_SHIFT (7U) |
#define | DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) |
DCHPRI1 - Channel Priority | |
#define | DMA_DCHPRI1_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI1_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) |
#define | DMA_DCHPRI1_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI1_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) |
#define | DMA_DCHPRI1_DPA_MASK (0x40U) |
#define | DMA_DCHPRI1_DPA_SHIFT (6U) |
#define | DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) |
#define | DMA_DCHPRI1_ECP_MASK (0x80U) |
#define | DMA_DCHPRI1_ECP_SHIFT (7U) |
#define | DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) |
DCHPRI0 - Channel Priority | |
#define | DMA_DCHPRI0_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI0_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) |
#define | DMA_DCHPRI0_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI0_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) |
#define | DMA_DCHPRI0_DPA_MASK (0x40U) |
#define | DMA_DCHPRI0_DPA_SHIFT (6U) |
#define | DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) |
#define | DMA_DCHPRI0_ECP_MASK (0x80U) |
#define | DMA_DCHPRI0_ECP_SHIFT (7U) |
#define | DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) |
DCHPRI7 - Channel Priority | |
#define | DMA_DCHPRI7_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI7_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) |
#define | DMA_DCHPRI7_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI7_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) |
#define | DMA_DCHPRI7_DPA_MASK (0x40U) |
#define | DMA_DCHPRI7_DPA_SHIFT (6U) |
#define | DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) |
#define | DMA_DCHPRI7_ECP_MASK (0x80U) |
#define | DMA_DCHPRI7_ECP_SHIFT (7U) |
#define | DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) |
DCHPRI6 - Channel Priority | |
#define | DMA_DCHPRI6_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI6_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) |
#define | DMA_DCHPRI6_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI6_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) |
#define | DMA_DCHPRI6_DPA_MASK (0x40U) |
#define | DMA_DCHPRI6_DPA_SHIFT (6U) |
#define | DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) |
#define | DMA_DCHPRI6_ECP_MASK (0x80U) |
#define | DMA_DCHPRI6_ECP_SHIFT (7U) |
#define | DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) |
DCHPRI5 - Channel Priority | |
#define | DMA_DCHPRI5_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI5_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) |
#define | DMA_DCHPRI5_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI5_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) |
#define | DMA_DCHPRI5_DPA_MASK (0x40U) |
#define | DMA_DCHPRI5_DPA_SHIFT (6U) |
#define | DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) |
#define | DMA_DCHPRI5_ECP_MASK (0x80U) |
#define | DMA_DCHPRI5_ECP_SHIFT (7U) |
#define | DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) |
DCHPRI4 - Channel Priority | |
#define | DMA_DCHPRI4_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI4_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) |
#define | DMA_DCHPRI4_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI4_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) |
#define | DMA_DCHPRI4_DPA_MASK (0x40U) |
#define | DMA_DCHPRI4_DPA_SHIFT (6U) |
#define | DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) |
#define | DMA_DCHPRI4_ECP_MASK (0x80U) |
#define | DMA_DCHPRI4_ECP_SHIFT (7U) |
#define | DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) |
DCHPRI11 - Channel Priority | |
#define | DMA_DCHPRI11_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI11_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) |
#define | DMA_DCHPRI11_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI11_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) |
#define | DMA_DCHPRI11_DPA_MASK (0x40U) |
#define | DMA_DCHPRI11_DPA_SHIFT (6U) |
#define | DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) |
#define | DMA_DCHPRI11_ECP_MASK (0x80U) |
#define | DMA_DCHPRI11_ECP_SHIFT (7U) |
#define | DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) |
DCHPRI10 - Channel Priority | |
#define | DMA_DCHPRI10_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI10_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) |
#define | DMA_DCHPRI10_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI10_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) |
#define | DMA_DCHPRI10_DPA_MASK (0x40U) |
#define | DMA_DCHPRI10_DPA_SHIFT (6U) |
#define | DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) |
#define | DMA_DCHPRI10_ECP_MASK (0x80U) |
#define | DMA_DCHPRI10_ECP_SHIFT (7U) |
#define | DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) |
DCHPRI9 - Channel Priority | |
#define | DMA_DCHPRI9_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI9_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) |
#define | DMA_DCHPRI9_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI9_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) |
#define | DMA_DCHPRI9_DPA_MASK (0x40U) |
#define | DMA_DCHPRI9_DPA_SHIFT (6U) |
#define | DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) |
#define | DMA_DCHPRI9_ECP_MASK (0x80U) |
#define | DMA_DCHPRI9_ECP_SHIFT (7U) |
#define | DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) |
DCHPRI8 - Channel Priority | |
#define | DMA_DCHPRI8_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI8_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) |
#define | DMA_DCHPRI8_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI8_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) |
#define | DMA_DCHPRI8_DPA_MASK (0x40U) |
#define | DMA_DCHPRI8_DPA_SHIFT (6U) |
#define | DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) |
#define | DMA_DCHPRI8_ECP_MASK (0x80U) |
#define | DMA_DCHPRI8_ECP_SHIFT (7U) |
#define | DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) |
DCHPRI15 - Channel Priority | |
#define | DMA_DCHPRI15_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI15_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) |
#define | DMA_DCHPRI15_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI15_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) |
#define | DMA_DCHPRI15_DPA_MASK (0x40U) |
#define | DMA_DCHPRI15_DPA_SHIFT (6U) |
#define | DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) |
#define | DMA_DCHPRI15_ECP_MASK (0x80U) |
#define | DMA_DCHPRI15_ECP_SHIFT (7U) |
#define | DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) |
DCHPRI14 - Channel Priority | |
#define | DMA_DCHPRI14_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI14_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) |
#define | DMA_DCHPRI14_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI14_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) |
#define | DMA_DCHPRI14_DPA_MASK (0x40U) |
#define | DMA_DCHPRI14_DPA_SHIFT (6U) |
#define | DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) |
#define | DMA_DCHPRI14_ECP_MASK (0x80U) |
#define | DMA_DCHPRI14_ECP_SHIFT (7U) |
#define | DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) |
DCHPRI13 - Channel Priority | |
#define | DMA_DCHPRI13_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI13_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) |
#define | DMA_DCHPRI13_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI13_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) |
#define | DMA_DCHPRI13_DPA_MASK (0x40U) |
#define | DMA_DCHPRI13_DPA_SHIFT (6U) |
#define | DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) |
#define | DMA_DCHPRI13_ECP_MASK (0x80U) |
#define | DMA_DCHPRI13_ECP_SHIFT (7U) |
#define | DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) |
DCHPRI12 - Channel Priority | |
#define | DMA_DCHPRI12_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI12_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) |
#define | DMA_DCHPRI12_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI12_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) |
#define | DMA_DCHPRI12_DPA_MASK (0x40U) |
#define | DMA_DCHPRI12_DPA_SHIFT (6U) |
#define | DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) |
#define | DMA_DCHPRI12_ECP_MASK (0x80U) |
#define | DMA_DCHPRI12_ECP_SHIFT (7U) |
#define | DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) |
DCHPRI19 - Channel Priority | |
#define | DMA_DCHPRI19_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI19_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) |
#define | DMA_DCHPRI19_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI19_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) |
#define | DMA_DCHPRI19_DPA_MASK (0x40U) |
#define | DMA_DCHPRI19_DPA_SHIFT (6U) |
#define | DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) |
#define | DMA_DCHPRI19_ECP_MASK (0x80U) |
#define | DMA_DCHPRI19_ECP_SHIFT (7U) |
#define | DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) |
DCHPRI18 - Channel Priority | |
#define | DMA_DCHPRI18_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI18_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) |
#define | DMA_DCHPRI18_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI18_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) |
#define | DMA_DCHPRI18_DPA_MASK (0x40U) |
#define | DMA_DCHPRI18_DPA_SHIFT (6U) |
#define | DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) |
#define | DMA_DCHPRI18_ECP_MASK (0x80U) |
#define | DMA_DCHPRI18_ECP_SHIFT (7U) |
#define | DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) |
DCHPRI17 - Channel Priority | |
#define | DMA_DCHPRI17_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI17_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) |
#define | DMA_DCHPRI17_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI17_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) |
#define | DMA_DCHPRI17_DPA_MASK (0x40U) |
#define | DMA_DCHPRI17_DPA_SHIFT (6U) |
#define | DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) |
#define | DMA_DCHPRI17_ECP_MASK (0x80U) |
#define | DMA_DCHPRI17_ECP_SHIFT (7U) |
#define | DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) |
DCHPRI16 - Channel Priority | |
#define | DMA_DCHPRI16_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI16_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) |
#define | DMA_DCHPRI16_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI16_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) |
#define | DMA_DCHPRI16_DPA_MASK (0x40U) |
#define | DMA_DCHPRI16_DPA_SHIFT (6U) |
#define | DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) |
#define | DMA_DCHPRI16_ECP_MASK (0x80U) |
#define | DMA_DCHPRI16_ECP_SHIFT (7U) |
#define | DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) |
DCHPRI23 - Channel Priority | |
#define | DMA_DCHPRI23_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI23_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) |
#define | DMA_DCHPRI23_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI23_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) |
#define | DMA_DCHPRI23_DPA_MASK (0x40U) |
#define | DMA_DCHPRI23_DPA_SHIFT (6U) |
#define | DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) |
#define | DMA_DCHPRI23_ECP_MASK (0x80U) |
#define | DMA_DCHPRI23_ECP_SHIFT (7U) |
#define | DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) |
DCHPRI22 - Channel Priority | |
#define | DMA_DCHPRI22_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI22_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) |
#define | DMA_DCHPRI22_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI22_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) |
#define | DMA_DCHPRI22_DPA_MASK (0x40U) |
#define | DMA_DCHPRI22_DPA_SHIFT (6U) |
#define | DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) |
#define | DMA_DCHPRI22_ECP_MASK (0x80U) |
#define | DMA_DCHPRI22_ECP_SHIFT (7U) |
#define | DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) |
DCHPRI21 - Channel Priority | |
#define | DMA_DCHPRI21_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI21_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) |
#define | DMA_DCHPRI21_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI21_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) |
#define | DMA_DCHPRI21_DPA_MASK (0x40U) |
#define | DMA_DCHPRI21_DPA_SHIFT (6U) |
#define | DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) |
#define | DMA_DCHPRI21_ECP_MASK (0x80U) |
#define | DMA_DCHPRI21_ECP_SHIFT (7U) |
#define | DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) |
DCHPRI20 - Channel Priority | |
#define | DMA_DCHPRI20_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI20_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) |
#define | DMA_DCHPRI20_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI20_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) |
#define | DMA_DCHPRI20_DPA_MASK (0x40U) |
#define | DMA_DCHPRI20_DPA_SHIFT (6U) |
#define | DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) |
#define | DMA_DCHPRI20_ECP_MASK (0x80U) |
#define | DMA_DCHPRI20_ECP_SHIFT (7U) |
#define | DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) |
DCHPRI27 - Channel Priority | |
#define | DMA_DCHPRI27_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI27_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) |
#define | DMA_DCHPRI27_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI27_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) |
#define | DMA_DCHPRI27_DPA_MASK (0x40U) |
#define | DMA_DCHPRI27_DPA_SHIFT (6U) |
#define | DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) |
#define | DMA_DCHPRI27_ECP_MASK (0x80U) |
#define | DMA_DCHPRI27_ECP_SHIFT (7U) |
#define | DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) |
DCHPRI26 - Channel Priority | |
#define | DMA_DCHPRI26_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI26_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) |
#define | DMA_DCHPRI26_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI26_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) |
#define | DMA_DCHPRI26_DPA_MASK (0x40U) |
#define | DMA_DCHPRI26_DPA_SHIFT (6U) |
#define | DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) |
#define | DMA_DCHPRI26_ECP_MASK (0x80U) |
#define | DMA_DCHPRI26_ECP_SHIFT (7U) |
#define | DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) |
DCHPRI25 - Channel Priority | |
#define | DMA_DCHPRI25_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI25_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) |
#define | DMA_DCHPRI25_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI25_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) |
#define | DMA_DCHPRI25_DPA_MASK (0x40U) |
#define | DMA_DCHPRI25_DPA_SHIFT (6U) |
#define | DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) |
#define | DMA_DCHPRI25_ECP_MASK (0x80U) |
#define | DMA_DCHPRI25_ECP_SHIFT (7U) |
#define | DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) |
DCHPRI24 - Channel Priority | |
#define | DMA_DCHPRI24_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI24_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) |
#define | DMA_DCHPRI24_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI24_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) |
#define | DMA_DCHPRI24_DPA_MASK (0x40U) |
#define | DMA_DCHPRI24_DPA_SHIFT (6U) |
#define | DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) |
#define | DMA_DCHPRI24_ECP_MASK (0x80U) |
#define | DMA_DCHPRI24_ECP_SHIFT (7U) |
#define | DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) |
DCHPRI31 - Channel Priority | |
#define | DMA_DCHPRI31_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI31_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) |
#define | DMA_DCHPRI31_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI31_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) |
#define | DMA_DCHPRI31_DPA_MASK (0x40U) |
#define | DMA_DCHPRI31_DPA_SHIFT (6U) |
#define | DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) |
#define | DMA_DCHPRI31_ECP_MASK (0x80U) |
#define | DMA_DCHPRI31_ECP_SHIFT (7U) |
#define | DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) |
DCHPRI30 - Channel Priority | |
#define | DMA_DCHPRI30_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI30_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) |
#define | DMA_DCHPRI30_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI30_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) |
#define | DMA_DCHPRI30_DPA_MASK (0x40U) |
#define | DMA_DCHPRI30_DPA_SHIFT (6U) |
#define | DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) |
#define | DMA_DCHPRI30_ECP_MASK (0x80U) |
#define | DMA_DCHPRI30_ECP_SHIFT (7U) |
#define | DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) |
DCHPRI29 - Channel Priority | |
#define | DMA_DCHPRI29_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI29_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) |
#define | DMA_DCHPRI29_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI29_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) |
#define | DMA_DCHPRI29_DPA_MASK (0x40U) |
#define | DMA_DCHPRI29_DPA_SHIFT (6U) |
#define | DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) |
#define | DMA_DCHPRI29_ECP_MASK (0x80U) |
#define | DMA_DCHPRI29_ECP_SHIFT (7U) |
#define | DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) |
DCHPRI28 - Channel Priority | |
#define | DMA_DCHPRI28_CHPRI_MASK (0xFU) |
#define | DMA_DCHPRI28_CHPRI_SHIFT (0U) |
#define | DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) |
#define | DMA_DCHPRI28_GRPPRI_MASK (0x30U) |
#define | DMA_DCHPRI28_GRPPRI_SHIFT (4U) |
#define | DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) |
#define | DMA_DCHPRI28_DPA_MASK (0x40U) |
#define | DMA_DCHPRI28_DPA_SHIFT (6U) |
#define | DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) |
#define | DMA_DCHPRI28_ECP_MASK (0x80U) |
#define | DMA_DCHPRI28_ECP_SHIFT (7U) |
#define | DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) |
SADDR - TCD Source Address | |
#define | DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) |
#define | DMA_SADDR_SADDR_SHIFT (0U) |
#define | DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) |
SOFF - TCD Signed Source Address Offset | |
#define | DMA_SOFF_SOFF_MASK (0xFFFFU) |
#define | DMA_SOFF_SOFF_SHIFT (0U) |
#define | DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) |
ATTR - TCD Transfer Attributes | |
#define | DMA_ATTR_DSIZE_MASK (0x7U) |
#define | DMA_ATTR_DSIZE_SHIFT (0U) |
#define | DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) |
#define | DMA_ATTR_DMOD_MASK (0xF8U) |
#define | DMA_ATTR_DMOD_SHIFT (3U) |
#define | DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) |
#define | DMA_ATTR_SSIZE_MASK (0x700U) |
#define | DMA_ATTR_SSIZE_SHIFT (8U) |
#define | DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) |
#define | DMA_ATTR_SMOD_MASK (0xF800U) |
#define | DMA_ATTR_SMOD_SHIFT (11U) |
#define | DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) |
NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) | |
#define | DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) |
#define | DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) |
#define | DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) |
NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) | |
#define | DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) |
#define | DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) |
#define | DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) |
#define | DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) |
#define | DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) |
#define | DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) |
#define | DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) |
#define | DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) |
#define | DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) |
NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) | |
#define | DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) |
#define | DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) |
#define | DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) |
#define | DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) |
#define | DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) |
#define | DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) |
#define | DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) |
#define | DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) |
#define | DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) |
#define | DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) |
#define | DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) |
#define | DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) |
SLAST - TCD Last Source Address Adjustment | |
#define | DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) |
#define | DMA_SLAST_SLAST_SHIFT (0U) |
#define | DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) |
DADDR - TCD Destination Address | |
#define | DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) |
#define | DMA_DADDR_DADDR_SHIFT (0U) |
#define | DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) |
DOFF - TCD Signed Destination Address Offset | |
#define | DMA_DOFF_DOFF_MASK (0xFFFFU) |
#define | DMA_DOFF_DOFF_SHIFT (0U) |
#define | DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) |
CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) | |
#define | DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) |
#define | DMA_CITER_ELINKNO_CITER_SHIFT (0U) |
#define | DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) |
#define | DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) |
#define | DMA_CITER_ELINKNO_ELINK_SHIFT (15U) |
#define | DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) |
CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) | |
#define | DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) |
#define | DMA_CITER_ELINKYES_CITER_SHIFT (0U) |
#define | DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) |
#define | DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) |
#define | DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) |
#define | DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) |
#define | DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) |
#define | DMA_CITER_ELINKYES_ELINK_SHIFT (15U) |
#define | DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) |
DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address | |
#define | DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) |
#define | DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) |
#define | DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) |
CSR - TCD Control and Status | |
#define | DMA_CSR_START_MASK (0x1U) |
#define | DMA_CSR_START_SHIFT (0U) |
#define | DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) |
#define | DMA_CSR_INTMAJOR_MASK (0x2U) |
#define | DMA_CSR_INTMAJOR_SHIFT (1U) |
#define | DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) |
#define | DMA_CSR_INTHALF_MASK (0x4U) |
#define | DMA_CSR_INTHALF_SHIFT (2U) |
#define | DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) |
#define | DMA_CSR_DREQ_MASK (0x8U) |
#define | DMA_CSR_DREQ_SHIFT (3U) |
#define | DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) |
#define | DMA_CSR_ESG_MASK (0x10U) |
#define | DMA_CSR_ESG_SHIFT (4U) |
#define | DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) |
#define | DMA_CSR_MAJORELINK_MASK (0x20U) |
#define | DMA_CSR_MAJORELINK_SHIFT (5U) |
#define | DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) |
#define | DMA_CSR_ACTIVE_MASK (0x40U) |
#define | DMA_CSR_ACTIVE_SHIFT (6U) |
#define | DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) |
#define | DMA_CSR_DONE_MASK (0x80U) |
#define | DMA_CSR_DONE_SHIFT (7U) |
#define | DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) |
#define | DMA_CSR_MAJORLINKCH_MASK (0x1F00U) |
#define | DMA_CSR_MAJORLINKCH_SHIFT (8U) |
#define | DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) |
#define | DMA_CSR_BWC_MASK (0xC000U) |
#define | DMA_CSR_BWC_SHIFT (14U) |
#define | DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) |
BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) | |
#define | DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) |
#define | DMA_BITER_ELINKNO_BITER_SHIFT (0U) |
#define | DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) |
#define | DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) |
#define | DMA_BITER_ELINKNO_ELINK_SHIFT (15U) |
#define | DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) |
BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) | |
#define | DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) |
#define | DMA_BITER_ELINKYES_BITER_SHIFT (0U) |
#define | DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) |
#define | DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) |
#define | DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) |
#define | DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) |
#define | DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) |
#define | DMA_BITER_ELINKYES_ELINK_SHIFT (15U) |
#define | DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) |
CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register | |
#define | DMAMUX_CHCFG_SOURCE_MASK (0xFFU) |
#define | DMAMUX_CHCFG_SOURCE_SHIFT (0U) |
#define | DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
#define | DMAMUX_CHCFG_A_ON_MASK (0x20000000U) |
#define | DMAMUX_CHCFG_A_ON_SHIFT (29U) |
#define | DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) |
#define | DMAMUX_CHCFG_TRIG_MASK (0x40000000U) |
#define | DMAMUX_CHCFG_TRIG_SHIFT (30U) |
#define | DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
#define | DMAMUX_CHCFG_ENBL_MASK (0x80000000U) |
#define | DMAMUX_CHCFG_ENBL_SHIFT (31U) |
#define | DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
CFG_NUM_LANES - CFG_NUM_LANES | |
#define | DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK (0x3U) |
#define | DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT (0U) |
#define | DSI_HOST_CFG_NUM_LANES_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK) |
CFG_NONCONTINUOUS_CLK - CFG_NONCONTINUOUS_CLK | |
#define | DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK (0x1U) |
#define | DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT (0U) |
#define | DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK) |
CFG_T_PRE - CFG_T_PRE | |
#define | DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK (0xFFU) |
#define | DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT (0U) |
#define | DSI_HOST_CFG_T_PRE_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK) |
CFG_T_POST - CFG_T_POST | |
#define | DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK (0xFFU) |
#define | DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT (0U) |
#define | DSI_HOST_CFG_T_POST_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK) |
CFG_TX_GAP - CFG_TX_GAP | |
#define | DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK (0xFFU) |
#define | DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT (0U) |
#define | DSI_HOST_CFG_TX_GAP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK) |
CFG_AUTOINSERT_EOTP - CFG_AUTOINSERT_ETOP | |
#define | DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK (0x1U) |
#define | DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT (0U) |
#define | DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK) |
CFG_EXTRA_CMDS_AFTER_EOTP - CFG_EXTRA_CMDS_AFTER_ETOP | |
#define | DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK (0xFFU) |
#define | DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT (0U) |
#define | DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK) |
CFG_HTX_TO_COUNT - CFG_HTX_TO_COUNT | |
#define | DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK (0xFFFFFFU) |
#define | DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT (0U) |
#define | DSI_HOST_CFG_HTX_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK) |
CFG_LRX_H_TO_COUNT - CFG_LRX_H_TO_COUNT | |
#define | DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK (0xFFFFFFU) |
#define | DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT (0U) |
#define | DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK) |
CFG_BTA_H_TO_COUNT - CFG_BTA_H_TO_COUNT | |
#define | DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK (0xFFFFFFU) |
#define | DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT (0U) |
#define | DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK) |
CFG_TWAKEUP - CFG_TWAKEUP | |
#define | DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK (0x7FFFFU) |
#define | DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT (0U) |
#define | DSI_HOST_CFG_TWAKEUP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK) |
CFG_STATUS_OUT - CFG_STATUS_OUT | |
#define | DSI_HOST_CFG_STATUS_OUT_STATUS_MASK (0xFFFFFFFFU) |
#define | DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT (0U) |
#define | DSI_HOST_CFG_STATUS_OUT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & DSI_HOST_CFG_STATUS_OUT_STATUS_MASK) |
RX_ERROR_STATUS - RX_ERROR_STATUS | |
#define | DSI_HOST_RX_ERROR_STATUS_STATUS_MASK (0x7FFU) |
#define | DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT (0U) |
#define | DSI_HOST_RX_ERROR_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT)) & DSI_HOST_RX_ERROR_STATUS_STATUS_MASK) |
TX_PAYLOAD - TX_PAYLOAD | |
#define | DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU) |
#define | DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK) |
PKT_CONTROL - PKT_CONTROL | |
#define | DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK (0x7FFFFFFU) |
#define | DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK) |
SEND_PACKET - SEND_PACKET | |
#define | DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK (0x1U) |
#define | DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT)) & DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK) |
PKT_STATUS - PKT_STATUS | |
#define | DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK (0x1FFU) |
#define | DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK) |
PKT_FIFO_WR_LEVEL - PKT_FIFO_WR_LEVEL | |
#define | DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK (0xFFFFU) |
#define | DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK) |
PKT_FIFO_RD_LEVEL - PKT_FIFO_RD_LEVEL | |
#define | DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK (0xFFFFU) |
#define | DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK) |
PKT_RX_PAYLOAD - PKT_RX_PAYLOAD | |
#define | DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU) |
#define | DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK) |
PKT_RX_PKT_HEADER - PKT_RX_PKT_HEADER | |
#define | DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK (0xFFFFFFU) |
#define | DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK) |
IRQ_STATUS - IRQ_STATUS | |
#define | DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK (0xFFFFFFFFU) |
#define | DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK) |
IRQ_STATUS2 - IRQ_STATUS2 | |
#define | DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK (0x7U) |
#define | DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK) |
IRQ_MASK - IRQ_MASK | |
#define | DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK (0xFFFFFFFFU) |
#define | DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK) |
IRQ_MASK2 - IRQ_MASK2 | |
#define | DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK (0x7U) |
#define | DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT (0U) |
#define | DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK) |
PIXEL_PAYLOAD_SIZE - PEXEL_PAYLOAD_SIZE | |
#define | DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK (0xFFFFU) |
#define | DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK) |
PIXEL_FIFO_SEND_LEVEL - PIXEL_FIFO_SEND_LEVEL | |
#define | DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK (0xFFFFU) |
#define | DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK) |
INTERFACE_COLOR_CODING - INTERFACE_COLOR_CODING | |
#define | DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK (0x7U) |
#define | DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK) |
PIXEL_FORMAT - PIXEL_FORMAT | |
#define | DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK (0x3U) |
#define | DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK) |
VSYNC_POLARITY - VSYNC_POLARITY | |
#define | DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK (0x1U) |
#define | DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK) |
HSYNC_POLARITY - HSYNC_POLARITY | |
#define | DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK (0x1U) |
#define | DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK) |
VIDEO_MODE - VIDEO_MODE | |
#define | DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK (0x3U) |
#define | DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT)) & DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK) |
HFP - HFP | |
#define | DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK (0xFFFFU) |
#define | DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK) |
HBP - HBP | |
#define | DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK (0xFFFFU) |
#define | DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK) |
HSA - HSA | |
#define | DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK (0xFFFFU) |
#define | DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK) |
ENABLE_MULT_PKTS - ENABLE_MULT_PKTS | |
#define | DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK (0x1U) |
#define | DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK) |
VBP - VBP | |
#define | DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK (0xFFU) |
#define | DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_VBP_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK) |
VFP - VFP | |
#define | DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK (0xFFU) |
#define | DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_VFP_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK) |
BLLP_MODE - BLLP_MODE | |
#define | DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK (0x1U) |
#define | DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_BLLP_MODE_LP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT)) & DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK) |
USE_NULL_PKT_BLLP - USE_NULL_PKT_BLLP | |
#define | DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK (0x1U) |
#define | DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT)) & DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK) |
VACTIVE - VACTIVE | |
#define | DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK (0x3FFFU) |
#define | DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT (0U) |
#define | DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK) |
PD_TX - PD_TX | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK (0x1U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK) |
M_PRG_HS_PREPARE - M_PRG_HS_PREPARE | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK (0x3U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK) |
MC_PRG_HS_PREPARE - MC_PRG_HS_PREPARE | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK (0x1U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK) |
M_PRG_HS_ZERO - M_PRG_HS_ZERO | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK (0x1FU) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK) |
MC_PRG_HS_ZERO - MC_PRG_HS_ZERO | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK (0x3FU) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK) |
M_PRG_HS_TRAIL - M_PRG_HS_TRAIL | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK (0xFU) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK) |
MC_PRG_HS_TRAIL - MC_PRG_HS_TRAIL | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK (0xFU) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK) |
PD_PLL - PD_PLL | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK (0x1U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK) |
TST - TST | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK (0x3FU) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK) |
CN - CN | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK (0x1FU) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK) |
CM - CM | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK (0xFFU) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK) |
CO - CO | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK (0x3U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK) |
LOCK - LOCK | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK (0x1U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK) |
LOCK_BYP - LOCK_BYP | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK (0x1U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK) |
TX_RCAL - TX_RCAL | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK (0x3U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK) |
AUTO_PD_EN - AUTO_PD_EN | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK (0x1U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK) |
RXLPRP - RXLPRP | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK (0x3U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK) |
RXCDRP - RXCDRP | |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK (0x3U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT (0U) |
#define | DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK) |
VER_ID - Version ID Register | |
#define | EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU) |
#define | EMVSIM_VER_ID_VER_SHIFT (0U) |
#define | EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK) |
CLKCFG - Clock Configuration Register | |
#define | EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU) |
#define | EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U) |
#define | EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK) |
#define | EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U) |
#define | EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U) |
#define | EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK) |
#define | EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U) |
#define | EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U) |
#define | EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK) |
DIVISOR - Baud Rate Divisor Register | |
#define | EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU) |
#define | EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U) |
#define | EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK) |
CTRL - Control Register | |
#define | EMVSIM_CTRL_IC_MASK (0x1U) |
#define | EMVSIM_CTRL_IC_SHIFT (0U) |
#define | EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK) |
#define | EMVSIM_CTRL_ICM_MASK (0x2U) |
#define | EMVSIM_CTRL_ICM_SHIFT (1U) |
#define | EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK) |
#define | EMVSIM_CTRL_ANACK_MASK (0x4U) |
#define | EMVSIM_CTRL_ANACK_SHIFT (2U) |
#define | EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK) |
#define | EMVSIM_CTRL_ONACK_MASK (0x8U) |
#define | EMVSIM_CTRL_ONACK_SHIFT (3U) |
#define | EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK) |
#define | EMVSIM_CTRL_FLSH_RX_MASK (0x100U) |
#define | EMVSIM_CTRL_FLSH_RX_SHIFT (8U) |
#define | EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK) |
#define | EMVSIM_CTRL_FLSH_TX_MASK (0x200U) |
#define | EMVSIM_CTRL_FLSH_TX_SHIFT (9U) |
#define | EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK) |
#define | EMVSIM_CTRL_SW_RST_MASK (0x400U) |
#define | EMVSIM_CTRL_SW_RST_SHIFT (10U) |
#define | EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK) |
#define | EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U) |
#define | EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U) |
#define | EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK) |
#define | EMVSIM_CTRL_DOZE_EN_MASK (0x1000U) |
#define | EMVSIM_CTRL_DOZE_EN_SHIFT (12U) |
#define | EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK) |
#define | EMVSIM_CTRL_STOP_EN_MASK (0x2000U) |
#define | EMVSIM_CTRL_STOP_EN_SHIFT (13U) |
#define | EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK) |
#define | EMVSIM_CTRL_RCV_EN_MASK (0x10000U) |
#define | EMVSIM_CTRL_RCV_EN_SHIFT (16U) |
#define | EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK) |
#define | EMVSIM_CTRL_XMT_EN_MASK (0x20000U) |
#define | EMVSIM_CTRL_XMT_EN_SHIFT (17U) |
#define | EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK) |
#define | EMVSIM_CTRL_RCVR_11_MASK (0x40000U) |
#define | EMVSIM_CTRL_RCVR_11_SHIFT (18U) |
#define | EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK) |
#define | EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U) |
#define | EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U) |
#define | EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK) |
#define | EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U) |
#define | EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U) |
#define | EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK) |
#define | EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U) |
#define | EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U) |
#define | EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK) |
#define | EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U) |
#define | EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U) |
#define | EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK) |
#define | EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U) |
#define | EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U) |
#define | EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK) |
#define | EMVSIM_CTRL_CWT_EN_MASK (0x8000000U) |
#define | EMVSIM_CTRL_CWT_EN_SHIFT (27U) |
#define | EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK) |
#define | EMVSIM_CTRL_LRC_EN_MASK (0x10000000U) |
#define | EMVSIM_CTRL_LRC_EN_SHIFT (28U) |
#define | EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK) |
#define | EMVSIM_CTRL_CRC_EN_MASK (0x20000000U) |
#define | EMVSIM_CTRL_CRC_EN_SHIFT (29U) |
#define | EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK) |
#define | EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U) |
#define | EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U) |
#define | EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK) |
#define | EMVSIM_CTRL_BWT_EN_MASK (0x80000000U) |
#define | EMVSIM_CTRL_BWT_EN_SHIFT (31U) |
#define | EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK) |
#define | ENC_CTRL_CMPIE_MASK (0x1U) |
#define | ENC_CTRL_CMPIE_SHIFT (0U) |
#define | ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) |
#define | ENC_CTRL_CMPIRQ_MASK (0x2U) |
#define | ENC_CTRL_CMPIRQ_SHIFT (1U) |
#define | ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) |
#define | ENC_CTRL_WDE_MASK (0x4U) |
#define | ENC_CTRL_WDE_SHIFT (2U) |
#define | ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) |
#define | ENC_CTRL_DIE_MASK (0x8U) |
#define | ENC_CTRL_DIE_SHIFT (3U) |
#define | ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) |
#define | ENC_CTRL_DIRQ_MASK (0x10U) |
#define | ENC_CTRL_DIRQ_SHIFT (4U) |
#define | ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) |
#define | ENC_CTRL_XNE_MASK (0x20U) |
#define | ENC_CTRL_XNE_SHIFT (5U) |
#define | ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) |
#define | ENC_CTRL_XIP_MASK (0x40U) |
#define | ENC_CTRL_XIP_SHIFT (6U) |
#define | ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) |
#define | ENC_CTRL_XIE_MASK (0x80U) |
#define | ENC_CTRL_XIE_SHIFT (7U) |
#define | ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) |
#define | ENC_CTRL_XIRQ_MASK (0x100U) |
#define | ENC_CTRL_XIRQ_SHIFT (8U) |
#define | ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) |
#define | ENC_CTRL_PH1_MASK (0x200U) |
#define | ENC_CTRL_PH1_SHIFT (9U) |
#define | ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) |
#define | ENC_CTRL_REV_MASK (0x400U) |
#define | ENC_CTRL_REV_SHIFT (10U) |
#define | ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) |
#define | ENC_CTRL_SWIP_MASK (0x800U) |
#define | ENC_CTRL_SWIP_SHIFT (11U) |
#define | ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) |
#define | ENC_CTRL_HNE_MASK (0x1000U) |
#define | ENC_CTRL_HNE_SHIFT (12U) |
#define | ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) |
#define | ENC_CTRL_HIP_MASK (0x2000U) |
#define | ENC_CTRL_HIP_SHIFT (13U) |
#define | ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) |
#define | ENC_CTRL_HIE_MASK (0x4000U) |
#define | ENC_CTRL_HIE_SHIFT (14U) |
#define | ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) |
#define | ENC_CTRL_HIRQ_MASK (0x8000U) |
#define | ENC_CTRL_HIRQ_SHIFT (15U) |
#define | ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) |
#define | EWM_CTRL_EWMEN_MASK (0x1U) |
#define | EWM_CTRL_EWMEN_SHIFT (0U) |
#define | EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) |
#define | EWM_CTRL_ASSIN_MASK (0x2U) |
#define | EWM_CTRL_ASSIN_SHIFT (1U) |
#define | EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) |
#define | EWM_CTRL_INEN_MASK (0x4U) |
#define | EWM_CTRL_INEN_SHIFT (2U) |
#define | EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) |
#define | EWM_CTRL_INTEN_MASK (0x8U) |
#define | EWM_CTRL_INTEN_SHIFT (3U) |
#define | EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) |
#define | PWM_CTRL_DBLEN_MASK (0x1U) |
#define | PWM_CTRL_DBLEN_SHIFT (0U) |
#define | PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) |
#define | PWM_CTRL_DBLX_MASK (0x2U) |
#define | PWM_CTRL_DBLX_SHIFT (1U) |
#define | PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) |
#define | PWM_CTRL_LDMOD_MASK (0x4U) |
#define | PWM_CTRL_LDMOD_SHIFT (2U) |
#define | PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) |
#define | PWM_CTRL_SPLIT_MASK (0x8U) |
#define | PWM_CTRL_SPLIT_SHIFT (3U) |
#define | PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) |
#define | PWM_CTRL_PRSC_MASK (0x70U) |
#define | PWM_CTRL_PRSC_SHIFT (4U) |
#define | PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) |
#define | PWM_CTRL_COMPMODE_MASK (0x80U) |
#define | PWM_CTRL_COMPMODE_SHIFT (7U) |
#define | PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) |
#define | PWM_CTRL_DT_MASK (0x300U) |
#define | PWM_CTRL_DT_SHIFT (8U) |
#define | PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) |
#define | PWM_CTRL_FULL_MASK (0x400U) |
#define | PWM_CTRL_FULL_SHIFT (10U) |
#define | PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) |
#define | PWM_CTRL_HALF_MASK (0x800U) |
#define | PWM_CTRL_HALF_SHIFT (11U) |
#define | PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) |
#define | PWM_CTRL_LDFQ_MASK (0xF000U) |
#define | PWM_CTRL_LDFQ_SHIFT (12U) |
#define | PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) |
#define | SRAM_CTRL_RAM_RD_EN_MASK (0x1U) |
#define | SRAM_CTRL_RAM_RD_EN_SHIFT (0U) |
#define | SRAM_CTRL_RAM_RD_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK) |
#define | SRAM_CTRL_RAM_WR_EN_MASK (0x2U) |
#define | SRAM_CTRL_RAM_WR_EN_SHIFT (1U) |
#define | SRAM_CTRL_RAM_WR_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK) |
#define | SRAM_CTRL_PWR_EN_MASK (0x3CU) |
#define | SRAM_CTRL_PWR_EN_SHIFT (2U) |
#define | SRAM_CTRL_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK) |
#define | SRAM_CTRL_TAMPER_BLOCK_EN_MASK (0x40U) |
#define | SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT (6U) |
#define | SRAM_CTRL_TAMPER_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK) |
#define | SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK (0x80U) |
#define | SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT (7U) |
#define | SRAM_CTRL_TAMPER_PWR_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK) |
#define | SRAM_CTRL_LOCK_BIT_MASK (0xFF0000U) |
#define | SRAM_CTRL_LOCK_BIT_SHIFT (16U) |
#define | SRAM_CTRL_LOCK_BIT(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK) |
#define | SSARC_LP_CTRL_DIS_HW_REQ_MASK (0x8000000U) |
#define | SSARC_LP_CTRL_DIS_HW_REQ_SHIFT (27U) |
#define | SSARC_LP_CTRL_DIS_HW_REQ(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK) |
#define | SSARC_LP_CTRL_SW_RESET_MASK (0x80000000U) |
#define | SSARC_LP_CTRL_SW_RESET_SHIFT (31U) |
#define | SSARC_LP_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK) |
INT_MASK - Interrupt Mask Register | |
#define | EMVSIM_INT_MASK_RDT_IM_MASK (0x1U) |
#define | EMVSIM_INT_MASK_RDT_IM_SHIFT (0U) |
#define | EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK) |
#define | EMVSIM_INT_MASK_TC_IM_MASK (0x2U) |
#define | EMVSIM_INT_MASK_TC_IM_SHIFT (1U) |
#define | EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK) |
#define | EMVSIM_INT_MASK_RFO_IM_MASK (0x4U) |
#define | EMVSIM_INT_MASK_RFO_IM_SHIFT (2U) |
#define | EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK) |
#define | EMVSIM_INT_MASK_ETC_IM_MASK (0x8U) |
#define | EMVSIM_INT_MASK_ETC_IM_SHIFT (3U) |
#define | EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK) |
#define | EMVSIM_INT_MASK_TFE_IM_MASK (0x10U) |
#define | EMVSIM_INT_MASK_TFE_IM_SHIFT (4U) |
#define | EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK) |
#define | EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U) |
#define | EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U) |
#define | EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK) |
#define | EMVSIM_INT_MASK_TFF_IM_MASK (0x40U) |
#define | EMVSIM_INT_MASK_TFF_IM_SHIFT (6U) |
#define | EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK) |
#define | EMVSIM_INT_MASK_TDT_IM_MASK (0x80U) |
#define | EMVSIM_INT_MASK_TDT_IM_SHIFT (7U) |
#define | EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK) |
#define | EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U) |
#define | EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U) |
#define | EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK) |
#define | EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U) |
#define | EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U) |
#define | EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK) |
#define | EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U) |
#define | EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U) |
#define | EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK) |
#define | EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U) |
#define | EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U) |
#define | EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK) |
#define | EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U) |
#define | EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U) |
#define | EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK) |
#define | EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U) |
#define | EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U) |
#define | EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK) |
#define | EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U) |
#define | EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U) |
#define | EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK) |
#define | EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) |
#define | EMVSIM_INT_MASK_PEF_IM_SHIFT (15U) |
#define | EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK) |
RX_THD - Receiver Threshold Register | |
#define | EMVSIM_RX_THD_RDT_MASK (0xFU) |
#define | EMVSIM_RX_THD_RDT_SHIFT (0U) |
#define | EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK) |
#define | EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U) |
#define | EMVSIM_RX_THD_RNCK_THD_SHIFT (8U) |
#define | EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK) |
TX_THD - Transmitter Threshold Register | |
#define | EMVSIM_TX_THD_TDT_MASK (0xFU) |
#define | EMVSIM_TX_THD_TDT_SHIFT (0U) |
#define | EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK) |
#define | EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U) |
#define | EMVSIM_TX_THD_TNCK_THD_SHIFT (8U) |
#define | EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK) |
RX_STATUS - Receive Status Register | |
#define | EMVSIM_RX_STATUS_RFO_MASK (0x1U) |
#define | EMVSIM_RX_STATUS_RFO_SHIFT (0U) |
#define | EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK) |
#define | EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U) |
#define | EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U) |
#define | EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK) |
#define | EMVSIM_RX_STATUS_RDTF_MASK (0x20U) |
#define | EMVSIM_RX_STATUS_RDTF_SHIFT (5U) |
#define | EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK) |
#define | EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U) |
#define | EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U) |
#define | EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK) |
#define | EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U) |
#define | EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U) |
#define | EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK) |
#define | EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U) |
#define | EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U) |
#define | EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK) |
#define | EMVSIM_RX_STATUS_RTE_MASK (0x200U) |
#define | EMVSIM_RX_STATUS_RTE_SHIFT (9U) |
#define | EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK) |
#define | EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U) |
#define | EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U) |
#define | EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK) |
#define | EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U) |
#define | EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U) |
#define | EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK) |
#define | EMVSIM_RX_STATUS_PEF_MASK (0x1000U) |
#define | EMVSIM_RX_STATUS_PEF_SHIFT (12U) |
#define | EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK) |
#define | EMVSIM_RX_STATUS_FEF_MASK (0x2000U) |
#define | EMVSIM_RX_STATUS_FEF_SHIFT (13U) |
#define | EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK) |
#define | EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U) |
#define | EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U) |
#define | EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK) |
#define | EMVSIM_RX_STATUS_RX_CNT_MASK (0xF000000U) |
#define | EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U) |
#define | EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK) |
TX_STATUS - Transmitter Status Register | |
#define | EMVSIM_TX_STATUS_TNTE_MASK (0x1U) |
#define | EMVSIM_TX_STATUS_TNTE_SHIFT (0U) |
#define | EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK) |
#define | EMVSIM_TX_STATUS_TFE_MASK (0x8U) |
#define | EMVSIM_TX_STATUS_TFE_SHIFT (3U) |
#define | EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK) |
#define | EMVSIM_TX_STATUS_ETCF_MASK (0x10U) |
#define | EMVSIM_TX_STATUS_ETCF_SHIFT (4U) |
#define | EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK) |
#define | EMVSIM_TX_STATUS_TCF_MASK (0x20U) |
#define | EMVSIM_TX_STATUS_TCF_SHIFT (5U) |
#define | EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK) |
#define | EMVSIM_TX_STATUS_TFF_MASK (0x40U) |
#define | EMVSIM_TX_STATUS_TFF_SHIFT (6U) |
#define | EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK) |
#define | EMVSIM_TX_STATUS_TDTF_MASK (0x80U) |
#define | EMVSIM_TX_STATUS_TDTF_SHIFT (7U) |
#define | EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK) |
#define | EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U) |
#define | EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U) |
#define | EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK) |
#define | EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U) |
#define | EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U) |
#define | EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK) |
#define | EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U) |
#define | EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U) |
#define | EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK) |
#define | EMVSIM_TX_STATUS_TX_CNT_MASK (0xF000000U) |
#define | EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U) |
#define | EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK) |
PCSR - Port Control and Status Register | |
#define | EMVSIM_PCSR_SAPD_MASK (0x1U) |
#define | EMVSIM_PCSR_SAPD_SHIFT (0U) |
#define | EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK) |
#define | EMVSIM_PCSR_SVCC_EN_MASK (0x2U) |
#define | EMVSIM_PCSR_SVCC_EN_SHIFT (1U) |
#define | EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK) |
#define | EMVSIM_PCSR_VCCENP_MASK (0x4U) |
#define | EMVSIM_PCSR_VCCENP_SHIFT (2U) |
#define | EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK) |
#define | EMVSIM_PCSR_SRST_MASK (0x8U) |
#define | EMVSIM_PCSR_SRST_SHIFT (3U) |
#define | EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK) |
#define | EMVSIM_PCSR_SCEN_MASK (0x10U) |
#define | EMVSIM_PCSR_SCEN_SHIFT (4U) |
#define | EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK) |
#define | EMVSIM_PCSR_SCSP_MASK (0x20U) |
#define | EMVSIM_PCSR_SCSP_SHIFT (5U) |
#define | EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK) |
#define | EMVSIM_PCSR_SPD_MASK (0x80U) |
#define | EMVSIM_PCSR_SPD_SHIFT (7U) |
#define | EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK) |
#define | EMVSIM_PCSR_SPDIM_MASK (0x1000000U) |
#define | EMVSIM_PCSR_SPDIM_SHIFT (24U) |
#define | EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK) |
#define | EMVSIM_PCSR_SPDIF_MASK (0x2000000U) |
#define | EMVSIM_PCSR_SPDIF_SHIFT (25U) |
#define | EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK) |
#define | EMVSIM_PCSR_SPDP_MASK (0x4000000U) |
#define | EMVSIM_PCSR_SPDP_SHIFT (26U) |
#define | EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK) |
#define | EMVSIM_PCSR_SPDES_MASK (0x8000000U) |
#define | EMVSIM_PCSR_SPDES_SHIFT (27U) |
#define | EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK) |
RX_BUF - Receive Data Read Buffer | |
#define | EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU) |
#define | EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U) |
#define | EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK) |
TX_BUF - Transmit Data Buffer | |
#define | EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU) |
#define | EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U) |
#define | EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK) |
TX_GETU - Transmitter Guard ETU Value Register | |
#define | EMVSIM_TX_GETU_GETU_MASK (0xFFU) |
#define | EMVSIM_TX_GETU_GETU_SHIFT (0U) |
#define | EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK) |
CWT_VAL - Character Wait Time Value Register | |
#define | EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU) |
#define | EMVSIM_CWT_VAL_CWT_SHIFT (0U) |
#define | EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK) |
BWT_VAL - Block Wait Time Value Register | |
#define | EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU) |
#define | EMVSIM_BWT_VAL_BWT_SHIFT (0U) |
#define | EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK) |
BGT_VAL - Block Guard Time Value Register | |
#define | EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU) |
#define | EMVSIM_BGT_VAL_BGT_SHIFT (0U) |
#define | EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK) |
GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register | |
#define | EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU) |
#define | EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U) |
#define | EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK) |
GPCNT1_VAL - General Purpose Counter 1 Timeout Value | |
#define | EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) |
#define | EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U) |
#define | EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK) |
FILT - Input Filter Register | |
#define | ENC_FILT_FILT_PER_MASK (0xFFU) |
#define | ENC_FILT_FILT_PER_SHIFT (0U) |
#define | ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) |
#define | ENC_FILT_FILT_CNT_MASK (0x700U) |
#define | ENC_FILT_FILT_CNT_SHIFT (8U) |
#define | ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) |
#define | ENC_FILT_FILT_PRSC_MASK (0xE000U) |
#define | ENC_FILT_FILT_PRSC_SHIFT (13U) |
#define | ENC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK) |
WTR - Watchdog Timeout Register | |
#define | ENC_WTR_WDOG_MASK (0xFFFFU) |
#define | ENC_WTR_WDOG_SHIFT (0U) |
#define | ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) |
POSD - Position Difference Counter Register | |
#define | ENC_POSD_POSD_MASK (0xFFFFU) |
#define | ENC_POSD_POSD_SHIFT (0U) |
#define | ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) |
POSDH - Position Difference Hold Register | |
#define | ENC_POSDH_POSDH_MASK (0xFFFFU) |
#define | ENC_POSDH_POSDH_SHIFT (0U) |
#define | ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) |
REV - Revolution Counter Register | |
#define | ENC_REV_REV_MASK (0xFFFFU) |
#define | ENC_REV_REV_SHIFT (0U) |
#define | ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) |
REVH - Revolution Hold Register | |
#define | ENC_REVH_REVH_MASK (0xFFFFU) |
#define | ENC_REVH_REVH_SHIFT (0U) |
#define | ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) |
UPOS - Upper Position Counter Register | |
#define | ENC_UPOS_POS_MASK (0xFFFFU) |
#define | ENC_UPOS_POS_SHIFT (0U) |
#define | ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) |
LPOS - Lower Position Counter Register | |
#define | ENC_LPOS_POS_MASK (0xFFFFU) |
#define | ENC_LPOS_POS_SHIFT (0U) |
#define | ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) |
UPOSH - Upper Position Hold Register | |
#define | ENC_UPOSH_POSH_MASK (0xFFFFU) |
#define | ENC_UPOSH_POSH_SHIFT (0U) |
#define | ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) |
LPOSH - Lower Position Hold Register | |
#define | ENC_LPOSH_POSH_MASK (0xFFFFU) |
#define | ENC_LPOSH_POSH_SHIFT (0U) |
#define | ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) |
UINIT - Upper Initialization Register | |
#define | ENC_UINIT_INIT_MASK (0xFFFFU) |
#define | ENC_UINIT_INIT_SHIFT (0U) |
#define | ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) |
LINIT - Lower Initialization Register | |
#define | ENC_LINIT_INIT_MASK (0xFFFFU) |
#define | ENC_LINIT_INIT_SHIFT (0U) |
#define | ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) |
IMR - Input Monitor Register | |
#define | ENC_IMR_HOME_MASK (0x1U) |
#define | ENC_IMR_HOME_SHIFT (0U) |
#define | ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) |
#define | ENC_IMR_INDEX_MASK (0x2U) |
#define | ENC_IMR_INDEX_SHIFT (1U) |
#define | ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) |
#define | ENC_IMR_PHB_MASK (0x4U) |
#define | ENC_IMR_PHB_SHIFT (2U) |
#define | ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) |
#define | ENC_IMR_PHA_MASK (0x8U) |
#define | ENC_IMR_PHA_SHIFT (3U) |
#define | ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) |
#define | ENC_IMR_FHOM_MASK (0x10U) |
#define | ENC_IMR_FHOM_SHIFT (4U) |
#define | ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) |
#define | ENC_IMR_FIND_MASK (0x20U) |
#define | ENC_IMR_FIND_SHIFT (5U) |
#define | ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) |
#define | ENC_IMR_FPHB_MASK (0x40U) |
#define | ENC_IMR_FPHB_SHIFT (6U) |
#define | ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) |
#define | ENC_IMR_FPHA_MASK (0x80U) |
#define | ENC_IMR_FPHA_SHIFT (7U) |
#define | ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) |
TST - Test Register | |
#define | ENC_TST_TEST_COUNT_MASK (0xFFU) |
#define | ENC_TST_TEST_COUNT_SHIFT (0U) |
#define | ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) |
#define | ENC_TST_TEST_PERIOD_MASK (0x1F00U) |
#define | ENC_TST_TEST_PERIOD_SHIFT (8U) |
#define | ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) |
#define | ENC_TST_QDN_MASK (0x2000U) |
#define | ENC_TST_QDN_SHIFT (13U) |
#define | ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) |
#define | ENC_TST_TCE_MASK (0x4000U) |
#define | ENC_TST_TCE_SHIFT (14U) |
#define | ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) |
#define | ENC_TST_TEN_MASK (0x8000U) |
#define | ENC_TST_TEN_SHIFT (15U) |
#define | ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) |
UMOD - Upper Modulus Register | |
#define | ENC_UMOD_MOD_MASK (0xFFFFU) |
#define | ENC_UMOD_MOD_SHIFT (0U) |
#define | ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) |
LMOD - Lower Modulus Register | |
#define | ENC_LMOD_MOD_MASK (0xFFFFU) |
#define | ENC_LMOD_MOD_SHIFT (0U) |
#define | ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) |
UCOMP - Upper Position Compare Register | |
#define | ENC_UCOMP_COMP_MASK (0xFFFFU) |
#define | ENC_UCOMP_COMP_SHIFT (0U) |
#define | ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) |
LCOMP - Lower Position Compare Register | |
#define | ENC_LCOMP_COMP_MASK (0xFFFFU) |
#define | ENC_LCOMP_COMP_SHIFT (0U) |
#define | ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) |
LASTEDGE - Last Edge Time Register | |
#define | ENC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) |
#define | ENC_LASTEDGE_LASTEDGE_SHIFT (0U) |
#define | ENC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK) |
LASTEDGEH - Last Edge Time Hold Register | |
#define | ENC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) |
#define | ENC_LASTEDGEH_LASTEDGEH_SHIFT (0U) |
#define | ENC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK) |
POSDPER - Position Difference Period Counter Register | |
#define | ENC_POSDPER_POSDPER_MASK (0xFFFFU) |
#define | ENC_POSDPER_POSDPER_SHIFT (0U) |
#define | ENC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK) |
POSDPERBFR - Position Difference Period Buffer Register | |
#define | ENC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) |
#define | ENC_POSDPERBFR_POSDPERBFR_SHIFT (0U) |
#define | ENC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK) |
POSDPERH - Position Difference Period Hold Register | |
#define | ENC_POSDPERH_POSDPERH_MASK (0xFFFFU) |
#define | ENC_POSDPERH_POSDPERH_SHIFT (0U) |
#define | ENC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK) |
CTRL3 - Control 3 Register | |
#define | ENC_CTRL3_PMEN_MASK (0x1U) |
#define | ENC_CTRL3_PMEN_SHIFT (0U) |
#define | ENC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK) |
#define | ENC_CTRL3_PRSC_MASK (0xF0U) |
#define | ENC_CTRL3_PRSC_SHIFT (4U) |
#define | ENC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK) |
EIR - Interrupt Event Register | |
#define | ENET_EIR_RXB1_MASK (0x1U) |
#define | ENET_EIR_RXB1_SHIFT (0U) |
#define | ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK) |
#define | ENET_EIR_RXF1_MASK (0x2U) |
#define | ENET_EIR_RXF1_SHIFT (1U) |
#define | ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK) |
#define | ENET_EIR_TXB1_MASK (0x4U) |
#define | ENET_EIR_TXB1_SHIFT (2U) |
#define | ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK) |
#define | ENET_EIR_TXF1_MASK (0x8U) |
#define | ENET_EIR_TXF1_SHIFT (3U) |
#define | ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK) |
#define | ENET_EIR_RXB2_MASK (0x10U) |
#define | ENET_EIR_RXB2_SHIFT (4U) |
#define | ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK) |
#define | ENET_EIR_RXF2_MASK (0x20U) |
#define | ENET_EIR_RXF2_SHIFT (5U) |
#define | ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK) |
#define | ENET_EIR_TXB2_MASK (0x40U) |
#define | ENET_EIR_TXB2_SHIFT (6U) |
#define | ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK) |
#define | ENET_EIR_TXF2_MASK (0x80U) |
#define | ENET_EIR_TXF2_SHIFT (7U) |
#define | ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK) |
#define | ENET_EIR_RXFLUSH_0_MASK (0x1000U) |
#define | ENET_EIR_RXFLUSH_0_SHIFT (12U) |
#define | ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK) |
#define | ENET_EIR_RXFLUSH_1_MASK (0x2000U) |
#define | ENET_EIR_RXFLUSH_1_SHIFT (13U) |
#define | ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK) |
#define | ENET_EIR_RXFLUSH_2_MASK (0x4000U) |
#define | ENET_EIR_RXFLUSH_2_SHIFT (14U) |
#define | ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK) |
#define | ENET_EIR_TS_TIMER_MASK (0x8000U) |
#define | ENET_EIR_TS_TIMER_SHIFT (15U) |
#define | ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) |
#define | ENET_EIR_TS_AVAIL_MASK (0x10000U) |
#define | ENET_EIR_TS_AVAIL_SHIFT (16U) |
#define | ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) |
#define | ENET_EIR_WAKEUP_MASK (0x20000U) |
#define | ENET_EIR_WAKEUP_SHIFT (17U) |
#define | ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) |
#define | ENET_EIR_PLR_MASK (0x40000U) |
#define | ENET_EIR_PLR_SHIFT (18U) |
#define | ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) |
#define | ENET_EIR_UN_MASK (0x80000U) |
#define | ENET_EIR_UN_SHIFT (19U) |
#define | ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) |
#define | ENET_EIR_RL_MASK (0x100000U) |
#define | ENET_EIR_RL_SHIFT (20U) |
#define | ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) |
#define | ENET_EIR_LC_MASK (0x200000U) |
#define | ENET_EIR_LC_SHIFT (21U) |
#define | ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) |
#define | ENET_EIR_EBERR_MASK (0x400000U) |
#define | ENET_EIR_EBERR_SHIFT (22U) |
#define | ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) |
#define | ENET_EIR_MII_MASK (0x800000U) |
#define | ENET_EIR_MII_SHIFT (23U) |
#define | ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) |
#define | ENET_EIR_RXB_MASK (0x1000000U) |
#define | ENET_EIR_RXB_SHIFT (24U) |
#define | ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) |
#define | ENET_EIR_RXF_MASK (0x2000000U) |
#define | ENET_EIR_RXF_SHIFT (25U) |
#define | ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) |
#define | ENET_EIR_TXB_MASK (0x4000000U) |
#define | ENET_EIR_TXB_SHIFT (26U) |
#define | ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) |
#define | ENET_EIR_TXF_MASK (0x8000000U) |
#define | ENET_EIR_TXF_SHIFT (27U) |
#define | ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) |
#define | ENET_EIR_GRA_MASK (0x10000000U) |
#define | ENET_EIR_GRA_SHIFT (28U) |
#define | ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) |
#define | ENET_EIR_BABT_MASK (0x20000000U) |
#define | ENET_EIR_BABT_SHIFT (29U) |
#define | ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) |
#define | ENET_EIR_BABR_MASK (0x40000000U) |
#define | ENET_EIR_BABR_SHIFT (30U) |
#define | ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) |
EIMR - Interrupt Mask Register | |
#define | ENET_EIMR_RXB1_MASK (0x1U) |
#define | ENET_EIMR_RXB1_SHIFT (0U) |
#define | ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK) |
#define | ENET_EIMR_RXF1_MASK (0x2U) |
#define | ENET_EIMR_RXF1_SHIFT (1U) |
#define | ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK) |
#define | ENET_EIMR_TXB1_MASK (0x4U) |
#define | ENET_EIMR_TXB1_SHIFT (2U) |
#define | ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK) |
#define | ENET_EIMR_TXF1_MASK (0x8U) |
#define | ENET_EIMR_TXF1_SHIFT (3U) |
#define | ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK) |
#define | ENET_EIMR_RXB2_MASK (0x10U) |
#define | ENET_EIMR_RXB2_SHIFT (4U) |
#define | ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK) |
#define | ENET_EIMR_RXF2_MASK (0x20U) |
#define | ENET_EIMR_RXF2_SHIFT (5U) |
#define | ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK) |
#define | ENET_EIMR_TXB2_MASK (0x40U) |
#define | ENET_EIMR_TXB2_SHIFT (6U) |
#define | ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK) |
#define | ENET_EIMR_TXF2_MASK (0x80U) |
#define | ENET_EIMR_TXF2_SHIFT (7U) |
#define | ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK) |
#define | ENET_EIMR_RXFLUSH_0_MASK (0x1000U) |
#define | ENET_EIMR_RXFLUSH_0_SHIFT (12U) |
#define | ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK) |
#define | ENET_EIMR_RXFLUSH_1_MASK (0x2000U) |
#define | ENET_EIMR_RXFLUSH_1_SHIFT (13U) |
#define | ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK) |
#define | ENET_EIMR_RXFLUSH_2_MASK (0x4000U) |
#define | ENET_EIMR_RXFLUSH_2_SHIFT (14U) |
#define | ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK) |
#define | ENET_EIMR_TS_TIMER_MASK (0x8000U) |
#define | ENET_EIMR_TS_TIMER_SHIFT (15U) |
#define | ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) |
#define | ENET_EIMR_TS_AVAIL_MASK (0x10000U) |
#define | ENET_EIMR_TS_AVAIL_SHIFT (16U) |
#define | ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) |
#define | ENET_EIMR_WAKEUP_MASK (0x20000U) |
#define | ENET_EIMR_WAKEUP_SHIFT (17U) |
#define | ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) |
#define | ENET_EIMR_PLR_MASK (0x40000U) |
#define | ENET_EIMR_PLR_SHIFT (18U) |
#define | ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) |
#define | ENET_EIMR_UN_MASK (0x80000U) |
#define | ENET_EIMR_UN_SHIFT (19U) |
#define | ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) |
#define | ENET_EIMR_RL_MASK (0x100000U) |
#define | ENET_EIMR_RL_SHIFT (20U) |
#define | ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) |
#define | ENET_EIMR_LC_MASK (0x200000U) |
#define | ENET_EIMR_LC_SHIFT (21U) |
#define | ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) |
#define | ENET_EIMR_EBERR_MASK (0x400000U) |
#define | ENET_EIMR_EBERR_SHIFT (22U) |
#define | ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) |
#define | ENET_EIMR_MII_MASK (0x800000U) |
#define | ENET_EIMR_MII_SHIFT (23U) |
#define | ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) |
#define | ENET_EIMR_RXB_MASK (0x1000000U) |
#define | ENET_EIMR_RXB_SHIFT (24U) |
#define | ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) |
#define | ENET_EIMR_RXF_MASK (0x2000000U) |
#define | ENET_EIMR_RXF_SHIFT (25U) |
#define | ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) |
#define | ENET_EIMR_TXB_MASK (0x4000000U) |
#define | ENET_EIMR_TXB_SHIFT (26U) |
#define | ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
#define | ENET_EIMR_TXF_MASK (0x8000000U) |
#define | ENET_EIMR_TXF_SHIFT (27U) |
#define | ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
#define | ENET_EIMR_GRA_MASK (0x10000000U) |
#define | ENET_EIMR_GRA_SHIFT (28U) |
#define | ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
#define | ENET_EIMR_BABT_MASK (0x20000000U) |
#define | ENET_EIMR_BABT_SHIFT (29U) |
#define | ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
#define | ENET_EIMR_BABR_MASK (0x40000000U) |
#define | ENET_EIMR_BABR_SHIFT (30U) |
#define | ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
RDAR - Receive Descriptor Active Register - Ring 0 | |
#define | ENET_RDAR_RDAR_MASK (0x1000000U) |
#define | ENET_RDAR_RDAR_SHIFT (24U) |
#define | ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) |
TDAR - Transmit Descriptor Active Register - Ring 0 | |
#define | ENET_TDAR_TDAR_MASK (0x1000000U) |
#define | ENET_TDAR_TDAR_SHIFT (24U) |
#define | ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) |
ECR - Ethernet Control Register | |
#define | ENET_ECR_RESET_MASK (0x1U) |
#define | ENET_ECR_RESET_SHIFT (0U) |
#define | ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) |
#define | ENET_ECR_ETHEREN_MASK (0x2U) |
#define | ENET_ECR_ETHEREN_SHIFT (1U) |
#define | ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
#define | ENET_ECR_MAGICEN_MASK (0x4U) |
#define | ENET_ECR_MAGICEN_SHIFT (2U) |
#define | ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
#define | ENET_ECR_SLEEP_MASK (0x8U) |
#define | ENET_ECR_SLEEP_SHIFT (3U) |
#define | ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
#define | ENET_ECR_EN1588_MASK (0x10U) |
#define | ENET_ECR_EN1588_SHIFT (4U) |
#define | ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
#define | ENET_ECR_SPEED_MASK (0x20U) |
#define | ENET_ECR_SPEED_SHIFT (5U) |
#define | ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK) |
#define | ENET_ECR_DBGEN_MASK (0x40U) |
#define | ENET_ECR_DBGEN_SHIFT (6U) |
#define | ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
#define | ENET_ECR_DBSWP_MASK (0x100U) |
#define | ENET_ECR_DBSWP_SHIFT (8U) |
#define | ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
#define | ENET_ECR_SVLANEN_MASK (0x200U) |
#define | ENET_ECR_SVLANEN_SHIFT (9U) |
#define | ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK) |
#define | ENET_ECR_VLANUSE2ND_MASK (0x400U) |
#define | ENET_ECR_VLANUSE2ND_SHIFT (10U) |
#define | ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK) |
#define | ENET_ECR_SVLANDBL_MASK (0x800U) |
#define | ENET_ECR_SVLANDBL_SHIFT (11U) |
#define | ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK) |
#define | ENET_ECR_TXC_DLY_MASK (0x10000U) |
#define | ENET_ECR_TXC_DLY_SHIFT (16U) |
#define | ENET_ECR_TXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK) |
MMFR - MII Management Frame Register | |
#define | ENET_MMFR_DATA_MASK (0xFFFFU) |
#define | ENET_MMFR_DATA_SHIFT (0U) |
#define | ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) |
#define | ENET_MMFR_TA_MASK (0x30000U) |
#define | ENET_MMFR_TA_SHIFT (16U) |
#define | ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) |
#define | ENET_MMFR_RA_MASK (0x7C0000U) |
#define | ENET_MMFR_RA_SHIFT (18U) |
#define | ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) |
#define | ENET_MMFR_PA_MASK (0xF800000U) |
#define | ENET_MMFR_PA_SHIFT (23U) |
#define | ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) |
#define | ENET_MMFR_OP_MASK (0x30000000U) |
#define | ENET_MMFR_OP_SHIFT (28U) |
#define | ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) |
#define | ENET_MMFR_ST_MASK (0xC0000000U) |
#define | ENET_MMFR_ST_SHIFT (30U) |
#define | ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) |
MSCR - MII Speed Control Register | |
#define | ENET_MSCR_MII_SPEED_MASK (0x7EU) |
#define | ENET_MSCR_MII_SPEED_SHIFT (1U) |
#define | ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) |
#define | ENET_MSCR_DIS_PRE_MASK (0x80U) |
#define | ENET_MSCR_DIS_PRE_SHIFT (7U) |
#define | ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
#define | ENET_MSCR_HOLDTIME_MASK (0x700U) |
#define | ENET_MSCR_HOLDTIME_SHIFT (8U) |
#define | ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
MIBC - MIB Control Register | |
#define | ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) |
#define | ENET_MIBC_MIB_CLEAR_SHIFT (29U) |
#define | ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
#define | ENET_MIBC_MIB_IDLE_MASK (0x40000000U) |
#define | ENET_MIBC_MIB_IDLE_SHIFT (30U) |
#define | ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
#define | ENET_MIBC_MIB_DIS_MASK (0x80000000U) |
#define | ENET_MIBC_MIB_DIS_SHIFT (31U) |
#define | ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
RCR - Receive Control Register | |
#define | ENET_RCR_LOOP_MASK (0x1U) |
#define | ENET_RCR_LOOP_SHIFT (0U) |
#define | ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
#define | ENET_RCR_DRT_MASK (0x2U) |
#define | ENET_RCR_DRT_SHIFT (1U) |
#define | ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
#define | ENET_RCR_MII_MODE_MASK (0x4U) |
#define | ENET_RCR_MII_MODE_SHIFT (2U) |
#define | ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
#define | ENET_RCR_PROM_MASK (0x8U) |
#define | ENET_RCR_PROM_SHIFT (3U) |
#define | ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
#define | ENET_RCR_BC_REJ_MASK (0x10U) |
#define | ENET_RCR_BC_REJ_SHIFT (4U) |
#define | ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) |
#define | ENET_RCR_FCE_MASK (0x20U) |
#define | ENET_RCR_FCE_SHIFT (5U) |
#define | ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) |
#define | ENET_RCR_RGMII_EN_MASK (0x40U) |
#define | ENET_RCR_RGMII_EN_SHIFT (6U) |
#define | ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK) |
#define | ENET_RCR_RMII_MODE_MASK (0x100U) |
#define | ENET_RCR_RMII_MODE_SHIFT (8U) |
#define | ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
#define | ENET_RCR_RMII_10T_MASK (0x200U) |
#define | ENET_RCR_RMII_10T_SHIFT (9U) |
#define | ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
#define | ENET_RCR_PADEN_MASK (0x1000U) |
#define | ENET_RCR_PADEN_SHIFT (12U) |
#define | ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
#define | ENET_RCR_PAUFWD_MASK (0x2000U) |
#define | ENET_RCR_PAUFWD_SHIFT (13U) |
#define | ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
#define | ENET_RCR_CRCFWD_MASK (0x4000U) |
#define | ENET_RCR_CRCFWD_SHIFT (14U) |
#define | ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
#define | ENET_RCR_CFEN_MASK (0x8000U) |
#define | ENET_RCR_CFEN_SHIFT (15U) |
#define | ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
#define | ENET_RCR_MAX_FL_MASK (0x3FFF0000U) |
#define | ENET_RCR_MAX_FL_SHIFT (16U) |
#define | ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) |
#define | ENET_RCR_NLC_MASK (0x40000000U) |
#define | ENET_RCR_NLC_SHIFT (30U) |
#define | ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
#define | ENET_RCR_GRS_MASK (0x80000000U) |
#define | ENET_RCR_GRS_SHIFT (31U) |
#define | ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) |
TCR - Transmit Control Register | |
#define | ENET_TCR_GTS_MASK (0x1U) |
#define | ENET_TCR_GTS_SHIFT (0U) |
#define | ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) |
#define | ENET_TCR_FDEN_MASK (0x4U) |
#define | ENET_TCR_FDEN_SHIFT (2U) |
#define | ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) |
#define | ENET_TCR_TFC_PAUSE_MASK (0x8U) |
#define | ENET_TCR_TFC_PAUSE_SHIFT (3U) |
#define | ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
#define | ENET_TCR_RFC_PAUSE_MASK (0x10U) |
#define | ENET_TCR_RFC_PAUSE_SHIFT (4U) |
#define | ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) |
#define | ENET_TCR_ADDSEL_MASK (0xE0U) |
#define | ENET_TCR_ADDSEL_SHIFT (5U) |
#define | ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
#define | ENET_TCR_ADDINS_MASK (0x100U) |
#define | ENET_TCR_ADDINS_SHIFT (8U) |
#define | ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
#define | ENET_TCR_CRCFWD_MASK (0x200U) |
#define | ENET_TCR_CRCFWD_SHIFT (9U) |
#define | ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
PALR - Physical Address Lower Register | |
#define | ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) |
#define | ENET_PALR_PADDR1_SHIFT (0U) |
#define | ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) |
PAUR - Physical Address Upper Register | |
#define | ENET_PAUR_TYPE_MASK (0xFFFFU) |
#define | ENET_PAUR_TYPE_SHIFT (0U) |
#define | ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) |
#define | ENET_PAUR_PADDR2_MASK (0xFFFF0000U) |
#define | ENET_PAUR_PADDR2_SHIFT (16U) |
#define | ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) |
OPD - Opcode/Pause Duration Register | |
#define | ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) |
#define | ENET_OPD_PAUSE_DUR_SHIFT (0U) |
#define | ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) |
#define | ENET_OPD_OPCODE_MASK (0xFFFF0000U) |
#define | ENET_OPD_OPCODE_SHIFT (16U) |
#define | ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) |
TXIC - Transmit Interrupt Coalescing Register | |
#define | ENET_TXIC_ICTT_MASK (0xFFFFU) |
#define | ENET_TXIC_ICTT_SHIFT (0U) |
#define | ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) |
#define | ENET_TXIC_ICFT_MASK (0xFF00000U) |
#define | ENET_TXIC_ICFT_SHIFT (20U) |
#define | ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) |
#define | ENET_TXIC_ICCS_MASK (0x40000000U) |
#define | ENET_TXIC_ICCS_SHIFT (30U) |
#define | ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) |
#define | ENET_TXIC_ICEN_MASK (0x80000000U) |
#define | ENET_TXIC_ICEN_SHIFT (31U) |
#define | ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) |
RXIC - Receive Interrupt Coalescing Register | |
#define | ENET_RXIC_ICTT_MASK (0xFFFFU) |
#define | ENET_RXIC_ICTT_SHIFT (0U) |
#define | ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) |
#define | ENET_RXIC_ICFT_MASK (0xFF00000U) |
#define | ENET_RXIC_ICFT_SHIFT (20U) |
#define | ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) |
#define | ENET_RXIC_ICCS_MASK (0x40000000U) |
#define | ENET_RXIC_ICCS_SHIFT (30U) |
#define | ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) |
#define | ENET_RXIC_ICEN_MASK (0x80000000U) |
#define | ENET_RXIC_ICEN_SHIFT (31U) |
#define | ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) |
IAUR - Descriptor Individual Upper Address Register | |
#define | ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) |
#define | ENET_IAUR_IADDR1_SHIFT (0U) |
#define | ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) |
IALR - Descriptor Individual Lower Address Register | |
#define | ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) |
#define | ENET_IALR_IADDR2_SHIFT (0U) |
#define | ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) |
GAUR - Descriptor Group Upper Address Register | |
#define | ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) |
#define | ENET_GAUR_GADDR1_SHIFT (0U) |
#define | ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) |
GALR - Descriptor Group Lower Address Register | |
#define | ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) |
#define | ENET_GALR_GADDR2_SHIFT (0U) |
#define | ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) |
TFWR - Transmit FIFO Watermark Register | |
#define | ENET_TFWR_TFWR_MASK (0x3FU) |
#define | ENET_TFWR_TFWR_SHIFT (0U) |
#define | ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
#define | ENET_TFWR_STRFWD_MASK (0x100U) |
#define | ENET_TFWR_STRFWD_SHIFT (8U) |
#define | ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
RDSR1 - Receive Descriptor Ring 1 Start Register | |
#define | ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U) |
#define | ENET_RDSR1_R_DES_START_SHIFT (3U) |
#define | ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK) |
TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register | |
#define | ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U) |
#define | ENET_TDSR1_X_DES_START_SHIFT (3U) |
#define | ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK) |
MRBR1 - Maximum Receive Buffer Size Register - Ring 1 | |
#define | ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U) |
#define | ENET_MRBR1_R_BUF_SIZE_SHIFT (4U) |
#define | ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK) |
RDSR2 - Receive Descriptor Ring 2 Start Register | |
#define | ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U) |
#define | ENET_RDSR2_R_DES_START_SHIFT (3U) |
#define | ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK) |
TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register | |
#define | ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U) |
#define | ENET_TDSR2_X_DES_START_SHIFT (3U) |
#define | ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK) |
MRBR2 - Maximum Receive Buffer Size Register - Ring 2 | |
#define | ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U) |
#define | ENET_MRBR2_R_BUF_SIZE_SHIFT (4U) |
#define | ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK) |
RDSR - Receive Descriptor Ring 0 Start Register | |
#define | ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) |
#define | ENET_RDSR_R_DES_START_SHIFT (3U) |
#define | ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) |
TDSR - Transmit Buffer Descriptor Ring 0 Start Register | |
#define | ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) |
#define | ENET_TDSR_X_DES_START_SHIFT (3U) |
#define | ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) |
MRBR - Maximum Receive Buffer Size Register - Ring 0 | |
#define | ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */ |
#define | ENET_MRBR_R_BUF_SIZE_SHIFT (4U) |
#define | ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */ |
RSFL - Receive FIFO Section Full Threshold | |
#define | ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
#define | ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) |
#define | ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
RSEM - Receive FIFO Section Empty Threshold | |
#define | ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
#define | ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) |
#define | ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
#define | ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) |
#define | ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) |
#define | ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) |
RAEM - Receive FIFO Almost Empty Threshold | |
#define | ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
#define | ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) |
#define | ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
RAFL - Receive FIFO Almost Full Threshold | |
#define | ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
#define | ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) |
#define | ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
TSEM - Transmit FIFO Section Empty Threshold | |
#define | ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
#define | ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) |
#define | ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
TAEM - Transmit FIFO Almost Empty Threshold | |
#define | ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
#define | ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) |
#define | ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
TAFL - Transmit FIFO Almost Full Threshold | |
#define | ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
#define | ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) |
#define | ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ |
TIPG - Transmit Inter-Packet Gap | |
#define | ENET_TIPG_IPG_MASK (0x1FU) |
#define | ENET_TIPG_IPG_SHIFT (0U) |
#define | ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) |
FTRL - Frame Truncation Length | |
#define | ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) |
#define | ENET_FTRL_TRUNC_FL_SHIFT (0U) |
#define | ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) |
TACC - Transmit Accelerator Function Configuration | |
#define | ENET_TACC_SHIFT16_MASK (0x1U) |
#define | ENET_TACC_SHIFT16_SHIFT (0U) |
#define | ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
#define | ENET_TACC_IPCHK_MASK (0x8U) |
#define | ENET_TACC_IPCHK_SHIFT (3U) |
#define | ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
#define | ENET_TACC_PROCHK_MASK (0x10U) |
#define | ENET_TACC_PROCHK_SHIFT (4U) |
#define | ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
RACC - Receive Accelerator Function Configuration | |
#define | ENET_RACC_PADREM_MASK (0x1U) |
#define | ENET_RACC_PADREM_SHIFT (0U) |
#define | ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
#define | ENET_RACC_IPDIS_MASK (0x2U) |
#define | ENET_RACC_IPDIS_SHIFT (1U) |
#define | ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
#define | ENET_RACC_PRODIS_MASK (0x4U) |
#define | ENET_RACC_PRODIS_SHIFT (2U) |
#define | ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
#define | ENET_RACC_LINEDIS_MASK (0x40U) |
#define | ENET_RACC_LINEDIS_SHIFT (6U) |
#define | ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
#define | ENET_RACC_SHIFT16_MASK (0x80U) |
#define | ENET_RACC_SHIFT16_SHIFT (7U) |
#define | ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
RCMR - Receive Classification Match Register for Class n | |
#define | ENET_RCMR_CMP0_MASK (0x7U) |
#define | ENET_RCMR_CMP0_SHIFT (0U) |
#define | ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK) |
#define | ENET_RCMR_CMP1_MASK (0x70U) |
#define | ENET_RCMR_CMP1_SHIFT (4U) |
#define | ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK) |
#define | ENET_RCMR_CMP2_MASK (0x700U) |
#define | ENET_RCMR_CMP2_SHIFT (8U) |
#define | ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK) |
#define | ENET_RCMR_CMP3_MASK (0x7000U) |
#define | ENET_RCMR_CMP3_SHIFT (12U) |
#define | ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK) |
#define | ENET_RCMR_MATCHEN_MASK (0x10000U) |
#define | ENET_RCMR_MATCHEN_SHIFT (16U) |
#define | ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK) |
DMACFG - DMA Class Based Configuration | |
#define | ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU) |
#define | ENET_DMACFG_IDLE_SLOPE_SHIFT (0U) |
#define | ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK) |
#define | ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U) |
#define | ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U) |
#define | ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK) |
#define | ENET_DMACFG_CALC_NOIPG_MASK (0x20000U) |
#define | ENET_DMACFG_CALC_NOIPG_SHIFT (17U) |
#define | ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK) |
RDAR1 - Receive Descriptor Active Register - Ring 1 | |
#define | ENET_RDAR1_RDAR_MASK (0x1000000U) |
#define | ENET_RDAR1_RDAR_SHIFT (24U) |
#define | ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK) |
TDAR1 - Transmit Descriptor Active Register - Ring 1 | |
#define | ENET_TDAR1_TDAR_MASK (0x1000000U) |
#define | ENET_TDAR1_TDAR_SHIFT (24U) |
#define | ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK) |
RDAR2 - Receive Descriptor Active Register - Ring 2 | |
#define | ENET_RDAR2_RDAR_MASK (0x1000000U) |
#define | ENET_RDAR2_RDAR_SHIFT (24U) |
#define | ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK) |
TDAR2 - Transmit Descriptor Active Register - Ring 2 | |
#define | ENET_TDAR2_TDAR_MASK (0x1000000U) |
#define | ENET_TDAR2_TDAR_SHIFT (24U) |
#define | ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK) |
QOS - QOS Scheme | |
#define | ENET_QOS_TX_SCHEME_MASK (0x7U) |
#define | ENET_QOS_TX_SCHEME_SHIFT (0U) |
#define | ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK) |
#define | ENET_QOS_RX_FLUSH0_MASK (0x8U) |
#define | ENET_QOS_RX_FLUSH0_SHIFT (3U) |
#define | ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK) |
#define | ENET_QOS_RX_FLUSH1_MASK (0x10U) |
#define | ENET_QOS_RX_FLUSH1_SHIFT (4U) |
#define | ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK) |
#define | ENET_QOS_RX_FLUSH2_MASK (0x20U) |
#define | ENET_QOS_RX_FLUSH2_SHIFT (5U) |
#define | ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK) |
RMON_T_PACKETS - Tx Packet Count Statistic Register | |
#define | ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) |
RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register | |
#define | ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) |
RMON_T_MC_PKT - Tx Multicast Packets Statistic Register | |
#define | ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) |
RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register | |
#define | ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) |
RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register | |
#define | ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) |
RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register | |
#define | ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) |
RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register | |
#define | ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) |
RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register | |
#define | ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) |
RMON_T_COL - Tx Collision Count Statistic Register | |
#define | ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_COL_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) |
RMON_T_P64 - Tx 64-Byte Packets Statistic Register | |
#define | ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_P64_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) |
RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register | |
#define | ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) |
RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register | |
#define | ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) |
RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register | |
#define | ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) |
RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register | |
#define | ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) |
RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register | |
#define | ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) |
RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register | |
#define | ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) |
#define | ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) |
#define | ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) |
RMON_T_OCTETS - Tx Octets Statistic Register | |
#define | ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) |
#define | ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) |
#define | ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) |
IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register | |
#define | ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) |
#define | ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) |
IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register | |
#define | ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_T_1COL_COUNT_SHIFT (0U) |
#define | ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) |
IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register | |
#define | ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) |
#define | ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) |
IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register | |
#define | ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_T_DEF_COUNT_SHIFT (0U) |
#define | ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) |
IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register | |
#define | ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) |
#define | ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) |
IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register | |
#define | ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) |
#define | ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) |
IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register | |
#define | ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) |
#define | ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) |
IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register | |
#define | ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) |
#define | ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) |
IEEE_T_SQE - Reserved Statistic Register | |
#define | ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_T_SQE_COUNT_SHIFT (0U) |
#define | ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) |
IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register | |
#define | ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) |
#define | ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) |
IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register | |
#define | ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) |
#define | ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) |
#define | ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) |
RMON_R_PACKETS - Rx Packet Count Statistic Register | |
#define | ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) |
RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register | |
#define | ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) |
RMON_R_MC_PKT - Rx Multicast Packets Statistic Register | |
#define | ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) |
RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register | |
#define | ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) |
RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register | |
#define | ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) |
RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register | |
#define | ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) |
RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register | |
#define | ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_FRAG_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) |
RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register | |
#define | ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_JAB_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) |
RMON_R_P64 - Rx 64-Byte Packets Statistic Register | |
#define | ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_P64_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) |
RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register | |
#define | ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) |
RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register | |
#define | ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) |
RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register | |
#define | ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) |
RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register | |
#define | ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) |
RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register | |
#define | ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) |
RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register | |
#define | ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) |
#define | ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) |
RMON_R_OCTETS - Rx Octets Statistic Register | |
#define | ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) |
#define | ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) |
#define | ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) |
IEEE_R_DROP - Frames not Counted Correctly Statistic Register | |
#define | ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_R_DROP_COUNT_SHIFT (0U) |
#define | ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) |
IEEE_R_FRAME_OK - Frames Received OK Statistic Register | |
#define | ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) |
#define | ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) |
IEEE_R_CRC - Frames Received with CRC Error Statistic Register | |
#define | ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_R_CRC_COUNT_SHIFT (0U) |
#define | ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) |
IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register | |
#define | ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) |
#define | ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) |
IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register | |
#define | ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) |
#define | ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) |
IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register | |
#define | ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) |
#define | ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) |
#define | ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) |
IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register | |
#define | ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) |
#define | ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) |
#define | ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) |
ATCR - Adjustable Timer Control Register | |
#define | ENET_ATCR_EN_MASK (0x1U) |
#define | ENET_ATCR_EN_SHIFT (0U) |
#define | ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
#define | ENET_ATCR_OFFEN_MASK (0x4U) |
#define | ENET_ATCR_OFFEN_SHIFT (2U) |
#define | ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
#define | ENET_ATCR_OFFRST_MASK (0x8U) |
#define | ENET_ATCR_OFFRST_SHIFT (3U) |
#define | ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
#define | ENET_ATCR_PEREN_MASK (0x10U) |
#define | ENET_ATCR_PEREN_SHIFT (4U) |
#define | ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
#define | ENET_ATCR_PINPER_MASK (0x80U) |
#define | ENET_ATCR_PINPER_SHIFT (7U) |
#define | ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
#define | ENET_ATCR_RESTART_MASK (0x200U) |
#define | ENET_ATCR_RESTART_SHIFT (9U) |
#define | ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) |
#define | ENET_ATCR_CAPTURE_MASK (0x800U) |
#define | ENET_ATCR_CAPTURE_SHIFT (11U) |
#define | ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
#define | ENET_ATCR_SLAVE_MASK (0x2000U) |
#define | ENET_ATCR_SLAVE_SHIFT (13U) |
#define | ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
ATVR - Timer Value Register | |
#define | ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) |
#define | ENET_ATVR_ATIME_SHIFT (0U) |
#define | ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) |
ATOFF - Timer Offset Register | |
#define | ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) |
#define | ENET_ATOFF_OFFSET_SHIFT (0U) |
#define | ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) |
ATPER - Timer Period Register | |
#define | ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) |
#define | ENET_ATPER_PERIOD_SHIFT (0U) |
#define | ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) |
ATCOR - Timer Correction Register | |
#define | ENET_ATCOR_COR_MASK (0x7FFFFFFFU) |
#define | ENET_ATCOR_COR_SHIFT (0U) |
#define | ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) |
ATINC - Time-Stamping Clock Period Register | |
#define | ENET_ATINC_INC_MASK (0x7FU) |
#define | ENET_ATINC_INC_SHIFT (0U) |
#define | ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) |
#define | ENET_ATINC_INC_CORR_MASK (0x7F00U) |
#define | ENET_ATINC_INC_CORR_SHIFT (8U) |
#define | ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) |
ATSTMP - Timestamp of Last Transmitted Frame | |
#define | ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) |
#define | ENET_ATSTMP_TIMESTAMP_SHIFT (0U) |
#define | ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) |
TGSR - Timer Global Status Register | |
#define | ENET_TGSR_TF0_MASK (0x1U) |
#define | ENET_TGSR_TF0_SHIFT (0U) |
#define | ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
#define | ENET_TGSR_TF1_MASK (0x2U) |
#define | ENET_TGSR_TF1_SHIFT (1U) |
#define | ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
#define | ENET_TGSR_TF2_MASK (0x4U) |
#define | ENET_TGSR_TF2_SHIFT (2U) |
#define | ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
#define | ENET_TGSR_TF3_MASK (0x8U) |
#define | ENET_TGSR_TF3_SHIFT (3U) |
#define | ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
TCSR - Timer Control Status Register | |
#define | ENET_TCSR_TDRE_MASK (0x1U) |
#define | ENET_TCSR_TDRE_SHIFT (0U) |
#define | ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
#define | ENET_TCSR_TMODE_MASK (0x3CU) |
#define | ENET_TCSR_TMODE_SHIFT (2U) |
#define | ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
#define | ENET_TCSR_TIE_MASK (0x40U) |
#define | ENET_TCSR_TIE_SHIFT (6U) |
#define | ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
#define | ENET_TCSR_TF_MASK (0x80U) |
#define | ENET_TCSR_TF_SHIFT (7U) |
#define | ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
#define | ENET_TCSR_TPWC_MASK (0xF800U) |
#define | ENET_TCSR_TPWC_SHIFT (11U) |
#define | ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) |
TCCR - Timer Compare Capture Register | |
#define | ENET_TCCR_TCC_MASK (0xFFFFFFFFU) |
#define | ENET_TCCR_TCC_SHIFT (0U) |
#define | ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) |
SERV - Service Register | |
#define | EWM_SERV_SERVICE_MASK (0xFFU) |
#define | EWM_SERV_SERVICE_SHIFT (0U) |
#define | EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) |
CMPL - Compare Low Register | |
#define | EWM_CMPL_COMPAREL_MASK (0xFFU) |
#define | EWM_CMPL_COMPAREL_SHIFT (0U) |
#define | EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) |
CMPH - Compare High Register | |
#define | EWM_CMPH_COMPAREH_MASK (0xFFU) |
#define | EWM_CMPH_COMPAREH_SHIFT (0U) |
#define | EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) |
CLKCTRL - Clock Control Register | |
#define | EWM_CLKCTRL_CLKSEL_MASK (0x3U) |
#define | EWM_CLKCTRL_CLKSEL_SHIFT (0U) |
#define | EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) |
CLKPRESCALER - Clock Prescaler Register | |
#define | EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) |
#define | EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) |
#define | EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) |
CTRL - FlexIO Control Register | |
#define | FLEXIO_CTRL_FLEXEN_MASK (0x1U) |
#define | FLEXIO_CTRL_FLEXEN_SHIFT (0U) |
#define | FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) |
#define | FLEXIO_CTRL_SWRST_MASK (0x2U) |
#define | FLEXIO_CTRL_SWRST_SHIFT (1U) |
#define | FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) |
#define | FLEXIO_CTRL_FASTACC_MASK (0x4U) |
#define | FLEXIO_CTRL_FASTACC_SHIFT (2U) |
#define | FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) |
#define | FLEXIO_CTRL_DBGE_MASK (0x40000000U) |
#define | FLEXIO_CTRL_DBGE_SHIFT (30U) |
#define | FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) |
#define | FLEXIO_CTRL_DOZEN_MASK (0x80000000U) |
#define | FLEXIO_CTRL_DOZEN_SHIFT (31U) |
#define | FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) |
PIN - Pin State Register | |
#define | FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) |
#define | FLEXIO_PIN_PDI_SHIFT (0U) |
#define | FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) |
SHIFTSTAT - Shifter Status Register | |
#define | FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) |
#define | FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) |
#define | FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) |
SHIFTERR - Shifter Error Register | |
#define | FLEXIO_SHIFTERR_SEF_MASK (0xFFU) |
#define | FLEXIO_SHIFTERR_SEF_SHIFT (0U) |
#define | FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) |
TIMSTAT - Timer Status Register | |
#define | FLEXIO_TIMSTAT_TSF_MASK (0xFFU) |
#define | FLEXIO_TIMSTAT_TSF_SHIFT (0U) |
#define | FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) |
SHIFTSIEN - Shifter Status Interrupt Enable | |
#define | FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) |
#define | FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) |
#define | FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) |
SHIFTEIEN - Shifter Error Interrupt Enable | |
#define | FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) |
#define | FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) |
#define | FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) |
TIMIEN - Timer Interrupt Enable Register | |
#define | FLEXIO_TIMIEN_TEIE_MASK (0xFFU) |
#define | FLEXIO_TIMIEN_TEIE_SHIFT (0U) |
#define | FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) |
SHIFTSDEN - Shifter Status DMA Enable | |
#define | FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) |
#define | FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) |
#define | FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) |
TIMERSDEN - Timer Status DMA Enable | |
#define | FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) |
#define | FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) |
#define | FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) |
SHIFTSTATE - Shifter State Register | |
#define | FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) |
#define | FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) |
#define | FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) |
SHIFTCTL - Shifter Control N Register | |
#define | FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) |
#define | FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) |
#define | FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) |
#define | FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) |
#define | FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) |
#define | FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) |
#define | FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) |
#define | FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) |
#define | FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) |
#define | FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) |
#define | FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) |
#define | FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) |
#define | FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) |
#define | FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) |
#define | FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) |
#define | FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) |
#define | FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) |
#define | FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) |
SHIFTCFG - Shifter Configuration N Register | |
#define | FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) |
#define | FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) |
#define | FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) |
#define | FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) |
#define | FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) |
#define | FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) |
#define | FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) |
#define | FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) |
#define | FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) |
#define | FLEXIO_SHIFTCFG_LATST_MASK (0x200U) |
#define | FLEXIO_SHIFTCFG_LATST_SHIFT (9U) |
#define | FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) |
#define | FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) |
#define | FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) |
#define | FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) |
SHIFTBUF - Shifter Buffer N Register | |
#define | FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) |
#define | FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) |
#define | FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) |
SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register | |
#define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) |
#define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) |
#define | FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) |
SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register | |
#define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) |
#define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) |
#define | FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) |
SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register | |
#define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) |
#define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) |
#define | FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) |
TIMCTL - Timer Control N Register | |
#define | FLEXIO_TIMCTL_TIMOD_MASK (0x7U) |
#define | FLEXIO_TIMCTL_TIMOD_SHIFT (0U) |
#define | FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) |
#define | FLEXIO_TIMCTL_ONETIM_MASK (0x20U) |
#define | FLEXIO_TIMCTL_ONETIM_SHIFT (5U) |
#define | FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) |
#define | FLEXIO_TIMCTL_PININS_MASK (0x40U) |
#define | FLEXIO_TIMCTL_PININS_SHIFT (6U) |
#define | FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) |
#define | FLEXIO_TIMCTL_PINPOL_MASK (0x80U) |
#define | FLEXIO_TIMCTL_PINPOL_SHIFT (7U) |
#define | FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) |
#define | FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) |
#define | FLEXIO_TIMCTL_PINSEL_SHIFT (8U) |
#define | FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) |
#define | FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) |
#define | FLEXIO_TIMCTL_PINCFG_SHIFT (16U) |
#define | FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) |
#define | FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) |
#define | FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) |
#define | FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) |
#define | FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) |
#define | FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) |
#define | FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) |
#define | FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) |
#define | FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) |
#define | FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) |
TIMCFG - Timer Configuration N Register | |
#define | FLEXIO_TIMCFG_TSTART_MASK (0x2U) |
#define | FLEXIO_TIMCFG_TSTART_SHIFT (1U) |
#define | FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) |
#define | FLEXIO_TIMCFG_TSTOP_MASK (0x30U) |
#define | FLEXIO_TIMCFG_TSTOP_SHIFT (4U) |
#define | FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) |
#define | FLEXIO_TIMCFG_TIMENA_MASK (0x700U) |
#define | FLEXIO_TIMCFG_TIMENA_SHIFT (8U) |
#define | FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) |
#define | FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) |
#define | FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) |
#define | FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) |
#define | FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) |
#define | FLEXIO_TIMCFG_TIMRST_SHIFT (16U) |
#define | FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) |
#define | FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) |
#define | FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) |
#define | FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) |
#define | FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) |
#define | FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) |
#define | FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) |
TIMCMP - Timer Compare N Register | |
#define | FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) |
#define | FLEXIO_TIMCMP_CMP_SHIFT (0U) |
#define | FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) |
SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register | |
#define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) |
#define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) |
#define | FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) |
SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register | |
#define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) |
#define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) |
#define | FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) |
SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register | |
#define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) |
#define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) |
#define | FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) |
SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register | |
#define | FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) |
#define | FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) |
#define | FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK) |
SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register | |
#define | FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) |
#define | FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) |
#define | FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK) |
TCM_CTRL - TCM CRTL Register | |
#define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) |
#define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) |
#define | FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) |
#define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) |
#define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) |
#define | FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) |
#define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) |
#define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) |
#define | FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) |
#define | FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U) |
#define | FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U) |
#define | FLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK) |
OCRAM_MAGIC_ADDR - OCRAM Magic Address Register | |
#define | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U) |
#define | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U) |
#define | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK) |
#define | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x3FFFEU) |
#define | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U) |
#define | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK) |
#define | FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) |
#define | FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (18U) |
#define | FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK) |
DTCM_MAGIC_ADDR - DTCM Magic Address Register | |
#define | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U) |
#define | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U) |
#define | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK) |
#define | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU) |
#define | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U) |
#define | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK) |
#define | FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) |
#define | FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U) |
#define | FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK) |
ITCM_MAGIC_ADDR - ITCM Magic Address Register | |
#define | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U) |
#define | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U) |
#define | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK) |
#define | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU) |
#define | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U) |
#define | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK) |
#define | FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) |
#define | FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U) |
#define | FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK) |
INT_STATUS - Interrupt Status Register | |
#define | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U) |
#define | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U) |
#define | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) |
#define | FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U) |
#define | FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U) |
#define | FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) |
#define | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U) |
#define | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U) |
#define | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) |
#define | FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) |
#define | FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) |
#define | FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) |
#define | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U) |
#define | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U) |
#define | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) |
#define | FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U) |
#define | FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U) |
#define | FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) |
#define | FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK (0x40U) |
#define | FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT (6U) |
#define | FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK) |
#define | FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK (0x80U) |
#define | FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT (7U) |
#define | FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK) |
#define | FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK (0x100U) |
#define | FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT (8U) |
#define | FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK) |
#define | FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK (0x200U) |
#define | FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT (9U) |
#define | FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK) |
#define | FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK (0x400U) |
#define | FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT (10U) |
#define | FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK) |
#define | FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK (0x800U) |
#define | FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT (11U) |
#define | FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK) |
#define | FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK (0x1000U) |
#define | FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT (12U) |
#define | FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK) |
#define | FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK (0x2000U) |
#define | FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT (13U) |
#define | FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK) |
#define | FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK (0x4000U) |
#define | FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT (14U) |
#define | FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK) |
#define | FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK (0x8000U) |
#define | FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT (15U) |
#define | FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK) |
#define | FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK (0x10000U) |
#define | FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT (16U) |
#define | FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK) |
#define | FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK (0x20000U) |
#define | FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT (17U) |
#define | FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK) |
#define | FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFC0000U) |
#define | FLEXRAM_INT_STATUS_Reserved_SHIFT (18U) |
#define | FLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK) |
#define | SSARC_LP_INT_STATUS_ERR_INDEX_MASK (0x3FFU) |
#define | SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT (0U) |
#define | SSARC_LP_INT_STATUS_ERR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT)) & SSARC_LP_INT_STATUS_ERR_INDEX_MASK) |
#define | SSARC_LP_INT_STATUS_AHB_RESP_MASK (0xC00U) |
#define | SSARC_LP_INT_STATUS_AHB_RESP_SHIFT (10U) |
#define | SSARC_LP_INT_STATUS_AHB_RESP(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_RESP_SHIFT)) & SSARC_LP_INT_STATUS_AHB_RESP_MASK) |
#define | SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK (0x8000000U) |
#define | SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT (27U) |
#define | SSARC_LP_INT_STATUS_GROUP_CONFLICT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT)) & SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK) |
#define | SSARC_LP_INT_STATUS_TIMEOUT_MASK (0x10000000U) |
#define | SSARC_LP_INT_STATUS_TIMEOUT_SHIFT (28U) |
#define | SSARC_LP_INT_STATUS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_TIMEOUT_SHIFT)) & SSARC_LP_INT_STATUS_TIMEOUT_MASK) |
#define | SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK (0x20000000U) |
#define | SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT (29U) |
#define | SSARC_LP_INT_STATUS_SW_REQ_DONE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT)) & SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK) |
#define | SSARC_LP_INT_STATUS_AHB_ERR_MASK (0x40000000U) |
#define | SSARC_LP_INT_STATUS_AHB_ERR_SHIFT (30U) |
#define | SSARC_LP_INT_STATUS_AHB_ERR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_ERR_SHIFT)) & SSARC_LP_INT_STATUS_AHB_ERR_MASK) |
#define | SSARC_LP_INT_STATUS_ADDR_ERR_MASK (0x80000000U) |
#define | SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT (31U) |
#define | SSARC_LP_INT_STATUS_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT)) & SSARC_LP_INT_STATUS_ADDR_ERR_MASK) |
INT_STAT_EN - Interrupt Status Enable Register | |
#define | FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U) |
#define | FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U) |
#define | FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U) |
#define | FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U) |
#define | FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) |
#define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) |
#define | FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) |
#define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) |
#define | FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK (0x40U) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT (6U) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK (0x80U) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT (7U) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK (0x100U) |
#define | FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT (8U) |
#define | FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK (0x200U) |
#define | FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT (9U) |
#define | FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK (0x400U) |
#define | FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT (10U) |
#define | FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK (0x800U) |
#define | FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT (11U) |
#define | FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK (0x1000U) |
#define | FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT (12U) |
#define | FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK (0x2000U) |
#define | FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT (13U) |
#define | FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK (0x4000U) |
#define | FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT (14U) |
#define | FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK (0x8000U) |
#define | FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT (15U) |
#define | FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK (0x10000U) |
#define | FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT (16U) |
#define | FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK (0x20000U) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT (17U) |
#define | FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK) |
#define | FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFC0000U) |
#define | FLEXRAM_INT_STAT_EN_Reserved_SHIFT (18U) |
#define | FLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK) |
INT_SIG_EN - Interrupt Enable Register | |
#define | FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U) |
#define | FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U) |
#define | FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U) |
#define | FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U) |
#define | FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) |
#define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) |
#define | FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) |
#define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) |
#define | FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK (0x40U) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT (6U) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK (0x80U) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT (7U) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK (0x100U) |
#define | FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT (8U) |
#define | FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK (0x200U) |
#define | FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT (9U) |
#define | FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK (0x400U) |
#define | FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT (10U) |
#define | FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK (0x800U) |
#define | FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT (11U) |
#define | FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK (0x1000U) |
#define | FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT (12U) |
#define | FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK (0x2000U) |
#define | FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT (13U) |
#define | FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK (0x4000U) |
#define | FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT (14U) |
#define | FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x8000U) |
#define | FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (15U) |
#define | FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x10000U) |
#define | FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (16U) |
#define | FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK (0x20000U) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT (17U) |
#define | FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK) |
#define | FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFC0000U) |
#define | FLEXRAM_INT_SIG_EN_Reserved_SHIFT (18U) |
#define | FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK) |
OCRAM_ECC_SINGLE_ERROR_INFO - OCRAM single-bit ECC Error Information Register | |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK (0xFFU) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT (0U) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK (0xFF00U) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT (8U) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFFF0000U) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (16U) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK) |
OCRAM_ECC_SINGLE_ERROR_ADDR - OCRAM single-bit ECC Error Address Register | |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT (0U) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK) |
OCRAM_ECC_SINGLE_ERROR_DATA_LSB - OCRAM single-bit ECC Error Data Register | |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT (0U) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK) |
OCRAM_ECC_SINGLE_ERROR_DATA_MSB - OCRAM single-bit ECC Error Data Register | |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT (0U) |
#define | FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK) |
OCRAM_ECC_MULTI_ERROR_INFO - OCRAM multi-bit ECC Error Information Register | |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK (0xFFU) |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT (0U) |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK) |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFFFFF00U) |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (8U) |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK) |
OCRAM_ECC_MULTI_ERROR_ADDR - OCRAM multi-bit ECC Error Address Register | |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT (0U) |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK) |
OCRAM_ECC_MULTI_ERROR_DATA_LSB - OCRAM multi-bit ECC Error Data Register | |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT (0U) |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK) |
OCRAM_ECC_MULTI_ERROR_DATA_MSB - OCRAM multi-bit ECC Error Data Register | |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT (0U) |
#define | FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK) |
ITCM_ECC_SINGLE_ERROR_INFO - ITCM single-bit ECC Error Information Register | |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK (0x1U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT (0U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK (0xEU) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT (1U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK (0xF0U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT (4U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK (0xF00U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT (8U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK (0xFF000U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT (12U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF00000U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (20U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK) |
ITCM_ECC_SINGLE_ERROR_ADDR - ITCM single-bit ECC Error Address Register | |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT (0U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK) |
ITCM_ECC_SINGLE_ERROR_DATA_LSB - ITCM single-bit ECC Error Data Register | |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT (0U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK) |
ITCM_ECC_SINGLE_ERROR_DATA_MSB - ITCM single-bit ECC Error Data Register | |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT (0U) |
#define | FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK) |
ITCM_ECC_MULTI_ERROR_INFO - ITCM multi-bit ECC Error Information Register | |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK (0x1U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT (0U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK (0xEU) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT (1U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK (0xF0U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT (4U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK (0xF00U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT (8U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK (0xFF000U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT (12U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF00000U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (20U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK) |
ITCM_ECC_MULTI_ERROR_ADDR - ITCM multi-bit ECC Error Address Register | |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT (0U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK) |
ITCM_ECC_MULTI_ERROR_DATA_LSB - ITCM multi-bit ECC Error Data Register | |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT (0U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK) |
ITCM_ECC_MULTI_ERROR_DATA_MSB - ITCM multi-bit ECC Error Data Register | |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT (0U) |
#define | FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK) |
D0TCM_ECC_SINGLE_ERROR_INFO - D0TCM single-bit ECC Error Information Register | |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK (0x1U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT (0U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK (0xEU) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT (1U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK (0xF0U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT (4U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK (0xF00U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT (8U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK (0x7F000U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT (12U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK) |
D0TCM_ECC_SINGLE_ERROR_ADDR - D0TCM single-bit ECC Error Address Register | |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT (0U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK) |
D0TCM_ECC_SINGLE_ERROR_DATA - D0TCM single-bit ECC Error Data Register | |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT (0U) |
#define | FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK) |
D0TCM_ECC_MULTI_ERROR_INFO - D0TCM multi-bit ECC Error Information Register | |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK (0x1U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT (0U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK (0xEU) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT (1U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK (0xF0U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT (4U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK (0xF00U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT (8U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK (0x7F000U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT (12U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK) |
D0TCM_ECC_MULTI_ERROR_ADDR - D0TCM multi-bit ECC Error Address Register | |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT (0U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK) |
D0TCM_ECC_MULTI_ERROR_DATA - D0TCM multi-bit ECC Error Data Register | |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT (0U) |
#define | FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK) |
D1TCM_ECC_SINGLE_ERROR_INFO - D1TCM single-bit ECC Error Information Register | |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK (0x1U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT (0U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK (0xEU) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT (1U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK (0xF0U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT (4U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK (0xF00U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT (8U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK (0x7F000U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT (12U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK) |
D1TCM_ECC_SINGLE_ERROR_ADDR - D1TCM single-bit ECC Error Address Register | |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT (0U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK) |
D1TCM_ECC_SINGLE_ERROR_DATA - D1TCM single-bit ECC Error Data Register | |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT (0U) |
#define | FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK) |
D1TCM_ECC_MULTI_ERROR_INFO - D1TCM multi-bit ECC Error Information Register | |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK (0x1U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT (0U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK (0xEU) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT (1U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK (0xF0U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT (4U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK (0xF00U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT (8U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK (0x7F000U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT (12U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK) |
D1TCM_ECC_MULTI_ERROR_ADDR - D1TCM multi-bit ECC Error Address Register | |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT (0U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK) |
D1TCM_ECC_MULTI_ERROR_DATA - D1TCM multi-bit ECC Error Data Register | |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT (0U) |
#define | FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK) |
FLEXRAM_CTRL - FlexRAM feature Control register | |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK (0x1U) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT (0U) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK (0x2U) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT (1U) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK (0x4U) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT (2U) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK (0x8U) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT (3U) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK (0x10U) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT (4U) |
#define | FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK) |
#define | FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK (0x20U) |
#define | FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT (5U) |
#define | FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK) |
#define | FLEXRAM_FLEXRAM_CTRL_Reserved_MASK (0xFFFFFFC0U) |
#define | FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT (6U) |
#define | FLEXRAM_FLEXRAM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_Reserved_MASK) |
OCRAM_PIPELINE_STATUS - OCRAM Pipeline Status register | |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK (0x1U) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT (0U) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x2U) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (1U) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK (0x4U) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT (2U) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x8U) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (3U) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK (0xFFFFFFF0U) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT (4U) |
#define | FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK) |
MCR0 - Module Control Register 0 | |
#define | FLEXSPI_MCR0_SWRESET_MASK (0x1U) |
#define | FLEXSPI_MCR0_SWRESET_SHIFT (0U) |
#define | FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) |
#define | FLEXSPI_MCR0_MDIS_MASK (0x2U) |
#define | FLEXSPI_MCR0_MDIS_SHIFT (1U) |
#define | FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) |
#define | FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) |
#define | FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) |
#define | FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) |
#define | FLEXSPI_MCR0_ARDFEN_MASK (0x40U) |
#define | FLEXSPI_MCR0_ARDFEN_SHIFT (6U) |
#define | FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) |
#define | FLEXSPI_MCR0_ATDFEN_MASK (0x80U) |
#define | FLEXSPI_MCR0_ATDFEN_SHIFT (7U) |
#define | FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) |
#define | FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) |
#define | FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) |
#define | FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) |
#define | FLEXSPI_MCR0_HSEN_MASK (0x800U) |
#define | FLEXSPI_MCR0_HSEN_SHIFT (11U) |
#define | FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) |
#define | FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) |
#define | FLEXSPI_MCR0_DOZEEN_SHIFT (12U) |
#define | FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) |
#define | FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) |
#define | FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) |
#define | FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) |
#define | FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) |
#define | FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) |
#define | FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) |
#define | FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) |
#define | FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) |
#define | FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) |
MCR1 - Module Control Register 1 | |
#define | FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) |
#define | FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) |
#define | FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) |
#define | FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) |
#define | FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) |
#define | FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) |
MCR2 - Module Control Register 2 | |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) |
#define | FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) |
#define | FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) |
#define | FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) |
AHBCR - AHB Bus Control Register | |
#define | FLEXSPI_AHBCR_APAREN_MASK (0x1U) |
#define | FLEXSPI_AHBCR_APAREN_SHIFT (0U) |
#define | FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) |
#define | FLEXSPI_AHBCR_CLRAHBRXBUF_MASK (0x2U) |
#define | FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT (1U) |
#define | FLEXSPI_AHBCR_CLRAHBRXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) |
#define | FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) |
#define | FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) |
#define | FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) |
#define | FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) |
#define | FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) |
#define | FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) |
#define | FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) |
#define | FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) |
#define | FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) |
#define | FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U) |
#define | FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U) |
#define | FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) |
#define | FLEXSPI_AHBCR_ECCEN_MASK (0x800U) |
#define | FLEXSPI_AHBCR_ECCEN_SHIFT (11U) |
#define | FLEXSPI_AHBCR_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCEN_SHIFT)) & FLEXSPI_AHBCR_ECCEN_MASK) |
#define | FLEXSPI_AHBCR_SPLITEN_MASK (0x1000U) |
#define | FLEXSPI_AHBCR_SPLITEN_SHIFT (12U) |
#define | FLEXSPI_AHBCR_SPLITEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLITEN_SHIFT)) & FLEXSPI_AHBCR_SPLITEN_MASK) |
#define | FLEXSPI_AHBCR_SPLIT_LIMIT_MASK (0x6000U) |
#define | FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT (13U) |
#define | FLEXSPI_AHBCR_SPLIT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT)) & FLEXSPI_AHBCR_SPLIT_LIMIT_MASK) |
#define | FLEXSPI_AHBCR_KEYECCEN_MASK (0x8000U) |
#define | FLEXSPI_AHBCR_KEYECCEN_SHIFT (15U) |
#define | FLEXSPI_AHBCR_KEYECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_KEYECCEN_SHIFT)) & FLEXSPI_AHBCR_KEYECCEN_MASK) |
#define | FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK (0x10000U) |
#define | FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT (16U) |
#define | FLEXSPI_AHBCR_ECCSINGLEERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK) |
#define | FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK (0x20000U) |
#define | FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT (17U) |
#define | FLEXSPI_AHBCR_ECCMULTIERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK) |
#define | FLEXSPI_AHBCR_HMSTRIDREMAP_MASK (0x40000U) |
#define | FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT (18U) |
#define | FLEXSPI_AHBCR_HMSTRIDREMAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT)) & FLEXSPI_AHBCR_HMSTRIDREMAP_MASK) |
#define | FLEXSPI_AHBCR_ECCSWAPEN_MASK (0x80000U) |
#define | FLEXSPI_AHBCR_ECCSWAPEN_SHIFT (19U) |
#define | FLEXSPI_AHBCR_ECCSWAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSWAPEN_SHIFT)) & FLEXSPI_AHBCR_ECCSWAPEN_MASK) |
#define | FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U) |
#define | FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U) |
#define | FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) |
INTEN - Interrupt Enable Register | |
#define | FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) |
#define | FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) |
#define | FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) |
#define | FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) |
#define | FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) |
#define | FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) |
#define | FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) |
#define | FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) |
#define | FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) |
#define | FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) |
#define | FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) |
#define | FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) |
#define | FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) |
#define | FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) |
#define | FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) |
#define | FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) |
#define | FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) |
#define | FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) |
#define | FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) |
#define | FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) |
#define | FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) |
#define | FLEXSPI_INTEN_AHBBUSERROREN_MASK (0x400U) |
#define | FLEXSPI_INTEN_AHBBUSERROREN_SHIFT (10U) |
#define | FLEXSPI_INTEN_AHBBUSERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) |
#define | FLEXSPI_INTEN_KEYDONEEN_MASK (0x1000U) |
#define | FLEXSPI_INTEN_KEYDONEEN_SHIFT (12U) |
#define | FLEXSPI_INTEN_KEYDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK) |
#define | FLEXSPI_INTEN_KEYERROREN_MASK (0x2000U) |
#define | FLEXSPI_INTEN_KEYERROREN_SHIFT (13U) |
#define | FLEXSPI_INTEN_KEYERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK) |
#define | FLEXSPI_INTEN_ECCMULTIERREN_MASK (0x4000U) |
#define | FLEXSPI_INTEN_ECCMULTIERREN_SHIFT (14U) |
#define | FLEXSPI_INTEN_ECCMULTIERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCMULTIERREN_SHIFT)) & FLEXSPI_INTEN_ECCMULTIERREN_MASK) |
#define | FLEXSPI_INTEN_ECCSINGLEERREN_MASK (0x8000U) |
#define | FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT (15U) |
#define | FLEXSPI_INTEN_ECCSINGLEERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT)) & FLEXSPI_INTEN_ECCSINGLEERREN_MASK) |
#define | FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK (0x10000U) |
#define | FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT (16U) |
#define | FLEXSPI_INTEN_IPCMDSECUREVIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK) |
#define | PWM_INTEN_CMPIE_MASK (0x3FU) |
#define | PWM_INTEN_CMPIE_SHIFT (0U) |
#define | PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) |
#define | PWM_INTEN_CX0IE_MASK (0x40U) |
#define | PWM_INTEN_CX0IE_SHIFT (6U) |
#define | PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) |
#define | PWM_INTEN_CX1IE_MASK (0x80U) |
#define | PWM_INTEN_CX1IE_SHIFT (7U) |
#define | PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) |
#define | PWM_INTEN_CB0IE_MASK (0x100U) |
#define | PWM_INTEN_CB0IE_SHIFT (8U) |
#define | PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) |
#define | PWM_INTEN_CB1IE_MASK (0x200U) |
#define | PWM_INTEN_CB1IE_SHIFT (9U) |
#define | PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) |
#define | PWM_INTEN_CA0IE_MASK (0x400U) |
#define | PWM_INTEN_CA0IE_SHIFT (10U) |
#define | PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) |
#define | PWM_INTEN_CA1IE_MASK (0x800U) |
#define | PWM_INTEN_CA1IE_SHIFT (11U) |
#define | PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) |
#define | PWM_INTEN_RIE_MASK (0x1000U) |
#define | PWM_INTEN_RIE_SHIFT (12U) |
#define | PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) |
#define | PWM_INTEN_REIE_MASK (0x2000U) |
#define | PWM_INTEN_REIE_SHIFT (13U) |
#define | PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) |
#define | SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) |
#define | SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) |
#define | SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
#define | SEMC_INTEN_IPCMDERREN_MASK (0x2U) |
#define | SEMC_INTEN_IPCMDERREN_SHIFT (1U) |
#define | SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
#define | SEMC_INTEN_AXICMDERREN_MASK (0x4U) |
#define | SEMC_INTEN_AXICMDERREN_SHIFT (2U) |
#define | SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
#define | SEMC_INTEN_AXIBUSERREN_MASK (0x8U) |
#define | SEMC_INTEN_AXIBUSERREN_SHIFT (3U) |
#define | SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
#define | SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) |
#define | SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) |
#define | SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
#define | SEMC_INTEN_NDNOPENDEN_MASK (0x20U) |
#define | SEMC_INTEN_NDNOPENDEN_SHIFT (5U) |
#define | SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
INTR - Interrupt Register | |
#define | FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) |
#define | FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) |
#define | FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) |
#define | FLEXSPI_INTR_IPCMDGE_MASK (0x2U) |
#define | FLEXSPI_INTR_IPCMDGE_SHIFT (1U) |
#define | FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) |
#define | FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) |
#define | FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) |
#define | FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) |
#define | FLEXSPI_INTR_IPCMDERR_MASK (0x8U) |
#define | FLEXSPI_INTR_IPCMDERR_SHIFT (3U) |
#define | FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) |
#define | FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) |
#define | FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) |
#define | FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) |
#define | FLEXSPI_INTR_IPRXWA_MASK (0x20U) |
#define | FLEXSPI_INTR_IPRXWA_SHIFT (5U) |
#define | FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) |
#define | FLEXSPI_INTR_IPTXWE_MASK (0x40U) |
#define | FLEXSPI_INTR_IPTXWE_SHIFT (6U) |
#define | FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) |
#define | FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) |
#define | FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) |
#define | FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) |
#define | FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) |
#define | FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) |
#define | FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) |
#define | FLEXSPI_INTR_AHBBUSERROR_MASK (0x400U) |
#define | FLEXSPI_INTR_AHBBUSERROR_SHIFT (10U) |
#define | FLEXSPI_INTR_AHBBUSERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK) |
#define | FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) |
#define | FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) |
#define | FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) |
#define | FLEXSPI_INTR_KEYDONE_MASK (0x1000U) |
#define | FLEXSPI_INTR_KEYDONE_SHIFT (12U) |
#define | FLEXSPI_INTR_KEYDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK) |
#define | FLEXSPI_INTR_KEYERROR_MASK (0x2000U) |
#define | FLEXSPI_INTR_KEYERROR_SHIFT (13U) |
#define | FLEXSPI_INTR_KEYERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK) |
#define | FLEXSPI_INTR_ECCMULTIERR_MASK (0x4000U) |
#define | FLEXSPI_INTR_ECCMULTIERR_SHIFT (14U) |
#define | FLEXSPI_INTR_ECCMULTIERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCMULTIERR_SHIFT)) & FLEXSPI_INTR_ECCMULTIERR_MASK) |
#define | FLEXSPI_INTR_ECCSINGLEERR_MASK (0x8000U) |
#define | FLEXSPI_INTR_ECCSINGLEERR_SHIFT (15U) |
#define | FLEXSPI_INTR_ECCSINGLEERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCSINGLEERR_SHIFT)) & FLEXSPI_INTR_ECCSINGLEERR_MASK) |
#define | FLEXSPI_INTR_IPCMDSECUREVIO_MASK (0x10000U) |
#define | FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT (16U) |
#define | FLEXSPI_INTR_IPCMDSECUREVIO(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK) |
#define | SEMC_INTR_IPCMDDONE_MASK (0x1U) |
#define | SEMC_INTR_IPCMDDONE_SHIFT (0U) |
#define | SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) |
#define | SEMC_INTR_IPCMDERR_MASK (0x2U) |
#define | SEMC_INTR_IPCMDERR_SHIFT (1U) |
#define | SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) |
#define | SEMC_INTR_AXICMDERR_MASK (0x4U) |
#define | SEMC_INTR_AXICMDERR_SHIFT (2U) |
#define | SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) |
#define | SEMC_INTR_AXIBUSERR_MASK (0x8U) |
#define | SEMC_INTR_AXIBUSERR_SHIFT (3U) |
#define | SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) |
#define | SEMC_INTR_NDPAGEEND_MASK (0x10U) |
#define | SEMC_INTR_NDPAGEEND_SHIFT (4U) |
#define | SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) |
#define | SEMC_INTR_NDNOPEND_MASK (0x20U) |
#define | SEMC_INTR_NDNOPEND_SHIFT (5U) |
#define | SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) |
LUTKEY - LUT Key Register | |
#define | FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_LUTKEY_KEY_SHIFT (0U) |
#define | FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) |
LUTCR - LUT Control Register | |
#define | FLEXSPI_LUTCR_LOCK_MASK (0x1U) |
#define | FLEXSPI_LUTCR_LOCK_SHIFT (0U) |
#define | FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) |
#define | FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) |
#define | FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) |
#define | FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) |
#define | FLEXSPI_LUTCR_PROTECT_MASK (0x4U) |
#define | FLEXSPI_LUTCR_PROTECT_SHIFT (2U) |
#define | FLEXSPI_LUTCR_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK) |
AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 | |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x3FFU) |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK (0x40000000U) |
#define | FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT (30U) |
#define | FLEXSPI_AHBRXBUFCR0_REGIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) |
FLSHCR0 - Flash Control Register 0 | |
#define | FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) |
#define | FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) |
#define | FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) |
#define | FLEXSPI_FLSHCR0_SPLITWREN_MASK (0x40000000U) |
#define | FLEXSPI_FLSHCR0_SPLITWREN_SHIFT (30U) |
#define | FLEXSPI_FLSHCR0_SPLITWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK) |
#define | FLEXSPI_FLSHCR0_SPLITRDEN_MASK (0x80000000U) |
#define | FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT (31U) |
#define | FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) |
FLSHCR1 - Flash Control Register 1 | |
#define | FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) |
#define | FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) |
#define | FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) |
#define | FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) |
#define | FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) |
#define | FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) |
#define | FLEXSPI_FLSHCR1_WA_MASK (0x400U) |
#define | FLEXSPI_FLSHCR1_WA_SHIFT (10U) |
#define | FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) |
#define | FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) |
#define | FLEXSPI_FLSHCR1_CAS_SHIFT (11U) |
#define | FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) |
FLSHCR2 - Flash Control Register 2 | |
#define | FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) |
#define | FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) |
#define | FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) |
#define | FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) |
#define | FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) |
#define | FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) |
#define | FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) |
#define | FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) |
#define | FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) |
FLSHCR4 - Flash Control Register 4 | |
#define | FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) |
#define | FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) |
#define | FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) |
#define | FLEXSPI_FLSHCR4_WMOPT2_MASK (0x2U) |
#define | FLEXSPI_FLSHCR4_WMOPT2_SHIFT (1U) |
#define | FLEXSPI_FLSHCR4_WMOPT2(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK) |
#define | FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) |
#define | FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) |
#define | FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) |
#define | FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) |
#define | FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) |
#define | FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) |
#define | FLEXSPI_FLSHCR4_PAR_WM_MASK (0x600U) |
#define | FLEXSPI_FLSHCR4_PAR_WM_SHIFT (9U) |
#define | FLEXSPI_FLSHCR4_PAR_WM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_WM_SHIFT)) & FLEXSPI_FLSHCR4_PAR_WM_MASK) |
#define | FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK (0x800U) |
#define | FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT (11U) |
#define | FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT)) & FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK) |
IPCR0 - IP Control Register 0 | |
#define | FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_IPCR0_SFAR_SHIFT (0U) |
#define | FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) |
IPCR1 - IP Control Register 1 | |
#define | FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) |
#define | FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) |
#define | FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) |
#define | FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) |
#define | FLEXSPI_IPCR1_ISEQID_SHIFT (16U) |
#define | FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) |
#define | FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) |
#define | FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) |
#define | FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) |
#define | FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) |
#define | FLEXSPI_IPCR1_IPAREN_SHIFT (31U) |
#define | FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) |
IPCMD - IP Command Register | |
#define | FLEXSPI_IPCMD_TRG_MASK (0x1U) |
#define | FLEXSPI_IPCMD_TRG_SHIFT (0U) |
#define | FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) |
#define | SEMC_IPCMD_CMD_MASK (0xFFFFU) |
#define | SEMC_IPCMD_CMD_SHIFT (0U) |
#define | SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) |
#define | SEMC_IPCMD_KEY_MASK (0xFFFF0000U) |
#define | SEMC_IPCMD_KEY_SHIFT (16U) |
#define | SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) |
IPRXFCR - IP RX FIFO Control Register | |
#define | FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) |
#define | FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) |
#define | FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) |
#define | FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) |
#define | FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) |
#define | FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) |
#define | FLEXSPI_IPRXFCR_RXWMRK_MASK (0x7CU) |
#define | FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) |
#define | FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) |
IPTXFCR - IP TX FIFO Control Register | |
#define | FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) |
#define | FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) |
#define | FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) |
#define | FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) |
#define | FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) |
#define | FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) |
#define | FLEXSPI_IPTXFCR_TXWMRK_MASK (0x7CU) |
#define | FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) |
#define | FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) |
DLLCR - DLL Control Register 0 | |
#define | FLEXSPI_DLLCR_DLLEN_MASK (0x1U) |
#define | FLEXSPI_DLLCR_DLLEN_SHIFT (0U) |
#define | FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) |
#define | FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) |
#define | FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) |
#define | FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) |
#define | FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) |
#define | FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) |
#define | FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) |
#define | FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) |
#define | FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) |
#define | FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) |
MISCCR4 - Misc Control Register 4 | |
#define | FLEXSPI_MISCCR4_AHBADDRESS_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_MISCCR4_AHBADDRESS_SHIFT (0U) |
#define | FLEXSPI_MISCCR4_AHBADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR4_AHBADDRESS_SHIFT)) & FLEXSPI_MISCCR4_AHBADDRESS_MASK) |
MISCCR5 - Misc Control Register 5 | |
#define | FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT (0U) |
#define | FLEXSPI_MISCCR5_ECCSINGLEERRORCORR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT)) & FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK) |
MISCCR6 - Misc Control Register 6 | |
#define | FLEXSPI_MISCCR6_VALID_MASK (0x1U) |
#define | FLEXSPI_MISCCR6_VALID_SHIFT (0U) |
#define | FLEXSPI_MISCCR6_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_VALID_SHIFT)) & FLEXSPI_MISCCR6_VALID_MASK) |
#define | FLEXSPI_MISCCR6_HIT_MASK (0x2U) |
#define | FLEXSPI_MISCCR6_HIT_SHIFT (1U) |
#define | FLEXSPI_MISCCR6_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_HIT_SHIFT)) & FLEXSPI_MISCCR6_HIT_MASK) |
#define | FLEXSPI_MISCCR6_ADDRESS_MASK (0xFFFFFFFCU) |
#define | FLEXSPI_MISCCR6_ADDRESS_SHIFT (2U) |
#define | FLEXSPI_MISCCR6_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_ADDRESS_SHIFT)) & FLEXSPI_MISCCR6_ADDRESS_MASK) |
MISCCR7 - Misc Control Register 7 | |
#define | FLEXSPI_MISCCR7_VALID_MASK (0x1U) |
#define | FLEXSPI_MISCCR7_VALID_SHIFT (0U) |
#define | FLEXSPI_MISCCR7_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_VALID_SHIFT)) & FLEXSPI_MISCCR7_VALID_MASK) |
#define | FLEXSPI_MISCCR7_HIT_MASK (0x2U) |
#define | FLEXSPI_MISCCR7_HIT_SHIFT (1U) |
#define | FLEXSPI_MISCCR7_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_HIT_SHIFT)) & FLEXSPI_MISCCR7_HIT_MASK) |
#define | FLEXSPI_MISCCR7_ADDRESS_MASK (0xFFFFFFFCU) |
#define | FLEXSPI_MISCCR7_ADDRESS_SHIFT (2U) |
#define | FLEXSPI_MISCCR7_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_ADDRESS_SHIFT)) & FLEXSPI_MISCCR7_ADDRESS_MASK) |
STS0 - Status Register 0 | |
#define | FLEXSPI_STS0_SEQIDLE_MASK (0x1U) |
#define | FLEXSPI_STS0_SEQIDLE_SHIFT (0U) |
#define | FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) |
#define | FLEXSPI_STS0_ARBIDLE_MASK (0x2U) |
#define | FLEXSPI_STS0_ARBIDLE_SHIFT (1U) |
#define | FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) |
#define | FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) |
#define | FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) |
#define | FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) |
#define | SEMC_STS0_IDLE_MASK (0x1U) |
#define | SEMC_STS0_IDLE_SHIFT (0U) |
#define | SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
#define | SEMC_STS0_NARDY_MASK (0x2U) |
#define | SEMC_STS0_NARDY_SHIFT (1U) |
#define | SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
STS1 - Status Register 1 | |
#define | FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) |
#define | FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) |
#define | FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) |
#define | FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) |
#define | FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) |
#define | FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) |
#define | FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) |
#define | FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) |
#define | FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) |
#define | FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) |
#define | FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) |
#define | FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) |
STS2 - Status Register 2 | |
#define | FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) |
#define | FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) |
#define | FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) |
#define | FLEXSPI_STS2_AREFLOCK_MASK (0x2U) |
#define | FLEXSPI_STS2_AREFLOCK_SHIFT (1U) |
#define | FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) |
#define | FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) |
#define | FLEXSPI_STS2_ASLVSEL_SHIFT (2U) |
#define | FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) |
#define | FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) |
#define | FLEXSPI_STS2_AREFSEL_SHIFT (8U) |
#define | FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) |
#define | FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) |
#define | FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) |
#define | FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) |
#define | FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) |
#define | FLEXSPI_STS2_BREFLOCK_SHIFT (17U) |
#define | FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) |
#define | FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) |
#define | FLEXSPI_STS2_BSLVSEL_SHIFT (18U) |
#define | FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) |
#define | FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) |
#define | FLEXSPI_STS2_BREFSEL_SHIFT (24U) |
#define | FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) |
#define | SEMC_STS2_NDWRPEND_MASK (0x8U) |
#define | SEMC_STS2_NDWRPEND_SHIFT (3U) |
#define | SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
AHBSPNDSTS - AHB Suspend Status Register | |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) |
#define | FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) |
#define | FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) |
#define | FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) |
IPRXFSTS - IP RX FIFO Status Register | |
#define | FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) |
#define | FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) |
#define | FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) |
#define | FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) |
#define | FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) |
#define | FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) |
IPTXFSTS - IP TX FIFO Status Register | |
#define | FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) |
#define | FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) |
#define | FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) |
#define | FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) |
#define | FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) |
#define | FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) |
RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 | |
#define | FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_RFDR_RXDATA_SHIFT (0U) |
#define | FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) |
TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 | |
#define | FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_TFDR_TXDATA_SHIFT (0U) |
#define | FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) |
LUT - LUT 0..LUT 63 | |
#define | FLEXSPI_LUT_OPERAND0_MASK (0xFFU) |
#define | FLEXSPI_LUT_OPERAND0_SHIFT (0U) |
#define | FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) |
#define | FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) |
#define | FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) |
#define | FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) |
#define | FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) |
#define | FLEXSPI_LUT_OPCODE0_SHIFT (10U) |
#define | FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) |
#define | FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) |
#define | FLEXSPI_LUT_OPERAND1_SHIFT (16U) |
#define | FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) |
#define | FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) |
#define | FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) |
#define | FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) |
#define | FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) |
#define | FLEXSPI_LUT_OPCODE1_SHIFT (26U) |
#define | FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) |
HMSTRCR - AHB Master ID 0 Control Register..AHB Master ID 7 Control Register | |
#define | FLEXSPI_HMSTRCR_MASK_MASK (0xFFFFU) |
#define | FLEXSPI_HMSTRCR_MASK_SHIFT (0U) |
#define | FLEXSPI_HMSTRCR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MASK_SHIFT)) & FLEXSPI_HMSTRCR_MASK_MASK) |
#define | FLEXSPI_HMSTRCR_MSTRID_MASK (0xFFFF0000U) |
#define | FLEXSPI_HMSTRCR_MSTRID_SHIFT (16U) |
#define | FLEXSPI_HMSTRCR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MSTRID_SHIFT)) & FLEXSPI_HMSTRCR_MSTRID_MASK) |
HADDRSTART - HADDR REMAP START ADDR | |
#define | FLEXSPI_HADDRSTART_REMAPEN_MASK (0x1U) |
#define | FLEXSPI_HADDRSTART_REMAPEN_SHIFT (0U) |
#define | FLEXSPI_HADDRSTART_REMAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK) |
#define | FLEXSPI_HADDRSTART_KBINECC_MASK (0x2U) |
#define | FLEXSPI_HADDRSTART_KBINECC_SHIFT (1U) |
#define | FLEXSPI_HADDRSTART_KBINECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_KBINECC_SHIFT)) & FLEXSPI_HADDRSTART_KBINECC_MASK) |
#define | FLEXSPI_HADDRSTART_ADDRSTART_MASK (0xFFFFF000U) |
#define | FLEXSPI_HADDRSTART_ADDRSTART_SHIFT (12U) |
#define | FLEXSPI_HADDRSTART_ADDRSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK) |
HADDREND - HADDR REMAP END ADDR | |
#define | FLEXSPI_HADDREND_ENDSTART_MASK (0xFFFFF000U) |
#define | FLEXSPI_HADDREND_ENDSTART_SHIFT (12U) |
#define | FLEXSPI_HADDREND_ENDSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK) |
HADDROFFSET - HADDR REMAP OFFSET | |
#define | FLEXSPI_HADDROFFSET_ADDROFFSET_MASK (0xFFFFF000U) |
#define | FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT (12U) |
#define | FLEXSPI_HADDROFFSET_ADDROFFSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK) |
IPSNSZSTART0 - IPS nonsecure region Start address of region 0 | |
#define | FLEXSPI_IPSNSZSTART0_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZSTART0_start_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK) |
IPSNSZEND0 - IPS nonsecure region End address of region 0 | |
#define | FLEXSPI_IPSNSZEND0_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZEND0_end_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK) |
IPSNSZSTART1 - IPS nonsecure region Start address of region 1 | |
#define | FLEXSPI_IPSNSZSTART1_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZSTART1_start_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK) |
IPSNSZEND1 - IPS nonsecure region End address of region 1 | |
#define | FLEXSPI_IPSNSZEND1_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZEND1_end_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK) |
AHBBUFREGIONSTART0 - RX BUF Start address of region 0 | |
#define | FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK) |
AHBBUFREGIONEND0 - RX BUF region End address of region 0 | |
#define | FLEXSPI_AHBBUFREGIONEND0_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_end_address_MASK) |
AHBBUFREGIONSTART1 - RX BUF Start address of region 1 | |
#define | FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK) |
AHBBUFREGIONEND1 - RX BUF region End address of region 1 | |
#define | FLEXSPI_AHBBUFREGIONEND1_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_end_address_MASK) |
AHBBUFREGIONSTART2 - RX BUF Start address of region 2 | |
#define | FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART2_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK) |
AHBBUFREGIONEND2 - RX BUF region End address of region 2 | |
#define | FLEXSPI_AHBBUFREGIONEND2_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND2_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_end_address_MASK) |
AHBBUFREGIONSTART3 - RX BUF Start address of region 3 | |
#define | FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART3_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK) |
AHBBUFREGIONEND3 - RX BUF region End address of region 3 | |
#define | FLEXSPI_AHBBUFREGIONEND3_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND3_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_end_address_MASK) |
CM_AUTHEN_CTRL - CM Authentication Control | |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK (0x1U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK (0x2U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT (1U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) |
#define | GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK) |
CM_INT_CTRL - CM Interrupt Control | |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK (0x1U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK (0x2U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT (1U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK (0x4U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT (2U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK (0x10000U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT (16U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK (0x20000U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT (17U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK (0x40000U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT (18U) |
#define | GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK) |
CM_MISC - Miscellaneous | |
#define | GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK (0x1U) |
#define | GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK (0x2U) |
#define | GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT (1U) |
#define | GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK (0x4U) |
#define | GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT (2U) |
#define | GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK (0x10U) |
#define | GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT (4U) |
#define | GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK) |
CM_MODE_CTRL - CPU mode control | |
#define | GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK (0x3U) |
#define | GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK (0x10U) |
#define | GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT (4U) |
#define | GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK) |
CM_MODE_STAT - CM CPU mode Status | |
#define | GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK (0x3U) |
#define | GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK (0xCU) |
#define | GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT (2U) |
#define | GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK) |
CM_IRQ_WAKEUP_MASK - CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask | |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK) |
CM_NON_IRQ_WAKEUP_MASK - CM non-irq wakeup mask | |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK (0x1U) |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK (0x2U) |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT (1U) |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK) |
CM_IRQ_WAKEUP_STAT - CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status | |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK (0xFFFFFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK) |
CM_NON_IRQ_WAKEUP_STAT - CM non-irq wakeup status | |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK (0x1U) |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK (0x2U) |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT (1U) |
#define | GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK) |
CM_SLEEP_SSAR_CTRL - CM sleep SSAR control | |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK) |
CM_SLEEP_LPCG_CTRL - CM sleep LPCG control | |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK) |
CM_SLEEP_PLL_CTRL - CM sleep PLL control | |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK) |
CM_SLEEP_ISO_CTRL - CM sleep isolation control | |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK) |
CM_SLEEP_RESET_CTRL - CM sleep reset control | |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK) |
CM_SLEEP_POWER_CTRL - CM sleep power control | |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK) |
CM_WAKEUP_POWER_CTRL - CM wakeup power control | |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK) |
CM_WAKEUP_RESET_CTRL - CM wakeup reset control | |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK) |
CM_WAKEUP_ISO_CTRL - CM wakeup isolation control | |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK) |
CM_WAKEUP_PLL_CTRL - CM wakeup PLL control | |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK) |
CM_WAKEUP_LPCG_CTRL - CM wakeup LPCG control | |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK) |
CM_WAKEUP_SSAR_CTRL - CM wakeup SSAR control | |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK) |
CM_SP_CTRL - CM Setpoint Control | |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK (0x1U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK (0x1EU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT (1U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK (0x20U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT (5U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK (0x3C0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT (6U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK (0x400U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT (10U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK (0x7800U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT (11U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK (0x8000U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT (15U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK) |
CM_SP_STAT - CM Setpoint Status | |
#define | GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK (0xFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK (0xF0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT (4U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK (0xF00U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT (8U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK) |
CM_RUN_MODE_MAPPING - CM Run Mode Setpoint Allowed | |
#define | GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK) |
CM_WAIT_MODE_MAPPING - CM Wait Mode Setpoint Allowed | |
#define | GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK) |
CM_STOP_MODE_MAPPING - CM Stop Mode Setpoint Allowed | |
#define | GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK) |
CM_SUSPEND_MODE_MAPPING - CM Suspend Mode Setpoint Allowed | |
#define | GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK) |
CM_SP_MAPPING - CM Setpoint 0 Mapping..CM Setpoint 15 Mapping | |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK (0xFFFFU) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK) |
CM_STBY_CTRL - CM standby control | |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK (0x1U) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT (0U) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK (0x2U) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT (1U) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK (0x4U) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT (2U) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK (0x10000U) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT (16U) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK (0x20000U) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT (17U) |
#define | GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK) |
SP_AUTHEN_CTRL - SP Authentication Control | |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK (0x1U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK (0x2U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT (1U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) |
#define | GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK) |
SP_INT_CTRL - SP Interrupt Control | |
#define | GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK (0x1U) |
#define | GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK) |
#define | GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK (0x2U) |
#define | GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT (1U) |
#define | GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK) |
SP_CPU_REQ - CPU SP Request | |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK (0xFU) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK (0xF0U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT (4U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK (0xF00U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT (8U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK (0xF000U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT (12U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK (0xF0000U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT (16U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK (0xF00000U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT (20U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK (0xF000000U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT (24U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK (0xF0000000U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK) |
SP_SYS_STAT - SP System Status | |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK) |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK (0xF0000U) |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT (16U) |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK) |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK (0xF00000U) |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT (20U) |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK (0xF000000U) |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT (24U) |
#define | GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK) |
SP_ROSC_CTRL - SP ROSC Control | |
#define | GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK) |
SP_PRIORITY_0_7 - SP0~7 Priority | |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK (0xFU) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK (0xF0U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT (4U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK (0xF00U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT (8U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK (0xF000U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT (12U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK (0xF0000U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT (16U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK (0xF00000U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT (20U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK (0xF000000U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT (24U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK (0xF0000000U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK) |
SP_PRIORITY_8_15 - SP8~15 Priority | |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK (0xFU) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK (0xF0U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT (4U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK (0xF00U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT (8U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK (0xF000U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT (12U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK (0xF0000U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT (16U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK (0xF00000U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT (20U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK (0xF000000U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT (24U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK (0xF0000000U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK) |
SP_SSAR_SAVE_CTRL - SP SSAR save control | |
#define | GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK) |
SP_LPCG_OFF_CTRL - SP LPCG off control | |
#define | GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK) |
SP_GROUP_DOWN_CTRL - SP group down control | |
#define | GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK) |
SP_ROOT_DOWN_CTRL - SP root down control | |
#define | GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK) |
SP_PLL_OFF_CTRL - SP PLL off control | |
#define | GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK) |
SP_ISO_ON_CTRL - SP ISO on control | |
#define | GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK) |
SP_RESET_EARLY_CTRL - SP reset early control | |
#define | GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK) |
SP_POWER_OFF_CTRL - SP power off control | |
#define | GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK) |
SP_BIAS_OFF_CTRL - SP bias off control | |
#define | GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK) |
SP_BG_PLDO_OFF_CTRL - SP bandgap and PLL_LDO off control | |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK) |
SP_LDO_PRE_CTRL - SP LDO pre control | |
#define | GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK) |
SP_DCDC_DOWN_CTRL - SP DCDC down control | |
#define | GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK) |
SP_DCDC_UP_CTRL - SP DCDC up control | |
#define | GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK) |
SP_LDO_POST_CTRL - SP LDO post control | |
#define | GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK) |
SP_BG_PLDO_ON_CTRL - SP bandgap and PLL_LDO on control | |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK) |
SP_BIAS_ON_CTRL - SP bias on control | |
#define | GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK) |
SP_POWER_ON_CTRL - SP power on control | |
#define | GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK) |
SP_RESET_LATE_CTRL - SP reset late control | |
#define | GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK) |
SP_ISO_OFF_CTRL - SP ISO off control | |
#define | GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK) |
SP_PLL_ON_CTRL - SP PLL on control | |
#define | GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK) |
SP_ROOT_UP_CTRL - SP root up control | |
#define | GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK) |
SP_GROUP_UP_CTRL - SP group up control | |
#define | GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK) |
SP_LPCG_ON_CTRL - SP LPCG on control | |
#define | GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK) |
SP_SSAR_RESTORE_CTRL - SP SSAR restore control | |
#define | GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK) |
STBY_AUTHEN_CTRL - Standby Authentication Control | |
#define | GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) |
#define | GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) |
#define | GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK) |
STBY_MISC - STBY Misc | |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK (0x1U) |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK) |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK (0x2U) |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT (1U) |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK) |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK (0x4U) |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT (2U) |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK) |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK (0x8U) |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT (3U) |
#define | GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK) |
STBY_LPCG_IN_CTRL - STBY lpcg_in control | |
#define | GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK) |
STBY_PLL_IN_CTRL - STBY pll_in control | |
#define | GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK) |
STBY_BIAS_IN_CTRL - STBY bias_in control | |
#define | GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK) |
STBY_PLDO_IN_CTRL - STBY pldo_in control | |
#define | GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK) |
STBY_BANDGAP_IN_CTRL - STBY bandgap_in control | |
#define | GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK) |
STBY_LDO_IN_CTRL - STBY ldo_in control | |
#define | GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK) |
STBY_DCDC_IN_CTRL - STBY dcdc_in control | |
#define | GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK) |
STBY_PMIC_IN_CTRL - STBY PMIC in control | |
#define | GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK) |
STBY_PMIC_OUT_CTRL - STBY PMIC out control | |
#define | GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK) |
STBY_DCDC_OUT_CTRL - STBY DCDC out control | |
#define | GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK) |
STBY_LDO_OUT_CTRL - STBY LDO out control | |
#define | GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK) |
STBY_BANDGAP_OUT_CTRL - STBY bandgap out control | |
#define | GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK) |
STBY_PLDO_OUT_CTRL - STBY pldo out control | |
#define | GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK) |
STBY_BIAS_OUT_CTRL - STBY bias out control | |
#define | GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK) |
STBY_PLL_OUT_CTRL - STBY PLL out control | |
#define | GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK) |
STBY_LPCG_OUT_CTRL - STBY LPCG out control | |
#define | GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) |
#define | GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT (0U) |
#define | GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK) |
#define | GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK (0x30000000U) |
#define | GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT (28U) |
#define | GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK) |
#define | GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK (0x80000000U) |
#define | GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT (31U) |
#define | GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK) |
DR - GPIO data register | |
#define | GPIO_DR_DR_MASK (0xFFFFFFFFU) |
#define | GPIO_DR_DR_SHIFT (0U) |
#define | GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) |
GDIR - GPIO direction register | |
#define | GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) |
#define | GPIO_GDIR_GDIR_SHIFT (0U) |
#define | GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) |
PSR - GPIO pad status register | |
#define | GPIO_PSR_PSR_MASK (0xFFFFFFFFU) |
#define | GPIO_PSR_PSR_SHIFT (0U) |
#define | GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) |
ICR1 - GPIO interrupt configuration register1 | |
#define | GPIO_ICR1_ICR0_MASK (0x3U) |
#define | GPIO_ICR1_ICR0_SHIFT (0U) |
#define | GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) |
#define | GPIO_ICR1_ICR1_MASK (0xCU) |
#define | GPIO_ICR1_ICR1_SHIFT (2U) |
#define | GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) |
#define | GPIO_ICR1_ICR2_MASK (0x30U) |
#define | GPIO_ICR1_ICR2_SHIFT (4U) |
#define | GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) |
#define | GPIO_ICR1_ICR3_MASK (0xC0U) |
#define | GPIO_ICR1_ICR3_SHIFT (6U) |
#define | GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) |
#define | GPIO_ICR1_ICR4_MASK (0x300U) |
#define | GPIO_ICR1_ICR4_SHIFT (8U) |
#define | GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) |
#define | GPIO_ICR1_ICR5_MASK (0xC00U) |
#define | GPIO_ICR1_ICR5_SHIFT (10U) |
#define | GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) |
#define | GPIO_ICR1_ICR6_MASK (0x3000U) |
#define | GPIO_ICR1_ICR6_SHIFT (12U) |
#define | GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) |
#define | GPIO_ICR1_ICR7_MASK (0xC000U) |
#define | GPIO_ICR1_ICR7_SHIFT (14U) |
#define | GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) |
#define | GPIO_ICR1_ICR8_MASK (0x30000U) |
#define | GPIO_ICR1_ICR8_SHIFT (16U) |
#define | GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) |
#define | GPIO_ICR1_ICR9_MASK (0xC0000U) |
#define | GPIO_ICR1_ICR9_SHIFT (18U) |
#define | GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) |
#define | GPIO_ICR1_ICR10_MASK (0x300000U) |
#define | GPIO_ICR1_ICR10_SHIFT (20U) |
#define | GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) |
#define | GPIO_ICR1_ICR11_MASK (0xC00000U) |
#define | GPIO_ICR1_ICR11_SHIFT (22U) |
#define | GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) |
#define | GPIO_ICR1_ICR12_MASK (0x3000000U) |
#define | GPIO_ICR1_ICR12_SHIFT (24U) |
#define | GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) |
#define | GPIO_ICR1_ICR13_MASK (0xC000000U) |
#define | GPIO_ICR1_ICR13_SHIFT (26U) |
#define | GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) |
#define | GPIO_ICR1_ICR14_MASK (0x30000000U) |
#define | GPIO_ICR1_ICR14_SHIFT (28U) |
#define | GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) |
#define | GPIO_ICR1_ICR15_MASK (0xC0000000U) |
#define | GPIO_ICR1_ICR15_SHIFT (30U) |
#define | GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) |
ICR2 - GPIO interrupt configuration register2 | |
#define | GPIO_ICR2_ICR16_MASK (0x3U) |
#define | GPIO_ICR2_ICR16_SHIFT (0U) |
#define | GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) |
#define | GPIO_ICR2_ICR17_MASK (0xCU) |
#define | GPIO_ICR2_ICR17_SHIFT (2U) |
#define | GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) |
#define | GPIO_ICR2_ICR18_MASK (0x30U) |
#define | GPIO_ICR2_ICR18_SHIFT (4U) |
#define | GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) |
#define | GPIO_ICR2_ICR19_MASK (0xC0U) |
#define | GPIO_ICR2_ICR19_SHIFT (6U) |
#define | GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) |
#define | GPIO_ICR2_ICR20_MASK (0x300U) |
#define | GPIO_ICR2_ICR20_SHIFT (8U) |
#define | GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) |
#define | GPIO_ICR2_ICR21_MASK (0xC00U) |
#define | GPIO_ICR2_ICR21_SHIFT (10U) |
#define | GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) |
#define | GPIO_ICR2_ICR22_MASK (0x3000U) |
#define | GPIO_ICR2_ICR22_SHIFT (12U) |
#define | GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) |
#define | GPIO_ICR2_ICR23_MASK (0xC000U) |
#define | GPIO_ICR2_ICR23_SHIFT (14U) |
#define | GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) |
#define | GPIO_ICR2_ICR24_MASK (0x30000U) |
#define | GPIO_ICR2_ICR24_SHIFT (16U) |
#define | GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) |
#define | GPIO_ICR2_ICR25_MASK (0xC0000U) |
#define | GPIO_ICR2_ICR25_SHIFT (18U) |
#define | GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) |
#define | GPIO_ICR2_ICR26_MASK (0x300000U) |
#define | GPIO_ICR2_ICR26_SHIFT (20U) |
#define | GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) |
#define | GPIO_ICR2_ICR27_MASK (0xC00000U) |
#define | GPIO_ICR2_ICR27_SHIFT (22U) |
#define | GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) |
#define | GPIO_ICR2_ICR28_MASK (0x3000000U) |
#define | GPIO_ICR2_ICR28_SHIFT (24U) |
#define | GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) |
#define | GPIO_ICR2_ICR29_MASK (0xC000000U) |
#define | GPIO_ICR2_ICR29_SHIFT (26U) |
#define | GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) |
#define | GPIO_ICR2_ICR30_MASK (0x30000000U) |
#define | GPIO_ICR2_ICR30_SHIFT (28U) |
#define | GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) |
#define | GPIO_ICR2_ICR31_MASK (0xC0000000U) |
#define | GPIO_ICR2_ICR31_SHIFT (30U) |
#define | GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) |
IMR - GPIO interrupt mask register | |
#define | GPIO_IMR_IMR_MASK (0xFFFFFFFFU) |
#define | GPIO_IMR_IMR_SHIFT (0U) |
#define | GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) |
ISR - GPIO interrupt status register | |
#define | GPIO_ISR_ISR_MASK (0xFFFFFFFFU) |
#define | GPIO_ISR_ISR_SHIFT (0U) |
#define | GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) |
EDGE_SEL - GPIO edge select register | |
#define | GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) |
#define | GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) |
#define | GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) |
DR_SET - GPIO data register SET | |
#define | GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) |
#define | GPIO_DR_SET_DR_SET_SHIFT (0U) |
#define | GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) |
DR_CLEAR - GPIO data register CLEAR | |
#define | GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) |
#define | GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) |
#define | GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) |
DR_TOGGLE - GPIO data register TOGGLE | |
#define | GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) |
#define | GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) |
#define | GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) |
CR - GPT Control Register | |
#define | GPT_CR_EN_MASK (0x1U) |
#define | GPT_CR_EN_SHIFT (0U) |
#define | GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) |
#define | GPT_CR_ENMOD_MASK (0x2U) |
#define | GPT_CR_ENMOD_SHIFT (1U) |
#define | GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) |
#define | GPT_CR_DBGEN_MASK (0x4U) |
#define | GPT_CR_DBGEN_SHIFT (2U) |
#define | GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) |
#define | GPT_CR_WAITEN_MASK (0x8U) |
#define | GPT_CR_WAITEN_SHIFT (3U) |
#define | GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) |
#define | GPT_CR_DOZEEN_MASK (0x10U) |
#define | GPT_CR_DOZEEN_SHIFT (4U) |
#define | GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) |
#define | GPT_CR_STOPEN_MASK (0x20U) |
#define | GPT_CR_STOPEN_SHIFT (5U) |
#define | GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) |
#define | GPT_CR_CLKSRC_MASK (0x1C0U) |
#define | GPT_CR_CLKSRC_SHIFT (6U) |
#define | GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) |
#define | GPT_CR_FRR_MASK (0x200U) |
#define | GPT_CR_FRR_SHIFT (9U) |
#define | GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) |
#define | GPT_CR_EN_24M_MASK (0x400U) |
#define | GPT_CR_EN_24M_SHIFT (10U) |
#define | GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) |
#define | GPT_CR_SWR_MASK (0x8000U) |
#define | GPT_CR_SWR_SHIFT (15U) |
#define | GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) |
#define | GPT_CR_IM1_MASK (0x30000U) |
#define | GPT_CR_IM1_SHIFT (16U) |
#define | GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) |
#define | GPT_CR_IM2_MASK (0xC0000U) |
#define | GPT_CR_IM2_SHIFT (18U) |
#define | GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) |
#define | GPT_CR_OM1_MASK (0x700000U) |
#define | GPT_CR_OM1_SHIFT (20U) |
#define | GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) |
#define | GPT_CR_OM2_MASK (0x3800000U) |
#define | GPT_CR_OM2_SHIFT (23U) |
#define | GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) |
#define | GPT_CR_OM3_MASK (0x1C000000U) |
#define | GPT_CR_OM3_SHIFT (26U) |
#define | GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) |
#define | GPT_CR_FO1_MASK (0x20000000U) |
#define | GPT_CR_FO1_SHIFT (29U) |
#define | GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) |
#define | GPT_CR_FO2_MASK (0x40000000U) |
#define | GPT_CR_FO2_SHIFT (30U) |
#define | GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) |
#define | GPT_CR_FO3_MASK (0x80000000U) |
#define | GPT_CR_FO3_SHIFT (31U) |
#define | GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) |
PR - GPT Prescaler Register | |
#define | GPT_PR_PRESCALER_MASK (0xFFFU) |
#define | GPT_PR_PRESCALER_SHIFT (0U) |
#define | GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) |
#define | GPT_PR_PRESCALER24M_MASK (0xF000U) |
#define | GPT_PR_PRESCALER24M_SHIFT (12U) |
#define | GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) |
SR - GPT Status Register | |
#define | GPT_SR_OF1_MASK (0x1U) |
#define | GPT_SR_OF1_SHIFT (0U) |
#define | GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) |
#define | GPT_SR_OF2_MASK (0x2U) |
#define | GPT_SR_OF2_SHIFT (1U) |
#define | GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) |
#define | GPT_SR_OF3_MASK (0x4U) |
#define | GPT_SR_OF3_SHIFT (2U) |
#define | GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) |
#define | GPT_SR_IF1_MASK (0x8U) |
#define | GPT_SR_IF1_SHIFT (3U) |
#define | GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) |
#define | GPT_SR_IF2_MASK (0x10U) |
#define | GPT_SR_IF2_SHIFT (4U) |
#define | GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) |
#define | GPT_SR_ROV_MASK (0x20U) |
#define | GPT_SR_ROV_SHIFT (5U) |
#define | GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) |
IR - GPT Interrupt Register | |
#define | GPT_IR_OF1IE_MASK (0x1U) |
#define | GPT_IR_OF1IE_SHIFT (0U) |
#define | GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) |
#define | GPT_IR_OF2IE_MASK (0x2U) |
#define | GPT_IR_OF2IE_SHIFT (1U) |
#define | GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) |
#define | GPT_IR_OF3IE_MASK (0x4U) |
#define | GPT_IR_OF3IE_SHIFT (2U) |
#define | GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) |
#define | GPT_IR_IF1IE_MASK (0x8U) |
#define | GPT_IR_IF1IE_SHIFT (3U) |
#define | GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) |
#define | GPT_IR_IF2IE_MASK (0x10U) |
#define | GPT_IR_IF2IE_SHIFT (4U) |
#define | GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) |
#define | GPT_IR_ROVIE_MASK (0x20U) |
#define | GPT_IR_ROVIE_SHIFT (5U) |
#define | GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) |
OCR - GPT Output Compare Register | |
#define | GPT_OCR_COMP_MASK (0xFFFFFFFFU) |
#define | GPT_OCR_COMP_SHIFT (0U) |
#define | GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) |
ICR - GPT Input Capture Register | |
#define | GPT_ICR_CAPT_MASK (0xFFFFFFFFU) |
#define | GPT_ICR_CAPT_SHIFT (0U) |
#define | GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) |
CNT - GPT Counter Register | |
#define | GPT_CNT_COUNT_MASK (0xFFFFFFFFU) |
#define | GPT_CNT_COUNT_SHIFT (0U) |
#define | GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) |
VERID - Version ID | |
#define | I2S_VERID_FEATURE_MASK (0xFFFFU) |
#define | I2S_VERID_FEATURE_SHIFT (0U) |
#define | I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) |
#define | I2S_VERID_MINOR_MASK (0xFF0000U) |
#define | I2S_VERID_MINOR_SHIFT (16U) |
#define | I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) |
#define | I2S_VERID_MAJOR_MASK (0xFF000000U) |
#define | I2S_VERID_MAJOR_SHIFT (24U) |
#define | I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) |
#define | LPI2C_VERID_FEATURE_MASK (0xFFFFU) |
#define | LPI2C_VERID_FEATURE_SHIFT (0U) |
#define | LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) |
#define | LPI2C_VERID_MINOR_MASK (0xFF0000U) |
#define | LPI2C_VERID_MINOR_SHIFT (16U) |
#define | LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) |
#define | LPI2C_VERID_MAJOR_MASK (0xFF000000U) |
#define | LPI2C_VERID_MAJOR_SHIFT (24U) |
#define | LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) |
#define | LPSPI_VERID_FEATURE_MASK (0xFFFFU) |
#define | LPSPI_VERID_FEATURE_SHIFT (0U) |
#define | LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) |
#define | LPSPI_VERID_MINOR_MASK (0xFF0000U) |
#define | LPSPI_VERID_MINOR_SHIFT (16U) |
#define | LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) |
#define | LPSPI_VERID_MAJOR_MASK (0xFF000000U) |
#define | LPSPI_VERID_MAJOR_SHIFT (24U) |
#define | LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) |
PARAM - Parameter | |
#define | I2S_PARAM_DATALINE_MASK (0xFU) |
#define | I2S_PARAM_DATALINE_SHIFT (0U) |
#define | I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) |
#define | I2S_PARAM_FIFO_MASK (0xF00U) |
#define | I2S_PARAM_FIFO_SHIFT (8U) |
#define | I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) |
#define | I2S_PARAM_FRAME_MASK (0xF0000U) |
#define | I2S_PARAM_FRAME_SHIFT (16U) |
#define | I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) |
#define | LPI2C_PARAM_MTXFIFO_MASK (0xFU) |
#define | LPI2C_PARAM_MTXFIFO_SHIFT (0U) |
#define | LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) |
#define | LPI2C_PARAM_MRXFIFO_MASK (0xF00U) |
#define | LPI2C_PARAM_MRXFIFO_SHIFT (8U) |
#define | LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) |
#define | LPSPI_PARAM_TXFIFO_MASK (0xFFU) |
#define | LPSPI_PARAM_TXFIFO_SHIFT (0U) |
#define | LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) |
#define | LPSPI_PARAM_RXFIFO_MASK (0xFF00U) |
#define | LPSPI_PARAM_RXFIFO_SHIFT (8U) |
#define | LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) |
#define | LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) |
#define | LPSPI_PARAM_PCSNUM_SHIFT (16U) |
#define | LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) |
TCSR - Transmit Control | |
#define | I2S_TCSR_FRDE_MASK (0x1U) |
#define | I2S_TCSR_FRDE_SHIFT (0U) |
#define | I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) |
#define | I2S_TCSR_FWDE_MASK (0x2U) |
#define | I2S_TCSR_FWDE_SHIFT (1U) |
#define | I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) |
#define | I2S_TCSR_FRIE_MASK (0x100U) |
#define | I2S_TCSR_FRIE_SHIFT (8U) |
#define | I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) |
#define | I2S_TCSR_FWIE_MASK (0x200U) |
#define | I2S_TCSR_FWIE_SHIFT (9U) |
#define | I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) |
#define | I2S_TCSR_FEIE_MASK (0x400U) |
#define | I2S_TCSR_FEIE_SHIFT (10U) |
#define | I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) |
#define | I2S_TCSR_SEIE_MASK (0x800U) |
#define | I2S_TCSR_SEIE_SHIFT (11U) |
#define | I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) |
#define | I2S_TCSR_WSIE_MASK (0x1000U) |
#define | I2S_TCSR_WSIE_SHIFT (12U) |
#define | I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) |
#define | I2S_TCSR_FRF_MASK (0x10000U) |
#define | I2S_TCSR_FRF_SHIFT (16U) |
#define | I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) |
#define | I2S_TCSR_FWF_MASK (0x20000U) |
#define | I2S_TCSR_FWF_SHIFT (17U) |
#define | I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) |
#define | I2S_TCSR_FEF_MASK (0x40000U) |
#define | I2S_TCSR_FEF_SHIFT (18U) |
#define | I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) |
#define | I2S_TCSR_SEF_MASK (0x80000U) |
#define | I2S_TCSR_SEF_SHIFT (19U) |
#define | I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) |
#define | I2S_TCSR_WSF_MASK (0x100000U) |
#define | I2S_TCSR_WSF_SHIFT (20U) |
#define | I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) |
#define | I2S_TCSR_SR_MASK (0x1000000U) |
#define | I2S_TCSR_SR_SHIFT (24U) |
#define | I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) |
#define | I2S_TCSR_FR_MASK (0x2000000U) |
#define | I2S_TCSR_FR_SHIFT (25U) |
#define | I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) |
#define | I2S_TCSR_BCE_MASK (0x10000000U) |
#define | I2S_TCSR_BCE_SHIFT (28U) |
#define | I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) |
#define | I2S_TCSR_DBGE_MASK (0x20000000U) |
#define | I2S_TCSR_DBGE_SHIFT (29U) |
#define | I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) |
#define | I2S_TCSR_STOPE_MASK (0x40000000U) |
#define | I2S_TCSR_STOPE_SHIFT (30U) |
#define | I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) |
#define | I2S_TCSR_TE_MASK (0x80000000U) |
#define | I2S_TCSR_TE_SHIFT (31U) |
#define | I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) |
TCR1 - Transmit Configuration 1 | |
#define | I2S_TCR1_TFW_MASK (0x1FU) |
#define | I2S_TCR1_TFW_SHIFT (0U) |
#define | I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) |
TCR2 - Transmit Configuration 2 | |
#define | I2S_TCR2_DIV_MASK (0xFFU) |
#define | I2S_TCR2_DIV_SHIFT (0U) |
#define | I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) |
#define | I2S_TCR2_BYP_MASK (0x800000U) |
#define | I2S_TCR2_BYP_SHIFT (23U) |
#define | I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) |
#define | I2S_TCR2_BCD_MASK (0x1000000U) |
#define | I2S_TCR2_BCD_SHIFT (24U) |
#define | I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) |
#define | I2S_TCR2_BCP_MASK (0x2000000U) |
#define | I2S_TCR2_BCP_SHIFT (25U) |
#define | I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) |
#define | I2S_TCR2_MSEL_MASK (0xC000000U) |
#define | I2S_TCR2_MSEL_SHIFT (26U) |
#define | I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) |
#define | I2S_TCR2_BCI_MASK (0x10000000U) |
#define | I2S_TCR2_BCI_SHIFT (28U) |
#define | I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) |
#define | I2S_TCR2_BCS_MASK (0x20000000U) |
#define | I2S_TCR2_BCS_SHIFT (29U) |
#define | I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) |
#define | I2S_TCR2_SYNC_MASK (0x40000000U) |
#define | I2S_TCR2_SYNC_SHIFT (30U) |
#define | I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) |
TCR3 - Transmit Configuration 3 | |
#define | I2S_TCR3_WDFL_MASK (0x1FU) |
#define | I2S_TCR3_WDFL_SHIFT (0U) |
#define | I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) |
#define | I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
#define | I2S_TCR3_TCE_SHIFT (16U) |
#define | I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
#define | I2S_TCR3_CFR_MASK (0xF000000U) |
#define | I2S_TCR3_CFR_SHIFT (24U) |
#define | I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) |
TCR4 - Transmit Configuration 4 | |
#define | I2S_TCR4_FSD_MASK (0x1U) |
#define | I2S_TCR4_FSD_SHIFT (0U) |
#define | I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) |
#define | I2S_TCR4_FSP_MASK (0x2U) |
#define | I2S_TCR4_FSP_SHIFT (1U) |
#define | I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) |
#define | I2S_TCR4_ONDEM_MASK (0x4U) |
#define | I2S_TCR4_ONDEM_SHIFT (2U) |
#define | I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) |
#define | I2S_TCR4_FSE_MASK (0x8U) |
#define | I2S_TCR4_FSE_SHIFT (3U) |
#define | I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) |
#define | I2S_TCR4_MF_MASK (0x10U) |
#define | I2S_TCR4_MF_SHIFT (4U) |
#define | I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) |
#define | I2S_TCR4_CHMOD_MASK (0x20U) |
#define | I2S_TCR4_CHMOD_SHIFT (5U) |
#define | I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) |
#define | I2S_TCR4_SYWD_MASK (0x1F00U) |
#define | I2S_TCR4_SYWD_SHIFT (8U) |
#define | I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) |
#define | I2S_TCR4_FRSZ_MASK (0x1F0000U) |
#define | I2S_TCR4_FRSZ_SHIFT (16U) |
#define | I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) |
#define | I2S_TCR4_FPACK_MASK (0x3000000U) |
#define | I2S_TCR4_FPACK_SHIFT (24U) |
#define | I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) |
#define | I2S_TCR4_FCOMB_MASK (0xC000000U) |
#define | I2S_TCR4_FCOMB_SHIFT (26U) |
#define | I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) |
#define | I2S_TCR4_FCONT_MASK (0x10000000U) |
#define | I2S_TCR4_FCONT_SHIFT (28U) |
#define | I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) |
TCR5 - Transmit Configuration 5 | |
#define | I2S_TCR5_FBT_MASK (0x1F00U) |
#define | I2S_TCR5_FBT_SHIFT (8U) |
#define | I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) |
#define | I2S_TCR5_W0W_MASK (0x1F0000U) |
#define | I2S_TCR5_W0W_SHIFT (16U) |
#define | I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) |
#define | I2S_TCR5_WNW_MASK (0x1F000000U) |
#define | I2S_TCR5_WNW_SHIFT (24U) |
#define | I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) |
TDR - Transmit Data | |
#define | I2S_TDR_TDR_MASK (0xFFFFFFFFU) |
#define | I2S_TDR_TDR_SHIFT (0U) |
#define | I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) |
#define | LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) |
#define | LPSPI_TDR_DATA_SHIFT (0U) |
#define | LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) |
TFR - Transmit FIFO | |
#define | I2S_TFR_RFP_MASK (0x3FU) |
#define | I2S_TFR_RFP_SHIFT (0U) |
#define | I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) |
#define | I2S_TFR_WFP_MASK (0x3F0000U) |
#define | I2S_TFR_WFP_SHIFT (16U) |
#define | I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) |
#define | I2S_TFR_WCP_MASK (0x80000000U) |
#define | I2S_TFR_WCP_SHIFT (31U) |
#define | I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) |
TMR - Transmit Mask | |
#define | I2S_TMR_TWM_MASK (0xFFFFFFFFU) |
#define | I2S_TMR_TWM_SHIFT (0U) |
#define | I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) |
RCSR - Receive Control | |
#define | I2S_RCSR_FRDE_MASK (0x1U) |
#define | I2S_RCSR_FRDE_SHIFT (0U) |
#define | I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) |
#define | I2S_RCSR_FWDE_MASK (0x2U) |
#define | I2S_RCSR_FWDE_SHIFT (1U) |
#define | I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) |
#define | I2S_RCSR_FRIE_MASK (0x100U) |
#define | I2S_RCSR_FRIE_SHIFT (8U) |
#define | I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) |
#define | I2S_RCSR_FWIE_MASK (0x200U) |
#define | I2S_RCSR_FWIE_SHIFT (9U) |
#define | I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) |
#define | I2S_RCSR_FEIE_MASK (0x400U) |
#define | I2S_RCSR_FEIE_SHIFT (10U) |
#define | I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) |
#define | I2S_RCSR_SEIE_MASK (0x800U) |
#define | I2S_RCSR_SEIE_SHIFT (11U) |
#define | I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) |
#define | I2S_RCSR_WSIE_MASK (0x1000U) |
#define | I2S_RCSR_WSIE_SHIFT (12U) |
#define | I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) |
#define | I2S_RCSR_FRF_MASK (0x10000U) |
#define | I2S_RCSR_FRF_SHIFT (16U) |
#define | I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) |
#define | I2S_RCSR_FWF_MASK (0x20000U) |
#define | I2S_RCSR_FWF_SHIFT (17U) |
#define | I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) |
#define | I2S_RCSR_FEF_MASK (0x40000U) |
#define | I2S_RCSR_FEF_SHIFT (18U) |
#define | I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) |
#define | I2S_RCSR_SEF_MASK (0x80000U) |
#define | I2S_RCSR_SEF_SHIFT (19U) |
#define | I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) |
#define | I2S_RCSR_WSF_MASK (0x100000U) |
#define | I2S_RCSR_WSF_SHIFT (20U) |
#define | I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) |
#define | I2S_RCSR_SR_MASK (0x1000000U) |
#define | I2S_RCSR_SR_SHIFT (24U) |
#define | I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) |
#define | I2S_RCSR_FR_MASK (0x2000000U) |
#define | I2S_RCSR_FR_SHIFT (25U) |
#define | I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) |
#define | I2S_RCSR_BCE_MASK (0x10000000U) |
#define | I2S_RCSR_BCE_SHIFT (28U) |
#define | I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) |
#define | I2S_RCSR_DBGE_MASK (0x20000000U) |
#define | I2S_RCSR_DBGE_SHIFT (29U) |
#define | I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) |
#define | I2S_RCSR_STOPE_MASK (0x40000000U) |
#define | I2S_RCSR_STOPE_SHIFT (30U) |
#define | I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) |
#define | I2S_RCSR_RE_MASK (0x80000000U) |
#define | I2S_RCSR_RE_SHIFT (31U) |
#define | I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) |
RCR1 - Receive Configuration 1 | |
#define | I2S_RCR1_RFW_MASK (0x1FU) |
#define | I2S_RCR1_RFW_SHIFT (0U) |
#define | I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) |
RCR2 - Receive Configuration 2 | |
#define | I2S_RCR2_DIV_MASK (0xFFU) |
#define | I2S_RCR2_DIV_SHIFT (0U) |
#define | I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) |
#define | I2S_RCR2_BYP_MASK (0x800000U) |
#define | I2S_RCR2_BYP_SHIFT (23U) |
#define | I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) |
#define | I2S_RCR2_BCD_MASK (0x1000000U) |
#define | I2S_RCR2_BCD_SHIFT (24U) |
#define | I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) |
#define | I2S_RCR2_BCP_MASK (0x2000000U) |
#define | I2S_RCR2_BCP_SHIFT (25U) |
#define | I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) |
#define | I2S_RCR2_MSEL_MASK (0xC000000U) |
#define | I2S_RCR2_MSEL_SHIFT (26U) |
#define | I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) |
#define | I2S_RCR2_BCI_MASK (0x10000000U) |
#define | I2S_RCR2_BCI_SHIFT (28U) |
#define | I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) |
#define | I2S_RCR2_BCS_MASK (0x20000000U) |
#define | I2S_RCR2_BCS_SHIFT (29U) |
#define | I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) |
#define | I2S_RCR2_SYNC_MASK (0x40000000U) |
#define | I2S_RCR2_SYNC_SHIFT (30U) |
#define | I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) |
RCR3 - Receive Configuration 3 | |
#define | I2S_RCR3_WDFL_MASK (0x1FU) |
#define | I2S_RCR3_WDFL_SHIFT (0U) |
#define | I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) |
#define | I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
#define | I2S_RCR3_RCE_SHIFT (16U) |
#define | I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ |
#define | I2S_RCR3_CFR_MASK (0xF000000U) |
#define | I2S_RCR3_CFR_SHIFT (24U) |
#define | I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) |
RCR4 - Receive Configuration 4 | |
#define | I2S_RCR4_FSD_MASK (0x1U) |
#define | I2S_RCR4_FSD_SHIFT (0U) |
#define | I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) |
#define | I2S_RCR4_FSP_MASK (0x2U) |
#define | I2S_RCR4_FSP_SHIFT (1U) |
#define | I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) |
#define | I2S_RCR4_ONDEM_MASK (0x4U) |
#define | I2S_RCR4_ONDEM_SHIFT (2U) |
#define | I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) |
#define | I2S_RCR4_FSE_MASK (0x8U) |
#define | I2S_RCR4_FSE_SHIFT (3U) |
#define | I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) |
#define | I2S_RCR4_MF_MASK (0x10U) |
#define | I2S_RCR4_MF_SHIFT (4U) |
#define | I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) |
#define | I2S_RCR4_SYWD_MASK (0x1F00U) |
#define | I2S_RCR4_SYWD_SHIFT (8U) |
#define | I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) |
#define | I2S_RCR4_FRSZ_MASK (0x1F0000U) |
#define | I2S_RCR4_FRSZ_SHIFT (16U) |
#define | I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) |
#define | I2S_RCR4_FPACK_MASK (0x3000000U) |
#define | I2S_RCR4_FPACK_SHIFT (24U) |
#define | I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) |
#define | I2S_RCR4_FCOMB_MASK (0xC000000U) |
#define | I2S_RCR4_FCOMB_SHIFT (26U) |
#define | I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) |
#define | I2S_RCR4_FCONT_MASK (0x10000000U) |
#define | I2S_RCR4_FCONT_SHIFT (28U) |
#define | I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) |
RCR5 - Receive Configuration 5 | |
#define | I2S_RCR5_FBT_MASK (0x1F00U) |
#define | I2S_RCR5_FBT_SHIFT (8U) |
#define | I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) |
#define | I2S_RCR5_W0W_MASK (0x1F0000U) |
#define | I2S_RCR5_W0W_SHIFT (16U) |
#define | I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) |
#define | I2S_RCR5_WNW_MASK (0x1F000000U) |
#define | I2S_RCR5_WNW_SHIFT (24U) |
#define | I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) |
RDR - Receive Data | |
#define | I2S_RDR_RDR_MASK (0xFFFFFFFFU) |
#define | I2S_RDR_RDR_SHIFT (0U) |
#define | I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) |
#define | LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) |
#define | LPSPI_RDR_DATA_SHIFT (0U) |
#define | LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) |
RFR - Receive FIFO | |
#define | I2S_RFR_RFP_MASK (0x3FU) |
#define | I2S_RFR_RFP_SHIFT (0U) |
#define | I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) |
#define | I2S_RFR_RCP_MASK (0x8000U) |
#define | I2S_RFR_RCP_SHIFT (15U) |
#define | I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) |
#define | I2S_RFR_WFP_MASK (0x3F0000U) |
#define | I2S_RFR_WFP_SHIFT (16U) |
#define | I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) |
RMR - Receive Mask | |
#define | I2S_RMR_RWM_MASK (0xFFFFFFFFU) |
#define | I2S_RMR_RWM_SHIFT (0U) |
#define | I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) |
GCFG - IEE Global Configuration | |
#define | IEE_GCFG_RL0_MASK (0x1U) |
#define | IEE_GCFG_RL0_SHIFT (0U) |
#define | IEE_GCFG_RL0(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK) |
#define | IEE_GCFG_RL1_MASK (0x2U) |
#define | IEE_GCFG_RL1_SHIFT (1U) |
#define | IEE_GCFG_RL1(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK) |
#define | IEE_GCFG_RL2_MASK (0x4U) |
#define | IEE_GCFG_RL2_SHIFT (2U) |
#define | IEE_GCFG_RL2(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK) |
#define | IEE_GCFG_RL3_MASK (0x8U) |
#define | IEE_GCFG_RL3_SHIFT (3U) |
#define | IEE_GCFG_RL3(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK) |
#define | IEE_GCFG_RL4_MASK (0x10U) |
#define | IEE_GCFG_RL4_SHIFT (4U) |
#define | IEE_GCFG_RL4(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK) |
#define | IEE_GCFG_RL5_MASK (0x20U) |
#define | IEE_GCFG_RL5_SHIFT (5U) |
#define | IEE_GCFG_RL5(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK) |
#define | IEE_GCFG_RL6_MASK (0x40U) |
#define | IEE_GCFG_RL6_SHIFT (6U) |
#define | IEE_GCFG_RL6(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK) |
#define | IEE_GCFG_RL7_MASK (0x80U) |
#define | IEE_GCFG_RL7_SHIFT (7U) |
#define | IEE_GCFG_RL7(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK) |
#define | IEE_GCFG_TME_MASK (0x10000U) |
#define | IEE_GCFG_TME_SHIFT (16U) |
#define | IEE_GCFG_TME(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK) |
#define | IEE_GCFG_TMD_MASK (0x20000U) |
#define | IEE_GCFG_TMD_SHIFT (17U) |
#define | IEE_GCFG_TMD(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK) |
#define | IEE_GCFG_KEY_RD_DIS_MASK (0x2000000U) |
#define | IEE_GCFG_KEY_RD_DIS_SHIFT (25U) |
#define | IEE_GCFG_KEY_RD_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK) |
#define | IEE_GCFG_MON_EN_MASK (0x10000000U) |
#define | IEE_GCFG_MON_EN_SHIFT (28U) |
#define | IEE_GCFG_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK) |
#define | IEE_GCFG_CLR_MON_MASK (0x20000000U) |
#define | IEE_GCFG_CLR_MON_SHIFT (29U) |
#define | IEE_GCFG_CLR_MON(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK) |
#define | IEE_GCFG_RST_MASK (0x80000000U) |
#define | IEE_GCFG_RST_SHIFT (31U) |
#define | IEE_GCFG_RST(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RST_SHIFT)) & IEE_GCFG_RST_MASK) |
STA - IEE Status | |
#define | IEE_STA_DSR_MASK (0x1U) |
#define | IEE_STA_DSR_SHIFT (0U) |
#define | IEE_STA_DSR(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK) |
#define | IEE_STA_AFD_MASK (0x10U) |
#define | IEE_STA_AFD_SHIFT (4U) |
#define | IEE_STA_AFD(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK) |
TSTMD - IEE Test Mode Register | |
#define | IEE_TSTMD_TMRDY_MASK (0x1U) |
#define | IEE_TSTMD_TMRDY_SHIFT (0U) |
#define | IEE_TSTMD_TMRDY(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK) |
#define | IEE_TSTMD_TMR_MASK (0x2U) |
#define | IEE_TSTMD_TMR_SHIFT (1U) |
#define | IEE_TSTMD_TMR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK) |
#define | IEE_TSTMD_TMENCR_MASK (0x4U) |
#define | IEE_TSTMD_TMENCR_SHIFT (2U) |
#define | IEE_TSTMD_TMENCR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK) |
#define | IEE_TSTMD_TMCONT_MASK (0x8U) |
#define | IEE_TSTMD_TMCONT_SHIFT (3U) |
#define | IEE_TSTMD_TMCONT(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK) |
#define | IEE_TSTMD_TMDONE_MASK (0x10U) |
#define | IEE_TSTMD_TMDONE_SHIFT (4U) |
#define | IEE_TSTMD_TMDONE(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK) |
#define | IEE_TSTMD_TMLEN_MASK (0xF00U) |
#define | IEE_TSTMD_TMLEN_SHIFT (8U) |
#define | IEE_TSTMD_TMLEN(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMLEN_SHIFT)) & IEE_TSTMD_TMLEN_MASK) |
DPAMS - AES Mask Generation Seed | |
#define | IEE_DPAMS_DPAMS_MASK (0xFFFFFFFFU) |
#define | IEE_DPAMS_DPAMS_SHIFT (0U) |
#define | IEE_DPAMS_DPAMS(x) (((uint32_t)(((uint32_t)(x)) << IEE_DPAMS_DPAMS_SHIFT)) & IEE_DPAMS_DPAMS_MASK) |
PC_S_LT - Performance Counter, AES Slave Latency Threshold Value | |
#define | IEE_PC_S_LT_SW_LT_MASK (0xFFFFU) |
#define | IEE_PC_S_LT_SW_LT_SHIFT (0U) |
#define | IEE_PC_S_LT_SW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SW_LT_SHIFT)) & IEE_PC_S_LT_SW_LT_MASK) |
#define | IEE_PC_S_LT_SR_LT_MASK (0xFFFF0000U) |
#define | IEE_PC_S_LT_SR_LT_SHIFT (16U) |
#define | IEE_PC_S_LT_SR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SR_LT_SHIFT)) & IEE_PC_S_LT_SR_LT_MASK) |
PC_M_LT - Performance Counter, AES Master Latency Threshold | |
#define | IEE_PC_M_LT_MW_LT_MASK (0xFFFU) |
#define | IEE_PC_M_LT_MW_LT_SHIFT (0U) |
#define | IEE_PC_M_LT_MW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MW_LT_SHIFT)) & IEE_PC_M_LT_MW_LT_MASK) |
#define | IEE_PC_M_LT_MR_LT_MASK (0xFFF0000U) |
#define | IEE_PC_M_LT_MR_LT_SHIFT (16U) |
#define | IEE_PC_M_LT_MR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MR_LT_SHIFT)) & IEE_PC_M_LT_MR_LT_MASK) |
PC_BLK_ENC - Performance Counter, Number of AES Block Encryptions | |
#define | IEE_PC_BLK_ENC_BLK_ENC_MASK (0xFFFFFFFFU) |
#define | IEE_PC_BLK_ENC_BLK_ENC_SHIFT (0U) |
#define | IEE_PC_BLK_ENC_BLK_ENC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_ENC_BLK_ENC_SHIFT)) & IEE_PC_BLK_ENC_BLK_ENC_MASK) |
PC_BLK_DEC - Performance Counter, Number of AES Block Decryptions | |
#define | IEE_PC_BLK_DEC_BLK_DEC_MASK (0xFFFFFFFFU) |
#define | IEE_PC_BLK_DEC_BLK_DEC_SHIFT (0U) |
#define | IEE_PC_BLK_DEC_BLK_DEC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_DEC_BLK_DEC_SHIFT)) & IEE_PC_BLK_DEC_BLK_DEC_MASK) |
PC_SR_TRANS - Performance Counter, Number of AXI Slave Read Transactions | |
#define | IEE_PC_SR_TRANS_SR_TRANS_MASK (0xFFFFFFFFU) |
#define | IEE_PC_SR_TRANS_SR_TRANS_SHIFT (0U) |
#define | IEE_PC_SR_TRANS_SR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TRANS_SR_TRANS_SHIFT)) & IEE_PC_SR_TRANS_SR_TRANS_MASK) |
PC_SW_TRANS - Performance Counter, Number of AXI Slave Write Transactions | |
#define | IEE_PC_SW_TRANS_SW_TRANS_MASK (0xFFFFFFFFU) |
#define | IEE_PC_SW_TRANS_SW_TRANS_SHIFT (0U) |
#define | IEE_PC_SW_TRANS_SW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TRANS_SW_TRANS_SHIFT)) & IEE_PC_SW_TRANS_SW_TRANS_MASK) |
PC_MR_TRANS - Performance Counter, Number of AXI Master Read Transactions | |
#define | IEE_PC_MR_TRANS_MR_TRANS_MASK (0xFFFFFFFFU) |
#define | IEE_PC_MR_TRANS_MR_TRANS_SHIFT (0U) |
#define | IEE_PC_MR_TRANS_MR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TRANS_MR_TRANS_SHIFT)) & IEE_PC_MR_TRANS_MR_TRANS_MASK) |
PC_MW_TRANS - Performance Counter, Number of AXI Master Write Transactions | |
#define | IEE_PC_MW_TRANS_MW_TRANS_MASK (0xFFFFFFFFU) |
#define | IEE_PC_MW_TRANS_MW_TRANS_SHIFT (0U) |
#define | IEE_PC_MW_TRANS_MW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TRANS_MW_TRANS_SHIFT)) & IEE_PC_MW_TRANS_MW_TRANS_MASK) |
PC_M_MBR - Performance Counter, Number of AXI Master Merge Buffer Read Transactions | |
#define | IEE_PC_M_MBR_M_MBR_MASK (0xFFFFFFFFU) |
#define | IEE_PC_M_MBR_M_MBR_SHIFT (0U) |
#define | IEE_PC_M_MBR_M_MBR(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_MBR_M_MBR_SHIFT)) & IEE_PC_M_MBR_M_MBR_MASK) |
PC_SR_TBC_U - Performance Counter, Upper Slave Read Transactions Byte Count | |
#define | IEE_PC_SR_TBC_U_SR_TBC_MASK (0xFFFFU) |
#define | IEE_PC_SR_TBC_U_SR_TBC_SHIFT (0U) |
#define | IEE_PC_SR_TBC_U_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_U_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_U_SR_TBC_MASK) |
PC_SR_TBC_L - Performance Counter, Lower Slave Read Transactions Byte Count | |
#define | IEE_PC_SR_TBC_L_SR_TBC_MASK (0xFFFFFFFFU) |
#define | IEE_PC_SR_TBC_L_SR_TBC_SHIFT (0U) |
#define | IEE_PC_SR_TBC_L_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_L_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_L_SR_TBC_MASK) |
PC_SW_TBC_U - Performance Counter, Upper Slave Write Transactions Byte Count | |
#define | IEE_PC_SW_TBC_U_SW_TBC_MASK (0xFFFFU) |
#define | IEE_PC_SW_TBC_U_SW_TBC_SHIFT (0U) |
#define | IEE_PC_SW_TBC_U_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_U_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_U_SW_TBC_MASK) |
PC_SW_TBC_L - Performance Counter, Lower Slave Write Transactions Byte Count | |
#define | IEE_PC_SW_TBC_L_SW_TBC_MASK (0xFFFFFFFFU) |
#define | IEE_PC_SW_TBC_L_SW_TBC_SHIFT (0U) |
#define | IEE_PC_SW_TBC_L_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_L_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_L_SW_TBC_MASK) |
PC_MR_TBC_U - Performance Counter, Upper Master Read Transactions Byte Count | |
#define | IEE_PC_MR_TBC_U_MR_TBC_MASK (0xFFFFU) |
#define | IEE_PC_MR_TBC_U_MR_TBC_SHIFT (0U) |
#define | IEE_PC_MR_TBC_U_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_U_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_U_MR_TBC_MASK) |
PC_MR_TBC_L - Performance Counter, Lower Master Read Transactions Byte Count | |
#define | IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK (0xFU) |
#define | IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT (0U) |
#define | IEE_PC_MR_TBC_L_MR_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK) |
#define | IEE_PC_MR_TBC_L_MR_TBC_MASK (0xFFFFFFF0U) |
#define | IEE_PC_MR_TBC_L_MR_TBC_SHIFT (4U) |
#define | IEE_PC_MR_TBC_L_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_MASK) |
PC_MW_TBC_U - Performance Counter, Upper Master Write Transactions Byte Count | |
#define | IEE_PC_MW_TBC_U_MW_TBC_MASK (0xFFFFU) |
#define | IEE_PC_MW_TBC_U_MW_TBC_SHIFT (0U) |
#define | IEE_PC_MW_TBC_U_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_U_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_U_MW_TBC_MASK) |
PC_MW_TBC_L - Performance Counter, Lower Master Write Transactions Byte Count | |
#define | IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK (0xFU) |
#define | IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT (0U) |
#define | IEE_PC_MW_TBC_L_MW_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK) |
#define | IEE_PC_MW_TBC_L_MW_TBC_MASK (0xFFFFFFF0U) |
#define | IEE_PC_MW_TBC_L_MW_TBC_SHIFT (4U) |
#define | IEE_PC_MW_TBC_L_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_MASK) |
PC_SR_TLGTT - Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold | |
#define | IEE_PC_SR_TLGTT_SR_TLGTT_MASK (0xFFFFFFFFU) |
#define | IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT (0U) |
#define | IEE_PC_SR_TLGTT_SR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT)) & IEE_PC_SR_TLGTT_SR_TLGTT_MASK) |
PC_SW_TLGTT - Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold | |
#define | IEE_PC_SW_TLGTT_SW_TLGTT_MASK (0xFFFFFFFFU) |
#define | IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT (0U) |
#define | IEE_PC_SW_TLGTT_SW_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT)) & IEE_PC_SW_TLGTT_SW_TLGTT_MASK) |
PC_MR_TLGTT - Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold | |
#define | IEE_PC_MR_TLGTT_MR_TLGTT_MASK (0xFFFFFFFFU) |
#define | IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT (0U) |
#define | IEE_PC_MR_TLGTT_MR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT)) & IEE_PC_MR_TLGTT_MR_TLGTT_MASK) |
PC_MW_TLGTT - Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold | |
#define | IEE_PC_MW_TLGTT_MW_TGTT_MASK (0xFFFFFFFFU) |
#define | IEE_PC_MW_TLGTT_MW_TGTT_SHIFT (0U) |
#define | IEE_PC_MW_TLGTT_MW_TGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLGTT_MW_TGTT_SHIFT)) & IEE_PC_MW_TLGTT_MW_TGTT_MASK) |
PC_SR_TLAT_U - Performance Counter, Upper Slave Read Latency Count | |
#define | IEE_PC_SR_TLAT_U_SR_TLAT_MASK (0xFFFFU) |
#define | IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT (0U) |
#define | IEE_PC_SR_TLAT_U_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_U_SR_TLAT_MASK) |
PC_SR_TLAT_L - Performance Counter, Lower Slave Read Latency Count | |
#define | IEE_PC_SR_TLAT_L_SR_TLAT_MASK (0xFFFFFFFFU) |
#define | IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT (0U) |
#define | IEE_PC_SR_TLAT_L_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_L_SR_TLAT_MASK) |
PC_SW_TLAT_U - Performance Counter, Upper Slave Write Latency Count | |
#define | IEE_PC_SW_TLAT_U_SW_TLAT_MASK (0xFFFFU) |
#define | IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT (0U) |
#define | IEE_PC_SW_TLAT_U_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_U_SW_TLAT_MASK) |
PC_SW_TLAT_L - Performance Counter, Lower Slave Write Latency Count | |
#define | IEE_PC_SW_TLAT_L_SW_TLAT_MASK (0xFFFFFFFFU) |
#define | IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT (0U) |
#define | IEE_PC_SW_TLAT_L_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_L_SW_TLAT_MASK) |
PC_MR_TLAT_U - Performance Counter, Upper Master Read Latency Count | |
#define | IEE_PC_MR_TLAT_U_MR_TLAT_MASK (0xFFFFU) |
#define | IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT (0U) |
#define | IEE_PC_MR_TLAT_U_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_U_MR_TLAT_MASK) |
PC_MR_TLAT_L - Performance Counter, Lower Master Read Latency Count | |
#define | IEE_PC_MR_TLAT_L_MR_TLAT_MASK (0xFFFFFFFFU) |
#define | IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT (0U) |
#define | IEE_PC_MR_TLAT_L_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_L_MR_TLAT_MASK) |
PC_MW_TLAT_U - Performance Counter, Upper Master Write Latency Count | |
#define | IEE_PC_MW_TLAT_U_MW_TLAT_MASK (0xFFFFU) |
#define | IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT (0U) |
#define | IEE_PC_MW_TLAT_U_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_U_MW_TLAT_MASK) |
PC_MW_TLAT_L - Performance Counter, Lower Master Write Latency Count | |
#define | IEE_PC_MW_TLAT_L_MW_TLAT_MASK (0xFFFFFFFFU) |
#define | IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT (0U) |
#define | IEE_PC_MW_TLAT_L_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_L_MW_TLAT_MASK) |
PC_SR_TNRT_U - Performance Counter, Upper Slave Read Total Non-Responding Time | |
#define | IEE_PC_SR_TNRT_U_SR_TNRT_MASK (0xFFFFU) |
#define | IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT (0U) |
#define | IEE_PC_SR_TNRT_U_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_U_SR_TNRT_MASK) |
PC_SR_TNRT_L - Performance Counter, Lower Slave Read Total Non-Responding Time | |
#define | IEE_PC_SR_TNRT_L_SR_TNRT_MASK (0xFFFFFFFFU) |
#define | IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT (0U) |
#define | IEE_PC_SR_TNRT_L_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_L_SR_TNRT_MASK) |
PC_SW_TNRT_U - Performance Counter, Upper Slave Write Total Non-Responding Time | |
#define | IEE_PC_SW_TNRT_U_SW_TNRT_MASK (0xFFFFU) |
#define | IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT (0U) |
#define | IEE_PC_SW_TNRT_U_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_U_SW_TNRT_MASK) |
PC_SW_TNRT_L - Performance Counter, Lower Slave Write Total Non-Responding Time | |
#define | IEE_PC_SW_TNRT_L_SW_TNRT_MASK (0xFFFFFFFFU) |
#define | IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT (0U) |
#define | IEE_PC_SW_TNRT_L_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_L_SW_TNRT_MASK) |
VIDR1 - IEE Version ID Register 1 | |
#define | IEE_VIDR1_MIN_REV_MASK (0xFFU) |
#define | IEE_VIDR1_MIN_REV_SHIFT (0U) |
#define | IEE_VIDR1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MIN_REV_SHIFT)) & IEE_VIDR1_MIN_REV_MASK) |
#define | IEE_VIDR1_MAJ_REV_MASK (0xFF00U) |
#define | IEE_VIDR1_MAJ_REV_SHIFT (8U) |
#define | IEE_VIDR1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MAJ_REV_SHIFT)) & IEE_VIDR1_MAJ_REV_MASK) |
#define | IEE_VIDR1_IP_ID_MASK (0xFFFF0000U) |
#define | IEE_VIDR1_IP_ID_SHIFT (16U) |
#define | IEE_VIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_IP_ID_SHIFT)) & IEE_VIDR1_IP_ID_MASK) |
AESVID - IEE AES Version ID Register | |
#define | IEE_AESVID_AESRN_MASK (0xFU) |
#define | IEE_AESVID_AESRN_SHIFT (0U) |
#define | IEE_AESVID_AESRN(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESRN_SHIFT)) & IEE_AESVID_AESRN_MASK) |
#define | IEE_AESVID_AESVID_MASK (0xF0U) |
#define | IEE_AESVID_AESVID_SHIFT (4U) |
#define | IEE_AESVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESVID_SHIFT)) & IEE_AESVID_AESVID_MASK) |
REGATTR - IEE Region 0 Attribute Register...IEE Region 7 Attribute Register. | |
#define | IEE_REGATTR_KS_MASK (0x1U) |
#define | IEE_REGATTR_KS_SHIFT (0U) |
#define | IEE_REGATTR_KS(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK) |
#define | IEE_REGATTR_MD_MASK (0x70U) |
#define | IEE_REGATTR_MD_SHIFT (4U) |
#define | IEE_REGATTR_MD(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK) |
#define | IEE_REGATTR_BYP_MASK (0x80U) |
#define | IEE_REGATTR_BYP_SHIFT (7U) |
#define | IEE_REGATTR_BYP(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_BYP_SHIFT)) & IEE_REGATTR_BYP_MASK) |
REGPO - IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register | |
#define | IEE_REGPO_PGOFF_MASK (0xFFFFFFU) |
#define | IEE_REGPO_PGOFF_SHIFT (0U) |
#define | IEE_REGPO_PGOFF(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGPO_PGOFF_SHIFT)) & IEE_REGPO_PGOFF_MASK) |
REGKEY1 - IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register | |
#define | IEE_REGKEY1_KEY1_MASK (0xFFFFFFFFU) |
#define | IEE_REGKEY1_KEY1_SHIFT (0U) |
#define | IEE_REGKEY1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY1_KEY1_SHIFT)) & IEE_REGKEY1_KEY1_MASK) |
REGKEY2 - IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register | |
#define | IEE_REGKEY2_KEY2_MASK (0xFFFFFFFFU) |
#define | IEE_REGKEY2_KEY2_SHIFT (0U) |
#define | IEE_REGKEY2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY2_KEY2_SHIFT)) & IEE_REGKEY2_KEY2_MASK) |
AES_TST_DB - IEE AES Test Mode Data Buffer | |
#define | IEE_AES_TST_DB_AES_TST_DB0_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB0_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB0(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB0_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB0_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB1_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB1_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB1(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB1_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB1_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB2_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB2_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB2(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB2_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB2_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB3_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB3_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB3(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB3_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB3_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB4_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB4_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB4(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB4_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB4_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB5_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB5_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB5(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB5_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB5_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB6_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB6_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB6(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB6_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB6_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB7_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB7_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB7(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB7_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB7_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB8_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB8_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB8(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB8_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB8_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB9_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB9_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB9(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB9_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB9_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB10_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB10_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB10(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB10_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB10_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB11_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB11_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB11(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB11_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB11_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB12_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB12_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB12(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB12_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB12_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB13_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB13_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB13(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB13_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB13_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB14_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB14_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB14(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB14_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB14_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB15_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB15_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB15(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB15_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB15_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB16_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB16_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB16(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB16_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB16_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB17_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB17_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB17(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB17_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB17_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB18_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB18_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB18(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB18_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB18_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB19_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB19_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB19(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB19_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB19_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB20_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB20_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB20(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB20_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB20_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB21_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB21_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB21(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB21_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB21_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB22_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB22_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB22(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB22_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB22_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB23_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB23_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB23(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB23_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB23_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB24_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB24_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB24(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB24_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB24_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB25_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB25_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB25(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB25_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB25_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB26_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB26_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB26(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB26_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB26_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB27_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB27_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB27(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB27_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB27_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB28_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB28_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB28(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB28_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB28_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB29_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB29_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB29(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB29_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB29_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB30_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB30_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB30(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB30_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB30_MASK) |
#define | IEE_AES_TST_DB_AES_TST_DB31_MASK (0xFFFFFFFFU) |
#define | IEE_AES_TST_DB_AES_TST_DB31_SHIFT (0U) |
#define | IEE_AES_TST_DB_AES_TST_DB31(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB31_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB31_MASK) |
REGION0_TOP_ADDR - End address of IEE region (n) | |
#define | IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION0_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK) |
REGION0_BOT_ADDR - Start address of IEE region (n) | |
#define | IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION0_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK) |
REGION0_RDC_D0 - Region control of core domain 0 for region (n) | |
#define | IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK) |
#define | IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK) |
REGION0_RDC_D1 - Region control of core domain 1 for region (n) | |
#define | IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK) |
#define | IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK) |
REGION1_TOP_ADDR - End address of IEE region (n) | |
#define | IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION1_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK) |
REGION1_BOT_ADDR - Start address of IEE region (n) | |
#define | IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION1_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK) |
REGION1_RDC_D0 - Region control of core domain 0 for region (n) | |
#define | IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK) |
#define | IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK) |
REGION1_RDC_D1 - Region control of core domain 1 for region (n) | |
#define | IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK) |
#define | IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK) |
REGION2_TOP_ADDR - End address of IEE region (n) | |
#define | IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION2_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK) |
REGION2_BOT_ADDR - Start address of IEE region (n) | |
#define | IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION2_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK) |
REGION2_RDC_D0 - Region control of core domain 0 for region (n) | |
#define | IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK) |
#define | IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK) |
REGION2_RDC_D1 - Region control of core domain 1 for region (n) | |
#define | IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK) |
#define | IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK) |
REGION3_TOP_ADDR - End address of IEE region (n) | |
#define | IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION3_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK) |
REGION3_BOT_ADDR - Start address of IEE region (n) | |
#define | IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION3_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK) |
REGION3_RDC_D0 - Region control of core domain 0 for region (n) | |
#define | IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK) |
#define | IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK) |
REGION3_RDC_D1 - Region control of core domain 1 for region (n) | |
#define | IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK) |
#define | IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK) |
REGION4_TOP_ADDR - End address of IEE region (n) | |
#define | IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION4_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK) |
REGION4_BOT_ADDR - Start address of IEE region (n) | |
#define | IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION4_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK) |
REGION4_RDC_D0 - Region control of core domain 0 for region (n) | |
#define | IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK) |
#define | IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK) |
REGION4_RDC_D1 - Region control of core domain 1 for region (n) | |
#define | IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK) |
#define | IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK) |
REGION5_TOP_ADDR - End address of IEE region (n) | |
#define | IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION5_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK) |
REGION5_BOT_ADDR - Start address of IEE region (n) | |
#define | IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION5_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK) |
REGION5_RDC_D0 - Region control of core domain 0 for region (n) | |
#define | IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK) |
#define | IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK) |
REGION5_RDC_D1 - Region control of core domain 1 for region (n) | |
#define | IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK) |
#define | IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK) |
REGION6_TOP_ADDR - End address of IEE region (n) | |
#define | IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION6_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK) |
REGION6_BOT_ADDR - Start address of IEE region (n) | |
#define | IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION6_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK) |
REGION6_RDC_D0 - Region control of core domain 0 for region (n) | |
#define | IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK) |
#define | IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK) |
REGION6_RDC_D1 - Region control of core domain 1 for region (n) | |
#define | IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK) |
#define | IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK) |
REGION7_TOP_ADDR - End address of IEE region (n) | |
#define | IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION7_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK) |
REGION7_BOT_ADDR - Start address of IEE region (n) | |
#define | IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) |
#define | IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT (0U) |
#define | IEE_APC_REGION7_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK) |
REGION7_RDC_D0 - Region control of core domain 0 for region (n) | |
#define | IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK) |
#define | IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK) |
REGION7_RDC_D1 - Region control of core domain 1 for region (n) | |
#define | IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) |
#define | IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) |
#define | IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK) |
#define | IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK (0x2U) |
#define | IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT (1U) |
#define | IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK) |
SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register | |
#define | IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) |
#define | IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) |
#define | IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) |
#define | IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) |
#define | IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) |
SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register | |
#define | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) |
#define | IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) |
#define | IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) |
#define | IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x2U) |
#define | IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (1U) |
#define | IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) |
#define | IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK (0x2U) |
#define | IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT (1U) |
#define | IOMUXC_SW_PAD_CTL_PAD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK) |
#define | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x4U) |
#define | IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (2U) |
#define | IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) |
#define | IOMUXC_SW_PAD_CTL_PAD_PULL_MASK (0xCU) |
#define | IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT (2U) |
#define | IOMUXC_SW_PAD_CTL_PAD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK) |
#define | IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0x8U) |
#define | IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (3U) |
#define | IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) |
#define | IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x10U) |
#define | IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (4U) |
#define | IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) |
#define | IOMUXC_SW_PAD_CTL_PAD_DWP_MASK (0x30000000U) |
#define | IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT (28U) |
#define | IOMUXC_SW_PAD_CTL_PAD_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK) |
#define | IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK) |
SELECT_INPUT - FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register | |
#define | IOMUXC_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ |
#define | IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) |
#define | IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ |
GPR0 - GPR0 General Purpose Register | |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT (0U) |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK) |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK (0x38U) |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT (3U) |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK) |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK (0xC0U) |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT (6U) |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK) |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK (0x100U) |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT (8U) |
#define | IOMUXC_GPR_GPR0_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK) |
#define | IOMUXC_GPR_GPR0_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR0_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR0_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_SHIFT)) & IOMUXC_GPR_GPR0_DWP_MASK) |
#define | IOMUXC_GPR_GPR0_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR0_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR0_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK (0xFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR0_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK) |
GPR1 - GPR1 General Purpose Register | |
#define | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x3U) |
#define | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (0U) |
#define | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK) |
#define | IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100U) |
#define | IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (8U) |
#define | IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) |
#define | IOMUXC_GPR_GPR1_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR1_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR1_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_SHIFT)) & IOMUXC_GPR_GPR1_DWP_MASK) |
#define | IOMUXC_GPR_GPR1_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR1_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK (0xFFFFU) |
#define | IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR1_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK) |
GPR2 - GPR2 General Purpose Register | |
#define | IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK (0x3U) |
#define | IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT (0U) |
#define | IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK) |
#define | IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK (0x100U) |
#define | IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT (8U) |
#define | IOMUXC_GPR_GPR2_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK) |
#define | IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK (0x200U) |
#define | IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT (9U) |
#define | IOMUXC_GPR_GPR2_SAI4_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK) |
#define | IOMUXC_GPR_GPR2_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR2_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR2_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_SHIFT)) & IOMUXC_GPR_GPR2_DWP_MASK) |
#define | IOMUXC_GPR_GPR2_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR2_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR2_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR2_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK) |
GPR3 - GPR3 General Purpose Register | |
#define | IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK (0xFFU) |
#define | IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT (0U) |
#define | IOMUXC_GPR_GPR3_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK) |
#define | IOMUXC_GPR_GPR3_MQS_SW_RST_MASK (0x100U) |
#define | IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT (8U) |
#define | IOMUXC_GPR_GPR3_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR3_MQS_SW_RST_MASK) |
#define | IOMUXC_GPR_GPR3_MQS_EN_MASK (0x200U) |
#define | IOMUXC_GPR_GPR3_MQS_EN_SHIFT (9U) |
#define | IOMUXC_GPR_GPR3_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR3_MQS_EN_MASK) |
#define | IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK (0x400U) |
#define | IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT (10U) |
#define | IOMUXC_GPR_GPR3_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK) |
#define | IOMUXC_GPR_GPR3_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR3_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR3_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_SHIFT)) & IOMUXC_GPR_GPR3_DWP_MASK) |
#define | IOMUXC_GPR_GPR3_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR3_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR3_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR3_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK) |
GPR4 - GPR4 General Purpose Register | |
#define | IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK (0x1U) |
#define | IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT (0U) |
#define | IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK) |
#define | IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK (0x2U) |
#define | IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT (1U) |
#define | IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK) |
#define | IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK (0x4U) |
#define | IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT (2U) |
#define | IOMUXC_GPR_GPR4_ENET_TIME_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK) |
#define | IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK (0x8U) |
#define | IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT (3U) |
#define | IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK) |
#define | IOMUXC_GPR_GPR4_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR4_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR4_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_SHIFT)) & IOMUXC_GPR_GPR4_DWP_MASK) |
#define | IOMUXC_GPR_GPR4_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR4_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR4_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR4_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK) |
GPR5 - GPR5 General Purpose Register | |
#define | IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK (0x1U) |
#define | IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT (0U) |
#define | IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) |
#define | IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK (0x2U) |
#define | IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT (1U) |
#define | IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK) |
#define | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK (0x4U) |
#define | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT (2U) |
#define | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK) |
#define | IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK (0x8U) |
#define | IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT (3U) |
#define | IOMUXC_GPR_GPR5_ENET1G_TIME_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK) |
#define | IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK (0x10U) |
#define | IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT (4U) |
#define | IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK) |
#define | IOMUXC_GPR_GPR5_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR5_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR5_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_SHIFT)) & IOMUXC_GPR_GPR5_DWP_MASK) |
#define | IOMUXC_GPR_GPR5_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR5_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR5_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR5_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR5_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK) |
GPR7 - GPR7 General Purpose Register | |
#define | IOMUXC_GPR_GPR7_GINT_MASK (0x1U) |
#define | IOMUXC_GPR_GPR7_GINT_SHIFT (0U) |
#define | IOMUXC_GPR_GPR7_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GINT_SHIFT)) & IOMUXC_GPR_GPR7_GINT_MASK) |
#define | IOMUXC_GPR_GPR7_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR7_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR7_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_SHIFT)) & IOMUXC_GPR_GPR7_DWP_MASK) |
#define | IOMUXC_GPR_GPR7_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR7_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR7_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR7_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR7_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK) |
GPR8 - GPR8 General Purpose Register | |
#define | IOMUXC_GPR_GPR8_WDOG1_MASK_MASK (0x1U) |
#define | IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT (0U) |
#define | IOMUXC_GPR_GPR8_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR8_WDOG1_MASK_MASK) |
#define | IOMUXC_GPR_GPR8_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR8_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR8_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_SHIFT)) & IOMUXC_GPR_GPR8_DWP_MASK) |
#define | IOMUXC_GPR_GPR8_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR8_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR8_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR8_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR8_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK) |
GPR9 - GPR9 General Purpose Register | |
#define | IOMUXC_GPR_GPR9_WDOG2_MASK_MASK (0x1U) |
#define | IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT (0U) |
#define | IOMUXC_GPR_GPR9_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR9_WDOG2_MASK_MASK) |
#define | IOMUXC_GPR_GPR9_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR9_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR9_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_SHIFT)) & IOMUXC_GPR_GPR9_DWP_MASK) |
#define | IOMUXC_GPR_GPR9_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR9_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR9_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR9_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR9_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK) |
GPR10 - GPR10 General Purpose Register | |
#define | IOMUXC_GPR_GPR10_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR10_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR10_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_SHIFT)) & IOMUXC_GPR_GPR10_DWP_MASK) |
#define | IOMUXC_GPR_GPR10_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR10_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR10_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR10_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR10_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK) |
GPR11 - GPR11 General Purpose Register | |
#define | IOMUXC_GPR_GPR11_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR11_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR11_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_SHIFT)) & IOMUXC_GPR_GPR11_DWP_MASK) |
#define | IOMUXC_GPR_GPR11_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR11_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR11_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR11_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR11_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK) |
GPR12 - GPR12 General Purpose Register | |
#define | IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK (0x100U) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT (8U) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK (0x200U) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT (9U) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK (0x400U) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT (10U) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK (0x800U) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT (11U) |
#define | IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR12_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR12_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR12_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_SHIFT)) & IOMUXC_GPR_GPR12_DWP_MASK) |
#define | IOMUXC_GPR_GPR12_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR12_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR12_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR12_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR12_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK) |
GPR13 - GPR13 General Purpose Register | |
#define | IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK (0x100U) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT (8U) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK (0x200U) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT (9U) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK (0x400U) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT (10U) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK (0x800U) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT (11U) |
#define | IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR13_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR13_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR13_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_SHIFT)) & IOMUXC_GPR_GPR13_DWP_MASK) |
#define | IOMUXC_GPR_GPR13_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR13_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR13_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR13_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR13_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK) |
GPR14 - GPR14 General Purpose Register | |
#define | IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U) |
#define | IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR14_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR14_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR14_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_SHIFT)) & IOMUXC_GPR_GPR14_DWP_MASK) |
#define | IOMUXC_GPR_GPR14_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR14_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR14_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR14_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR14_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK) |
GPR15 - GPR15 General Purpose Register | |
#define | IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK (0x100U) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT (8U) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK (0x200U) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT (9U) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK (0x400U) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT (10U) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK (0x800U) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT (11U) |
#define | IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK) |
#define | IOMUXC_GPR_GPR15_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR15_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR15_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_SHIFT)) & IOMUXC_GPR_GPR15_DWP_MASK) |
#define | IOMUXC_GPR_GPR15_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR15_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR15_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR15_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR15_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK) |
GPR16 - GPR16 General Purpose Register | |
#define | IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U) |
#define | IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U) |
#define | IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) |
#define | IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK (0x8U) |
#define | IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT (3U) |
#define | IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK) |
#define | IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK (0x20U) |
#define | IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT (5U) |
#define | IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK) |
#define | IOMUXC_GPR_GPR16_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR16_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR16_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_SHIFT)) & IOMUXC_GPR_GPR16_DWP_MASK) |
#define | IOMUXC_GPR_GPR16_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR16_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR16_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR16_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR16_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK) |
GPR17 - GPR17 General Purpose Register | |
#define | IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK (0xFFFFU) |
#define | IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT (0U) |
#define | IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK) |
#define | IOMUXC_GPR_GPR17_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR17_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR17_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_SHIFT)) & IOMUXC_GPR_GPR17_DWP_MASK) |
#define | IOMUXC_GPR_GPR17_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR17_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR17_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR17_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR17_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK) |
GPR18 - GPR18 General Purpose Register | |
#define | IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK (0xFFFFU) |
#define | IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT (0U) |
#define | IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT)) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK) |
#define | IOMUXC_GPR_GPR18_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR18_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR18_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_SHIFT)) & IOMUXC_GPR_GPR18_DWP_MASK) |
#define | IOMUXC_GPR_GPR18_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR18_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR18_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR18_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR18_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK) |
GPR20 - GPR20 General Purpose Register | |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK (0x1U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT (0U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK (0x2U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT (1U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK (0x4U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT (2U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK (0x8U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT (3U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK (0x10U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT (4U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK (0x20U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT (5U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK (0x40U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT (6U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK (0x80U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT (7U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK (0x100U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT (8U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK (0x200U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT (9U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK (0x400U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT (10U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK (0x800U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT (11U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT (12U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT (13U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT (14U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK (0x8000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT (15U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK (0x10000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT (16U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK (0x20000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT (17U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK (0x40000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT (18U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK (0x80000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT (19U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK (0x100000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT (20U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK (0x200000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT (21U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK (0x400000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT (22U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK (0x800000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT (23U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK (0x1000000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT (24U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK (0x2000000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT (25U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK (0x4000000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT (26U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK (0x8000000U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT (27U) |
#define | IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK) |
#define | IOMUXC_GPR_GPR20_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR20_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR20_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_SHIFT)) & IOMUXC_GPR_GPR20_DWP_MASK) |
#define | IOMUXC_GPR_GPR20_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR20_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR20_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR20_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR20_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK) |
GPR21 - GPR21 General Purpose Register | |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK (0x1U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT (0U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK (0x2U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT (1U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK (0x4U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT (2U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK (0x8U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT (3U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK (0x10U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT (4U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK (0x20U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT (5U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK (0x40U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT (6U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK (0x80U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT (7U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK (0x100U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT (8U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK (0x200U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT (9U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK (0x400U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT (10U) |
#define | IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK) |
#define | IOMUXC_GPR_GPR21_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR21_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR21_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_SHIFT)) & IOMUXC_GPR_GPR21_DWP_MASK) |
#define | IOMUXC_GPR_GPR21_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR21_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR21_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR21_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR21_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK) |
GPR22 - GPR22 General Purpose Register | |
#define | IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK (0x1U) |
#define | IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT (0U) |
#define | IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK) |
#define | IOMUXC_GPR_GPR22_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR22_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR22_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_SHIFT)) & IOMUXC_GPR_GPR22_DWP_MASK) |
#define | IOMUXC_GPR_GPR22_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR22_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR22_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR22_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR22_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK) |
GPR23 - GPR23 General Purpose Register | |
#define | IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK (0x1U) |
#define | IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT (0U) |
#define | IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK) |
#define | IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK (0x2U) |
#define | IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT (1U) |
#define | IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK) |
#define | IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK (0x4U) |
#define | IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT (2U) |
#define | IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK) |
#define | IOMUXC_GPR_GPR23_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR23_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR23_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_SHIFT)) & IOMUXC_GPR_GPR23_DWP_MASK) |
#define | IOMUXC_GPR_GPR23_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR23_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR23_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR23_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR23_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK) |
GPR24 - GPR24 General Purpose Register | |
#define | IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK (0x1U) |
#define | IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT (0U) |
#define | IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT)) & IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK) |
#define | IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK (0x2U) |
#define | IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT (1U) |
#define | IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK) |
#define | IOMUXC_GPR_GPR24_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR24_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR24_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_SHIFT)) & IOMUXC_GPR_GPR24_DWP_MASK) |
#define | IOMUXC_GPR_GPR24_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR24_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR24_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR24_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR24_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK) |
GPR25 - GPR25 General Purpose Register | |
#define | IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK (0x1U) |
#define | IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT (0U) |
#define | IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT)) & IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK) |
#define | IOMUXC_GPR_GPR25_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR25_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR25_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_SHIFT)) & IOMUXC_GPR_GPR25_DWP_MASK) |
#define | IOMUXC_GPR_GPR25_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR25_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR25_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR25_APC_VALID(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK) |
#define | IOMUXC_LPSR_GPR_GPR25_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR25_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK) |
GPR26 - GPR26 General Purpose Register | |
#define | IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK (0x1U) |
#define | IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT (0U) |
#define | IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT)) & IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK) |
#define | IOMUXC_GPR_GPR26_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR26_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR26_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_SHIFT)) & IOMUXC_GPR_GPR26_DWP_MASK) |
#define | IOMUXC_GPR_GPR26_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR26_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR26_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK (0x1FFFFFFU) |
#define | IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK (0xE000000U) |
#define | IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR26_FIELD_0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK) |
GPR27 - GPR27 General Purpose Register | |
#define | IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK (0x1U) |
#define | IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT (0U) |
#define | IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT)) & IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK) |
#define | IOMUXC_GPR_GPR27_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR27_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR27_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_SHIFT)) & IOMUXC_GPR_GPR27_DWP_MASK) |
#define | IOMUXC_GPR_GPR27_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR27_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR27_DWP_LOCK_MASK) |
GPR28 - GPR28 General Purpose Register | |
#define | IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK (0x1U) |
#define | IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT (0U) |
#define | IOMUXC_GPR_GPR28_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK) |
#define | IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK (0x2U) |
#define | IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT (1U) |
#define | IOMUXC_GPR_GPR28_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK) |
#define | IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK (0x20U) |
#define | IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT (5U) |
#define | IOMUXC_GPR_GPR28_CACHE_ENET1G(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK) |
#define | IOMUXC_GPR_GPR28_CACHE_ENET_MASK (0x80U) |
#define | IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT (7U) |
#define | IOMUXC_GPR_GPR28_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET_MASK) |
#define | IOMUXC_GPR_GPR28_CACHE_USB_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR28_CACHE_USB_SHIFT (13U) |
#define | IOMUXC_GPR_GPR28_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_USB_MASK) |
#define | IOMUXC_GPR_GPR28_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR28_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR28_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_SHIFT)) & IOMUXC_GPR_GPR28_DWP_MASK) |
#define | IOMUXC_GPR_GPR28_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR28_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR28_DWP_LOCK_MASK) |
GPR29 - GPR29 General Purpose Register | |
#define | IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK) |
#define | IOMUXC_GPR_GPR29_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR29_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR29_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_SHIFT)) & IOMUXC_GPR_GPR29_DWP_MASK) |
#define | IOMUXC_GPR_GPR29_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR29_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR29_DWP_LOCK_MASK) |
GPR30 - GPR30 General Purpose Register | |
#define | IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK) |
#define | IOMUXC_GPR_GPR30_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR30_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR30_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_SHIFT)) & IOMUXC_GPR_GPR30_DWP_MASK) |
#define | IOMUXC_GPR_GPR30_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR30_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR30_DWP_LOCK_MASK) |
GPR31 - GPR31 General Purpose Register | |
#define | IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK (0x1U) |
#define | IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT (0U) |
#define | IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK) |
#define | IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK (0x4U) |
#define | IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT (2U) |
#define | IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT)) & IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK) |
#define | IOMUXC_GPR_GPR31_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR31_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR31_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_SHIFT)) & IOMUXC_GPR_GPR31_DWP_MASK) |
#define | IOMUXC_GPR_GPR31_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR31_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR31_DWP_LOCK_MASK) |
GPR32 - GPR32 General Purpose Register | |
#define | IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK (0x1U) |
#define | IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT (0U) |
#define | IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK) |
#define | IOMUXC_GPR_GPR32_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR32_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR32_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_SHIFT)) & IOMUXC_GPR_GPR32_DWP_MASK) |
#define | IOMUXC_GPR_GPR32_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR32_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR32_DWP_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR32_GPR_MASK (0xFFFEU) |
#define | IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR32_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK) |
#define | IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR32_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK) |
GPR33 - GPR33 General Purpose Register | |
#define | IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK (0x1U) |
#define | IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT (0U) |
#define | IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK) |
#define | IOMUXC_GPR_GPR33_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR33_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR33_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_SHIFT)) & IOMUXC_GPR_GPR33_DWP_MASK) |
#define | IOMUXC_GPR_GPR33_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR33_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR33_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK (0x2U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK (0x4U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT (2U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK (0x10000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK (0x20000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT (17U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK (0x40000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT (18U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK (0x80000U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT (19U) |
#define | IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK (0x100000U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT (20U) |
#define | IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK) |
GPR34 - GPR34 General Purpose Register | |
#define | IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK (0x1U) |
#define | IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT (0U) |
#define | IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK) |
#define | IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK (0x2U) |
#define | IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT (1U) |
#define | IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK) |
#define | IOMUXC_GPR_GPR34_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR34_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR34_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_SHIFT)) & IOMUXC_GPR_GPR34_DWP_MASK) |
#define | IOMUXC_GPR_GPR34_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR34_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR34_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR34_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_LOCK_MASK (0x1U) |
#define | IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR34_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK (0x2U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK (0xCU) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT (2U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK (0x80U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT (7U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK (0xFF00U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT (8U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK (0x30000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK (0xC0000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT (18U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK (0x800000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT (23U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK (0xF000000U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT (24U) |
#define | IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK) |
GPR35 - GPR35 General Purpose Register | |
#define | IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK (0x1U) |
#define | IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT (0U) |
#define | IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK) |
#define | IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK (0x2U) |
#define | IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT (1U) |
#define | IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK) |
#define | IOMUXC_GPR_GPR35_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR35_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR35_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_SHIFT)) & IOMUXC_GPR_GPR35_DWP_MASK) |
#define | IOMUXC_GPR_GPR35_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR35_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR35_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR35_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_LOCK_MASK (0x1U) |
#define | IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR35_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK (0x8U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT (3U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK (0xFF0U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT (4U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK (0x8000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT (15U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK (0xFFF0000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT (16U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK (0x30000000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT (28U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT (30U) |
#define | IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK) |
GPR36 - GPR36 General Purpose Register | |
#define | IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK (0x1U) |
#define | IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT (0U) |
#define | IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK) |
#define | IOMUXC_GPR_GPR36_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR36_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR36_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_SHIFT)) & IOMUXC_GPR_GPR36_DWP_MASK) |
#define | IOMUXC_GPR_GPR36_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR36_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR36_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR36_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK (0x800000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT (23U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK (0x4000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT (26U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK (0x8000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT (27U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK (0x10000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT (28U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK (0x20000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT (29U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK (0x40000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT (30U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK (0x80000000U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT (31U) |
#define | IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK) |
GPR37 - GPR37 General Purpose Register | |
#define | IOMUXC_GPR_GPR37_NIDEN_MASK (0x1U) |
#define | IOMUXC_GPR_GPR37_NIDEN_SHIFT (0U) |
#define | IOMUXC_GPR_GPR37_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_NIDEN_SHIFT)) & IOMUXC_GPR_GPR37_NIDEN_MASK) |
#define | IOMUXC_GPR_GPR37_DBG_EN_MASK (0x2U) |
#define | IOMUXC_GPR_GPR37_DBG_EN_SHIFT (1U) |
#define | IOMUXC_GPR_GPR37_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR37_DBG_EN_MASK) |
#define | IOMUXC_GPR_GPR37_EXC_MON_MASK (0x8U) |
#define | IOMUXC_GPR_GPR37_EXC_MON_SHIFT (3U) |
#define | IOMUXC_GPR_GPR37_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR37_EXC_MON_MASK) |
#define | IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK (0x20U) |
#define | IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT (5U) |
#define | IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK) |
#define | IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK (0x40U) |
#define | IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT (6U) |
#define | IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK) |
#define | IOMUXC_GPR_GPR37_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR37_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR37_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_SHIFT)) & IOMUXC_GPR_GPR37_DWP_MASK) |
#define | IOMUXC_GPR_GPR37_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR37_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR37_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR37_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR37_LOCK_MASK (0x1U) |
#define | IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR37_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK (0x7FEU) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT (1U) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK (0x1FF800U) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT (11U) |
#define | IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK) |
GPR38 - GPR38 General Purpose Register | |
#define | IOMUXC_GPR_GPR38_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR38_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR38_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_SHIFT)) & IOMUXC_GPR_GPR38_DWP_MASK) |
#define | IOMUXC_GPR_GPR38_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR38_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR38_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR38_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK) |
GPR39 - GPR39 General Purpose Register | |
#define | IOMUXC_GPR_GPR39_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR39_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR39_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_SHIFT)) & IOMUXC_GPR_GPR39_DWP_MASK) |
#define | IOMUXC_GPR_GPR39_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR39_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR39_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR39_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK) |
GPR40 - GPR40 General Purpose Register | |
#define | IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK (0xFFFFU) |
#define | IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT (0U) |
#define | IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK) |
#define | IOMUXC_GPR_GPR40_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR40_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR40_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_SHIFT)) & IOMUXC_GPR_GPR40_DWP_MASK) |
#define | IOMUXC_GPR_GPR40_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR40_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR40_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK (0x20000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT (17U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK (0x40000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT (18U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK (0x80000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT (19U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK (0x100000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT (20U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK (0x200000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT (21U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK (0x400000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT (22U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK (0x800000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT (23U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK (0x2000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT (25U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK (0x4000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT (26U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK (0x8000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT (27U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK (0x10000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT (28U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK (0x20000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT (29U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK (0x40000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT (30U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK (0x80000000U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT (31U) |
#define | IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK) |
GPR41 - GPR41 General Purpose Register | |
#define | IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK (0xFFFFU) |
#define | IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT (0U) |
#define | IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK) |
#define | IOMUXC_GPR_GPR41_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR41_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR41_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_SHIFT)) & IOMUXC_GPR_GPR41_DWP_MASK) |
#define | IOMUXC_GPR_GPR41_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR41_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR41_DWP_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK (0x2U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT (1U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK (0x4U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT (2U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK (0x8U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK (0x20U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT (5U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK (0x40U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT (6U) |
#define | IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK (0x80U) |
#define | IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT (7U) |
#define | IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK (0x100U) |
#define | IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT (8U) |
#define | IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK (0x200U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT (9U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK (0x400U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT (10U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK (0x800U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT (11U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK (0x1000U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT (12U) |
#define | IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT (13U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK (0x4000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT (14U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT (15U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK (0x10000U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK) |
#define | IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK (0x1000000U) |
#define | IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT (24U) |
#define | IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK) |
GPR42 - GPR42 General Purpose Register | |
#define | IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK (0xFFFFU) |
#define | IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT (0U) |
#define | IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK) |
#define | IOMUXC_GPR_GPR42_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR42_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR42_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_SHIFT)) & IOMUXC_GPR_GPR42_DWP_MASK) |
#define | IOMUXC_GPR_GPR42_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR42_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR42_DWP_LOCK_MASK) |
GPR43 - GPR43 General Purpose Register | |
#define | IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK (0xFFFFU) |
#define | IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT (0U) |
#define | IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK) |
#define | IOMUXC_GPR_GPR43_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR43_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR43_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_SHIFT)) & IOMUXC_GPR_GPR43_DWP_MASK) |
#define | IOMUXC_GPR_GPR43_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR43_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR43_DWP_LOCK_MASK) |
GPR44 - GPR44 General Purpose Register | |
#define | IOMUXC_GPR_GPR44_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR44_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR44_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_SHIFT)) & IOMUXC_GPR_GPR44_DWP_MASK) |
#define | IOMUXC_GPR_GPR44_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR44_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR44_DWP_LOCK_MASK) |
GPR45 - GPR45 General Purpose Register | |
#define | IOMUXC_GPR_GPR45_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR45_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR45_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_SHIFT)) & IOMUXC_GPR_GPR45_DWP_MASK) |
#define | IOMUXC_GPR_GPR45_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR45_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR45_DWP_LOCK_MASK) |
GPR46 - GPR46 General Purpose Register | |
#define | IOMUXC_GPR_GPR46_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR46_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR46_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_SHIFT)) & IOMUXC_GPR_GPR46_DWP_MASK) |
#define | IOMUXC_GPR_GPR46_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR46_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR46_DWP_LOCK_MASK) |
GPR47 - GPR47 General Purpose Register | |
#define | IOMUXC_GPR_GPR47_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR47_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR47_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_SHIFT)) & IOMUXC_GPR_GPR47_DWP_MASK) |
#define | IOMUXC_GPR_GPR47_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR47_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR47_DWP_LOCK_MASK) |
GPR48 - GPR48 General Purpose Register | |
#define | IOMUXC_GPR_GPR48_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR48_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR48_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_SHIFT)) & IOMUXC_GPR_GPR48_DWP_MASK) |
#define | IOMUXC_GPR_GPR48_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR48_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR48_DWP_LOCK_MASK) |
GPR49 - GPR49 General Purpose Register | |
#define | IOMUXC_GPR_GPR49_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR49_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR49_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_SHIFT)) & IOMUXC_GPR_GPR49_DWP_MASK) |
#define | IOMUXC_GPR_GPR49_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR49_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR49_DWP_LOCK_MASK) |
GPR50 - GPR50 General Purpose Register | |
#define | IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK (0x1FU) |
#define | IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT (0U) |
#define | IOMUXC_GPR_GPR50_CAAM_IPS_MGR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT)) & IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK) |
#define | IOMUXC_GPR_GPR50_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR50_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR50_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_SHIFT)) & IOMUXC_GPR_GPR50_DWP_MASK) |
#define | IOMUXC_GPR_GPR50_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR50_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR50_DWP_LOCK_MASK) |
GPR51 - GPR51 General Purpose Register | |
#define | IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK (0x1U) |
#define | IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT (0U) |
#define | IOMUXC_GPR_GPR51_M7_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT)) & IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK) |
#define | IOMUXC_GPR_GPR51_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR51_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR51_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_SHIFT)) & IOMUXC_GPR_GPR51_DWP_MASK) |
#define | IOMUXC_GPR_GPR51_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR51_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR51_DWP_LOCK_MASK) |
GPR52 - GPR52 General Purpose Register | |
#define | IOMUXC_GPR_GPR52_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR52_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR52_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_SHIFT)) & IOMUXC_GPR_GPR52_DWP_MASK) |
#define | IOMUXC_GPR_GPR52_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR52_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR52_DWP_LOCK_MASK) |
GPR53 - GPR53 General Purpose Register | |
#define | IOMUXC_GPR_GPR53_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR53_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR53_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_SHIFT)) & IOMUXC_GPR_GPR53_DWP_MASK) |
#define | IOMUXC_GPR_GPR53_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR53_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR53_DWP_LOCK_MASK) |
GPR54 - GPR54 General Purpose Register | |
#define | IOMUXC_GPR_GPR54_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR54_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR54_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_SHIFT)) & IOMUXC_GPR_GPR54_DWP_MASK) |
#define | IOMUXC_GPR_GPR54_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR54_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR54_DWP_LOCK_MASK) |
GPR55 - GPR55 General Purpose Register | |
#define | IOMUXC_GPR_GPR55_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR55_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR55_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_SHIFT)) & IOMUXC_GPR_GPR55_DWP_MASK) |
#define | IOMUXC_GPR_GPR55_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR55_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR55_DWP_LOCK_MASK) |
GPR59 - GPR59 General Purpose Register | |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK (0x1U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT (0U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK (0x2U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT (1U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK (0x4U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT (2U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK (0x8U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT (3U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK (0x10U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT (4U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK (0x20U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT (5U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK (0xC0U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT (6U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK (0x300U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT (8U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK (0xC00U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT (10U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK (0x3F000U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT (12U) |
#define | IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK) |
#define | IOMUXC_GPR_GPR59_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR59_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR59_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_SHIFT)) & IOMUXC_GPR_GPR59_DWP_MASK) |
#define | IOMUXC_GPR_GPR59_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR59_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR59_DWP_LOCK_MASK) |
GPR62 - GPR62 General Purpose Register | |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK (0x7U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT (0U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK (0x38U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT (3U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK (0x1C0U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT (6U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK (0x600U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT (9U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK (0x3800U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT (11U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK (0x10000U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT (16U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK (0x20000U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT (17U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK (0x40000U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT (18U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK (0x80000U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT (19U) |
#define | IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK) |
#define | IOMUXC_GPR_GPR62_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR62_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR62_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_SHIFT)) & IOMUXC_GPR_GPR62_DWP_MASK) |
#define | IOMUXC_GPR_GPR62_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR62_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR62_DWP_LOCK_MASK) |
GPR63 - GPR63 General Purpose Register | |
#define | IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK (0x7U) |
#define | IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK) |
GPR64 - GPR64 General Purpose Register | |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK (0x2U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT (1U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK (0x4U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT (2U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK (0x8U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT (3U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK (0xF0U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT (4U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK (0xF00U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT (8U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT (12U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT (13U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT (14U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK (0x100000U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT (20U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK (0x1E00000U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT (21U) |
#define | IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK) |
#define | IOMUXC_GPR_GPR64_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR64_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR64_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_SHIFT)) & IOMUXC_GPR_GPR64_DWP_MASK) |
#define | IOMUXC_GPR_GPR64_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR64_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR64_DWP_LOCK_MASK) |
GPR65 - GPR65 General Purpose Register | |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK (0x2U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT (1U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK (0x4U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT (2U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK (0x8U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT (3U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK (0xF0U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT (4U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK (0xF00U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT (8U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT (12U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT (13U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT (14U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK (0x100000U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT (20U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK (0x1E00000U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT (21U) |
#define | IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK) |
#define | IOMUXC_GPR_GPR65_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR65_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR65_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_SHIFT)) & IOMUXC_GPR_GPR65_DWP_MASK) |
#define | IOMUXC_GPR_GPR65_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR65_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR65_DWP_LOCK_MASK) |
GPR66 - GPR66 General Purpose Register | |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK (0x2U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT (1U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK (0x4U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT (2U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK (0x8U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT (3U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK (0xF0U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT (4U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK (0xF00U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT (8U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT (12U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT (13U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT (14U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK (0x100000U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT (20U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK (0x1E00000U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT (21U) |
#define | IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK) |
#define | IOMUXC_GPR_GPR66_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR66_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR66_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_SHIFT)) & IOMUXC_GPR_GPR66_DWP_MASK) |
#define | IOMUXC_GPR_GPR66_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR66_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR66_DWP_LOCK_MASK) |
GPR67 - GPR67 General Purpose Register | |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK (0x2U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT (1U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK (0x4U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT (2U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK (0x8U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT (3U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK (0xF0U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT (4U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK (0xF00U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT (8U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT (12U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT (13U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT (14U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK (0x100000U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT (20U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK (0x1E00000U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT (21U) |
#define | IOMUXC_GPR_GPR67_GPIO_SD1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK) |
#define | IOMUXC_GPR_GPR67_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR67_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR67_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_SHIFT)) & IOMUXC_GPR_GPR67_DWP_MASK) |
#define | IOMUXC_GPR_GPR67_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR67_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR67_DWP_LOCK_MASK) |
GPR68 - GPR68 General Purpose Register | |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK (0x2U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT (1U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK (0x4U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT (2U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK (0x8U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT (3U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK (0xF0U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT (4U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK (0xF00U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT (8U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT (12U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT (13U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT (14U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK (0x100000U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT (20U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK (0x1E00000U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT (21U) |
#define | IOMUXC_GPR_GPR68_GPIO_SD2_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK) |
#define | IOMUXC_GPR_GPR68_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR68_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR68_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_SHIFT)) & IOMUXC_GPR_GPR68_DWP_MASK) |
#define | IOMUXC_GPR_GPR68_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR68_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR68_DWP_LOCK_MASK) |
GPR69 - GPR69 General Purpose Register | |
#define | IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK (0x2U) |
#define | IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT (1U) |
#define | IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK) |
#define | IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK (0x4U) |
#define | IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT (2U) |
#define | IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK) |
#define | IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK (0x10U) |
#define | IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT (4U) |
#define | IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK) |
#define | IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK (0x20U) |
#define | IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT (5U) |
#define | IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK) |
#define | IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK (0x80U) |
#define | IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT (7U) |
#define | IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK) |
#define | IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK (0x100U) |
#define | IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT (8U) |
#define | IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK (0x200U) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT (9U) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK (0x400U) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT (10U) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK (0x800U) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT (11U) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT (12U) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT (13U) |
#define | IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK) |
#define | IOMUXC_GPR_GPR69_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR69_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR69_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_SHIFT)) & IOMUXC_GPR_GPR69_DWP_MASK) |
#define | IOMUXC_GPR_GPR69_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR69_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR69_DWP_LOCK_MASK) |
GPR70 - GPR70 General Purpose Register | |
#define | IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR70_ADC1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_GPR_GPR70_ADC1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_GPR_GPR70_ADC2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_GPR_GPR70_ADC2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_GPR_GPR70_CAAM_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_GPR_GPR70_CAAM_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK (0x100U) |
#define | IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT (8U) |
#define | IOMUXC_GPR_GPR70_CAN1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK (0x200U) |
#define | IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT (9U) |
#define | IOMUXC_GPR_GPR70_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK (0x400U) |
#define | IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT (10U) |
#define | IOMUXC_GPR_GPR70_CAN2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK (0x800U) |
#define | IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT (11U) |
#define | IOMUXC_GPR_GPR70_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_GPR_GPR70_CAN3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_GPR_GPR70_CAN3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK (0x8000U) |
#define | IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT (15U) |
#define | IOMUXC_GPR_GPR70_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK (0x20000U) |
#define | IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT (17U) |
#define | IOMUXC_GPR_GPR70_ENET_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK (0x40000U) |
#define | IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT (18U) |
#define | IOMUXC_GPR_GPR70_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK (0x80000U) |
#define | IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT (19U) |
#define | IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK (0x100000U) |
#define | IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT (20U) |
#define | IOMUXC_GPR_GPR70_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK (0x400000U) |
#define | IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT (22U) |
#define | IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK (0x800000U) |
#define | IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT (23U) |
#define | IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK (0x1000000U) |
#define | IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT (24U) |
#define | IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK (0x2000000U) |
#define | IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT (25U) |
#define | IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK (0x4000000U) |
#define | IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT (26U) |
#define | IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR70_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR70_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR70_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_SHIFT)) & IOMUXC_GPR_GPR70_DWP_MASK) |
#define | IOMUXC_GPR_GPR70_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR70_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR70_DWP_LOCK_MASK) |
GPR71 - GPR71 General Purpose Register | |
#define | IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR71_GPT1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK (0x2U) |
#define | IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT (1U) |
#define | IOMUXC_GPR_GPR71_GPT2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK (0x4U) |
#define | IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT (2U) |
#define | IOMUXC_GPR_GPR71_GPT3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_GPR_GPR71_GPT4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK (0x10U) |
#define | IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT (4U) |
#define | IOMUXC_GPR_GPR71_GPT5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK (0x20U) |
#define | IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT (5U) |
#define | IOMUXC_GPR_GPR71_GPT6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR71_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR71_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR71_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_SHIFT)) & IOMUXC_GPR_GPR71_DWP_MASK) |
#define | IOMUXC_GPR_GPR71_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR71_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR71_DWP_LOCK_MASK) |
GPR72 - GPR72 General Purpose Register | |
#define | IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_GPR_GPR72_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_GPR_GPR72_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_GPR_GPR72_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_GPR_GPR72_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR72_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR72_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR72_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_SHIFT)) & IOMUXC_GPR_GPR72_DWP_MASK) |
#define | IOMUXC_GPR_GPR72_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR72_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR72_DWP_LOCK_MASK) |
GPR73 - GPR73 General Purpose Register | |
#define | IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK (0x1U) |
#define | IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT (0U) |
#define | IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_GPR_GPR73_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK (0x4U) |
#define | IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT (2U) |
#define | IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK (0x8U) |
#define | IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT (3U) |
#define | IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK (0x10U) |
#define | IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT (4U) |
#define | IOMUXC_GPR_GPR73_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK (0x20U) |
#define | IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT (5U) |
#define | IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_GPR_GPR73_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK (0x100U) |
#define | IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT (8U) |
#define | IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_GPR_GPR73_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK (0x800U) |
#define | IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT (11U) |
#define | IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT (12U) |
#define | IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_GPR_GPR73_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT (14U) |
#define | IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK (0x8000U) |
#define | IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT (15U) |
#define | IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK (0x10000U) |
#define | IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT (16U) |
#define | IOMUXC_GPR_GPR73_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK (0x20000U) |
#define | IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT (17U) |
#define | IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK (0x40000U) |
#define | IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT (18U) |
#define | IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK (0x80000U) |
#define | IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT (19U) |
#define | IOMUXC_GPR_GPR73_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK (0x100000U) |
#define | IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT (20U) |
#define | IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK (0x200000U) |
#define | IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT (21U) |
#define | IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK (0x400000U) |
#define | IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT (22U) |
#define | IOMUXC_GPR_GPR73_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK (0x800000U) |
#define | IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT (23U) |
#define | IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK (0x1000000U) |
#define | IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT (24U) |
#define | IOMUXC_GPR_GPR73_MIC_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK (0x2000000U) |
#define | IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT (25U) |
#define | IOMUXC_GPR_GPR73_MIC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK (0x4000000U) |
#define | IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT (26U) |
#define | IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK) |
#define | IOMUXC_GPR_GPR73_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR73_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR73_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_SHIFT)) & IOMUXC_GPR_GPR73_DWP_MASK) |
#define | IOMUXC_GPR_GPR73_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR73_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR73_DWP_LOCK_MASK) |
GPR74 - GPR74 General Purpose Register | |
#define | IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK (0x2U) |
#define | IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT (1U) |
#define | IOMUXC_GPR_GPR74_PIT1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK (0x4U) |
#define | IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT (2U) |
#define | IOMUXC_GPR_GPR74_PIT2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK (0x8U) |
#define | IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT (3U) |
#define | IOMUXC_GPR_GPR74_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK (0x10U) |
#define | IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT (4U) |
#define | IOMUXC_GPR_GPR74_SIM1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK (0x20U) |
#define | IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT (5U) |
#define | IOMUXC_GPR_GPR74_SIM2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK (0x40U) |
#define | IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT (6U) |
#define | IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK (0x80U) |
#define | IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT (7U) |
#define | IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK (0x100U) |
#define | IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT (8U) |
#define | IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK (0x200U) |
#define | IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT (9U) |
#define | IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK) |
#define | IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK (0x400U) |
#define | IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT (10U) |
#define | IOMUXC_GPR_GPR74_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK (0x800U) |
#define | IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT (11U) |
#define | IOMUXC_GPR_GPR74_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT (12U) |
#define | IOMUXC_GPR_GPR74_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT (13U) |
#define | IOMUXC_GPR_GPR74_SAI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK) |
#define | IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT (14U) |
#define | IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK) |
#define | IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK (0x8000U) |
#define | IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT (15U) |
#define | IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK) |
#define | IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U) |
#define | IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT (16U) |
#define | IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK) |
#define | IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK (0x20000U) |
#define | IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT (17U) |
#define | IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK) |
#define | IOMUXC_GPR_GPR74_DWP_MASK (0x30000000U) |
#define | IOMUXC_GPR_GPR74_DWP_SHIFT (28U) |
#define | IOMUXC_GPR_GPR74_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_SHIFT)) & IOMUXC_GPR_GPR74_DWP_MASK) |
#define | IOMUXC_GPR_GPR74_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR74_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR74_DWP_LOCK_MASK) |
GPR75 - GPR75 General Purpose Register | |
#define | IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK (0x1U) |
#define | IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT (0U) |
#define | IOMUXC_GPR_GPR75_ADC1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK (0x2U) |
#define | IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT (1U) |
#define | IOMUXC_GPR_GPR75_ADC2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK (0x4U) |
#define | IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT (2U) |
#define | IOMUXC_GPR_GPR75_CAAM_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK (0x8U) |
#define | IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT (3U) |
#define | IOMUXC_GPR_GPR75_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK (0x10U) |
#define | IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT (4U) |
#define | IOMUXC_GPR_GPR75_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK (0x20U) |
#define | IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT (5U) |
#define | IOMUXC_GPR_GPR75_CAN3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK (0x40U) |
#define | IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT (6U) |
#define | IOMUXC_GPR_GPR75_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK (0x80U) |
#define | IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT (7U) |
#define | IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK (0x100U) |
#define | IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT (8U) |
#define | IOMUXC_GPR_GPR75_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK (0x200U) |
#define | IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT (9U) |
#define | IOMUXC_GPR_GPR75_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK (0x400U) |
#define | IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT (10U) |
#define | IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK (0x800U) |
#define | IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT (11U) |
#define | IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT (12U) |
#define | IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT (13U) |
#define | IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT (14U) |
#define | IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK (0x8000U) |
#define | IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT (15U) |
#define | IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK (0x10000U) |
#define | IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT (16U) |
#define | IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK (0x20000U) |
#define | IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT (17U) |
#define | IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK (0x40000U) |
#define | IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT (18U) |
#define | IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK (0x80000U) |
#define | IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT (19U) |
#define | IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK (0x100000U) |
#define | IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT (20U) |
#define | IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK (0x200000U) |
#define | IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT (21U) |
#define | IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK (0x400000U) |
#define | IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT (22U) |
#define | IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK (0x800000U) |
#define | IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT (23U) |
#define | IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK (0x1000000U) |
#define | IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT (24U) |
#define | IOMUXC_GPR_GPR75_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK (0x2000000U) |
#define | IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT (25U) |
#define | IOMUXC_GPR_GPR75_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK (0x4000000U) |
#define | IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT (26U) |
#define | IOMUXC_GPR_GPR75_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK (0x8000000U) |
#define | IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT (27U) |
#define | IOMUXC_GPR_GPR75_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK (0x10000000U) |
#define | IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT (28U) |
#define | IOMUXC_GPR_GPR75_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK (0x20000000U) |
#define | IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT (29U) |
#define | IOMUXC_GPR_GPR75_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK (0x40000000U) |
#define | IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT (30U) |
#define | IOMUXC_GPR_GPR75_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK (0x80000000U) |
#define | IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT (31U) |
#define | IOMUXC_GPR_GPR75_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK) |
GPR76 - GPR76 General Purpose Register | |
#define | IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK (0x1U) |
#define | IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT (0U) |
#define | IOMUXC_GPR_GPR76_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK (0x2U) |
#define | IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT (1U) |
#define | IOMUXC_GPR_GPR76_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK (0x4U) |
#define | IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT (2U) |
#define | IOMUXC_GPR_GPR76_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK (0x8U) |
#define | IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT (3U) |
#define | IOMUXC_GPR_GPR76_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK (0x10U) |
#define | IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT (4U) |
#define | IOMUXC_GPR_GPR76_MIC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK (0x20U) |
#define | IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT (5U) |
#define | IOMUXC_GPR_GPR76_PIT1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK (0x40U) |
#define | IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT (6U) |
#define | IOMUXC_GPR_GPR76_PIT2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK (0x80U) |
#define | IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT (7U) |
#define | IOMUXC_GPR_GPR76_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK (0x100U) |
#define | IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT (8U) |
#define | IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK (0x200U) |
#define | IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT (9U) |
#define | IOMUXC_GPR_GPR76_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK (0x400U) |
#define | IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT (10U) |
#define | IOMUXC_GPR_GPR76_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK (0x800U) |
#define | IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT (11U) |
#define | IOMUXC_GPR_GPR76_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK (0x1000U) |
#define | IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT (12U) |
#define | IOMUXC_GPR_GPR76_SAI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK) |
#define | IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U) |
#define | IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT (13U) |
#define | IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK) |
#define | IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK (0x4000U) |
#define | IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT (14U) |
#define | IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK) |
#define | IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U) |
#define | IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT (15U) |
#define | IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK) |
#define | IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK (0x10000U) |
#define | IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT (16U) |
#define | IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK) |
SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register | |
#define | IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) |
#define | IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK) |
#define | IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK (0x10U) |
#define | IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT (4U) |
#define | IOMUXC_LPSR_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK) |
SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register | |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK (0x1U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT (0U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK (0x2U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT (1U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK (0x4U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT (2U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK (0x8U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT (3U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK (0x20U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT (5U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK (0x30000000U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT (28U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK) |
SELECT_INPUT - CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register | |
#define | IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ |
#define | IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT (0U) |
#define | IOMUXC_LPSR_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ |
GPR6 - GPR6 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR6_LOCK_MASK (0x1U) |
#define | IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT (0U) |
#define | IOMUXC_LPSR_GPR_GPR6_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_LOCK_MASK) |
#define | IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) |
#define | IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT (3U) |
#define | IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK) |
GPR19 - GPR19 General Purpose Register | |
#define | IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK (0x10U) |
#define | IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT (4U) |
#define | IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK) |
#define | IOMUXC_LPSR_GPR_GPR19_LOCK_MASK (0xFFFF0000U) |
#define | IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT (16U) |
#define | IOMUXC_LPSR_GPR_GPR19_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_LOCK_MASK) |
SW_MUX_CTL_PAD_WAKEUP_DIG - SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK) |
SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG - SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK) |
SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG - SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK) |
SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK) |
SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK) |
SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK) |
SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK) |
SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK) |
SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK) |
SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK) |
SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK) |
SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK) |
SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register | |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK (0x7U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK (0x10U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT (4U) |
#define | IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK) |
SW_PAD_CTL_PAD_TEST_MODE_DIG - SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_POR_B_DIG - SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_ONOFF_DIG - SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_WAKEUP_DIG - SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG - SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG - SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK) |
SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register | |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK (0x1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT (0U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK (0x2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT (1U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK (0x4U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT (2U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK (0x8U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT (3U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK (0x40U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT (6U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK (0x30000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT (28U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK (0xC0000000U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT (30U) |
#define | IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK) |
GPR - GPR0 General Purpose Register | |
#define | IOMUXC_SNVS_GPR_GPR_GPR_MASK (0xFFFFFFFFU) |
#define | IOMUXC_SNVS_GPR_GPR_GPR_SHIFT (0U) |
#define | IOMUXC_SNVS_GPR_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR_GPR_MASK) |
SLOT_CTRL - Slot Control Register | |
#define | IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK (0x8000U) |
#define | IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT (15U) |
#define | IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK (0x10000U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT (16U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK (0x20000U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT (17U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_USER(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK (0x80000000U) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT (31U) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK) |
MASTER_KEY_CTRL - CSR Master Key Control Register | |
#define | KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK (0x1U) |
#define | KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT (0U) |
#define | KEY_MANAGER_MASTER_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK) |
#define | KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK (0x10000U) |
#define | KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT (16U) |
#define | KEY_MANAGER_MASTER_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK) |
OTFAD1_KEY_CTRL - CSR OTFAD-1 Key Control | |
#define | KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK (0x1U) |
#define | KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT (0U) |
#define | KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK) |
#define | KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK (0x10000U) |
#define | KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT (16U) |
#define | KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK) |
OTFAD2_KEY_CTRL - CSR OTFAD-2 Key Control | |
#define | KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK (0x1U) |
#define | KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT (0U) |
#define | KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK) |
#define | KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK (0x10000U) |
#define | KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT (16U) |
#define | KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK) |
IEE_KEY_CTRL - CSR IEE Key Control | |
#define | KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK (0x1U) |
#define | KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT (0U) |
#define | KEY_MANAGER_IEE_KEY_CTRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT)) & KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK) |
PUF_KEY_CTRL - CSR PUF Key Control | |
#define | KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK (0x1U) |
#define | KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT (0U) |
#define | KEY_MANAGER_PUF_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK) |
SLOT0_CTRL - Slot 0 Control | |
#define | KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK (0xFU) |
#define | KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT (0U) |
#define | KEY_MANAGER_SLOT0_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK) |
#define | KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK (0x8000U) |
#define | KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT (15U) |
#define | KEY_MANAGER_SLOT0_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK) |
#define | KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK (0x10000U) |
#define | KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT (16U) |
#define | KEY_MANAGER_SLOT0_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK) |
#define | KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK (0x20000U) |
#define | KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT (17U) |
#define | KEY_MANAGER_SLOT0_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK) |
#define | KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK (0x80000000U) |
#define | KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT (31U) |
#define | KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK) |
SLOT1_CTRL - Slot1 Control | |
#define | KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK (0xFU) |
#define | KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT (0U) |
#define | KEY_MANAGER_SLOT1_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK) |
#define | KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK (0x8000U) |
#define | KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT (15U) |
#define | KEY_MANAGER_SLOT1_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK) |
#define | KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK (0x10000U) |
#define | KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT (16U) |
#define | KEY_MANAGER_SLOT1_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK) |
#define | KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK (0x20000U) |
#define | KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT (17U) |
#define | KEY_MANAGER_SLOT1_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK) |
#define | KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK (0x80000000U) |
#define | KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT (31U) |
#define | KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK) |
SLOT2_CTRL - Slot2 Control | |
#define | KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK (0xFU) |
#define | KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT (0U) |
#define | KEY_MANAGER_SLOT2_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK) |
#define | KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK (0x8000U) |
#define | KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT (15U) |
#define | KEY_MANAGER_SLOT2_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK) |
#define | KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK (0x10000U) |
#define | KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT (16U) |
#define | KEY_MANAGER_SLOT2_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK) |
#define | KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK (0x20000U) |
#define | KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT (17U) |
#define | KEY_MANAGER_SLOT2_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK) |
#define | KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK (0x80000000U) |
#define | KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT (31U) |
#define | KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK) |
SLOT3_CTRL - Slot3 Control | |
#define | KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK (0xFU) |
#define | KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT (0U) |
#define | KEY_MANAGER_SLOT3_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK) |
#define | KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK (0x8000U) |
#define | KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT (15U) |
#define | KEY_MANAGER_SLOT3_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK) |
#define | KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK (0x10000U) |
#define | KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT (16U) |
#define | KEY_MANAGER_SLOT3_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK) |
#define | KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK (0x20000U) |
#define | KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT (17U) |
#define | KEY_MANAGER_SLOT3_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK) |
#define | KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK (0x80000000U) |
#define | KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT (31U) |
#define | KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK) |
SLOT4_CTRL - Slot 4 Control | |
#define | KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK (0xFU) |
#define | KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT (0U) |
#define | KEY_MANAGER_SLOT4_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK) |
#define | KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK (0x8000U) |
#define | KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT (15U) |
#define | KEY_MANAGER_SLOT4_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK) |
#define | KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK (0x10000U) |
#define | KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT (16U) |
#define | KEY_MANAGER_SLOT4_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK) |
#define | KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK (0x20000U) |
#define | KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT (17U) |
#define | KEY_MANAGER_SLOT4_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK) |
#define | KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK (0x80000000U) |
#define | KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT (31U) |
#define | KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK) |
KPCR - Keypad Control Register | |
#define | KPP_KPCR_KRE_MASK (0xFFU) |
#define | KPP_KPCR_KRE_SHIFT (0U) |
#define | KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) |
#define | KPP_KPCR_KCO_MASK (0xFF00U) |
#define | KPP_KPCR_KCO_SHIFT (8U) |
#define | KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) |
KPSR - Keypad Status Register | |
#define | KPP_KPSR_KPKD_MASK (0x1U) |
#define | KPP_KPSR_KPKD_SHIFT (0U) |
#define | KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) |
#define | KPP_KPSR_KPKR_MASK (0x2U) |
#define | KPP_KPSR_KPKR_SHIFT (1U) |
#define | KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) |
#define | KPP_KPSR_KDSC_MASK (0x4U) |
#define | KPP_KPSR_KDSC_SHIFT (2U) |
#define | KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) |
#define | KPP_KPSR_KRSS_MASK (0x8U) |
#define | KPP_KPSR_KRSS_SHIFT (3U) |
#define | KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) |
#define | KPP_KPSR_KDIE_MASK (0x100U) |
#define | KPP_KPSR_KDIE_SHIFT (8U) |
#define | KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) |
#define | KPP_KPSR_KRIE_MASK (0x200U) |
#define | KPP_KPSR_KRIE_SHIFT (9U) |
#define | KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) |
KDDR - Keypad Data Direction Register | |
#define | KPP_KDDR_KRDD_MASK (0xFFU) |
#define | KPP_KDDR_KRDD_SHIFT (0U) |
#define | KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) |
#define | KPP_KDDR_KCDD_MASK (0xFF00U) |
#define | KPP_KDDR_KCDD_SHIFT (8U) |
#define | KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) |
KPDR - Keypad Data Register | |
#define | KPP_KPDR_KRD_MASK (0xFFU) |
#define | KPP_KPDR_KRD_SHIFT (0U) |
#define | KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) |
#define | KPP_KPDR_KCD_MASK (0xFF00U) |
#define | KPP_KPDR_KCD_SHIFT (8U) |
#define | KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) |
CTRL - LCDIF General Control Register | |
#define | LCDIF_CTRL_RUN_MASK (0x1U) |
#define | LCDIF_CTRL_RUN_SHIFT (0U) |
#define | LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) |
#define | LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) |
#define | LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) |
#define | LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) |
#define | LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) |
#define | LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) |
#define | LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) |
#define | LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) |
#define | LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) |
#define | LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) |
#define | LCDIF_CTRL_RSRVD0_MASK (0x10U) |
#define | LCDIF_CTRL_RSRVD0_SHIFT (4U) |
#define | LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) |
#define | LCDIF_CTRL_MASTER_MASK (0x20U) |
#define | LCDIF_CTRL_MASTER_SHIFT (5U) |
#define | LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) |
#define | LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) |
#define | LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) |
#define | LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) |
#define | LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) |
#define | LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) |
#define | LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) |
#define | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) |
#define | LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) |
#define | LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) |
#define | LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) |
#define | LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) |
#define | LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) |
#define | LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) |
#define | LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) |
#define | LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) |
#define | LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) |
#define | LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) |
#define | LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) |
#define | LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) |
#define | LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) |
#define | LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) |
#define | LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) |
#define | LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) |
#define | LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) |
#define | LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) |
#define | LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) |
#define | LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) |
#define | LCDIF_CTRL_CLKGATE_MASK (0x40000000U) |
#define | LCDIF_CTRL_CLKGATE_SHIFT (30U) |
#define | LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) |
#define | LCDIF_CTRL_SFTRST_MASK (0x80000000U) |
#define | LCDIF_CTRL_SFTRST_SHIFT (31U) |
#define | LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) |
CTRL_SET - LCDIF General Control Register | |
#define | LCDIF_CTRL_SET_RUN_MASK (0x1U) |
#define | LCDIF_CTRL_SET_RUN_SHIFT (0U) |
#define | LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) |
#define | LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) |
#define | LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) |
#define | LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) |
#define | LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) |
#define | LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) |
#define | LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) |
#define | LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) |
#define | LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) |
#define | LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) |
#define | LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) |
#define | LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) |
#define | LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) |
#define | LCDIF_CTRL_SET_MASTER_MASK (0x20U) |
#define | LCDIF_CTRL_SET_MASTER_SHIFT (5U) |
#define | LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) |
#define | LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) |
#define | LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) |
#define | LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) |
#define | LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) |
#define | LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) |
#define | LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) |
#define | LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) |
#define | LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) |
#define | LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) |
#define | LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) |
#define | LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) |
#define | LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) |
#define | LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) |
#define | LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) |
#define | LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) |
#define | LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) |
#define | LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) |
#define | LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) |
#define | LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) |
#define | LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) |
#define | LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) |
#define | LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) |
#define | LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) |
#define | LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) |
#define | LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) |
#define | LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) |
#define | LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) |
#define | LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) |
#define | LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) |
#define | LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) |
#define | LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) |
#define | LCDIF_CTRL_SET_SFTRST_SHIFT (31U) |
#define | LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) |
CTRL_CLR - LCDIF General Control Register | |
#define | LCDIF_CTRL_CLR_RUN_MASK (0x1U) |
#define | LCDIF_CTRL_CLR_RUN_SHIFT (0U) |
#define | LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) |
#define | LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) |
#define | LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) |
#define | LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) |
#define | LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) |
#define | LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) |
#define | LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) |
#define | LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) |
#define | LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) |
#define | LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) |
#define | LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) |
#define | LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) |
#define | LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) |
#define | LCDIF_CTRL_CLR_MASTER_MASK (0x20U) |
#define | LCDIF_CTRL_CLR_MASTER_SHIFT (5U) |
#define | LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) |
#define | LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) |
#define | LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) |
#define | LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) |
#define | LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) |
#define | LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) |
#define | LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) |
#define | LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) |
#define | LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) |
#define | LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) |
#define | LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) |
#define | LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) |
#define | LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) |
#define | LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) |
#define | LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) |
#define | LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) |
#define | LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) |
#define | LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) |
#define | LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) |
#define | LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) |
#define | LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) |
#define | LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) |
#define | LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) |
#define | LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) |
#define | LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) |
#define | LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) |
#define | LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) |
#define | LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) |
#define | LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) |
#define | LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) |
#define | LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) |
#define | LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) |
#define | LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) |
#define | LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) |
CTRL_TOG - LCDIF General Control Register | |
#define | LCDIF_CTRL_TOG_RUN_MASK (0x1U) |
#define | LCDIF_CTRL_TOG_RUN_SHIFT (0U) |
#define | LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) |
#define | LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) |
#define | LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) |
#define | LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) |
#define | LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) |
#define | LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) |
#define | LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) |
#define | LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) |
#define | LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) |
#define | LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) |
#define | LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) |
#define | LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) |
#define | LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) |
#define | LCDIF_CTRL_TOG_MASTER_MASK (0x20U) |
#define | LCDIF_CTRL_TOG_MASTER_SHIFT (5U) |
#define | LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) |
#define | LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) |
#define | LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) |
#define | LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) |
#define | LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) |
#define | LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) |
#define | LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) |
#define | LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) |
#define | LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) |
#define | LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) |
#define | LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) |
#define | LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) |
#define | LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) |
#define | LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) |
#define | LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) |
#define | LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) |
#define | LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) |
#define | LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) |
#define | LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) |
#define | LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) |
#define | LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) |
#define | LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) |
#define | LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) |
#define | LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) |
#define | LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) |
#define | LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) |
#define | LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) |
#define | LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) |
#define | LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) |
#define | LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) |
#define | LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) |
#define | LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) |
#define | LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) |
#define | LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) |
CTRL1 - LCDIF General Control1 Register | |
#define | LCDIF_CTRL1_RSRVD0_MASK (0xF8U) |
#define | LCDIF_CTRL1_RSRVD0_SHIFT (3U) |
#define | LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) |
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) |
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) |
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) |
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) |
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) |
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) |
#define | LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) |
#define | LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) |
#define | LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) |
#define | LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) |
#define | LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) |
#define | LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) |
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) |
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) |
#define | LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) |
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) |
#define | LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) |
#define | LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) |
#define | LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) |
#define | LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) |
#define | LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) |
#define | LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) |
#define | LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) |
#define | LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) |
#define | LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) |
#define | LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) |
#define | LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) |
#define | LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) |
#define | LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) |
#define | LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) |
#define | LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) |
#define | LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) |
#define | LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) |
#define | LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) |
#define | LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) |
#define | LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) |
#define | LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) |
#define | LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) |
#define | LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) |
#define | LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) |
#define | LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) |
#define | LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) |
#define | LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) |
#define | LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U) |
#define | LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U) |
#define | LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK) |
#define | LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U) |
#define | LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U) |
#define | LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK) |
CTRL1_SET - LCDIF General Control1 Register | |
#define | LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) |
#define | LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) |
#define | LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) |
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) |
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) |
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) |
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) |
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) |
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) |
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) |
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) |
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) |
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) |
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) |
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) |
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) |
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) |
#define | LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) |
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) |
#define | LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) |
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) |
#define | LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) |
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) |
#define | LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) |
#define | LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) |
#define | LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) |
#define | LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) |
#define | LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) |
#define | LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) |
#define | LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) |
#define | LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) |
#define | LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) |
#define | LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) |
#define | LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) |
#define | LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) |
#define | LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) |
#define | LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) |
#define | LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) |
#define | LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) |
#define | LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) |
#define | LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) |
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) |
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) |
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) |
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) |
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) |
#define | LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U) |
#define | LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U) |
#define | LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK) |
#define | LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U) |
#define | LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U) |
#define | LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK) |
CTRL1_CLR - LCDIF General Control1 Register | |
#define | LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) |
#define | LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) |
#define | LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) |
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) |
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) |
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) |
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) |
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) |
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) |
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) |
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) |
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) |
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) |
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) |
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) |
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) |
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) |
#define | LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) |
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) |
#define | LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) |
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) |
#define | LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) |
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) |
#define | LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) |
#define | LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) |
#define | LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) |
#define | LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) |
#define | LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) |
#define | LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) |
#define | LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) |
#define | LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) |
#define | LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) |
#define | LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) |
#define | LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) |
#define | LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) |
#define | LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) |
#define | LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) |
#define | LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) |
#define | LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) |
#define | LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) |
#define | LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) |
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) |
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) |
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) |
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) |
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) |
#define | LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U) |
#define | LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U) |
#define | LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK) |
#define | LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U) |
#define | LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U) |
#define | LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK) |
CTRL1_TOG - LCDIF General Control1 Register | |
#define | LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) |
#define | LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) |
#define | LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) |
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) |
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) |
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) |
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) |
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) |
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) |
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) |
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) |
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) |
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) |
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) |
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) |
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) |
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) |
#define | LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) |
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) |
#define | LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) |
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) |
#define | LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) |
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) |
#define | LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) |
#define | LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) |
#define | LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) |
#define | LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) |
#define | LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) |
#define | LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) |
#define | LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) |
#define | LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) |
#define | LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) |
#define | LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) |
#define | LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) |
#define | LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) |
#define | LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) |
#define | LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) |
#define | LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) |
#define | LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) |
#define | LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) |
#define | LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) |
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) |
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) |
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) |
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) |
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) |
#define | LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) |
#define | LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U) |
#define | LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U) |
#define | LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK) |
#define | LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U) |
#define | LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U) |
#define | LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK) |
CTRL2 - LCDIF General Control2 Register | |
#define | LCDIF_CTRL2_RSRVD0_MASK (0xFFFU) |
#define | LCDIF_CTRL2_RSRVD0_SHIFT (0U) |
#define | LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) |
#define | LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) |
#define | LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) |
#define | LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) |
#define | LCDIF_CTRL2_RSRVD3_MASK (0x8000U) |
#define | LCDIF_CTRL2_RSRVD3_SHIFT (15U) |
#define | LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) |
#define | LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) |
#define | LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) |
#define | LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) |
#define | LCDIF_CTRL2_RSRVD4_MASK (0x80000U) |
#define | LCDIF_CTRL2_RSRVD4_SHIFT (19U) |
#define | LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) |
#define | LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) |
#define | LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) |
#define | LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) |
#define | LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) |
#define | LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) |
#define | LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) |
#define | LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) |
#define | LCDIF_CTRL2_RSRVD5_SHIFT (24U) |
#define | LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) |
CTRL2_SET - LCDIF General Control2 Register | |
#define | LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU) |
#define | LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) |
#define | LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) |
#define | LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) |
#define | LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) |
#define | LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) |
#define | LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) |
#define | LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) |
#define | LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) |
#define | LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) |
#define | LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) |
#define | LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) |
#define | LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) |
#define | LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) |
#define | LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) |
#define | LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) |
#define | LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) |
#define | LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) |
#define | LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) |
#define | LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) |
#define | LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) |
#define | LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) |
#define | LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) |
#define | LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) |
CTRL2_CLR - LCDIF General Control2 Register | |
#define | LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU) |
#define | LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) |
#define | LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) |
#define | LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) |
#define | LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) |
#define | LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) |
#define | LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) |
#define | LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) |
#define | LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) |
#define | LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) |
#define | LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) |
#define | LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) |
#define | LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) |
#define | LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) |
#define | LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) |
#define | LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) |
#define | LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) |
#define | LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) |
#define | LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) |
#define | LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) |
#define | LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) |
#define | LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) |
#define | LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) |
#define | LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) |
CTRL2_TOG - LCDIF General Control2 Register | |
#define | LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU) |
#define | LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) |
#define | LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) |
#define | LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) |
#define | LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) |
#define | LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) |
#define | LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) |
#define | LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) |
#define | LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) |
#define | LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) |
#define | LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) |
#define | LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) |
#define | LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) |
#define | LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) |
#define | LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) |
#define | LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) |
#define | LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) |
#define | LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) |
#define | LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) |
#define | LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) |
#define | LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) |
#define | LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) |
#define | LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) |
#define | LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) |
TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register | |
#define | LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) |
#define | LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) |
#define | LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) |
#define | LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) |
#define | LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) |
#define | LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) |
CUR_BUF - LCD Interface Current Buffer Address Register | |
#define | LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) |
#define | LCDIF_CUR_BUF_ADDR_SHIFT (0U) |
#define | LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) |
NEXT_BUF - LCD Interface Next Buffer Address Register | |
#define | LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) |
#define | LCDIF_NEXT_BUF_ADDR_SHIFT (0U) |
#define | LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) |
VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 | |
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) |
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) |
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) |
#define | LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) |
#define | LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) |
#define | LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) |
#define | LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) |
#define | LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) |
#define | LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) |
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) |
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) |
#define | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) |
#define | LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) |
#define | LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) |
#define | LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) |
#define | LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) |
#define | LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) |
#define | LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) |
#define | LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) |
#define | LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) |
#define | LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) |
#define | LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) |
#define | LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) |
#define | LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) |
#define | LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) |
#define | LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) |
#define | LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) |
#define | LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) |
#define | LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) |
#define | LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) |
#define | LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) |
#define | LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) |
#define | LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) |
#define | LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U) |
#define | LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U) |
#define | LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK) |
#define | LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U) |
#define | LCDIF_VDCTRL0_RSRVD2_SHIFT (30U) |
#define | LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) |
VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 | |
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) |
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) |
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) |
#define | LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) |
#define | LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) |
#define | LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) |
#define | LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) |
#define | LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) |
#define | LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) |
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) |
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) |
#define | LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) |
#define | LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) |
#define | LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) |
#define | LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) |
#define | LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) |
#define | LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) |
#define | LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) |
#define | LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) |
#define | LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) |
#define | LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) |
#define | LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) |
#define | LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) |
#define | LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) |
#define | LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) |
#define | LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) |
#define | LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) |
#define | LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) |
#define | LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) |
#define | LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) |
#define | LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) |
#define | LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) |
#define | LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) |
#define | LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U) |
#define | LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U) |
#define | LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK) |
#define | LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U) |
#define | LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U) |
#define | LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) |
VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 | |
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) |
#define | LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) |
#define | LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) |
#define | LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) |
#define | LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) |
#define | LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) |
#define | LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) |
#define | LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) |
#define | LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) |
#define | LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) |
#define | LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) |
#define | LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) |
#define | LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) |
#define | LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) |
#define | LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) |
#define | LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) |
#define | LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) |
#define | LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) |
#define | LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) |
#define | LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) |
#define | LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) |
#define | LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U) |
#define | LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK) |
#define | LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U) |
#define | LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U) |
#define | LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) |
VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 | |
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) |
#define | LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) |
#define | LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) |
#define | LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) |
#define | LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) |
#define | LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) |
#define | LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) |
#define | LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) |
#define | LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) |
#define | LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) |
#define | LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) |
#define | LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) |
#define | LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) |
#define | LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) |
#define | LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) |
#define | LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) |
#define | LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) |
#define | LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) |
#define | LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) |
#define | LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) |
#define | LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) |
#define | LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U) |
#define | LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK) |
#define | LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U) |
#define | LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U) |
#define | LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) |
VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 | |
#define | LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) |
#define | LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) |
#define | LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) |
VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 | |
#define | LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) |
#define | LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) |
#define | LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) |
#define | LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) |
#define | LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) |
#define | LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) |
VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 | |
#define | LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) |
#define | LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) |
#define | LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) |
#define | LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) |
#define | LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) |
#define | LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) |
#define | LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) |
#define | LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) |
#define | LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) |
#define | LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) |
#define | LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) |
#define | LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) |
#define | LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) |
#define | LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) |
#define | LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) |
VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 | |
#define | LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) |
#define | LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) |
#define | LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) |
#define | LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) |
#define | LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) |
#define | LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) |
#define | LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) |
#define | LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) |
#define | LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) |
#define | LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) |
#define | LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) |
#define | LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) |
BM_ERROR_STAT - Bus Master Error Status Register | |
#define | LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) |
#define | LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) |
#define | LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) |
CRC_STAT - CRC Status Register | |
#define | LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) |
#define | LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) |
#define | LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) |
STAT - LCD Interface Status Register | |
#define | LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) |
#define | LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) |
#define | LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) |
#define | LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U) |
#define | LCDIF_STAT_RSRVD0_SHIFT (9U) |
#define | LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) |
#define | LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) |
#define | LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) |
#define | LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) |
#define | LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) |
#define | LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) |
#define | LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) |
#define | LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) |
#define | LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) |
#define | LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) |
#define | LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) |
#define | LCDIF_STAT_LFIFO_FULL_SHIFT (29U) |
#define | LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) |
#define | LCDIF_STAT_DMA_REQ_MASK (0x40000000U) |
#define | LCDIF_STAT_DMA_REQ_SHIFT (30U) |
#define | LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK) |
#define | LCDIF_STAT_PRESENT_MASK (0x80000000U) |
#define | LCDIF_STAT_PRESENT_SHIFT (31U) |
#define | LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) |
THRES - LCDIF Threshold Register | |
#define | LCDIF_THRES_RSRVD_MASK (0x1FFU) |
#define | LCDIF_THRES_RSRVD_SHIFT (0U) |
#define | LCDIF_THRES_RSRVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD_SHIFT)) & LCDIF_THRES_RSRVD_MASK) |
#define | LCDIF_THRES_RSRVD1_MASK (0xFE00U) |
#define | LCDIF_THRES_RSRVD1_SHIFT (9U) |
#define | LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) |
#define | LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) |
#define | LCDIF_THRES_FASTCLOCK_SHIFT (16U) |
#define | LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) |
#define | LCDIF_THRES_RSRVD2_MASK (0xFE000000U) |
#define | LCDIF_THRES_RSRVD2_SHIFT (25U) |
#define | LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) |
PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register | |
#define | LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU) |
#define | LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK) |
#define | LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U) |
#define | LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U) |
#define | LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK) |
PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register | |
#define | LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU) |
#define | LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK) |
#define | LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U) |
#define | LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U) |
#define | LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK) |
PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register | |
#define | LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU) |
#define | LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK) |
#define | LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U) |
#define | LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U) |
#define | LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK) |
PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register | |
#define | LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU) |
#define | LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK) |
#define | LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U) |
#define | LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U) |
#define | LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK) |
PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register | |
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU) |
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK) |
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U) |
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U) |
#define | LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK) |
PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register | |
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU) |
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK) |
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U) |
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U) |
#define | LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK) |
PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register | |
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU) |
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK) |
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U) |
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U) |
#define | LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK) |
PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register | |
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU) |
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK) |
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U) |
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U) |
#define | LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK) |
PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register | |
#define | LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U) |
#define | LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK) |
#define | LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U) |
#define | LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U) |
#define | LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK) |
PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register | |
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U) |
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK) |
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U) |
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U) |
#define | LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK) |
PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register | |
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U) |
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK) |
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U) |
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U) |
#define | LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK) |
PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register | |
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U) |
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U) |
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK) |
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U) |
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U) |
#define | LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK) |
PIGEON_0 - Panel Interface Signal Generator Register | |
#define | LCDIF_PIGEON_0_EN_MASK (0x1U) |
#define | LCDIF_PIGEON_0_EN_SHIFT (0U) |
#define | LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK) |
#define | LCDIF_PIGEON_0_POL_MASK (0x2U) |
#define | LCDIF_PIGEON_0_POL_SHIFT (1U) |
#define | LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK) |
#define | LCDIF_PIGEON_0_INC_SEL_MASK (0xCU) |
#define | LCDIF_PIGEON_0_INC_SEL_SHIFT (2U) |
#define | LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK) |
#define | LCDIF_PIGEON_0_OFFSET_MASK (0xF0U) |
#define | LCDIF_PIGEON_0_OFFSET_SHIFT (4U) |
#define | LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK) |
#define | LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U) |
#define | LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U) |
#define | LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK) |
#define | LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U) |
#define | LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U) |
#define | LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK) |
#define | LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U) |
#define | LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U) |
#define | LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK) |
PIGEON_1 - Panel Interface Signal Generator Register | |
#define | LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU) |
#define | LCDIF_PIGEON_1_SET_CNT_SHIFT (0U) |
#define | LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK) |
#define | LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U) |
#define | LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U) |
#define | LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK) |
PIGEON_2 - Panel Interface Signal Generator Register | |
#define | LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU) |
#define | LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U) |
#define | LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK) |
#define | LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U) |
#define | LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U) |
#define | LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK) |
#define | LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U) |
#define | LCDIF_PIGEON_2_RSVD_SHIFT (9U) |
#define | LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK) |
LUT_CTRL - Look Up Table Control Register | |
#define | LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U) |
#define | LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U) |
#define | LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK) |
LUT0_ADDR - Lookup Table 0 Index Register | |
#define | LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU) |
#define | LCDIF_LUT0_ADDR_ADDR_SHIFT (0U) |
#define | LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK) |
LUT0_DATA - Lookup Table 0 Data Register | |
#define | LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU) |
#define | LCDIF_LUT0_DATA_DATA_SHIFT (0U) |
#define | LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK) |
LUT1_ADDR - Lookup Table 1 Index Register | |
#define | LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU) |
#define | LCDIF_LUT1_ADDR_ADDR_SHIFT (0U) |
#define | LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK) |
LUT1_DATA - Lookup Table 1 Data Register | |
#define | LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU) |
#define | LCDIF_LUT1_DATA_DATA_SHIFT (0U) |
#define | LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) |
CTRL - LCDIFv2 display control Register | |
#define | LCDIFV2_CTRL_INV_HS_MASK (0x1U) |
#define | LCDIFV2_CTRL_INV_HS_SHIFT (0U) |
#define | LCDIFV2_CTRL_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_HS_SHIFT)) & LCDIFV2_CTRL_INV_HS_MASK) |
#define | LCDIFV2_CTRL_INV_VS_MASK (0x2U) |
#define | LCDIFV2_CTRL_INV_VS_SHIFT (1U) |
#define | LCDIFV2_CTRL_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_VS_SHIFT)) & LCDIFV2_CTRL_INV_VS_MASK) |
#define | LCDIFV2_CTRL_INV_DE_MASK (0x4U) |
#define | LCDIFV2_CTRL_INV_DE_SHIFT (2U) |
#define | LCDIFV2_CTRL_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_DE_SHIFT)) & LCDIFV2_CTRL_INV_DE_MASK) |
#define | LCDIFV2_CTRL_INV_PXCK_MASK (0x8U) |
#define | LCDIFV2_CTRL_INV_PXCK_SHIFT (3U) |
#define | LCDIFV2_CTRL_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_INV_PXCK_MASK) |
#define | LCDIFV2_CTRL_NEG_MASK (0x10U) |
#define | LCDIFV2_CTRL_NEG_SHIFT (4U) |
#define | LCDIFV2_CTRL_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_NEG_SHIFT)) & LCDIFV2_CTRL_NEG_MASK) |
#define | LCDIFV2_CTRL_SW_RESET_MASK (0x80000000U) |
#define | LCDIFV2_CTRL_SW_RESET_SHIFT (31U) |
#define | LCDIFV2_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SW_RESET_MASK) |
CTRL_SET - LCDIFv2 display control Register | |
#define | LCDIFV2_CTRL_SET_INV_HS_MASK (0x1U) |
#define | LCDIFV2_CTRL_SET_INV_HS_SHIFT (0U) |
#define | LCDIFV2_CTRL_SET_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_HS_SHIFT)) & LCDIFV2_CTRL_SET_INV_HS_MASK) |
#define | LCDIFV2_CTRL_SET_INV_VS_MASK (0x2U) |
#define | LCDIFV2_CTRL_SET_INV_VS_SHIFT (1U) |
#define | LCDIFV2_CTRL_SET_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_VS_SHIFT)) & LCDIFV2_CTRL_SET_INV_VS_MASK) |
#define | LCDIFV2_CTRL_SET_INV_DE_MASK (0x4U) |
#define | LCDIFV2_CTRL_SET_INV_DE_SHIFT (2U) |
#define | LCDIFV2_CTRL_SET_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_DE_SHIFT)) & LCDIFV2_CTRL_SET_INV_DE_MASK) |
#define | LCDIFV2_CTRL_SET_INV_PXCK_MASK (0x8U) |
#define | LCDIFV2_CTRL_SET_INV_PXCK_SHIFT (3U) |
#define | LCDIFV2_CTRL_SET_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_SET_INV_PXCK_MASK) |
#define | LCDIFV2_CTRL_SET_NEG_MASK (0x10U) |
#define | LCDIFV2_CTRL_SET_NEG_SHIFT (4U) |
#define | LCDIFV2_CTRL_SET_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_NEG_SHIFT)) & LCDIFV2_CTRL_SET_NEG_MASK) |
#define | LCDIFV2_CTRL_SET_SW_RESET_MASK (0x80000000U) |
#define | LCDIFV2_CTRL_SET_SW_RESET_SHIFT (31U) |
#define | LCDIFV2_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SET_SW_RESET_MASK) |
CTRL_CLR - LCDIFv2 display control Register | |
#define | LCDIFV2_CTRL_CLR_INV_HS_MASK (0x1U) |
#define | LCDIFV2_CTRL_CLR_INV_HS_SHIFT (0U) |
#define | LCDIFV2_CTRL_CLR_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_HS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_HS_MASK) |
#define | LCDIFV2_CTRL_CLR_INV_VS_MASK (0x2U) |
#define | LCDIFV2_CTRL_CLR_INV_VS_SHIFT (1U) |
#define | LCDIFV2_CTRL_CLR_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_VS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_VS_MASK) |
#define | LCDIFV2_CTRL_CLR_INV_DE_MASK (0x4U) |
#define | LCDIFV2_CTRL_CLR_INV_DE_SHIFT (2U) |
#define | LCDIFV2_CTRL_CLR_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_DE_SHIFT)) & LCDIFV2_CTRL_CLR_INV_DE_MASK) |
#define | LCDIFV2_CTRL_CLR_INV_PXCK_MASK (0x8U) |
#define | LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT (3U) |
#define | LCDIFV2_CTRL_CLR_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_CLR_INV_PXCK_MASK) |
#define | LCDIFV2_CTRL_CLR_NEG_MASK (0x10U) |
#define | LCDIFV2_CTRL_CLR_NEG_SHIFT (4U) |
#define | LCDIFV2_CTRL_CLR_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_NEG_SHIFT)) & LCDIFV2_CTRL_CLR_NEG_MASK) |
#define | LCDIFV2_CTRL_CLR_SW_RESET_MASK (0x80000000U) |
#define | LCDIFV2_CTRL_CLR_SW_RESET_SHIFT (31U) |
#define | LCDIFV2_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_SW_RESET_SHIFT)) & LCDIFV2_CTRL_CLR_SW_RESET_MASK) |
CTRL_TOG - LCDIFv2 display control Register | |
#define | LCDIFV2_CTRL_TOG_INV_HS_MASK (0x1U) |
#define | LCDIFV2_CTRL_TOG_INV_HS_SHIFT (0U) |
#define | LCDIFV2_CTRL_TOG_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_HS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_HS_MASK) |
#define | LCDIFV2_CTRL_TOG_INV_VS_MASK (0x2U) |
#define | LCDIFV2_CTRL_TOG_INV_VS_SHIFT (1U) |
#define | LCDIFV2_CTRL_TOG_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_VS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_VS_MASK) |
#define | LCDIFV2_CTRL_TOG_INV_DE_MASK (0x4U) |
#define | LCDIFV2_CTRL_TOG_INV_DE_SHIFT (2U) |
#define | LCDIFV2_CTRL_TOG_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_DE_SHIFT)) & LCDIFV2_CTRL_TOG_INV_DE_MASK) |
#define | LCDIFV2_CTRL_TOG_INV_PXCK_MASK (0x8U) |
#define | LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT (3U) |
#define | LCDIFV2_CTRL_TOG_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_TOG_INV_PXCK_MASK) |
#define | LCDIFV2_CTRL_TOG_NEG_MASK (0x10U) |
#define | LCDIFV2_CTRL_TOG_NEG_SHIFT (4U) |
#define | LCDIFV2_CTRL_TOG_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_NEG_SHIFT)) & LCDIFV2_CTRL_TOG_NEG_MASK) |
#define | LCDIFV2_CTRL_TOG_SW_RESET_MASK (0x80000000U) |
#define | LCDIFV2_CTRL_TOG_SW_RESET_SHIFT (31U) |
#define | LCDIFV2_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_SW_RESET_SHIFT)) & LCDIFV2_CTRL_TOG_SW_RESET_MASK) |
DISP_PARA - Display Parameter Register | |
#define | LCDIFV2_DISP_PARA_BGND_B_MASK (0xFFU) |
#define | LCDIFV2_DISP_PARA_BGND_B_SHIFT (0U) |
#define | LCDIFV2_DISP_PARA_BGND_B(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_B_SHIFT)) & LCDIFV2_DISP_PARA_BGND_B_MASK) |
#define | LCDIFV2_DISP_PARA_BGND_G_MASK (0xFF00U) |
#define | LCDIFV2_DISP_PARA_BGND_G_SHIFT (8U) |
#define | LCDIFV2_DISP_PARA_BGND_G(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_G_SHIFT)) & LCDIFV2_DISP_PARA_BGND_G_MASK) |
#define | LCDIFV2_DISP_PARA_BGND_R_MASK (0xFF0000U) |
#define | LCDIFV2_DISP_PARA_BGND_R_SHIFT (16U) |
#define | LCDIFV2_DISP_PARA_BGND_R(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_R_SHIFT)) & LCDIFV2_DISP_PARA_BGND_R_MASK) |
#define | LCDIFV2_DISP_PARA_DISP_MODE_MASK (0x3000000U) |
#define | LCDIFV2_DISP_PARA_DISP_MODE_SHIFT (24U) |
#define | LCDIFV2_DISP_PARA_DISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_MODE_SHIFT)) & LCDIFV2_DISP_PARA_DISP_MODE_MASK) |
#define | LCDIFV2_DISP_PARA_LINE_PATTERN_MASK (0x1C000000U) |
#define | LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT (26U) |
#define | LCDIFV2_DISP_PARA_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIFV2_DISP_PARA_LINE_PATTERN_MASK) |
#define | LCDIFV2_DISP_PARA_DISP_ON_MASK (0x80000000U) |
#define | LCDIFV2_DISP_PARA_DISP_ON_SHIFT (31U) |
#define | LCDIFV2_DISP_PARA_DISP_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_ON_SHIFT)) & LCDIFV2_DISP_PARA_DISP_ON_MASK) |
DISP_SIZE - Display Size Register | |
#define | LCDIFV2_DISP_SIZE_DELTA_X_MASK (0xFFFU) |
#define | LCDIFV2_DISP_SIZE_DELTA_X_SHIFT (0U) |
#define | LCDIFV2_DISP_SIZE_DELTA_X(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_X_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_X_MASK) |
#define | LCDIFV2_DISP_SIZE_DELTA_Y_MASK (0xFFF0000U) |
#define | LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT (16U) |
#define | LCDIFV2_DISP_SIZE_DELTA_Y(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_Y_MASK) |
HSYN_PARA - Horizontal Sync Parameter Register | |
#define | LCDIFV2_HSYN_PARA_FP_H_MASK (0x1FFU) |
#define | LCDIFV2_HSYN_PARA_FP_H_SHIFT (0U) |
#define | LCDIFV2_HSYN_PARA_FP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_FP_H_SHIFT)) & LCDIFV2_HSYN_PARA_FP_H_MASK) |
#define | LCDIFV2_HSYN_PARA_PW_H_MASK (0xFF800U) |
#define | LCDIFV2_HSYN_PARA_PW_H_SHIFT (11U) |
#define | LCDIFV2_HSYN_PARA_PW_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_PW_H_SHIFT)) & LCDIFV2_HSYN_PARA_PW_H_MASK) |
#define | LCDIFV2_HSYN_PARA_BP_H_MASK (0x7FC00000U) |
#define | LCDIFV2_HSYN_PARA_BP_H_SHIFT (22U) |
#define | LCDIFV2_HSYN_PARA_BP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_BP_H_SHIFT)) & LCDIFV2_HSYN_PARA_BP_H_MASK) |
VSYN_PARA - Vertical Sync Parameter Register | |
#define | LCDIFV2_VSYN_PARA_FP_V_MASK (0x1FFU) |
#define | LCDIFV2_VSYN_PARA_FP_V_SHIFT (0U) |
#define | LCDIFV2_VSYN_PARA_FP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_FP_V_SHIFT)) & LCDIFV2_VSYN_PARA_FP_V_MASK) |
#define | LCDIFV2_VSYN_PARA_PW_V_MASK (0xFF800U) |
#define | LCDIFV2_VSYN_PARA_PW_V_SHIFT (11U) |
#define | LCDIFV2_VSYN_PARA_PW_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_PW_V_SHIFT)) & LCDIFV2_VSYN_PARA_PW_V_MASK) |
#define | LCDIFV2_VSYN_PARA_BP_V_MASK (0x7FC00000U) |
#define | LCDIFV2_VSYN_PARA_BP_V_SHIFT (22U) |
#define | LCDIFV2_VSYN_PARA_BP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_BP_V_SHIFT)) & LCDIFV2_VSYN_PARA_BP_V_MASK) |
INT_STATUS - Interrupt Status Register for domain 0..Interrupt Status Register for domain 1 | |
#define | LCDIFV2_INT_STATUS_VSYNC_MASK (0x1U) |
#define | LCDIFV2_INT_STATUS_VSYNC_SHIFT (0U) |
#define | LCDIFV2_INT_STATUS_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VSYNC_SHIFT)) & LCDIFV2_INT_STATUS_VSYNC_MASK) |
#define | LCDIFV2_INT_STATUS_UNDERRUN_MASK (0x2U) |
#define | LCDIFV2_INT_STATUS_UNDERRUN_SHIFT (1U) |
#define | LCDIFV2_INT_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_UNDERRUN_SHIFT)) & LCDIFV2_INT_STATUS_UNDERRUN_MASK) |
#define | LCDIFV2_INT_STATUS_VS_BLANK_MASK (0x4U) |
#define | LCDIFV2_INT_STATUS_VS_BLANK_SHIFT (2U) |
#define | LCDIFV2_INT_STATUS_VS_BLANK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VS_BLANK_SHIFT)) & LCDIFV2_INT_STATUS_VS_BLANK_MASK) |
#define | LCDIFV2_INT_STATUS_DMA_ERR_MASK (0xFF00U) |
#define | LCDIFV2_INT_STATUS_DMA_ERR_SHIFT (8U) |
#define | LCDIFV2_INT_STATUS_DMA_ERR(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_ERR_SHIFT)) & LCDIFV2_INT_STATUS_DMA_ERR_MASK) |
#define | LCDIFV2_INT_STATUS_DMA_DONE_MASK (0xFF0000U) |
#define | LCDIFV2_INT_STATUS_DMA_DONE_SHIFT (16U) |
#define | LCDIFV2_INT_STATUS_DMA_DONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_DONE_SHIFT)) & LCDIFV2_INT_STATUS_DMA_DONE_MASK) |
#define | LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK (0xFF000000U) |
#define | LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT (24U) |
#define | LCDIFV2_INT_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT)) & LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK) |
INT_ENABLE - Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1 | |
#define | LCDIFV2_INT_ENABLE_VSYNC_EN_MASK (0x1U) |
#define | LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT (0U) |
#define | LCDIFV2_INT_ENABLE_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VSYNC_EN_MASK) |
#define | LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK (0x2U) |
#define | LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT (1U) |
#define | LCDIFV2_INT_ENABLE_UNDERRUN_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT)) & LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK) |
#define | LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK (0x4U) |
#define | LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT (2U) |
#define | LCDIFV2_INT_ENABLE_VS_BLANK_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK) |
#define | LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK (0xFF00U) |
#define | LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT (8U) |
#define | LCDIFV2_INT_ENABLE_DMA_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK) |
#define | LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK (0xFF0000U) |
#define | LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT (16U) |
#define | LCDIFV2_INT_ENABLE_DMA_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK) |
#define | LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK (0xFF000000U) |
#define | LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT (24U) |
#define | LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK) |
PDI_PARA - Parallel Data Interface Parameter Register | |
#define | LCDIFV2_PDI_PARA_INV_PDI_HS_MASK (0x1U) |
#define | LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT (0U) |
#define | LCDIFV2_PDI_PARA_INV_PDI_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_HS_MASK) |
#define | LCDIFV2_PDI_PARA_INV_PDI_VS_MASK (0x2U) |
#define | LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT (1U) |
#define | LCDIFV2_PDI_PARA_INV_PDI_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_VS_MASK) |
#define | LCDIFV2_PDI_PARA_INV_PDI_DE_MASK (0x4U) |
#define | LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT (2U) |
#define | LCDIFV2_PDI_PARA_INV_PDI_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_DE_MASK) |
#define | LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK (0x8U) |
#define | LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT (3U) |
#define | LCDIFV2_PDI_PARA_INV_PDI_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK) |
#define | LCDIFV2_PDI_PARA_MODE_MASK (0xF0U) |
#define | LCDIFV2_PDI_PARA_MODE_SHIFT (4U) |
#define | LCDIFV2_PDI_PARA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_MODE_SHIFT)) & LCDIFV2_PDI_PARA_MODE_MASK) |
#define | LCDIFV2_PDI_PARA_PDI_SEL_MASK (0x40000000U) |
#define | LCDIFV2_PDI_PARA_PDI_SEL_SHIFT (30U) |
#define | LCDIFV2_PDI_PARA_PDI_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_SEL_SHIFT)) & LCDIFV2_PDI_PARA_PDI_SEL_MASK) |
#define | LCDIFV2_PDI_PARA_PDI_EN_MASK (0x80000000U) |
#define | LCDIFV2_PDI_PARA_PDI_EN_SHIFT (31U) |
#define | LCDIFV2_PDI_PARA_PDI_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_EN_SHIFT)) & LCDIFV2_PDI_PARA_PDI_EN_MASK) |
CTRLDESCL1 - Control Descriptor Layer 1 Register | |
#define | LCDIFV2_CTRLDESCL1_WIDTH_MASK (0xFFFU) |
#define | LCDIFV2_CTRLDESCL1_WIDTH_SHIFT (0U) |
#define | LCDIFV2_CTRLDESCL1_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_WIDTH_SHIFT)) & LCDIFV2_CTRLDESCL1_WIDTH_MASK) |
#define | LCDIFV2_CTRLDESCL1_HEIGHT_MASK (0xFFF0000U) |
#define | LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT (16U) |
#define | LCDIFV2_CTRLDESCL1_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT)) & LCDIFV2_CTRLDESCL1_HEIGHT_MASK) |
CTRLDESCL2 - Control Descriptor Layer 2 Register | |
#define | LCDIFV2_CTRLDESCL2_POSX_MASK (0xFFFU) |
#define | LCDIFV2_CTRLDESCL2_POSX_SHIFT (0U) |
#define | LCDIFV2_CTRLDESCL2_POSX(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSX_SHIFT)) & LCDIFV2_CTRLDESCL2_POSX_MASK) |
#define | LCDIFV2_CTRLDESCL2_POSY_MASK (0xFFF0000U) |
#define | LCDIFV2_CTRLDESCL2_POSY_SHIFT (16U) |
#define | LCDIFV2_CTRLDESCL2_POSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSY_SHIFT)) & LCDIFV2_CTRLDESCL2_POSY_MASK) |
CTRLDESCL3 - Control Descriptor Layer 3 Register | |
#define | LCDIFV2_CTRLDESCL3_PITCH_MASK (0xFFFFU) |
#define | LCDIFV2_CTRLDESCL3_PITCH_SHIFT (0U) |
#define | LCDIFV2_CTRLDESCL3_PITCH(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL3_PITCH_SHIFT)) & LCDIFV2_CTRLDESCL3_PITCH_MASK) |
CTRLDESCL4 - Control Descriptor Layer 4 Register | |
#define | LCDIFV2_CTRLDESCL4_ADDR_MASK (0xFFFFFFFFU) |
#define | LCDIFV2_CTRLDESCL4_ADDR_SHIFT (0U) |
#define | LCDIFV2_CTRLDESCL4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL4_ADDR_SHIFT)) & LCDIFV2_CTRLDESCL4_ADDR_MASK) |
CTRLDESCL5 - Control Descriptor Layer 5 Register | |
#define | LCDIFV2_CTRLDESCL5_AB_MODE_MASK (0x3U) |
#define | LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT (0U) |
#define | LCDIFV2_CTRLDESCL5_AB_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_AB_MODE_MASK) |
#define | LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK (0x30U) |
#define | LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT (4U) |
#define | LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK) |
#define | LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK (0xC0U) |
#define | LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT (6U) |
#define | LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK) |
#define | LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK (0x100U) |
#define | LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT (8U) |
#define | LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK) |
#define | LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK (0x200U) |
#define | LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT (9U) |
#define | LCDIFV2_CTRLDESCL5_PD_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK) |
#define | LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK (0xC000U) |
#define | LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT (14U) |
#define | LCDIFV2_CTRLDESCL5_YUV_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT)) & LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK) |
#define | LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK (0xFF0000U) |
#define | LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT (16U) |
#define | LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT)) & LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK) |
#define | LCDIFV2_CTRLDESCL5_BPP_MASK (0xF000000U) |
#define | LCDIFV2_CTRLDESCL5_BPP_SHIFT (24U) |
#define | LCDIFV2_CTRLDESCL5_BPP(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_BPP_SHIFT)) & LCDIFV2_CTRLDESCL5_BPP_MASK) |
#define | LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK (0x10000000U) |
#define | LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT (28U) |
#define | LCDIFV2_CTRLDESCL5_SAFETY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK) |
#define | LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK (0x40000000U) |
#define | LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT (30U) |
#define | LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK) |
#define | LCDIFV2_CTRLDESCL5_EN_MASK (0x80000000U) |
#define | LCDIFV2_CTRLDESCL5_EN_SHIFT (31U) |
#define | LCDIFV2_CTRLDESCL5_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_EN_MASK) |
CTRLDESCL6 - Control Descriptor Layer 6 Register | |
#define | LCDIFV2_CTRLDESCL6_BCLR_B_MASK (0xFFU) |
#define | LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT (0U) |
#define | LCDIFV2_CTRLDESCL6_BCLR_B(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_B_MASK) |
#define | LCDIFV2_CTRLDESCL6_BCLR_G_MASK (0xFF00U) |
#define | LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT (8U) |
#define | LCDIFV2_CTRLDESCL6_BCLR_G(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_G_MASK) |
#define | LCDIFV2_CTRLDESCL6_BCLR_R_MASK (0xFF0000U) |
#define | LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT (16U) |
#define | LCDIFV2_CTRLDESCL6_BCLR_R(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_R_MASK) |
CSC_COEF0 - Color Space Conversion Coefficient Register 0 | |
#define | LCDIFV2_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) |
#define | LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT (0U) |
#define | LCDIFV2_CSC_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_Y_OFFSET_MASK) |
#define | LCDIFV2_CSC_COEF0_UV_OFFSET_MASK (0x3FE00U) |
#define | LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT (9U) |
#define | LCDIFV2_CSC_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_UV_OFFSET_MASK) |
#define | LCDIFV2_CSC_COEF0_C0_MASK (0x1FFC0000U) |
#define | LCDIFV2_CSC_COEF0_C0_SHIFT (18U) |
#define | LCDIFV2_CSC_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_C0_SHIFT)) & LCDIFV2_CSC_COEF0_C0_MASK) |
#define | LCDIFV2_CSC_COEF0_ENABLE_MASK (0x40000000U) |
#define | LCDIFV2_CSC_COEF0_ENABLE_SHIFT (30U) |
#define | LCDIFV2_CSC_COEF0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_ENABLE_SHIFT)) & LCDIFV2_CSC_COEF0_ENABLE_MASK) |
#define | LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK (0x80000000U) |
#define | LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT (31U) |
#define | LCDIFV2_CSC_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT)) & LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK) |
CSC_COEF1 - Color Space Conversion Coefficient Register 1 | |
#define | LCDIFV2_CSC_COEF1_C4_MASK (0x7FFU) |
#define | LCDIFV2_CSC_COEF1_C4_SHIFT (0U) |
#define | LCDIFV2_CSC_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C4_SHIFT)) & LCDIFV2_CSC_COEF1_C4_MASK) |
#define | LCDIFV2_CSC_COEF1_C1_MASK (0x7FF0000U) |
#define | LCDIFV2_CSC_COEF1_C1_SHIFT (16U) |
#define | LCDIFV2_CSC_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C1_SHIFT)) & LCDIFV2_CSC_COEF1_C1_MASK) |
CSC_COEF2 - Color Space Conversion Coefficient Register 2 | |
#define | LCDIFV2_CSC_COEF2_C3_MASK (0x7FFU) |
#define | LCDIFV2_CSC_COEF2_C3_SHIFT (0U) |
#define | LCDIFV2_CSC_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C3_SHIFT)) & LCDIFV2_CSC_COEF2_C3_MASK) |
#define | LCDIFV2_CSC_COEF2_C2_MASK (0x7FF0000U) |
#define | LCDIFV2_CSC_COEF2_C2_SHIFT (16U) |
#define | LCDIFV2_CSC_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C2_SHIFT)) & LCDIFV2_CSC_COEF2_C2_MASK) |
CLUT_LOAD - LCDIFv2 CLUT load Register | |
#define | LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK (0x1U) |
#define | LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT (0U) |
#define | LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT)) & LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK) |
#define | LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK (0x70U) |
#define | LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT (4U) |
#define | LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT)) & LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK) |
PCCCR - PC bus Cache control register | |
#define | LMEM_PCCCR_ENCACHE_MASK (0x1U) |
#define | LMEM_PCCCR_ENCACHE_SHIFT (0U) |
#define | LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK) |
#define | LMEM_PCCCR_ENWRBUF_MASK (0x2U) |
#define | LMEM_PCCCR_ENWRBUF_SHIFT (1U) |
#define | LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK) |
#define | LMEM_PCCCR_PCCR2_MASK (0x4U) |
#define | LMEM_PCCCR_PCCR2_SHIFT (2U) |
#define | LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK) |
#define | LMEM_PCCCR_PCCR3_MASK (0x8U) |
#define | LMEM_PCCCR_PCCR3_SHIFT (3U) |
#define | LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK) |
#define | LMEM_PCCCR_INVW0_MASK (0x1000000U) |
#define | LMEM_PCCCR_INVW0_SHIFT (24U) |
#define | LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK) |
#define | LMEM_PCCCR_PUSHW0_MASK (0x2000000U) |
#define | LMEM_PCCCR_PUSHW0_SHIFT (25U) |
#define | LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK) |
#define | LMEM_PCCCR_INVW1_MASK (0x4000000U) |
#define | LMEM_PCCCR_INVW1_SHIFT (26U) |
#define | LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK) |
#define | LMEM_PCCCR_PUSHW1_MASK (0x8000000U) |
#define | LMEM_PCCCR_PUSHW1_SHIFT (27U) |
#define | LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK) |
#define | LMEM_PCCCR_GO_MASK (0x80000000U) |
#define | LMEM_PCCCR_GO_SHIFT (31U) |
#define | LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK) |
PCCLCR - PC bus Cache line control register | |
#define | LMEM_PCCLCR_LGO_MASK (0x1U) |
#define | LMEM_PCCLCR_LGO_SHIFT (0U) |
#define | LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK) |
#define | LMEM_PCCLCR_CACHEADDR_MASK (0x3FFCU) |
#define | LMEM_PCCLCR_CACHEADDR_SHIFT (2U) |
#define | LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK) |
#define | LMEM_PCCLCR_WSEL_MASK (0x4000U) |
#define | LMEM_PCCLCR_WSEL_SHIFT (14U) |
#define | LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK) |
#define | LMEM_PCCLCR_TDSEL_MASK (0x10000U) |
#define | LMEM_PCCLCR_TDSEL_SHIFT (16U) |
#define | LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK) |
#define | LMEM_PCCLCR_LCIVB_MASK (0x100000U) |
#define | LMEM_PCCLCR_LCIVB_SHIFT (20U) |
#define | LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK) |
#define | LMEM_PCCLCR_LCIMB_MASK (0x200000U) |
#define | LMEM_PCCLCR_LCIMB_SHIFT (21U) |
#define | LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK) |
#define | LMEM_PCCLCR_LCWAY_MASK (0x400000U) |
#define | LMEM_PCCLCR_LCWAY_SHIFT (22U) |
#define | LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK) |
#define | LMEM_PCCLCR_LCMD_MASK (0x3000000U) |
#define | LMEM_PCCLCR_LCMD_SHIFT (24U) |
#define | LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK) |
#define | LMEM_PCCLCR_LADSEL_MASK (0x4000000U) |
#define | LMEM_PCCLCR_LADSEL_SHIFT (26U) |
#define | LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK) |
#define | LMEM_PCCLCR_LACC_MASK (0x8000000U) |
#define | LMEM_PCCLCR_LACC_SHIFT (27U) |
#define | LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK) |
PCCSAR - PC bus Cache search address register | |
#define | LMEM_PCCSAR_LGO_MASK (0x1U) |
#define | LMEM_PCCSAR_LGO_SHIFT (0U) |
#define | LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK) |
#define | LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFEU) |
#define | LMEM_PCCSAR_PHYADDR_SHIFT (1U) |
#define | LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK) |
PCCCVR - PC bus Cache read/write value register | |
#define | LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU) |
#define | LMEM_PCCCVR_DATA_SHIFT (0U) |
#define | LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK) |
PSCCR - PS bus Cache control register | |
#define | LMEM_PSCCR_ENCACHE_MASK (0x1U) |
#define | LMEM_PSCCR_ENCACHE_SHIFT (0U) |
#define | LMEM_PSCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK) |
#define | LMEM_PSCCR_ENWRBUF_MASK (0x2U) |
#define | LMEM_PSCCR_ENWRBUF_SHIFT (1U) |
#define | LMEM_PSCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK) |
#define | LMEM_PSCCR_PSCR2_MASK (0x4U) |
#define | LMEM_PSCCR_PSCR2_SHIFT (2U) |
#define | LMEM_PSCCR_PSCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PSCR2_SHIFT)) & LMEM_PSCCR_PSCR2_MASK) |
#define | LMEM_PSCCR_PSCR3_MASK (0x8U) |
#define | LMEM_PSCCR_PSCR3_SHIFT (3U) |
#define | LMEM_PSCCR_PSCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PSCR3_SHIFT)) & LMEM_PSCCR_PSCR3_MASK) |
#define | LMEM_PSCCR_INVW0_MASK (0x1000000U) |
#define | LMEM_PSCCR_INVW0_SHIFT (24U) |
#define | LMEM_PSCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK) |
#define | LMEM_PSCCR_PUSHW0_MASK (0x2000000U) |
#define | LMEM_PSCCR_PUSHW0_SHIFT (25U) |
#define | LMEM_PSCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK) |
#define | LMEM_PSCCR_INVW1_MASK (0x4000000U) |
#define | LMEM_PSCCR_INVW1_SHIFT (26U) |
#define | LMEM_PSCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK) |
#define | LMEM_PSCCR_PUSHW1_MASK (0x8000000U) |
#define | LMEM_PSCCR_PUSHW1_SHIFT (27U) |
#define | LMEM_PSCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK) |
#define | LMEM_PSCCR_GO_MASK (0x80000000U) |
#define | LMEM_PSCCR_GO_SHIFT (31U) |
#define | LMEM_PSCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK) |
PSCLCR - PS bus Cache line control register | |
#define | LMEM_PSCLCR_LGO_MASK (0x1U) |
#define | LMEM_PSCLCR_LGO_SHIFT (0U) |
#define | LMEM_PSCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK) |
#define | LMEM_PSCLCR_CACHEADDR_MASK (0x3FFCU) |
#define | LMEM_PSCLCR_CACHEADDR_SHIFT (2U) |
#define | LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK) |
#define | LMEM_PSCLCR_WSEL_MASK (0x4000U) |
#define | LMEM_PSCLCR_WSEL_SHIFT (14U) |
#define | LMEM_PSCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK) |
#define | LMEM_PSCLCR_TDSEL_MASK (0x10000U) |
#define | LMEM_PSCLCR_TDSEL_SHIFT (16U) |
#define | LMEM_PSCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK) |
#define | LMEM_PSCLCR_LCIVB_MASK (0x100000U) |
#define | LMEM_PSCLCR_LCIVB_SHIFT (20U) |
#define | LMEM_PSCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK) |
#define | LMEM_PSCLCR_LCIMB_MASK (0x200000U) |
#define | LMEM_PSCLCR_LCIMB_SHIFT (21U) |
#define | LMEM_PSCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK) |
#define | LMEM_PSCLCR_LCWAY_MASK (0x400000U) |
#define | LMEM_PSCLCR_LCWAY_SHIFT (22U) |
#define | LMEM_PSCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK) |
#define | LMEM_PSCLCR_LCMD_MASK (0x3000000U) |
#define | LMEM_PSCLCR_LCMD_SHIFT (24U) |
#define | LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK) |
#define | LMEM_PSCLCR_LADSEL_MASK (0x4000000U) |
#define | LMEM_PSCLCR_LADSEL_SHIFT (26U) |
#define | LMEM_PSCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK) |
#define | LMEM_PSCLCR_LACC_MASK (0x8000000U) |
#define | LMEM_PSCLCR_LACC_SHIFT (27U) |
#define | LMEM_PSCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK) |
PSCSAR - PS bus Cache search address register | |
#define | LMEM_PSCSAR_LGO_MASK (0x1U) |
#define | LMEM_PSCSAR_LGO_SHIFT (0U) |
#define | LMEM_PSCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK) |
#define | LMEM_PSCSAR_PHYADDR_MASK (0xFFFFFFFEU) |
#define | LMEM_PSCSAR_PHYADDR_SHIFT (1U) |
#define | LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK) |
PSCCVR - PS bus Cache read/write value register | |
#define | LMEM_PSCCVR_DATA_MASK (0xFFFFFFFFU) |
#define | LMEM_PSCCVR_DATA_SHIFT (0U) |
#define | LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK) |
MCR - Master Control | |
#define | LPI2C_MCR_MEN_MASK (0x1U) |
#define | LPI2C_MCR_MEN_SHIFT (0U) |
#define | LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) |
#define | LPI2C_MCR_RST_MASK (0x2U) |
#define | LPI2C_MCR_RST_SHIFT (1U) |
#define | LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) |
#define | LPI2C_MCR_DOZEN_MASK (0x4U) |
#define | LPI2C_MCR_DOZEN_SHIFT (2U) |
#define | LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) |
#define | LPI2C_MCR_DBGEN_MASK (0x8U) |
#define | LPI2C_MCR_DBGEN_SHIFT (3U) |
#define | LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) |
#define | LPI2C_MCR_RTF_MASK (0x100U) |
#define | LPI2C_MCR_RTF_SHIFT (8U) |
#define | LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) |
#define | LPI2C_MCR_RRF_MASK (0x200U) |
#define | LPI2C_MCR_RRF_SHIFT (9U) |
#define | LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) |
MSR - Master Status | |
#define | LPI2C_MSR_TDF_MASK (0x1U) |
#define | LPI2C_MSR_TDF_SHIFT (0U) |
#define | LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) |
#define | LPI2C_MSR_RDF_MASK (0x2U) |
#define | LPI2C_MSR_RDF_SHIFT (1U) |
#define | LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) |
#define | LPI2C_MSR_EPF_MASK (0x100U) |
#define | LPI2C_MSR_EPF_SHIFT (8U) |
#define | LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) |
#define | LPI2C_MSR_SDF_MASK (0x200U) |
#define | LPI2C_MSR_SDF_SHIFT (9U) |
#define | LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) |
#define | LPI2C_MSR_NDF_MASK (0x400U) |
#define | LPI2C_MSR_NDF_SHIFT (10U) |
#define | LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) |
#define | LPI2C_MSR_ALF_MASK (0x800U) |
#define | LPI2C_MSR_ALF_SHIFT (11U) |
#define | LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) |
#define | LPI2C_MSR_FEF_MASK (0x1000U) |
#define | LPI2C_MSR_FEF_SHIFT (12U) |
#define | LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) |
#define | LPI2C_MSR_PLTF_MASK (0x2000U) |
#define | LPI2C_MSR_PLTF_SHIFT (13U) |
#define | LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) |
#define | LPI2C_MSR_DMF_MASK (0x4000U) |
#define | LPI2C_MSR_DMF_SHIFT (14U) |
#define | LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) |
#define | LPI2C_MSR_MBF_MASK (0x1000000U) |
#define | LPI2C_MSR_MBF_SHIFT (24U) |
#define | LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) |
#define | LPI2C_MSR_BBF_MASK (0x2000000U) |
#define | LPI2C_MSR_BBF_SHIFT (25U) |
#define | LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) |
MIER - Master Interrupt Enable | |
#define | LPI2C_MIER_TDIE_MASK (0x1U) |
#define | LPI2C_MIER_TDIE_SHIFT (0U) |
#define | LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) |
#define | LPI2C_MIER_RDIE_MASK (0x2U) |
#define | LPI2C_MIER_RDIE_SHIFT (1U) |
#define | LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) |
#define | LPI2C_MIER_EPIE_MASK (0x100U) |
#define | LPI2C_MIER_EPIE_SHIFT (8U) |
#define | LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) |
#define | LPI2C_MIER_SDIE_MASK (0x200U) |
#define | LPI2C_MIER_SDIE_SHIFT (9U) |
#define | LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) |
#define | LPI2C_MIER_NDIE_MASK (0x400U) |
#define | LPI2C_MIER_NDIE_SHIFT (10U) |
#define | LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) |
#define | LPI2C_MIER_ALIE_MASK (0x800U) |
#define | LPI2C_MIER_ALIE_SHIFT (11U) |
#define | LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) |
#define | LPI2C_MIER_FEIE_MASK (0x1000U) |
#define | LPI2C_MIER_FEIE_SHIFT (12U) |
#define | LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) |
#define | LPI2C_MIER_PLTIE_MASK (0x2000U) |
#define | LPI2C_MIER_PLTIE_SHIFT (13U) |
#define | LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) |
#define | LPI2C_MIER_DMIE_MASK (0x4000U) |
#define | LPI2C_MIER_DMIE_SHIFT (14U) |
#define | LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) |
MDER - Master DMA Enable | |
#define | LPI2C_MDER_TDDE_MASK (0x1U) |
#define | LPI2C_MDER_TDDE_SHIFT (0U) |
#define | LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) |
#define | LPI2C_MDER_RDDE_MASK (0x2U) |
#define | LPI2C_MDER_RDDE_SHIFT (1U) |
#define | LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) |
MCFGR0 - Master Configuration 0 | |
#define | LPI2C_MCFGR0_HREN_MASK (0x1U) |
#define | LPI2C_MCFGR0_HREN_SHIFT (0U) |
#define | LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) |
#define | LPI2C_MCFGR0_HRPOL_MASK (0x2U) |
#define | LPI2C_MCFGR0_HRPOL_SHIFT (1U) |
#define | LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) |
#define | LPI2C_MCFGR0_HRSEL_MASK (0x4U) |
#define | LPI2C_MCFGR0_HRSEL_SHIFT (2U) |
#define | LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) |
#define | LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) |
#define | LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) |
#define | LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) |
#define | LPI2C_MCFGR0_RDMO_MASK (0x200U) |
#define | LPI2C_MCFGR0_RDMO_SHIFT (9U) |
#define | LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) |
MCFGR1 - Master Configuration 1 | |
#define | LPI2C_MCFGR1_PRESCALE_MASK (0x7U) |
#define | LPI2C_MCFGR1_PRESCALE_SHIFT (0U) |
#define | LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) |
#define | LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) |
#define | LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) |
#define | LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) |
#define | LPI2C_MCFGR1_IGNACK_MASK (0x200U) |
#define | LPI2C_MCFGR1_IGNACK_SHIFT (9U) |
#define | LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) |
#define | LPI2C_MCFGR1_TIMECFG_MASK (0x400U) |
#define | LPI2C_MCFGR1_TIMECFG_SHIFT (10U) |
#define | LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) |
#define | LPI2C_MCFGR1_MATCFG_MASK (0x70000U) |
#define | LPI2C_MCFGR1_MATCFG_SHIFT (16U) |
#define | LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) |
#define | LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) |
#define | LPI2C_MCFGR1_PINCFG_SHIFT (24U) |
#define | LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) |
MCFGR2 - Master Configuration 2 | |
#define | LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) |
#define | LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) |
#define | LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) |
#define | LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) |
#define | LPI2C_MCFGR2_FILTSCL_SHIFT (16U) |
#define | LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) |
#define | LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) |
#define | LPI2C_MCFGR2_FILTSDA_SHIFT (24U) |
#define | LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) |
MCFGR3 - Master Configuration 3 | |
#define | LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) |
#define | LPI2C_MCFGR3_PINLOW_SHIFT (8U) |
#define | LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) |
MDMR - Master Data Match | |
#define | LPI2C_MDMR_MATCH0_MASK (0xFFU) |
#define | LPI2C_MDMR_MATCH0_SHIFT (0U) |
#define | LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) |
#define | LPI2C_MDMR_MATCH1_MASK (0xFF0000U) |
#define | LPI2C_MDMR_MATCH1_SHIFT (16U) |
#define | LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) |
MCCR0 - Master Clock Configuration 0 | |
#define | LPI2C_MCCR0_CLKLO_MASK (0x3FU) |
#define | LPI2C_MCCR0_CLKLO_SHIFT (0U) |
#define | LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) |
#define | LPI2C_MCCR0_CLKHI_MASK (0x3F00U) |
#define | LPI2C_MCCR0_CLKHI_SHIFT (8U) |
#define | LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) |
#define | LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) |
#define | LPI2C_MCCR0_SETHOLD_SHIFT (16U) |
#define | LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) |
#define | LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) |
#define | LPI2C_MCCR0_DATAVD_SHIFT (24U) |
#define | LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) |
MCCR1 - Master Clock Configuration 1 | |
#define | LPI2C_MCCR1_CLKLO_MASK (0x3FU) |
#define | LPI2C_MCCR1_CLKLO_SHIFT (0U) |
#define | LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) |
#define | LPI2C_MCCR1_CLKHI_MASK (0x3F00U) |
#define | LPI2C_MCCR1_CLKHI_SHIFT (8U) |
#define | LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) |
#define | LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) |
#define | LPI2C_MCCR1_SETHOLD_SHIFT (16U) |
#define | LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) |
#define | LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) |
#define | LPI2C_MCCR1_DATAVD_SHIFT (24U) |
#define | LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) |
MFCR - Master FIFO Control | |
#define | LPI2C_MFCR_TXWATER_MASK (0x3U) |
#define | LPI2C_MFCR_TXWATER_SHIFT (0U) |
#define | LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) |
#define | LPI2C_MFCR_RXWATER_MASK (0x30000U) |
#define | LPI2C_MFCR_RXWATER_SHIFT (16U) |
#define | LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) |
MFSR - Master FIFO Status | |
#define | LPI2C_MFSR_TXCOUNT_MASK (0x7U) |
#define | LPI2C_MFSR_TXCOUNT_SHIFT (0U) |
#define | LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) |
#define | LPI2C_MFSR_RXCOUNT_MASK (0x70000U) |
#define | LPI2C_MFSR_RXCOUNT_SHIFT (16U) |
#define | LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) |
MTDR - Master Transmit Data | |
#define | LPI2C_MTDR_DATA_MASK (0xFFU) |
#define | LPI2C_MTDR_DATA_SHIFT (0U) |
#define | LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) |
#define | LPI2C_MTDR_CMD_MASK (0x700U) |
#define | LPI2C_MTDR_CMD_SHIFT (8U) |
#define | LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) |
MRDR - Master Receive Data | |
#define | LPI2C_MRDR_DATA_MASK (0xFFU) |
#define | LPI2C_MRDR_DATA_SHIFT (0U) |
#define | LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) |
#define | LPI2C_MRDR_RXEMPTY_MASK (0x4000U) |
#define | LPI2C_MRDR_RXEMPTY_SHIFT (14U) |
#define | LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) |
SCR - Slave Control | |
#define | LPI2C_SCR_SEN_MASK (0x1U) |
#define | LPI2C_SCR_SEN_SHIFT (0U) |
#define | LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) |
#define | LPI2C_SCR_RST_MASK (0x2U) |
#define | LPI2C_SCR_RST_SHIFT (1U) |
#define | LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) |
#define | LPI2C_SCR_FILTEN_MASK (0x10U) |
#define | LPI2C_SCR_FILTEN_SHIFT (4U) |
#define | LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) |
#define | LPI2C_SCR_FILTDZ_MASK (0x20U) |
#define | LPI2C_SCR_FILTDZ_SHIFT (5U) |
#define | LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) |
#define | LPI2C_SCR_RTF_MASK (0x100U) |
#define | LPI2C_SCR_RTF_SHIFT (8U) |
#define | LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) |
#define | LPI2C_SCR_RRF_MASK (0x200U) |
#define | LPI2C_SCR_RRF_SHIFT (9U) |
#define | LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) |
SSR - Slave Status | |
#define | LPI2C_SSR_TDF_MASK (0x1U) |
#define | LPI2C_SSR_TDF_SHIFT (0U) |
#define | LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) |
#define | LPI2C_SSR_RDF_MASK (0x2U) |
#define | LPI2C_SSR_RDF_SHIFT (1U) |
#define | LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) |
#define | LPI2C_SSR_AVF_MASK (0x4U) |
#define | LPI2C_SSR_AVF_SHIFT (2U) |
#define | LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) |
#define | LPI2C_SSR_TAF_MASK (0x8U) |
#define | LPI2C_SSR_TAF_SHIFT (3U) |
#define | LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) |
#define | LPI2C_SSR_RSF_MASK (0x100U) |
#define | LPI2C_SSR_RSF_SHIFT (8U) |
#define | LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) |
#define | LPI2C_SSR_SDF_MASK (0x200U) |
#define | LPI2C_SSR_SDF_SHIFT (9U) |
#define | LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) |
#define | LPI2C_SSR_BEF_MASK (0x400U) |
#define | LPI2C_SSR_BEF_SHIFT (10U) |
#define | LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) |
#define | LPI2C_SSR_FEF_MASK (0x800U) |
#define | LPI2C_SSR_FEF_SHIFT (11U) |
#define | LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) |
#define | LPI2C_SSR_AM0F_MASK (0x1000U) |
#define | LPI2C_SSR_AM0F_SHIFT (12U) |
#define | LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) |
#define | LPI2C_SSR_AM1F_MASK (0x2000U) |
#define | LPI2C_SSR_AM1F_SHIFT (13U) |
#define | LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) |
#define | LPI2C_SSR_GCF_MASK (0x4000U) |
#define | LPI2C_SSR_GCF_SHIFT (14U) |
#define | LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) |
#define | LPI2C_SSR_SARF_MASK (0x8000U) |
#define | LPI2C_SSR_SARF_SHIFT (15U) |
#define | LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) |
#define | LPI2C_SSR_SBF_MASK (0x1000000U) |
#define | LPI2C_SSR_SBF_SHIFT (24U) |
#define | LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) |
#define | LPI2C_SSR_BBF_MASK (0x2000000U) |
#define | LPI2C_SSR_BBF_SHIFT (25U) |
#define | LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) |
SIER - Slave Interrupt Enable | |
#define | LPI2C_SIER_TDIE_MASK (0x1U) |
#define | LPI2C_SIER_TDIE_SHIFT (0U) |
#define | LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) |
#define | LPI2C_SIER_RDIE_MASK (0x2U) |
#define | LPI2C_SIER_RDIE_SHIFT (1U) |
#define | LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) |
#define | LPI2C_SIER_AVIE_MASK (0x4U) |
#define | LPI2C_SIER_AVIE_SHIFT (2U) |
#define | LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) |
#define | LPI2C_SIER_TAIE_MASK (0x8U) |
#define | LPI2C_SIER_TAIE_SHIFT (3U) |
#define | LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) |
#define | LPI2C_SIER_RSIE_MASK (0x100U) |
#define | LPI2C_SIER_RSIE_SHIFT (8U) |
#define | LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) |
#define | LPI2C_SIER_SDIE_MASK (0x200U) |
#define | LPI2C_SIER_SDIE_SHIFT (9U) |
#define | LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) |
#define | LPI2C_SIER_BEIE_MASK (0x400U) |
#define | LPI2C_SIER_BEIE_SHIFT (10U) |
#define | LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) |
#define | LPI2C_SIER_FEIE_MASK (0x800U) |
#define | LPI2C_SIER_FEIE_SHIFT (11U) |
#define | LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) |
#define | LPI2C_SIER_AM0IE_MASK (0x1000U) |
#define | LPI2C_SIER_AM0IE_SHIFT (12U) |
#define | LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) |
#define | LPI2C_SIER_AM1IE_MASK (0x2000U) |
#define | LPI2C_SIER_AM1IE_SHIFT (13U) |
#define | LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) |
#define | LPI2C_SIER_GCIE_MASK (0x4000U) |
#define | LPI2C_SIER_GCIE_SHIFT (14U) |
#define | LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) |
#define | LPI2C_SIER_SARIE_MASK (0x8000U) |
#define | LPI2C_SIER_SARIE_SHIFT (15U) |
#define | LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) |
SDER - Slave DMA Enable | |
#define | LPI2C_SDER_TDDE_MASK (0x1U) |
#define | LPI2C_SDER_TDDE_SHIFT (0U) |
#define | LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) |
#define | LPI2C_SDER_RDDE_MASK (0x2U) |
#define | LPI2C_SDER_RDDE_SHIFT (1U) |
#define | LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) |
#define | LPI2C_SDER_AVDE_MASK (0x4U) |
#define | LPI2C_SDER_AVDE_SHIFT (2U) |
#define | LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) |
SCFGR1 - Slave Configuration 1 | |
#define | LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) |
#define | LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) |
#define | LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) |
#define | LPI2C_SCFGR1_RXSTALL_MASK (0x2U) |
#define | LPI2C_SCFGR1_RXSTALL_SHIFT (1U) |
#define | LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) |
#define | LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) |
#define | LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) |
#define | LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) |
#define | LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) |
#define | LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) |
#define | LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) |
#define | LPI2C_SCFGR1_GCEN_MASK (0x100U) |
#define | LPI2C_SCFGR1_GCEN_SHIFT (8U) |
#define | LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) |
#define | LPI2C_SCFGR1_SAEN_MASK (0x200U) |
#define | LPI2C_SCFGR1_SAEN_SHIFT (9U) |
#define | LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) |
#define | LPI2C_SCFGR1_TXCFG_MASK (0x400U) |
#define | LPI2C_SCFGR1_TXCFG_SHIFT (10U) |
#define | LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) |
#define | LPI2C_SCFGR1_RXCFG_MASK (0x800U) |
#define | LPI2C_SCFGR1_RXCFG_SHIFT (11U) |
#define | LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) |
#define | LPI2C_SCFGR1_IGNACK_MASK (0x1000U) |
#define | LPI2C_SCFGR1_IGNACK_SHIFT (12U) |
#define | LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) |
#define | LPI2C_SCFGR1_HSMEN_MASK (0x2000U) |
#define | LPI2C_SCFGR1_HSMEN_SHIFT (13U) |
#define | LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) |
#define | LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) |
#define | LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) |
#define | LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) |
SCFGR2 - Slave Configuration 2 | |
#define | LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) |
#define | LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) |
#define | LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) |
#define | LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) |
#define | LPI2C_SCFGR2_DATAVD_SHIFT (8U) |
#define | LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) |
#define | LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) |
#define | LPI2C_SCFGR2_FILTSCL_SHIFT (16U) |
#define | LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) |
#define | LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) |
#define | LPI2C_SCFGR2_FILTSDA_SHIFT (24U) |
#define | LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) |
SAMR - Slave Address Match | |
#define | LPI2C_SAMR_ADDR0_MASK (0x7FEU) |
#define | LPI2C_SAMR_ADDR0_SHIFT (1U) |
#define | LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) |
#define | LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) |
#define | LPI2C_SAMR_ADDR1_SHIFT (17U) |
#define | LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) |
SASR - Slave Address Status | |
#define | LPI2C_SASR_RADDR_MASK (0x7FFU) |
#define | LPI2C_SASR_RADDR_SHIFT (0U) |
#define | LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) |
#define | LPI2C_SASR_ANV_MASK (0x4000U) |
#define | LPI2C_SASR_ANV_SHIFT (14U) |
#define | LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) |
STAR - Slave Transmit ACK | |
#define | LPI2C_STAR_TXNACK_MASK (0x1U) |
#define | LPI2C_STAR_TXNACK_SHIFT (0U) |
#define | LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) |
STDR - Slave Transmit Data | |
#define | LPI2C_STDR_DATA_MASK (0xFFU) |
#define | LPI2C_STDR_DATA_SHIFT (0U) |
#define | LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) |
SRDR - Slave Receive Data | |
#define | LPI2C_SRDR_DATA_MASK (0xFFU) |
#define | LPI2C_SRDR_DATA_SHIFT (0U) |
#define | LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) |
#define | LPI2C_SRDR_RXEMPTY_MASK (0x4000U) |
#define | LPI2C_SRDR_RXEMPTY_SHIFT (14U) |
#define | LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) |
#define | LPI2C_SRDR_SOF_MASK (0x8000U) |
#define | LPI2C_SRDR_SOF_SHIFT (15U) |
#define | LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) |
SR - Status | |
#define | LPSPI_SR_TDF_MASK (0x1U) |
#define | LPSPI_SR_TDF_SHIFT (0U) |
#define | LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) |
#define | LPSPI_SR_RDF_MASK (0x2U) |
#define | LPSPI_SR_RDF_SHIFT (1U) |
#define | LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) |
#define | LPSPI_SR_WCF_MASK (0x100U) |
#define | LPSPI_SR_WCF_SHIFT (8U) |
#define | LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) |
#define | LPSPI_SR_FCF_MASK (0x200U) |
#define | LPSPI_SR_FCF_SHIFT (9U) |
#define | LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) |
#define | LPSPI_SR_TCF_MASK (0x400U) |
#define | LPSPI_SR_TCF_SHIFT (10U) |
#define | LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) |
#define | LPSPI_SR_TEF_MASK (0x800U) |
#define | LPSPI_SR_TEF_SHIFT (11U) |
#define | LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) |
#define | LPSPI_SR_REF_MASK (0x1000U) |
#define | LPSPI_SR_REF_SHIFT (12U) |
#define | LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) |
#define | LPSPI_SR_DMF_MASK (0x2000U) |
#define | LPSPI_SR_DMF_SHIFT (13U) |
#define | LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) |
#define | LPSPI_SR_MBF_MASK (0x1000000U) |
#define | LPSPI_SR_MBF_SHIFT (24U) |
#define | LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) |
IER - Interrupt Enable | |
#define | LPSPI_IER_TDIE_MASK (0x1U) |
#define | LPSPI_IER_TDIE_SHIFT (0U) |
#define | LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) |
#define | LPSPI_IER_RDIE_MASK (0x2U) |
#define | LPSPI_IER_RDIE_SHIFT (1U) |
#define | LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) |
#define | LPSPI_IER_WCIE_MASK (0x100U) |
#define | LPSPI_IER_WCIE_SHIFT (8U) |
#define | LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) |
#define | LPSPI_IER_FCIE_MASK (0x200U) |
#define | LPSPI_IER_FCIE_SHIFT (9U) |
#define | LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) |
#define | LPSPI_IER_TCIE_MASK (0x400U) |
#define | LPSPI_IER_TCIE_SHIFT (10U) |
#define | LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) |
#define | LPSPI_IER_TEIE_MASK (0x800U) |
#define | LPSPI_IER_TEIE_SHIFT (11U) |
#define | LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) |
#define | LPSPI_IER_REIE_MASK (0x1000U) |
#define | LPSPI_IER_REIE_SHIFT (12U) |
#define | LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) |
#define | LPSPI_IER_DMIE_MASK (0x2000U) |
#define | LPSPI_IER_DMIE_SHIFT (13U) |
#define | LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) |
DER - DMA Enable | |
#define | LPSPI_DER_TDDE_MASK (0x1U) |
#define | LPSPI_DER_TDDE_SHIFT (0U) |
#define | LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) |
#define | LPSPI_DER_RDDE_MASK (0x2U) |
#define | LPSPI_DER_RDDE_SHIFT (1U) |
#define | LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) |
CFGR0 - Configuration 0 | |
#define | LPSPI_CFGR0_CIRFIFO_MASK (0x100U) |
#define | LPSPI_CFGR0_CIRFIFO_SHIFT (8U) |
#define | LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) |
#define | LPSPI_CFGR0_RDMO_MASK (0x200U) |
#define | LPSPI_CFGR0_RDMO_SHIFT (9U) |
#define | LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) |
CFGR1 - Configuration 1 | |
#define | LPSPI_CFGR1_MASTER_MASK (0x1U) |
#define | LPSPI_CFGR1_MASTER_SHIFT (0U) |
#define | LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) |
#define | LPSPI_CFGR1_SAMPLE_MASK (0x2U) |
#define | LPSPI_CFGR1_SAMPLE_SHIFT (1U) |
#define | LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) |
#define | LPSPI_CFGR1_AUTOPCS_MASK (0x4U) |
#define | LPSPI_CFGR1_AUTOPCS_SHIFT (2U) |
#define | LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) |
#define | LPSPI_CFGR1_NOSTALL_MASK (0x8U) |
#define | LPSPI_CFGR1_NOSTALL_SHIFT (3U) |
#define | LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) |
#define | LPSPI_CFGR1_PCSPOL_MASK (0xF00U) |
#define | LPSPI_CFGR1_PCSPOL_SHIFT (8U) |
#define | LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) |
#define | LPSPI_CFGR1_MATCFG_MASK (0x70000U) |
#define | LPSPI_CFGR1_MATCFG_SHIFT (16U) |
#define | LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) |
#define | LPSPI_CFGR1_PINCFG_MASK (0x3000000U) |
#define | LPSPI_CFGR1_PINCFG_SHIFT (24U) |
#define | LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) |
#define | LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) |
#define | LPSPI_CFGR1_OUTCFG_SHIFT (26U) |
#define | LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) |
#define | LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) |
#define | LPSPI_CFGR1_PCSCFG_SHIFT (27U) |
#define | LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) |
DMR0 - Data Match 0 | |
#define | LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) |
#define | LPSPI_DMR0_MATCH0_SHIFT (0U) |
#define | LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) |
DMR1 - Data Match 1 | |
#define | LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) |
#define | LPSPI_DMR1_MATCH1_SHIFT (0U) |
#define | LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) |
CCR - Clock Configuration | |
#define | LPSPI_CCR_SCKDIV_MASK (0xFFU) |
#define | LPSPI_CCR_SCKDIV_SHIFT (0U) |
#define | LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) |
#define | LPSPI_CCR_DBT_MASK (0xFF00U) |
#define | LPSPI_CCR_DBT_SHIFT (8U) |
#define | LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) |
#define | LPSPI_CCR_PCSSCK_MASK (0xFF0000U) |
#define | LPSPI_CCR_PCSSCK_SHIFT (16U) |
#define | LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) |
#define | LPSPI_CCR_SCKPCS_MASK (0xFF000000U) |
#define | LPSPI_CCR_SCKPCS_SHIFT (24U) |
#define | LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) |
FCR - FIFO Control | |
#define | LPSPI_FCR_TXWATER_MASK (0xFU) |
#define | LPSPI_FCR_TXWATER_SHIFT (0U) |
#define | LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) |
#define | LPSPI_FCR_RXWATER_MASK (0xF0000U) |
#define | LPSPI_FCR_RXWATER_SHIFT (16U) |
#define | LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) |
FSR - FIFO Status | |
#define | LPSPI_FSR_TXCOUNT_MASK (0x1FU) |
#define | LPSPI_FSR_TXCOUNT_SHIFT (0U) |
#define | LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) |
#define | LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) |
#define | LPSPI_FSR_RXCOUNT_SHIFT (16U) |
#define | LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) |
TCR - Transmit Command | |
#define | LPSPI_TCR_FRAMESZ_MASK (0xFFFU) |
#define | LPSPI_TCR_FRAMESZ_SHIFT (0U) |
#define | LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) |
#define | LPSPI_TCR_WIDTH_MASK (0x30000U) |
#define | LPSPI_TCR_WIDTH_SHIFT (16U) |
#define | LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) |
#define | LPSPI_TCR_TXMSK_MASK (0x40000U) |
#define | LPSPI_TCR_TXMSK_SHIFT (18U) |
#define | LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) |
#define | LPSPI_TCR_RXMSK_MASK (0x80000U) |
#define | LPSPI_TCR_RXMSK_SHIFT (19U) |
#define | LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) |
#define | LPSPI_TCR_CONTC_MASK (0x100000U) |
#define | LPSPI_TCR_CONTC_SHIFT (20U) |
#define | LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) |
#define | LPSPI_TCR_CONT_MASK (0x200000U) |
#define | LPSPI_TCR_CONT_SHIFT (21U) |
#define | LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) |
#define | LPSPI_TCR_BYSW_MASK (0x400000U) |
#define | LPSPI_TCR_BYSW_SHIFT (22U) |
#define | LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) |
#define | LPSPI_TCR_LSBF_MASK (0x800000U) |
#define | LPSPI_TCR_LSBF_SHIFT (23U) |
#define | LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) |
#define | LPSPI_TCR_PCS_MASK (0x3000000U) |
#define | LPSPI_TCR_PCS_SHIFT (24U) |
#define | LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) |
#define | LPSPI_TCR_PRESCALE_MASK (0x38000000U) |
#define | LPSPI_TCR_PRESCALE_SHIFT (27U) |
#define | LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) |
#define | LPSPI_TCR_CPHA_MASK (0x40000000U) |
#define | LPSPI_TCR_CPHA_SHIFT (30U) |
#define | LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) |
#define | LPSPI_TCR_CPOL_MASK (0x80000000U) |
#define | LPSPI_TCR_CPOL_SHIFT (31U) |
#define | LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) |
RSR - Receive Status | |
#define | LPSPI_RSR_SOF_MASK (0x1U) |
#define | LPSPI_RSR_SOF_SHIFT (0U) |
#define | LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) |
#define | LPSPI_RSR_RXEMPTY_MASK (0x2U) |
#define | LPSPI_RSR_RXEMPTY_SHIFT (1U) |
#define | LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) |
GLOBAL - LPUART Global Register | |
#define | LPUART_GLOBAL_RST_MASK (0x2U) |
#define | LPUART_GLOBAL_RST_SHIFT (1U) |
#define | LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) |
PINCFG - LPUART Pin Configuration Register | |
#define | LPUART_PINCFG_TRGSEL_MASK (0x3U) |
#define | LPUART_PINCFG_TRGSEL_SHIFT (0U) |
#define | LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) |
BAUD - LPUART Baud Rate Register | |
#define | LPUART_BAUD_SBR_MASK (0x1FFFU) |
#define | LPUART_BAUD_SBR_SHIFT (0U) |
#define | LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) |
#define | LPUART_BAUD_SBNS_MASK (0x2000U) |
#define | LPUART_BAUD_SBNS_SHIFT (13U) |
#define | LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) |
#define | LPUART_BAUD_RXEDGIE_MASK (0x4000U) |
#define | LPUART_BAUD_RXEDGIE_SHIFT (14U) |
#define | LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) |
#define | LPUART_BAUD_LBKDIE_MASK (0x8000U) |
#define | LPUART_BAUD_LBKDIE_SHIFT (15U) |
#define | LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) |
#define | LPUART_BAUD_RESYNCDIS_MASK (0x10000U) |
#define | LPUART_BAUD_RESYNCDIS_SHIFT (16U) |
#define | LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) |
#define | LPUART_BAUD_BOTHEDGE_MASK (0x20000U) |
#define | LPUART_BAUD_BOTHEDGE_SHIFT (17U) |
#define | LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) |
#define | LPUART_BAUD_MATCFG_MASK (0xC0000U) |
#define | LPUART_BAUD_MATCFG_SHIFT (18U) |
#define | LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) |
#define | LPUART_BAUD_RDMAE_MASK (0x200000U) |
#define | LPUART_BAUD_RDMAE_SHIFT (21U) |
#define | LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) |
#define | LPUART_BAUD_TDMAE_MASK (0x800000U) |
#define | LPUART_BAUD_TDMAE_SHIFT (23U) |
#define | LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) |
#define | LPUART_BAUD_OSR_MASK (0x1F000000U) |
#define | LPUART_BAUD_OSR_SHIFT (24U) |
#define | LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) |
#define | LPUART_BAUD_M10_MASK (0x20000000U) |
#define | LPUART_BAUD_M10_SHIFT (29U) |
#define | LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) |
#define | LPUART_BAUD_MAEN2_MASK (0x40000000U) |
#define | LPUART_BAUD_MAEN2_SHIFT (30U) |
#define | LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) |
#define | LPUART_BAUD_MAEN1_MASK (0x80000000U) |
#define | LPUART_BAUD_MAEN1_SHIFT (31U) |
#define | LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) |
STAT - LPUART Status Register | |
#define | LPUART_STAT_MA2F_MASK (0x4000U) |
#define | LPUART_STAT_MA2F_SHIFT (14U) |
#define | LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) |
#define | LPUART_STAT_MA1F_MASK (0x8000U) |
#define | LPUART_STAT_MA1F_SHIFT (15U) |
#define | LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) |
#define | LPUART_STAT_PF_MASK (0x10000U) |
#define | LPUART_STAT_PF_SHIFT (16U) |
#define | LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) |
#define | LPUART_STAT_FE_MASK (0x20000U) |
#define | LPUART_STAT_FE_SHIFT (17U) |
#define | LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) |
#define | LPUART_STAT_NF_MASK (0x40000U) |
#define | LPUART_STAT_NF_SHIFT (18U) |
#define | LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) |
#define | LPUART_STAT_OR_MASK (0x80000U) |
#define | LPUART_STAT_OR_SHIFT (19U) |
#define | LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) |
#define | LPUART_STAT_IDLE_MASK (0x100000U) |
#define | LPUART_STAT_IDLE_SHIFT (20U) |
#define | LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) |
#define | LPUART_STAT_RDRF_MASK (0x200000U) |
#define | LPUART_STAT_RDRF_SHIFT (21U) |
#define | LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) |
#define | LPUART_STAT_TC_MASK (0x400000U) |
#define | LPUART_STAT_TC_SHIFT (22U) |
#define | LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) |
#define | LPUART_STAT_TDRE_MASK (0x800000U) |
#define | LPUART_STAT_TDRE_SHIFT (23U) |
#define | LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) |
#define | LPUART_STAT_RAF_MASK (0x1000000U) |
#define | LPUART_STAT_RAF_SHIFT (24U) |
#define | LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) |
#define | LPUART_STAT_LBKDE_MASK (0x2000000U) |
#define | LPUART_STAT_LBKDE_SHIFT (25U) |
#define | LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) |
#define | LPUART_STAT_BRK13_MASK (0x4000000U) |
#define | LPUART_STAT_BRK13_SHIFT (26U) |
#define | LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) |
#define | LPUART_STAT_RWUID_MASK (0x8000000U) |
#define | LPUART_STAT_RWUID_SHIFT (27U) |
#define | LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) |
#define | LPUART_STAT_RXINV_MASK (0x10000000U) |
#define | LPUART_STAT_RXINV_SHIFT (28U) |
#define | LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) |
#define | LPUART_STAT_MSBF_MASK (0x20000000U) |
#define | LPUART_STAT_MSBF_SHIFT (29U) |
#define | LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) |
#define | LPUART_STAT_RXEDGIF_MASK (0x40000000U) |
#define | LPUART_STAT_RXEDGIF_SHIFT (30U) |
#define | LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) |
#define | LPUART_STAT_LBKDIF_MASK (0x80000000U) |
#define | LPUART_STAT_LBKDIF_SHIFT (31U) |
#define | LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) |
CTRL - LPUART Control Register | |
#define | LPUART_CTRL_PT_MASK (0x1U) |
#define | LPUART_CTRL_PT_SHIFT (0U) |
#define | LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) |
#define | LPUART_CTRL_PE_MASK (0x2U) |
#define | LPUART_CTRL_PE_SHIFT (1U) |
#define | LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) |
#define | LPUART_CTRL_ILT_MASK (0x4U) |
#define | LPUART_CTRL_ILT_SHIFT (2U) |
#define | LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) |
#define | LPUART_CTRL_WAKE_MASK (0x8U) |
#define | LPUART_CTRL_WAKE_SHIFT (3U) |
#define | LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) |
#define | LPUART_CTRL_M_MASK (0x10U) |
#define | LPUART_CTRL_M_SHIFT (4U) |
#define | LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) |
#define | LPUART_CTRL_RSRC_MASK (0x20U) |
#define | LPUART_CTRL_RSRC_SHIFT (5U) |
#define | LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) |
#define | LPUART_CTRL_DOZEEN_MASK (0x40U) |
#define | LPUART_CTRL_DOZEEN_SHIFT (6U) |
#define | LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) |
#define | LPUART_CTRL_LOOPS_MASK (0x80U) |
#define | LPUART_CTRL_LOOPS_SHIFT (7U) |
#define | LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) |
#define | LPUART_CTRL_IDLECFG_MASK (0x700U) |
#define | LPUART_CTRL_IDLECFG_SHIFT (8U) |
#define | LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) |
#define | LPUART_CTRL_M7_MASK (0x800U) |
#define | LPUART_CTRL_M7_SHIFT (11U) |
#define | LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) |
#define | LPUART_CTRL_MA2IE_MASK (0x4000U) |
#define | LPUART_CTRL_MA2IE_SHIFT (14U) |
#define | LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) |
#define | LPUART_CTRL_MA1IE_MASK (0x8000U) |
#define | LPUART_CTRL_MA1IE_SHIFT (15U) |
#define | LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) |
#define | LPUART_CTRL_SBK_MASK (0x10000U) |
#define | LPUART_CTRL_SBK_SHIFT (16U) |
#define | LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) |
#define | LPUART_CTRL_RWU_MASK (0x20000U) |
#define | LPUART_CTRL_RWU_SHIFT (17U) |
#define | LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) |
#define | LPUART_CTRL_RE_MASK (0x40000U) |
#define | LPUART_CTRL_RE_SHIFT (18U) |
#define | LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) |
#define | LPUART_CTRL_TE_MASK (0x80000U) |
#define | LPUART_CTRL_TE_SHIFT (19U) |
#define | LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) |
#define | LPUART_CTRL_ILIE_MASK (0x100000U) |
#define | LPUART_CTRL_ILIE_SHIFT (20U) |
#define | LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) |
#define | LPUART_CTRL_RIE_MASK (0x200000U) |
#define | LPUART_CTRL_RIE_SHIFT (21U) |
#define | LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) |
#define | LPUART_CTRL_TCIE_MASK (0x400000U) |
#define | LPUART_CTRL_TCIE_SHIFT (22U) |
#define | LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) |
#define | LPUART_CTRL_TIE_MASK (0x800000U) |
#define | LPUART_CTRL_TIE_SHIFT (23U) |
#define | LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) |
#define | LPUART_CTRL_PEIE_MASK (0x1000000U) |
#define | LPUART_CTRL_PEIE_SHIFT (24U) |
#define | LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) |
#define | LPUART_CTRL_FEIE_MASK (0x2000000U) |
#define | LPUART_CTRL_FEIE_SHIFT (25U) |
#define | LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) |
#define | LPUART_CTRL_NEIE_MASK (0x4000000U) |
#define | LPUART_CTRL_NEIE_SHIFT (26U) |
#define | LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) |
#define | LPUART_CTRL_ORIE_MASK (0x8000000U) |
#define | LPUART_CTRL_ORIE_SHIFT (27U) |
#define | LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) |
#define | LPUART_CTRL_TXINV_MASK (0x10000000U) |
#define | LPUART_CTRL_TXINV_SHIFT (28U) |
#define | LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) |
#define | LPUART_CTRL_TXDIR_MASK (0x20000000U) |
#define | LPUART_CTRL_TXDIR_SHIFT (29U) |
#define | LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) |
#define | LPUART_CTRL_R9T8_MASK (0x40000000U) |
#define | LPUART_CTRL_R9T8_SHIFT (30U) |
#define | LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) |
#define | LPUART_CTRL_R8T9_MASK (0x80000000U) |
#define | LPUART_CTRL_R8T9_SHIFT (31U) |
#define | LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) |
DATA - LPUART Data Register | |
#define | LPUART_DATA_R0T0_MASK (0x1U) |
#define | LPUART_DATA_R0T0_SHIFT (0U) |
#define | LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) |
#define | LPUART_DATA_R1T1_MASK (0x2U) |
#define | LPUART_DATA_R1T1_SHIFT (1U) |
#define | LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) |
#define | LPUART_DATA_R2T2_MASK (0x4U) |
#define | LPUART_DATA_R2T2_SHIFT (2U) |
#define | LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) |
#define | LPUART_DATA_R3T3_MASK (0x8U) |
#define | LPUART_DATA_R3T3_SHIFT (3U) |
#define | LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) |
#define | LPUART_DATA_R4T4_MASK (0x10U) |
#define | LPUART_DATA_R4T4_SHIFT (4U) |
#define | LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) |
#define | LPUART_DATA_R5T5_MASK (0x20U) |
#define | LPUART_DATA_R5T5_SHIFT (5U) |
#define | LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) |
#define | LPUART_DATA_R6T6_MASK (0x40U) |
#define | LPUART_DATA_R6T6_SHIFT (6U) |
#define | LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) |
#define | LPUART_DATA_R7T7_MASK (0x80U) |
#define | LPUART_DATA_R7T7_SHIFT (7U) |
#define | LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) |
#define | LPUART_DATA_R8T8_MASK (0x100U) |
#define | LPUART_DATA_R8T8_SHIFT (8U) |
#define | LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) |
#define | LPUART_DATA_R9T9_MASK (0x200U) |
#define | LPUART_DATA_R9T9_SHIFT (9U) |
#define | LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) |
#define | LPUART_DATA_IDLINE_MASK (0x800U) |
#define | LPUART_DATA_IDLINE_SHIFT (11U) |
#define | LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) |
#define | LPUART_DATA_RXEMPT_MASK (0x1000U) |
#define | LPUART_DATA_RXEMPT_SHIFT (12U) |
#define | LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) |
#define | LPUART_DATA_FRETSC_MASK (0x2000U) |
#define | LPUART_DATA_FRETSC_SHIFT (13U) |
#define | LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) |
#define | LPUART_DATA_PARITYE_MASK (0x4000U) |
#define | LPUART_DATA_PARITYE_SHIFT (14U) |
#define | LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) |
#define | LPUART_DATA_NOISY_MASK (0x8000U) |
#define | LPUART_DATA_NOISY_SHIFT (15U) |
#define | LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) |
MATCH - LPUART Match Address Register | |
#define | LPUART_MATCH_MA1_MASK (0x3FFU) |
#define | LPUART_MATCH_MA1_SHIFT (0U) |
#define | LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) |
#define | LPUART_MATCH_MA2_MASK (0x3FF0000U) |
#define | LPUART_MATCH_MA2_SHIFT (16U) |
#define | LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) |
MODIR - LPUART Modem IrDA Register | |
#define | LPUART_MODIR_TXCTSE_MASK (0x1U) |
#define | LPUART_MODIR_TXCTSE_SHIFT (0U) |
#define | LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) |
#define | LPUART_MODIR_TXRTSE_MASK (0x2U) |
#define | LPUART_MODIR_TXRTSE_SHIFT (1U) |
#define | LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) |
#define | LPUART_MODIR_TXRTSPOL_MASK (0x4U) |
#define | LPUART_MODIR_TXRTSPOL_SHIFT (2U) |
#define | LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) |
#define | LPUART_MODIR_RXRTSE_MASK (0x8U) |
#define | LPUART_MODIR_RXRTSE_SHIFT (3U) |
#define | LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) |
#define | LPUART_MODIR_TXCTSC_MASK (0x10U) |
#define | LPUART_MODIR_TXCTSC_SHIFT (4U) |
#define | LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) |
#define | LPUART_MODIR_TXCTSSRC_MASK (0x20U) |
#define | LPUART_MODIR_TXCTSSRC_SHIFT (5U) |
#define | LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) |
#define | LPUART_MODIR_RTSWATER_MASK (0x300U) |
#define | LPUART_MODIR_RTSWATER_SHIFT (8U) |
#define | LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) |
#define | LPUART_MODIR_TNP_MASK (0x30000U) |
#define | LPUART_MODIR_TNP_SHIFT (16U) |
#define | LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) |
#define | LPUART_MODIR_IREN_MASK (0x40000U) |
#define | LPUART_MODIR_IREN_SHIFT (18U) |
#define | LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) |
FIFO - LPUART FIFO Register | |
#define | LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) |
#define | LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) |
#define | LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) |
#define | LPUART_FIFO_RXFE_MASK (0x8U) |
#define | LPUART_FIFO_RXFE_SHIFT (3U) |
#define | LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) |
#define | LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) |
#define | LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) |
#define | LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) |
#define | LPUART_FIFO_TXFE_MASK (0x80U) |
#define | LPUART_FIFO_TXFE_SHIFT (7U) |
#define | LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) |
#define | LPUART_FIFO_RXUFE_MASK (0x100U) |
#define | LPUART_FIFO_RXUFE_SHIFT (8U) |
#define | LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) |
#define | LPUART_FIFO_TXOFE_MASK (0x200U) |
#define | LPUART_FIFO_TXOFE_SHIFT (9U) |
#define | LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) |
#define | LPUART_FIFO_RXIDEN_MASK (0x1C00U) |
#define | LPUART_FIFO_RXIDEN_SHIFT (10U) |
#define | LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) |
#define | LPUART_FIFO_RXFLUSH_MASK (0x4000U) |
#define | LPUART_FIFO_RXFLUSH_SHIFT (14U) |
#define | LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) |
#define | LPUART_FIFO_TXFLUSH_MASK (0x8000U) |
#define | LPUART_FIFO_TXFLUSH_SHIFT (15U) |
#define | LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) |
#define | LPUART_FIFO_RXUF_MASK (0x10000U) |
#define | LPUART_FIFO_RXUF_SHIFT (16U) |
#define | LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) |
#define | LPUART_FIFO_TXOF_MASK (0x20000U) |
#define | LPUART_FIFO_TXOF_SHIFT (17U) |
#define | LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) |
#define | LPUART_FIFO_RXEMPT_MASK (0x400000U) |
#define | LPUART_FIFO_RXEMPT_SHIFT (22U) |
#define | LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) |
#define | LPUART_FIFO_TXEMPT_MASK (0x800000U) |
#define | LPUART_FIFO_TXEMPT_SHIFT (23U) |
#define | LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) |
WATER - LPUART Watermark Register | |
#define | LPUART_WATER_TXWATER_MASK (0x3U) |
#define | LPUART_WATER_TXWATER_SHIFT (0U) |
#define | LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) |
#define | LPUART_WATER_TXCOUNT_MASK (0x700U) |
#define | LPUART_WATER_TXCOUNT_SHIFT (8U) |
#define | LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) |
#define | LPUART_WATER_RXWATER_MASK (0x30000U) |
#define | LPUART_WATER_RXWATER_SHIFT (16U) |
#define | LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) |
#define | LPUART_WATER_RXCOUNT_MASK (0x7000000U) |
#define | LPUART_WATER_RXCOUNT_SHIFT (24U) |
#define | LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) |
PLREV - SoC-defined platform revision | |
#define | MCM_PLREV_PLREV_MASK (0xFFFFU) |
#define | MCM_PLREV_PLREV_SHIFT (0U) |
#define | MCM_PLREV_PLREV(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLREV_PLREV_SHIFT)) & MCM_PLREV_PLREV_MASK) |
PCT - Processor core type | |
#define | MCM_PCT_PCT_MASK (0xFFFFU) |
#define | MCM_PCT_PCT_SHIFT (0U) |
#define | MCM_PCT_PCT(x) (((uint16_t)(((uint16_t)(x)) << MCM_PCT_PCT_SHIFT)) & MCM_PCT_PCT_MASK) |
MEMCFG - Memory configuration | |
#define | MCM_MEMCFG_TCRAMUSZ_MASK (0x3CU) |
#define | MCM_MEMCFG_TCRAMUSZ_SHIFT (2U) |
#define | MCM_MEMCFG_TCRAMUSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_MEMCFG_TCRAMUSZ_SHIFT)) & MCM_MEMCFG_TCRAMUSZ_MASK) |
#define | MCM_MEMCFG_TCRAMLSZ_MASK (0xF00U) |
#define | MCM_MEMCFG_TCRAMLSZ_SHIFT (8U) |
#define | MCM_MEMCFG_TCRAMLSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_MEMCFG_TCRAMLSZ_SHIFT)) & MCM_MEMCFG_TCRAMLSZ_MASK) |
PLASC - Crossbar Switch (AXBS) Slave Configuration | |
#define | MCM_PLASC_ASC_MASK (0xFFU) |
#define | MCM_PLASC_ASC_SHIFT (0U) |
#define | MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) |
PLAMC - Crossbar Switch (AXBS) Master Configuration | |
#define | MCM_PLAMC_AMC_MASK (0xFFU) |
#define | MCM_PLAMC_AMC_SHIFT (0U) |
#define | MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) |
CR - Control Register | |
#define | MCM_CR_STATUS_MASK (0x1FFU) |
#define | MCM_CR_STATUS_SHIFT (0U) |
#define | MCM_CR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_STATUS_SHIFT)) & MCM_CR_STATUS_MASK) |
#define | MCM_CR_CBRR_MASK (0x200U) |
#define | MCM_CR_CBRR_SHIFT (9U) |
#define | MCM_CR_CBRR(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_CBRR_SHIFT)) & MCM_CR_CBRR_MASK) |
#define | MCM_CR_STCMAP_MASK (0x3000000U) |
#define | MCM_CR_STCMAP_SHIFT (24U) |
#define | MCM_CR_STCMAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_STCMAP_SHIFT)) & MCM_CR_STCMAP_MASK) |
#define | MCM_CR_STCMWP_MASK (0x4000000U) |
#define | MCM_CR_STCMWP_SHIFT (26U) |
#define | MCM_CR_STCMWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_STCMWP_SHIFT)) & MCM_CR_STCMWP_MASK) |
#define | MCM_CR_CTCMAP_MASK (0x30000000U) |
#define | MCM_CR_CTCMAP_SHIFT (28U) |
#define | MCM_CR_CTCMAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_CTCMAP_SHIFT)) & MCM_CR_CTCMAP_MASK) |
#define | MCM_CR_CTCMWP_MASK (0x40000000U) |
#define | MCM_CR_CTCMWP_SHIFT (30U) |
#define | MCM_CR_CTCMWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_CTCMWP_SHIFT)) & MCM_CR_CTCMWP_MASK) |
#define | OTFAD_CR_FERR_MASK (0x2U) |
#define | OTFAD_CR_FERR_SHIFT (1U) |
#define | OTFAD_CR_FERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK) |
#define | OTFAD_CR_FLDM_MASK (0x8U) |
#define | OTFAD_CR_FLDM_SHIFT (3U) |
#define | OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK) |
#define | OTFAD_CR_KBSE_MASK (0x10U) |
#define | OTFAD_CR_KBSE_SHIFT (4U) |
#define | OTFAD_CR_KBSE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK) |
#define | OTFAD_CR_KBPE_MASK (0x20U) |
#define | OTFAD_CR_KBPE_SHIFT (5U) |
#define | OTFAD_CR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK) |
#define | OTFAD_CR_RRAE_MASK (0x80U) |
#define | OTFAD_CR_RRAE_SHIFT (7U) |
#define | OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK) |
#define | OTFAD_CR_SKBP_MASK (0x40000000U) |
#define | OTFAD_CR_SKBP_SHIFT (30U) |
#define | OTFAD_CR_SKBP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK) |
#define | OTFAD_CR_GE_MASK (0x80000000U) |
#define | OTFAD_CR_GE_SHIFT (31U) |
#define | OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK) |
ISCR - Interrupt Status and Control Register | |
#define | MCM_ISCR_CWBER_MASK (0x10U) |
#define | MCM_ISCR_CWBER_SHIFT (4U) |
#define | MCM_ISCR_CWBER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBER_SHIFT)) & MCM_ISCR_CWBER_MASK) |
#define | MCM_ISCR_FIOC_MASK (0x100U) |
#define | MCM_ISCR_FIOC_SHIFT (8U) |
#define | MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) |
#define | MCM_ISCR_FDZC_MASK (0x200U) |
#define | MCM_ISCR_FDZC_SHIFT (9U) |
#define | MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) |
#define | MCM_ISCR_FOFC_MASK (0x400U) |
#define | MCM_ISCR_FOFC_SHIFT (10U) |
#define | MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) |
#define | MCM_ISCR_FUFC_MASK (0x800U) |
#define | MCM_ISCR_FUFC_SHIFT (11U) |
#define | MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) |
#define | MCM_ISCR_FIXC_MASK (0x1000U) |
#define | MCM_ISCR_FIXC_SHIFT (12U) |
#define | MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) |
#define | MCM_ISCR_FIDC_MASK (0x8000U) |
#define | MCM_ISCR_FIDC_SHIFT (15U) |
#define | MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) |
#define | MCM_ISCR_CWBEE_MASK (0x100000U) |
#define | MCM_ISCR_CWBEE_SHIFT (20U) |
#define | MCM_ISCR_CWBEE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBEE_SHIFT)) & MCM_ISCR_CWBEE_MASK) |
#define | MCM_ISCR_FIOCE_MASK (0x1000000U) |
#define | MCM_ISCR_FIOCE_SHIFT (24U) |
#define | MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) |
#define | MCM_ISCR_FDZCE_MASK (0x2000000U) |
#define | MCM_ISCR_FDZCE_SHIFT (25U) |
#define | MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) |
#define | MCM_ISCR_FOFCE_MASK (0x4000000U) |
#define | MCM_ISCR_FOFCE_SHIFT (26U) |
#define | MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) |
#define | MCM_ISCR_FUFCE_MASK (0x8000000U) |
#define | MCM_ISCR_FUFCE_SHIFT (27U) |
#define | MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) |
#define | MCM_ISCR_FIXCE_MASK (0x10000000U) |
#define | MCM_ISCR_FIXCE_SHIFT (28U) |
#define | MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) |
#define | MCM_ISCR_FIDCE_MASK (0x80000000U) |
#define | MCM_ISCR_FIDCE_SHIFT (31U) |
#define | MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) |
FADR - Fault address register | |
#define | MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU) |
#define | MCM_FADR_ADDRESS_SHIFT (0U) |
#define | MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK) |
FATR - Fault attributes register | |
#define | MCM_FATR_BEDA_MASK (0x1U) |
#define | MCM_FATR_BEDA_SHIFT (0U) |
#define | MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK) |
#define | MCM_FATR_BEMD_MASK (0x2U) |
#define | MCM_FATR_BEMD_SHIFT (1U) |
#define | MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK) |
#define | MCM_FATR_BESZ_MASK (0x30U) |
#define | MCM_FATR_BESZ_SHIFT (4U) |
#define | MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK) |
#define | MCM_FATR_BEWT_MASK (0x80U) |
#define | MCM_FATR_BEWT_SHIFT (7U) |
#define | MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK) |
#define | MCM_FATR_BEMN_MASK (0xF00U) |
#define | MCM_FATR_BEMN_SHIFT (8U) |
#define | MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK) |
#define | MCM_FATR_BEOVR_MASK (0x80000000U) |
#define | MCM_FATR_BEOVR_SHIFT (31U) |
#define | MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK) |
FDR - Fault data register | |
#define | MCM_FDR_DATA_MASK (0xFFFFFFFFU) |
#define | MCM_FDR_DATA_SHIFT (0U) |
#define | MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK) |
LMDR - Local Memory Descriptor Register | |
#define | MCM_LMDR_CF0_MASK (0xFU) |
#define | MCM_LMDR_CF0_SHIFT (0U) |
#define | MCM_LMDR_CF0(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_CF0_SHIFT)) & MCM_LMDR_CF0_MASK) |
#define | MCM_LMDR_CF1_MASK (0xF0U) |
#define | MCM_LMDR_CF1_SHIFT (4U) |
#define | MCM_LMDR_CF1(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_CF1_SHIFT)) & MCM_LMDR_CF1_MASK) |
#define | MCM_LMDR_MT_MASK (0xE000U) |
#define | MCM_LMDR_MT_SHIFT (13U) |
#define | MCM_LMDR_MT(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_MT_SHIFT)) & MCM_LMDR_MT_MASK) |
#define | MCM_LMDR_RO_MASK (0x10000U) |
#define | MCM_LMDR_RO_SHIFT (16U) |
#define | MCM_LMDR_RO(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_RO_SHIFT)) & MCM_LMDR_RO_MASK) |
#define | MCM_LMDR_DPW_MASK (0xE0000U) |
#define | MCM_LMDR_DPW_SHIFT (17U) |
#define | MCM_LMDR_DPW(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_DPW_SHIFT)) & MCM_LMDR_DPW_MASK) |
#define | MCM_LMDR_WY_MASK (0xF00000U) |
#define | MCM_LMDR_WY_SHIFT (20U) |
#define | MCM_LMDR_WY(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_WY_SHIFT)) & MCM_LMDR_WY_MASK) |
#define | MCM_LMDR_LMSZ_MASK (0xF000000U) |
#define | MCM_LMDR_LMSZ_SHIFT (24U) |
#define | MCM_LMDR_LMSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZ_SHIFT)) & MCM_LMDR_LMSZ_MASK) |
#define | MCM_LMDR_LMSZH_MASK (0x10000000U) |
#define | MCM_LMDR_LMSZH_SHIFT (28U) |
#define | MCM_LMDR_LMSZH(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZH_SHIFT)) & MCM_LMDR_LMSZH_MASK) |
#define | MCM_LMDR_V_MASK (0x80000000U) |
#define | MCM_LMDR_V_SHIFT (31U) |
#define | MCM_LMDR_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_V_SHIFT)) & MCM_LMDR_V_MASK) |
LMPECR - LMEM Parity & ECC Control Register | |
#define | MCM_LMPECR_ERNCR_MASK (0x1U) |
#define | MCM_LMPECR_ERNCR_SHIFT (0U) |
#define | MCM_LMPECR_ERNCR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ERNCR_SHIFT)) & MCM_LMPECR_ERNCR_MASK) |
#define | MCM_LMPECR_ERNCI_MASK (0x2U) |
#define | MCM_LMPECR_ERNCI_SHIFT (1U) |
#define | MCM_LMPECR_ERNCI(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ERNCI_SHIFT)) & MCM_LMPECR_ERNCI_MASK) |
#define | MCM_LMPECR_ER1BR_MASK (0x100U) |
#define | MCM_LMPECR_ER1BR_SHIFT (8U) |
#define | MCM_LMPECR_ER1BR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ER1BR_SHIFT)) & MCM_LMPECR_ER1BR_MASK) |
#define | MCM_LMPECR_ER1BI_MASK (0x200U) |
#define | MCM_LMPECR_ER1BI_SHIFT (9U) |
#define | MCM_LMPECR_ER1BI(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ER1BI_SHIFT)) & MCM_LMPECR_ER1BI_MASK) |
#define | MCM_LMPECR_ECPR_MASK (0x100000U) |
#define | MCM_LMPECR_ECPR_SHIFT (20U) |
#define | MCM_LMPECR_ECPR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ECPR_SHIFT)) & MCM_LMPECR_ECPR_MASK) |
#define | MCM_LMPECR_ECPI_MASK (0x200000U) |
#define | MCM_LMPECR_ECPI_SHIFT (21U) |
#define | MCM_LMPECR_ECPI(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ECPI_SHIFT)) & MCM_LMPECR_ECPI_MASK) |
LMPEIR - LMEM Parity & ECC Interrupt Register | |
#define | MCM_LMPEIR_ENC_MASK (0xFFU) |
#define | MCM_LMPEIR_ENC_SHIFT (0U) |
#define | MCM_LMPEIR_ENC(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_ENC_SHIFT)) & MCM_LMPEIR_ENC_MASK) |
#define | MCM_LMPEIR_E1B_MASK (0xFF00U) |
#define | MCM_LMPEIR_E1B_SHIFT (8U) |
#define | MCM_LMPEIR_E1B(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_E1B_SHIFT)) & MCM_LMPEIR_E1B_MASK) |
#define | MCM_LMPEIR_PE_MASK (0xFF0000U) |
#define | MCM_LMPEIR_PE_SHIFT (16U) |
#define | MCM_LMPEIR_PE(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PE_SHIFT)) & MCM_LMPEIR_PE_MASK) |
#define | MCM_LMPEIR_PEELOC_MASK (0x1F000000U) |
#define | MCM_LMPEIR_PEELOC_SHIFT (24U) |
#define | MCM_LMPEIR_PEELOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PEELOC_SHIFT)) & MCM_LMPEIR_PEELOC_MASK) |
#define | MCM_LMPEIR_V_MASK (0x80000000U) |
#define | MCM_LMPEIR_V_SHIFT (31U) |
#define | MCM_LMPEIR_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_V_SHIFT)) & MCM_LMPEIR_V_MASK) |
LMFAR - LMEM Fault Address Register | |
#define | MCM_LMFAR_EFADD_MASK (0xFFFFFFFFU) |
#define | MCM_LMFAR_EFADD_SHIFT (0U) |
#define | MCM_LMFAR_EFADD(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFAR_EFADD_SHIFT)) & MCM_LMFAR_EFADD_MASK) |
LMFATR - LMEM Fault Attribute Register | |
#define | MCM_LMFATR_PEFPRT_MASK (0xFU) |
#define | MCM_LMFATR_PEFPRT_SHIFT (0U) |
#define | MCM_LMFATR_PEFPRT(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFPRT_SHIFT)) & MCM_LMFATR_PEFPRT_MASK) |
#define | MCM_LMFATR_PEFSIZE_MASK (0x70U) |
#define | MCM_LMFATR_PEFSIZE_SHIFT (4U) |
#define | MCM_LMFATR_PEFSIZE(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFSIZE_SHIFT)) & MCM_LMFATR_PEFSIZE_MASK) |
#define | MCM_LMFATR_PEFW_MASK (0x80U) |
#define | MCM_LMFATR_PEFW_SHIFT (7U) |
#define | MCM_LMFATR_PEFW(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFW_SHIFT)) & MCM_LMFATR_PEFW_MASK) |
#define | MCM_LMFATR_PEFMST_MASK (0xFF00U) |
#define | MCM_LMFATR_PEFMST_SHIFT (8U) |
#define | MCM_LMFATR_PEFMST(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFMST_SHIFT)) & MCM_LMFATR_PEFMST_MASK) |
#define | MCM_LMFATR_WORDID_MASK (0x1000000U) |
#define | MCM_LMFATR_WORDID_SHIFT (24U) |
#define | MCM_LMFATR_WORDID(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_WORDID_SHIFT)) & MCM_LMFATR_WORDID_MASK) |
#define | MCM_LMFATR_OVR_MASK (0x80000000U) |
#define | MCM_LMFATR_OVR_SHIFT (31U) |
#define | MCM_LMFATR_OVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_OVR_SHIFT)) & MCM_LMFATR_OVR_MASK) |
LMFDHR - LMEM Fault Data High Register | |
#define | MCM_LMFDHR_PEFDH_MASK (0xFFFFFFFFU) |
#define | MCM_LMFDHR_PEFDH_SHIFT (0U) |
#define | MCM_LMFDHR_PEFDH(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFDHR_PEFDH_SHIFT)) & MCM_LMFDHR_PEFDH_MASK) |
LMFDLR - LMEM Fault Data Low Register | |
#define | MCM_LMFDLR_PEFDL_MASK (0xFFFFFFFFU) |
#define | MCM_LMFDLR_PEFDL_SHIFT (0U) |
#define | MCM_LMFDLR_PEFDL(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFDLR_PEFDL_SHIFT)) & MCM_LMFDLR_PEFDL_MASK) |
ERR_STATUS - Error Interrupt Status Register | |
#define | MECC_ERR_STATUS_SINGLE_ERR0_MASK (0x1U) |
#define | MECC_ERR_STATUS_SINGLE_ERR0_SHIFT (0U) |
#define | MECC_ERR_STATUS_SINGLE_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK) |
#define | MECC_ERR_STATUS_SINGLE_ERR1_MASK (0x2U) |
#define | MECC_ERR_STATUS_SINGLE_ERR1_SHIFT (1U) |
#define | MECC_ERR_STATUS_SINGLE_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK) |
#define | MECC_ERR_STATUS_SINGLE_ERR2_MASK (0x4U) |
#define | MECC_ERR_STATUS_SINGLE_ERR2_SHIFT (2U) |
#define | MECC_ERR_STATUS_SINGLE_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK) |
#define | MECC_ERR_STATUS_SINGLE_ERR3_MASK (0x8U) |
#define | MECC_ERR_STATUS_SINGLE_ERR3_SHIFT (3U) |
#define | MECC_ERR_STATUS_SINGLE_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK) |
#define | MECC_ERR_STATUS_MULTI_ERR0_MASK (0x10U) |
#define | MECC_ERR_STATUS_MULTI_ERR0_SHIFT (4U) |
#define | MECC_ERR_STATUS_MULTI_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK) |
#define | MECC_ERR_STATUS_MULTI_ERR1_MASK (0x20U) |
#define | MECC_ERR_STATUS_MULTI_ERR1_SHIFT (5U) |
#define | MECC_ERR_STATUS_MULTI_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK) |
#define | MECC_ERR_STATUS_MULTI_ERR2_MASK (0x40U) |
#define | MECC_ERR_STATUS_MULTI_ERR2_SHIFT (6U) |
#define | MECC_ERR_STATUS_MULTI_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK) |
#define | MECC_ERR_STATUS_MULTI_ERR3_MASK (0x80U) |
#define | MECC_ERR_STATUS_MULTI_ERR3_SHIFT (7U) |
#define | MECC_ERR_STATUS_MULTI_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK) |
#define | MECC_ERR_STATUS_STRB_ERR0_MASK (0x100U) |
#define | MECC_ERR_STATUS_STRB_ERR0_SHIFT (8U) |
#define | MECC_ERR_STATUS_STRB_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK) |
#define | MECC_ERR_STATUS_STRB_ERR1_MASK (0x200U) |
#define | MECC_ERR_STATUS_STRB_ERR1_SHIFT (9U) |
#define | MECC_ERR_STATUS_STRB_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK) |
#define | MECC_ERR_STATUS_STRB_ERR2_MASK (0x400U) |
#define | MECC_ERR_STATUS_STRB_ERR2_SHIFT (10U) |
#define | MECC_ERR_STATUS_STRB_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK) |
#define | MECC_ERR_STATUS_STRB_ERR3_MASK (0x800U) |
#define | MECC_ERR_STATUS_STRB_ERR3_SHIFT (11U) |
#define | MECC_ERR_STATUS_STRB_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK) |
#define | MECC_ERR_STATUS_ADDR_ERR0_MASK (0x1000U) |
#define | MECC_ERR_STATUS_ADDR_ERR0_SHIFT (12U) |
#define | MECC_ERR_STATUS_ADDR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK) |
#define | MECC_ERR_STATUS_ADDR_ERR1_MASK (0x2000U) |
#define | MECC_ERR_STATUS_ADDR_ERR1_SHIFT (13U) |
#define | MECC_ERR_STATUS_ADDR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK) |
#define | MECC_ERR_STATUS_ADDR_ERR2_MASK (0x4000U) |
#define | MECC_ERR_STATUS_ADDR_ERR2_SHIFT (14U) |
#define | MECC_ERR_STATUS_ADDR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK) |
#define | MECC_ERR_STATUS_ADDR_ERR3_MASK (0x8000U) |
#define | MECC_ERR_STATUS_ADDR_ERR3_SHIFT (15U) |
#define | MECC_ERR_STATUS_ADDR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK) |
#define | XECC_ERR_STATUS_SINGLE_ERR_MASK (0x1U) |
#define | XECC_ERR_STATUS_SINGLE_ERR_SHIFT (0U) |
#define | XECC_ERR_STATUS_SINGLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_SINGLE_ERR_SHIFT)) & XECC_ERR_STATUS_SINGLE_ERR_MASK) |
#define | XECC_ERR_STATUS_MULTI_ERR_MASK (0x2U) |
#define | XECC_ERR_STATUS_MULTI_ERR_SHIFT (1U) |
#define | XECC_ERR_STATUS_MULTI_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_MULTI_ERR_SHIFT)) & XECC_ERR_STATUS_MULTI_ERR_MASK) |
#define | XECC_ERR_STATUS_Reserved1_MASK (0xFFFFFFFCU) |
#define | XECC_ERR_STATUS_Reserved1_SHIFT (2U) |
#define | XECC_ERR_STATUS_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_Reserved1_SHIFT)) & XECC_ERR_STATUS_Reserved1_MASK) |
ERR_STAT_EN - Error Interrupt Status Enable Register | |
#define | MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK (0x1U) |
#define | MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT (0U) |
#define | MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK (0x2U) |
#define | MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT (1U) |
#define | MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK (0x4U) |
#define | MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT (2U) |
#define | MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK (0x8U) |
#define | MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT (3U) |
#define | MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK (0x10U) |
#define | MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT (4U) |
#define | MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK (0x20U) |
#define | MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT (5U) |
#define | MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK (0x40U) |
#define | MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT (6U) |
#define | MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK (0x80U) |
#define | MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT (7U) |
#define | MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK (0x100U) |
#define | MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT (8U) |
#define | MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK (0x200U) |
#define | MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT (9U) |
#define | MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK (0x400U) |
#define | MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT (10U) |
#define | MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK (0x800U) |
#define | MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT (11U) |
#define | MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK (0x1000U) |
#define | MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT (12U) |
#define | MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK (0x2000U) |
#define | MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT (13U) |
#define | MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK (0x4000U) |
#define | MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT (14U) |
#define | MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK) |
#define | MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK (0x8000U) |
#define | MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT (15U) |
#define | MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK) |
#define | XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK (0x1U) |
#define | XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT (0U) |
#define | XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK) |
#define | XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK (0x2U) |
#define | XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT (1U) |
#define | XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK) |
#define | XECC_ERR_STAT_EN_Reserved1_MASK (0xFFFFFFFCU) |
#define | XECC_ERR_STAT_EN_Reserved1_SHIFT (2U) |
#define | XECC_ERR_STAT_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_Reserved1_SHIFT)) & XECC_ERR_STAT_EN_Reserved1_MASK) |
ERR_SIG_EN - Error Interrupt Enable Register | |
#define | MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK (0x1U) |
#define | MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT (0U) |
#define | MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK (0x2U) |
#define | MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT (1U) |
#define | MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK (0x4U) |
#define | MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT (2U) |
#define | MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK (0x8U) |
#define | MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT (3U) |
#define | MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK (0x10U) |
#define | MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT (4U) |
#define | MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK (0x20U) |
#define | MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT (5U) |
#define | MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK (0x40U) |
#define | MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT (6U) |
#define | MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK (0x80U) |
#define | MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT (7U) |
#define | MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK (0x100U) |
#define | MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT (8U) |
#define | MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK (0x200U) |
#define | MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT (9U) |
#define | MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK (0x400U) |
#define | MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT (10U) |
#define | MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK (0x800U) |
#define | MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT (11U) |
#define | MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK (0x1000U) |
#define | MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT (12U) |
#define | MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK (0x2000U) |
#define | MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT (13U) |
#define | MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK (0x4000U) |
#define | MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT (14U) |
#define | MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK) |
#define | MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK (0x8000U) |
#define | MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT (15U) |
#define | MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK) |
#define | XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK (0x1U) |
#define | XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT (0U) |
#define | XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK) |
#define | XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK (0x2U) |
#define | XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT (1U) |
#define | XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK) |
#define | XECC_ERR_SIG_EN_Reserved1_MASK (0xFFFFFFFCU) |
#define | XECC_ERR_SIG_EN_Reserved1_SHIFT (2U) |
#define | XECC_ERR_SIG_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_Reserved1_SHIFT)) & XECC_ERR_SIG_EN_Reserved1_MASK) |
ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data | |
#define | MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK (0xFFFFFFFFU) |
#define | MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT (0U) |
#define | MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK) |
ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data | |
#define | MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK (0xFFFFFFFFU) |
#define | MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT (0U) |
#define | MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK) |
ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data | |
#define | MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK (0xFFU) |
#define | MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT (0U) |
#define | MECC_ERR_ECC_INJ0_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK) |
ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data | |
#define | MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK (0xFFFFFFFFU) |
#define | MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT (0U) |
#define | MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK) |
ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data | |
#define | MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK (0xFFFFFFFFU) |
#define | MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT (0U) |
#define | MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK) |
ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data | |
#define | MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK (0xFFU) |
#define | MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT (0U) |
#define | MECC_ERR_ECC_INJ1_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK) |
ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data | |
#define | MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK (0xFFFFFFFFU) |
#define | MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT (0U) |
#define | MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK) |
ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data | |
#define | MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK (0xFFFFFFFFU) |
#define | MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT (0U) |
#define | MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK) |
ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data | |
#define | MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK (0xFFU) |
#define | MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT (0U) |
#define | MECC_ERR_ECC_INJ2_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK) |
ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data | |
#define | MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK (0xFFFFFFFFU) |
#define | MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT (0U) |
#define | MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK) |
ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data | |
#define | MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK (0xFFFFFFFFU) |
#define | MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT (0U) |
#define | MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK) |
ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data | |
#define | MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK (0xFFU) |
#define | MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT (0U) |
#define | MECC_ERR_ECC_INJ3_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK) |
SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0 | |
#define | MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK (0xFFU) |
#define | MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT (0U) |
#define | MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK) |
#define | MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK (0x7FFFF00U) |
#define | MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT (8U) |
#define | MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK) |
SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0 | |
#define | MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT (0U) |
#define | MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK) |
SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0 | |
#define | MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT (0U) |
#define | MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK) |
SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0 | |
#define | MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT (0U) |
#define | MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK) |
SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0 | |
#define | MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT (0U) |
#define | MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK) |
SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1 | |
#define | MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK (0xFFU) |
#define | MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT (0U) |
#define | MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK) |
#define | MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK (0x7FFFF00U) |
#define | MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT (8U) |
#define | MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK) |
SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1 | |
#define | MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT (0U) |
#define | MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK) |
SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1 | |
#define | MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT (0U) |
#define | MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK) |
SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1 | |
#define | MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT (0U) |
#define | MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK) |
SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1 | |
#define | MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT (0U) |
#define | MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK) |
SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2 | |
#define | MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK (0xFFU) |
#define | MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT (0U) |
#define | MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK) |
#define | MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK (0x7FFFF00U) |
#define | MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT (8U) |
#define | MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK) |
SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2 | |
#define | MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT (0U) |
#define | MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK) |
SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2 | |
#define | MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT (0U) |
#define | MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK) |
SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2 | |
#define | MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT (0U) |
#define | MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK) |
SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2 | |
#define | MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT (0U) |
#define | MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK) |
SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3 | |
#define | MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK (0xFFU) |
#define | MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT (0U) |
#define | MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK) |
#define | MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK (0x7FFFF00U) |
#define | MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT (8U) |
#define | MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK) |
SINGLE_ERR_DATA_LOW3 - LOW 32 Bits Single Error Read Data On OCRAM Bank3 | |
#define | MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT (0U) |
#define | MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK) |
SINGLE_ERR_DATA_HIGH3 - HIGH 32 Bits Single Error Read Data On OCRAM Bank3 | |
#define | MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT (0U) |
#define | MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK) |
SINGLE_ERR_POS_LOW3 - LOW Single Error Bit Position On OCRAM Bank3 | |
#define | MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT (0U) |
#define | MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK) |
SINGLE_ERR_POS_HIGH3 - HIGH Single Error Bit Position On OCRAM Bank3 | |
#define | MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) |
#define | MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT (0U) |
#define | MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK) |
MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC code On OCRAM Bank0 | |
#define | MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK (0xFFU) |
#define | MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT (0U) |
#define | MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK) |
#define | MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK (0x7FFFF00U) |
#define | MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT (8U) |
#define | MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK) |
MULTI_ERR_DATA_LOW0 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 | |
#define | MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT (0U) |
#define | MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK) |
MULTI_ERR_DATA_HIGH0 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 | |
#define | MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT (0U) |
#define | MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK) |
MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC code On OCRAM Bank1 | |
#define | MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK (0xFFU) |
#define | MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT (0U) |
#define | MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK) |
#define | MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK (0x7FFFF00U) |
#define | MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT (8U) |
#define | MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK) |
MULTI_ERR_DATA_LOW1 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 | |
#define | MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT (0U) |
#define | MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK) |
MULTI_ERR_DATA_HIGH1 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 | |
#define | MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT (0U) |
#define | MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK) |
MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC code On OCRAM Bank2 | |
#define | MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK (0xFFU) |
#define | MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT (0U) |
#define | MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK) |
#define | MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK (0x7FFFF00U) |
#define | MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT (8U) |
#define | MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK) |
MULTI_ERR_DATA_LOW2 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 | |
#define | MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT (0U) |
#define | MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK) |
MULTI_ERR_DATA_HIGH2 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 | |
#define | MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT (0U) |
#define | MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK) |
MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC code On OCRAM Bank3 | |
#define | MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK (0xFFU) |
#define | MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT (0U) |
#define | MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK) |
#define | MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK (0x7FFFF00U) |
#define | MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT (8U) |
#define | MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK) |
MULTI_ERR_DATA_LOW3 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 | |
#define | MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT (0U) |
#define | MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK) |
MULTI_ERR_DATA_HIGH3 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 | |
#define | MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT (0U) |
#define | MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK) |
PIPE_ECC_EN - OCRAM Pipeline And ECC Enable | |
#define | MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK (0x1U) |
#define | MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT (0U) |
#define | MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK) |
#define | MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK (0x2U) |
#define | MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT (1U) |
#define | MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK) |
#define | MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK (0x4U) |
#define | MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT (2U) |
#define | MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK) |
#define | MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK (0x8U) |
#define | MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT (3U) |
#define | MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK) |
#define | MECC_PIPE_ECC_EN_ECC_EN_MASK (0x10U) |
#define | MECC_PIPE_ECC_EN_ECC_EN_SHIFT (4U) |
#define | MECC_PIPE_ECC_EN_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK) |
PENDING_STAT - Pending Status | |
#define | MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK (0x1U) |
#define | MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT (0U) |
#define | MECC_PENDING_STAT_READ_DATA_WAIT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK) |
#define | MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK (0x2U) |
#define | MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT (1U) |
#define | MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK) |
#define | MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK (0x4U) |
#define | MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT (2U) |
#define | MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK) |
#define | MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK (0x8U) |
#define | MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT (3U) |
#define | MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK) |
CFG_NUM_LANES - Lane Configuration Register | |
#define | MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK (0x3U) |
#define | MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT (0U) |
#define | MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT)) & MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK) |
CFG_DISABLE_DATA_LANES - Disable Data Lane Register | |
#define | MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK (0xFU) |
#define | MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT (0U) |
#define | MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK) |
BIT_ERR - ECC and CRC Error Status Register | |
#define | MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK (0x3FFU) |
#define | MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT (0U) |
#define | MIPI_CSI2RX_BIT_ERR_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT)) & MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK) |
IRQ_STATUS - IRQ Status Register | |
#define | MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK (0x1FFU) |
#define | MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT (0U) |
#define | MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT)) & MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK) |
IRQ_MASK - IRQ Mask Setting Register | |
#define | MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK (0x1FFU) |
#define | MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT (0U) |
#define | MIPI_CSI2RX_IRQ_MASK_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT)) & MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK) |
ULPS_STATUS - Ultra Low Power State (ULPS) Status Register | |
#define | MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK (0x3FFU) |
#define | MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT (0U) |
#define | MIPI_CSI2RX_ULPS_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT)) & MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK) |
PPI_ERRSOT_HS - ERRSot HS Status Register | |
#define | MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK (0xFU) |
#define | MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT (0U) |
#define | MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK) |
PPI_ERRSOTSYNC_HS - ErrSotSync HS Status Register | |
#define | MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK (0xFU) |
#define | MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT (0U) |
#define | MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK) |
PPI_ERRESC - ErrEsc Status Register | |
#define | MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK (0xFU) |
#define | MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT (0U) |
#define | MIPI_CSI2RX_PPI_ERRESC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK) |
PPI_ERRSYNCESC - ErrSyncEsc Status Register | |
#define | MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK (0xFU) |
#define | MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT (0U) |
#define | MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK) |
PPI_ERRCONTROL - ErrControl Status Register | |
#define | MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK (0xFU) |
#define | MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT (0U) |
#define | MIPI_CSI2RX_PPI_ERRCONTROL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK) |
CFG_DISABLE_PAYLOAD_0 - Disable Payload 0 Register | |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK (0x1U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT (0U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK (0x2U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT (1U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK (0x4U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT (2U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK (0x400U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT (10U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK (0x4000U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT (14U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK (0x10000U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT (16U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK (0x20000U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT (17U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK (0x40000U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT (18U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK (0x80000U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT (19U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK (0x100000U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT (20U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK) |
CFG_DISABLE_PAYLOAD_1 - Disable Payload 1 Register | |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK (0x1U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT (0U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK (0x2U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT (1U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK (0x4U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT (2U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK (0x8U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT (3U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK (0x10U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT (4U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK (0x20U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT (5U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK (0x40U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT (6U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK (0x80U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT (7U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK (0x10000U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT (16U) |
#define | MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK) |
CFG_IGNORE_VC - Ignore Virtual Channel Register | |
#define | MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK (0x1U) |
#define | MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT (0U) |
#define | MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT)) & MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK) |
CFG_VID_VC - Virtual Channel value Register | |
#define | MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK (0x3U) |
#define | MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT (0U) |
#define | MIPI_CSI2RX_CFG_VID_VC_VID_VC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT)) & MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK) |
CFG_VID_P_FIFO_SEND_LEVEL - FIFO Send Level Configuration Register | |
#define | MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK (0xFFFFU) |
#define | MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT (0U) |
#define | MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT)) & MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK) |
CFG_VID_VSYNC - VSYNC Configuration Register | |
#define | MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK (0xFFU) |
#define | MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT (0U) |
#define | MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK) |
CFG_VID_HSYNC_FP - Start of HSYNC Delay control Register | |
#define | MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK (0xFFU) |
#define | MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT (0U) |
#define | MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK) |
CFG_VID_HSYNC - HSYNC Configuration Register | |
#define | MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK (0xFFU) |
#define | MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT (0U) |
#define | MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK) |
CFG_VID_HSYNC_BP - End of HSYNC Delay Control Register | |
#define | MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK (0xFFU) |
#define | MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT (0U) |
#define | MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK) |
CASR - Status Register | |
#define | MMCAU_CASR_IC_MASK (0x1U) |
#define | MMCAU_CASR_IC_SHIFT (0U) |
#define | MMCAU_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_IC_SHIFT)) & MMCAU_CASR_IC_MASK) |
#define | MMCAU_CASR_DPE_MASK (0x2U) |
#define | MMCAU_CASR_DPE_SHIFT (1U) |
#define | MMCAU_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_DPE_SHIFT)) & MMCAU_CASR_DPE_MASK) |
#define | MMCAU_CASR_VER_MASK (0xF0000000U) |
#define | MMCAU_CASR_VER_SHIFT (28U) |
#define | MMCAU_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_VER_SHIFT)) & MMCAU_CASR_VER_MASK) |
CAA - Accumulator | |
#define | MMCAU_CAA_ACC_MASK (0xFFFFFFFFU) |
#define | MMCAU_CAA_ACC_SHIFT (0U) |
#define | MMCAU_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CAA_ACC_SHIFT)) & MMCAU_CAA_ACC_MASK) |
CA - General Purpose Register | |
#define | MMCAU_CA_CAn_MASK (0xFFFFFFFFU) |
#define | MMCAU_CA_CAn_SHIFT (0U) |
#define | MMCAU_CA_CAn(x) (((uint32_t)(((uint32_t)(x)) << MMCAU_CA_CAn_SHIFT)) & MMCAU_CA_CAn_MASK) |
TR - Processor B Transmit Register 0..Processor B Transmit Register 3 | |
#define | MU_TR_DATA_MASK (0xFFFFFFFFU) |
#define | MU_TR_DATA_SHIFT (0U) |
#define | MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK) |
RR - Processor B Receive Register 0..Processor B Receive Register 3 | |
#define | MU_RR_DATA_MASK (0xFFFFFFFFU) |
#define | MU_RR_DATA_SHIFT (0U) |
#define | MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK) |
SR - Processor B Status Register | |
#define | MU_SR_Fn_MASK (0x7U) |
#define | MU_SR_Fn_SHIFT (0U) |
#define | MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK) |
#define | MU_SR_EP_MASK (0x10U) |
#define | MU_SR_EP_SHIFT (4U) |
#define | MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) |
#define | MU_SR_RS_MASK (0x80U) |
#define | MU_SR_RS_SHIFT (7U) |
#define | MU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK) |
#define | MU_SR_FUP_MASK (0x100U) |
#define | MU_SR_FUP_SHIFT (8U) |
#define | MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) |
#define | MU_SR_TEn_MASK (0xF00000U) |
#define | MU_SR_TEn_SHIFT (20U) |
#define | MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK) |
#define | MU_SR_RFn_MASK (0xF000000U) |
#define | MU_SR_RFn_SHIFT (24U) |
#define | MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK) |
#define | MU_SR_GIPn_MASK (0xF0000000U) |
#define | MU_SR_GIPn_SHIFT (28U) |
#define | MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK) |
CR - Processor B Control Register | |
#define | MU_CR_Fn_MASK (0x7U) |
#define | MU_CR_Fn_SHIFT (0U) |
#define | MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK) |
#define | MU_CR_GIRn_MASK (0xF0000U) |
#define | MU_CR_GIRn_SHIFT (16U) |
#define | MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK) |
#define | MU_CR_TIEn_MASK (0xF00000U) |
#define | MU_CR_TIEn_SHIFT (20U) |
#define | MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK) |
#define | MU_CR_RIEn_MASK (0xF000000U) |
#define | MU_CR_RIEn_SHIFT (24U) |
#define | MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK) |
#define | MU_CR_GIEn_MASK (0xF0000000U) |
#define | MU_CR_GIEn_SHIFT (28U) |
#define | MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK) |
CTRL - OTP Controller Control and Status Register | |
#define | OCOTP_CTRL_ADDR_MASK (0x3FFU) |
#define | OCOTP_CTRL_ADDR_SHIFT (0U) |
#define | OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) |
#define | OCOTP_CTRL_BUSY_MASK (0x400U) |
#define | OCOTP_CTRL_BUSY_SHIFT (10U) |
#define | OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) |
#define | OCOTP_CTRL_ERROR_MASK (0x800U) |
#define | OCOTP_CTRL_ERROR_SHIFT (11U) |
#define | OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) |
#define | OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x1000U) |
#define | OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (12U) |
#define | OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) |
#define | OCOTP_CTRL_WORDLOCK_MASK (0x8000U) |
#define | OCOTP_CTRL_WORDLOCK_SHIFT (15U) |
#define | OCOTP_CTRL_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WORDLOCK_SHIFT)) & OCOTP_CTRL_WORDLOCK_MASK) |
#define | OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) |
#define | OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) |
#define | OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) |
CTRL_SET - OTP Controller Control and Status Register | |
#define | OCOTP_CTRL_SET_ADDR_MASK (0x3FFU) |
#define | OCOTP_CTRL_SET_ADDR_SHIFT (0U) |
#define | OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) |
#define | OCOTP_CTRL_SET_BUSY_MASK (0x400U) |
#define | OCOTP_CTRL_SET_BUSY_SHIFT (10U) |
#define | OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) |
#define | OCOTP_CTRL_SET_ERROR_MASK (0x800U) |
#define | OCOTP_CTRL_SET_ERROR_SHIFT (11U) |
#define | OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) |
#define | OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x1000U) |
#define | OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (12U) |
#define | OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) |
#define | OCOTP_CTRL_SET_WORDLOCK_MASK (0x8000U) |
#define | OCOTP_CTRL_SET_WORDLOCK_SHIFT (15U) |
#define | OCOTP_CTRL_SET_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WORDLOCK_SHIFT)) & OCOTP_CTRL_SET_WORDLOCK_MASK) |
#define | OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) |
#define | OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) |
#define | OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) |
CTRL_CLR - OTP Controller Control and Status Register | |
#define | OCOTP_CTRL_CLR_ADDR_MASK (0x3FFU) |
#define | OCOTP_CTRL_CLR_ADDR_SHIFT (0U) |
#define | OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) |
#define | OCOTP_CTRL_CLR_BUSY_MASK (0x400U) |
#define | OCOTP_CTRL_CLR_BUSY_SHIFT (10U) |
#define | OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) |
#define | OCOTP_CTRL_CLR_ERROR_MASK (0x800U) |
#define | OCOTP_CTRL_CLR_ERROR_SHIFT (11U) |
#define | OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) |
#define | OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x1000U) |
#define | OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (12U) |
#define | OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) |
#define | OCOTP_CTRL_CLR_WORDLOCK_MASK (0x8000U) |
#define | OCOTP_CTRL_CLR_WORDLOCK_SHIFT (15U) |
#define | OCOTP_CTRL_CLR_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WORDLOCK_SHIFT)) & OCOTP_CTRL_CLR_WORDLOCK_MASK) |
#define | OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) |
#define | OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) |
#define | OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) |
CTRL_TOG - OTP Controller Control and Status Register | |
#define | OCOTP_CTRL_TOG_ADDR_MASK (0x3FFU) |
#define | OCOTP_CTRL_TOG_ADDR_SHIFT (0U) |
#define | OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) |
#define | OCOTP_CTRL_TOG_BUSY_MASK (0x400U) |
#define | OCOTP_CTRL_TOG_BUSY_SHIFT (10U) |
#define | OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) |
#define | OCOTP_CTRL_TOG_ERROR_MASK (0x800U) |
#define | OCOTP_CTRL_TOG_ERROR_SHIFT (11U) |
#define | OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) |
#define | OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x1000U) |
#define | OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (12U) |
#define | OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) |
#define | OCOTP_CTRL_TOG_WORDLOCK_MASK (0x8000U) |
#define | OCOTP_CTRL_TOG_WORDLOCK_SHIFT (15U) |
#define | OCOTP_CTRL_TOG_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WORDLOCK_SHIFT)) & OCOTP_CTRL_TOG_WORDLOCK_MASK) |
#define | OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) |
#define | OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) |
#define | OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) |
PDN - OTP Controller PDN Register | |
#define | OCOTP_PDN_PDN_MASK (0x1U) |
#define | OCOTP_PDN_PDN_SHIFT (0U) |
#define | OCOTP_PDN_PDN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_PDN_PDN_SHIFT)) & OCOTP_PDN_PDN_MASK) |
DATA - OTP Controller Write Data Register | |
#define | OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) |
#define | OCOTP_DATA_DATA_SHIFT (0U) |
#define | OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) |
READ_CTRL - OTP Controller Read Control Register | |
#define | OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) |
#define | OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) |
#define | OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) |
#define | OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK (0x6U) |
#define | OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT (1U) |
#define | OCOTP_READ_CTRL_READ_FUSE_CNTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK) |
#define | OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK (0x8U) |
#define | OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT (3U) |
#define | OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK) |
#define | OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK (0x10U) |
#define | OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT (4U) |
#define | OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK) |
OUT_STATUS - 8K OTP Memory STATUS Register | |
#define | OCOTP_OUT_STATUS_SEC_MASK (0x200U) |
#define | OCOTP_OUT_STATUS_SEC_SHIFT (9U) |
#define | OCOTP_OUT_STATUS_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_SHIFT)) & OCOTP_OUT_STATUS_SEC_MASK) |
#define | OCOTP_OUT_STATUS_DED_MASK (0x400U) |
#define | OCOTP_OUT_STATUS_DED_SHIFT (10U) |
#define | OCOTP_OUT_STATUS_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_SHIFT)) & OCOTP_OUT_STATUS_DED_MASK) |
#define | OCOTP_OUT_STATUS_LOCKED_MASK (0x800U) |
#define | OCOTP_OUT_STATUS_LOCKED_SHIFT (11U) |
#define | OCOTP_OUT_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_LOCKED_MASK) |
#define | OCOTP_OUT_STATUS_PROGFAIL_MASK (0x1000U) |
#define | OCOTP_OUT_STATUS_PROGFAIL_SHIFT (12U) |
#define | OCOTP_OUT_STATUS_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_PROGFAIL_MASK) |
#define | OCOTP_OUT_STATUS_ACK_MASK (0x2000U) |
#define | OCOTP_OUT_STATUS_ACK_SHIFT (13U) |
#define | OCOTP_OUT_STATUS_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_ACK_SHIFT)) & OCOTP_OUT_STATUS_ACK_MASK) |
#define | OCOTP_OUT_STATUS_PWOK_MASK (0x4000U) |
#define | OCOTP_OUT_STATUS_PWOK_SHIFT (14U) |
#define | OCOTP_OUT_STATUS_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PWOK_SHIFT)) & OCOTP_OUT_STATUS_PWOK_MASK) |
#define | OCOTP_OUT_STATUS_FLAGSTATE_MASK (0x78000U) |
#define | OCOTP_OUT_STATUS_FLAGSTATE_SHIFT (15U) |
#define | OCOTP_OUT_STATUS_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_FLAGSTATE_MASK) |
#define | OCOTP_OUT_STATUS_SEC_RELOAD_MASK (0x80000U) |
#define | OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT (19U) |
#define | OCOTP_OUT_STATUS_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SEC_RELOAD_MASK) |
#define | OCOTP_OUT_STATUS_DED_RELOAD_MASK (0x100000U) |
#define | OCOTP_OUT_STATUS_DED_RELOAD_SHIFT (20U) |
#define | OCOTP_OUT_STATUS_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_DED_RELOAD_MASK) |
#define | OCOTP_OUT_STATUS_CALIBRATED_MASK (0x200000U) |
#define | OCOTP_OUT_STATUS_CALIBRATED_SHIFT (21U) |
#define | OCOTP_OUT_STATUS_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CALIBRATED_MASK) |
#define | OCOTP_OUT_STATUS_READ_DONE_INTR_MASK (0x400000U) |
#define | OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT (22U) |
#define | OCOTP_OUT_STATUS_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_DONE_INTR_MASK) |
#define | OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK (0x800000U) |
#define | OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT (23U) |
#define | OCOTP_OUT_STATUS_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK) |
#define | OCOTP_OUT_STATUS_DED0_MASK (0x1000000U) |
#define | OCOTP_OUT_STATUS_DED0_SHIFT (24U) |
#define | OCOTP_OUT_STATUS_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED0_SHIFT)) & OCOTP_OUT_STATUS_DED0_MASK) |
#define | OCOTP_OUT_STATUS_DED1_MASK (0x2000000U) |
#define | OCOTP_OUT_STATUS_DED1_SHIFT (25U) |
#define | OCOTP_OUT_STATUS_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED1_SHIFT)) & OCOTP_OUT_STATUS_DED1_MASK) |
#define | OCOTP_OUT_STATUS_DED2_MASK (0x4000000U) |
#define | OCOTP_OUT_STATUS_DED2_SHIFT (26U) |
#define | OCOTP_OUT_STATUS_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED2_SHIFT)) & OCOTP_OUT_STATUS_DED2_MASK) |
#define | OCOTP_OUT_STATUS_DED3_MASK (0x8000000U) |
#define | OCOTP_OUT_STATUS_DED3_SHIFT (27U) |
#define | OCOTP_OUT_STATUS_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED3_SHIFT)) & OCOTP_OUT_STATUS_DED3_MASK) |
OUT_STATUS_SET - 8K OTP Memory STATUS Register | |
#define | OCOTP_OUT_STATUS_SET_SEC_MASK (0x200U) |
#define | OCOTP_OUT_STATUS_SET_SEC_SHIFT (9U) |
#define | OCOTP_OUT_STATUS_SET_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_MASK) |
#define | OCOTP_OUT_STATUS_SET_DED_MASK (0x400U) |
#define | OCOTP_OUT_STATUS_SET_DED_SHIFT (10U) |
#define | OCOTP_OUT_STATUS_SET_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_MASK) |
#define | OCOTP_OUT_STATUS_SET_LOCKED_MASK (0x800U) |
#define | OCOTP_OUT_STATUS_SET_LOCKED_SHIFT (11U) |
#define | OCOTP_OUT_STATUS_SET_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_SET_LOCKED_MASK) |
#define | OCOTP_OUT_STATUS_SET_PROGFAIL_MASK (0x1000U) |
#define | OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT (12U) |
#define | OCOTP_OUT_STATUS_SET_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_SET_PROGFAIL_MASK) |
#define | OCOTP_OUT_STATUS_SET_ACK_MASK (0x2000U) |
#define | OCOTP_OUT_STATUS_SET_ACK_SHIFT (13U) |
#define | OCOTP_OUT_STATUS_SET_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_ACK_SHIFT)) & OCOTP_OUT_STATUS_SET_ACK_MASK) |
#define | OCOTP_OUT_STATUS_SET_PWOK_MASK (0x4000U) |
#define | OCOTP_OUT_STATUS_SET_PWOK_SHIFT (14U) |
#define | OCOTP_OUT_STATUS_SET_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PWOK_SHIFT)) & OCOTP_OUT_STATUS_SET_PWOK_MASK) |
#define | OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK (0x78000U) |
#define | OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT (15U) |
#define | OCOTP_OUT_STATUS_SET_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK) |
#define | OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK (0x80000U) |
#define | OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT (19U) |
#define | OCOTP_OUT_STATUS_SET_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK) |
#define | OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK (0x100000U) |
#define | OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT (20U) |
#define | OCOTP_OUT_STATUS_SET_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK) |
#define | OCOTP_OUT_STATUS_SET_CALIBRATED_MASK (0x200000U) |
#define | OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT (21U) |
#define | OCOTP_OUT_STATUS_SET_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_SET_CALIBRATED_MASK) |
#define | OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK (0x400000U) |
#define | OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT (22U) |
#define | OCOTP_OUT_STATUS_SET_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK) |
#define | OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK (0x800000U) |
#define | OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT (23U) |
#define | OCOTP_OUT_STATUS_SET_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK) |
#define | OCOTP_OUT_STATUS_SET_DED0_MASK (0x1000000U) |
#define | OCOTP_OUT_STATUS_SET_DED0_SHIFT (24U) |
#define | OCOTP_OUT_STATUS_SET_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED0_SHIFT)) & OCOTP_OUT_STATUS_SET_DED0_MASK) |
#define | OCOTP_OUT_STATUS_SET_DED1_MASK (0x2000000U) |
#define | OCOTP_OUT_STATUS_SET_DED1_SHIFT (25U) |
#define | OCOTP_OUT_STATUS_SET_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED1_SHIFT)) & OCOTP_OUT_STATUS_SET_DED1_MASK) |
#define | OCOTP_OUT_STATUS_SET_DED2_MASK (0x4000000U) |
#define | OCOTP_OUT_STATUS_SET_DED2_SHIFT (26U) |
#define | OCOTP_OUT_STATUS_SET_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED2_SHIFT)) & OCOTP_OUT_STATUS_SET_DED2_MASK) |
#define | OCOTP_OUT_STATUS_SET_DED3_MASK (0x8000000U) |
#define | OCOTP_OUT_STATUS_SET_DED3_SHIFT (27U) |
#define | OCOTP_OUT_STATUS_SET_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED3_SHIFT)) & OCOTP_OUT_STATUS_SET_DED3_MASK) |
OUT_STATUS_CLR - 8K OTP Memory STATUS Register | |
#define | OCOTP_OUT_STATUS_CLR_SEC_MASK (0x200U) |
#define | OCOTP_OUT_STATUS_CLR_SEC_SHIFT (9U) |
#define | OCOTP_OUT_STATUS_CLR_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_MASK) |
#define | OCOTP_OUT_STATUS_CLR_DED_MASK (0x400U) |
#define | OCOTP_OUT_STATUS_CLR_DED_SHIFT (10U) |
#define | OCOTP_OUT_STATUS_CLR_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_MASK) |
#define | OCOTP_OUT_STATUS_CLR_LOCKED_MASK (0x800U) |
#define | OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT (11U) |
#define | OCOTP_OUT_STATUS_CLR_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_CLR_LOCKED_MASK) |
#define | OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK (0x1000U) |
#define | OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT (12U) |
#define | OCOTP_OUT_STATUS_CLR_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK) |
#define | OCOTP_OUT_STATUS_CLR_ACK_MASK (0x2000U) |
#define | OCOTP_OUT_STATUS_CLR_ACK_SHIFT (13U) |
#define | OCOTP_OUT_STATUS_CLR_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_ACK_SHIFT)) & OCOTP_OUT_STATUS_CLR_ACK_MASK) |
#define | OCOTP_OUT_STATUS_CLR_PWOK_MASK (0x4000U) |
#define | OCOTP_OUT_STATUS_CLR_PWOK_SHIFT (14U) |
#define | OCOTP_OUT_STATUS_CLR_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PWOK_SHIFT)) & OCOTP_OUT_STATUS_CLR_PWOK_MASK) |
#define | OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK (0x78000U) |
#define | OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT (15U) |
#define | OCOTP_OUT_STATUS_CLR_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK) |
#define | OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK (0x80000U) |
#define | OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT (19U) |
#define | OCOTP_OUT_STATUS_CLR_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK) |
#define | OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK (0x100000U) |
#define | OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT (20U) |
#define | OCOTP_OUT_STATUS_CLR_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK) |
#define | OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK (0x200000U) |
#define | OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT (21U) |
#define | OCOTP_OUT_STATUS_CLR_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK) |
#define | OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK (0x400000U) |
#define | OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT (22U) |
#define | OCOTP_OUT_STATUS_CLR_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK) |
#define | OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK (0x800000U) |
#define | OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT (23U) |
#define | OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK) |
#define | OCOTP_OUT_STATUS_CLR_DED0_MASK (0x1000000U) |
#define | OCOTP_OUT_STATUS_CLR_DED0_SHIFT (24U) |
#define | OCOTP_OUT_STATUS_CLR_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED0_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED0_MASK) |
#define | OCOTP_OUT_STATUS_CLR_DED1_MASK (0x2000000U) |
#define | OCOTP_OUT_STATUS_CLR_DED1_SHIFT (25U) |
#define | OCOTP_OUT_STATUS_CLR_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED1_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED1_MASK) |
#define | OCOTP_OUT_STATUS_CLR_DED2_MASK (0x4000000U) |
#define | OCOTP_OUT_STATUS_CLR_DED2_SHIFT (26U) |
#define | OCOTP_OUT_STATUS_CLR_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED2_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED2_MASK) |
#define | OCOTP_OUT_STATUS_CLR_DED3_MASK (0x8000000U) |
#define | OCOTP_OUT_STATUS_CLR_DED3_SHIFT (27U) |
#define | OCOTP_OUT_STATUS_CLR_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED3_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED3_MASK) |
OUT_STATUS_TOG - 8K OTP Memory STATUS Register | |
#define | OCOTP_OUT_STATUS_TOG_SEC_MASK (0x200U) |
#define | OCOTP_OUT_STATUS_TOG_SEC_SHIFT (9U) |
#define | OCOTP_OUT_STATUS_TOG_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_MASK) |
#define | OCOTP_OUT_STATUS_TOG_DED_MASK (0x400U) |
#define | OCOTP_OUT_STATUS_TOG_DED_SHIFT (10U) |
#define | OCOTP_OUT_STATUS_TOG_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_MASK) |
#define | OCOTP_OUT_STATUS_TOG_LOCKED_MASK (0x800U) |
#define | OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT (11U) |
#define | OCOTP_OUT_STATUS_TOG_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_TOG_LOCKED_MASK) |
#define | OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK (0x1000U) |
#define | OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT (12U) |
#define | OCOTP_OUT_STATUS_TOG_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK) |
#define | OCOTP_OUT_STATUS_TOG_ACK_MASK (0x2000U) |
#define | OCOTP_OUT_STATUS_TOG_ACK_SHIFT (13U) |
#define | OCOTP_OUT_STATUS_TOG_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_ACK_SHIFT)) & OCOTP_OUT_STATUS_TOG_ACK_MASK) |
#define | OCOTP_OUT_STATUS_TOG_PWOK_MASK (0x4000U) |
#define | OCOTP_OUT_STATUS_TOG_PWOK_SHIFT (14U) |
#define | OCOTP_OUT_STATUS_TOG_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PWOK_SHIFT)) & OCOTP_OUT_STATUS_TOG_PWOK_MASK) |
#define | OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK (0x78000U) |
#define | OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT (15U) |
#define | OCOTP_OUT_STATUS_TOG_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK) |
#define | OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK (0x80000U) |
#define | OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT (19U) |
#define | OCOTP_OUT_STATUS_TOG_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK) |
#define | OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK (0x100000U) |
#define | OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT (20U) |
#define | OCOTP_OUT_STATUS_TOG_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK) |
#define | OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK (0x200000U) |
#define | OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT (21U) |
#define | OCOTP_OUT_STATUS_TOG_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK) |
#define | OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK (0x400000U) |
#define | OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT (22U) |
#define | OCOTP_OUT_STATUS_TOG_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK) |
#define | OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK (0x800000U) |
#define | OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT (23U) |
#define | OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK) |
#define | OCOTP_OUT_STATUS_TOG_DED0_MASK (0x1000000U) |
#define | OCOTP_OUT_STATUS_TOG_DED0_SHIFT (24U) |
#define | OCOTP_OUT_STATUS_TOG_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED0_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED0_MASK) |
#define | OCOTP_OUT_STATUS_TOG_DED1_MASK (0x2000000U) |
#define | OCOTP_OUT_STATUS_TOG_DED1_SHIFT (25U) |
#define | OCOTP_OUT_STATUS_TOG_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED1_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED1_MASK) |
#define | OCOTP_OUT_STATUS_TOG_DED2_MASK (0x4000000U) |
#define | OCOTP_OUT_STATUS_TOG_DED2_SHIFT (26U) |
#define | OCOTP_OUT_STATUS_TOG_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED2_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED2_MASK) |
#define | OCOTP_OUT_STATUS_TOG_DED3_MASK (0x8000000U) |
#define | OCOTP_OUT_STATUS_TOG_DED3_SHIFT (27U) |
#define | OCOTP_OUT_STATUS_TOG_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED3_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED3_MASK) |
VERSION - OTP Controller Version Register | |
#define | OCOTP_VERSION_STEP_MASK (0xFFFFU) |
#define | OCOTP_VERSION_STEP_SHIFT (0U) |
#define | OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) |
#define | OCOTP_VERSION_MINOR_MASK (0xFF0000U) |
#define | OCOTP_VERSION_MINOR_SHIFT (16U) |
#define | OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) |
#define | OCOTP_VERSION_MAJOR_MASK (0xFF000000U) |
#define | OCOTP_VERSION_MAJOR_SHIFT (24U) |
#define | OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) |
READ_FUSE_DATA - OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register | |
#define | OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) |
#define | OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) |
#define | OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) |
SW_LOCK - SW_LOCK Register | |
#define | OCOTP_SW_LOCK_SW_LOCK_MASK (0xFFFFFFFFU) |
#define | OCOTP_SW_LOCK_SW_LOCK_SHIFT (0U) |
#define | OCOTP_SW_LOCK_SW_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_LOCK_SW_LOCK_SHIFT)) & OCOTP_SW_LOCK_SW_LOCK_MASK) |
BIT_LOCK - BIT_LOCK Register | |
#define | OCOTP_BIT_LOCK_BIT_LOCK_MASK (0xFFFFFFFFU) |
#define | OCOTP_BIT_LOCK_BIT_LOCK_SHIFT (0U) |
#define | OCOTP_BIT_LOCK_BIT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BIT_LOCK_BIT_LOCK_SHIFT)) & OCOTP_BIT_LOCK_BIT_LOCK_MASK) |
LOCKED0 - OTP Controller Program Locked Status 0 Register | |
#define | OCOTP_LOCKED0_LOCKED_MASK (0xFFFFU) |
#define | OCOTP_LOCKED0_LOCKED_SHIFT (0U) |
#define | OCOTP_LOCKED0_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED0_LOCKED_SHIFT)) & OCOTP_LOCKED0_LOCKED_MASK) |
LOCKED1 - OTP Controller Program Locked Status 1 Register | |
#define | OCOTP_LOCKED1_LOCKED_MASK (0xFFFFFFFFU) |
#define | OCOTP_LOCKED1_LOCKED_SHIFT (0U) |
#define | OCOTP_LOCKED1_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED1_LOCKED_SHIFT)) & OCOTP_LOCKED1_LOCKED_MASK) |
LOCKED2 - OTP Controller Program Locked Status 2 Register | |
#define | OCOTP_LOCKED2_LOCKED_MASK (0xFFFFFFFFU) |
#define | OCOTP_LOCKED2_LOCKED_SHIFT (0U) |
#define | OCOTP_LOCKED2_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED2_LOCKED_SHIFT)) & OCOTP_LOCKED2_LOCKED_MASK) |
LOCKED3 - OTP Controller Program Locked Status 3 Register | |
#define | OCOTP_LOCKED3_LOCKED_MASK (0xFFFFFFFFU) |
#define | OCOTP_LOCKED3_LOCKED_SHIFT (0U) |
#define | OCOTP_LOCKED3_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED3_LOCKED_SHIFT)) & OCOTP_LOCKED3_LOCKED_MASK) |
LOCKED4 - OTP Controller Program Locked Status 4 Register | |
#define | OCOTP_LOCKED4_LOCKED_MASK (0xFFFFFFFFU) |
#define | OCOTP_LOCKED4_LOCKED_SHIFT (0U) |
#define | OCOTP_LOCKED4_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED4_LOCKED_SHIFT)) & OCOTP_LOCKED4_LOCKED_MASK) |
FUSE - Value of fuse word 0..Value of fuse word 143 | |
#define | OCOTP_FUSE_BITS_MASK (0xFFFFFFFFU) |
#define | OCOTP_FUSE_BITS_SHIFT (0U) |
#define | OCOTP_FUSE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE_BITS_SHIFT)) & OCOTP_FUSE_BITS_MASK) |
CTRL0 - Control Register 0 | |
#define | OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK (0x3F000000U) |
#define | OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT (24U) |
#define | OSC_RC_400M_CTRL0_REF_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT)) & OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK) |
CTRL1 - Control Register 1 | |
#define | OSC_RC_400M_CTRL1_HYST_MINUS_MASK (0xFU) |
#define | OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT (0U) |
#define | OSC_RC_400M_CTRL1_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_MINUS_MASK) |
#define | OSC_RC_400M_CTRL1_HYST_PLUS_MASK (0xF00U) |
#define | OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT (8U) |
#define | OSC_RC_400M_CTRL1_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_PLUS_MASK) |
#define | OSC_RC_400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) |
#define | OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT (16U) |
#define | OSC_RC_400M_CTRL1_TARGET_COUNT(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT)) & OSC_RC_400M_CTRL1_TARGET_COUNT_MASK) |
CTRL2 - Control Register 2 | |
#define | OSC_RC_400M_CTRL2_TUNE_BYP_MASK (0x400U) |
#define | OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT (10U) |
#define | OSC_RC_400M_CTRL2_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_BYP_MASK) |
#define | OSC_RC_400M_CTRL2_TUNE_EN_MASK (0x1000U) |
#define | OSC_RC_400M_CTRL2_TUNE_EN_SHIFT (12U) |
#define | OSC_RC_400M_CTRL2_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_EN_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_EN_MASK) |
#define | OSC_RC_400M_CTRL2_TUNE_START_MASK (0x4000U) |
#define | OSC_RC_400M_CTRL2_TUNE_START_SHIFT (14U) |
#define | OSC_RC_400M_CTRL2_TUNE_START(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_START_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_START_MASK) |
#define | OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) |
#define | OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U) |
#define | OSC_RC_400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK) |
CTRL3 - Control Register 3 | |
#define | OSC_RC_400M_CTRL3_CLR_ERR_MASK (0x1U) |
#define | OSC_RC_400M_CTRL3_CLR_ERR_SHIFT (0U) |
#define | OSC_RC_400M_CTRL3_CLR_ERR(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_CLR_ERR_SHIFT)) & OSC_RC_400M_CTRL3_CLR_ERR_MASK) |
#define | OSC_RC_400M_CTRL3_EN_1M_CLK_MASK (0x100U) |
#define | OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT (8U) |
#define | OSC_RC_400M_CTRL3_EN_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_EN_1M_CLK_MASK) |
#define | OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK (0x400U) |
#define | OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT (10U) |
#define | OSC_RC_400M_CTRL3_MUX_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK) |
#define | OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK (0xFFFF0000U) |
#define | OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT (16U) |
#define | OSC_RC_400M_CTRL3_COUNT_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK) |
STAT0 - Status Register 0 | |
#define | OSC_RC_400M_STAT0_CLK1M_ERR_MASK (0x1U) |
#define | OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT (0U) |
#define | OSC_RC_400M_STAT0_CLK1M_ERR(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT)) & OSC_RC_400M_STAT0_CLK1M_ERR_MASK) |
STAT1 - Status Register 1 | |
#define | OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK (0xFFFF0000U) |
#define | OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT (16U) |
#define | OSC_RC_400M_STAT1_CURR_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT)) & OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK) |
STAT2 - Status Register 2 | |
#define | OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U) |
#define | OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U) |
#define | OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK) |
SR - Status Register | |
#define | OTFAD_SR_KBERR_MASK (0x1U) |
#define | OTFAD_SR_KBERR_SHIFT (0U) |
#define | OTFAD_SR_KBERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK) |
#define | OTFAD_SR_MDPCP_MASK (0x2U) |
#define | OTFAD_SR_MDPCP_SHIFT (1U) |
#define | OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK) |
#define | OTFAD_SR_MODE_MASK (0xCU) |
#define | OTFAD_SR_MODE_SHIFT (2U) |
#define | OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK) |
#define | OTFAD_SR_NCTX_MASK (0xF0U) |
#define | OTFAD_SR_NCTX_SHIFT (4U) |
#define | OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK) |
#define | OTFAD_SR_CTXER0_MASK (0x100U) |
#define | OTFAD_SR_CTXER0_SHIFT (8U) |
#define | OTFAD_SR_CTXER0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK) |
#define | OTFAD_SR_CTXER1_MASK (0x200U) |
#define | OTFAD_SR_CTXER1_SHIFT (9U) |
#define | OTFAD_SR_CTXER1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK) |
#define | OTFAD_SR_CTXER2_MASK (0x400U) |
#define | OTFAD_SR_CTXER2_SHIFT (10U) |
#define | OTFAD_SR_CTXER2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK) |
#define | OTFAD_SR_CTXER3_MASK (0x800U) |
#define | OTFAD_SR_CTXER3_SHIFT (11U) |
#define | OTFAD_SR_CTXER3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK) |
#define | OTFAD_SR_CTXIE0_MASK (0x10000U) |
#define | OTFAD_SR_CTXIE0_SHIFT (16U) |
#define | OTFAD_SR_CTXIE0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK) |
#define | OTFAD_SR_CTXIE1_MASK (0x20000U) |
#define | OTFAD_SR_CTXIE1_SHIFT (17U) |
#define | OTFAD_SR_CTXIE1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK) |
#define | OTFAD_SR_CTXIE2_MASK (0x40000U) |
#define | OTFAD_SR_CTXIE2_SHIFT (18U) |
#define | OTFAD_SR_CTXIE2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK) |
#define | OTFAD_SR_CTXIE3_MASK (0x80000U) |
#define | OTFAD_SR_CTXIE3_SHIFT (19U) |
#define | OTFAD_SR_CTXIE3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK) |
#define | OTFAD_SR_HRL_MASK (0xF000000U) |
#define | OTFAD_SR_HRL_SHIFT (24U) |
#define | OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK) |
#define | OTFAD_SR_RRAM_MASK (0x10000000U) |
#define | OTFAD_SR_RRAM_SHIFT (28U) |
#define | OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK) |
#define | OTFAD_SR_GEM_MASK (0x20000000U) |
#define | OTFAD_SR_GEM_SHIFT (29U) |
#define | OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK) |
#define | OTFAD_SR_KBPE_MASK (0x40000000U) |
#define | OTFAD_SR_KBPE_SHIFT (30U) |
#define | OTFAD_SR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK) |
#define | OTFAD_SR_KBD_MASK (0x80000000U) |
#define | OTFAD_SR_KBD_SHIFT (31U) |
#define | OTFAD_SR_KBD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK) |
#define | XRDC2_SR_DIN_MASK (0xFU) |
#define | XRDC2_SR_DIN_SHIFT (0U) |
#define | XRDC2_SR_DIN(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK) |
#define | XRDC2_SR_HRL_MASK (0xF0U) |
#define | XRDC2_SR_HRL_SHIFT (4U) |
#define | XRDC2_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK) |
#define | XRDC2_SR_GCLO_MASK (0xF00U) |
#define | XRDC2_SR_GCLO_SHIFT (8U) |
#define | XRDC2_SR_GCLO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK) |
KEY - AES Key Word | |
#define | OTFAD_KEY_KEY_MASK (0xFFFFFFFFU) |
#define | OTFAD_KEY_KEY_SHIFT (0U) |
#define | OTFAD_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK) |
CTR - AES Counter Word | |
#define | OTFAD_CTR_CTR_MASK (0xFFFFFFFFU) |
#define | OTFAD_CTR_CTR_SHIFT (0U) |
#define | OTFAD_CTR_CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK) |
RGD_W0 - AES Region Descriptor Word0 | |
#define | OTFAD_RGD_W0_SRTADDR_MASK (0xFFFFFC00U) |
#define | OTFAD_RGD_W0_SRTADDR_SHIFT (10U) |
#define | OTFAD_RGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK) |
RGD_W1 - AES Region Descriptor Word1 | |
#define | OTFAD_RGD_W1_VLD_MASK (0x1U) |
#define | OTFAD_RGD_W1_VLD_SHIFT (0U) |
#define | OTFAD_RGD_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK) |
#define | OTFAD_RGD_W1_ADE_MASK (0x2U) |
#define | OTFAD_RGD_W1_ADE_SHIFT (1U) |
#define | OTFAD_RGD_W1_ADE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK) |
#define | OTFAD_RGD_W1_RO_MASK (0x4U) |
#define | OTFAD_RGD_W1_RO_SHIFT (2U) |
#define | OTFAD_RGD_W1_RO(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK) |
#define | OTFAD_RGD_W1_ENDADDR_MASK (0xFFFFFC00U) |
#define | OTFAD_RGD_W1_ENDADDR_SHIFT (10U) |
#define | OTFAD_RGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK) |
CTRL_1 - PDM Control register 1 | |
#define | PDM_CTRL_1_CH0EN_MASK (0x1U) |
#define | PDM_CTRL_1_CH0EN_SHIFT (0U) |
#define | PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK) |
#define | PDM_CTRL_1_CH1EN_MASK (0x2U) |
#define | PDM_CTRL_1_CH1EN_SHIFT (1U) |
#define | PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK) |
#define | PDM_CTRL_1_CH2EN_MASK (0x4U) |
#define | PDM_CTRL_1_CH2EN_SHIFT (2U) |
#define | PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK) |
#define | PDM_CTRL_1_CH3EN_MASK (0x8U) |
#define | PDM_CTRL_1_CH3EN_SHIFT (3U) |
#define | PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK) |
#define | PDM_CTRL_1_CH4EN_MASK (0x10U) |
#define | PDM_CTRL_1_CH4EN_SHIFT (4U) |
#define | PDM_CTRL_1_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK) |
#define | PDM_CTRL_1_CH5EN_MASK (0x20U) |
#define | PDM_CTRL_1_CH5EN_SHIFT (5U) |
#define | PDM_CTRL_1_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK) |
#define | PDM_CTRL_1_CH6EN_MASK (0x40U) |
#define | PDM_CTRL_1_CH6EN_SHIFT (6U) |
#define | PDM_CTRL_1_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK) |
#define | PDM_CTRL_1_CH7EN_MASK (0x80U) |
#define | PDM_CTRL_1_CH7EN_SHIFT (7U) |
#define | PDM_CTRL_1_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK) |
#define | PDM_CTRL_1_ERREN_MASK (0x800000U) |
#define | PDM_CTRL_1_ERREN_SHIFT (23U) |
#define | PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK) |
#define | PDM_CTRL_1_DISEL_MASK (0x3000000U) |
#define | PDM_CTRL_1_DISEL_SHIFT (24U) |
#define | PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK) |
#define | PDM_CTRL_1_DBGE_MASK (0x4000000U) |
#define | PDM_CTRL_1_DBGE_SHIFT (26U) |
#define | PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK) |
#define | PDM_CTRL_1_SRES_MASK (0x8000000U) |
#define | PDM_CTRL_1_SRES_SHIFT (27U) |
#define | PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK) |
#define | PDM_CTRL_1_DBG_MASK (0x10000000U) |
#define | PDM_CTRL_1_DBG_SHIFT (28U) |
#define | PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK) |
#define | PDM_CTRL_1_PDMIEN_MASK (0x20000000U) |
#define | PDM_CTRL_1_PDMIEN_SHIFT (29U) |
#define | PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK) |
#define | PDM_CTRL_1_DOZEN_MASK (0x40000000U) |
#define | PDM_CTRL_1_DOZEN_SHIFT (30U) |
#define | PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) |
#define | PDM_CTRL_1_MDIS_MASK (0x80000000U) |
#define | PDM_CTRL_1_MDIS_SHIFT (31U) |
#define | PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK) |
CTRL_2 - PDM Control register 2 | |
#define | PDM_CTRL_2_CLKDIV_MASK (0xFFU) |
#define | PDM_CTRL_2_CLKDIV_SHIFT (0U) |
#define | PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) |
#define | PDM_CTRL_2_CICOSR_MASK (0xF0000U) |
#define | PDM_CTRL_2_CICOSR_SHIFT (16U) |
#define | PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) |
#define | PDM_CTRL_2_QSEL_MASK (0xE000000U) |
#define | PDM_CTRL_2_QSEL_SHIFT (25U) |
#define | PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK) |
STAT - PDM Status register | |
#define | PDM_STAT_CH0F_MASK (0x1U) |
#define | PDM_STAT_CH0F_SHIFT (0U) |
#define | PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK) |
#define | PDM_STAT_CH1F_MASK (0x2U) |
#define | PDM_STAT_CH1F_SHIFT (1U) |
#define | PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK) |
#define | PDM_STAT_CH2F_MASK (0x4U) |
#define | PDM_STAT_CH2F_SHIFT (2U) |
#define | PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK) |
#define | PDM_STAT_CH3F_MASK (0x8U) |
#define | PDM_STAT_CH3F_SHIFT (3U) |
#define | PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK) |
#define | PDM_STAT_CH4F_MASK (0x10U) |
#define | PDM_STAT_CH4F_SHIFT (4U) |
#define | PDM_STAT_CH4F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK) |
#define | PDM_STAT_CH5F_MASK (0x20U) |
#define | PDM_STAT_CH5F_SHIFT (5U) |
#define | PDM_STAT_CH5F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK) |
#define | PDM_STAT_CH6F_MASK (0x40U) |
#define | PDM_STAT_CH6F_SHIFT (6U) |
#define | PDM_STAT_CH6F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK) |
#define | PDM_STAT_CH7F_MASK (0x80U) |
#define | PDM_STAT_CH7F_SHIFT (7U) |
#define | PDM_STAT_CH7F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK) |
#define | PDM_STAT_LOWFREQF_MASK (0x20000000U) |
#define | PDM_STAT_LOWFREQF_SHIFT (29U) |
#define | PDM_STAT_LOWFREQF(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK) |
#define | PDM_STAT_FIR_RDY_MASK (0x40000000U) |
#define | PDM_STAT_FIR_RDY_SHIFT (30U) |
#define | PDM_STAT_FIR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK) |
#define | PDM_STAT_BSY_FIL_MASK (0x80000000U) |
#define | PDM_STAT_BSY_FIL_SHIFT (31U) |
#define | PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK) |
FIFO_CTRL - PDM FIFO Control register | |
#define | PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) |
#define | PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U) |
#define | PDM_FIFO_CTRL_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK) |
FIFO_STAT - PDM FIFO Status register | |
#define | PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U) |
#define | PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U) |
#define | PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK) |
#define | PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U) |
#define | PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U) |
#define | PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK) |
#define | PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U) |
#define | PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U) |
#define | PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK) |
#define | PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U) |
#define | PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U) |
#define | PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK) |
#define | PDM_FIFO_STAT_FIFOOVF4_MASK (0x10U) |
#define | PDM_FIFO_STAT_FIFOOVF4_SHIFT (4U) |
#define | PDM_FIFO_STAT_FIFOOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK) |
#define | PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) |
#define | PDM_FIFO_STAT_FIFOOVF5_SHIFT (5U) |
#define | PDM_FIFO_STAT_FIFOOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK) |
#define | PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) |
#define | PDM_FIFO_STAT_FIFOOVF6_SHIFT (6U) |
#define | PDM_FIFO_STAT_FIFOOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK) |
#define | PDM_FIFO_STAT_FIFOOVF7_MASK (0x80U) |
#define | PDM_FIFO_STAT_FIFOOVF7_SHIFT (7U) |
#define | PDM_FIFO_STAT_FIFOOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK) |
#define | PDM_FIFO_STAT_FIFOUND0_MASK (0x100U) |
#define | PDM_FIFO_STAT_FIFOUND0_SHIFT (8U) |
#define | PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK) |
#define | PDM_FIFO_STAT_FIFOUND1_MASK (0x200U) |
#define | PDM_FIFO_STAT_FIFOUND1_SHIFT (9U) |
#define | PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK) |
#define | PDM_FIFO_STAT_FIFOUND2_MASK (0x400U) |
#define | PDM_FIFO_STAT_FIFOUND2_SHIFT (10U) |
#define | PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK) |
#define | PDM_FIFO_STAT_FIFOUND3_MASK (0x800U) |
#define | PDM_FIFO_STAT_FIFOUND3_SHIFT (11U) |
#define | PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK) |
#define | PDM_FIFO_STAT_FIFOUND4_MASK (0x1000U) |
#define | PDM_FIFO_STAT_FIFOUND4_SHIFT (12U) |
#define | PDM_FIFO_STAT_FIFOUND4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK) |
#define | PDM_FIFO_STAT_FIFOUND5_MASK (0x2000U) |
#define | PDM_FIFO_STAT_FIFOUND5_SHIFT (13U) |
#define | PDM_FIFO_STAT_FIFOUND5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK) |
#define | PDM_FIFO_STAT_FIFOUND6_MASK (0x4000U) |
#define | PDM_FIFO_STAT_FIFOUND6_SHIFT (14U) |
#define | PDM_FIFO_STAT_FIFOUND6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK) |
#define | PDM_FIFO_STAT_FIFOUND7_MASK (0x8000U) |
#define | PDM_FIFO_STAT_FIFOUND7_SHIFT (15U) |
#define | PDM_FIFO_STAT_FIFOUND7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK) |
DATACH - PDM Output Result Register | |
#define | PDM_DATACH_DATA_MASK (0xFFFFFFFFU) |
#define | PDM_DATACH_DATA_SHIFT (0U) |
#define | PDM_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK) |
DC_CTRL - PDM DC Remover Control register | |
#define | PDM_DC_CTRL_DCCONFIG0_MASK (0x3U) |
#define | PDM_DC_CTRL_DCCONFIG0_SHIFT (0U) |
#define | PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK) |
#define | PDM_DC_CTRL_DCCONFIG1_MASK (0xCU) |
#define | PDM_DC_CTRL_DCCONFIG1_SHIFT (2U) |
#define | PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK) |
#define | PDM_DC_CTRL_DCCONFIG2_MASK (0x30U) |
#define | PDM_DC_CTRL_DCCONFIG2_SHIFT (4U) |
#define | PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK) |
#define | PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U) |
#define | PDM_DC_CTRL_DCCONFIG3_SHIFT (6U) |
#define | PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK) |
#define | PDM_DC_CTRL_DCCONFIG4_MASK (0x300U) |
#define | PDM_DC_CTRL_DCCONFIG4_SHIFT (8U) |
#define | PDM_DC_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK) |
#define | PDM_DC_CTRL_DCCONFIG5_MASK (0xC00U) |
#define | PDM_DC_CTRL_DCCONFIG5_SHIFT (10U) |
#define | PDM_DC_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK) |
#define | PDM_DC_CTRL_DCCONFIG6_MASK (0x3000U) |
#define | PDM_DC_CTRL_DCCONFIG6_SHIFT (12U) |
#define | PDM_DC_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK) |
#define | PDM_DC_CTRL_DCCONFIG7_MASK (0xC000U) |
#define | PDM_DC_CTRL_DCCONFIG7_SHIFT (14U) |
#define | PDM_DC_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK) |
RANGE_CTRL - PDM Range Control register | |
#define | PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU) |
#define | PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U) |
#define | PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK) |
#define | PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U) |
#define | PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U) |
#define | PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK) |
#define | PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U) |
#define | PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U) |
#define | PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK) |
#define | PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U) |
#define | PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U) |
#define | PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK) |
#define | PDM_RANGE_CTRL_RANGEADJ4_MASK (0xF0000U) |
#define | PDM_RANGE_CTRL_RANGEADJ4_SHIFT (16U) |
#define | PDM_RANGE_CTRL_RANGEADJ4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK) |
#define | PDM_RANGE_CTRL_RANGEADJ5_MASK (0xF00000U) |
#define | PDM_RANGE_CTRL_RANGEADJ5_SHIFT (20U) |
#define | PDM_RANGE_CTRL_RANGEADJ5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK) |
#define | PDM_RANGE_CTRL_RANGEADJ6_MASK (0xF000000U) |
#define | PDM_RANGE_CTRL_RANGEADJ6_SHIFT (24U) |
#define | PDM_RANGE_CTRL_RANGEADJ6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK) |
#define | PDM_RANGE_CTRL_RANGEADJ7_MASK (0xF0000000U) |
#define | PDM_RANGE_CTRL_RANGEADJ7_SHIFT (28U) |
#define | PDM_RANGE_CTRL_RANGEADJ7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK) |
RANGE_STAT - PDM Range Status register | |
#define | PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U) |
#define | PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U) |
#define | PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK) |
#define | PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U) |
#define | PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U) |
#define | PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK) |
#define | PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U) |
#define | PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U) |
#define | PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK) |
#define | PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U) |
#define | PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U) |
#define | PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK) |
#define | PDM_RANGE_STAT_RANGEOVF4_MASK (0x10U) |
#define | PDM_RANGE_STAT_RANGEOVF4_SHIFT (4U) |
#define | PDM_RANGE_STAT_RANGEOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK) |
#define | PDM_RANGE_STAT_RANGEOVF5_MASK (0x20U) |
#define | PDM_RANGE_STAT_RANGEOVF5_SHIFT (5U) |
#define | PDM_RANGE_STAT_RANGEOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK) |
#define | PDM_RANGE_STAT_RANGEOVF6_MASK (0x40U) |
#define | PDM_RANGE_STAT_RANGEOVF6_SHIFT (6U) |
#define | PDM_RANGE_STAT_RANGEOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK) |
#define | PDM_RANGE_STAT_RANGEOVF7_MASK (0x80U) |
#define | PDM_RANGE_STAT_RANGEOVF7_SHIFT (7U) |
#define | PDM_RANGE_STAT_RANGEOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK) |
#define | PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U) |
#define | PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U) |
#define | PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK) |
#define | PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U) |
#define | PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U) |
#define | PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK) |
#define | PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U) |
#define | PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U) |
#define | PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK) |
#define | PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U) |
#define | PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U) |
#define | PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK) |
#define | PDM_RANGE_STAT_RANGEUNF4_MASK (0x100000U) |
#define | PDM_RANGE_STAT_RANGEUNF4_SHIFT (20U) |
#define | PDM_RANGE_STAT_RANGEUNF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK) |
#define | PDM_RANGE_STAT_RANGEUNF5_MASK (0x200000U) |
#define | PDM_RANGE_STAT_RANGEUNF5_SHIFT (21U) |
#define | PDM_RANGE_STAT_RANGEUNF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK) |
#define | PDM_RANGE_STAT_RANGEUNF6_MASK (0x400000U) |
#define | PDM_RANGE_STAT_RANGEUNF6_SHIFT (22U) |
#define | PDM_RANGE_STAT_RANGEUNF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK) |
#define | PDM_RANGE_STAT_RANGEUNF7_MASK (0x800000U) |
#define | PDM_RANGE_STAT_RANGEUNF7_SHIFT (23U) |
#define | PDM_RANGE_STAT_RANGEUNF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK) |
VAD0_CTRL_1 - Voice Activity Detector 0 Control register | |
#define | PDM_VAD0_CTRL_1_VADEN_MASK (0x1U) |
#define | PDM_VAD0_CTRL_1_VADEN_SHIFT (0U) |
#define | PDM_VAD0_CTRL_1_VADEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK) |
#define | PDM_VAD0_CTRL_1_VADRST_MASK (0x2U) |
#define | PDM_VAD0_CTRL_1_VADRST_SHIFT (1U) |
#define | PDM_VAD0_CTRL_1_VADRST(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK) |
#define | PDM_VAD0_CTRL_1_VADIE_MASK (0x4U) |
#define | PDM_VAD0_CTRL_1_VADIE_SHIFT (2U) |
#define | PDM_VAD0_CTRL_1_VADIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK) |
#define | PDM_VAD0_CTRL_1_VADERIE_MASK (0x8U) |
#define | PDM_VAD0_CTRL_1_VADERIE_SHIFT (3U) |
#define | PDM_VAD0_CTRL_1_VADERIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK) |
#define | PDM_VAD0_CTRL_1_VADST10_MASK (0x10U) |
#define | PDM_VAD0_CTRL_1_VADST10_SHIFT (4U) |
#define | PDM_VAD0_CTRL_1_VADST10(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK) |
#define | PDM_VAD0_CTRL_1_VADINITT_MASK (0x1F00U) |
#define | PDM_VAD0_CTRL_1_VADINITT_SHIFT (8U) |
#define | PDM_VAD0_CTRL_1_VADINITT(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK) |
#define | PDM_VAD0_CTRL_1_VADCICOSR_MASK (0xF0000U) |
#define | PDM_VAD0_CTRL_1_VADCICOSR_SHIFT (16U) |
#define | PDM_VAD0_CTRL_1_VADCICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK) |
#define | PDM_VAD0_CTRL_1_VADCHSEL_MASK (0x7000000U) |
#define | PDM_VAD0_CTRL_1_VADCHSEL_SHIFT (24U) |
#define | PDM_VAD0_CTRL_1_VADCHSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK) |
VAD0_CTRL_2 - Voice Activity Detector 0 Control register | |
#define | PDM_VAD0_CTRL_2_VADHPF_MASK (0x3U) |
#define | PDM_VAD0_CTRL_2_VADHPF_SHIFT (0U) |
#define | PDM_VAD0_CTRL_2_VADHPF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK) |
#define | PDM_VAD0_CTRL_2_VADINPGAIN_MASK (0xF00U) |
#define | PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT (8U) |
#define | PDM_VAD0_CTRL_2_VADINPGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK) |
#define | PDM_VAD0_CTRL_2_VADFRAMET_MASK (0x3F0000U) |
#define | PDM_VAD0_CTRL_2_VADFRAMET_SHIFT (16U) |
#define | PDM_VAD0_CTRL_2_VADFRAMET(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK) |
#define | PDM_VAD0_CTRL_2_VADFOUTDIS_MASK (0x10000000U) |
#define | PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT (28U) |
#define | PDM_VAD0_CTRL_2_VADFOUTDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK) |
#define | PDM_VAD0_CTRL_2_VADPREFEN_MASK (0x40000000U) |
#define | PDM_VAD0_CTRL_2_VADPREFEN_SHIFT (30U) |
#define | PDM_VAD0_CTRL_2_VADPREFEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK) |
#define | PDM_VAD0_CTRL_2_VADFRENDIS_MASK (0x80000000U) |
#define | PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT (31U) |
#define | PDM_VAD0_CTRL_2_VADFRENDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK) |
VAD0_STAT - Voice Activity Detector 0 Status register | |
#define | PDM_VAD0_STAT_VADIF_MASK (0x1U) |
#define | PDM_VAD0_STAT_VADIF_SHIFT (0U) |
#define | PDM_VAD0_STAT_VADIF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK) |
#define | PDM_VAD0_STAT_VADEF_MASK (0x8000U) |
#define | PDM_VAD0_STAT_VADEF_SHIFT (15U) |
#define | PDM_VAD0_STAT_VADEF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK) |
#define | PDM_VAD0_STAT_VADINSATF_MASK (0x10000U) |
#define | PDM_VAD0_STAT_VADINSATF_SHIFT (16U) |
#define | PDM_VAD0_STAT_VADINSATF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK) |
#define | PDM_VAD0_STAT_VADINITF_MASK (0x80000000U) |
#define | PDM_VAD0_STAT_VADINITF_SHIFT (31U) |
#define | PDM_VAD0_STAT_VADINITF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK) |
VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration | |
#define | PDM_VAD0_SCONFIG_VADSGAIN_MASK (0xFU) |
#define | PDM_VAD0_SCONFIG_VADSGAIN_SHIFT (0U) |
#define | PDM_VAD0_SCONFIG_VADSGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK) |
#define | PDM_VAD0_SCONFIG_VADSMAXEN_MASK (0x40000000U) |
#define | PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT (30U) |
#define | PDM_VAD0_SCONFIG_VADSMAXEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK) |
#define | PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) |
#define | PDM_VAD0_SCONFIG_VADSFILEN_SHIFT (31U) |
#define | PDM_VAD0_SCONFIG_VADSFILEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK) |
VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration | |
#define | PDM_VAD0_NCONFIG_VADNGAIN_MASK (0xFU) |
#define | PDM_VAD0_NCONFIG_VADNGAIN_SHIFT (0U) |
#define | PDM_VAD0_NCONFIG_VADNGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK) |
#define | PDM_VAD0_NCONFIG_VADNFILADJ_MASK (0x1F00U) |
#define | PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT (8U) |
#define | PDM_VAD0_NCONFIG_VADNFILADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK) |
#define | PDM_VAD0_NCONFIG_VADNOREN_MASK (0x10000000U) |
#define | PDM_VAD0_NCONFIG_VADNOREN_SHIFT (28U) |
#define | PDM_VAD0_NCONFIG_VADNOREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK) |
#define | PDM_VAD0_NCONFIG_VADNDECEN_MASK (0x20000000U) |
#define | PDM_VAD0_NCONFIG_VADNDECEN_SHIFT (29U) |
#define | PDM_VAD0_NCONFIG_VADNDECEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK) |
#define | PDM_VAD0_NCONFIG_VADNMINEN_MASK (0x40000000U) |
#define | PDM_VAD0_NCONFIG_VADNMINEN_SHIFT (30U) |
#define | PDM_VAD0_NCONFIG_VADNMINEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK) |
#define | PDM_VAD0_NCONFIG_VADNFILAUTO_MASK (0x80000000U) |
#define | PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT (31U) |
#define | PDM_VAD0_NCONFIG_VADNFILAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK) |
VAD0_NDATA - Voice Activity Detector 0 Noise Data | |
#define | PDM_VAD0_NDATA_VADNDATA_MASK (0xFFFFU) |
#define | PDM_VAD0_NDATA_VADNDATA_SHIFT (0U) |
#define | PDM_VAD0_NDATA_VADNDATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK) |
VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector | |
#define | PDM_VAD0_ZCD_VADZCDEN_MASK (0x1U) |
#define | PDM_VAD0_ZCD_VADZCDEN_SHIFT (0U) |
#define | PDM_VAD0_ZCD_VADZCDEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK) |
#define | PDM_VAD0_ZCD_VADZCDAUTO_MASK (0x4U) |
#define | PDM_VAD0_ZCD_VADZCDAUTO_SHIFT (2U) |
#define | PDM_VAD0_ZCD_VADZCDAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK) |
#define | PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) |
#define | PDM_VAD0_ZCD_VADZCDAND_SHIFT (4U) |
#define | PDM_VAD0_ZCD_VADZCDAND(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK) |
#define | PDM_VAD0_ZCD_VADZCDADJ_MASK (0xF00U) |
#define | PDM_VAD0_ZCD_VADZCDADJ_SHIFT (8U) |
#define | PDM_VAD0_ZCD_VADZCDADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK) |
#define | PDM_VAD0_ZCD_VADZCDTH_MASK (0x3FF0000U) |
#define | PDM_VAD0_ZCD_VADZCDTH_SHIFT (16U) |
#define | PDM_VAD0_ZCD_VADZCDTH(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK) |
BPC_AUTHEN_CTRL - BPC Authentication Control | |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK (0x1U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT (0U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK) |
BPC_MODE - BPC Mode | |
#define | PGMC_BPC_BPC_MODE_CTRL_MODE_MASK (0x3U) |
#define | PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT (0U) |
#define | PGMC_BPC_BPC_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT)) & PGMC_BPC_BPC_MODE_CTRL_MODE_MASK) |
#define | PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK (0x30U) |
#define | PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT (4U) |
#define | PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK) |
BPC_POWER_CTRL - BPC power control | |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK (0xFFFF0000U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT (16U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK) |
BPC_FLAG - BPC flag | |
#define | PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK (0x1U) |
#define | PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT (0U) |
#define | PGMC_BPC_BPC_FLAG_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT)) & PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK) |
BPC_SSAR_SAVE_CTRL - BPC SSAR save control | |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK (0x1U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT (0U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK (0x2U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT (1U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK (0x4U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT (2U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK (0x8U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT (3U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK (0xFFFF0000U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT (16U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK) |
BPC_SSAR_RESTORE_CTRL - BPC SSAR restore control | |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK (0x1U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT (0U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK (0xFFFF0000U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT (16U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK) |
CPC_AUTHEN_CTRL - CPC Authentication Control | |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK (0x1U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT (0U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) |
#define | PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK) |
CPC_CORE_MODE - CPC Core Mode | |
#define | PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK (0x3U) |
#define | PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT (0U) |
#define | PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK) |
CPC_CORE_POWER_CTRL - CPC core power control | |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U) |
#define | PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK) |
CPC_FLAG - CPC flag | |
#define | PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK (0x1U) |
#define | PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT (0U) |
#define | PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT)) & PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK) |
CPC_CACHE_MODE - CPC Cache Mode | |
#define | PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK (0x3U) |
#define | PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT (0U) |
#define | PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK) |
CPC_CACHE_CM_CTRL - CPC cache CPU mode control | |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK (0xFU) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT (0U) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT (8U) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK (0x10000U) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT (16U) |
#define | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK) |
CPC_CACHE_SP_CTRL_0 - CPC cache Setpoint control 0 | |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK) |
CPC_CACHE_SP_CTRL_1 - CPC cache Setpoint control 1 | |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U) |
#define | PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK) |
CPC_LMEM_MODE - CPC local memory Mode | |
#define | PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK (0x3U) |
#define | PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT (0U) |
#define | PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK) |
CPC_LMEM_CM_CTRL - CPC local memory CPU mode control | |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK (0xFU) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT (0U) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT (8U) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK (0x10000U) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT (16U) |
#define | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK) |
CPC_LMEM_SP_CTRL_0 - CPC local memory Setpoint control 0 | |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK) |
CPC_LMEM_SP_CTRL_1 - CPC local memory Setpoint control 1 | |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U) |
#define | PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK) |
MIF_AUTHEN_CTRL - MIF Authentication Control | |
#define | PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) |
#define | PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) |
#define | PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK) |
MIF_MLPL_SLEEP - MIF MLPL control of SLEEP | |
#define | PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK (0xFFFFU) |
#define | PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT (0U) |
#define | PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK) |
MIF_MLPL_IG - MIF MLPL control of IG | |
#define | PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK (0xFFFFU) |
#define | PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT (0U) |
#define | PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK) |
MIF_MLPL_LS - MIF MLPL control of LS | |
#define | PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK (0xFFFFU) |
#define | PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT (0U) |
#define | PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK) |
MIF_MLPL_HS - MIF MLPL control of HS | |
#define | PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK (0xFFFFU) |
#define | PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT (0U) |
#define | PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK) |
MIF_MLPL_STDBY - MIF MLPL control of STDBY | |
#define | PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK (0xFFFFU) |
#define | PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT (0U) |
#define | PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK) |
MIF_MLPL_ARR_PDN - MIF MLPL control of array power down | |
#define | PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK (0xFFFFU) |
#define | PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT (0U) |
#define | PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK) |
MIF_MLPL_PER_PDN - MIF MLPL control of peripheral power down | |
#define | PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK (0xFFFFU) |
#define | PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT (0U) |
#define | PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK) |
MIF_MLPL_INITN - MIF MLPL control of INITN | |
#define | PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK (0xFFFFU) |
#define | PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT (0U) |
#define | PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK) |
#define | PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK (0x80000000U) |
#define | PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT (31U) |
#define | PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK) |
MIF_MLPL_ISO - MIF MLPL control of isolation enable | |
#define | PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK (0xFFFFU) |
#define | PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT (0U) |
#define | PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK) |
PPC_AUTHEN_CTRL - PPC Authentication Control | |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK (0x1U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT (0U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) |
#define | PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK) |
PPC_MODE - PPC Mode | |
#define | PGMC_PPC_PPC_MODE_CTRL_MODE_MASK (0x3U) |
#define | PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT (0U) |
#define | PGMC_PPC_PPC_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT)) & PGMC_PPC_PPC_MODE_CTRL_MODE_MASK) |
#define | PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK (0x30U) |
#define | PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT (4U) |
#define | PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK) |
PPC_STBY_CM_CTRL - PPC standby CPU mode control | |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK (0x2U) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT (1U) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK (0x4U) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT (2U) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK (0x8U) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT (3U) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK (0x100U) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT (8U) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK (0x200U) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT (9U) |
#define | PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK) |
PPC_STBY_SP_CTRL - PPC standby Setpoint control | |
#define | PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK (0xFFFFU) |
#define | PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT (0U) |
#define | PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK) |
#define | PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK (0xFFFF0000U) |
#define | PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT (16U) |
#define | PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK) |
CTRL0 - Analog Control Register CTRL0 | |
#define | PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U) |
#define | PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U) |
#define | PHY_LDO_CTRL0_LINREG_EN(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_EN_MASK) |
#define | PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK (0x2U) |
#define | PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT (1U) |
#define | PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT)) & PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK) |
#define | PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK (0x4U) |
#define | PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT (2U) |
#define | PHY_LDO_CTRL0_LINREG_ILIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK) |
#define | PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK (0x1F0U) |
#define | PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT (4U) |
#define | PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT)) & PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK) |
#define | PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK (0x8000U) |
#define | PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT (15U) |
#define | PHY_LDO_CTRL0_LINREG_PHY_ISO_B(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT)) & PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK) |
#define | VMBANDGAP_CTRL0_REFTOP_PWD_MASK (0x1U) |
#define | VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT (0U) |
#define | VMBANDGAP_CTRL0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWD_MASK) |
#define | VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U) |
#define | VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U) |
#define | VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK) |
#define | VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U) |
#define | VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U) |
#define | VMBANDGAP_CTRL0_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK) |
#define | VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK (0x8U) |
#define | VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT (3U) |
#define | VMBANDGAP_CTRL0_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK) |
#define | VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U) |
#define | VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U) |
#define | VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK) |
STAT0 - Analog Status Register STAT0 | |
#define | PHY_LDO_STAT0_LINREG_STAT_MASK (0xFU) |
#define | PHY_LDO_STAT0_LINREG_STAT_SHIFT (0U) |
#define | PHY_LDO_STAT0_LINREG_STAT(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & PHY_LDO_STAT0_LINREG_STAT_MASK) |
#define | VMBANDGAP_STAT0_REFTOP_VBGUP_MASK (0x1U) |
#define | VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT (0U) |
#define | VMBANDGAP_STAT0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & VMBANDGAP_STAT0_REFTOP_VBGUP_MASK) |
#define | VMBANDGAP_STAT0_VDD1_PORB_MASK (0x2U) |
#define | VMBANDGAP_STAT0_VDD1_PORB_SHIFT (1U) |
#define | VMBANDGAP_STAT0_VDD1_PORB(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD1_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD1_PORB_MASK) |
#define | VMBANDGAP_STAT0_VDD2_PORB_MASK (0x4U) |
#define | VMBANDGAP_STAT0_VDD2_PORB_SHIFT (2U) |
#define | VMBANDGAP_STAT0_VDD2_PORB(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD2_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD2_PORB_MASK) |
#define | VMBANDGAP_STAT0_VDD3_PORB_MASK (0x8U) |
#define | VMBANDGAP_STAT0_VDD3_PORB_SHIFT (3U) |
#define | VMBANDGAP_STAT0_VDD3_PORB(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD3_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD3_PORB_MASK) |
MCR - PIT Module Control Register | |
#define | PIT_MCR_FRZ_MASK (0x1U) |
#define | PIT_MCR_FRZ_SHIFT (0U) |
#define | PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) |
#define | PIT_MCR_MDIS_MASK (0x2U) |
#define | PIT_MCR_MDIS_SHIFT (1U) |
#define | PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) |
LTMR64H - PIT Upper Lifetime Timer Register | |
#define | PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) |
#define | PIT_LTMR64H_LTH_SHIFT (0U) |
#define | PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) |
LTMR64L - PIT Lower Lifetime Timer Register | |
#define | PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) |
#define | PIT_LTMR64L_LTL_SHIFT (0U) |
#define | PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) |
LDVAL - Timer Load Value Register | |
#define | PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) |
#define | PIT_LDVAL_TSV_SHIFT (0U) |
#define | PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) |
CVAL - Current Timer Value Register | |
#define | PIT_CVAL_TVL_MASK (0xFFFFFFFFU) |
#define | PIT_CVAL_TVL_SHIFT (0U) |
#define | PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) |
TCTRL - Timer Control Register | |
#define | PIT_TCTRL_TEN_MASK (0x1U) |
#define | PIT_TCTRL_TEN_SHIFT (0U) |
#define | PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) |
#define | PIT_TCTRL_TIE_MASK (0x2U) |
#define | PIT_TCTRL_TIE_SHIFT (1U) |
#define | PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) |
#define | PIT_TCTRL_CHN_MASK (0x4U) |
#define | PIT_TCTRL_CHN_SHIFT (2U) |
#define | PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) |
TFLG - Timer Flag Register | |
#define | PIT_TFLG_TIF_MASK (0x1U) |
#define | PIT_TFLG_TIF_SHIFT (0U) |
#define | PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) |
CTRL - PUF Control Register | |
#define | PUF_CTRL_ZEROIZE_MASK (0x1U) |
#define | PUF_CTRL_ZEROIZE_SHIFT (0U) |
#define | PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) |
#define | PUF_CTRL_ENROLL_MASK (0x2U) |
#define | PUF_CTRL_ENROLL_SHIFT (1U) |
#define | PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) |
#define | PUF_CTRL_START_MASK (0x4U) |
#define | PUF_CTRL_START_SHIFT (2U) |
#define | PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) |
#define | PUF_CTRL_GENERATEKEY_MASK (0x8U) |
#define | PUF_CTRL_GENERATEKEY_SHIFT (3U) |
#define | PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) |
#define | PUF_CTRL_SETKEY_MASK (0x10U) |
#define | PUF_CTRL_SETKEY_SHIFT (4U) |
#define | PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) |
#define | PUF_CTRL_GETKEY_MASK (0x40U) |
#define | PUF_CTRL_GETKEY_SHIFT (6U) |
#define | PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) |
KEYINDEX - PUF Key Index Register | |
#define | PUF_KEYINDEX_KEYIDX_MASK (0xFU) |
#define | PUF_KEYINDEX_KEYIDX_SHIFT (0U) |
#define | PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) |
KEYSIZE - PUF Key Size Register | |
#define | PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) |
#define | PUF_KEYSIZE_KEYSIZE_SHIFT (0U) |
#define | PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) |
STAT - PUF Status Register | |
#define | PUF_STAT_BUSY_MASK (0x1U) |
#define | PUF_STAT_BUSY_SHIFT (0U) |
#define | PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) |
#define | PUF_STAT_SUCCESS_MASK (0x2U) |
#define | PUF_STAT_SUCCESS_SHIFT (1U) |
#define | PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) |
#define | PUF_STAT_ERROR_MASK (0x4U) |
#define | PUF_STAT_ERROR_SHIFT (2U) |
#define | PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) |
#define | PUF_STAT_KEYINREQ_MASK (0x10U) |
#define | PUF_STAT_KEYINREQ_SHIFT (4U) |
#define | PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) |
#define | PUF_STAT_KEYOUTAVAIL_MASK (0x20U) |
#define | PUF_STAT_KEYOUTAVAIL_SHIFT (5U) |
#define | PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) |
#define | PUF_STAT_CODEINREQ_MASK (0x40U) |
#define | PUF_STAT_CODEINREQ_SHIFT (6U) |
#define | PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) |
#define | PUF_STAT_CODEOUTAVAIL_MASK (0x80U) |
#define | PUF_STAT_CODEOUTAVAIL_SHIFT (7U) |
#define | PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) |
ALLOW - PUF Allow Register | |
#define | PUF_ALLOW_ALLOWENROLL_MASK (0x1U) |
#define | PUF_ALLOW_ALLOWENROLL_SHIFT (0U) |
#define | PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) |
#define | PUF_ALLOW_ALLOWSTART_MASK (0x2U) |
#define | PUF_ALLOW_ALLOWSTART_SHIFT (1U) |
#define | PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) |
#define | PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) |
#define | PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) |
#define | PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) |
#define | PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) |
#define | PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) |
#define | PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) |
KEYINPUT - PUF Key Input Register | |
#define | PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) |
#define | PUF_KEYINPUT_KEYIN_SHIFT (0U) |
#define | PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) |
CODEINPUT - PUF Code Input Register | |
#define | PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) |
#define | PUF_CODEINPUT_CODEIN_SHIFT (0U) |
#define | PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) |
CODEOUTPUT - PUF Code Output Register | |
#define | PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) |
#define | PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) |
#define | PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) |
KEYOUTINDEX - PUF Key Output Index Register | |
#define | PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFFFFFFFFU) |
#define | PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) |
#define | PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) |
KEYOUTPUT - PUF Key Output Register | |
#define | PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) |
#define | PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) |
#define | PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) |
IFSTAT - PUF Interface Status Register | |
#define | PUF_IFSTAT_ERROR_MASK (0x1U) |
#define | PUF_IFSTAT_ERROR_SHIFT (0U) |
#define | PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) |
VERSION - PUF Version Register | |
#define | PUF_VERSION_VERSION_MASK (0xFFFFFFFFU) |
#define | PUF_VERSION_VERSION_SHIFT (0U) |
#define | PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK) |
INTEN - PUF Interrupt Enable | |
#define | PUF_INTEN_READYEN_MASK (0x1U) |
#define | PUF_INTEN_READYEN_SHIFT (0U) |
#define | PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) |
#define | PUF_INTEN_SUCCESSEN_MASK (0x2U) |
#define | PUF_INTEN_SUCCESSEN_SHIFT (1U) |
#define | PUF_INTEN_SUCCESSEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESSEN_SHIFT)) & PUF_INTEN_SUCCESSEN_MASK) |
#define | PUF_INTEN_ERROREN_MASK (0x4U) |
#define | PUF_INTEN_ERROREN_SHIFT (2U) |
#define | PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) |
#define | PUF_INTEN_KEYINREQEN_MASK (0x10U) |
#define | PUF_INTEN_KEYINREQEN_SHIFT (4U) |
#define | PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) |
#define | PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) |
#define | PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) |
#define | PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) |
#define | PUF_INTEN_CODEINREQEN_MASK (0x40U) |
#define | PUF_INTEN_CODEINREQEN_SHIFT (6U) |
#define | PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) |
#define | PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) |
#define | PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) |
#define | PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) |
INTSTAT - PUF Interrupt Status | |
#define | PUF_INTSTAT_READY_MASK (0x1U) |
#define | PUF_INTSTAT_READY_SHIFT (0U) |
#define | PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) |
#define | PUF_INTSTAT_SUCCESS_MASK (0x2U) |
#define | PUF_INTSTAT_SUCCESS_SHIFT (1U) |
#define | PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) |
#define | PUF_INTSTAT_ERROR_MASK (0x4U) |
#define | PUF_INTSTAT_ERROR_SHIFT (2U) |
#define | PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) |
#define | PUF_INTSTAT_KEYINREQ_MASK (0x10U) |
#define | PUF_INTSTAT_KEYINREQ_SHIFT (4U) |
#define | PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) |
#define | PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) |
#define | PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) |
#define | PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) |
#define | PUF_INTSTAT_CODEINREQ_MASK (0x40U) |
#define | PUF_INTSTAT_CODEINREQ_SHIFT (6U) |
#define | PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) |
#define | PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) |
#define | PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) |
#define | PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) |
PWRCTRL - PUF Power Control Of RAM | |
#define | PUF_PWRCTRL_RAM_ON_MASK (0x1U) |
#define | PUF_PWRCTRL_RAM_ON_SHIFT (0U) |
#define | PUF_PWRCTRL_RAM_ON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_ON_SHIFT)) & PUF_PWRCTRL_RAM_ON_MASK) |
#define | PUF_PWRCTRL_CK_DIS_MASK (0x4U) |
#define | PUF_PWRCTRL_CK_DIS_SHIFT (2U) |
#define | PUF_PWRCTRL_CK_DIS(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_CK_DIS_SHIFT)) & PUF_PWRCTRL_CK_DIS_MASK) |
#define | PUF_PWRCTRL_RAM_INITN_MASK (0x8U) |
#define | PUF_PWRCTRL_RAM_INITN_SHIFT (3U) |
#define | PUF_PWRCTRL_RAM_INITN(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_INITN_SHIFT)) & PUF_PWRCTRL_RAM_INITN_MASK) |
#define | PUF_PWRCTRL_RAM_PSW_MASK (0xF0U) |
#define | PUF_PWRCTRL_RAM_PSW_SHIFT (4U) |
#define | PUF_PWRCTRL_RAM_PSW(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_PSW_SHIFT)) & PUF_PWRCTRL_RAM_PSW_MASK) |
CFG - PUF Configuration Register | |
#define | PUF_CFG_PUF_BLOCK_SET_KEY_MASK (0x1U) |
#define | PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT (0U) |
#define | PUF_CFG_PUF_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT)) & PUF_CFG_PUF_BLOCK_SET_KEY_MASK) |
#define | PUF_CFG_PUF_BLOCK_ENROLL_MASK (0x2U) |
#define | PUF_CFG_PUF_BLOCK_ENROLL_SHIFT (1U) |
#define | PUF_CFG_PUF_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_ENROLL_SHIFT)) & PUF_CFG_PUF_BLOCK_ENROLL_MASK) |
KEYLOCK - PUF Key Manager Lock | |
#define | PUF_KEYLOCK_LOCK0_MASK (0x3U) |
#define | PUF_KEYLOCK_LOCK0_SHIFT (0U) |
#define | PUF_KEYLOCK_LOCK0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK0_SHIFT)) & PUF_KEYLOCK_LOCK0_MASK) |
#define | PUF_KEYLOCK_LOCK1_MASK (0xCU) |
#define | PUF_KEYLOCK_LOCK1_SHIFT (2U) |
#define | PUF_KEYLOCK_LOCK1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK1_SHIFT)) & PUF_KEYLOCK_LOCK1_MASK) |
KEYENABLE - PUF Key Manager Enable | |
#define | PUF_KEYENABLE_ENABLE0_MASK (0x3U) |
#define | PUF_KEYENABLE_ENABLE0_SHIFT (0U) |
#define | PUF_KEYENABLE_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE0_SHIFT)) & PUF_KEYENABLE_ENABLE0_MASK) |
#define | PUF_KEYENABLE_ENABLE1_MASK (0xCU) |
#define | PUF_KEYENABLE_ENABLE1_SHIFT (2U) |
#define | PUF_KEYENABLE_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE1_SHIFT)) & PUF_KEYENABLE_ENABLE1_MASK) |
KEYRESET - PUF Key Manager Reset | |
#define | PUF_KEYRESET_RESET0_MASK (0x3U) |
#define | PUF_KEYRESET_RESET0_SHIFT (0U) |
#define | PUF_KEYRESET_RESET0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET0_SHIFT)) & PUF_KEYRESET_RESET0_MASK) |
#define | PUF_KEYRESET_RESET1_MASK (0xCU) |
#define | PUF_KEYRESET_RESET1_SHIFT (2U) |
#define | PUF_KEYRESET_RESET1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET1_SHIFT)) & PUF_KEYRESET_RESET1_MASK) |
IDXBLK - PUF Index Block Key Output | |
#define | PUF_IDXBLK_IDXBLK0_MASK (0x3U) |
#define | PUF_IDXBLK_IDXBLK0_SHIFT (0U) |
#define | PUF_IDXBLK_IDXBLK0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK0_SHIFT)) & PUF_IDXBLK_IDXBLK0_MASK) |
#define | PUF_IDXBLK_IDXBLK1_MASK (0xCU) |
#define | PUF_IDXBLK_IDXBLK1_SHIFT (2U) |
#define | PUF_IDXBLK_IDXBLK1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK1_SHIFT)) & PUF_IDXBLK_IDXBLK1_MASK) |
#define | PUF_IDXBLK_IDXBLK2_MASK (0x30U) |
#define | PUF_IDXBLK_IDXBLK2_SHIFT (4U) |
#define | PUF_IDXBLK_IDXBLK2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK2_SHIFT)) & PUF_IDXBLK_IDXBLK2_MASK) |
#define | PUF_IDXBLK_IDXBLK3_MASK (0xC0U) |
#define | PUF_IDXBLK_IDXBLK3_SHIFT (6U) |
#define | PUF_IDXBLK_IDXBLK3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK3_SHIFT)) & PUF_IDXBLK_IDXBLK3_MASK) |
#define | PUF_IDXBLK_IDXBLK4_MASK (0x300U) |
#define | PUF_IDXBLK_IDXBLK4_SHIFT (8U) |
#define | PUF_IDXBLK_IDXBLK4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK4_SHIFT)) & PUF_IDXBLK_IDXBLK4_MASK) |
#define | PUF_IDXBLK_IDXBLK5_MASK (0xC00U) |
#define | PUF_IDXBLK_IDXBLK5_SHIFT (10U) |
#define | PUF_IDXBLK_IDXBLK5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK5_SHIFT)) & PUF_IDXBLK_IDXBLK5_MASK) |
#define | PUF_IDXBLK_IDXBLK6_MASK (0x3000U) |
#define | PUF_IDXBLK_IDXBLK6_SHIFT (12U) |
#define | PUF_IDXBLK_IDXBLK6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK6_SHIFT)) & PUF_IDXBLK_IDXBLK6_MASK) |
#define | PUF_IDXBLK_IDXBLK7_MASK (0xC000U) |
#define | PUF_IDXBLK_IDXBLK7_SHIFT (14U) |
#define | PUF_IDXBLK_IDXBLK7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK7_SHIFT)) & PUF_IDXBLK_IDXBLK7_MASK) |
#define | PUF_IDXBLK_IDXBLK8_MASK (0x30000U) |
#define | PUF_IDXBLK_IDXBLK8_SHIFT (16U) |
#define | PUF_IDXBLK_IDXBLK8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK8_SHIFT)) & PUF_IDXBLK_IDXBLK8_MASK) |
#define | PUF_IDXBLK_IDXBLK9_MASK (0xC0000U) |
#define | PUF_IDXBLK_IDXBLK9_SHIFT (18U) |
#define | PUF_IDXBLK_IDXBLK9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK9_SHIFT)) & PUF_IDXBLK_IDXBLK9_MASK) |
#define | PUF_IDXBLK_IDXBLK10_MASK (0x300000U) |
#define | PUF_IDXBLK_IDXBLK10_SHIFT (20U) |
#define | PUF_IDXBLK_IDXBLK10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK10_SHIFT)) & PUF_IDXBLK_IDXBLK10_MASK) |
#define | PUF_IDXBLK_IDXBLK11_MASK (0xC00000U) |
#define | PUF_IDXBLK_IDXBLK11_SHIFT (22U) |
#define | PUF_IDXBLK_IDXBLK11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK11_SHIFT)) & PUF_IDXBLK_IDXBLK11_MASK) |
#define | PUF_IDXBLK_IDXBLK12_MASK (0x3000000U) |
#define | PUF_IDXBLK_IDXBLK12_SHIFT (24U) |
#define | PUF_IDXBLK_IDXBLK12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK12_SHIFT)) & PUF_IDXBLK_IDXBLK12_MASK) |
#define | PUF_IDXBLK_IDXBLK13_MASK (0xC000000U) |
#define | PUF_IDXBLK_IDXBLK13_SHIFT (26U) |
#define | PUF_IDXBLK_IDXBLK13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK13_SHIFT)) & PUF_IDXBLK_IDXBLK13_MASK) |
#define | PUF_IDXBLK_IDXBLK14_MASK (0x30000000U) |
#define | PUF_IDXBLK_IDXBLK14_SHIFT (28U) |
#define | PUF_IDXBLK_IDXBLK14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK14_SHIFT)) & PUF_IDXBLK_IDXBLK14_MASK) |
#define | PUF_IDXBLK_IDXBLK15_MASK (0xC0000000U) |
#define | PUF_IDXBLK_IDXBLK15_SHIFT (30U) |
#define | PUF_IDXBLK_IDXBLK15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK15_SHIFT)) & PUF_IDXBLK_IDXBLK15_MASK) |
IDXBLK_DP - PUF Index Block Key Output | |
#define | PUF_IDXBLK_DP_IDXBLK_DP0_MASK (0x3U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT (0U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP0_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP1_MASK (0xCU) |
#define | PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT (2U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP1_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP2_MASK (0x30U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT (4U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP2_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP3_MASK (0xC0U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT (6U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP3_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP4_MASK (0x300U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT (8U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP4_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP5_MASK (0xC00U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT (10U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP5_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP6_MASK (0x3000U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT (12U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP6_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP7_MASK (0xC000U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT (14U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP7_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP8_MASK (0x30000U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT (16U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP8_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP9_MASK (0xC0000U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT (18U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP9_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT (20U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP11_MASK (0xC00000U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT (22U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP11_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP12_MASK (0x3000000U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT (24U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP12_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP13_MASK (0xC000000U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT (26U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP13_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP14_MASK (0x30000000U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT (28U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP14_MASK) |
#define | PUF_IDXBLK_DP_IDXBLK_DP15_MASK (0xC0000000U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT (30U) |
#define | PUF_IDXBLK_DP_IDXBLK_DP15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP15_MASK) |
KEYMASK - PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable | |
#define | PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) |
#define | PUF_KEYMASK_KEYMASK_SHIFT (0U) |
#define | PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) |
IDXBLK_STATUS - PUF Index Block Setting Status Register | |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK (0x3U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT (0U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT (2U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK (0x30U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT (4U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK (0xC0U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT (6U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK (0x300U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT (8U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK (0xC00U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT (10U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK (0x3000U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT (12U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK (0xC000U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT (14U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK (0x30000U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT (16U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK (0xC0000U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT (18U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK (0x300000U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT (20U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK (0xC00000U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT (22U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK (0x3000000U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT (24U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK (0xC000000U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT (26U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK (0x30000000U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT (28U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK (0xC0000000U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT (30U) |
#define | PUF_IDXBLK_STATUS_IDXBLK_STATUS15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK) |
IDXBLK_SHIFT - PUF Key Manager Shift Status | |
#define | PUF_IDXBLK_SHIFT_IND_KEY0_MASK (0xFU) |
#define | PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT (0U) |
#define | PUF_IDXBLK_SHIFT_IND_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY0_MASK) |
#define | PUF_IDXBLK_SHIFT_IND_KEY1_MASK (0xF0U) |
#define | PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT (4U) |
#define | PUF_IDXBLK_SHIFT_IND_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY1_MASK) |
CNT - Counter Register | |
#define | PWM_CNT_CNT_MASK (0xFFFFU) |
#define | PWM_CNT_CNT_SHIFT (0U) |
#define | PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) |
INIT - Initial Count Register | |
#define | PWM_INIT_INIT_MASK (0xFFFFU) |
#define | PWM_INIT_INIT_SHIFT (0U) |
#define | PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) |
VAL0 - Value Register 0 | |
#define | PWM_VAL0_VAL0_MASK (0xFFFFU) |
#define | PWM_VAL0_VAL0_SHIFT (0U) |
#define | PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) |
FRACVAL1 - Fractional Value Register 1 | |
#define | PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) |
#define | PWM_FRACVAL1_FRACVAL1_SHIFT (11U) |
#define | PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) |
VAL1 - Value Register 1 | |
#define | PWM_VAL1_VAL1_MASK (0xFFFFU) |
#define | PWM_VAL1_VAL1_SHIFT (0U) |
#define | PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) |
FRACVAL2 - Fractional Value Register 2 | |
#define | PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) |
#define | PWM_FRACVAL2_FRACVAL2_SHIFT (11U) |
#define | PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) |
VAL2 - Value Register 2 | |
#define | PWM_VAL2_VAL2_MASK (0xFFFFU) |
#define | PWM_VAL2_VAL2_SHIFT (0U) |
#define | PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) |
FRACVAL3 - Fractional Value Register 3 | |
#define | PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) |
#define | PWM_FRACVAL3_FRACVAL3_SHIFT (11U) |
#define | PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) |
VAL3 - Value Register 3 | |
#define | PWM_VAL3_VAL3_MASK (0xFFFFU) |
#define | PWM_VAL3_VAL3_SHIFT (0U) |
#define | PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) |
FRACVAL4 - Fractional Value Register 4 | |
#define | PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) |
#define | PWM_FRACVAL4_FRACVAL4_SHIFT (11U) |
#define | PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) |
VAL4 - Value Register 4 | |
#define | PWM_VAL4_VAL4_MASK (0xFFFFU) |
#define | PWM_VAL4_VAL4_SHIFT (0U) |
#define | PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) |
FRACVAL5 - Fractional Value Register 5 | |
#define | PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) |
#define | PWM_FRACVAL5_FRACVAL5_SHIFT (11U) |
#define | PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) |
VAL5 - Value Register 5 | |
#define | PWM_VAL5_VAL5_MASK (0xFFFFU) |
#define | PWM_VAL5_VAL5_SHIFT (0U) |
#define | PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) |
FRCTRL - Fractional Control Register | |
#define | PWM_FRCTRL_FRAC1_EN_MASK (0x2U) |
#define | PWM_FRCTRL_FRAC1_EN_SHIFT (1U) |
#define | PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) |
#define | PWM_FRCTRL_FRAC23_EN_MASK (0x4U) |
#define | PWM_FRCTRL_FRAC23_EN_SHIFT (2U) |
#define | PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) |
#define | PWM_FRCTRL_FRAC45_EN_MASK (0x10U) |
#define | PWM_FRCTRL_FRAC45_EN_SHIFT (4U) |
#define | PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) |
#define | PWM_FRCTRL_TEST_MASK (0x8000U) |
#define | PWM_FRCTRL_TEST_SHIFT (15U) |
#define | PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) |
OCTRL - Output Control Register | |
#define | PWM_OCTRL_PWMXFS_MASK (0x3U) |
#define | PWM_OCTRL_PWMXFS_SHIFT (0U) |
#define | PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) |
#define | PWM_OCTRL_PWMBFS_MASK (0xCU) |
#define | PWM_OCTRL_PWMBFS_SHIFT (2U) |
#define | PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) |
#define | PWM_OCTRL_PWMAFS_MASK (0x30U) |
#define | PWM_OCTRL_PWMAFS_SHIFT (4U) |
#define | PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) |
#define | PWM_OCTRL_POLX_MASK (0x100U) |
#define | PWM_OCTRL_POLX_SHIFT (8U) |
#define | PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) |
#define | PWM_OCTRL_POLB_MASK (0x200U) |
#define | PWM_OCTRL_POLB_SHIFT (9U) |
#define | PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) |
#define | PWM_OCTRL_POLA_MASK (0x400U) |
#define | PWM_OCTRL_POLA_SHIFT (10U) |
#define | PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) |
#define | PWM_OCTRL_PWMX_IN_MASK (0x2000U) |
#define | PWM_OCTRL_PWMX_IN_SHIFT (13U) |
#define | PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) |
#define | PWM_OCTRL_PWMB_IN_MASK (0x4000U) |
#define | PWM_OCTRL_PWMB_IN_SHIFT (14U) |
#define | PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) |
#define | PWM_OCTRL_PWMA_IN_MASK (0x8000U) |
#define | PWM_OCTRL_PWMA_IN_SHIFT (15U) |
#define | PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) |
STS - Status Register | |
#define | PWM_STS_CMPF_MASK (0x3FU) |
#define | PWM_STS_CMPF_SHIFT (0U) |
#define | PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) |
#define | PWM_STS_CFX0_MASK (0x40U) |
#define | PWM_STS_CFX0_SHIFT (6U) |
#define | PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) |
#define | PWM_STS_CFX1_MASK (0x80U) |
#define | PWM_STS_CFX1_SHIFT (7U) |
#define | PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) |
#define | PWM_STS_CFB0_MASK (0x100U) |
#define | PWM_STS_CFB0_SHIFT (8U) |
#define | PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) |
#define | PWM_STS_CFB1_MASK (0x200U) |
#define | PWM_STS_CFB1_SHIFT (9U) |
#define | PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) |
#define | PWM_STS_CFA0_MASK (0x400U) |
#define | PWM_STS_CFA0_SHIFT (10U) |
#define | PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) |
#define | PWM_STS_CFA1_MASK (0x800U) |
#define | PWM_STS_CFA1_SHIFT (11U) |
#define | PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) |
#define | PWM_STS_RF_MASK (0x1000U) |
#define | PWM_STS_RF_SHIFT (12U) |
#define | PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) |
#define | PWM_STS_REF_MASK (0x2000U) |
#define | PWM_STS_REF_SHIFT (13U) |
#define | PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) |
#define | PWM_STS_RUF_MASK (0x4000U) |
#define | PWM_STS_RUF_SHIFT (14U) |
#define | PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) |
DMAEN - DMA Enable Register | |
#define | PWM_DMAEN_CX0DE_MASK (0x1U) |
#define | PWM_DMAEN_CX0DE_SHIFT (0U) |
#define | PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) |
#define | PWM_DMAEN_CX1DE_MASK (0x2U) |
#define | PWM_DMAEN_CX1DE_SHIFT (1U) |
#define | PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) |
#define | PWM_DMAEN_CB0DE_MASK (0x4U) |
#define | PWM_DMAEN_CB0DE_SHIFT (2U) |
#define | PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) |
#define | PWM_DMAEN_CB1DE_MASK (0x8U) |
#define | PWM_DMAEN_CB1DE_SHIFT (3U) |
#define | PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) |
#define | PWM_DMAEN_CA0DE_MASK (0x10U) |
#define | PWM_DMAEN_CA0DE_SHIFT (4U) |
#define | PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) |
#define | PWM_DMAEN_CA1DE_MASK (0x20U) |
#define | PWM_DMAEN_CA1DE_SHIFT (5U) |
#define | PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) |
#define | PWM_DMAEN_CAPTDE_MASK (0xC0U) |
#define | PWM_DMAEN_CAPTDE_SHIFT (6U) |
#define | PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) |
#define | PWM_DMAEN_FAND_MASK (0x100U) |
#define | PWM_DMAEN_FAND_SHIFT (8U) |
#define | PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) |
#define | PWM_DMAEN_VALDE_MASK (0x200U) |
#define | PWM_DMAEN_VALDE_SHIFT (9U) |
#define | PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) |
TCTRL - Output Trigger Control Register | |
#define | PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) |
#define | PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) |
#define | PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) |
#define | PWM_TCTRL_TRGFRQ_MASK (0x1000U) |
#define | PWM_TCTRL_TRGFRQ_SHIFT (12U) |
#define | PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) |
#define | PWM_TCTRL_PWBOT1_MASK (0x4000U) |
#define | PWM_TCTRL_PWBOT1_SHIFT (14U) |
#define | PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) |
#define | PWM_TCTRL_PWAOT0_MASK (0x8000U) |
#define | PWM_TCTRL_PWAOT0_SHIFT (15U) |
#define | PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) |
DISMAP - Fault Disable Mapping Register 0 | |
#define | PWM_DISMAP_DIS0A_MASK (0xFU) |
#define | PWM_DISMAP_DIS0A_SHIFT (0U) |
#define | PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) |
#define | PWM_DISMAP_DIS0B_MASK (0xF0U) |
#define | PWM_DISMAP_DIS0B_SHIFT (4U) |
#define | PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) |
#define | PWM_DISMAP_DIS0X_MASK (0xF00U) |
#define | PWM_DISMAP_DIS0X_SHIFT (8U) |
#define | PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) |
DTCNT0 - Deadtime Count Register 0 | |
#define | PWM_DTCNT0_DTCNT0_MASK (0xFFFFU) |
#define | PWM_DTCNT0_DTCNT0_SHIFT (0U) |
#define | PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) |
DTCNT1 - Deadtime Count Register 1 | |
#define | PWM_DTCNT1_DTCNT1_MASK (0xFFFFU) |
#define | PWM_DTCNT1_DTCNT1_SHIFT (0U) |
#define | PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) |
CAPTCTRLA - Capture Control A Register | |
#define | PWM_CAPTCTRLA_ARMA_MASK (0x1U) |
#define | PWM_CAPTCTRLA_ARMA_SHIFT (0U) |
#define | PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) |
#define | PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) |
#define | PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) |
#define | PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) |
#define | PWM_CAPTCTRLA_EDGA0_MASK (0xCU) |
#define | PWM_CAPTCTRLA_EDGA0_SHIFT (2U) |
#define | PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) |
#define | PWM_CAPTCTRLA_EDGA1_MASK (0x30U) |
#define | PWM_CAPTCTRLA_EDGA1_SHIFT (4U) |
#define | PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) |
#define | PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) |
#define | PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) |
#define | PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) |
#define | PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) |
#define | PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) |
#define | PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) |
#define | PWM_CAPTCTRLA_CFAWM_MASK (0x300U) |
#define | PWM_CAPTCTRLA_CFAWM_SHIFT (8U) |
#define | PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) |
#define | PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) |
#define | PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) |
#define | PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) |
#define | PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) |
#define | PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) |
#define | PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) |
CAPTCOMPA - Capture Compare A Register | |
#define | PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) |
#define | PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) |
#define | PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) |
#define | PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) |
#define | PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) |
#define | PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) |
CAPTCTRLB - Capture Control B Register | |
#define | PWM_CAPTCTRLB_ARMB_MASK (0x1U) |
#define | PWM_CAPTCTRLB_ARMB_SHIFT (0U) |
#define | PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) |
#define | PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) |
#define | PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) |
#define | PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) |
#define | PWM_CAPTCTRLB_EDGB0_MASK (0xCU) |
#define | PWM_CAPTCTRLB_EDGB0_SHIFT (2U) |
#define | PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) |
#define | PWM_CAPTCTRLB_EDGB1_MASK (0x30U) |
#define | PWM_CAPTCTRLB_EDGB1_SHIFT (4U) |
#define | PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) |
#define | PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) |
#define | PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) |
#define | PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) |
#define | PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) |
#define | PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) |
#define | PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) |
#define | PWM_CAPTCTRLB_CFBWM_MASK (0x300U) |
#define | PWM_CAPTCTRLB_CFBWM_SHIFT (8U) |
#define | PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) |
#define | PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) |
#define | PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) |
#define | PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) |
#define | PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) |
#define | PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) |
#define | PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) |
CAPTCOMPB - Capture Compare B Register | |
#define | PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) |
#define | PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) |
#define | PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) |
#define | PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) |
#define | PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) |
#define | PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) |
CAPTCTRLX - Capture Control X Register | |
#define | PWM_CAPTCTRLX_ARMX_MASK (0x1U) |
#define | PWM_CAPTCTRLX_ARMX_SHIFT (0U) |
#define | PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) |
#define | PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) |
#define | PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) |
#define | PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) |
#define | PWM_CAPTCTRLX_EDGX0_MASK (0xCU) |
#define | PWM_CAPTCTRLX_EDGX0_SHIFT (2U) |
#define | PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) |
#define | PWM_CAPTCTRLX_EDGX1_MASK (0x30U) |
#define | PWM_CAPTCTRLX_EDGX1_SHIFT (4U) |
#define | PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) |
#define | PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) |
#define | PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) |
#define | PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) |
#define | PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) |
#define | PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) |
#define | PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) |
#define | PWM_CAPTCTRLX_CFXWM_MASK (0x300U) |
#define | PWM_CAPTCTRLX_CFXWM_SHIFT (8U) |
#define | PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) |
#define | PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) |
#define | PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) |
#define | PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) |
#define | PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) |
#define | PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) |
#define | PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) |
CAPTCOMPX - Capture Compare X Register | |
#define | PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) |
#define | PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) |
#define | PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) |
#define | PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) |
#define | PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) |
#define | PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) |
CVAL0 - Capture Value 0 Register | |
#define | PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) |
#define | PWM_CVAL0_CAPTVAL0_SHIFT (0U) |
#define | PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) |
CVAL0CYC - Capture Value 0 Cycle Register | |
#define | PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) |
#define | PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) |
#define | PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) |
CVAL1 - Capture Value 1 Register | |
#define | PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) |
#define | PWM_CVAL1_CAPTVAL1_SHIFT (0U) |
#define | PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) |
CVAL1CYC - Capture Value 1 Cycle Register | |
#define | PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) |
#define | PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) |
#define | PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) |
CVAL2 - Capture Value 2 Register | |
#define | PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) |
#define | PWM_CVAL2_CAPTVAL2_SHIFT (0U) |
#define | PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) |
CVAL2CYC - Capture Value 2 Cycle Register | |
#define | PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) |
#define | PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) |
#define | PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) |
CVAL3 - Capture Value 3 Register | |
#define | PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) |
#define | PWM_CVAL3_CAPTVAL3_SHIFT (0U) |
#define | PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) |
CVAL3CYC - Capture Value 3 Cycle Register | |
#define | PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) |
#define | PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) |
#define | PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) |
CVAL4 - Capture Value 4 Register | |
#define | PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) |
#define | PWM_CVAL4_CAPTVAL4_SHIFT (0U) |
#define | PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) |
CVAL4CYC - Capture Value 4 Cycle Register | |
#define | PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) |
#define | PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) |
#define | PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) |
CVAL5 - Capture Value 5 Register | |
#define | PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) |
#define | PWM_CVAL5_CAPTVAL5_SHIFT (0U) |
#define | PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) |
CVAL5CYC - Capture Value 5 Cycle Register | |
#define | PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) |
#define | PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) |
#define | PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) |
OUTEN - Output Enable Register | |
#define | PWM_OUTEN_PWMX_EN_MASK (0xFU) |
#define | PWM_OUTEN_PWMX_EN_SHIFT (0U) |
#define | PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) |
#define | PWM_OUTEN_PWMB_EN_MASK (0xF0U) |
#define | PWM_OUTEN_PWMB_EN_SHIFT (4U) |
#define | PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) |
#define | PWM_OUTEN_PWMA_EN_MASK (0xF00U) |
#define | PWM_OUTEN_PWMA_EN_SHIFT (8U) |
#define | PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) |
MASK - Mask Register | |
#define | PWM_MASK_MASKX_MASK (0xFU) |
#define | PWM_MASK_MASKX_SHIFT (0U) |
#define | PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) |
#define | PWM_MASK_MASKB_MASK (0xF0U) |
#define | PWM_MASK_MASKB_SHIFT (4U) |
#define | PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) |
#define | PWM_MASK_MASKA_MASK (0xF00U) |
#define | PWM_MASK_MASKA_SHIFT (8U) |
#define | PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) |
SWCOUT - Software Controlled Output Register | |
#define | PWM_SWCOUT_SM0OUT45_MASK (0x1U) |
#define | PWM_SWCOUT_SM0OUT45_SHIFT (0U) |
#define | PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) |
#define | PWM_SWCOUT_SM0OUT23_MASK (0x2U) |
#define | PWM_SWCOUT_SM0OUT23_SHIFT (1U) |
#define | PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) |
#define | PWM_SWCOUT_SM1OUT45_MASK (0x4U) |
#define | PWM_SWCOUT_SM1OUT45_SHIFT (2U) |
#define | PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) |
#define | PWM_SWCOUT_SM1OUT23_MASK (0x8U) |
#define | PWM_SWCOUT_SM1OUT23_SHIFT (3U) |
#define | PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) |
#define | PWM_SWCOUT_SM2OUT45_MASK (0x10U) |
#define | PWM_SWCOUT_SM2OUT45_SHIFT (4U) |
#define | PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) |
#define | PWM_SWCOUT_SM2OUT23_MASK (0x20U) |
#define | PWM_SWCOUT_SM2OUT23_SHIFT (5U) |
#define | PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) |
#define | PWM_SWCOUT_SM3OUT45_MASK (0x40U) |
#define | PWM_SWCOUT_SM3OUT45_SHIFT (6U) |
#define | PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) |
#define | PWM_SWCOUT_SM3OUT23_MASK (0x80U) |
#define | PWM_SWCOUT_SM3OUT23_SHIFT (7U) |
#define | PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) |
DTSRCSEL - PWM Source Select Register | |
#define | PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) |
#define | PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) |
#define | PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) |
#define | PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) |
#define | PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) |
#define | PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) |
#define | PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) |
#define | PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) |
#define | PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) |
#define | PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) |
#define | PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) |
#define | PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) |
#define | PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) |
#define | PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) |
#define | PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) |
#define | PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) |
#define | PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) |
#define | PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) |
#define | PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) |
#define | PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) |
#define | PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) |
#define | PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) |
#define | PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) |
#define | PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) |
MCTRL - Master Control Register | |
#define | PWM_MCTRL_LDOK_MASK (0xFU) |
#define | PWM_MCTRL_LDOK_SHIFT (0U) |
#define | PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) |
#define | PWM_MCTRL_CLDOK_MASK (0xF0U) |
#define | PWM_MCTRL_CLDOK_SHIFT (4U) |
#define | PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) |
#define | PWM_MCTRL_RUN_MASK (0xF00U) |
#define | PWM_MCTRL_RUN_SHIFT (8U) |
#define | PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) |
#define | PWM_MCTRL_IPOL_MASK (0xF000U) |
#define | PWM_MCTRL_IPOL_SHIFT (12U) |
#define | PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) |
MCTRL2 - Master Control 2 Register | |
#define | PWM_MCTRL2_MONPLL_MASK (0x3U) |
#define | PWM_MCTRL2_MONPLL_SHIFT (0U) |
#define | PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) |
FCTRL - Fault Control Register | |
#define | PWM_FCTRL_FIE_MASK (0xFU) |
#define | PWM_FCTRL_FIE_SHIFT (0U) |
#define | PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) |
#define | PWM_FCTRL_FSAFE_MASK (0xF0U) |
#define | PWM_FCTRL_FSAFE_SHIFT (4U) |
#define | PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) |
#define | PWM_FCTRL_FAUTO_MASK (0xF00U) |
#define | PWM_FCTRL_FAUTO_SHIFT (8U) |
#define | PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) |
#define | PWM_FCTRL_FLVL_MASK (0xF000U) |
#define | PWM_FCTRL_FLVL_SHIFT (12U) |
#define | PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) |
FSTS - Fault Status Register | |
#define | PWM_FSTS_FFLAG_MASK (0xFU) |
#define | PWM_FSTS_FFLAG_SHIFT (0U) |
#define | PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) |
#define | PWM_FSTS_FFULL_MASK (0xF0U) |
#define | PWM_FSTS_FFULL_SHIFT (4U) |
#define | PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) |
#define | PWM_FSTS_FFPIN_MASK (0xF00U) |
#define | PWM_FSTS_FFPIN_SHIFT (8U) |
#define | PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) |
#define | PWM_FSTS_FHALF_MASK (0xF000U) |
#define | PWM_FSTS_FHALF_SHIFT (12U) |
#define | PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) |
FFILT - Fault Filter Register | |
#define | PWM_FFILT_FILT_PER_MASK (0xFFU) |
#define | PWM_FFILT_FILT_PER_SHIFT (0U) |
#define | PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) |
#define | PWM_FFILT_FILT_CNT_MASK (0x700U) |
#define | PWM_FFILT_FILT_CNT_SHIFT (8U) |
#define | PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) |
#define | PWM_FFILT_GSTR_MASK (0x8000U) |
#define | PWM_FFILT_GSTR_SHIFT (15U) |
#define | PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) |
FTST - Fault Test Register | |
#define | PWM_FTST_FTEST_MASK (0x1U) |
#define | PWM_FTST_FTEST_SHIFT (0U) |
#define | PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) |
FCTRL2 - Fault Control 2 Register | |
#define | PWM_FCTRL2_NOCOMB_MASK (0xFU) |
#define | PWM_FCTRL2_NOCOMB_SHIFT (0U) |
#define | PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) |
CTRL - Control Register 0 | |
#define | PXP_CTRL_ENABLE_MASK (0x1U) |
#define | PXP_CTRL_ENABLE_SHIFT (0U) |
#define | PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) |
#define | PXP_CTRL_IRQ_ENABLE_MASK (0x2U) |
#define | PXP_CTRL_IRQ_ENABLE_SHIFT (1U) |
#define | PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK) |
#define | PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U) |
#define | PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U) |
#define | PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK) |
#define | PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U) |
#define | PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U) |
#define | PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK) |
#define | PXP_CTRL_ROTATE_MASK (0x300U) |
#define | PXP_CTRL_ROTATE_SHIFT (8U) |
#define | PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK) |
#define | PXP_CTRL_HFLIP_MASK (0x400U) |
#define | PXP_CTRL_HFLIP_SHIFT (10U) |
#define | PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK) |
#define | PXP_CTRL_VFLIP_MASK (0x800U) |
#define | PXP_CTRL_VFLIP_SHIFT (11U) |
#define | PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK) |
#define | PXP_CTRL_ROT_POS_MASK (0x400000U) |
#define | PXP_CTRL_ROT_POS_SHIFT (22U) |
#define | PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK) |
#define | PXP_CTRL_BLOCK_SIZE_MASK (0x800000U) |
#define | PXP_CTRL_BLOCK_SIZE_SHIFT (23U) |
#define | PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK) |
#define | PXP_CTRL_EN_REPEAT_MASK (0x10000000U) |
#define | PXP_CTRL_EN_REPEAT_SHIFT (28U) |
#define | PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK) |
#define | PXP_CTRL_CLKGATE_MASK (0x40000000U) |
#define | PXP_CTRL_CLKGATE_SHIFT (30U) |
#define | PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK) |
#define | PXP_CTRL_SFTRST_MASK (0x80000000U) |
#define | PXP_CTRL_SFTRST_SHIFT (31U) |
#define | PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) |
CTRL_SET - Control Register 0 | |
#define | PXP_CTRL_SET_ENABLE_MASK (0x1U) |
#define | PXP_CTRL_SET_ENABLE_SHIFT (0U) |
#define | PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) |
#define | PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U) |
#define | PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U) |
#define | PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK) |
#define | PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U) |
#define | PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U) |
#define | PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK) |
#define | PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U) |
#define | PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U) |
#define | PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK) |
#define | PXP_CTRL_SET_ROTATE_MASK (0x300U) |
#define | PXP_CTRL_SET_ROTATE_SHIFT (8U) |
#define | PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK) |
#define | PXP_CTRL_SET_HFLIP_MASK (0x400U) |
#define | PXP_CTRL_SET_HFLIP_SHIFT (10U) |
#define | PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK) |
#define | PXP_CTRL_SET_VFLIP_MASK (0x800U) |
#define | PXP_CTRL_SET_VFLIP_SHIFT (11U) |
#define | PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK) |
#define | PXP_CTRL_SET_ROT_POS_MASK (0x400000U) |
#define | PXP_CTRL_SET_ROT_POS_SHIFT (22U) |
#define | PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK) |
#define | PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) |
#define | PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) |
#define | PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) |
#define | PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U) |
#define | PXP_CTRL_SET_EN_REPEAT_SHIFT (28U) |
#define | PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK) |
#define | PXP_CTRL_SET_CLKGATE_MASK (0x40000000U) |
#define | PXP_CTRL_SET_CLKGATE_SHIFT (30U) |
#define | PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK) |
#define | PXP_CTRL_SET_SFTRST_MASK (0x80000000U) |
#define | PXP_CTRL_SET_SFTRST_SHIFT (31U) |
#define | PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) |
CTRL_CLR - Control Register 0 | |
#define | PXP_CTRL_CLR_ENABLE_MASK (0x1U) |
#define | PXP_CTRL_CLR_ENABLE_SHIFT (0U) |
#define | PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) |
#define | PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U) |
#define | PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U) |
#define | PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK) |
#define | PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U) |
#define | PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U) |
#define | PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK) |
#define | PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U) |
#define | PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U) |
#define | PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK) |
#define | PXP_CTRL_CLR_ROTATE_MASK (0x300U) |
#define | PXP_CTRL_CLR_ROTATE_SHIFT (8U) |
#define | PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK) |
#define | PXP_CTRL_CLR_HFLIP_MASK (0x400U) |
#define | PXP_CTRL_CLR_HFLIP_SHIFT (10U) |
#define | PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK) |
#define | PXP_CTRL_CLR_VFLIP_MASK (0x800U) |
#define | PXP_CTRL_CLR_VFLIP_SHIFT (11U) |
#define | PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK) |
#define | PXP_CTRL_CLR_ROT_POS_MASK (0x400000U) |
#define | PXP_CTRL_CLR_ROT_POS_SHIFT (22U) |
#define | PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK) |
#define | PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) |
#define | PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) |
#define | PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) |
#define | PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U) |
#define | PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U) |
#define | PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK) |
#define | PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U) |
#define | PXP_CTRL_CLR_CLKGATE_SHIFT (30U) |
#define | PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK) |
#define | PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) |
#define | PXP_CTRL_CLR_SFTRST_SHIFT (31U) |
#define | PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) |
CTRL_TOG - Control Register 0 | |
#define | PXP_CTRL_TOG_ENABLE_MASK (0x1U) |
#define | PXP_CTRL_TOG_ENABLE_SHIFT (0U) |
#define | PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) |
#define | PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U) |
#define | PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U) |
#define | PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK) |
#define | PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U) |
#define | PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U) |
#define | PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK) |
#define | PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U) |
#define | PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U) |
#define | PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK) |
#define | PXP_CTRL_TOG_ROTATE_MASK (0x300U) |
#define | PXP_CTRL_TOG_ROTATE_SHIFT (8U) |
#define | PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK) |
#define | PXP_CTRL_TOG_HFLIP_MASK (0x400U) |
#define | PXP_CTRL_TOG_HFLIP_SHIFT (10U) |
#define | PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK) |
#define | PXP_CTRL_TOG_VFLIP_MASK (0x800U) |
#define | PXP_CTRL_TOG_VFLIP_SHIFT (11U) |
#define | PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK) |
#define | PXP_CTRL_TOG_ROT_POS_MASK (0x400000U) |
#define | PXP_CTRL_TOG_ROT_POS_SHIFT (22U) |
#define | PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK) |
#define | PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) |
#define | PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) |
#define | PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) |
#define | PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U) |
#define | PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U) |
#define | PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK) |
#define | PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U) |
#define | PXP_CTRL_TOG_CLKGATE_SHIFT (30U) |
#define | PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK) |
#define | PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) |
#define | PXP_CTRL_TOG_SFTRST_SHIFT (31U) |
#define | PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) |
STAT - Status Register | |
#define | PXP_STAT_IRQ_MASK (0x1U) |
#define | PXP_STAT_IRQ_SHIFT (0U) |
#define | PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK) |
#define | PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U) |
#define | PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U) |
#define | PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK) |
#define | PXP_STAT_AXI_READ_ERROR_MASK (0x4U) |
#define | PXP_STAT_AXI_READ_ERROR_SHIFT (2U) |
#define | PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK) |
#define | PXP_STAT_NEXT_IRQ_MASK (0x8U) |
#define | PXP_STAT_NEXT_IRQ_SHIFT (3U) |
#define | PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK) |
#define | PXP_STAT_AXI_ERROR_ID_MASK (0xF0U) |
#define | PXP_STAT_AXI_ERROR_ID_SHIFT (4U) |
#define | PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK) |
#define | PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) |
#define | PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) |
#define | PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK) |
#define | PXP_STAT_BLOCKY_MASK (0xFF0000U) |
#define | PXP_STAT_BLOCKY_SHIFT (16U) |
#define | PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK) |
#define | PXP_STAT_BLOCKX_MASK (0xFF000000U) |
#define | PXP_STAT_BLOCKX_SHIFT (24U) |
#define | PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) |
STAT_SET - Status Register | |
#define | PXP_STAT_SET_IRQ_MASK (0x1U) |
#define | PXP_STAT_SET_IRQ_SHIFT (0U) |
#define | PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK) |
#define | PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U) |
#define | PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U) |
#define | PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK) |
#define | PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U) |
#define | PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U) |
#define | PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK) |
#define | PXP_STAT_SET_NEXT_IRQ_MASK (0x8U) |
#define | PXP_STAT_SET_NEXT_IRQ_SHIFT (3U) |
#define | PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK) |
#define | PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U) |
#define | PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U) |
#define | PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK) |
#define | PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) |
#define | PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) |
#define | PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK) |
#define | PXP_STAT_SET_BLOCKY_MASK (0xFF0000U) |
#define | PXP_STAT_SET_BLOCKY_SHIFT (16U) |
#define | PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK) |
#define | PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) |
#define | PXP_STAT_SET_BLOCKX_SHIFT (24U) |
#define | PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) |
STAT_CLR - Status Register | |
#define | PXP_STAT_CLR_IRQ_MASK (0x1U) |
#define | PXP_STAT_CLR_IRQ_SHIFT (0U) |
#define | PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK) |
#define | PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U) |
#define | PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U) |
#define | PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK) |
#define | PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U) |
#define | PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U) |
#define | PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK) |
#define | PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U) |
#define | PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U) |
#define | PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK) |
#define | PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U) |
#define | PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U) |
#define | PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK) |
#define | PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) |
#define | PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) |
#define | PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK) |
#define | PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U) |
#define | PXP_STAT_CLR_BLOCKY_SHIFT (16U) |
#define | PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK) |
#define | PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) |
#define | PXP_STAT_CLR_BLOCKX_SHIFT (24U) |
#define | PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) |
STAT_TOG - Status Register | |
#define | PXP_STAT_TOG_IRQ_MASK (0x1U) |
#define | PXP_STAT_TOG_IRQ_SHIFT (0U) |
#define | PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK) |
#define | PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U) |
#define | PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U) |
#define | PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK) |
#define | PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U) |
#define | PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U) |
#define | PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK) |
#define | PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U) |
#define | PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U) |
#define | PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK) |
#define | PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U) |
#define | PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U) |
#define | PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK) |
#define | PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) |
#define | PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) |
#define | PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK) |
#define | PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U) |
#define | PXP_STAT_TOG_BLOCKY_SHIFT (16U) |
#define | PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK) |
#define | PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) |
#define | PXP_STAT_TOG_BLOCKX_SHIFT (24U) |
#define | PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) |
OUT_CTRL - Output Buffer Control Register | |
#define | PXP_OUT_CTRL_FORMAT_MASK (0x1FU) |
#define | PXP_OUT_CTRL_FORMAT_SHIFT (0U) |
#define | PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) |
#define | PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U) |
#define | PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U) |
#define | PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) |
#define | PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U) |
#define | PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U) |
#define | PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK) |
#define | PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) |
#define | PXP_OUT_CTRL_ALPHA_SHIFT (24U) |
#define | PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) |
OUT_CTRL_SET - Output Buffer Control Register | |
#define | PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) |
#define | PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) |
#define | PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) |
#define | PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) |
#define | PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) |
#define | PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) |
#define | PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U) |
#define | PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U) |
#define | PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK) |
#define | PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) |
#define | PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) |
#define | PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) |
OUT_CTRL_CLR - Output Buffer Control Register | |
#define | PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) |
#define | PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) |
#define | PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) |
#define | PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) |
#define | PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) |
#define | PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) |
#define | PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U) |
#define | PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U) |
#define | PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK) |
#define | PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) |
#define | PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) |
#define | PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) |
OUT_CTRL_TOG - Output Buffer Control Register | |
#define | PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) |
#define | PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) |
#define | PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) |
#define | PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) |
#define | PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) |
#define | PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) |
#define | PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U) |
#define | PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U) |
#define | PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK) |
#define | PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) |
#define | PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) |
#define | PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) |
OUT_BUF - Output Frame Buffer Pointer | |
#define | PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) |
#define | PXP_OUT_BUF_ADDR_SHIFT (0U) |
#define | PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) |
OUT_BUF2 - Output Frame Buffer Pointer #2 | |
#define | PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) |
#define | PXP_OUT_BUF2_ADDR_SHIFT (0U) |
#define | PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) |
OUT_PITCH - Output Buffer Pitch | |
#define | PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) |
#define | PXP_OUT_PITCH_PITCH_SHIFT (0U) |
#define | PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) |
OUT_LRC - Output Surface Lower Right Coordinate | |
#define | PXP_OUT_LRC_Y_MASK (0x3FFFU) |
#define | PXP_OUT_LRC_Y_SHIFT (0U) |
#define | PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) |
#define | PXP_OUT_LRC_X_MASK (0x3FFF0000U) |
#define | PXP_OUT_LRC_X_SHIFT (16U) |
#define | PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK) |
OUT_PS_ULC - Processed Surface Upper Left Coordinate | |
#define | PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) |
#define | PXP_OUT_PS_ULC_Y_SHIFT (0U) |
#define | PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) |
#define | PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U) |
#define | PXP_OUT_PS_ULC_X_SHIFT (16U) |
#define | PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK) |
OUT_PS_LRC - Processed Surface Lower Right Coordinate | |
#define | PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) |
#define | PXP_OUT_PS_LRC_Y_SHIFT (0U) |
#define | PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) |
#define | PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U) |
#define | PXP_OUT_PS_LRC_X_SHIFT (16U) |
#define | PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK) |
OUT_AS_ULC - Alpha Surface Upper Left Coordinate | |
#define | PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) |
#define | PXP_OUT_AS_ULC_Y_SHIFT (0U) |
#define | PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) |
#define | PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U) |
#define | PXP_OUT_AS_ULC_X_SHIFT (16U) |
#define | PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK) |
OUT_AS_LRC - Alpha Surface Lower Right Coordinate | |
#define | PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) |
#define | PXP_OUT_AS_LRC_Y_SHIFT (0U) |
#define | PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) |
#define | PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U) |
#define | PXP_OUT_AS_LRC_X_SHIFT (16U) |
#define | PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK) |
PS_CTRL - Processed Surface (PS) Control Register | |
#define | PXP_PS_CTRL_FORMAT_MASK (0x3FU) |
#define | PXP_PS_CTRL_FORMAT_SHIFT (0U) |
#define | PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) |
#define | PXP_PS_CTRL_WB_SWAP_MASK (0x40U) |
#define | PXP_PS_CTRL_WB_SWAP_SHIFT (6U) |
#define | PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK) |
#define | PXP_PS_CTRL_DECY_MASK (0x300U) |
#define | PXP_PS_CTRL_DECY_SHIFT (8U) |
#define | PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK) |
#define | PXP_PS_CTRL_DECX_MASK (0xC00U) |
#define | PXP_PS_CTRL_DECX_SHIFT (10U) |
#define | PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) |
PS_CTRL_SET - Processed Surface (PS) Control Register | |
#define | PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU) |
#define | PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) |
#define | PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) |
#define | PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U) |
#define | PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U) |
#define | PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK) |
#define | PXP_PS_CTRL_SET_DECY_MASK (0x300U) |
#define | PXP_PS_CTRL_SET_DECY_SHIFT (8U) |
#define | PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) |
#define | PXP_PS_CTRL_SET_DECX_MASK (0xC00U) |
#define | PXP_PS_CTRL_SET_DECX_SHIFT (10U) |
#define | PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) |
PS_CTRL_CLR - Processed Surface (PS) Control Register | |
#define | PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU) |
#define | PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) |
#define | PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) |
#define | PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U) |
#define | PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U) |
#define | PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK) |
#define | PXP_PS_CTRL_CLR_DECY_MASK (0x300U) |
#define | PXP_PS_CTRL_CLR_DECY_SHIFT (8U) |
#define | PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) |
#define | PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) |
#define | PXP_PS_CTRL_CLR_DECX_SHIFT (10U) |
#define | PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) |
PS_CTRL_TOG - Processed Surface (PS) Control Register | |
#define | PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU) |
#define | PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) |
#define | PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) |
#define | PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U) |
#define | PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U) |
#define | PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK) |
#define | PXP_PS_CTRL_TOG_DECY_MASK (0x300U) |
#define | PXP_PS_CTRL_TOG_DECY_SHIFT (8U) |
#define | PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) |
#define | PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) |
#define | PXP_PS_CTRL_TOG_DECX_SHIFT (10U) |
#define | PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) |
PS_BUF - PS Input Buffer Address | |
#define | PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) |
#define | PXP_PS_BUF_ADDR_SHIFT (0U) |
#define | PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) |
PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address | |
#define | PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) |
#define | PXP_PS_UBUF_ADDR_SHIFT (0U) |
#define | PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) |
PS_VBUF - PS V/Cr Input Buffer Address | |
#define | PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) |
#define | PXP_PS_VBUF_ADDR_SHIFT (0U) |
#define | PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) |
PS_PITCH - Processed Surface Pitch | |
#define | PXP_PS_PITCH_PITCH_MASK (0xFFFFU) |
#define | PXP_PS_PITCH_PITCH_SHIFT (0U) |
#define | PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) |
PS_BACKGROUND - PS Background Color | |
#define | PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU) |
#define | PXP_PS_BACKGROUND_COLOR_SHIFT (0U) |
#define | PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK) |
PS_SCALE - PS Scale Factor Register | |
#define | PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) |
#define | PXP_PS_SCALE_XSCALE_SHIFT (0U) |
#define | PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) |
#define | PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U) |
#define | PXP_PS_SCALE_YSCALE_SHIFT (16U) |
#define | PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK) |
PS_OFFSET - PS Scale Offset Register | |
#define | PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) |
#define | PXP_PS_OFFSET_XOFFSET_SHIFT (0U) |
#define | PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) |
#define | PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U) |
#define | PXP_PS_OFFSET_YOFFSET_SHIFT (16U) |
#define | PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK) |
PS_CLRKEYLOW - PS Color Key Low | |
#define | PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) |
#define | PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U) |
#define | PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK) |
PS_CLRKEYHIGH - PS Color Key High | |
#define | PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) |
#define | PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U) |
#define | PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK) |
AS_CTRL - Alpha Surface Control | |
#define | PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U) |
#define | PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U) |
#define | PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK) |
#define | PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) |
#define | PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) |
#define | PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK) |
#define | PXP_AS_CTRL_FORMAT_MASK (0xF0U) |
#define | PXP_AS_CTRL_FORMAT_SHIFT (4U) |
#define | PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK) |
#define | PXP_AS_CTRL_ALPHA_MASK (0xFF00U) |
#define | PXP_AS_CTRL_ALPHA_SHIFT (8U) |
#define | PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK) |
#define | PXP_AS_CTRL_ROP_MASK (0xF0000U) |
#define | PXP_AS_CTRL_ROP_SHIFT (16U) |
#define | PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK) |
#define | PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) |
#define | PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U) |
#define | PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK) |
AS_BUF - Alpha Surface Buffer Pointer | |
#define | PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) |
#define | PXP_AS_BUF_ADDR_SHIFT (0U) |
#define | PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) |
AS_PITCH - Alpha Surface Pitch | |
#define | PXP_AS_PITCH_PITCH_MASK (0xFFFFU) |
#define | PXP_AS_PITCH_PITCH_SHIFT (0U) |
#define | PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) |
AS_CLRKEYLOW - Overlay Color Key Low | |
#define | PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) |
#define | PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U) |
#define | PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK) |
AS_CLRKEYHIGH - Overlay Color Key High | |
#define | PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) |
#define | PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) |
#define | PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK) |
CSC1_COEF0 - Color Space Conversion Coefficient Register 0 | |
#define | PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) |
#define | PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) |
#define | PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) |
#define | PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U) |
#define | PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U) |
#define | PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK) |
#define | PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U) |
#define | PXP_CSC1_COEF0_C0_SHIFT (18U) |
#define | PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK) |
#define | PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U) |
#define | PXP_CSC1_COEF0_BYPASS_SHIFT (30U) |
#define | PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK) |
#define | PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) |
#define | PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) |
#define | PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) |
CSC1_COEF1 - Color Space Conversion Coefficient Register 1 | |
#define | PXP_CSC1_COEF1_C4_MASK (0x7FFU) |
#define | PXP_CSC1_COEF1_C4_SHIFT (0U) |
#define | PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) |
#define | PXP_CSC1_COEF1_C1_MASK (0x7FF0000U) |
#define | PXP_CSC1_COEF1_C1_SHIFT (16U) |
#define | PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK) |
CSC1_COEF2 - Color Space Conversion Coefficient Register 2 | |
#define | PXP_CSC1_COEF2_C3_MASK (0x7FFU) |
#define | PXP_CSC1_COEF2_C3_SHIFT (0U) |
#define | PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) |
#define | PXP_CSC1_COEF2_C2_MASK (0x7FF0000U) |
#define | PXP_CSC1_COEF2_C2_SHIFT (16U) |
#define | PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK) |
POWER - PXP Power Control Register | |
#define | PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U) |
#define | PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U) |
#define | PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK) |
NEXT - Next Frame Pointer | |
#define | PXP_NEXT_ENABLED_MASK (0x1U) |
#define | PXP_NEXT_ENABLED_SHIFT (0U) |
#define | PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) |
#define | PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) |
#define | PXP_NEXT_POINTER_SHIFT (2U) |
#define | PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) |
PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. | |
#define | PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U) |
#define | PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U) |
#define | PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK) |
#define | PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U) |
#define | PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U) |
#define | PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK) |
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U) |
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U) |
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) |
#define | PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U) |
#define | PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U) |
#define | PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK) |
#define | PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U) |
#define | PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U) |
#define | PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK) |
#define | PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U) |
#define | PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U) |
#define | PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK) |
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U) |
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U) |
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) |
#define | PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U) |
#define | PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U) |
#define | PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK) |
#define | PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U) |
#define | PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U) |
#define | PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK) |
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U) |
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U) |
#define | PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK) |
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) |
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) |
#define | PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK) |
VIR - Version Information | |
#define | RDC_VIR_NDID_MASK (0xFU) |
#define | RDC_VIR_NDID_SHIFT (0U) |
#define | RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK) |
#define | RDC_VIR_NMSTR_MASK (0xFF0U) |
#define | RDC_VIR_NMSTR_SHIFT (4U) |
#define | RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK) |
#define | RDC_VIR_NPER_MASK (0xFF000U) |
#define | RDC_VIR_NPER_SHIFT (12U) |
#define | RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK) |
#define | RDC_VIR_NRGN_MASK (0xFF00000U) |
#define | RDC_VIR_NRGN_SHIFT (20U) |
#define | RDC_VIR_NRGN(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK) |
STAT - Status | |
#define | RDC_STAT_DID_MASK (0xFU) |
#define | RDC_STAT_DID_SHIFT (0U) |
#define | RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK) |
#define | RDC_STAT_PDS_MASK (0x100U) |
#define | RDC_STAT_PDS_SHIFT (8U) |
#define | RDC_STAT_PDS(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK) |
INTCTRL - Interrupt and Control | |
#define | RDC_INTCTRL_RCI_EN_MASK (0x1U) |
#define | RDC_INTCTRL_RCI_EN_SHIFT (0U) |
#define | RDC_INTCTRL_RCI_EN(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK) |
INTSTAT - Interrupt Status | |
#define | RDC_INTSTAT_INT_MASK (0x1U) |
#define | RDC_INTSTAT_INT_SHIFT (0U) |
#define | RDC_INTSTAT_INT(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK) |
MDA - Master Domain Assignment | |
#define | RDC_MDA_DID_MASK (0x3U) |
#define | RDC_MDA_DID_SHIFT (0U) |
#define | RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK) |
#define | RDC_MDA_LCK_MASK (0x80000000U) |
#define | RDC_MDA_LCK_SHIFT (31U) |
#define | RDC_MDA_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK) |
PDAP - Peripheral Domain Access Permissions | |
#define | RDC_PDAP_D0W_MASK (0x1U) |
#define | RDC_PDAP_D0W_SHIFT (0U) |
#define | RDC_PDAP_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK) |
#define | RDC_PDAP_D0R_MASK (0x2U) |
#define | RDC_PDAP_D0R_SHIFT (1U) |
#define | RDC_PDAP_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK) |
#define | RDC_PDAP_D1W_MASK (0x4U) |
#define | RDC_PDAP_D1W_SHIFT (2U) |
#define | RDC_PDAP_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK) |
#define | RDC_PDAP_D1R_MASK (0x8U) |
#define | RDC_PDAP_D1R_SHIFT (3U) |
#define | RDC_PDAP_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK) |
#define | RDC_PDAP_SREQ_MASK (0x40000000U) |
#define | RDC_PDAP_SREQ_SHIFT (30U) |
#define | RDC_PDAP_SREQ(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK) |
#define | RDC_PDAP_LCK_MASK (0x80000000U) |
#define | RDC_PDAP_LCK_SHIFT (31U) |
#define | RDC_PDAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK) |
MRSA - Memory Region Start Address | |
#define | RDC_MRSA_SADR_MASK (0xFFFFFF80U) |
#define | RDC_MRSA_SADR_SHIFT (7U) |
#define | RDC_MRSA_SADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK) |
MREA - Memory Region End Address | |
#define | RDC_MREA_EADR_MASK (0xFFFFFF80U) |
#define | RDC_MREA_EADR_SHIFT (7U) |
#define | RDC_MREA_EADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK) |
MRC - Memory Region Control | |
#define | RDC_MRC_D0W_MASK (0x1U) |
#define | RDC_MRC_D0W_SHIFT (0U) |
#define | RDC_MRC_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK) |
#define | RDC_MRC_D0R_MASK (0x2U) |
#define | RDC_MRC_D0R_SHIFT (1U) |
#define | RDC_MRC_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK) |
#define | RDC_MRC_D1W_MASK (0x4U) |
#define | RDC_MRC_D1W_SHIFT (2U) |
#define | RDC_MRC_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK) |
#define | RDC_MRC_D1R_MASK (0x8U) |
#define | RDC_MRC_D1R_SHIFT (3U) |
#define | RDC_MRC_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK) |
#define | RDC_MRC_ENA_MASK (0x40000000U) |
#define | RDC_MRC_ENA_SHIFT (30U) |
#define | RDC_MRC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK) |
#define | RDC_MRC_LCK_MASK (0x80000000U) |
#define | RDC_MRC_LCK_SHIFT (31U) |
#define | RDC_MRC_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK) |
MRVS - Memory Region Violation Status | |
#define | RDC_MRVS_VDID_MASK (0x3U) |
#define | RDC_MRVS_VDID_SHIFT (0U) |
#define | RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK) |
#define | RDC_MRVS_AD_MASK (0x10U) |
#define | RDC_MRVS_AD_SHIFT (4U) |
#define | RDC_MRVS_AD(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK) |
#define | RDC_MRVS_VADR_MASK (0xFFFFFFE0U) |
#define | RDC_MRVS_VADR_SHIFT (5U) |
#define | RDC_MRVS_VADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK) |
GATE - Gate Register | |
#define | RDC_SEMAPHORE_GATE_GTFSM_MASK (0xFU) |
#define | RDC_SEMAPHORE_GATE_GTFSM_SHIFT (0U) |
#define | RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE_GTFSM_MASK) |
#define | RDC_SEMAPHORE_GATE_LDOM_MASK (0x30U) |
#define | RDC_SEMAPHORE_GATE_LDOM_SHIFT (4U) |
#define | RDC_SEMAPHORE_GATE_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE_LDOM_MASK) |
RSTGT_R - Reset Gate Read | |
#define | RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU) |
#define | RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U) |
#define | RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK) |
#define | RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U) |
#define | RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U) |
#define | RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) |
#define | RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U) |
#define | RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U) |
#define | RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK) |
RSTGT_W - Reset Gate Write | |
#define | RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU) |
#define | RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U) |
#define | RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK) |
#define | RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U) |
#define | RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U) |
#define | RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK) |
CS - Watchdog Control and Status Register | |
#define | RTWDOG_CS_STOP_MASK (0x1U) |
#define | RTWDOG_CS_STOP_SHIFT (0U) |
#define | RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) |
#define | RTWDOG_CS_WAIT_MASK (0x2U) |
#define | RTWDOG_CS_WAIT_SHIFT (1U) |
#define | RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) |
#define | RTWDOG_CS_DBG_MASK (0x4U) |
#define | RTWDOG_CS_DBG_SHIFT (2U) |
#define | RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) |
#define | RTWDOG_CS_TST_MASK (0x18U) |
#define | RTWDOG_CS_TST_SHIFT (3U) |
#define | RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) |
#define | RTWDOG_CS_UPDATE_MASK (0x20U) |
#define | RTWDOG_CS_UPDATE_SHIFT (5U) |
#define | RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) |
#define | RTWDOG_CS_INT_MASK (0x40U) |
#define | RTWDOG_CS_INT_SHIFT (6U) |
#define | RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) |
#define | RTWDOG_CS_EN_MASK (0x80U) |
#define | RTWDOG_CS_EN_SHIFT (7U) |
#define | RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) |
#define | RTWDOG_CS_CLK_MASK (0x300U) |
#define | RTWDOG_CS_CLK_SHIFT (8U) |
#define | RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) |
#define | RTWDOG_CS_RCS_MASK (0x400U) |
#define | RTWDOG_CS_RCS_SHIFT (10U) |
#define | RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) |
#define | RTWDOG_CS_ULK_MASK (0x800U) |
#define | RTWDOG_CS_ULK_SHIFT (11U) |
#define | RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) |
#define | RTWDOG_CS_PRES_MASK (0x1000U) |
#define | RTWDOG_CS_PRES_SHIFT (12U) |
#define | RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) |
#define | RTWDOG_CS_CMD32EN_MASK (0x2000U) |
#define | RTWDOG_CS_CMD32EN_SHIFT (13U) |
#define | RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) |
#define | RTWDOG_CS_FLG_MASK (0x4000U) |
#define | RTWDOG_CS_FLG_SHIFT (14U) |
#define | RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) |
#define | RTWDOG_CS_WIN_MASK (0x8000U) |
#define | RTWDOG_CS_WIN_SHIFT (15U) |
#define | RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) |
CNT - Watchdog Counter Register | |
#define | RTWDOG_CNT_CNTLOW_MASK (0xFFU) |
#define | RTWDOG_CNT_CNTLOW_SHIFT (0U) |
#define | RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) |
#define | RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) |
#define | RTWDOG_CNT_CNTHIGH_SHIFT (8U) |
#define | RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) |
TOVAL - Watchdog Timeout Value Register | |
#define | RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) |
#define | RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) |
#define | RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) |
#define | RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) |
#define | RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) |
#define | RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) |
WIN - Watchdog Window Register | |
#define | RTWDOG_WIN_WINLOW_MASK (0xFFU) |
#define | RTWDOG_WIN_WINLOW_SHIFT (0U) |
#define | RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) |
#define | RTWDOG_WIN_WINHIGH_MASK (0xFF00U) |
#define | RTWDOG_WIN_WINHIGH_SHIFT (8U) |
#define | RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) |
GATE - Semaphores Gate n Register | |
#define | SEMA4_GATE_GTFSM_MASK (0x3U) |
#define | SEMA4_GATE_GTFSM_SHIFT (0U) |
#define | SEMA4_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_GATE_GTFSM_SHIFT)) & SEMA4_GATE_GTFSM_MASK) |
CPINE - Semaphores Processor n IRQ Notification Enable | |
#define | SEMA4_CPINE_INE7_MASK (0x1U) |
#define | SEMA4_CPINE_INE7_SHIFT (0U) |
#define | SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK) |
#define | SEMA4_CPINE_INE6_MASK (0x2U) |
#define | SEMA4_CPINE_INE6_SHIFT (1U) |
#define | SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK) |
#define | SEMA4_CPINE_INE5_MASK (0x4U) |
#define | SEMA4_CPINE_INE5_SHIFT (2U) |
#define | SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK) |
#define | SEMA4_CPINE_INE4_MASK (0x8U) |
#define | SEMA4_CPINE_INE4_SHIFT (3U) |
#define | SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK) |
#define | SEMA4_CPINE_INE3_MASK (0x10U) |
#define | SEMA4_CPINE_INE3_SHIFT (4U) |
#define | SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK) |
#define | SEMA4_CPINE_INE2_MASK (0x20U) |
#define | SEMA4_CPINE_INE2_SHIFT (5U) |
#define | SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK) |
#define | SEMA4_CPINE_INE1_MASK (0x40U) |
#define | SEMA4_CPINE_INE1_SHIFT (6U) |
#define | SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK) |
#define | SEMA4_CPINE_INE0_MASK (0x80U) |
#define | SEMA4_CPINE_INE0_SHIFT (7U) |
#define | SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK) |
#define | SEMA4_CPINE_INE15_MASK (0x100U) |
#define | SEMA4_CPINE_INE15_SHIFT (8U) |
#define | SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK) |
#define | SEMA4_CPINE_INE14_MASK (0x200U) |
#define | SEMA4_CPINE_INE14_SHIFT (9U) |
#define | SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK) |
#define | SEMA4_CPINE_INE13_MASK (0x400U) |
#define | SEMA4_CPINE_INE13_SHIFT (10U) |
#define | SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK) |
#define | SEMA4_CPINE_INE12_MASK (0x800U) |
#define | SEMA4_CPINE_INE12_SHIFT (11U) |
#define | SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK) |
#define | SEMA4_CPINE_INE11_MASK (0x1000U) |
#define | SEMA4_CPINE_INE11_SHIFT (12U) |
#define | SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK) |
#define | SEMA4_CPINE_INE10_MASK (0x2000U) |
#define | SEMA4_CPINE_INE10_SHIFT (13U) |
#define | SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK) |
#define | SEMA4_CPINE_INE9_MASK (0x4000U) |
#define | SEMA4_CPINE_INE9_SHIFT (14U) |
#define | SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK) |
#define | SEMA4_CPINE_INE8_MASK (0x8000U) |
#define | SEMA4_CPINE_INE8_SHIFT (15U) |
#define | SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK) |
CPNTF - Semaphores Processor n IRQ Notification | |
#define | SEMA4_CPNTF_GN7_MASK (0x1U) |
#define | SEMA4_CPNTF_GN7_SHIFT (0U) |
#define | SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK) |
#define | SEMA4_CPNTF_GN6_MASK (0x2U) |
#define | SEMA4_CPNTF_GN6_SHIFT (1U) |
#define | SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK) |
#define | SEMA4_CPNTF_GN5_MASK (0x4U) |
#define | SEMA4_CPNTF_GN5_SHIFT (2U) |
#define | SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK) |
#define | SEMA4_CPNTF_GN4_MASK (0x8U) |
#define | SEMA4_CPNTF_GN4_SHIFT (3U) |
#define | SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK) |
#define | SEMA4_CPNTF_GN3_MASK (0x10U) |
#define | SEMA4_CPNTF_GN3_SHIFT (4U) |
#define | SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK) |
#define | SEMA4_CPNTF_GN2_MASK (0x20U) |
#define | SEMA4_CPNTF_GN2_SHIFT (5U) |
#define | SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK) |
#define | SEMA4_CPNTF_GN1_MASK (0x40U) |
#define | SEMA4_CPNTF_GN1_SHIFT (6U) |
#define | SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK) |
#define | SEMA4_CPNTF_GN0_MASK (0x80U) |
#define | SEMA4_CPNTF_GN0_SHIFT (7U) |
#define | SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK) |
#define | SEMA4_CPNTF_GN15_MASK (0x100U) |
#define | SEMA4_CPNTF_GN15_SHIFT (8U) |
#define | SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK) |
#define | SEMA4_CPNTF_GN14_MASK (0x200U) |
#define | SEMA4_CPNTF_GN14_SHIFT (9U) |
#define | SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK) |
#define | SEMA4_CPNTF_GN13_MASK (0x400U) |
#define | SEMA4_CPNTF_GN13_SHIFT (10U) |
#define | SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK) |
#define | SEMA4_CPNTF_GN12_MASK (0x800U) |
#define | SEMA4_CPNTF_GN12_SHIFT (11U) |
#define | SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK) |
#define | SEMA4_CPNTF_GN11_MASK (0x1000U) |
#define | SEMA4_CPNTF_GN11_SHIFT (12U) |
#define | SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK) |
#define | SEMA4_CPNTF_GN10_MASK (0x2000U) |
#define | SEMA4_CPNTF_GN10_SHIFT (13U) |
#define | SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK) |
#define | SEMA4_CPNTF_GN9_MASK (0x4000U) |
#define | SEMA4_CPNTF_GN9_SHIFT (14U) |
#define | SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK) |
#define | SEMA4_CPNTF_GN8_MASK (0x8000U) |
#define | SEMA4_CPNTF_GN8_SHIFT (15U) |
#define | SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK) |
RSTGT - Semaphores (Secure) Reset Gate n | |
#define | SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU) |
#define | SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U) |
#define | SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK) |
#define | SEMA4_RSTGT_RSTGTN_MASK (0xFF00U) |
#define | SEMA4_RSTGT_RSTGTN_SHIFT (8U) |
#define | SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK) |
RSTNTF - Semaphores (Secure) Reset IRQ Notification | |
#define | SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU) |
#define | SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U) |
#define | SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK) |
#define | SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U) |
#define | SEMA4_RSTNTF_RSTNTN_SHIFT (8U) |
#define | SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK) |
MCR - Module Control Register | |
#define | SEMC_MCR_SWRST_MASK (0x1U) |
#define | SEMC_MCR_SWRST_SHIFT (0U) |
#define | SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) |
#define | SEMC_MCR_MDIS_MASK (0x2U) |
#define | SEMC_MCR_MDIS_SHIFT (1U) |
#define | SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) |
#define | SEMC_MCR_DQSMD_MASK (0x4U) |
#define | SEMC_MCR_DQSMD_SHIFT (2U) |
#define | SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) |
#define | SEMC_MCR_WPOL0_MASK (0x40U) |
#define | SEMC_MCR_WPOL0_SHIFT (6U) |
#define | SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) |
#define | SEMC_MCR_WPOL1_MASK (0x80U) |
#define | SEMC_MCR_WPOL1_SHIFT (7U) |
#define | SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) |
#define | SEMC_MCR_CTO_MASK (0xFF0000U) |
#define | SEMC_MCR_CTO_SHIFT (16U) |
#define | SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) |
#define | SEMC_MCR_BTO_MASK (0x1F000000U) |
#define | SEMC_MCR_BTO_SHIFT (24U) |
#define | SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) |
#define | XRDC2_MCR_GVLDM_MASK (0x1U) |
#define | XRDC2_MCR_GVLDM_SHIFT (0U) |
#define | XRDC2_MCR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK) |
#define | XRDC2_MCR_GVLDC_MASK (0x2U) |
#define | XRDC2_MCR_GVLDC_SHIFT (1U) |
#define | XRDC2_MCR_GVLDC(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK) |
#define | XRDC2_MCR_GCL_MASK (0x30U) |
#define | XRDC2_MCR_GCL_SHIFT (4U) |
#define | XRDC2_MCR_GCL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK) |
IOCR - IO MUX Control Register | |
#define | SEMC_IOCR_MUX_A8_MASK (0xFU) |
#define | SEMC_IOCR_MUX_A8_SHIFT (0U) |
#define | SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) |
#define | SEMC_IOCR_MUX_CSX0_MASK (0xF0U) |
#define | SEMC_IOCR_MUX_CSX0_SHIFT (4U) |
#define | SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) |
#define | SEMC_IOCR_MUX_CSX1_MASK (0xF00U) |
#define | SEMC_IOCR_MUX_CSX1_SHIFT (8U) |
#define | SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) |
#define | SEMC_IOCR_MUX_CSX2_MASK (0xF000U) |
#define | SEMC_IOCR_MUX_CSX2_SHIFT (12U) |
#define | SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) |
#define | SEMC_IOCR_MUX_CSX3_MASK (0xF0000U) |
#define | SEMC_IOCR_MUX_CSX3_SHIFT (16U) |
#define | SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) |
#define | SEMC_IOCR_MUX_RDY_MASK (0xF00000U) |
#define | SEMC_IOCR_MUX_RDY_SHIFT (20U) |
#define | SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) |
#define | SEMC_IOCR_MUX_CLKX0_MASK (0x3000000U) |
#define | SEMC_IOCR_MUX_CLKX0_SHIFT (24U) |
#define | SEMC_IOCR_MUX_CLKX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK) |
#define | SEMC_IOCR_MUX_CLKX1_MASK (0xC000000U) |
#define | SEMC_IOCR_MUX_CLKX1_SHIFT (26U) |
#define | SEMC_IOCR_MUX_CLKX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK) |
#define | SEMC_IOCR_CLKX0_AO_MASK (0x10000000U) |
#define | SEMC_IOCR_CLKX0_AO_SHIFT (28U) |
#define | SEMC_IOCR_CLKX0_AO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX0_AO_SHIFT)) & SEMC_IOCR_CLKX0_AO_MASK) |
#define | SEMC_IOCR_CLKX1_AO_MASK (0x20000000U) |
#define | SEMC_IOCR_CLKX1_AO_SHIFT (29U) |
#define | SEMC_IOCR_CLKX1_AO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX1_AO_SHIFT)) & SEMC_IOCR_CLKX1_AO_MASK) |
BMCR0 - Bus (AXI) Master Control Register 0 | |
#define | SEMC_BMCR0_WQOS_MASK (0xFU) |
#define | SEMC_BMCR0_WQOS_SHIFT (0U) |
#define | SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) |
#define | SEMC_BMCR0_WAGE_MASK (0xF0U) |
#define | SEMC_BMCR0_WAGE_SHIFT (4U) |
#define | SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) |
#define | SEMC_BMCR0_WSH_MASK (0xFF00U) |
#define | SEMC_BMCR0_WSH_SHIFT (8U) |
#define | SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) |
#define | SEMC_BMCR0_WRWS_MASK (0xFF0000U) |
#define | SEMC_BMCR0_WRWS_SHIFT (16U) |
#define | SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) |
BMCR1 - Bus (AXI) Master Control Register 1 | |
#define | SEMC_BMCR1_WQOS_MASK (0xFU) |
#define | SEMC_BMCR1_WQOS_SHIFT (0U) |
#define | SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) |
#define | SEMC_BMCR1_WAGE_MASK (0xF0U) |
#define | SEMC_BMCR1_WAGE_SHIFT (4U) |
#define | SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) |
#define | SEMC_BMCR1_WPH_MASK (0xFF00U) |
#define | SEMC_BMCR1_WPH_SHIFT (8U) |
#define | SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) |
#define | SEMC_BMCR1_WRWS_MASK (0xFF0000U) |
#define | SEMC_BMCR1_WRWS_SHIFT (16U) |
#define | SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) |
#define | SEMC_BMCR1_WBR_MASK (0xFF000000U) |
#define | SEMC_BMCR1_WBR_SHIFT (24U) |
#define | SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) |
BR - Base Register 0..Base Register 8 | |
#define | SEMC_BR_VLD_MASK (0x1U) |
#define | SEMC_BR_VLD_SHIFT (0U) |
#define | SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) |
#define | SEMC_BR_MS_MASK (0x3EU) |
#define | SEMC_BR_MS_SHIFT (1U) |
#define | SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) |
#define | SEMC_BR_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR_BA_SHIFT (12U) |
#define | SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) |
DLLCR - DLL Control Register | |
#define | SEMC_DLLCR_DLLEN_MASK (0x1U) |
#define | SEMC_DLLCR_DLLEN_SHIFT (0U) |
#define | SEMC_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK) |
#define | SEMC_DLLCR_DLLRESET_MASK (0x2U) |
#define | SEMC_DLLCR_DLLRESET_SHIFT (1U) |
#define | SEMC_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK) |
#define | SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U) |
#define | SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U) |
#define | SEMC_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK) |
#define | SEMC_DLLCR_OVRDEN_MASK (0x100U) |
#define | SEMC_DLLCR_OVRDEN_SHIFT (8U) |
#define | SEMC_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK) |
#define | SEMC_DLLCR_OVRDVAL_MASK (0x7E00U) |
#define | SEMC_DLLCR_OVRDVAL_SHIFT (9U) |
#define | SEMC_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK) |
SDRAMCR0 - SDRAM Control Register 0 | |
#define | SEMC_SDRAMCR0_PS_MASK (0x3U) |
#define | SEMC_SDRAMCR0_PS_SHIFT (0U) |
#define | SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) |
#define | SEMC_SDRAMCR0_BL_MASK (0x70U) |
#define | SEMC_SDRAMCR0_BL_SHIFT (4U) |
#define | SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) |
#define | SEMC_SDRAMCR0_COL8_MASK (0x80U) |
#define | SEMC_SDRAMCR0_COL8_SHIFT (7U) |
#define | SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK) |
#define | SEMC_SDRAMCR0_COL_MASK (0x300U) |
#define | SEMC_SDRAMCR0_COL_SHIFT (8U) |
#define | SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) |
#define | SEMC_SDRAMCR0_CL_MASK (0xC00U) |
#define | SEMC_SDRAMCR0_CL_SHIFT (10U) |
#define | SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) |
#define | SEMC_SDRAMCR0_BANK2_MASK (0x4000U) |
#define | SEMC_SDRAMCR0_BANK2_SHIFT (14U) |
#define | SEMC_SDRAMCR0_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK) |
SDRAMCR1 - SDRAM Control Register 1 | |
#define | SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) |
#define | SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) |
#define | SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) |
#define | SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U) |
#define | SEMC_SDRAMCR1_ACT2RW_SHIFT (4U) |
#define | SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) |
#define | SEMC_SDRAMCR1_RFRC_MASK (0x1F00U) |
#define | SEMC_SDRAMCR1_RFRC_SHIFT (8U) |
#define | SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) |
#define | SEMC_SDRAMCR1_WRC_MASK (0xE000U) |
#define | SEMC_SDRAMCR1_WRC_SHIFT (13U) |
#define | SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) |
#define | SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U) |
#define | SEMC_SDRAMCR1_CKEOFF_SHIFT (16U) |
#define | SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) |
#define | SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) |
#define | SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) |
#define | SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) |
SDRAMCR2 - SDRAM Control Register 2 | |
#define | SEMC_SDRAMCR2_SRRC_MASK (0xFFU) |
#define | SEMC_SDRAMCR2_SRRC_SHIFT (0U) |
#define | SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) |
#define | SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U) |
#define | SEMC_SDRAMCR2_REF2REF_SHIFT (8U) |
#define | SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) |
#define | SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U) |
#define | SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U) |
#define | SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) |
#define | SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) |
#define | SEMC_SDRAMCR2_ITO_SHIFT (24U) |
#define | SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) |
SDRAMCR3 - SDRAM Control Register 3 | |
#define | SEMC_SDRAMCR3_REN_MASK (0x1U) |
#define | SEMC_SDRAMCR3_REN_SHIFT (0U) |
#define | SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) |
#define | SEMC_SDRAMCR3_REBL_MASK (0xEU) |
#define | SEMC_SDRAMCR3_REBL_SHIFT (1U) |
#define | SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) |
#define | SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) |
#define | SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) |
#define | SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) |
#define | SEMC_SDRAMCR3_RT_MASK (0xFF0000U) |
#define | SEMC_SDRAMCR3_RT_SHIFT (16U) |
#define | SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) |
#define | SEMC_SDRAMCR3_UT_MASK (0xFF000000U) |
#define | SEMC_SDRAMCR3_UT_SHIFT (24U) |
#define | SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) |
NANDCR0 - NAND Control Register 0 | |
#define | SEMC_NANDCR0_PS_MASK (0x1U) |
#define | SEMC_NANDCR0_PS_SHIFT (0U) |
#define | SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) |
#define | SEMC_NANDCR0_SYNCEN_MASK (0x2U) |
#define | SEMC_NANDCR0_SYNCEN_SHIFT (1U) |
#define | SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK) |
#define | SEMC_NANDCR0_BL_MASK (0x70U) |
#define | SEMC_NANDCR0_BL_SHIFT (4U) |
#define | SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) |
#define | SEMC_NANDCR0_EDO_MASK (0x80U) |
#define | SEMC_NANDCR0_EDO_SHIFT (7U) |
#define | SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) |
#define | SEMC_NANDCR0_COL_MASK (0x700U) |
#define | SEMC_NANDCR0_COL_SHIFT (8U) |
#define | SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) |
NANDCR1 - NAND Control Register 1 | |
#define | SEMC_NANDCR1_CES_MASK (0xFU) |
#define | SEMC_NANDCR1_CES_SHIFT (0U) |
#define | SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) |
#define | SEMC_NANDCR1_CEH_MASK (0xF0U) |
#define | SEMC_NANDCR1_CEH_SHIFT (4U) |
#define | SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) |
#define | SEMC_NANDCR1_WEL_MASK (0xF00U) |
#define | SEMC_NANDCR1_WEL_SHIFT (8U) |
#define | SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) |
#define | SEMC_NANDCR1_WEH_MASK (0xF000U) |
#define | SEMC_NANDCR1_WEH_SHIFT (12U) |
#define | SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) |
#define | SEMC_NANDCR1_REL_MASK (0xF0000U) |
#define | SEMC_NANDCR1_REL_SHIFT (16U) |
#define | SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) |
#define | SEMC_NANDCR1_REH_MASK (0xF00000U) |
#define | SEMC_NANDCR1_REH_SHIFT (20U) |
#define | SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) |
#define | SEMC_NANDCR1_TA_MASK (0xF000000U) |
#define | SEMC_NANDCR1_TA_SHIFT (24U) |
#define | SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) |
#define | SEMC_NANDCR1_CEITV_MASK (0xF0000000U) |
#define | SEMC_NANDCR1_CEITV_SHIFT (28U) |
#define | SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) |
NANDCR2 - NAND Control Register 2 | |
#define | SEMC_NANDCR2_TWHR_MASK (0x3FU) |
#define | SEMC_NANDCR2_TWHR_SHIFT (0U) |
#define | SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) |
#define | SEMC_NANDCR2_TRHW_MASK (0xFC0U) |
#define | SEMC_NANDCR2_TRHW_SHIFT (6U) |
#define | SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) |
#define | SEMC_NANDCR2_TADL_MASK (0x3F000U) |
#define | SEMC_NANDCR2_TADL_SHIFT (12U) |
#define | SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) |
#define | SEMC_NANDCR2_TRR_MASK (0xFC0000U) |
#define | SEMC_NANDCR2_TRR_SHIFT (18U) |
#define | SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) |
#define | SEMC_NANDCR2_TWB_MASK (0x3F000000U) |
#define | SEMC_NANDCR2_TWB_SHIFT (24U) |
#define | SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) |
NANDCR3 - NAND Control Register 3 | |
#define | SEMC_NANDCR3_NDOPT1_MASK (0x1U) |
#define | SEMC_NANDCR3_NDOPT1_SHIFT (0U) |
#define | SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) |
#define | SEMC_NANDCR3_NDOPT2_MASK (0x2U) |
#define | SEMC_NANDCR3_NDOPT2_SHIFT (1U) |
#define | SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) |
#define | SEMC_NANDCR3_NDOPT3_MASK (0x4U) |
#define | SEMC_NANDCR3_NDOPT3_SHIFT (2U) |
#define | SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) |
#define | SEMC_NANDCR3_CLE_MASK (0x8U) |
#define | SEMC_NANDCR3_CLE_SHIFT (3U) |
#define | SEMC_NANDCR3_CLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK) |
#define | SEMC_NANDCR3_RDS_MASK (0xF0000U) |
#define | SEMC_NANDCR3_RDS_SHIFT (16U) |
#define | SEMC_NANDCR3_RDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK) |
#define | SEMC_NANDCR3_RDH_MASK (0xF00000U) |
#define | SEMC_NANDCR3_RDH_SHIFT (20U) |
#define | SEMC_NANDCR3_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK) |
#define | SEMC_NANDCR3_WDS_MASK (0xF000000U) |
#define | SEMC_NANDCR3_WDS_SHIFT (24U) |
#define | SEMC_NANDCR3_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK) |
#define | SEMC_NANDCR3_WDH_MASK (0xF0000000U) |
#define | SEMC_NANDCR3_WDH_SHIFT (28U) |
#define | SEMC_NANDCR3_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK) |
NORCR0 - NOR Control Register 0 | |
#define | SEMC_NORCR0_PS_MASK (0x1U) |
#define | SEMC_NORCR0_PS_SHIFT (0U) |
#define | SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) |
#define | SEMC_NORCR0_SYNCEN_MASK (0x2U) |
#define | SEMC_NORCR0_SYNCEN_SHIFT (1U) |
#define | SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK) |
#define | SEMC_NORCR0_BL_MASK (0x70U) |
#define | SEMC_NORCR0_BL_SHIFT (4U) |
#define | SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) |
#define | SEMC_NORCR0_AM_MASK (0x300U) |
#define | SEMC_NORCR0_AM_SHIFT (8U) |
#define | SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) |
#define | SEMC_NORCR0_ADVP_MASK (0x400U) |
#define | SEMC_NORCR0_ADVP_SHIFT (10U) |
#define | SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) |
#define | SEMC_NORCR0_ADVH_MASK (0x800U) |
#define | SEMC_NORCR0_ADVH_SHIFT (11U) |
#define | SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK) |
#define | SEMC_NORCR0_COL_MASK (0xF000U) |
#define | SEMC_NORCR0_COL_SHIFT (12U) |
#define | SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) |
NORCR1 - NOR Control Register 1 | |
#define | SEMC_NORCR1_CES_MASK (0xFU) |
#define | SEMC_NORCR1_CES_SHIFT (0U) |
#define | SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) |
#define | SEMC_NORCR1_CEH_MASK (0xF0U) |
#define | SEMC_NORCR1_CEH_SHIFT (4U) |
#define | SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) |
#define | SEMC_NORCR1_AS_MASK (0xF00U) |
#define | SEMC_NORCR1_AS_SHIFT (8U) |
#define | SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) |
#define | SEMC_NORCR1_AH_MASK (0xF000U) |
#define | SEMC_NORCR1_AH_SHIFT (12U) |
#define | SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) |
#define | SEMC_NORCR1_WEL_MASK (0xF0000U) |
#define | SEMC_NORCR1_WEL_SHIFT (16U) |
#define | SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) |
#define | SEMC_NORCR1_WEH_MASK (0xF00000U) |
#define | SEMC_NORCR1_WEH_SHIFT (20U) |
#define | SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) |
#define | SEMC_NORCR1_REL_MASK (0xF000000U) |
#define | SEMC_NORCR1_REL_SHIFT (24U) |
#define | SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) |
#define | SEMC_NORCR1_REH_MASK (0xF0000000U) |
#define | SEMC_NORCR1_REH_SHIFT (28U) |
#define | SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) |
NORCR2 - NOR Control Register 2 | |
#define | SEMC_NORCR2_TA_MASK (0xF00U) |
#define | SEMC_NORCR2_TA_SHIFT (8U) |
#define | SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) |
#define | SEMC_NORCR2_AWDH_MASK (0xF000U) |
#define | SEMC_NORCR2_AWDH_SHIFT (12U) |
#define | SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) |
#define | SEMC_NORCR2_LC_MASK (0xF0000U) |
#define | SEMC_NORCR2_LC_SHIFT (16U) |
#define | SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK) |
#define | SEMC_NORCR2_RD_MASK (0xF00000U) |
#define | SEMC_NORCR2_RD_SHIFT (20U) |
#define | SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK) |
#define | SEMC_NORCR2_CEITV_MASK (0xF000000U) |
#define | SEMC_NORCR2_CEITV_SHIFT (24U) |
#define | SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) |
#define | SEMC_NORCR2_RDH_MASK (0xF0000000U) |
#define | SEMC_NORCR2_RDH_SHIFT (28U) |
#define | SEMC_NORCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK) |
NORCR3 - NOR Control Register 3 | |
#define | SEMC_NORCR3_ASSR_MASK (0xFU) |
#define | SEMC_NORCR3_ASSR_SHIFT (0U) |
#define | SEMC_NORCR3_ASSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK) |
#define | SEMC_NORCR3_AHSR_MASK (0xF0U) |
#define | SEMC_NORCR3_AHSR_SHIFT (4U) |
#define | SEMC_NORCR3_AHSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK) |
SRAMCR0 - SRAM Control Register 0 | |
#define | SEMC_SRAMCR0_PS_MASK (0x1U) |
#define | SEMC_SRAMCR0_PS_SHIFT (0U) |
#define | SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) |
#define | SEMC_SRAMCR0_SYNCEN_MASK (0x2U) |
#define | SEMC_SRAMCR0_SYNCEN_SHIFT (1U) |
#define | SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK) |
#define | SEMC_SRAMCR0_WAITEN_MASK (0x4U) |
#define | SEMC_SRAMCR0_WAITEN_SHIFT (2U) |
#define | SEMC_SRAMCR0_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITEN_SHIFT)) & SEMC_SRAMCR0_WAITEN_MASK) |
#define | SEMC_SRAMCR0_WAITSP_MASK (0x8U) |
#define | SEMC_SRAMCR0_WAITSP_SHIFT (3U) |
#define | SEMC_SRAMCR0_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITSP_SHIFT)) & SEMC_SRAMCR0_WAITSP_MASK) |
#define | SEMC_SRAMCR0_BL_MASK (0x70U) |
#define | SEMC_SRAMCR0_BL_SHIFT (4U) |
#define | SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) |
#define | SEMC_SRAMCR0_AM_MASK (0x300U) |
#define | SEMC_SRAMCR0_AM_SHIFT (8U) |
#define | SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) |
#define | SEMC_SRAMCR0_ADVP_MASK (0x400U) |
#define | SEMC_SRAMCR0_ADVP_SHIFT (10U) |
#define | SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) |
#define | SEMC_SRAMCR0_ADVH_MASK (0x800U) |
#define | SEMC_SRAMCR0_ADVH_SHIFT (11U) |
#define | SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK) |
#define | SEMC_SRAMCR0_COL_MASK (0xF000U) |
#define | SEMC_SRAMCR0_COL_SHIFT (12U) |
#define | SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) |
SRAMCR1 - SRAM Control Register 1 | |
#define | SEMC_SRAMCR1_CES_MASK (0xFU) |
#define | SEMC_SRAMCR1_CES_SHIFT (0U) |
#define | SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) |
#define | SEMC_SRAMCR1_CEH_MASK (0xF0U) |
#define | SEMC_SRAMCR1_CEH_SHIFT (4U) |
#define | SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) |
#define | SEMC_SRAMCR1_AS_MASK (0xF00U) |
#define | SEMC_SRAMCR1_AS_SHIFT (8U) |
#define | SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) |
#define | SEMC_SRAMCR1_AH_MASK (0xF000U) |
#define | SEMC_SRAMCR1_AH_SHIFT (12U) |
#define | SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) |
#define | SEMC_SRAMCR1_WEL_MASK (0xF0000U) |
#define | SEMC_SRAMCR1_WEL_SHIFT (16U) |
#define | SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) |
#define | SEMC_SRAMCR1_WEH_MASK (0xF00000U) |
#define | SEMC_SRAMCR1_WEH_SHIFT (20U) |
#define | SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) |
#define | SEMC_SRAMCR1_REL_MASK (0xF000000U) |
#define | SEMC_SRAMCR1_REL_SHIFT (24U) |
#define | SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) |
#define | SEMC_SRAMCR1_REH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR1_REH_SHIFT (28U) |
#define | SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) |
SRAMCR2 - SRAM Control Register 2 | |
#define | SEMC_SRAMCR2_WDS_MASK (0xFU) |
#define | SEMC_SRAMCR2_WDS_SHIFT (0U) |
#define | SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) |
#define | SEMC_SRAMCR2_WDH_MASK (0xF0U) |
#define | SEMC_SRAMCR2_WDH_SHIFT (4U) |
#define | SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK) |
#define | SEMC_SRAMCR2_TA_MASK (0xF00U) |
#define | SEMC_SRAMCR2_TA_SHIFT (8U) |
#define | SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) |
#define | SEMC_SRAMCR2_AWDH_MASK (0xF000U) |
#define | SEMC_SRAMCR2_AWDH_SHIFT (12U) |
#define | SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) |
#define | SEMC_SRAMCR2_LC_MASK (0xF0000U) |
#define | SEMC_SRAMCR2_LC_SHIFT (16U) |
#define | SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK) |
#define | SEMC_SRAMCR2_RD_MASK (0xF00000U) |
#define | SEMC_SRAMCR2_RD_SHIFT (20U) |
#define | SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK) |
#define | SEMC_SRAMCR2_CEITV_MASK (0xF000000U) |
#define | SEMC_SRAMCR2_CEITV_SHIFT (24U) |
#define | SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) |
#define | SEMC_SRAMCR2_RDH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR2_RDH_SHIFT (28U) |
#define | SEMC_SRAMCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK) |
DBICR0 - DBI-B Control Register 0 | |
#define | SEMC_DBICR0_PS_MASK (0x1U) |
#define | SEMC_DBICR0_PS_SHIFT (0U) |
#define | SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) |
#define | SEMC_DBICR0_BL_MASK (0x70U) |
#define | SEMC_DBICR0_BL_SHIFT (4U) |
#define | SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) |
#define | SEMC_DBICR0_COL_MASK (0xF000U) |
#define | SEMC_DBICR0_COL_SHIFT (12U) |
#define | SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) |
DBICR1 - DBI-B Control Register 1 | |
#define | SEMC_DBICR1_CES_MASK (0xFU) |
#define | SEMC_DBICR1_CES_SHIFT (0U) |
#define | SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) |
#define | SEMC_DBICR1_CEH_MASK (0xF0U) |
#define | SEMC_DBICR1_CEH_SHIFT (4U) |
#define | SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) |
#define | SEMC_DBICR1_WEL_MASK (0xF00U) |
#define | SEMC_DBICR1_WEL_SHIFT (8U) |
#define | SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) |
#define | SEMC_DBICR1_WEH_MASK (0xF000U) |
#define | SEMC_DBICR1_WEH_SHIFT (12U) |
#define | SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) |
#define | SEMC_DBICR1_REL_MASK (0x7F0000U) |
#define | SEMC_DBICR1_REL_SHIFT (16U) |
#define | SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) |
#define | SEMC_DBICR1_REH_MASK (0x7F000000U) |
#define | SEMC_DBICR1_REH_SHIFT (24U) |
#define | SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) |
DBICR2 - DBI-B Control Register 2 | |
#define | SEMC_DBICR2_CEITV_MASK (0xFU) |
#define | SEMC_DBICR2_CEITV_SHIFT (0U) |
#define | SEMC_DBICR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR2_CEITV_SHIFT)) & SEMC_DBICR2_CEITV_MASK) |
IPCR0 - IP Command Control Register 0 | |
#define | SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) |
#define | SEMC_IPCR0_SA_SHIFT (0U) |
#define | SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) |
IPCR1 - IP Command Control Register 1 | |
#define | SEMC_IPCR1_DATSZ_MASK (0x7U) |
#define | SEMC_IPCR1_DATSZ_SHIFT (0U) |
#define | SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) |
#define | SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U) |
#define | SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U) |
#define | SEMC_IPCR1_NAND_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK) |
IPCR2 - IP Command Control Register 2 | |
#define | SEMC_IPCR2_BM0_MASK (0x1U) |
#define | SEMC_IPCR2_BM0_SHIFT (0U) |
#define | SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) |
#define | SEMC_IPCR2_BM1_MASK (0x2U) |
#define | SEMC_IPCR2_BM1_SHIFT (1U) |
#define | SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) |
#define | SEMC_IPCR2_BM2_MASK (0x4U) |
#define | SEMC_IPCR2_BM2_SHIFT (2U) |
#define | SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) |
#define | SEMC_IPCR2_BM3_MASK (0x8U) |
#define | SEMC_IPCR2_BM3_SHIFT (3U) |
#define | SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) |
IPTXDAT - TX DATA Register | |
#define | SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU) |
#define | SEMC_IPTXDAT_DAT_SHIFT (0U) |
#define | SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) |
IPRXDAT - RX DATA Register | |
#define | SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU) |
#define | SEMC_IPRXDAT_DAT_SHIFT (0U) |
#define | SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) |
STS12 - Status Register 12 | |
#define | SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) |
#define | SEMC_STS12_NDADDR_SHIFT (0U) |
#define | SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) |
STS13 - Status Register 13 | |
#define | SEMC_STS13_SLVLOCK_MASK (0x1U) |
#define | SEMC_STS13_SLVLOCK_SHIFT (0U) |
#define | SEMC_STS13_SLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK) |
#define | SEMC_STS13_REFLOCK_MASK (0x2U) |
#define | SEMC_STS13_REFLOCK_SHIFT (1U) |
#define | SEMC_STS13_REFLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK) |
#define | SEMC_STS13_SLVSEL_MASK (0xFCU) |
#define | SEMC_STS13_SLVSEL_SHIFT (2U) |
#define | SEMC_STS13_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK) |
#define | SEMC_STS13_REFSEL_MASK (0x3F00U) |
#define | SEMC_STS13_REFSEL_SHIFT (8U) |
#define | SEMC_STS13_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK) |
BR9 - Base Register 9 | |
#define | SEMC_BR9_VLD_MASK (0x1U) |
#define | SEMC_BR9_VLD_SHIFT (0U) |
#define | SEMC_BR9_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_VLD_SHIFT)) & SEMC_BR9_VLD_MASK) |
#define | SEMC_BR9_MS_MASK (0x3EU) |
#define | SEMC_BR9_MS_SHIFT (1U) |
#define | SEMC_BR9_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_MS_SHIFT)) & SEMC_BR9_MS_MASK) |
#define | SEMC_BR9_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR9_BA_SHIFT (12U) |
#define | SEMC_BR9_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_BA_SHIFT)) & SEMC_BR9_BA_MASK) |
BR10 - Base Register 10 | |
#define | SEMC_BR10_VLD_MASK (0x1U) |
#define | SEMC_BR10_VLD_SHIFT (0U) |
#define | SEMC_BR10_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_VLD_SHIFT)) & SEMC_BR10_VLD_MASK) |
#define | SEMC_BR10_MS_MASK (0x3EU) |
#define | SEMC_BR10_MS_SHIFT (1U) |
#define | SEMC_BR10_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_MS_SHIFT)) & SEMC_BR10_MS_MASK) |
#define | SEMC_BR10_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR10_BA_SHIFT (12U) |
#define | SEMC_BR10_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_BA_SHIFT)) & SEMC_BR10_BA_MASK) |
BR11 - Base Register 11 | |
#define | SEMC_BR11_VLD_MASK (0x1U) |
#define | SEMC_BR11_VLD_SHIFT (0U) |
#define | SEMC_BR11_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_VLD_SHIFT)) & SEMC_BR11_VLD_MASK) |
#define | SEMC_BR11_MS_MASK (0x3EU) |
#define | SEMC_BR11_MS_SHIFT (1U) |
#define | SEMC_BR11_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_MS_SHIFT)) & SEMC_BR11_MS_MASK) |
#define | SEMC_BR11_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR11_BA_SHIFT (12U) |
#define | SEMC_BR11_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_BA_SHIFT)) & SEMC_BR11_BA_MASK) |
SRAMCR4 - SRAM Control Register 4 | |
#define | SEMC_SRAMCR4_PS_MASK (0x1U) |
#define | SEMC_SRAMCR4_PS_SHIFT (0U) |
#define | SEMC_SRAMCR4_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_PS_SHIFT)) & SEMC_SRAMCR4_PS_MASK) |
#define | SEMC_SRAMCR4_SYNCEN_MASK (0x2U) |
#define | SEMC_SRAMCR4_SYNCEN_SHIFT (1U) |
#define | SEMC_SRAMCR4_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK) |
#define | SEMC_SRAMCR4_WAITEN_MASK (0x4U) |
#define | SEMC_SRAMCR4_WAITEN_SHIFT (2U) |
#define | SEMC_SRAMCR4_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITEN_SHIFT)) & SEMC_SRAMCR4_WAITEN_MASK) |
#define | SEMC_SRAMCR4_WAITSP_MASK (0x8U) |
#define | SEMC_SRAMCR4_WAITSP_SHIFT (3U) |
#define | SEMC_SRAMCR4_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITSP_SHIFT)) & SEMC_SRAMCR4_WAITSP_MASK) |
#define | SEMC_SRAMCR4_BL_MASK (0x70U) |
#define | SEMC_SRAMCR4_BL_SHIFT (4U) |
#define | SEMC_SRAMCR4_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK) |
#define | SEMC_SRAMCR4_AM_MASK (0x300U) |
#define | SEMC_SRAMCR4_AM_SHIFT (8U) |
#define | SEMC_SRAMCR4_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_AM_SHIFT)) & SEMC_SRAMCR4_AM_MASK) |
#define | SEMC_SRAMCR4_ADVP_MASK (0x400U) |
#define | SEMC_SRAMCR4_ADVP_SHIFT (10U) |
#define | SEMC_SRAMCR4_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVP_SHIFT)) & SEMC_SRAMCR4_ADVP_MASK) |
#define | SEMC_SRAMCR4_ADVH_MASK (0x800U) |
#define | SEMC_SRAMCR4_ADVH_SHIFT (11U) |
#define | SEMC_SRAMCR4_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVH_SHIFT)) & SEMC_SRAMCR4_ADVH_MASK) |
#define | SEMC_SRAMCR4_COL_MASK (0xF000U) |
#define | SEMC_SRAMCR4_COL_SHIFT (12U) |
#define | SEMC_SRAMCR4_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_COL_SHIFT)) & SEMC_SRAMCR4_COL_MASK) |
SRAMCR5 - SRAM Control Register 5 | |
#define | SEMC_SRAMCR5_CES_MASK (0xFU) |
#define | SEMC_SRAMCR5_CES_SHIFT (0U) |
#define | SEMC_SRAMCR5_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CES_SHIFT)) & SEMC_SRAMCR5_CES_MASK) |
#define | SEMC_SRAMCR5_CEH_MASK (0xF0U) |
#define | SEMC_SRAMCR5_CEH_SHIFT (4U) |
#define | SEMC_SRAMCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_SRAMCR5_CEH_MASK) |
#define | SEMC_SRAMCR5_AS_MASK (0xF00U) |
#define | SEMC_SRAMCR5_AS_SHIFT (8U) |
#define | SEMC_SRAMCR5_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AS_SHIFT)) & SEMC_SRAMCR5_AS_MASK) |
#define | SEMC_SRAMCR5_AH_MASK (0xF000U) |
#define | SEMC_SRAMCR5_AH_SHIFT (12U) |
#define | SEMC_SRAMCR5_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AH_SHIFT)) & SEMC_SRAMCR5_AH_MASK) |
#define | SEMC_SRAMCR5_WEL_MASK (0xF0000U) |
#define | SEMC_SRAMCR5_WEL_SHIFT (16U) |
#define | SEMC_SRAMCR5_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEL_SHIFT)) & SEMC_SRAMCR5_WEL_MASK) |
#define | SEMC_SRAMCR5_WEH_MASK (0xF00000U) |
#define | SEMC_SRAMCR5_WEH_SHIFT (20U) |
#define | SEMC_SRAMCR5_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEH_SHIFT)) & SEMC_SRAMCR5_WEH_MASK) |
#define | SEMC_SRAMCR5_REL_MASK (0xF000000U) |
#define | SEMC_SRAMCR5_REL_SHIFT (24U) |
#define | SEMC_SRAMCR5_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REL_SHIFT)) & SEMC_SRAMCR5_REL_MASK) |
#define | SEMC_SRAMCR5_REH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR5_REH_SHIFT (28U) |
#define | SEMC_SRAMCR5_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REH_SHIFT)) & SEMC_SRAMCR5_REH_MASK) |
SRAMCR6 - SRAM Control Register 6 | |
#define | SEMC_SRAMCR6_WDS_MASK (0xFU) |
#define | SEMC_SRAMCR6_WDS_SHIFT (0U) |
#define | SEMC_SRAMCR6_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDS_SHIFT)) & SEMC_SRAMCR6_WDS_MASK) |
#define | SEMC_SRAMCR6_WDH_MASK (0xF0U) |
#define | SEMC_SRAMCR6_WDH_SHIFT (4U) |
#define | SEMC_SRAMCR6_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDH_SHIFT)) & SEMC_SRAMCR6_WDH_MASK) |
#define | SEMC_SRAMCR6_TA_MASK (0xF00U) |
#define | SEMC_SRAMCR6_TA_SHIFT (8U) |
#define | SEMC_SRAMCR6_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_TA_SHIFT)) & SEMC_SRAMCR6_TA_MASK) |
#define | SEMC_SRAMCR6_AWDH_MASK (0xF000U) |
#define | SEMC_SRAMCR6_AWDH_SHIFT (12U) |
#define | SEMC_SRAMCR6_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_AWDH_SHIFT)) & SEMC_SRAMCR6_AWDH_MASK) |
#define | SEMC_SRAMCR6_LC_MASK (0xF0000U) |
#define | SEMC_SRAMCR6_LC_SHIFT (16U) |
#define | SEMC_SRAMCR6_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_LC_SHIFT)) & SEMC_SRAMCR6_LC_MASK) |
#define | SEMC_SRAMCR6_RD_MASK (0xF00000U) |
#define | SEMC_SRAMCR6_RD_SHIFT (20U) |
#define | SEMC_SRAMCR6_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RD_SHIFT)) & SEMC_SRAMCR6_RD_MASK) |
#define | SEMC_SRAMCR6_CEITV_MASK (0xF000000U) |
#define | SEMC_SRAMCR6_CEITV_SHIFT (24U) |
#define | SEMC_SRAMCR6_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_CEITV_SHIFT)) & SEMC_SRAMCR6_CEITV_MASK) |
#define | SEMC_SRAMCR6_RDH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR6_RDH_SHIFT (28U) |
#define | SEMC_SRAMCR6_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RDH_SHIFT)) & SEMC_SRAMCR6_RDH_MASK) |
DCCR - Delay Chain Control Register | |
#define | SEMC_DCCR_SDRAMEN_MASK (0x1U) |
#define | SEMC_DCCR_SDRAMEN_SHIFT (0U) |
#define | SEMC_DCCR_SDRAMEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMEN_SHIFT)) & SEMC_DCCR_SDRAMEN_MASK) |
#define | SEMC_DCCR_SDRAMVAL_MASK (0x3EU) |
#define | SEMC_DCCR_SDRAMVAL_SHIFT (1U) |
#define | SEMC_DCCR_SDRAMVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMVAL_SHIFT)) & SEMC_DCCR_SDRAMVAL_MASK) |
#define | SEMC_DCCR_NOREN_MASK (0x100U) |
#define | SEMC_DCCR_NOREN_SHIFT (8U) |
#define | SEMC_DCCR_NOREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NOREN_SHIFT)) & SEMC_DCCR_NOREN_MASK) |
#define | SEMC_DCCR_NORVAL_MASK (0x3E00U) |
#define | SEMC_DCCR_NORVAL_SHIFT (9U) |
#define | SEMC_DCCR_NORVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NORVAL_SHIFT)) & SEMC_DCCR_NORVAL_MASK) |
#define | SEMC_DCCR_SRAM0EN_MASK (0x10000U) |
#define | SEMC_DCCR_SRAM0EN_SHIFT (16U) |
#define | SEMC_DCCR_SRAM0EN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0EN_SHIFT)) & SEMC_DCCR_SRAM0EN_MASK) |
#define | SEMC_DCCR_SRAM0VAL_MASK (0x3E0000U) |
#define | SEMC_DCCR_SRAM0VAL_SHIFT (17U) |
#define | SEMC_DCCR_SRAM0VAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0VAL_SHIFT)) & SEMC_DCCR_SRAM0VAL_MASK) |
#define | SEMC_DCCR_SRAMXEN_MASK (0x1000000U) |
#define | SEMC_DCCR_SRAMXEN_SHIFT (24U) |
#define | SEMC_DCCR_SRAMXEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXEN_SHIFT)) & SEMC_DCCR_SRAMXEN_MASK) |
#define | SEMC_DCCR_SRAMXVAL_MASK (0x3E000000U) |
#define | SEMC_DCCR_SRAMXVAL_SHIFT (25U) |
#define | SEMC_DCCR_SRAMXVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXVAL_SHIFT)) & SEMC_DCCR_SRAMXVAL_MASK) |
HPLR - SNVS_HP Lock Register | |
#define | SNVS_HPLR_ZMK_WSL_MASK (0x1U) |
#define | SNVS_HPLR_ZMK_WSL_SHIFT (0U) |
#define | SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) |
#define | SNVS_HPLR_ZMK_RSL_MASK (0x2U) |
#define | SNVS_HPLR_ZMK_RSL_SHIFT (1U) |
#define | SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) |
#define | SNVS_HPLR_SRTC_SL_MASK (0x4U) |
#define | SNVS_HPLR_SRTC_SL_SHIFT (2U) |
#define | SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) |
#define | SNVS_HPLR_LPCALB_SL_MASK (0x8U) |
#define | SNVS_HPLR_LPCALB_SL_SHIFT (3U) |
#define | SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) |
#define | SNVS_HPLR_MC_SL_MASK (0x10U) |
#define | SNVS_HPLR_MC_SL_SHIFT (4U) |
#define | SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) |
#define | SNVS_HPLR_GPR_SL_MASK (0x20U) |
#define | SNVS_HPLR_GPR_SL_SHIFT (5U) |
#define | SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) |
#define | SNVS_HPLR_LPSVCR_SL_MASK (0x40U) |
#define | SNVS_HPLR_LPSVCR_SL_SHIFT (6U) |
#define | SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) |
#define | SNVS_HPLR_LPTGFCR_SL_MASK (0x80U) |
#define | SNVS_HPLR_LPTGFCR_SL_SHIFT (7U) |
#define | SNVS_HPLR_LPTGFCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK) |
#define | SNVS_HPLR_LPSECR_SL_MASK (0x100U) |
#define | SNVS_HPLR_LPSECR_SL_SHIFT (8U) |
#define | SNVS_HPLR_LPSECR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK) |
#define | SNVS_HPLR_MKS_SL_MASK (0x200U) |
#define | SNVS_HPLR_MKS_SL_SHIFT (9U) |
#define | SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) |
#define | SNVS_HPLR_HPSVCR_L_MASK (0x10000U) |
#define | SNVS_HPLR_HPSVCR_L_SHIFT (16U) |
#define | SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) |
#define | SNVS_HPLR_HPSICR_L_MASK (0x20000U) |
#define | SNVS_HPLR_HPSICR_L_SHIFT (17U) |
#define | SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) |
#define | SNVS_HPLR_HAC_L_MASK (0x40000U) |
#define | SNVS_HPLR_HAC_L_SHIFT (18U) |
#define | SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) |
#define | SNVS_HPLR_AT1_SL_MASK (0x1000000U) |
#define | SNVS_HPLR_AT1_SL_SHIFT (24U) |
#define | SNVS_HPLR_AT1_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT1_SL_SHIFT)) & SNVS_HPLR_AT1_SL_MASK) |
#define | SNVS_HPLR_AT2_SL_MASK (0x2000000U) |
#define | SNVS_HPLR_AT2_SL_SHIFT (25U) |
#define | SNVS_HPLR_AT2_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT2_SL_SHIFT)) & SNVS_HPLR_AT2_SL_MASK) |
#define | SNVS_HPLR_AT3_SL_MASK (0x4000000U) |
#define | SNVS_HPLR_AT3_SL_SHIFT (26U) |
#define | SNVS_HPLR_AT3_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT3_SL_SHIFT)) & SNVS_HPLR_AT3_SL_MASK) |
#define | SNVS_HPLR_AT4_SL_MASK (0x8000000U) |
#define | SNVS_HPLR_AT4_SL_SHIFT (27U) |
#define | SNVS_HPLR_AT4_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT4_SL_SHIFT)) & SNVS_HPLR_AT4_SL_MASK) |
#define | SNVS_HPLR_AT5_SL_MASK (0x10000000U) |
#define | SNVS_HPLR_AT5_SL_SHIFT (28U) |
#define | SNVS_HPLR_AT5_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT5_SL_SHIFT)) & SNVS_HPLR_AT5_SL_MASK) |
HPCOMR - SNVS_HP Command Register | |
#define | SNVS_HPCOMR_SSM_ST_MASK (0x1U) |
#define | SNVS_HPCOMR_SSM_ST_SHIFT (0U) |
#define | SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) |
#define | SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) |
#define | SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) |
#define | SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) |
#define | SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) |
#define | SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) |
#define | SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) |
#define | SNVS_HPCOMR_LP_SWR_MASK (0x10U) |
#define | SNVS_HPCOMR_LP_SWR_SHIFT (4U) |
#define | SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) |
#define | SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) |
#define | SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) |
#define | SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) |
#define | SNVS_HPCOMR_SW_SV_MASK (0x100U) |
#define | SNVS_HPCOMR_SW_SV_SHIFT (8U) |
#define | SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) |
#define | SNVS_HPCOMR_SW_FSV_MASK (0x200U) |
#define | SNVS_HPCOMR_SW_FSV_SHIFT (9U) |
#define | SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) |
#define | SNVS_HPCOMR_SW_LPSV_MASK (0x400U) |
#define | SNVS_HPCOMR_SW_LPSV_SHIFT (10U) |
#define | SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) |
#define | SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) |
#define | SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) |
#define | SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) |
#define | SNVS_HPCOMR_MKS_EN_MASK (0x2000U) |
#define | SNVS_HPCOMR_MKS_EN_SHIFT (13U) |
#define | SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) |
#define | SNVS_HPCOMR_HAC_EN_MASK (0x10000U) |
#define | SNVS_HPCOMR_HAC_EN_SHIFT (16U) |
#define | SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) |
#define | SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) |
#define | SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) |
#define | SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) |
#define | SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) |
#define | SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) |
#define | SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) |
#define | SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) |
#define | SNVS_HPCOMR_HAC_STOP_SHIFT (19U) |
#define | SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) |
#define | SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) |
#define | SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) |
#define | SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) |
HPCR - SNVS_HP Control Register | |
#define | SNVS_HPCR_RTC_EN_MASK (0x1U) |
#define | SNVS_HPCR_RTC_EN_SHIFT (0U) |
#define | SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) |
#define | SNVS_HPCR_HPTA_EN_MASK (0x2U) |
#define | SNVS_HPCR_HPTA_EN_SHIFT (1U) |
#define | SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) |
#define | SNVS_HPCR_DIS_PI_MASK (0x4U) |
#define | SNVS_HPCR_DIS_PI_SHIFT (2U) |
#define | SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) |
#define | SNVS_HPCR_PI_EN_MASK (0x8U) |
#define | SNVS_HPCR_PI_EN_SHIFT (3U) |
#define | SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) |
#define | SNVS_HPCR_PI_FREQ_MASK (0xF0U) |
#define | SNVS_HPCR_PI_FREQ_SHIFT (4U) |
#define | SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) |
#define | SNVS_HPCR_HPCALB_EN_MASK (0x100U) |
#define | SNVS_HPCR_HPCALB_EN_SHIFT (8U) |
#define | SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) |
#define | SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) |
#define | SNVS_HPCR_HPCALB_VAL_SHIFT (10U) |
#define | SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) |
#define | SNVS_HPCR_HP_TS_MASK (0x10000U) |
#define | SNVS_HPCR_HP_TS_SHIFT (16U) |
#define | SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) |
#define | SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) |
#define | SNVS_HPCR_BTN_CONFIG_SHIFT (24U) |
#define | SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) |
#define | SNVS_HPCR_BTN_MASK_MASK (0x8000000U) |
#define | SNVS_HPCR_BTN_MASK_SHIFT (27U) |
#define | SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) |
HPSICR - SNVS_HP Security Interrupt Control Register | |
#define | SNVS_HPSICR_CAAM_EN_MASK (0x1U) |
#define | SNVS_HPSICR_CAAM_EN_SHIFT (0U) |
#define | SNVS_HPSICR_CAAM_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_CAAM_EN_SHIFT)) & SNVS_HPSICR_CAAM_EN_MASK) |
#define | SNVS_HPSICR_JTAGC_EN_MASK (0x2U) |
#define | SNVS_HPSICR_JTAGC_EN_SHIFT (1U) |
#define | SNVS_HPSICR_JTAGC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_JTAGC_EN_SHIFT)) & SNVS_HPSICR_JTAGC_EN_MASK) |
#define | SNVS_HPSICR_WDOG2_EN_MASK (0x4U) |
#define | SNVS_HPSICR_WDOG2_EN_SHIFT (2U) |
#define | SNVS_HPSICR_WDOG2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_WDOG2_EN_SHIFT)) & SNVS_HPSICR_WDOG2_EN_MASK) |
#define | SNVS_HPSICR_SRC_EN_MASK (0x10U) |
#define | SNVS_HPSICR_SRC_EN_SHIFT (4U) |
#define | SNVS_HPSICR_SRC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SRC_EN_SHIFT)) & SNVS_HPSICR_SRC_EN_MASK) |
#define | SNVS_HPSICR_OCOTP_EN_MASK (0x20U) |
#define | SNVS_HPSICR_OCOTP_EN_SHIFT (5U) |
#define | SNVS_HPSICR_OCOTP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_OCOTP_EN_SHIFT)) & SNVS_HPSICR_OCOTP_EN_MASK) |
#define | SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) |
#define | SNVS_HPSICR_LPSVI_EN_SHIFT (31U) |
#define | SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) |
HPSVCR - SNVS_HP Security Violation Control Register | |
#define | SNVS_HPSVCR_CAAM_CFG_MASK (0x1U) |
#define | SNVS_HPSVCR_CAAM_CFG_SHIFT (0U) |
#define | SNVS_HPSVCR_CAAM_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_CAAM_CFG_SHIFT)) & SNVS_HPSVCR_CAAM_CFG_MASK) |
#define | SNVS_HPSVCR_JTAGC_CFG_MASK (0x2U) |
#define | SNVS_HPSVCR_JTAGC_CFG_SHIFT (1U) |
#define | SNVS_HPSVCR_JTAGC_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_JTAGC_CFG_SHIFT)) & SNVS_HPSVCR_JTAGC_CFG_MASK) |
#define | SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) |
#define | SNVS_HPSVCR_WDOG2_CFG_SHIFT (2U) |
#define | SNVS_HPSVCR_WDOG2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK) |
#define | SNVS_HPSVCR_SRC_CFG_MASK (0x10U) |
#define | SNVS_HPSVCR_SRC_CFG_SHIFT (4U) |
#define | SNVS_HPSVCR_SRC_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SRC_CFG_SHIFT)) & SNVS_HPSVCR_SRC_CFG_MASK) |
#define | SNVS_HPSVCR_OCOTP_CFG_MASK (0x60U) |
#define | SNVS_HPSVCR_OCOTP_CFG_SHIFT (5U) |
#define | SNVS_HPSVCR_OCOTP_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_OCOTP_CFG_SHIFT)) & SNVS_HPSVCR_OCOTP_CFG_MASK) |
#define | SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) |
#define | SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) |
#define | SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) |
HPSR - SNVS_HP Status Register | |
#define | SNVS_HPSR_HPTA_MASK (0x1U) |
#define | SNVS_HPSR_HPTA_SHIFT (0U) |
#define | SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) |
#define | SNVS_HPSR_PI_MASK (0x2U) |
#define | SNVS_HPSR_PI_SHIFT (1U) |
#define | SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) |
#define | SNVS_HPSR_LPDIS_MASK (0x10U) |
#define | SNVS_HPSR_LPDIS_SHIFT (4U) |
#define | SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) |
#define | SNVS_HPSR_BTN_MASK (0x40U) |
#define | SNVS_HPSR_BTN_SHIFT (6U) |
#define | SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) |
#define | SNVS_HPSR_BI_MASK (0x80U) |
#define | SNVS_HPSR_BI_SHIFT (7U) |
#define | SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) |
#define | SNVS_HPSR_SSM_STATE_MASK (0xF00U) |
#define | SNVS_HPSR_SSM_STATE_SHIFT (8U) |
#define | SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) |
#define | SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U) |
#define | SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U) |
#define | SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK) |
#define | SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U) |
#define | SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U) |
#define | SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK) |
#define | SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) |
#define | SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) |
#define | SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) |
#define | SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) |
#define | SNVS_HPSR_ZMK_ZERO_SHIFT (31U) |
#define | SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) |
HPSVSR - SNVS_HP Security Violation Status Register | |
#define | SNVS_HPSVSR_CAAM_MASK (0x1U) |
#define | SNVS_HPSVSR_CAAM_SHIFT (0U) |
#define | SNVS_HPSVSR_CAAM(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_CAAM_SHIFT)) & SNVS_HPSVSR_CAAM_MASK) |
#define | SNVS_HPSVSR_JTAGC_MASK (0x2U) |
#define | SNVS_HPSVSR_JTAGC_SHIFT (1U) |
#define | SNVS_HPSVSR_JTAGC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_JTAGC_SHIFT)) & SNVS_HPSVSR_JTAGC_MASK) |
#define | SNVS_HPSVSR_WDOG2_MASK (0x4U) |
#define | SNVS_HPSVSR_WDOG2_SHIFT (2U) |
#define | SNVS_HPSVSR_WDOG2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_WDOG2_SHIFT)) & SNVS_HPSVSR_WDOG2_MASK) |
#define | SNVS_HPSVSR_SRC_MASK (0x10U) |
#define | SNVS_HPSVSR_SRC_SHIFT (4U) |
#define | SNVS_HPSVSR_SRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SRC_SHIFT)) & SNVS_HPSVSR_SRC_MASK) |
#define | SNVS_HPSVSR_OCOTP_MASK (0x20U) |
#define | SNVS_HPSVSR_OCOTP_SHIFT (5U) |
#define | SNVS_HPSVSR_OCOTP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_OCOTP_SHIFT)) & SNVS_HPSVSR_OCOTP_MASK) |
#define | SNVS_HPSVSR_SW_SV_MASK (0x2000U) |
#define | SNVS_HPSVSR_SW_SV_SHIFT (13U) |
#define | SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) |
#define | SNVS_HPSVSR_SW_FSV_MASK (0x4000U) |
#define | SNVS_HPSVSR_SW_FSV_SHIFT (14U) |
#define | SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) |
#define | SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) |
#define | SNVS_HPSVSR_SW_LPSV_SHIFT (15U) |
#define | SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) |
#define | SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) |
#define | SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) |
#define | SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) |
#define | SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) |
#define | SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) |
#define | SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) |
#define | SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) |
#define | SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) |
#define | SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) |
HPHACIVR - SNVS_HP High Assurance Counter IV Register | |
#define | SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) |
#define | SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) |
#define | SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) |
HPHACR - SNVS_HP High Assurance Counter Register | |
#define | SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) |
#define | SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) |
#define | SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) |
HPRTCMR - SNVS_HP Real Time Counter MSB Register | |
#define | SNVS_HPRTCMR_RTC_MASK (0x7FFFU) |
#define | SNVS_HPRTCMR_RTC_SHIFT (0U) |
#define | SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) |
HPRTCLR - SNVS_HP Real Time Counter LSB Register | |
#define | SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) |
#define | SNVS_HPRTCLR_RTC_SHIFT (0U) |
#define | SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) |
HPTAMR - SNVS_HP Time Alarm MSB Register | |
#define | SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) |
#define | SNVS_HPTAMR_HPTA_MS_SHIFT (0U) |
#define | SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) |
HPTALR - SNVS_HP Time Alarm LSB Register | |
#define | SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) |
#define | SNVS_HPTALR_HPTA_LS_SHIFT (0U) |
#define | SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) |
LPLR - SNVS_LP Lock Register | |
#define | SNVS_LPLR_ZMK_WHL_MASK (0x1U) |
#define | SNVS_LPLR_ZMK_WHL_SHIFT (0U) |
#define | SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) |
#define | SNVS_LPLR_ZMK_RHL_MASK (0x2U) |
#define | SNVS_LPLR_ZMK_RHL_SHIFT (1U) |
#define | SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) |
#define | SNVS_LPLR_SRTC_HL_MASK (0x4U) |
#define | SNVS_LPLR_SRTC_HL_SHIFT (2U) |
#define | SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) |
#define | SNVS_LPLR_LPCALB_HL_MASK (0x8U) |
#define | SNVS_LPLR_LPCALB_HL_SHIFT (3U) |
#define | SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) |
#define | SNVS_LPLR_MC_HL_MASK (0x10U) |
#define | SNVS_LPLR_MC_HL_SHIFT (4U) |
#define | SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) |
#define | SNVS_LPLR_GPR_HL_MASK (0x20U) |
#define | SNVS_LPLR_GPR_HL_SHIFT (5U) |
#define | SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) |
#define | SNVS_LPLR_LPSVCR_HL_MASK (0x40U) |
#define | SNVS_LPLR_LPSVCR_HL_SHIFT (6U) |
#define | SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) |
#define | SNVS_LPLR_LPTGFCR_HL_MASK (0x80U) |
#define | SNVS_LPLR_LPTGFCR_HL_SHIFT (7U) |
#define | SNVS_LPLR_LPTGFCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK) |
#define | SNVS_LPLR_LPSECR_HL_MASK (0x100U) |
#define | SNVS_LPLR_LPSECR_HL_SHIFT (8U) |
#define | SNVS_LPLR_LPSECR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK) |
#define | SNVS_LPLR_MKS_HL_MASK (0x200U) |
#define | SNVS_LPLR_MKS_HL_SHIFT (9U) |
#define | SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) |
#define | SNVS_LPLR_AT1_HL_MASK (0x1000000U) |
#define | SNVS_LPLR_AT1_HL_SHIFT (24U) |
#define | SNVS_LPLR_AT1_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT1_HL_SHIFT)) & SNVS_LPLR_AT1_HL_MASK) |
#define | SNVS_LPLR_AT2_HL_MASK (0x2000000U) |
#define | SNVS_LPLR_AT2_HL_SHIFT (25U) |
#define | SNVS_LPLR_AT2_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT2_HL_SHIFT)) & SNVS_LPLR_AT2_HL_MASK) |
#define | SNVS_LPLR_AT3_HL_MASK (0x4000000U) |
#define | SNVS_LPLR_AT3_HL_SHIFT (26U) |
#define | SNVS_LPLR_AT3_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT3_HL_SHIFT)) & SNVS_LPLR_AT3_HL_MASK) |
#define | SNVS_LPLR_AT4_HL_MASK (0x8000000U) |
#define | SNVS_LPLR_AT4_HL_SHIFT (27U) |
#define | SNVS_LPLR_AT4_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT4_HL_SHIFT)) & SNVS_LPLR_AT4_HL_MASK) |
#define | SNVS_LPLR_AT5_HL_MASK (0x10000000U) |
#define | SNVS_LPLR_AT5_HL_SHIFT (28U) |
#define | SNVS_LPLR_AT5_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT5_HL_SHIFT)) & SNVS_LPLR_AT5_HL_MASK) |
LPCR - SNVS_LP Control Register | |
#define | SNVS_LPCR_SRTC_ENV_MASK (0x1U) |
#define | SNVS_LPCR_SRTC_ENV_SHIFT (0U) |
#define | SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) |
#define | SNVS_LPCR_LPTA_EN_MASK (0x2U) |
#define | SNVS_LPCR_LPTA_EN_SHIFT (1U) |
#define | SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) |
#define | SNVS_LPCR_MC_ENV_MASK (0x4U) |
#define | SNVS_LPCR_MC_ENV_SHIFT (2U) |
#define | SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) |
#define | SNVS_LPCR_LPWUI_EN_MASK (0x8U) |
#define | SNVS_LPCR_LPWUI_EN_SHIFT (3U) |
#define | SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) |
#define | SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) |
#define | SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) |
#define | SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) |
#define | SNVS_LPCR_DP_EN_MASK (0x20U) |
#define | SNVS_LPCR_DP_EN_SHIFT (5U) |
#define | SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) |
#define | SNVS_LPCR_TOP_MASK (0x40U) |
#define | SNVS_LPCR_TOP_SHIFT (6U) |
#define | SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) |
#define | SNVS_LPCR_LVD_EN_MASK (0x80U) |
#define | SNVS_LPCR_LVD_EN_SHIFT (7U) |
#define | SNVS_LPCR_LVD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK) |
#define | SNVS_LPCR_LPCALB_EN_MASK (0x100U) |
#define | SNVS_LPCR_LPCALB_EN_SHIFT (8U) |
#define | SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) |
#define | SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) |
#define | SNVS_LPCR_LPCALB_VAL_SHIFT (10U) |
#define | SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) |
#define | SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) |
#define | SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) |
#define | SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) |
#define | SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) |
#define | SNVS_LPCR_DEBOUNCE_SHIFT (18U) |
#define | SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) |
#define | SNVS_LPCR_ON_TIME_MASK (0x300000U) |
#define | SNVS_LPCR_ON_TIME_SHIFT (20U) |
#define | SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) |
#define | SNVS_LPCR_PK_EN_MASK (0x400000U) |
#define | SNVS_LPCR_PK_EN_SHIFT (22U) |
#define | SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) |
#define | SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) |
#define | SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) |
#define | SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) |
#define | SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) |
#define | SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) |
#define | SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) |
LPMKCR - SNVS_LP Master Key Control Register | |
#define | SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) |
#define | SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) |
#define | SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) |
#define | SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) |
#define | SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) |
#define | SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) |
#define | SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) |
#define | SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) |
#define | SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) |
#define | SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) |
#define | SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) |
#define | SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) |
#define | SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) |
#define | SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) |
#define | SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) |
LPSVCR - SNVS_LP Security Violation Control Register | |
#define | SNVS_LPSVCR_CAAM_EN_MASK (0x1U) |
#define | SNVS_LPSVCR_CAAM_EN_SHIFT (0U) |
#define | SNVS_LPSVCR_CAAM_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_CAAM_EN_SHIFT)) & SNVS_LPSVCR_CAAM_EN_MASK) |
#define | SNVS_LPSVCR_JTAGC_EN_MASK (0x2U) |
#define | SNVS_LPSVCR_JTAGC_EN_SHIFT (1U) |
#define | SNVS_LPSVCR_JTAGC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_JTAGC_EN_SHIFT)) & SNVS_LPSVCR_JTAGC_EN_MASK) |
#define | SNVS_LPSVCR_WDOG2_EN_MASK (0x4U) |
#define | SNVS_LPSVCR_WDOG2_EN_SHIFT (2U) |
#define | SNVS_LPSVCR_WDOG2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_WDOG2_EN_SHIFT)) & SNVS_LPSVCR_WDOG2_EN_MASK) |
#define | SNVS_LPSVCR_SRC_EN_MASK (0x10U) |
#define | SNVS_LPSVCR_SRC_EN_SHIFT (4U) |
#define | SNVS_LPSVCR_SRC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SRC_EN_SHIFT)) & SNVS_LPSVCR_SRC_EN_MASK) |
#define | SNVS_LPSVCR_OCOTP_EN_MASK (0x20U) |
#define | SNVS_LPSVCR_OCOTP_EN_SHIFT (5U) |
#define | SNVS_LPSVCR_OCOTP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_OCOTP_EN_SHIFT)) & SNVS_LPSVCR_OCOTP_EN_MASK) |
LPTGFCR - SNVS_LP Tamper Glitch Filters Configuration Register | |
#define | SNVS_LPTGFCR_WMTGF_MASK (0x1FU) |
#define | SNVS_LPTGFCR_WMTGF_SHIFT (0U) |
#define | SNVS_LPTGFCR_WMTGF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_SHIFT)) & SNVS_LPTGFCR_WMTGF_MASK) |
#define | SNVS_LPTGFCR_WMTGF_EN_MASK (0x80U) |
#define | SNVS_LPTGFCR_WMTGF_EN_SHIFT (7U) |
#define | SNVS_LPTGFCR_WMTGF_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK) |
#define | SNVS_LPTGFCR_ETGF1_MASK (0x7F0000U) |
#define | SNVS_LPTGFCR_ETGF1_SHIFT (16U) |
#define | SNVS_LPTGFCR_ETGF1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_SHIFT)) & SNVS_LPTGFCR_ETGF1_MASK) |
#define | SNVS_LPTGFCR_ETGF1_EN_MASK (0x800000U) |
#define | SNVS_LPTGFCR_ETGF1_EN_SHIFT (23U) |
#define | SNVS_LPTGFCR_ETGF1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK) |
#define | SNVS_LPTGFCR_ETGF2_MASK (0x7F000000U) |
#define | SNVS_LPTGFCR_ETGF2_SHIFT (24U) |
#define | SNVS_LPTGFCR_ETGF2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_SHIFT)) & SNVS_LPTGFCR_ETGF2_MASK) |
#define | SNVS_LPTGFCR_ETGF2_EN_MASK (0x80000000U) |
#define | SNVS_LPTGFCR_ETGF2_EN_SHIFT (31U) |
#define | SNVS_LPTGFCR_ETGF2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_EN_SHIFT)) & SNVS_LPTGFCR_ETGF2_EN_MASK) |
LPTDCR - SNVS_LP Tamper Detect Configuration Register | |
#define | SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) |
#define | SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) |
#define | SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) |
#define | SNVS_LPTDCR_MCR_EN_MASK (0x4U) |
#define | SNVS_LPTDCR_MCR_EN_SHIFT (2U) |
#define | SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) |
#define | SNVS_LPTDCR_CT_EN_MASK (0x10U) |
#define | SNVS_LPTDCR_CT_EN_SHIFT (4U) |
#define | SNVS_LPTDCR_CT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK) |
#define | SNVS_LPTDCR_TT_EN_MASK (0x20U) |
#define | SNVS_LPTDCR_TT_EN_SHIFT (5U) |
#define | SNVS_LPTDCR_TT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK) |
#define | SNVS_LPTDCR_VT_EN_MASK (0x40U) |
#define | SNVS_LPTDCR_VT_EN_SHIFT (6U) |
#define | SNVS_LPTDCR_VT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK) |
#define | SNVS_LPTDCR_WMT1_EN_MASK (0x80U) |
#define | SNVS_LPTDCR_WMT1_EN_SHIFT (7U) |
#define | SNVS_LPTDCR_WMT1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK) |
#define | SNVS_LPTDCR_WMT2_EN_MASK (0x100U) |
#define | SNVS_LPTDCR_WMT2_EN_SHIFT (8U) |
#define | SNVS_LPTDCR_WMT2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK) |
#define | SNVS_LPTDCR_ET1_EN_MASK (0x200U) |
#define | SNVS_LPTDCR_ET1_EN_SHIFT (9U) |
#define | SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) |
#define | SNVS_LPTDCR_ET2_EN_MASK (0x400U) |
#define | SNVS_LPTDCR_ET2_EN_SHIFT (10U) |
#define | SNVS_LPTDCR_ET2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK) |
#define | SNVS_LPTDCR_ET1P_MASK (0x800U) |
#define | SNVS_LPTDCR_ET1P_SHIFT (11U) |
#define | SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) |
#define | SNVS_LPTDCR_ET2P_MASK (0x1000U) |
#define | SNVS_LPTDCR_ET2P_SHIFT (12U) |
#define | SNVS_LPTDCR_ET2P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK) |
#define | SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) |
#define | SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) |
#define | SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK) |
#define | SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U) |
#define | SNVS_LPTDCR_POR_OBSERV_SHIFT (15U) |
#define | SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) |
#define | SNVS_LPTDCR_LTDC_MASK (0x70000U) |
#define | SNVS_LPTDCR_LTDC_SHIFT (16U) |
#define | SNVS_LPTDCR_LTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_LTDC_SHIFT)) & SNVS_LPTDCR_LTDC_MASK) |
#define | SNVS_LPTDCR_HTDC_MASK (0x700000U) |
#define | SNVS_LPTDCR_HTDC_SHIFT (20U) |
#define | SNVS_LPTDCR_HTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_HTDC_SHIFT)) & SNVS_LPTDCR_HTDC_MASK) |
#define | SNVS_LPTDCR_VRC_MASK (0x7000000U) |
#define | SNVS_LPTDCR_VRC_SHIFT (24U) |
#define | SNVS_LPTDCR_VRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VRC_SHIFT)) & SNVS_LPTDCR_VRC_MASK) |
#define | SNVS_LPTDCR_OSCB_MASK (0x10000000U) |
#define | SNVS_LPTDCR_OSCB_SHIFT (28U) |
#define | SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) |
LPSR - SNVS_LP Status Register | |
#define | SNVS_LPSR_LPTA_MASK (0x1U) |
#define | SNVS_LPSR_LPTA_SHIFT (0U) |
#define | SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) |
#define | SNVS_LPSR_SRTCR_MASK (0x2U) |
#define | SNVS_LPSR_SRTCR_SHIFT (1U) |
#define | SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) |
#define | SNVS_LPSR_MCR_MASK (0x4U) |
#define | SNVS_LPSR_MCR_SHIFT (2U) |
#define | SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) |
#define | SNVS_LPSR_LVD_MASK (0x8U) |
#define | SNVS_LPSR_LVD_SHIFT (3U) |
#define | SNVS_LPSR_LVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK) |
#define | SNVS_LPSR_CTD_MASK (0x10U) |
#define | SNVS_LPSR_CTD_SHIFT (4U) |
#define | SNVS_LPSR_CTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK) |
#define | SNVS_LPSR_TTD_MASK (0x20U) |
#define | SNVS_LPSR_TTD_SHIFT (5U) |
#define | SNVS_LPSR_TTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK) |
#define | SNVS_LPSR_VTD_MASK (0x40U) |
#define | SNVS_LPSR_VTD_SHIFT (6U) |
#define | SNVS_LPSR_VTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK) |
#define | SNVS_LPSR_WMT1D_MASK (0x80U) |
#define | SNVS_LPSR_WMT1D_SHIFT (7U) |
#define | SNVS_LPSR_WMT1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK) |
#define | SNVS_LPSR_WMT2D_MASK (0x100U) |
#define | SNVS_LPSR_WMT2D_SHIFT (8U) |
#define | SNVS_LPSR_WMT2D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK) |
#define | SNVS_LPSR_ET1D_MASK (0x200U) |
#define | SNVS_LPSR_ET1D_SHIFT (9U) |
#define | SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) |
#define | SNVS_LPSR_ET2D_MASK (0x400U) |
#define | SNVS_LPSR_ET2D_SHIFT (10U) |
#define | SNVS_LPSR_ET2D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK) |
#define | SNVS_LPSR_ESVD_MASK (0x10000U) |
#define | SNVS_LPSR_ESVD_SHIFT (16U) |
#define | SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) |
#define | SNVS_LPSR_EO_MASK (0x20000U) |
#define | SNVS_LPSR_EO_SHIFT (17U) |
#define | SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) |
#define | SNVS_LPSR_SPOF_MASK (0x40000U) |
#define | SNVS_LPSR_SPOF_SHIFT (18U) |
#define | SNVS_LPSR_SPOF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK) |
#define | SNVS_LPSR_LPNS_MASK (0x40000000U) |
#define | SNVS_LPSR_LPNS_SHIFT (30U) |
#define | SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) |
#define | SNVS_LPSR_LPS_MASK (0x80000000U) |
#define | SNVS_LPSR_LPS_SHIFT (31U) |
#define | SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) |
LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register | |
#define | SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) |
#define | SNVS_LPSRTCMR_SRTC_SHIFT (0U) |
#define | SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) |
LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register | |
#define | SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) |
#define | SNVS_LPSRTCLR_SRTC_SHIFT (0U) |
#define | SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) |
LPTAR - SNVS_LP Time Alarm Register | |
#define | SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) |
#define | SNVS_LPTAR_LPTA_SHIFT (0U) |
#define | SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) |
LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register | |
#define | SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) |
#define | SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) |
#define | SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) |
#define | SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) |
#define | SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) |
#define | SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) |
LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register | |
#define | SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) |
#define | SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) |
#define | SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) |
LPLVDR - SNVS_LP Digital Low-Voltage Detector Register | |
#define | SNVS_LPLVDR_LVD_MASK (0xFFFFFFFFU) |
#define | SNVS_LPLVDR_LVD_SHIFT (0U) |
#define | SNVS_LPLVDR_LVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK) |
LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) | |
#define | SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) |
#define | SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) |
#define | SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) |
LPZMKR - SNVS_LP Zeroizable Master Key Register | |
#define | SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) |
#define | SNVS_LPZMKR_ZMK_SHIFT (0U) |
#define | SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) |
LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 | |
#define | SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) |
#define | SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) |
#define | SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) |
LPTDC2R - SNVS_LP Tamper Detectors Config 2 Register | |
#define | SNVS_LPTDC2R_ET3_EN_MASK (0x1U) |
#define | SNVS_LPTDC2R_ET3_EN_SHIFT (0U) |
#define | SNVS_LPTDC2R_ET3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK) |
#define | SNVS_LPTDC2R_ET4_EN_MASK (0x2U) |
#define | SNVS_LPTDC2R_ET4_EN_SHIFT (1U) |
#define | SNVS_LPTDC2R_ET4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK) |
#define | SNVS_LPTDC2R_ET5_EN_MASK (0x4U) |
#define | SNVS_LPTDC2R_ET5_EN_SHIFT (2U) |
#define | SNVS_LPTDC2R_ET5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK) |
#define | SNVS_LPTDC2R_ET6_EN_MASK (0x8U) |
#define | SNVS_LPTDC2R_ET6_EN_SHIFT (3U) |
#define | SNVS_LPTDC2R_ET6_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK) |
#define | SNVS_LPTDC2R_ET7_EN_MASK (0x10U) |
#define | SNVS_LPTDC2R_ET7_EN_SHIFT (4U) |
#define | SNVS_LPTDC2R_ET7_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK) |
#define | SNVS_LPTDC2R_ET8_EN_MASK (0x20U) |
#define | SNVS_LPTDC2R_ET8_EN_SHIFT (5U) |
#define | SNVS_LPTDC2R_ET8_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK) |
#define | SNVS_LPTDC2R_ET9_EN_MASK (0x40U) |
#define | SNVS_LPTDC2R_ET9_EN_SHIFT (6U) |
#define | SNVS_LPTDC2R_ET9_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK) |
#define | SNVS_LPTDC2R_ET10_EN_MASK (0x80U) |
#define | SNVS_LPTDC2R_ET10_EN_SHIFT (7U) |
#define | SNVS_LPTDC2R_ET10_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK) |
#define | SNVS_LPTDC2R_ET3P_MASK (0x10000U) |
#define | SNVS_LPTDC2R_ET3P_SHIFT (16U) |
#define | SNVS_LPTDC2R_ET3P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK) |
#define | SNVS_LPTDC2R_ET4P_MASK (0x20000U) |
#define | SNVS_LPTDC2R_ET4P_SHIFT (17U) |
#define | SNVS_LPTDC2R_ET4P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK) |
#define | SNVS_LPTDC2R_ET5P_MASK (0x40000U) |
#define | SNVS_LPTDC2R_ET5P_SHIFT (18U) |
#define | SNVS_LPTDC2R_ET5P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK) |
#define | SNVS_LPTDC2R_ET6P_MASK (0x80000U) |
#define | SNVS_LPTDC2R_ET6P_SHIFT (19U) |
#define | SNVS_LPTDC2R_ET6P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK) |
#define | SNVS_LPTDC2R_ET7P_MASK (0x100000U) |
#define | SNVS_LPTDC2R_ET7P_SHIFT (20U) |
#define | SNVS_LPTDC2R_ET7P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK) |
#define | SNVS_LPTDC2R_ET8P_MASK (0x200000U) |
#define | SNVS_LPTDC2R_ET8P_SHIFT (21U) |
#define | SNVS_LPTDC2R_ET8P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK) |
#define | SNVS_LPTDC2R_ET9P_MASK (0x400000U) |
#define | SNVS_LPTDC2R_ET9P_SHIFT (22U) |
#define | SNVS_LPTDC2R_ET9P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK) |
#define | SNVS_LPTDC2R_ET10P_MASK (0x800000U) |
#define | SNVS_LPTDC2R_ET10P_SHIFT (23U) |
#define | SNVS_LPTDC2R_ET10P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10P_SHIFT)) & SNVS_LPTDC2R_ET10P_MASK) |
LPTDSR - SNVS_LP Tamper Detectors Status Register | |
#define | SNVS_LPTDSR_ET3D_MASK (0x1U) |
#define | SNVS_LPTDSR_ET3D_SHIFT (0U) |
#define | SNVS_LPTDSR_ET3D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK) |
#define | SNVS_LPTDSR_ET4D_MASK (0x2U) |
#define | SNVS_LPTDSR_ET4D_SHIFT (1U) |
#define | SNVS_LPTDSR_ET4D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK) |
#define | SNVS_LPTDSR_ET5D_MASK (0x4U) |
#define | SNVS_LPTDSR_ET5D_SHIFT (2U) |
#define | SNVS_LPTDSR_ET5D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK) |
#define | SNVS_LPTDSR_ET6D_MASK (0x8U) |
#define | SNVS_LPTDSR_ET6D_SHIFT (3U) |
#define | SNVS_LPTDSR_ET6D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK) |
#define | SNVS_LPTDSR_ET7D_MASK (0x10U) |
#define | SNVS_LPTDSR_ET7D_SHIFT (4U) |
#define | SNVS_LPTDSR_ET7D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK) |
#define | SNVS_LPTDSR_ET8D_MASK (0x20U) |
#define | SNVS_LPTDSR_ET8D_SHIFT (5U) |
#define | SNVS_LPTDSR_ET8D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK) |
#define | SNVS_LPTDSR_ET9D_MASK (0x40U) |
#define | SNVS_LPTDSR_ET9D_SHIFT (6U) |
#define | SNVS_LPTDSR_ET9D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK) |
#define | SNVS_LPTDSR_ET10D_MASK (0x80U) |
#define | SNVS_LPTDSR_ET10D_SHIFT (7U) |
#define | SNVS_LPTDSR_ET10D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET10D_SHIFT)) & SNVS_LPTDSR_ET10D_MASK) |
LPTGF1CR - SNVS_LP Tamper Glitch Filter 1 Configuration Register | |
#define | SNVS_LPTGF1CR_ETGF3_MASK (0x7FU) |
#define | SNVS_LPTGF1CR_ETGF3_SHIFT (0U) |
#define | SNVS_LPTGF1CR_ETGF3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_SHIFT)) & SNVS_LPTGF1CR_ETGF3_MASK) |
#define | SNVS_LPTGF1CR_ETGF3_EN_MASK (0x80U) |
#define | SNVS_LPTGF1CR_ETGF3_EN_SHIFT (7U) |
#define | SNVS_LPTGF1CR_ETGF3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK) |
#define | SNVS_LPTGF1CR_ETGF4_MASK (0x7F00U) |
#define | SNVS_LPTGF1CR_ETGF4_SHIFT (8U) |
#define | SNVS_LPTGF1CR_ETGF4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_SHIFT)) & SNVS_LPTGF1CR_ETGF4_MASK) |
#define | SNVS_LPTGF1CR_ETGF4_EN_MASK (0x8000U) |
#define | SNVS_LPTGF1CR_ETGF4_EN_SHIFT (15U) |
#define | SNVS_LPTGF1CR_ETGF4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK) |
#define | SNVS_LPTGF1CR_ETGF5_MASK (0x7F0000U) |
#define | SNVS_LPTGF1CR_ETGF5_SHIFT (16U) |
#define | SNVS_LPTGF1CR_ETGF5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_SHIFT)) & SNVS_LPTGF1CR_ETGF5_MASK) |
#define | SNVS_LPTGF1CR_ETGF5_EN_MASK (0x800000U) |
#define | SNVS_LPTGF1CR_ETGF5_EN_SHIFT (23U) |
#define | SNVS_LPTGF1CR_ETGF5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK) |
#define | SNVS_LPTGF1CR_ETGF6_MASK (0x7F000000U) |
#define | SNVS_LPTGF1CR_ETGF6_SHIFT (24U) |
#define | SNVS_LPTGF1CR_ETGF6(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_SHIFT)) & SNVS_LPTGF1CR_ETGF6_MASK) |
#define | SNVS_LPTGF1CR_ETGF6_EN_MASK (0x80000000U) |
#define | SNVS_LPTGF1CR_ETGF6_EN_SHIFT (31U) |
#define | SNVS_LPTGF1CR_ETGF6_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF6_EN_MASK) |
LPTGF2CR - SNVS_LP Tamper Glitch Filter 2 Configuration Register | |
#define | SNVS_LPTGF2CR_ETGF7_MASK (0x7FU) |
#define | SNVS_LPTGF2CR_ETGF7_SHIFT (0U) |
#define | SNVS_LPTGF2CR_ETGF7(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_SHIFT)) & SNVS_LPTGF2CR_ETGF7_MASK) |
#define | SNVS_LPTGF2CR_ETGF7_EN_MASK (0x80U) |
#define | SNVS_LPTGF2CR_ETGF7_EN_SHIFT (7U) |
#define | SNVS_LPTGF2CR_ETGF7_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK) |
#define | SNVS_LPTGF2CR_ETGF8_MASK (0x7F00U) |
#define | SNVS_LPTGF2CR_ETGF8_SHIFT (8U) |
#define | SNVS_LPTGF2CR_ETGF8(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_SHIFT)) & SNVS_LPTGF2CR_ETGF8_MASK) |
#define | SNVS_LPTGF2CR_ETGF8_EN_MASK (0x8000U) |
#define | SNVS_LPTGF2CR_ETGF8_EN_SHIFT (15U) |
#define | SNVS_LPTGF2CR_ETGF8_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK) |
#define | SNVS_LPTGF2CR_ETGF9_MASK (0x7F0000U) |
#define | SNVS_LPTGF2CR_ETGF9_SHIFT (16U) |
#define | SNVS_LPTGF2CR_ETGF9(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_SHIFT)) & SNVS_LPTGF2CR_ETGF9_MASK) |
#define | SNVS_LPTGF2CR_ETGF9_EN_MASK (0x800000U) |
#define | SNVS_LPTGF2CR_ETGF9_EN_SHIFT (23U) |
#define | SNVS_LPTGF2CR_ETGF9_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK) |
#define | SNVS_LPTGF2CR_ETGF10_MASK (0x7F000000U) |
#define | SNVS_LPTGF2CR_ETGF10_SHIFT (24U) |
#define | SNVS_LPTGF2CR_ETGF10(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_SHIFT)) & SNVS_LPTGF2CR_ETGF10_MASK) |
#define | SNVS_LPTGF2CR_ETGF10_EN_MASK (0x80000000U) |
#define | SNVS_LPTGF2CR_ETGF10_EN_SHIFT (31U) |
#define | SNVS_LPTGF2CR_ETGF10_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF10_EN_MASK) |
LPATCR - SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register | |
#define | SNVS_LPATCR_Seed_MASK (0xFFFFU) |
#define | SNVS_LPATCR_Seed_SHIFT (0U) |
#define | SNVS_LPATCR_Seed(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Seed_SHIFT)) & SNVS_LPATCR_Seed_MASK) |
#define | SNVS_LPATCR_Polynomial_MASK (0xFFFF0000U) |
#define | SNVS_LPATCR_Polynomial_SHIFT (16U) |
#define | SNVS_LPATCR_Polynomial(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Polynomial_SHIFT)) & SNVS_LPATCR_Polynomial_MASK) |
LPATCTLR - SNVS_LP Active Tamper Control Register | |
#define | SNVS_LPATCTLR_AT1_EN_MASK (0x1U) |
#define | SNVS_LPATCTLR_AT1_EN_SHIFT (0U) |
#define | SNVS_LPATCTLR_AT1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_EN_SHIFT)) & SNVS_LPATCTLR_AT1_EN_MASK) |
#define | SNVS_LPATCTLR_AT2_EN_MASK (0x2U) |
#define | SNVS_LPATCTLR_AT2_EN_SHIFT (1U) |
#define | SNVS_LPATCTLR_AT2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_EN_SHIFT)) & SNVS_LPATCTLR_AT2_EN_MASK) |
#define | SNVS_LPATCTLR_AT3_EN_MASK (0x4U) |
#define | SNVS_LPATCTLR_AT3_EN_SHIFT (2U) |
#define | SNVS_LPATCTLR_AT3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_EN_SHIFT)) & SNVS_LPATCTLR_AT3_EN_MASK) |
#define | SNVS_LPATCTLR_AT4_EN_MASK (0x8U) |
#define | SNVS_LPATCTLR_AT4_EN_SHIFT (3U) |
#define | SNVS_LPATCTLR_AT4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_EN_SHIFT)) & SNVS_LPATCTLR_AT4_EN_MASK) |
#define | SNVS_LPATCTLR_AT5_EN_MASK (0x10U) |
#define | SNVS_LPATCTLR_AT5_EN_SHIFT (4U) |
#define | SNVS_LPATCTLR_AT5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_EN_SHIFT)) & SNVS_LPATCTLR_AT5_EN_MASK) |
#define | SNVS_LPATCTLR_AT1_PAD_EN_MASK (0x10000U) |
#define | SNVS_LPATCTLR_AT1_PAD_EN_SHIFT (16U) |
#define | SNVS_LPATCTLR_AT1_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT1_PAD_EN_MASK) |
#define | SNVS_LPATCTLR_AT2_PAD_EN_MASK (0x20000U) |
#define | SNVS_LPATCTLR_AT2_PAD_EN_SHIFT (17U) |
#define | SNVS_LPATCTLR_AT2_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT2_PAD_EN_MASK) |
#define | SNVS_LPATCTLR_AT3_PAD_EN_MASK (0x40000U) |
#define | SNVS_LPATCTLR_AT3_PAD_EN_SHIFT (18U) |
#define | SNVS_LPATCTLR_AT3_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT3_PAD_EN_MASK) |
#define | SNVS_LPATCTLR_AT4_PAD_EN_MASK (0x80000U) |
#define | SNVS_LPATCTLR_AT4_PAD_EN_SHIFT (19U) |
#define | SNVS_LPATCTLR_AT4_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT4_PAD_EN_MASK) |
#define | SNVS_LPATCTLR_AT5_PAD_EN_MASK (0x100000U) |
#define | SNVS_LPATCTLR_AT5_PAD_EN_SHIFT (20U) |
#define | SNVS_LPATCTLR_AT5_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT5_PAD_EN_MASK) |
LPATCLKR - SNVS_LP Active Tamper Clock Control Register | |
#define | SNVS_LPATCLKR_AT1_CLK_CTL_MASK (0x3U) |
#define | SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT (0U) |
#define | SNVS_LPATCLKR_AT1_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT1_CLK_CTL_MASK) |
#define | SNVS_LPATCLKR_AT2_CLK_CTL_MASK (0x30U) |
#define | SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT (4U) |
#define | SNVS_LPATCLKR_AT2_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT2_CLK_CTL_MASK) |
#define | SNVS_LPATCLKR_AT3_CLK_CTL_MASK (0x300U) |
#define | SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT (8U) |
#define | SNVS_LPATCLKR_AT3_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT3_CLK_CTL_MASK) |
#define | SNVS_LPATCLKR_AT4_CLK_CTL_MASK (0x3000U) |
#define | SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT (12U) |
#define | SNVS_LPATCLKR_AT4_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT4_CLK_CTL_MASK) |
#define | SNVS_LPATCLKR_AT5_CLK_CTL_MASK (0x30000U) |
#define | SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT (16U) |
#define | SNVS_LPATCLKR_AT5_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT5_CLK_CTL_MASK) |
LPATRC1R - SNVS_LP Active Tamper Routing Control 1 Register | |
#define | SNVS_LPATRC1R_ET1RCTL_MASK (0x7U) |
#define | SNVS_LPATRC1R_ET1RCTL_SHIFT (0U) |
#define | SNVS_LPATRC1R_ET1RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET1RCTL_SHIFT)) & SNVS_LPATRC1R_ET1RCTL_MASK) |
#define | SNVS_LPATRC1R_ET2RCTL_MASK (0x70U) |
#define | SNVS_LPATRC1R_ET2RCTL_SHIFT (4U) |
#define | SNVS_LPATRC1R_ET2RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET2RCTL_SHIFT)) & SNVS_LPATRC1R_ET2RCTL_MASK) |
#define | SNVS_LPATRC1R_ET3RCTL_MASK (0x700U) |
#define | SNVS_LPATRC1R_ET3RCTL_SHIFT (8U) |
#define | SNVS_LPATRC1R_ET3RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET3RCTL_SHIFT)) & SNVS_LPATRC1R_ET3RCTL_MASK) |
#define | SNVS_LPATRC1R_ET4RCTL_MASK (0x7000U) |
#define | SNVS_LPATRC1R_ET4RCTL_SHIFT (12U) |
#define | SNVS_LPATRC1R_ET4RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET4RCTL_SHIFT)) & SNVS_LPATRC1R_ET4RCTL_MASK) |
#define | SNVS_LPATRC1R_ET5RCTL_MASK (0x70000U) |
#define | SNVS_LPATRC1R_ET5RCTL_SHIFT (16U) |
#define | SNVS_LPATRC1R_ET5RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET5RCTL_SHIFT)) & SNVS_LPATRC1R_ET5RCTL_MASK) |
#define | SNVS_LPATRC1R_ET6RCTL_MASK (0x700000U) |
#define | SNVS_LPATRC1R_ET6RCTL_SHIFT (20U) |
#define | SNVS_LPATRC1R_ET6RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET6RCTL_SHIFT)) & SNVS_LPATRC1R_ET6RCTL_MASK) |
#define | SNVS_LPATRC1R_ET7RCTL_MASK (0x7000000U) |
#define | SNVS_LPATRC1R_ET7RCTL_SHIFT (24U) |
#define | SNVS_LPATRC1R_ET7RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET7RCTL_SHIFT)) & SNVS_LPATRC1R_ET7RCTL_MASK) |
#define | SNVS_LPATRC1R_ET8RCTL_MASK (0x70000000U) |
#define | SNVS_LPATRC1R_ET8RCTL_SHIFT (28U) |
#define | SNVS_LPATRC1R_ET8RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET8RCTL_SHIFT)) & SNVS_LPATRC1R_ET8RCTL_MASK) |
LPATRC2R - SNVS_LP Active Tamper Routing Control 2 Register | |
#define | SNVS_LPATRC2R_ET9RCTL_MASK (0x7U) |
#define | SNVS_LPATRC2R_ET9RCTL_SHIFT (0U) |
#define | SNVS_LPATRC2R_ET9RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET9RCTL_SHIFT)) & SNVS_LPATRC2R_ET9RCTL_MASK) |
#define | SNVS_LPATRC2R_ET10RCTL_MASK (0x70U) |
#define | SNVS_LPATRC2R_ET10RCTL_SHIFT (4U) |
#define | SNVS_LPATRC2R_ET10RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET10RCTL_SHIFT)) & SNVS_LPATRC2R_ET10RCTL_MASK) |
LPGPR - SNVS_LP General Purpose Registers 0 .. 3 | |
#define | SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) |
#define | SNVS_LPGPR_GPR_SHIFT (0U) |
#define | SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) |
HPVIDR1 - SNVS_HP Version ID Register 1 | |
#define | SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) |
#define | SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) |
#define | SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) |
#define | SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) |
#define | SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) |
#define | SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) |
#define | SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) |
#define | SNVS_HPVIDR1_IP_ID_SHIFT (16U) |
#define | SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) |
HPVIDR2 - SNVS_HP Version ID Register 2 | |
#define | SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) |
#define | SNVS_HPVIDR2_ECO_REV_SHIFT (8U) |
#define | SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) |
#define | SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) |
#define | SNVS_HPVIDR2_IP_ERA_SHIFT (24U) |
#define | SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) |
SCR - SPDIF Configuration Register | |
#define | SPDIF_SCR_USRC_SEL_MASK (0x3U) |
#define | SPDIF_SCR_USRC_SEL_SHIFT (0U) |
#define | SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) |
#define | SPDIF_SCR_TXSEL_MASK (0x1CU) |
#define | SPDIF_SCR_TXSEL_SHIFT (2U) |
#define | SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) |
#define | SPDIF_SCR_VALCTRL_MASK (0x20U) |
#define | SPDIF_SCR_VALCTRL_SHIFT (5U) |
#define | SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) |
#define | SPDIF_SCR_INPUTSRCSEL_MASK (0xC0U) |
#define | SPDIF_SCR_INPUTSRCSEL_SHIFT (6U) |
#define | SPDIF_SCR_INPUTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_INPUTSRCSEL_SHIFT)) & SPDIF_SCR_INPUTSRCSEL_MASK) |
#define | SPDIF_SCR_DMA_TX_EN_MASK (0x100U) |
#define | SPDIF_SCR_DMA_TX_EN_SHIFT (8U) |
#define | SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) |
#define | SPDIF_SCR_DMA_RX_EN_MASK (0x200U) |
#define | SPDIF_SCR_DMA_RX_EN_SHIFT (9U) |
#define | SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) |
#define | SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) |
#define | SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) |
#define | SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) |
#define | SPDIF_SCR_SOFT_RESET_MASK (0x1000U) |
#define | SPDIF_SCR_SOFT_RESET_SHIFT (12U) |
#define | SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) |
#define | SPDIF_SCR_LOW_POWER_MASK (0x2000U) |
#define | SPDIF_SCR_LOW_POWER_SHIFT (13U) |
#define | SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) |
#define | SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) |
#define | SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) |
#define | SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) |
#define | SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) |
#define | SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) |
#define | SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) |
#define | SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) |
#define | SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) |
#define | SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) |
#define | SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) |
#define | SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) |
#define | SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) |
#define | SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) |
#define | SPDIF_SCR_RXFIFO_RST_SHIFT (21U) |
#define | SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) |
#define | SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) |
#define | SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) |
#define | SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) |
#define | SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) |
#define | SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) |
#define | SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) |
SRCD - CDText Control Register | |
#define | SPDIF_SRCD_USYNCMODE_MASK (0x2U) |
#define | SPDIF_SRCD_USYNCMODE_SHIFT (1U) |
#define | SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) |
SRPC - PhaseConfig Register | |
#define | SPDIF_SRPC_GAINSEL_MASK (0x38U) |
#define | SPDIF_SRPC_GAINSEL_SHIFT (3U) |
#define | SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) |
#define | SPDIF_SRPC_LOCK_MASK (0x40U) |
#define | SPDIF_SRPC_LOCK_SHIFT (6U) |
#define | SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) |
#define | SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) |
#define | SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) |
#define | SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) |
SIE - InterruptEn Register | |
#define | SPDIF_SIE_RXFIFOFUL_MASK (0x1U) |
#define | SPDIF_SIE_RXFIFOFUL_SHIFT (0U) |
#define | SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) |
#define | SPDIF_SIE_TXEM_MASK (0x2U) |
#define | SPDIF_SIE_TXEM_SHIFT (1U) |
#define | SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) |
#define | SPDIF_SIE_LOCKLOSS_MASK (0x4U) |
#define | SPDIF_SIE_LOCKLOSS_SHIFT (2U) |
#define | SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) |
#define | SPDIF_SIE_RXFIFORESYN_MASK (0x8U) |
#define | SPDIF_SIE_RXFIFORESYN_SHIFT (3U) |
#define | SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) |
#define | SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) |
#define | SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) |
#define | SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) |
#define | SPDIF_SIE_UQERR_MASK (0x20U) |
#define | SPDIF_SIE_UQERR_SHIFT (5U) |
#define | SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) |
#define | SPDIF_SIE_UQSYNC_MASK (0x40U) |
#define | SPDIF_SIE_UQSYNC_SHIFT (6U) |
#define | SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) |
#define | SPDIF_SIE_QRXOV_MASK (0x80U) |
#define | SPDIF_SIE_QRXOV_SHIFT (7U) |
#define | SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) |
#define | SPDIF_SIE_QRXFUL_MASK (0x100U) |
#define | SPDIF_SIE_QRXFUL_SHIFT (8U) |
#define | SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) |
#define | SPDIF_SIE_URXOV_MASK (0x200U) |
#define | SPDIF_SIE_URXOV_SHIFT (9U) |
#define | SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) |
#define | SPDIF_SIE_URXFUL_MASK (0x400U) |
#define | SPDIF_SIE_URXFUL_SHIFT (10U) |
#define | SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) |
#define | SPDIF_SIE_BITERR_MASK (0x4000U) |
#define | SPDIF_SIE_BITERR_SHIFT (14U) |
#define | SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) |
#define | SPDIF_SIE_SYMERR_MASK (0x8000U) |
#define | SPDIF_SIE_SYMERR_SHIFT (15U) |
#define | SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) |
#define | SPDIF_SIE_VALNOGOOD_MASK (0x10000U) |
#define | SPDIF_SIE_VALNOGOOD_SHIFT (16U) |
#define | SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) |
#define | SPDIF_SIE_CNEW_MASK (0x20000U) |
#define | SPDIF_SIE_CNEW_SHIFT (17U) |
#define | SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) |
#define | SPDIF_SIE_TXRESYN_MASK (0x40000U) |
#define | SPDIF_SIE_TXRESYN_SHIFT (18U) |
#define | SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) |
#define | SPDIF_SIE_TXUNOV_MASK (0x80000U) |
#define | SPDIF_SIE_TXUNOV_SHIFT (19U) |
#define | SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) |
#define | SPDIF_SIE_LOCK_MASK (0x100000U) |
#define | SPDIF_SIE_LOCK_SHIFT (20U) |
#define | SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) |
SIC - InterruptClear Register | |
#define | SPDIF_SIC_LOCKLOSS_MASK (0x4U) |
#define | SPDIF_SIC_LOCKLOSS_SHIFT (2U) |
#define | SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) |
#define | SPDIF_SIC_RXFIFORESYN_MASK (0x8U) |
#define | SPDIF_SIC_RXFIFORESYN_SHIFT (3U) |
#define | SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) |
#define | SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) |
#define | SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) |
#define | SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) |
#define | SPDIF_SIC_UQERR_MASK (0x20U) |
#define | SPDIF_SIC_UQERR_SHIFT (5U) |
#define | SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) |
#define | SPDIF_SIC_UQSYNC_MASK (0x40U) |
#define | SPDIF_SIC_UQSYNC_SHIFT (6U) |
#define | SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) |
#define | SPDIF_SIC_QRXOV_MASK (0x80U) |
#define | SPDIF_SIC_QRXOV_SHIFT (7U) |
#define | SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) |
#define | SPDIF_SIC_URXOV_MASK (0x200U) |
#define | SPDIF_SIC_URXOV_SHIFT (9U) |
#define | SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) |
#define | SPDIF_SIC_BITERR_MASK (0x4000U) |
#define | SPDIF_SIC_BITERR_SHIFT (14U) |
#define | SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) |
#define | SPDIF_SIC_SYMERR_MASK (0x8000U) |
#define | SPDIF_SIC_SYMERR_SHIFT (15U) |
#define | SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) |
#define | SPDIF_SIC_VALNOGOOD_MASK (0x10000U) |
#define | SPDIF_SIC_VALNOGOOD_SHIFT (16U) |
#define | SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) |
#define | SPDIF_SIC_CNEW_MASK (0x20000U) |
#define | SPDIF_SIC_CNEW_SHIFT (17U) |
#define | SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) |
#define | SPDIF_SIC_TXRESYN_MASK (0x40000U) |
#define | SPDIF_SIC_TXRESYN_SHIFT (18U) |
#define | SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) |
#define | SPDIF_SIC_TXUNOV_MASK (0x80000U) |
#define | SPDIF_SIC_TXUNOV_SHIFT (19U) |
#define | SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) |
#define | SPDIF_SIC_LOCK_MASK (0x100000U) |
#define | SPDIF_SIC_LOCK_SHIFT (20U) |
#define | SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) |
SIS - InterruptStat Register | |
#define | SPDIF_SIS_RXFIFOFUL_MASK (0x1U) |
#define | SPDIF_SIS_RXFIFOFUL_SHIFT (0U) |
#define | SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) |
#define | SPDIF_SIS_TXEM_MASK (0x2U) |
#define | SPDIF_SIS_TXEM_SHIFT (1U) |
#define | SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) |
#define | SPDIF_SIS_LOCKLOSS_MASK (0x4U) |
#define | SPDIF_SIS_LOCKLOSS_SHIFT (2U) |
#define | SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) |
#define | SPDIF_SIS_RXFIFORESYN_MASK (0x8U) |
#define | SPDIF_SIS_RXFIFORESYN_SHIFT (3U) |
#define | SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) |
#define | SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) |
#define | SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) |
#define | SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) |
#define | SPDIF_SIS_UQERR_MASK (0x20U) |
#define | SPDIF_SIS_UQERR_SHIFT (5U) |
#define | SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) |
#define | SPDIF_SIS_UQSYNC_MASK (0x40U) |
#define | SPDIF_SIS_UQSYNC_SHIFT (6U) |
#define | SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) |
#define | SPDIF_SIS_QRXOV_MASK (0x80U) |
#define | SPDIF_SIS_QRXOV_SHIFT (7U) |
#define | SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) |
#define | SPDIF_SIS_QRXFUL_MASK (0x100U) |
#define | SPDIF_SIS_QRXFUL_SHIFT (8U) |
#define | SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) |
#define | SPDIF_SIS_URXOV_MASK (0x200U) |
#define | SPDIF_SIS_URXOV_SHIFT (9U) |
#define | SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) |
#define | SPDIF_SIS_URXFUL_MASK (0x400U) |
#define | SPDIF_SIS_URXFUL_SHIFT (10U) |
#define | SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) |
#define | SPDIF_SIS_BITERR_MASK (0x4000U) |
#define | SPDIF_SIS_BITERR_SHIFT (14U) |
#define | SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) |
#define | SPDIF_SIS_SYMERR_MASK (0x8000U) |
#define | SPDIF_SIS_SYMERR_SHIFT (15U) |
#define | SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) |
#define | SPDIF_SIS_VALNOGOOD_MASK (0x10000U) |
#define | SPDIF_SIS_VALNOGOOD_SHIFT (16U) |
#define | SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) |
#define | SPDIF_SIS_CNEW_MASK (0x20000U) |
#define | SPDIF_SIS_CNEW_SHIFT (17U) |
#define | SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) |
#define | SPDIF_SIS_TXRESYN_MASK (0x40000U) |
#define | SPDIF_SIS_TXRESYN_SHIFT (18U) |
#define | SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) |
#define | SPDIF_SIS_TXUNOV_MASK (0x80000U) |
#define | SPDIF_SIS_TXUNOV_SHIFT (19U) |
#define | SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) |
#define | SPDIF_SIS_LOCK_MASK (0x100000U) |
#define | SPDIF_SIS_LOCK_SHIFT (20U) |
#define | SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) |
SRL - SPDIFRxLeft Register | |
#define | SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) |
#define | SPDIF_SRL_RXDATALEFT_SHIFT (0U) |
#define | SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) |
SRR - SPDIFRxRight Register | |
#define | SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) |
#define | SPDIF_SRR_RXDATARIGHT_SHIFT (0U) |
#define | SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) |
SRCSH - SPDIFRxCChannel_h Register | |
#define | SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) |
#define | SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) |
#define | SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) |
SRCSL - SPDIFRxCChannel_l Register | |
#define | SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) |
#define | SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) |
#define | SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) |
SRU - UchannelRx Register | |
#define | SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) |
#define | SPDIF_SRU_RXUCHANNEL_SHIFT (0U) |
#define | SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) |
SRQ - QchannelRx Register | |
#define | SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) |
#define | SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) |
#define | SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) |
STL - SPDIFTxLeft Register | |
#define | SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) |
#define | SPDIF_STL_TXDATALEFT_SHIFT (0U) |
#define | SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) |
STR - SPDIFTxRight Register | |
#define | SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) |
#define | SPDIF_STR_TXDATARIGHT_SHIFT (0U) |
#define | SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) |
STCSCH - SPDIFTxCChannelCons_h Register | |
#define | SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) |
#define | SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) |
#define | SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) |
STCSCL - SPDIFTxCChannelCons_l Register | |
#define | SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) |
#define | SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) |
#define | SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) |
SRFM - FreqMeas Register | |
#define | SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) |
#define | SPDIF_SRFM_FREQMEAS_SHIFT (0U) |
#define | SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) |
STC - SPDIFTxClk Register | |
#define | SPDIF_STC_TXCLK_DF_MASK (0x7FU) |
#define | SPDIF_STC_TXCLK_DF_SHIFT (0U) |
#define | SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) |
#define | SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) |
#define | SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) |
#define | SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) |
#define | SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) |
#define | SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) |
#define | SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) |
#define | SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) |
#define | SPDIF_STC_SYSCLK_DF_SHIFT (11U) |
#define | SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) |
SCR - SRC Control Register | |
#define | SRC_SCR_BT_RELEASE_M4_MASK (0x1U) |
#define | SRC_SCR_BT_RELEASE_M4_SHIFT (0U) |
#define | SRC_SCR_BT_RELEASE_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M4_SHIFT)) & SRC_SCR_BT_RELEASE_M4_MASK) |
#define | SRC_SCR_BT_RELEASE_M7_MASK (0x2U) |
#define | SRC_SCR_BT_RELEASE_M7_SHIFT (1U) |
#define | SRC_SCR_BT_RELEASE_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M7_SHIFT)) & SRC_SCR_BT_RELEASE_M7_MASK) |
SRMR - SRC Reset Mode Register | |
#define | SRC_SRMR_WDOG_RESET_MODE_MASK (0x3U) |
#define | SRC_SRMR_WDOG_RESET_MODE_SHIFT (0U) |
#define | SRC_SRMR_WDOG_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG_RESET_MODE_MASK) |
#define | SRC_SRMR_WDOG3_RESET_MODE_MASK (0xCU) |
#define | SRC_SRMR_WDOG3_RESET_MODE_SHIFT (2U) |
#define | SRC_SRMR_WDOG3_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG3_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG3_RESET_MODE_MASK) |
#define | SRC_SRMR_WDOG4_RESET_MODE_MASK (0x30U) |
#define | SRC_SRMR_WDOG4_RESET_MODE_SHIFT (4U) |
#define | SRC_SRMR_WDOG4_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG4_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG4_RESET_MODE_MASK) |
#define | SRC_SRMR_M4LOCKUP_RESET_MODE_MASK (0xC0U) |
#define | SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT (6U) |
#define | SRC_SRMR_M4LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M4LOCKUP_RESET_MODE_MASK) |
#define | SRC_SRMR_M7LOCKUP_RESET_MODE_MASK (0x300U) |
#define | SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT (8U) |
#define | SRC_SRMR_M7LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M7LOCKUP_RESET_MODE_MASK) |
#define | SRC_SRMR_M4REQ_RESET_MODE_MASK (0xC00U) |
#define | SRC_SRMR_M4REQ_RESET_MODE_SHIFT (10U) |
#define | SRC_SRMR_M4REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M4REQ_RESET_MODE_MASK) |
#define | SRC_SRMR_M7REQ_RESET_MODE_MASK (0x3000U) |
#define | SRC_SRMR_M7REQ_RESET_MODE_SHIFT (12U) |
#define | SRC_SRMR_M7REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M7REQ_RESET_MODE_MASK) |
#define | SRC_SRMR_TEMPSENSE_RESET_MODE_MASK (0xC000U) |
#define | SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT (14U) |
#define | SRC_SRMR_TEMPSENSE_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_SRMR_TEMPSENSE_RESET_MODE_MASK) |
#define | SRC_SRMR_CSU_RESET_MODE_MASK (0x30000U) |
#define | SRC_SRMR_CSU_RESET_MODE_SHIFT (16U) |
#define | SRC_SRMR_CSU_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_CSU_RESET_MODE_SHIFT)) & SRC_SRMR_CSU_RESET_MODE_MASK) |
#define | SRC_SRMR_JTAGSW_RESET_MODE_MASK (0xC0000U) |
#define | SRC_SRMR_JTAGSW_RESET_MODE_SHIFT (18U) |
#define | SRC_SRMR_JTAGSW_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_JTAGSW_RESET_MODE_SHIFT)) & SRC_SRMR_JTAGSW_RESET_MODE_MASK) |
#define | SRC_SRMR_OVERVOLT_RESET_MODE_MASK (0x300000U) |
#define | SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT (20U) |
#define | SRC_SRMR_OVERVOLT_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT)) & SRC_SRMR_OVERVOLT_RESET_MODE_MASK) |
SBMR1 - SRC Boot Mode Register 1 | |
#define | SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) |
#define | SRC_SBMR1_BOOT_CFG1_SHIFT (0U) |
#define | SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) |
#define | SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) |
#define | SRC_SBMR1_BOOT_CFG2_SHIFT (8U) |
#define | SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) |
#define | SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) |
#define | SRC_SBMR1_BOOT_CFG3_SHIFT (16U) |
#define | SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) |
#define | SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) |
#define | SRC_SBMR1_BOOT_CFG4_SHIFT (24U) |
#define | SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) |
SBMR2 - SRC Boot Mode Register 2 | |
#define | SRC_SBMR2_SEC_CONFIG_MASK (0x3U) |
#define | SRC_SBMR2_SEC_CONFIG_SHIFT (0U) |
#define | SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) |
#define | SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) |
#define | SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) |
#define | SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) |
#define | SRC_SBMR2_BMOD_MASK (0x3000000U) |
#define | SRC_SBMR2_BMOD_SHIFT (24U) |
#define | SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) |
SRSR - SRC Reset Status Register | |
#define | SRC_SRSR_IPP_RESET_B_M7_MASK (0x1U) |
#define | SRC_SRSR_IPP_RESET_B_M7_SHIFT (0U) |
#define | SRC_SRSR_IPP_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_RESET_B_M7_MASK) |
#define | SRC_SRSR_M7_REQUEST_M7_MASK (0x2U) |
#define | SRC_SRSR_M7_REQUEST_M7_SHIFT (1U) |
#define | SRC_SRSR_M7_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M7_SHIFT)) & SRC_SRSR_M7_REQUEST_M7_MASK) |
#define | SRC_SRSR_M7_LOCKUP_M7_MASK (0x4U) |
#define | SRC_SRSR_M7_LOCKUP_M7_SHIFT (2U) |
#define | SRC_SRSR_M7_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M7_SHIFT)) & SRC_SRSR_M7_LOCKUP_M7_MASK) |
#define | SRC_SRSR_CSU_RESET_B_M7_MASK (0x8U) |
#define | SRC_SRSR_CSU_RESET_B_M7_SHIFT (3U) |
#define | SRC_SRSR_CSU_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M7_SHIFT)) & SRC_SRSR_CSU_RESET_B_M7_MASK) |
#define | SRC_SRSR_IPP_USER_RESET_B_M7_MASK (0x10U) |
#define | SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT (4U) |
#define | SRC_SRSR_IPP_USER_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M7_MASK) |
#define | SRC_SRSR_WDOG_RST_B_M7_MASK (0x20U) |
#define | SRC_SRSR_WDOG_RST_B_M7_SHIFT (5U) |
#define | SRC_SRSR_WDOG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG_RST_B_M7_MASK) |
#define | SRC_SRSR_JTAG_RST_B_M7_MASK (0x40U) |
#define | SRC_SRSR_JTAG_RST_B_M7_SHIFT (6U) |
#define | SRC_SRSR_JTAG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M7_SHIFT)) & SRC_SRSR_JTAG_RST_B_M7_MASK) |
#define | SRC_SRSR_JTAG_SW_RST_M7_MASK (0x80U) |
#define | SRC_SRSR_JTAG_SW_RST_M7_SHIFT (7U) |
#define | SRC_SRSR_JTAG_SW_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M7_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M7_MASK) |
#define | SRC_SRSR_WDOG3_RST_B_M7_MASK (0x100U) |
#define | SRC_SRSR_WDOG3_RST_B_M7_SHIFT (8U) |
#define | SRC_SRSR_WDOG3_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M7_MASK) |
#define | SRC_SRSR_WDOG4_RST_B_M7_MASK (0x200U) |
#define | SRC_SRSR_WDOG4_RST_B_M7_SHIFT (9U) |
#define | SRC_SRSR_WDOG4_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M7_MASK) |
#define | SRC_SRSR_TEMPSENSE_RST_B_M7_MASK (0x400U) |
#define | SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT (10U) |
#define | SRC_SRSR_TEMPSENSE_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M7_MASK) |
#define | SRC_SRSR_M4_REQUEST_M7_MASK (0x800U) |
#define | SRC_SRSR_M4_REQUEST_M7_SHIFT (11U) |
#define | SRC_SRSR_M4_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M7_SHIFT)) & SRC_SRSR_M4_REQUEST_M7_MASK) |
#define | SRC_SRSR_M4_LOCKUP_M7_MASK (0x1000U) |
#define | SRC_SRSR_M4_LOCKUP_M7_SHIFT (12U) |
#define | SRC_SRSR_M4_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M7_SHIFT)) & SRC_SRSR_M4_LOCKUP_M7_MASK) |
#define | SRC_SRSR_OVERVOLT_RST_M7_MASK (0x2000U) |
#define | SRC_SRSR_OVERVOLT_RST_M7_SHIFT (13U) |
#define | SRC_SRSR_OVERVOLT_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M7_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M7_MASK) |
#define | SRC_SRSR_CDOG_RST_M7_MASK (0x4000U) |
#define | SRC_SRSR_CDOG_RST_M7_SHIFT (14U) |
#define | SRC_SRSR_CDOG_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M7_SHIFT)) & SRC_SRSR_CDOG_RST_M7_MASK) |
#define | SRC_SRSR_IPP_RESET_B_M4_MASK (0x10000U) |
#define | SRC_SRSR_IPP_RESET_B_M4_SHIFT (16U) |
#define | SRC_SRSR_IPP_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_RESET_B_M4_MASK) |
#define | SRC_SRSR_M4_REQUEST_M4_MASK (0x20000U) |
#define | SRC_SRSR_M4_REQUEST_M4_SHIFT (17U) |
#define | SRC_SRSR_M4_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M4_SHIFT)) & SRC_SRSR_M4_REQUEST_M4_MASK) |
#define | SRC_SRSR_M4_LOCKUP_M4_MASK (0x40000U) |
#define | SRC_SRSR_M4_LOCKUP_M4_SHIFT (18U) |
#define | SRC_SRSR_M4_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M4_SHIFT)) & SRC_SRSR_M4_LOCKUP_M4_MASK) |
#define | SRC_SRSR_CSU_RESET_B_M4_MASK (0x80000U) |
#define | SRC_SRSR_CSU_RESET_B_M4_SHIFT (19U) |
#define | SRC_SRSR_CSU_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M4_SHIFT)) & SRC_SRSR_CSU_RESET_B_M4_MASK) |
#define | SRC_SRSR_IPP_USER_RESET_B_M4_MASK (0x100000U) |
#define | SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT (20U) |
#define | SRC_SRSR_IPP_USER_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M4_MASK) |
#define | SRC_SRSR_WDOG_RST_B_M4_MASK (0x200000U) |
#define | SRC_SRSR_WDOG_RST_B_M4_SHIFT (21U) |
#define | SRC_SRSR_WDOG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG_RST_B_M4_MASK) |
#define | SRC_SRSR_JTAG_RST_B_M4_MASK (0x400000U) |
#define | SRC_SRSR_JTAG_RST_B_M4_SHIFT (22U) |
#define | SRC_SRSR_JTAG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M4_SHIFT)) & SRC_SRSR_JTAG_RST_B_M4_MASK) |
#define | SRC_SRSR_JTAG_SW_RST_M4_MASK (0x800000U) |
#define | SRC_SRSR_JTAG_SW_RST_M4_SHIFT (23U) |
#define | SRC_SRSR_JTAG_SW_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M4_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M4_MASK) |
#define | SRC_SRSR_WDOG3_RST_B_M4_MASK (0x1000000U) |
#define | SRC_SRSR_WDOG3_RST_B_M4_SHIFT (24U) |
#define | SRC_SRSR_WDOG3_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M4_MASK) |
#define | SRC_SRSR_WDOG4_RST_B_M4_MASK (0x2000000U) |
#define | SRC_SRSR_WDOG4_RST_B_M4_SHIFT (25U) |
#define | SRC_SRSR_WDOG4_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M4_MASK) |
#define | SRC_SRSR_TEMPSENSE_RST_B_M4_MASK (0x4000000U) |
#define | SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT (26U) |
#define | SRC_SRSR_TEMPSENSE_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M4_MASK) |
#define | SRC_SRSR_M7_REQUEST_M4_MASK (0x8000000U) |
#define | SRC_SRSR_M7_REQUEST_M4_SHIFT (27U) |
#define | SRC_SRSR_M7_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M4_SHIFT)) & SRC_SRSR_M7_REQUEST_M4_MASK) |
#define | SRC_SRSR_M7_LOCKUP_M4_MASK (0x10000000U) |
#define | SRC_SRSR_M7_LOCKUP_M4_SHIFT (28U) |
#define | SRC_SRSR_M7_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M4_SHIFT)) & SRC_SRSR_M7_LOCKUP_M4_MASK) |
#define | SRC_SRSR_OVERVOLT_RST_M4_MASK (0x20000000U) |
#define | SRC_SRSR_OVERVOLT_RST_M4_SHIFT (29U) |
#define | SRC_SRSR_OVERVOLT_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M4_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M4_MASK) |
#define | SRC_SRSR_CDOG_RST_M4_MASK (0x40000000U) |
#define | SRC_SRSR_CDOG_RST_M4_SHIFT (30U) |
#define | SRC_SRSR_CDOG_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M4_SHIFT)) & SRC_SRSR_CDOG_RST_M4_MASK) |
GPR - SRC General Purpose Register | |
#define | SRC_GPR_GPR_MASK (0xFFFFFFFFU) |
#define | SRC_GPR_GPR_SHIFT (0U) |
#define | SRC_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_GPR_SHIFT)) & SRC_GPR_GPR_MASK) |
AUTHEN_MEGA - Slice Authentication Register | |
#define | SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK (0x1U) |
#define | SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT (0U) |
#define | SRC_AUTHEN_MEGA_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK) |
#define | SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK (0x2U) |
#define | SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT (1U) |
#define | SRC_AUTHEN_MEGA_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK) |
#define | SRC_AUTHEN_MEGA_LOCK_MODE_MASK (0x80U) |
#define | SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT (7U) |
#define | SRC_AUTHEN_MEGA_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_MODE_MASK) |
#define | SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK (0xF00U) |
#define | SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT (8U) |
#define | SRC_AUTHEN_MEGA_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK) |
#define | SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK (0x8000U) |
#define | SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT (15U) |
#define | SRC_AUTHEN_MEGA_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK) |
#define | SRC_AUTHEN_MEGA_WHITE_LIST_MASK (0xF0000U) |
#define | SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT (16U) |
#define | SRC_AUTHEN_MEGA_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT)) & SRC_AUTHEN_MEGA_WHITE_LIST_MASK) |
#define | SRC_AUTHEN_MEGA_LOCK_LIST_MASK (0x800000U) |
#define | SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT (23U) |
#define | SRC_AUTHEN_MEGA_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_LIST_MASK) |
#define | SRC_AUTHEN_MEGA_USER_MASK (0x1000000U) |
#define | SRC_AUTHEN_MEGA_USER_SHIFT (24U) |
#define | SRC_AUTHEN_MEGA_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_USER_SHIFT)) & SRC_AUTHEN_MEGA_USER_MASK) |
#define | SRC_AUTHEN_MEGA_NONSECURE_MASK (0x2000000U) |
#define | SRC_AUTHEN_MEGA_NONSECURE_SHIFT (25U) |
#define | SRC_AUTHEN_MEGA_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_NONSECURE_SHIFT)) & SRC_AUTHEN_MEGA_NONSECURE_MASK) |
#define | SRC_AUTHEN_MEGA_LOCK_SETTING_MASK (0x80000000U) |
#define | SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT (31U) |
#define | SRC_AUTHEN_MEGA_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_SETTING_MASK) |
CTRL_MEGA - Slice Control Register | |
#define | SRC_CTRL_MEGA_SW_RESET_MASK (0x1U) |
#define | SRC_CTRL_MEGA_SW_RESET_SHIFT (0U) |
#define | SRC_CTRL_MEGA_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_MEGA_SW_RESET_SHIFT)) & SRC_CTRL_MEGA_SW_RESET_MASK) |
SETPOINT_MEGA - Slice Setpoint Config Register | |
#define | SRC_SETPOINT_MEGA_SETPOINT0_MASK (0x1U) |
#define | SRC_SETPOINT_MEGA_SETPOINT0_SHIFT (0U) |
#define | SRC_SETPOINT_MEGA_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT0_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT0_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT1_MASK (0x2U) |
#define | SRC_SETPOINT_MEGA_SETPOINT1_SHIFT (1U) |
#define | SRC_SETPOINT_MEGA_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT1_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT1_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT2_MASK (0x4U) |
#define | SRC_SETPOINT_MEGA_SETPOINT2_SHIFT (2U) |
#define | SRC_SETPOINT_MEGA_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT2_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT2_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT3_MASK (0x8U) |
#define | SRC_SETPOINT_MEGA_SETPOINT3_SHIFT (3U) |
#define | SRC_SETPOINT_MEGA_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT3_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT3_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT4_MASK (0x10U) |
#define | SRC_SETPOINT_MEGA_SETPOINT4_SHIFT (4U) |
#define | SRC_SETPOINT_MEGA_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT4_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT4_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT5_MASK (0x20U) |
#define | SRC_SETPOINT_MEGA_SETPOINT5_SHIFT (5U) |
#define | SRC_SETPOINT_MEGA_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT5_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT5_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT6_MASK (0x40U) |
#define | SRC_SETPOINT_MEGA_SETPOINT6_SHIFT (6U) |
#define | SRC_SETPOINT_MEGA_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT6_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT6_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT7_MASK (0x80U) |
#define | SRC_SETPOINT_MEGA_SETPOINT7_SHIFT (7U) |
#define | SRC_SETPOINT_MEGA_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT7_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT7_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT8_MASK (0x100U) |
#define | SRC_SETPOINT_MEGA_SETPOINT8_SHIFT (8U) |
#define | SRC_SETPOINT_MEGA_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT8_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT8_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT9_MASK (0x200U) |
#define | SRC_SETPOINT_MEGA_SETPOINT9_SHIFT (9U) |
#define | SRC_SETPOINT_MEGA_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT9_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT9_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT10_MASK (0x400U) |
#define | SRC_SETPOINT_MEGA_SETPOINT10_SHIFT (10U) |
#define | SRC_SETPOINT_MEGA_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT10_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT10_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT11_MASK (0x800U) |
#define | SRC_SETPOINT_MEGA_SETPOINT11_SHIFT (11U) |
#define | SRC_SETPOINT_MEGA_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT11_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT11_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT12_MASK (0x1000U) |
#define | SRC_SETPOINT_MEGA_SETPOINT12_SHIFT (12U) |
#define | SRC_SETPOINT_MEGA_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT12_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT12_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT13_MASK (0x2000U) |
#define | SRC_SETPOINT_MEGA_SETPOINT13_SHIFT (13U) |
#define | SRC_SETPOINT_MEGA_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT13_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT13_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT14_MASK (0x4000U) |
#define | SRC_SETPOINT_MEGA_SETPOINT14_SHIFT (14U) |
#define | SRC_SETPOINT_MEGA_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT14_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT14_MASK) |
#define | SRC_SETPOINT_MEGA_SETPOINT15_MASK (0x8000U) |
#define | SRC_SETPOINT_MEGA_SETPOINT15_SHIFT (15U) |
#define | SRC_SETPOINT_MEGA_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT15_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT15_MASK) |
DOMAIN_MEGA - Slice Domain Config Register | |
#define | SRC_DOMAIN_MEGA_CPU0_RUN_MASK (0x1U) |
#define | SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT (0U) |
#define | SRC_DOMAIN_MEGA_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_RUN_MASK) |
#define | SRC_DOMAIN_MEGA_CPU0_WAIT_MASK (0x2U) |
#define | SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT (1U) |
#define | SRC_DOMAIN_MEGA_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_WAIT_MASK) |
#define | SRC_DOMAIN_MEGA_CPU0_STOP_MASK (0x4U) |
#define | SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT (2U) |
#define | SRC_DOMAIN_MEGA_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_STOP_MASK) |
#define | SRC_DOMAIN_MEGA_CPU0_SUSP_MASK (0x8U) |
#define | SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT (3U) |
#define | SRC_DOMAIN_MEGA_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_SUSP_MASK) |
#define | SRC_DOMAIN_MEGA_CPU1_RUN_MASK (0x10U) |
#define | SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT (4U) |
#define | SRC_DOMAIN_MEGA_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_RUN_MASK) |
#define | SRC_DOMAIN_MEGA_CPU1_WAIT_MASK (0x20U) |
#define | SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT (5U) |
#define | SRC_DOMAIN_MEGA_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_WAIT_MASK) |
#define | SRC_DOMAIN_MEGA_CPU1_STOP_MASK (0x40U) |
#define | SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT (6U) |
#define | SRC_DOMAIN_MEGA_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_STOP_MASK) |
#define | SRC_DOMAIN_MEGA_CPU1_SUSP_MASK (0x80U) |
#define | SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT (7U) |
#define | SRC_DOMAIN_MEGA_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_SUSP_MASK) |
STAT_MEGA - Slice Status Register | |
#define | SRC_STAT_MEGA_UNDER_RST_MASK (0x1U) |
#define | SRC_STAT_MEGA_UNDER_RST_SHIFT (0U) |
#define | SRC_STAT_MEGA_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_UNDER_RST_SHIFT)) & SRC_STAT_MEGA_UNDER_RST_MASK) |
#define | SRC_STAT_MEGA_RST_BY_HW_MASK (0x4U) |
#define | SRC_STAT_MEGA_RST_BY_HW_SHIFT (2U) |
#define | SRC_STAT_MEGA_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_HW_SHIFT)) & SRC_STAT_MEGA_RST_BY_HW_MASK) |
#define | SRC_STAT_MEGA_RST_BY_SW_MASK (0x8U) |
#define | SRC_STAT_MEGA_RST_BY_SW_SHIFT (3U) |
#define | SRC_STAT_MEGA_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_SW_SHIFT)) & SRC_STAT_MEGA_RST_BY_SW_MASK) |
AUTHEN_DISPLAY - Slice Authentication Register | |
#define | SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK (0x1U) |
#define | SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT (0U) |
#define | SRC_AUTHEN_DISPLAY_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK) |
#define | SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK (0x2U) |
#define | SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT (1U) |
#define | SRC_AUTHEN_DISPLAY_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK) |
#define | SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK (0x80U) |
#define | SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT (7U) |
#define | SRC_AUTHEN_DISPLAY_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK) |
#define | SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK (0xF00U) |
#define | SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT (8U) |
#define | SRC_AUTHEN_DISPLAY_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK) |
#define | SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK (0x8000U) |
#define | SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT (15U) |
#define | SRC_AUTHEN_DISPLAY_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK) |
#define | SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK (0xF0000U) |
#define | SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT (16U) |
#define | SRC_AUTHEN_DISPLAY_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK) |
#define | SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK (0x800000U) |
#define | SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT (23U) |
#define | SRC_AUTHEN_DISPLAY_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK) |
#define | SRC_AUTHEN_DISPLAY_USER_MASK (0x1000000U) |
#define | SRC_AUTHEN_DISPLAY_USER_SHIFT (24U) |
#define | SRC_AUTHEN_DISPLAY_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_USER_SHIFT)) & SRC_AUTHEN_DISPLAY_USER_MASK) |
#define | SRC_AUTHEN_DISPLAY_NONSECURE_MASK (0x2000000U) |
#define | SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT (25U) |
#define | SRC_AUTHEN_DISPLAY_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT)) & SRC_AUTHEN_DISPLAY_NONSECURE_MASK) |
#define | SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK (0x80000000U) |
#define | SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT (31U) |
#define | SRC_AUTHEN_DISPLAY_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK) |
CTRL_DISPLAY - Slice Control Register | |
#define | SRC_CTRL_DISPLAY_SW_RESET_MASK (0x1U) |
#define | SRC_CTRL_DISPLAY_SW_RESET_SHIFT (0U) |
#define | SRC_CTRL_DISPLAY_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_DISPLAY_SW_RESET_SHIFT)) & SRC_CTRL_DISPLAY_SW_RESET_MASK) |
SETPOINT_DISPLAY - Slice Setpoint Config Register | |
#define | SRC_SETPOINT_DISPLAY_SETPOINT0_MASK (0x1U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT (0U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT0_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT1_MASK (0x2U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT (1U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT1_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT2_MASK (0x4U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT (2U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT2_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT3_MASK (0x8U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT (3U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT3_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT4_MASK (0x10U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT (4U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT4_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT5_MASK (0x20U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT (5U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT5_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT6_MASK (0x40U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT (6U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT6_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT7_MASK (0x80U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT (7U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT7_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT8_MASK (0x100U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT (8U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT8_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT9_MASK (0x200U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT (9U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT9_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT10_MASK (0x400U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT (10U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT10_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT11_MASK (0x800U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT (11U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT11_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT12_MASK (0x1000U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT (12U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT12_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT13_MASK (0x2000U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT (13U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT13_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT14_MASK (0x4000U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT (14U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT14_MASK) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT15_MASK (0x8000U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT (15U) |
#define | SRC_SETPOINT_DISPLAY_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT15_MASK) |
DOMAIN_DISPLAY - Slice Domain Config Register | |
#define | SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK (0x1U) |
#define | SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT (0U) |
#define | SRC_DOMAIN_DISPLAY_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK) |
#define | SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK (0x2U) |
#define | SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT (1U) |
#define | SRC_DOMAIN_DISPLAY_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK) |
#define | SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK (0x4U) |
#define | SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT (2U) |
#define | SRC_DOMAIN_DISPLAY_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK) |
#define | SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK (0x8U) |
#define | SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT (3U) |
#define | SRC_DOMAIN_DISPLAY_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK) |
#define | SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK (0x10U) |
#define | SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT (4U) |
#define | SRC_DOMAIN_DISPLAY_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK) |
#define | SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK (0x20U) |
#define | SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT (5U) |
#define | SRC_DOMAIN_DISPLAY_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK) |
#define | SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK (0x40U) |
#define | SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT (6U) |
#define | SRC_DOMAIN_DISPLAY_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK) |
#define | SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK (0x80U) |
#define | SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT (7U) |
#define | SRC_DOMAIN_DISPLAY_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK) |
STAT_DISPLAY - Slice Status Register | |
#define | SRC_STAT_DISPLAY_UNDER_RST_MASK (0x1U) |
#define | SRC_STAT_DISPLAY_UNDER_RST_SHIFT (0U) |
#define | SRC_STAT_DISPLAY_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_UNDER_RST_SHIFT)) & SRC_STAT_DISPLAY_UNDER_RST_MASK) |
#define | SRC_STAT_DISPLAY_RST_BY_HW_MASK (0x4U) |
#define | SRC_STAT_DISPLAY_RST_BY_HW_SHIFT (2U) |
#define | SRC_STAT_DISPLAY_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_HW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_HW_MASK) |
#define | SRC_STAT_DISPLAY_RST_BY_SW_MASK (0x8U) |
#define | SRC_STAT_DISPLAY_RST_BY_SW_SHIFT (3U) |
#define | SRC_STAT_DISPLAY_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_SW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_SW_MASK) |
AUTHEN_WAKEUP - Slice Authentication Register | |
#define | SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK (0x1U) |
#define | SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT (0U) |
#define | SRC_AUTHEN_WAKEUP_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK) |
#define | SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK (0x2U) |
#define | SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT (1U) |
#define | SRC_AUTHEN_WAKEUP_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK) |
#define | SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK (0x80U) |
#define | SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT (7U) |
#define | SRC_AUTHEN_WAKEUP_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK) |
#define | SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK (0xF00U) |
#define | SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT (8U) |
#define | SRC_AUTHEN_WAKEUP_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK) |
#define | SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK (0x8000U) |
#define | SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT (15U) |
#define | SRC_AUTHEN_WAKEUP_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK) |
#define | SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK (0xF0000U) |
#define | SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT (16U) |
#define | SRC_AUTHEN_WAKEUP_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK) |
#define | SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK (0x800000U) |
#define | SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT (23U) |
#define | SRC_AUTHEN_WAKEUP_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK) |
#define | SRC_AUTHEN_WAKEUP_USER_MASK (0x1000000U) |
#define | SRC_AUTHEN_WAKEUP_USER_SHIFT (24U) |
#define | SRC_AUTHEN_WAKEUP_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_USER_SHIFT)) & SRC_AUTHEN_WAKEUP_USER_MASK) |
#define | SRC_AUTHEN_WAKEUP_NONSECURE_MASK (0x2000000U) |
#define | SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT (25U) |
#define | SRC_AUTHEN_WAKEUP_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT)) & SRC_AUTHEN_WAKEUP_NONSECURE_MASK) |
#define | SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK (0x80000000U) |
#define | SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT (31U) |
#define | SRC_AUTHEN_WAKEUP_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK) |
CTRL_WAKEUP - Slice Control Register | |
#define | SRC_CTRL_WAKEUP_SW_RESET_MASK (0x1U) |
#define | SRC_CTRL_WAKEUP_SW_RESET_SHIFT (0U) |
#define | SRC_CTRL_WAKEUP_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_WAKEUP_SW_RESET_SHIFT)) & SRC_CTRL_WAKEUP_SW_RESET_MASK) |
SETPOINT_WAKEUP - Slice Setpoint Config Register | |
#define | SRC_SETPOINT_WAKEUP_SETPOINT0_MASK (0x1U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT (0U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT0_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT1_MASK (0x2U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT (1U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT1_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT2_MASK (0x4U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT (2U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT2_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT3_MASK (0x8U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT (3U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT3_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT4_MASK (0x10U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT (4U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT4_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT5_MASK (0x20U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT (5U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT5_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT6_MASK (0x40U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT (6U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT6_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT7_MASK (0x80U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT (7U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT7_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT8_MASK (0x100U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT (8U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT8_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT9_MASK (0x200U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT (9U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT9_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT10_MASK (0x400U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT (10U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT10_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT11_MASK (0x800U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT (11U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT11_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT12_MASK (0x1000U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT (12U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT12_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT13_MASK (0x2000U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT (13U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT13_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT14_MASK (0x4000U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT (14U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT14_MASK) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT15_MASK (0x8000U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT (15U) |
#define | SRC_SETPOINT_WAKEUP_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT15_MASK) |
DOMAIN_WAKEUP - Slice Domain Config Register | |
#define | SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK (0x1U) |
#define | SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT (0U) |
#define | SRC_DOMAIN_WAKEUP_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK) |
#define | SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK (0x2U) |
#define | SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT (1U) |
#define | SRC_DOMAIN_WAKEUP_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK) |
#define | SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK (0x4U) |
#define | SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT (2U) |
#define | SRC_DOMAIN_WAKEUP_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK) |
#define | SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK (0x8U) |
#define | SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT (3U) |
#define | SRC_DOMAIN_WAKEUP_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK) |
#define | SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK (0x10U) |
#define | SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT (4U) |
#define | SRC_DOMAIN_WAKEUP_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK) |
#define | SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK (0x20U) |
#define | SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT (5U) |
#define | SRC_DOMAIN_WAKEUP_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK) |
#define | SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK (0x40U) |
#define | SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT (6U) |
#define | SRC_DOMAIN_WAKEUP_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK) |
#define | SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK (0x80U) |
#define | SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT (7U) |
#define | SRC_DOMAIN_WAKEUP_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK) |
STAT_WAKEUP - Slice Status Register | |
#define | SRC_STAT_WAKEUP_UNDER_RST_MASK (0x1U) |
#define | SRC_STAT_WAKEUP_UNDER_RST_SHIFT (0U) |
#define | SRC_STAT_WAKEUP_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_UNDER_RST_SHIFT)) & SRC_STAT_WAKEUP_UNDER_RST_MASK) |
#define | SRC_STAT_WAKEUP_RST_BY_HW_MASK (0x4U) |
#define | SRC_STAT_WAKEUP_RST_BY_HW_SHIFT (2U) |
#define | SRC_STAT_WAKEUP_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_HW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_HW_MASK) |
#define | SRC_STAT_WAKEUP_RST_BY_SW_MASK (0x8U) |
#define | SRC_STAT_WAKEUP_RST_BY_SW_SHIFT (3U) |
#define | SRC_STAT_WAKEUP_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_SW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_SW_MASK) |
AUTHEN_M4CORE - Slice Authentication Register | |
#define | SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK (0x1U) |
#define | SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT (0U) |
#define | SRC_AUTHEN_M4CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK) |
#define | SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK (0x2U) |
#define | SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT (1U) |
#define | SRC_AUTHEN_M4CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK) |
#define | SRC_AUTHEN_M4CORE_LOCK_MODE_MASK (0x80U) |
#define | SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT (7U) |
#define | SRC_AUTHEN_M4CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_MODE_MASK) |
#define | SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK (0xF00U) |
#define | SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT (8U) |
#define | SRC_AUTHEN_M4CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK) |
#define | SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK (0x8000U) |
#define | SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT (15U) |
#define | SRC_AUTHEN_M4CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK) |
#define | SRC_AUTHEN_M4CORE_WHITE_LIST_MASK (0xF0000U) |
#define | SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT (16U) |
#define | SRC_AUTHEN_M4CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_WHITE_LIST_MASK) |
#define | SRC_AUTHEN_M4CORE_LOCK_LIST_MASK (0x800000U) |
#define | SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT (23U) |
#define | SRC_AUTHEN_M4CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_LIST_MASK) |
#define | SRC_AUTHEN_M4CORE_USER_MASK (0x1000000U) |
#define | SRC_AUTHEN_M4CORE_USER_SHIFT (24U) |
#define | SRC_AUTHEN_M4CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_USER_SHIFT)) & SRC_AUTHEN_M4CORE_USER_MASK) |
#define | SRC_AUTHEN_M4CORE_NONSECURE_MASK (0x2000000U) |
#define | SRC_AUTHEN_M4CORE_NONSECURE_SHIFT (25U) |
#define | SRC_AUTHEN_M4CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M4CORE_NONSECURE_MASK) |
#define | SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK (0x80000000U) |
#define | SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT (31U) |
#define | SRC_AUTHEN_M4CORE_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK) |
CTRL_M4CORE - Slice Control Register | |
#define | SRC_CTRL_M4CORE_SW_RESET_MASK (0x1U) |
#define | SRC_CTRL_M4CORE_SW_RESET_SHIFT (0U) |
#define | SRC_CTRL_M4CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4CORE_SW_RESET_SHIFT)) & SRC_CTRL_M4CORE_SW_RESET_MASK) |
SETPOINT_M4CORE - Slice Setpoint Config Register | |
#define | SRC_SETPOINT_M4CORE_SETPOINT0_MASK (0x1U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT (0U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT0_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT1_MASK (0x2U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT (1U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT1_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT2_MASK (0x4U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT (2U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT2_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT3_MASK (0x8U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT (3U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT3_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT4_MASK (0x10U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT (4U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT4_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT5_MASK (0x20U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT (5U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT5_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT6_MASK (0x40U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT (6U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT6_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT7_MASK (0x80U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT (7U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT7_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT8_MASK (0x100U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT (8U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT8_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT9_MASK (0x200U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT (9U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT9_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT10_MASK (0x400U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT (10U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT10_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT11_MASK (0x800U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT (11U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT11_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT12_MASK (0x1000U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT (12U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT12_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT13_MASK (0x2000U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT (13U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT13_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT14_MASK (0x4000U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT (14U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT14_MASK) |
#define | SRC_SETPOINT_M4CORE_SETPOINT15_MASK (0x8000U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT (15U) |
#define | SRC_SETPOINT_M4CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT15_MASK) |
DOMAIN_M4CORE - Slice Domain Config Register | |
#define | SRC_DOMAIN_M4CORE_CPU0_RUN_MASK (0x1U) |
#define | SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT (0U) |
#define | SRC_DOMAIN_M4CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_RUN_MASK) |
#define | SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK (0x2U) |
#define | SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT (1U) |
#define | SRC_DOMAIN_M4CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK) |
#define | SRC_DOMAIN_M4CORE_CPU0_STOP_MASK (0x4U) |
#define | SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT (2U) |
#define | SRC_DOMAIN_M4CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_STOP_MASK) |
#define | SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK (0x8U) |
#define | SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT (3U) |
#define | SRC_DOMAIN_M4CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK) |
#define | SRC_DOMAIN_M4CORE_CPU1_RUN_MASK (0x10U) |
#define | SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT (4U) |
#define | SRC_DOMAIN_M4CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_RUN_MASK) |
#define | SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK (0x20U) |
#define | SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT (5U) |
#define | SRC_DOMAIN_M4CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK) |
#define | SRC_DOMAIN_M4CORE_CPU1_STOP_MASK (0x40U) |
#define | SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT (6U) |
#define | SRC_DOMAIN_M4CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_STOP_MASK) |
#define | SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK (0x80U) |
#define | SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT (7U) |
#define | SRC_DOMAIN_M4CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK) |
STAT_M4CORE - Slice Status Register | |
#define | SRC_STAT_M4CORE_UNDER_RST_MASK (0x1U) |
#define | SRC_STAT_M4CORE_UNDER_RST_SHIFT (0U) |
#define | SRC_STAT_M4CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_UNDER_RST_SHIFT)) & SRC_STAT_M4CORE_UNDER_RST_MASK) |
#define | SRC_STAT_M4CORE_RST_BY_HW_MASK (0x4U) |
#define | SRC_STAT_M4CORE_RST_BY_HW_SHIFT (2U) |
#define | SRC_STAT_M4CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_HW_MASK) |
#define | SRC_STAT_M4CORE_RST_BY_SW_MASK (0x8U) |
#define | SRC_STAT_M4CORE_RST_BY_SW_SHIFT (3U) |
#define | SRC_STAT_M4CORE_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_SW_MASK) |
AUTHEN_M7CORE - Slice Authentication Register | |
#define | SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK (0x1U) |
#define | SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT (0U) |
#define | SRC_AUTHEN_M7CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK) |
#define | SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK (0x2U) |
#define | SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT (1U) |
#define | SRC_AUTHEN_M7CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK) |
#define | SRC_AUTHEN_M7CORE_LOCK_MODE_MASK (0x80U) |
#define | SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT (7U) |
#define | SRC_AUTHEN_M7CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_MODE_MASK) |
#define | SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK (0xF00U) |
#define | SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT (8U) |
#define | SRC_AUTHEN_M7CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK) |
#define | SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK (0x8000U) |
#define | SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT (15U) |
#define | SRC_AUTHEN_M7CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK) |
#define | SRC_AUTHEN_M7CORE_WHITE_LIST_MASK (0xF0000U) |
#define | SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT (16U) |
#define | SRC_AUTHEN_M7CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_WHITE_LIST_MASK) |
#define | SRC_AUTHEN_M7CORE_LOCK_LIST_MASK (0x800000U) |
#define | SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT (23U) |
#define | SRC_AUTHEN_M7CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_LIST_MASK) |
#define | SRC_AUTHEN_M7CORE_USER_MASK (0x1000000U) |
#define | SRC_AUTHEN_M7CORE_USER_SHIFT (24U) |
#define | SRC_AUTHEN_M7CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_USER_SHIFT)) & SRC_AUTHEN_M7CORE_USER_MASK) |
#define | SRC_AUTHEN_M7CORE_NONSECURE_MASK (0x2000000U) |
#define | SRC_AUTHEN_M7CORE_NONSECURE_SHIFT (25U) |
#define | SRC_AUTHEN_M7CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M7CORE_NONSECURE_MASK) |
#define | SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK (0x80000000U) |
#define | SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT (31U) |
#define | SRC_AUTHEN_M7CORE_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK) |
CTRL_M7CORE - Slice Control Register | |
#define | SRC_CTRL_M7CORE_SW_RESET_MASK (0x1U) |
#define | SRC_CTRL_M7CORE_SW_RESET_SHIFT (0U) |
#define | SRC_CTRL_M7CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7CORE_SW_RESET_SHIFT)) & SRC_CTRL_M7CORE_SW_RESET_MASK) |
SETPOINT_M7CORE - Slice Setpoint Config Register | |
#define | SRC_SETPOINT_M7CORE_SETPOINT0_MASK (0x1U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT (0U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT0_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT1_MASK (0x2U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT (1U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT1_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT2_MASK (0x4U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT (2U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT2_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT3_MASK (0x8U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT (3U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT3_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT4_MASK (0x10U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT (4U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT4_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT5_MASK (0x20U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT (5U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT5_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT6_MASK (0x40U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT (6U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT6_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT7_MASK (0x80U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT (7U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT7_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT8_MASK (0x100U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT (8U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT8_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT9_MASK (0x200U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT (9U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT9_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT10_MASK (0x400U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT (10U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT10_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT11_MASK (0x800U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT (11U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT11_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT12_MASK (0x1000U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT (12U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT12_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT13_MASK (0x2000U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT (13U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT13_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT14_MASK (0x4000U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT (14U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT14_MASK) |
#define | SRC_SETPOINT_M7CORE_SETPOINT15_MASK (0x8000U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT (15U) |
#define | SRC_SETPOINT_M7CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT15_MASK) |
DOMAIN_M7CORE - Slice Domain Config Register | |
#define | SRC_DOMAIN_M7CORE_CPU0_RUN_MASK (0x1U) |
#define | SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT (0U) |
#define | SRC_DOMAIN_M7CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_RUN_MASK) |
#define | SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK (0x2U) |
#define | SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT (1U) |
#define | SRC_DOMAIN_M7CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK) |
#define | SRC_DOMAIN_M7CORE_CPU0_STOP_MASK (0x4U) |
#define | SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT (2U) |
#define | SRC_DOMAIN_M7CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_STOP_MASK) |
#define | SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK (0x8U) |
#define | SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT (3U) |
#define | SRC_DOMAIN_M7CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK) |
#define | SRC_DOMAIN_M7CORE_CPU1_RUN_MASK (0x10U) |
#define | SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT (4U) |
#define | SRC_DOMAIN_M7CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_RUN_MASK) |
#define | SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK (0x20U) |
#define | SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT (5U) |
#define | SRC_DOMAIN_M7CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK) |
#define | SRC_DOMAIN_M7CORE_CPU1_STOP_MASK (0x40U) |
#define | SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT (6U) |
#define | SRC_DOMAIN_M7CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_STOP_MASK) |
#define | SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK (0x80U) |
#define | SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT (7U) |
#define | SRC_DOMAIN_M7CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK) |
STAT_M7CORE - Slice Status Register | |
#define | SRC_STAT_M7CORE_UNDER_RST_MASK (0x1U) |
#define | SRC_STAT_M7CORE_UNDER_RST_SHIFT (0U) |
#define | SRC_STAT_M7CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_UNDER_RST_SHIFT)) & SRC_STAT_M7CORE_UNDER_RST_MASK) |
#define | SRC_STAT_M7CORE_RST_BY_HW_MASK (0x4U) |
#define | SRC_STAT_M7CORE_RST_BY_HW_SHIFT (2U) |
#define | SRC_STAT_M7CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_HW_MASK) |
#define | SRC_STAT_M7CORE_RST_BY_SW_MASK (0x8U) |
#define | SRC_STAT_M7CORE_RST_BY_SW_SHIFT (3U) |
#define | SRC_STAT_M7CORE_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_SW_MASK) |
AUTHEN_M4DEBUG - Slice Authentication Register | |
#define | SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK (0x1U) |
#define | SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT (0U) |
#define | SRC_AUTHEN_M4DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK) |
#define | SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK (0x2U) |
#define | SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT (1U) |
#define | SRC_AUTHEN_M4DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK (0x80U) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT (7U) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK) |
#define | SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK (0xF00U) |
#define | SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT (8U) |
#define | SRC_AUTHEN_M4DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK (0x8000U) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT (15U) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK) |
#define | SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK (0xF0000U) |
#define | SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT (16U) |
#define | SRC_AUTHEN_M4DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK (0x800000U) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT (23U) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK) |
#define | SRC_AUTHEN_M4DEBUG_USER_MASK (0x1000000U) |
#define | SRC_AUTHEN_M4DEBUG_USER_SHIFT (24U) |
#define | SRC_AUTHEN_M4DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_USER_SHIFT)) & SRC_AUTHEN_M4DEBUG_USER_MASK) |
#define | SRC_AUTHEN_M4DEBUG_NONSECURE_MASK (0x2000000U) |
#define | SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT (25U) |
#define | SRC_AUTHEN_M4DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M4DEBUG_NONSECURE_MASK) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK (0x80000000U) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT (31U) |
#define | SRC_AUTHEN_M4DEBUG_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK) |
CTRL_M4DEBUG - Slice Control Register | |
#define | SRC_CTRL_M4DEBUG_SW_RESET_MASK (0x1U) |
#define | SRC_CTRL_M4DEBUG_SW_RESET_SHIFT (0U) |
#define | SRC_CTRL_M4DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M4DEBUG_SW_RESET_MASK) |
SETPOINT_M4DEBUG - Slice Setpoint Config Register | |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK (0x1U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT (0U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK (0x2U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT (1U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK (0x4U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT (2U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK (0x8U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT (3U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK (0x10U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT (4U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK (0x20U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT (5U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK (0x40U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT (6U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK (0x80U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT (7U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK (0x100U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT (8U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK (0x200U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT (9U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK (0x400U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT (10U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK (0x800U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT (11U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK (0x1000U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT (12U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK (0x2000U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT (13U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK (0x4000U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT (14U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK (0x8000U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT (15U) |
#define | SRC_SETPOINT_M4DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK) |
DOMAIN_M4DEBUG - Slice Domain Config Register | |
#define | SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK (0x1U) |
#define | SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT (0U) |
#define | SRC_DOMAIN_M4DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK) |
#define | SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK (0x2U) |
#define | SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT (1U) |
#define | SRC_DOMAIN_M4DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK) |
#define | SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK (0x4U) |
#define | SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT (2U) |
#define | SRC_DOMAIN_M4DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK) |
#define | SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK (0x8U) |
#define | SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT (3U) |
#define | SRC_DOMAIN_M4DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK (0x10U) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT (4U) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK (0x20U) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT (5U) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK (0x40U) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT (6U) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK (0x80U) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT (7U) |
#define | SRC_DOMAIN_M4DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK) |
STAT_M4DEBUG - Slice Status Register | |
#define | SRC_STAT_M4DEBUG_UNDER_RST_MASK (0x1U) |
#define | SRC_STAT_M4DEBUG_UNDER_RST_SHIFT (0U) |
#define | SRC_STAT_M4DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M4DEBUG_UNDER_RST_MASK) |
#define | SRC_STAT_M4DEBUG_RST_BY_HW_MASK (0x4U) |
#define | SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT (2U) |
#define | SRC_STAT_M4DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_HW_MASK) |
#define | SRC_STAT_M4DEBUG_RST_BY_SW_MASK (0x8U) |
#define | SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT (3U) |
#define | SRC_STAT_M4DEBUG_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_SW_MASK) |
AUTHEN_M7DEBUG - Slice Authentication Register | |
#define | SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK (0x1U) |
#define | SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT (0U) |
#define | SRC_AUTHEN_M7DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK) |
#define | SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK (0x2U) |
#define | SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT (1U) |
#define | SRC_AUTHEN_M7DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK (0x80U) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT (7U) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK) |
#define | SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK (0xF00U) |
#define | SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT (8U) |
#define | SRC_AUTHEN_M7DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK (0x8000U) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT (15U) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK) |
#define | SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK (0xF0000U) |
#define | SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT (16U) |
#define | SRC_AUTHEN_M7DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK (0x800000U) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT (23U) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK) |
#define | SRC_AUTHEN_M7DEBUG_USER_MASK (0x1000000U) |
#define | SRC_AUTHEN_M7DEBUG_USER_SHIFT (24U) |
#define | SRC_AUTHEN_M7DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_USER_SHIFT)) & SRC_AUTHEN_M7DEBUG_USER_MASK) |
#define | SRC_AUTHEN_M7DEBUG_NONSECURE_MASK (0x2000000U) |
#define | SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT (25U) |
#define | SRC_AUTHEN_M7DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M7DEBUG_NONSECURE_MASK) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK (0x80000000U) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT (31U) |
#define | SRC_AUTHEN_M7DEBUG_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK) |
CTRL_M7DEBUG - Slice Control Register | |
#define | SRC_CTRL_M7DEBUG_SW_RESET_MASK (0x1U) |
#define | SRC_CTRL_M7DEBUG_SW_RESET_SHIFT (0U) |
#define | SRC_CTRL_M7DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M7DEBUG_SW_RESET_MASK) |
SETPOINT_M7DEBUG - Slice Setpoint Config Register | |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK (0x1U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT (0U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK (0x2U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT (1U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK (0x4U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT (2U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK (0x8U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT (3U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK (0x10U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT (4U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK (0x20U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT (5U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK (0x40U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT (6U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK (0x80U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT (7U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK (0x100U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT (8U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK (0x200U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT (9U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK (0x400U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT (10U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK (0x800U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT (11U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK (0x1000U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT (12U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK (0x2000U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT (13U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK (0x4000U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT (14U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK (0x8000U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT (15U) |
#define | SRC_SETPOINT_M7DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK) |
DOMAIN_M7DEBUG - Slice Domain Config Register | |
#define | SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK (0x1U) |
#define | SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT (0U) |
#define | SRC_DOMAIN_M7DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK) |
#define | SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK (0x2U) |
#define | SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT (1U) |
#define | SRC_DOMAIN_M7DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK) |
#define | SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK (0x4U) |
#define | SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT (2U) |
#define | SRC_DOMAIN_M7DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK) |
#define | SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK (0x8U) |
#define | SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT (3U) |
#define | SRC_DOMAIN_M7DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK (0x10U) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT (4U) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK (0x20U) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT (5U) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK (0x40U) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT (6U) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK (0x80U) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT (7U) |
#define | SRC_DOMAIN_M7DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK) |
STAT_M7DEBUG - Slice Status Register | |
#define | SRC_STAT_M7DEBUG_UNDER_RST_MASK (0x1U) |
#define | SRC_STAT_M7DEBUG_UNDER_RST_SHIFT (0U) |
#define | SRC_STAT_M7DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M7DEBUG_UNDER_RST_MASK) |
#define | SRC_STAT_M7DEBUG_RST_BY_HW_MASK (0x4U) |
#define | SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT (2U) |
#define | SRC_STAT_M7DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_HW_MASK) |
#define | SRC_STAT_M7DEBUG_RST_BY_SW_MASK (0x8U) |
#define | SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT (3U) |
#define | SRC_STAT_M7DEBUG_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_SW_MASK) |
AUTHEN_USBPHY1 - Slice Authentication Register | |
#define | SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK (0x1U) |
#define | SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT (0U) |
#define | SRC_AUTHEN_USBPHY1_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK) |
#define | SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK (0x2U) |
#define | SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT (1U) |
#define | SRC_AUTHEN_USBPHY1_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK) |
#define | SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK (0x80U) |
#define | SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT (7U) |
#define | SRC_AUTHEN_USBPHY1_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK) |
#define | SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK (0xF00U) |
#define | SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT (8U) |
#define | SRC_AUTHEN_USBPHY1_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK) |
#define | SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK (0x8000U) |
#define | SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT (15U) |
#define | SRC_AUTHEN_USBPHY1_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK) |
#define | SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK (0xF0000U) |
#define | SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT (16U) |
#define | SRC_AUTHEN_USBPHY1_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK) |
#define | SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK (0x800000U) |
#define | SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT (23U) |
#define | SRC_AUTHEN_USBPHY1_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK) |
#define | SRC_AUTHEN_USBPHY1_USER_MASK (0x1000000U) |
#define | SRC_AUTHEN_USBPHY1_USER_SHIFT (24U) |
#define | SRC_AUTHEN_USBPHY1_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_USER_SHIFT)) & SRC_AUTHEN_USBPHY1_USER_MASK) |
#define | SRC_AUTHEN_USBPHY1_NONSECURE_MASK (0x2000000U) |
#define | SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT (25U) |
#define | SRC_AUTHEN_USBPHY1_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY1_NONSECURE_MASK) |
#define | SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK (0x80000000U) |
#define | SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT (31U) |
#define | SRC_AUTHEN_USBPHY1_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK) |
CTRL_USBPHY1 - Slice Control Register | |
#define | SRC_CTRL_USBPHY1_SW_RESET_MASK (0x1U) |
#define | SRC_CTRL_USBPHY1_SW_RESET_SHIFT (0U) |
#define | SRC_CTRL_USBPHY1_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY1_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY1_SW_RESET_MASK) |
SETPOINT_USBPHY1 - Slice Setpoint Config Register | |
#define | SRC_SETPOINT_USBPHY1_SETPOINT0_MASK (0x1U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT (0U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT0_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT1_MASK (0x2U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT (1U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT1_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT2_MASK (0x4U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT (2U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT2_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT3_MASK (0x8U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT (3U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT3_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT4_MASK (0x10U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT (4U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT4_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT5_MASK (0x20U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT (5U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT5_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT6_MASK (0x40U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT (6U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT6_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT7_MASK (0x80U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT (7U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT7_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT8_MASK (0x100U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT (8U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT8_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT9_MASK (0x200U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT (9U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT9_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT10_MASK (0x400U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT (10U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT10_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT11_MASK (0x800U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT (11U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT11_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT12_MASK (0x1000U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT (12U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT12_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT13_MASK (0x2000U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT (13U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT13_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT14_MASK (0x4000U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT (14U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT14_MASK) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT15_MASK (0x8000U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT (15U) |
#define | SRC_SETPOINT_USBPHY1_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT15_MASK) |
DOMAIN_USBPHY1 - Slice Domain Config Register | |
#define | SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK (0x1U) |
#define | SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT (0U) |
#define | SRC_DOMAIN_USBPHY1_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK) |
#define | SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK (0x2U) |
#define | SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT (1U) |
#define | SRC_DOMAIN_USBPHY1_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK) |
#define | SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK (0x4U) |
#define | SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT (2U) |
#define | SRC_DOMAIN_USBPHY1_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK) |
#define | SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK (0x8U) |
#define | SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT (3U) |
#define | SRC_DOMAIN_USBPHY1_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK) |
#define | SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK (0x10U) |
#define | SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT (4U) |
#define | SRC_DOMAIN_USBPHY1_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK) |
#define | SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK (0x20U) |
#define | SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT (5U) |
#define | SRC_DOMAIN_USBPHY1_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK) |
#define | SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK (0x40U) |
#define | SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT (6U) |
#define | SRC_DOMAIN_USBPHY1_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK) |
#define | SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK (0x80U) |
#define | SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT (7U) |
#define | SRC_DOMAIN_USBPHY1_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK) |
STAT_USBPHY1 - Slice Status Register | |
#define | SRC_STAT_USBPHY1_UNDER_RST_MASK (0x1U) |
#define | SRC_STAT_USBPHY1_UNDER_RST_SHIFT (0U) |
#define | SRC_STAT_USBPHY1_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY1_UNDER_RST_MASK) |
#define | SRC_STAT_USBPHY1_RST_BY_HW_MASK (0x4U) |
#define | SRC_STAT_USBPHY1_RST_BY_HW_SHIFT (2U) |
#define | SRC_STAT_USBPHY1_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_HW_MASK) |
#define | SRC_STAT_USBPHY1_RST_BY_SW_MASK (0x8U) |
#define | SRC_STAT_USBPHY1_RST_BY_SW_SHIFT (3U) |
#define | SRC_STAT_USBPHY1_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_SW_MASK) |
AUTHEN_USBPHY2 - Slice Authentication Register | |
#define | SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK (0x1U) |
#define | SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT (0U) |
#define | SRC_AUTHEN_USBPHY2_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK) |
#define | SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK (0x2U) |
#define | SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT (1U) |
#define | SRC_AUTHEN_USBPHY2_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK) |
#define | SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK (0x80U) |
#define | SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT (7U) |
#define | SRC_AUTHEN_USBPHY2_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK) |
#define | SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK (0xF00U) |
#define | SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT (8U) |
#define | SRC_AUTHEN_USBPHY2_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK) |
#define | SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK (0x8000U) |
#define | SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT (15U) |
#define | SRC_AUTHEN_USBPHY2_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK) |
#define | SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK (0xF0000U) |
#define | SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT (16U) |
#define | SRC_AUTHEN_USBPHY2_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK) |
#define | SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK (0x800000U) |
#define | SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT (23U) |
#define | SRC_AUTHEN_USBPHY2_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK) |
#define | SRC_AUTHEN_USBPHY2_USER_MASK (0x1000000U) |
#define | SRC_AUTHEN_USBPHY2_USER_SHIFT (24U) |
#define | SRC_AUTHEN_USBPHY2_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_USER_SHIFT)) & SRC_AUTHEN_USBPHY2_USER_MASK) |
#define | SRC_AUTHEN_USBPHY2_NONSECURE_MASK (0x2000000U) |
#define | SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT (25U) |
#define | SRC_AUTHEN_USBPHY2_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY2_NONSECURE_MASK) |
#define | SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK (0x80000000U) |
#define | SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT (31U) |
#define | SRC_AUTHEN_USBPHY2_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK) |
CTRL_USBPHY2 - Slice Control Register | |
#define | SRC_CTRL_USBPHY2_SW_RESET_MASK (0x1U) |
#define | SRC_CTRL_USBPHY2_SW_RESET_SHIFT (0U) |
#define | SRC_CTRL_USBPHY2_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY2_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY2_SW_RESET_MASK) |
SETPOINT_USBPHY2 - Slice Setpoint Config Register | |
#define | SRC_SETPOINT_USBPHY2_SETPOINT0_MASK (0x1U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT (0U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT0_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT1_MASK (0x2U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT (1U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT1_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT2_MASK (0x4U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT (2U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT2_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT3_MASK (0x8U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT (3U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT3_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT4_MASK (0x10U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT (4U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT4_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT5_MASK (0x20U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT (5U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT5_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT6_MASK (0x40U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT (6U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT6_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT7_MASK (0x80U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT (7U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT7_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT8_MASK (0x100U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT (8U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT8_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT9_MASK (0x200U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT (9U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT9_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT10_MASK (0x400U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT (10U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT10_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT11_MASK (0x800U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT (11U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT11_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT12_MASK (0x1000U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT (12U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT12_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT13_MASK (0x2000U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT (13U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT13_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT14_MASK (0x4000U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT (14U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT14_MASK) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT15_MASK (0x8000U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT (15U) |
#define | SRC_SETPOINT_USBPHY2_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT15_MASK) |
DOMAIN_USBPHY2 - Slice Domain Config Register | |
#define | SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK (0x1U) |
#define | SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT (0U) |
#define | SRC_DOMAIN_USBPHY2_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK) |
#define | SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK (0x2U) |
#define | SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT (1U) |
#define | SRC_DOMAIN_USBPHY2_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK) |
#define | SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK (0x4U) |
#define | SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT (2U) |
#define | SRC_DOMAIN_USBPHY2_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK) |
#define | SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK (0x8U) |
#define | SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT (3U) |
#define | SRC_DOMAIN_USBPHY2_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK) |
#define | SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK (0x10U) |
#define | SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT (4U) |
#define | SRC_DOMAIN_USBPHY2_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK) |
#define | SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK (0x20U) |
#define | SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT (5U) |
#define | SRC_DOMAIN_USBPHY2_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK) |
#define | SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK (0x40U) |
#define | SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT (6U) |
#define | SRC_DOMAIN_USBPHY2_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK) |
#define | SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK (0x80U) |
#define | SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT (7U) |
#define | SRC_DOMAIN_USBPHY2_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK) |
STAT_USBPHY2 - Slice Status Register | |
#define | SRC_STAT_USBPHY2_UNDER_RST_MASK (0x1U) |
#define | SRC_STAT_USBPHY2_UNDER_RST_SHIFT (0U) |
#define | SRC_STAT_USBPHY2_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY2_UNDER_RST_MASK) |
#define | SRC_STAT_USBPHY2_RST_BY_HW_MASK (0x4U) |
#define | SRC_STAT_USBPHY2_RST_BY_HW_SHIFT (2U) |
#define | SRC_STAT_USBPHY2_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_HW_MASK) |
#define | SRC_STAT_USBPHY2_RST_BY_SW_MASK (0x8U) |
#define | SRC_STAT_USBPHY2_RST_BY_SW_SHIFT (3U) |
#define | SRC_STAT_USBPHY2_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_SW_MASK) |
SRAM0 - Description Address Register | |
#define | SSARC_HP_SRAM0_ADDR_MASK (0xFFFFFFFFU) |
#define | SSARC_HP_SRAM0_ADDR_SHIFT (0U) |
#define | SSARC_HP_SRAM0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM0_ADDR_SHIFT)) & SSARC_HP_SRAM0_ADDR_MASK) |
SRAM1 - Description Data Register | |
#define | SSARC_HP_SRAM1_DATA_MASK (0xFFFFFFFFU) |
#define | SSARC_HP_SRAM1_DATA_SHIFT (0U) |
#define | SSARC_HP_SRAM1_DATA(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM1_DATA_SHIFT)) & SSARC_HP_SRAM1_DATA_MASK) |
SRAM2 - Description Control Register | |
#define | SSARC_HP_SRAM2_TYPE_MASK (0x7U) |
#define | SSARC_HP_SRAM2_TYPE_SHIFT (0U) |
#define | SSARC_HP_SRAM2_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_TYPE_SHIFT)) & SSARC_HP_SRAM2_TYPE_MASK) |
#define | SSARC_HP_SRAM2_SV_EN_MASK (0x10U) |
#define | SSARC_HP_SRAM2_SV_EN_SHIFT (4U) |
#define | SSARC_HP_SRAM2_SV_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SV_EN_SHIFT)) & SSARC_HP_SRAM2_SV_EN_MASK) |
#define | SSARC_HP_SRAM2_RT_EN_MASK (0x20U) |
#define | SSARC_HP_SRAM2_RT_EN_SHIFT (5U) |
#define | SSARC_HP_SRAM2_RT_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_RT_EN_SHIFT)) & SSARC_HP_SRAM2_RT_EN_MASK) |
#define | SSARC_HP_SRAM2_SIZE_MASK (0xC0U) |
#define | SSARC_HP_SRAM2_SIZE_SHIFT (6U) |
#define | SSARC_HP_SRAM2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SIZE_SHIFT)) & SSARC_HP_SRAM2_SIZE_MASK) |
DESC_CTRL0 - Descriptor Control0 0 Register..Descriptor Control0 15 Register | |
#define | SSARC_LP_DESC_CTRL0_START_MASK (0x3FFU) |
#define | SSARC_LP_DESC_CTRL0_START_SHIFT (0U) |
#define | SSARC_LP_DESC_CTRL0_START(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_START_SHIFT)) & SSARC_LP_DESC_CTRL0_START_MASK) |
#define | SSARC_LP_DESC_CTRL0_END_MASK (0xFFC00U) |
#define | SSARC_LP_DESC_CTRL0_END_SHIFT (10U) |
#define | SSARC_LP_DESC_CTRL0_END(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_END_SHIFT)) & SSARC_LP_DESC_CTRL0_END_MASK) |
#define | SSARC_LP_DESC_CTRL0_SV_ORDER_MASK (0x100000U) |
#define | SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT (20U) |
#define | SSARC_LP_DESC_CTRL0_SV_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_SV_ORDER_MASK) |
#define | SSARC_LP_DESC_CTRL0_RT_ORDER_MASK (0x200000U) |
#define | SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT (21U) |
#define | SSARC_LP_DESC_CTRL0_RT_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_RT_ORDER_MASK) |
DESC_CTRL1 - Descriptor Control1 0 Register..Descriptor Control1 15 Register | |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK (0x1U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT (0U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_SV(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK (0x2U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT (1U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_RT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK) |
#define | SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK (0x70U) |
#define | SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT (4U) |
#define | SSARC_LP_DESC_CTRL1_POWER_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT)) & SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK) |
#define | SSARC_LP_DESC_CTRL1_GP_EN_MASK (0x80U) |
#define | SSARC_LP_DESC_CTRL1_GP_EN_SHIFT (7U) |
#define | SSARC_LP_DESC_CTRL1_GP_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_GP_EN_SHIFT)) & SSARC_LP_DESC_CTRL1_GP_EN_MASK) |
#define | SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK (0xF00U) |
#define | SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT (8U) |
#define | SSARC_LP_DESC_CTRL1_SV_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK) |
#define | SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK (0xF000U) |
#define | SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT (12U) |
#define | SSARC_LP_DESC_CTRL1_RT_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK) |
#define | SSARC_LP_DESC_CTRL1_CPUD_MASK (0x30000U) |
#define | SSARC_LP_DESC_CTRL1_CPUD_SHIFT (16U) |
#define | SSARC_LP_DESC_CTRL1_CPUD(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_CPUD_SHIFT)) & SSARC_LP_DESC_CTRL1_CPUD_MASK) |
#define | SSARC_LP_DESC_CTRL1_RL_MASK (0x40000U) |
#define | SSARC_LP_DESC_CTRL1_RL_SHIFT (18U) |
#define | SSARC_LP_DESC_CTRL1_RL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RL_SHIFT)) & SSARC_LP_DESC_CTRL1_RL_MASK) |
#define | SSARC_LP_DESC_CTRL1_WL_MASK (0x80000U) |
#define | SSARC_LP_DESC_CTRL1_WL_SHIFT (19U) |
#define | SSARC_LP_DESC_CTRL1_WL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_WL_SHIFT)) & SSARC_LP_DESC_CTRL1_WL_MASK) |
#define | SSARC_LP_DESC_CTRL1_DL_MASK (0x100000U) |
#define | SSARC_LP_DESC_CTRL1_DL_SHIFT (20U) |
#define | SSARC_LP_DESC_CTRL1_DL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_DL_SHIFT)) & SSARC_LP_DESC_CTRL1_DL_MASK) |
DESC_ADDR_UP - Descriptor Address Up 0 Register..Descriptor Address Up 15 Register | |
#define | SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK (0xFFFFFFFFU) |
#define | SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT (0U) |
#define | SSARC_LP_DESC_ADDR_UP_ADDR_UP(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT)) & SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK) |
DESC_ADDR_DOWN - Descriptor Address Down 0 Register..Descriptor Address Down 15 Register | |
#define | SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK (0xFFFFFFFFU) |
#define | SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT (0U) |
#define | SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT)) & SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK) |
HP_TIMEOUT - HP Timeout Register | |
#define | SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK (0xFFFFFFFFU) |
#define | SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT (0U) |
#define | SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT)) & SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK) |
HW_GROUP_PENDING - Hardware Request Pending Register | |
#define | SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK (0xFFFFU) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT (0U) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK (0xFFFF0000U) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT (16U) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK) |
SW_GROUP_PENDING - Software Request Pending Register | |
#define | SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK (0xFFFFU) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT (0U) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK (0xFFFF0000U) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT (16U) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK) |
CTRL0 - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_V_SEL_SHIFT)) & TMPSNS_CTRL0_V_SEL_MASK) |
#define | TMPSNS_CTRL0_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_IBIAS_TRIM_MASK) |
CTRL0_SET - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_SET_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_SET_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SET_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_SET_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_SET_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_SET_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_V_SEL_SHIFT)) & TMPSNS_CTRL0_SET_V_SEL_MASK) |
#define | TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_SET_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK) |
CTRL0_CLR - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_CLR_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_CLR_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_CLR_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_CLR_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_V_SEL_SHIFT)) & TMPSNS_CTRL0_CLR_V_SEL_MASK) |
#define | TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_CLR_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK) |
CTRL0_TOG - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_TOG_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_TOG_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_TOG_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_TOG_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_V_SEL_SHIFT)) & TMPSNS_CTRL0_TOG_V_SEL_MASK) |
#define | TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_TOG_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK) |
CTRL1 - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK) |
#define | TMPSNS_CTRL1_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK) |
#define | TMPSNS_CTRL1_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK) |
#define | TMPSNS_CTRL1_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RFU_SHIFT)) & TMPSNS_CTRL1_RFU_MASK) |
#define | TMPSNS_CTRL1_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_PWD_FULL_MASK) |
CTRL1_SET - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_SET_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_SET_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_SET_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK) |
#define | TMPSNS_CTRL1_SET_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_SET_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_SET_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_SET_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_SET_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_SET_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_SET_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_SET_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_SET_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK) |
#define | TMPSNS_CTRL1_SET_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_SET_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_SET_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK) |
#define | TMPSNS_CTRL1_SET_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_SET_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_SET_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RFU_SHIFT)) & TMPSNS_CTRL1_SET_RFU_MASK) |
#define | TMPSNS_CTRL1_SET_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_SET_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_SET_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_SET_PWD_FULL_MASK) |
CTRL1_CLR - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_CLR_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_CLR_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_CLR_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK) |
#define | TMPSNS_CTRL1_CLR_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_CLR_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_CLR_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_CLR_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_CLR_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_CLR_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK) |
#define | TMPSNS_CTRL1_CLR_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_CLR_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_CLR_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK) |
#define | TMPSNS_CTRL1_CLR_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_CLR_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_CLR_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RFU_SHIFT)) & TMPSNS_CTRL1_CLR_RFU_MASK) |
#define | TMPSNS_CTRL1_CLR_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_CLR_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_FULL_MASK) |
CTRL1_TOG - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_TOG_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_TOG_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_TOG_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK) |
#define | TMPSNS_CTRL1_TOG_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_TOG_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_TOG_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_TOG_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_TOG_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_TOG_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK) |
#define | TMPSNS_CTRL1_TOG_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_TOG_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_TOG_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK) |
#define | TMPSNS_CTRL1_TOG_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_TOG_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_TOG_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RFU_SHIFT)) & TMPSNS_CTRL1_TOG_RFU_MASK) |
#define | TMPSNS_CTRL1_TOG_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_TOG_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_FULL_MASK) |
RANGE0 - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK) |
RANGE0_SET - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_SET_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_SET_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK) |
RANGE0_CLR - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_CLR_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK) |
RANGE0_TOG - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_TOG_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK) |
RANGE1 - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK) |
RANGE1_SET - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_SET_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK) |
RANGE1_CLR - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK) |
RANGE1_TOG - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK) |
STATUS0 - Temperature Sensor Status Register 0 | |
#define | TMPSNS_STATUS0_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_STATUS0_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_STATUS0_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK) |
#define | TMPSNS_STATUS0_FINISH_MASK (0x10000U) |
#define | TMPSNS_STATUS0_FINISH_SHIFT (16U) |
#define | TMPSNS_STATUS0_FINISH(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK) |
#define | TMPSNS_STATUS0_LOW_TEMP_MASK (0x20000U) |
#define | TMPSNS_STATUS0_LOW_TEMP_SHIFT (17U) |
#define | TMPSNS_STATUS0_LOW_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK) |
#define | TMPSNS_STATUS0_HIGH_TEMP_MASK (0x40000U) |
#define | TMPSNS_STATUS0_HIGH_TEMP_SHIFT (18U) |
#define | TMPSNS_STATUS0_HIGH_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK) |
#define | TMPSNS_STATUS0_PANIC_TEMP_MASK (0x80000U) |
#define | TMPSNS_STATUS0_PANIC_TEMP_SHIFT (19U) |
#define | TMPSNS_STATUS0_PANIC_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_PANIC_TEMP_SHIFT)) & TMPSNS_STATUS0_PANIC_TEMP_MASK) |
COMP1 - Timer Channel Compare Register 1 | |
#define | TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) |
#define | TMR_COMP1_COMPARISON_1_SHIFT (0U) |
#define | TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK) |
COMP2 - Timer Channel Compare Register 2 | |
#define | TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) |
#define | TMR_COMP2_COMPARISON_2_SHIFT (0U) |
#define | TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK) |
CAPT - Timer Channel Capture Register | |
#define | TMR_CAPT_CAPTURE_MASK (0xFFFFU) |
#define | TMR_CAPT_CAPTURE_SHIFT (0U) |
#define | TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK) |
LOAD - Timer Channel Load Register | |
#define | TMR_LOAD_LOAD_MASK (0xFFFFU) |
#define | TMR_LOAD_LOAD_SHIFT (0U) |
#define | TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK) |
HOLD - Timer Channel Hold Register | |
#define | TMR_HOLD_HOLD_MASK (0xFFFFU) |
#define | TMR_HOLD_HOLD_SHIFT (0U) |
#define | TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK) |
CNTR - Timer Channel Counter Register | |
#define | TMR_CNTR_COUNTER_MASK (0xFFFFU) |
#define | TMR_CNTR_COUNTER_SHIFT (0U) |
#define | TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK) |
CTRL - Timer Channel Control Register | |
#define | TMR_CTRL_OUTMODE_MASK (0x7U) |
#define | TMR_CTRL_OUTMODE_SHIFT (0U) |
#define | TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) |
#define | TMR_CTRL_COINIT_MASK (0x8U) |
#define | TMR_CTRL_COINIT_SHIFT (3U) |
#define | TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK) |
#define | TMR_CTRL_DIR_MASK (0x10U) |
#define | TMR_CTRL_DIR_SHIFT (4U) |
#define | TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK) |
#define | TMR_CTRL_LENGTH_MASK (0x20U) |
#define | TMR_CTRL_LENGTH_SHIFT (5U) |
#define | TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK) |
#define | TMR_CTRL_ONCE_MASK (0x40U) |
#define | TMR_CTRL_ONCE_SHIFT (6U) |
#define | TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK) |
#define | TMR_CTRL_SCS_MASK (0x180U) |
#define | TMR_CTRL_SCS_SHIFT (7U) |
#define | TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK) |
#define | TMR_CTRL_PCS_MASK (0x1E00U) |
#define | TMR_CTRL_PCS_SHIFT (9U) |
#define | TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK) |
#define | TMR_CTRL_CM_MASK (0xE000U) |
#define | TMR_CTRL_CM_SHIFT (13U) |
#define | TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK) |
SCTRL - Timer Channel Status and Control Register | |
#define | TMR_SCTRL_OEN_MASK (0x1U) |
#define | TMR_SCTRL_OEN_SHIFT (0U) |
#define | TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) |
#define | TMR_SCTRL_OPS_MASK (0x2U) |
#define | TMR_SCTRL_OPS_SHIFT (1U) |
#define | TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK) |
#define | TMR_SCTRL_FORCE_MASK (0x4U) |
#define | TMR_SCTRL_FORCE_SHIFT (2U) |
#define | TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK) |
#define | TMR_SCTRL_VAL_MASK (0x8U) |
#define | TMR_SCTRL_VAL_SHIFT (3U) |
#define | TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK) |
#define | TMR_SCTRL_EEOF_MASK (0x10U) |
#define | TMR_SCTRL_EEOF_SHIFT (4U) |
#define | TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK) |
#define | TMR_SCTRL_MSTR_MASK (0x20U) |
#define | TMR_SCTRL_MSTR_SHIFT (5U) |
#define | TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK) |
#define | TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U) |
#define | TMR_SCTRL_CAPTURE_MODE_SHIFT (6U) |
#define | TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK) |
#define | TMR_SCTRL_INPUT_MASK (0x100U) |
#define | TMR_SCTRL_INPUT_SHIFT (8U) |
#define | TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK) |
#define | TMR_SCTRL_IPS_MASK (0x200U) |
#define | TMR_SCTRL_IPS_SHIFT (9U) |
#define | TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK) |
#define | TMR_SCTRL_IEFIE_MASK (0x400U) |
#define | TMR_SCTRL_IEFIE_SHIFT (10U) |
#define | TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK) |
#define | TMR_SCTRL_IEF_MASK (0x800U) |
#define | TMR_SCTRL_IEF_SHIFT (11U) |
#define | TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK) |
#define | TMR_SCTRL_TOFIE_MASK (0x1000U) |
#define | TMR_SCTRL_TOFIE_SHIFT (12U) |
#define | TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK) |
#define | TMR_SCTRL_TOF_MASK (0x2000U) |
#define | TMR_SCTRL_TOF_SHIFT (13U) |
#define | TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK) |
#define | TMR_SCTRL_TCFIE_MASK (0x4000U) |
#define | TMR_SCTRL_TCFIE_SHIFT (14U) |
#define | TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK) |
#define | TMR_SCTRL_TCF_MASK (0x8000U) |
#define | TMR_SCTRL_TCF_SHIFT (15U) |
#define | TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK) |
CMPLD1 - Timer Channel Comparator Load Register 1 | |
#define | TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) |
#define | TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) |
#define | TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK) |
CMPLD2 - Timer Channel Comparator Load Register 2 | |
#define | TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) |
#define | TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) |
#define | TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK) |
CSCTRL - Timer Channel Comparator Status and Control Register | |
#define | TMR_CSCTRL_CL1_MASK (0x3U) |
#define | TMR_CSCTRL_CL1_SHIFT (0U) |
#define | TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) |
#define | TMR_CSCTRL_CL2_MASK (0xCU) |
#define | TMR_CSCTRL_CL2_SHIFT (2U) |
#define | TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK) |
#define | TMR_CSCTRL_TCF1_MASK (0x10U) |
#define | TMR_CSCTRL_TCF1_SHIFT (4U) |
#define | TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK) |
#define | TMR_CSCTRL_TCF2_MASK (0x20U) |
#define | TMR_CSCTRL_TCF2_SHIFT (5U) |
#define | TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK) |
#define | TMR_CSCTRL_TCF1EN_MASK (0x40U) |
#define | TMR_CSCTRL_TCF1EN_SHIFT (6U) |
#define | TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK) |
#define | TMR_CSCTRL_TCF2EN_MASK (0x80U) |
#define | TMR_CSCTRL_TCF2EN_SHIFT (7U) |
#define | TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK) |
#define | TMR_CSCTRL_UP_MASK (0x200U) |
#define | TMR_CSCTRL_UP_SHIFT (9U) |
#define | TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK) |
#define | TMR_CSCTRL_TCI_MASK (0x400U) |
#define | TMR_CSCTRL_TCI_SHIFT (10U) |
#define | TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK) |
#define | TMR_CSCTRL_ROC_MASK (0x800U) |
#define | TMR_CSCTRL_ROC_SHIFT (11U) |
#define | TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK) |
#define | TMR_CSCTRL_ALT_LOAD_MASK (0x1000U) |
#define | TMR_CSCTRL_ALT_LOAD_SHIFT (12U) |
#define | TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK) |
#define | TMR_CSCTRL_FAULT_MASK (0x2000U) |
#define | TMR_CSCTRL_FAULT_SHIFT (13U) |
#define | TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK) |
#define | TMR_CSCTRL_DBG_EN_MASK (0xC000U) |
#define | TMR_CSCTRL_DBG_EN_SHIFT (14U) |
#define | TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK) |
FILT - Timer Channel Input Filter Register | |
#define | TMR_FILT_FILT_PER_MASK (0xFFU) |
#define | TMR_FILT_FILT_PER_SHIFT (0U) |
#define | TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) |
#define | TMR_FILT_FILT_CNT_MASK (0x700U) |
#define | TMR_FILT_FILT_CNT_SHIFT (8U) |
#define | TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK) |
DMA - Timer Channel DMA Enable Register | |
#define | TMR_DMA_IEFDE_MASK (0x1U) |
#define | TMR_DMA_IEFDE_SHIFT (0U) |
#define | TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK) |
#define | TMR_DMA_CMPLD1DE_MASK (0x2U) |
#define | TMR_DMA_CMPLD1DE_SHIFT (1U) |
#define | TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK) |
#define | TMR_DMA_CMPLD2DE_MASK (0x4U) |
#define | TMR_DMA_CMPLD2DE_SHIFT (2U) |
#define | TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK) |
ENBL - Timer Channel Enable Register | |
#define | TMR_ENBL_ENBL_MASK (0xFU) |
#define | TMR_ENBL_ENBL_SHIFT (0U) |
#define | TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK) |
ID - Identification register | |
#define | USB_ID_ID_MASK (0x3FU) |
#define | USB_ID_ID_SHIFT (0U) |
#define | USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) |
#define | USB_ID_NID_MASK (0x3F00U) |
#define | USB_ID_NID_SHIFT (8U) |
#define | USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) |
#define | USB_ID_REVISION_MASK (0xFF0000U) |
#define | USB_ID_REVISION_SHIFT (16U) |
#define | USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) |
HWGENERAL - Hardware General | |
#define | USB_HWGENERAL_PHYW_MASK (0x30U) |
#define | USB_HWGENERAL_PHYW_SHIFT (4U) |
#define | USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) |
#define | USB_HWGENERAL_PHYM_MASK (0x1C0U) |
#define | USB_HWGENERAL_PHYM_SHIFT (6U) |
#define | USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) |
#define | USB_HWGENERAL_SM_MASK (0x600U) |
#define | USB_HWGENERAL_SM_SHIFT (9U) |
#define | USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) |
HWHOST - Host Hardware Parameters | |
#define | USB_HWHOST_HC_MASK (0x1U) |
#define | USB_HWHOST_HC_SHIFT (0U) |
#define | USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) |
#define | USB_HWHOST_NPORT_MASK (0xEU) |
#define | USB_HWHOST_NPORT_SHIFT (1U) |
#define | USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) |
HWDEVICE - Device Hardware Parameters | |
#define | USB_HWDEVICE_DC_MASK (0x1U) |
#define | USB_HWDEVICE_DC_SHIFT (0U) |
#define | USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) |
#define | USB_HWDEVICE_DEVEP_MASK (0x3EU) |
#define | USB_HWDEVICE_DEVEP_SHIFT (1U) |
#define | USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) |
HWTXBUF - TX Buffer Hardware Parameters | |
#define | USB_HWTXBUF_TXBURST_MASK (0xFFU) |
#define | USB_HWTXBUF_TXBURST_SHIFT (0U) |
#define | USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) |
#define | USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) |
#define | USB_HWTXBUF_TXCHANADD_SHIFT (16U) |
#define | USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) |
HWRXBUF - RX Buffer Hardware Parameters | |
#define | USB_HWRXBUF_RXBURST_MASK (0xFFU) |
#define | USB_HWRXBUF_RXBURST_SHIFT (0U) |
#define | USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) |
#define | USB_HWRXBUF_RXADD_MASK (0xFF00U) |
#define | USB_HWRXBUF_RXADD_SHIFT (8U) |
#define | USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) |
GPTIMER0LD - General Purpose Timer #0 Load | |
#define | USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) |
#define | USB_GPTIMER0LD_GPTLD_SHIFT (0U) |
#define | USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) |
GPTIMER0CTRL - General Purpose Timer #0 Controller | |
#define | USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) |
#define | USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) |
#define | USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) |
#define | USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) |
#define | USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) |
#define | USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) |
#define | USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) |
#define | USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) |
#define | USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) |
#define | USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) |
#define | USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) |
#define | USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) |
GPTIMER1LD - General Purpose Timer #1 Load | |
#define | USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) |
#define | USB_GPTIMER1LD_GPTLD_SHIFT (0U) |
#define | USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) |
GPTIMER1CTRL - General Purpose Timer #1 Controller | |
#define | USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) |
#define | USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) |
#define | USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) |
#define | USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) |
#define | USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) |
#define | USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) |
#define | USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) |
#define | USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) |
#define | USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) |
#define | USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) |
#define | USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) |
#define | USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) |
SBUSCFG - System Bus Config | |
#define | USB_SBUSCFG_AHBBRST_MASK (0x7U) |
#define | USB_SBUSCFG_AHBBRST_SHIFT (0U) |
#define | USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) |
CAPLENGTH - Capability Registers Length | |
#define | USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) |
#define | USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) |
#define | USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) |
HCIVERSION - Host Controller Interface Version | |
#define | USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) |
#define | USB_HCIVERSION_HCIVERSION_SHIFT (0U) |
#define | USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) |
HCSPARAMS - Host Controller Structural Parameters | |
#define | USB_HCSPARAMS_N_PORTS_MASK (0xFU) |
#define | USB_HCSPARAMS_N_PORTS_SHIFT (0U) |
#define | USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) |
#define | USB_HCSPARAMS_PPC_MASK (0x10U) |
#define | USB_HCSPARAMS_PPC_SHIFT (4U) |
#define | USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) |
#define | USB_HCSPARAMS_N_PCC_MASK (0xF00U) |
#define | USB_HCSPARAMS_N_PCC_SHIFT (8U) |
#define | USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) |
#define | USB_HCSPARAMS_N_CC_MASK (0xF000U) |
#define | USB_HCSPARAMS_N_CC_SHIFT (12U) |
#define | USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) |
#define | USB_HCSPARAMS_PI_MASK (0x10000U) |
#define | USB_HCSPARAMS_PI_SHIFT (16U) |
#define | USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) |
#define | USB_HCSPARAMS_N_PTT_MASK (0xF00000U) |
#define | USB_HCSPARAMS_N_PTT_SHIFT (20U) |
#define | USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) |
#define | USB_HCSPARAMS_N_TT_MASK (0xF000000U) |
#define | USB_HCSPARAMS_N_TT_SHIFT (24U) |
#define | USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) |
HCCPARAMS - Host Controller Capability Parameters | |
#define | USB_HCCPARAMS_ADC_MASK (0x1U) |
#define | USB_HCCPARAMS_ADC_SHIFT (0U) |
#define | USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) |
#define | USB_HCCPARAMS_PFL_MASK (0x2U) |
#define | USB_HCCPARAMS_PFL_SHIFT (1U) |
#define | USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) |
#define | USB_HCCPARAMS_ASP_MASK (0x4U) |
#define | USB_HCCPARAMS_ASP_SHIFT (2U) |
#define | USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) |
#define | USB_HCCPARAMS_IST_MASK (0xF0U) |
#define | USB_HCCPARAMS_IST_SHIFT (4U) |
#define | USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) |
#define | USB_HCCPARAMS_EECP_MASK (0xFF00U) |
#define | USB_HCCPARAMS_EECP_SHIFT (8U) |
#define | USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) |
DCIVERSION - Device Controller Interface Version | |
#define | USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) |
#define | USB_DCIVERSION_DCIVERSION_SHIFT (0U) |
#define | USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) |
DCCPARAMS - Device Controller Capability Parameters | |
#define | USB_DCCPARAMS_DEN_MASK (0x1FU) |
#define | USB_DCCPARAMS_DEN_SHIFT (0U) |
#define | USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) |
#define | USB_DCCPARAMS_DC_MASK (0x80U) |
#define | USB_DCCPARAMS_DC_SHIFT (7U) |
#define | USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) |
#define | USB_DCCPARAMS_HC_MASK (0x100U) |
#define | USB_DCCPARAMS_HC_SHIFT (8U) |
#define | USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) |
USBCMD - USB Command Register | |
#define | USB_USBCMD_RS_MASK (0x1U) |
#define | USB_USBCMD_RS_SHIFT (0U) |
#define | USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) |
#define | USB_USBCMD_RST_MASK (0x2U) |
#define | USB_USBCMD_RST_SHIFT (1U) |
#define | USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) |
#define | USB_USBCMD_FS_1_MASK (0xCU) |
#define | USB_USBCMD_FS_1_SHIFT (2U) |
#define | USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) |
#define | USB_USBCMD_PSE_MASK (0x10U) |
#define | USB_USBCMD_PSE_SHIFT (4U) |
#define | USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) |
#define | USB_USBCMD_ASE_MASK (0x20U) |
#define | USB_USBCMD_ASE_SHIFT (5U) |
#define | USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) |
#define | USB_USBCMD_IAA_MASK (0x40U) |
#define | USB_USBCMD_IAA_SHIFT (6U) |
#define | USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) |
#define | USB_USBCMD_ASP_MASK (0x300U) |
#define | USB_USBCMD_ASP_SHIFT (8U) |
#define | USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) |
#define | USB_USBCMD_ASPE_MASK (0x800U) |
#define | USB_USBCMD_ASPE_SHIFT (11U) |
#define | USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) |
#define | USB_USBCMD_SUTW_MASK (0x2000U) |
#define | USB_USBCMD_SUTW_SHIFT (13U) |
#define | USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) |
#define | USB_USBCMD_ATDTW_MASK (0x4000U) |
#define | USB_USBCMD_ATDTW_SHIFT (14U) |
#define | USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) |
#define | USB_USBCMD_FS_2_MASK (0x8000U) |
#define | USB_USBCMD_FS_2_SHIFT (15U) |
#define | USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) |
#define | USB_USBCMD_ITC_MASK (0xFF0000U) |
#define | USB_USBCMD_ITC_SHIFT (16U) |
#define | USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) |
USBSTS - USB Status Register | |
#define | USB_USBSTS_UI_MASK (0x1U) |
#define | USB_USBSTS_UI_SHIFT (0U) |
#define | USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) |
#define | USB_USBSTS_UEI_MASK (0x2U) |
#define | USB_USBSTS_UEI_SHIFT (1U) |
#define | USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) |
#define | USB_USBSTS_PCI_MASK (0x4U) |
#define | USB_USBSTS_PCI_SHIFT (2U) |
#define | USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) |
#define | USB_USBSTS_FRI_MASK (0x8U) |
#define | USB_USBSTS_FRI_SHIFT (3U) |
#define | USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) |
#define | USB_USBSTS_SEI_MASK (0x10U) |
#define | USB_USBSTS_SEI_SHIFT (4U) |
#define | USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) |
#define | USB_USBSTS_AAI_MASK (0x20U) |
#define | USB_USBSTS_AAI_SHIFT (5U) |
#define | USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) |
#define | USB_USBSTS_URI_MASK (0x40U) |
#define | USB_USBSTS_URI_SHIFT (6U) |
#define | USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) |
#define | USB_USBSTS_SRI_MASK (0x80U) |
#define | USB_USBSTS_SRI_SHIFT (7U) |
#define | USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) |
#define | USB_USBSTS_SLI_MASK (0x100U) |
#define | USB_USBSTS_SLI_SHIFT (8U) |
#define | USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) |
#define | USB_USBSTS_ULPII_MASK (0x400U) |
#define | USB_USBSTS_ULPII_SHIFT (10U) |
#define | USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) |
#define | USB_USBSTS_HCH_MASK (0x1000U) |
#define | USB_USBSTS_HCH_SHIFT (12U) |
#define | USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) |
#define | USB_USBSTS_RCL_MASK (0x2000U) |
#define | USB_USBSTS_RCL_SHIFT (13U) |
#define | USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) |
#define | USB_USBSTS_PS_MASK (0x4000U) |
#define | USB_USBSTS_PS_SHIFT (14U) |
#define | USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) |
#define | USB_USBSTS_AS_MASK (0x8000U) |
#define | USB_USBSTS_AS_SHIFT (15U) |
#define | USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) |
#define | USB_USBSTS_NAKI_MASK (0x10000U) |
#define | USB_USBSTS_NAKI_SHIFT (16U) |
#define | USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) |
#define | USB_USBSTS_TI0_MASK (0x1000000U) |
#define | USB_USBSTS_TI0_SHIFT (24U) |
#define | USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) |
#define | USB_USBSTS_TI1_MASK (0x2000000U) |
#define | USB_USBSTS_TI1_SHIFT (25U) |
#define | USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) |
USBINTR - Interrupt Enable Register | |
#define | USB_USBINTR_UE_MASK (0x1U) |
#define | USB_USBINTR_UE_SHIFT (0U) |
#define | USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) |
#define | USB_USBINTR_UEE_MASK (0x2U) |
#define | USB_USBINTR_UEE_SHIFT (1U) |
#define | USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) |
#define | USB_USBINTR_PCE_MASK (0x4U) |
#define | USB_USBINTR_PCE_SHIFT (2U) |
#define | USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) |
#define | USB_USBINTR_FRE_MASK (0x8U) |
#define | USB_USBINTR_FRE_SHIFT (3U) |
#define | USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) |
#define | USB_USBINTR_SEE_MASK (0x10U) |
#define | USB_USBINTR_SEE_SHIFT (4U) |
#define | USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) |
#define | USB_USBINTR_AAE_MASK (0x20U) |
#define | USB_USBINTR_AAE_SHIFT (5U) |
#define | USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) |
#define | USB_USBINTR_URE_MASK (0x40U) |
#define | USB_USBINTR_URE_SHIFT (6U) |
#define | USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) |
#define | USB_USBINTR_SRE_MASK (0x80U) |
#define | USB_USBINTR_SRE_SHIFT (7U) |
#define | USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) |
#define | USB_USBINTR_SLE_MASK (0x100U) |
#define | USB_USBINTR_SLE_SHIFT (8U) |
#define | USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) |
#define | USB_USBINTR_ULPIE_MASK (0x400U) |
#define | USB_USBINTR_ULPIE_SHIFT (10U) |
#define | USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) |
#define | USB_USBINTR_NAKE_MASK (0x10000U) |
#define | USB_USBINTR_NAKE_SHIFT (16U) |
#define | USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) |
#define | USB_USBINTR_UAIE_MASK (0x40000U) |
#define | USB_USBINTR_UAIE_SHIFT (18U) |
#define | USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) |
#define | USB_USBINTR_UPIE_MASK (0x80000U) |
#define | USB_USBINTR_UPIE_SHIFT (19U) |
#define | USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) |
#define | USB_USBINTR_TIE0_MASK (0x1000000U) |
#define | USB_USBINTR_TIE0_SHIFT (24U) |
#define | USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) |
#define | USB_USBINTR_TIE1_MASK (0x2000000U) |
#define | USB_USBINTR_TIE1_SHIFT (25U) |
#define | USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) |
FRINDEX - USB Frame Index | |
#define | USB_FRINDEX_FRINDEX_MASK (0x3FFFU) |
#define | USB_FRINDEX_FRINDEX_SHIFT (0U) |
#define | USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) |
DEVICEADDR - Device Address | |
#define | USB_DEVICEADDR_USBADRA_MASK (0x1000000U) |
#define | USB_DEVICEADDR_USBADRA_SHIFT (24U) |
#define | USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) |
#define | USB_DEVICEADDR_USBADR_MASK (0xFE000000U) |
#define | USB_DEVICEADDR_USBADR_SHIFT (25U) |
#define | USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) |
PERIODICLISTBASE - Frame List Base Address | |
#define | USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) |
#define | USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) |
#define | USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) |
ASYNCLISTADDR - Next Asynch. Address | |
#define | USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) |
#define | USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) |
#define | USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) |
ENDPTLISTADDR - Endpoint List Address | |
#define | USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) |
#define | USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) |
#define | USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) |
BURSTSIZE - Programmable Burst Size | |
#define | USB_BURSTSIZE_RXPBURST_MASK (0xFFU) |
#define | USB_BURSTSIZE_RXPBURST_SHIFT (0U) |
#define | USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) |
#define | USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) |
#define | USB_BURSTSIZE_TXPBURST_SHIFT (8U) |
#define | USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) |
TXFILLTUNING - TX FIFO Fill Tuning | |
#define | USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) |
#define | USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) |
#define | USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) |
#define | USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) |
#define | USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) |
#define | USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) |
#define | USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) |
#define | USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) |
#define | USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) |
ENDPTNAK - Endpoint NAK | |
#define | USB_ENDPTNAK_EPRN_MASK (0xFFU) |
#define | USB_ENDPTNAK_EPRN_SHIFT (0U) |
#define | USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) |
#define | USB_ENDPTNAK_EPTN_MASK (0xFF0000U) |
#define | USB_ENDPTNAK_EPTN_SHIFT (16U) |
#define | USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) |
ENDPTNAKEN - Endpoint NAK Enable | |
#define | USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) |
#define | USB_ENDPTNAKEN_EPRNE_SHIFT (0U) |
#define | USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) |
#define | USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) |
#define | USB_ENDPTNAKEN_EPTNE_SHIFT (16U) |
#define | USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) |
CONFIGFLAG - Configure Flag Register | |
#define | USB_CONFIGFLAG_CF_MASK (0x1U) |
#define | USB_CONFIGFLAG_CF_SHIFT (0U) |
#define | USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) |
PORTSC1 - Port Status & Control | |
#define | USB_PORTSC1_CCS_MASK (0x1U) |
#define | USB_PORTSC1_CCS_SHIFT (0U) |
#define | USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) |
#define | USB_PORTSC1_CSC_MASK (0x2U) |
#define | USB_PORTSC1_CSC_SHIFT (1U) |
#define | USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) |
#define | USB_PORTSC1_PE_MASK (0x4U) |
#define | USB_PORTSC1_PE_SHIFT (2U) |
#define | USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) |
#define | USB_PORTSC1_PEC_MASK (0x8U) |
#define | USB_PORTSC1_PEC_SHIFT (3U) |
#define | USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) |
#define | USB_PORTSC1_OCA_MASK (0x10U) |
#define | USB_PORTSC1_OCA_SHIFT (4U) |
#define | USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) |
#define | USB_PORTSC1_OCC_MASK (0x20U) |
#define | USB_PORTSC1_OCC_SHIFT (5U) |
#define | USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) |
#define | USB_PORTSC1_FPR_MASK (0x40U) |
#define | USB_PORTSC1_FPR_SHIFT (6U) |
#define | USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) |
#define | USB_PORTSC1_SUSP_MASK (0x80U) |
#define | USB_PORTSC1_SUSP_SHIFT (7U) |
#define | USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) |
#define | USB_PORTSC1_PR_MASK (0x100U) |
#define | USB_PORTSC1_PR_SHIFT (8U) |
#define | USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) |
#define | USB_PORTSC1_HSP_MASK (0x200U) |
#define | USB_PORTSC1_HSP_SHIFT (9U) |
#define | USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) |
#define | USB_PORTSC1_LS_MASK (0xC00U) |
#define | USB_PORTSC1_LS_SHIFT (10U) |
#define | USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) |
#define | USB_PORTSC1_PP_MASK (0x1000U) |
#define | USB_PORTSC1_PP_SHIFT (12U) |
#define | USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) |
#define | USB_PORTSC1_PO_MASK (0x2000U) |
#define | USB_PORTSC1_PO_SHIFT (13U) |
#define | USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) |
#define | USB_PORTSC1_PIC_MASK (0xC000U) |
#define | USB_PORTSC1_PIC_SHIFT (14U) |
#define | USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) |
#define | USB_PORTSC1_PTC_MASK (0xF0000U) |
#define | USB_PORTSC1_PTC_SHIFT (16U) |
#define | USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) |
#define | USB_PORTSC1_WKCN_MASK (0x100000U) |
#define | USB_PORTSC1_WKCN_SHIFT (20U) |
#define | USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) |
#define | USB_PORTSC1_WKDC_MASK (0x200000U) |
#define | USB_PORTSC1_WKDC_SHIFT (21U) |
#define | USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) |
#define | USB_PORTSC1_WKOC_MASK (0x400000U) |
#define | USB_PORTSC1_WKOC_SHIFT (22U) |
#define | USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) |
#define | USB_PORTSC1_PHCD_MASK (0x800000U) |
#define | USB_PORTSC1_PHCD_SHIFT (23U) |
#define | USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) |
#define | USB_PORTSC1_PFSC_MASK (0x1000000U) |
#define | USB_PORTSC1_PFSC_SHIFT (24U) |
#define | USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) |
#define | USB_PORTSC1_PTS_2_MASK (0x2000000U) |
#define | USB_PORTSC1_PTS_2_SHIFT (25U) |
#define | USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) |
#define | USB_PORTSC1_PSPD_MASK (0xC000000U) |
#define | USB_PORTSC1_PSPD_SHIFT (26U) |
#define | USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) |
#define | USB_PORTSC1_PTW_MASK (0x10000000U) |
#define | USB_PORTSC1_PTW_SHIFT (28U) |
#define | USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) |
#define | USB_PORTSC1_STS_MASK (0x20000000U) |
#define | USB_PORTSC1_STS_SHIFT (29U) |
#define | USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) |
#define | USB_PORTSC1_PTS_1_MASK (0xC0000000U) |
#define | USB_PORTSC1_PTS_1_SHIFT (30U) |
#define | USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) |
OTGSC - On-The-Go Status & control | |
#define | USB_OTGSC_VD_MASK (0x1U) |
#define | USB_OTGSC_VD_SHIFT (0U) |
#define | USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) |
#define | USB_OTGSC_VC_MASK (0x2U) |
#define | USB_OTGSC_VC_SHIFT (1U) |
#define | USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) |
#define | USB_OTGSC_OT_MASK (0x8U) |
#define | USB_OTGSC_OT_SHIFT (3U) |
#define | USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) |
#define | USB_OTGSC_DP_MASK (0x10U) |
#define | USB_OTGSC_DP_SHIFT (4U) |
#define | USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) |
#define | USB_OTGSC_IDPU_MASK (0x20U) |
#define | USB_OTGSC_IDPU_SHIFT (5U) |
#define | USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) |
#define | USB_OTGSC_ID_MASK (0x100U) |
#define | USB_OTGSC_ID_SHIFT (8U) |
#define | USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) |
#define | USB_OTGSC_AVV_MASK (0x200U) |
#define | USB_OTGSC_AVV_SHIFT (9U) |
#define | USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) |
#define | USB_OTGSC_ASV_MASK (0x400U) |
#define | USB_OTGSC_ASV_SHIFT (10U) |
#define | USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) |
#define | USB_OTGSC_BSV_MASK (0x800U) |
#define | USB_OTGSC_BSV_SHIFT (11U) |
#define | USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) |
#define | USB_OTGSC_BSE_MASK (0x1000U) |
#define | USB_OTGSC_BSE_SHIFT (12U) |
#define | USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) |
#define | USB_OTGSC_TOG_1MS_MASK (0x2000U) |
#define | USB_OTGSC_TOG_1MS_SHIFT (13U) |
#define | USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) |
#define | USB_OTGSC_DPS_MASK (0x4000U) |
#define | USB_OTGSC_DPS_SHIFT (14U) |
#define | USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) |
#define | USB_OTGSC_IDIS_MASK (0x10000U) |
#define | USB_OTGSC_IDIS_SHIFT (16U) |
#define | USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) |
#define | USB_OTGSC_AVVIS_MASK (0x20000U) |
#define | USB_OTGSC_AVVIS_SHIFT (17U) |
#define | USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) |
#define | USB_OTGSC_ASVIS_MASK (0x40000U) |
#define | USB_OTGSC_ASVIS_SHIFT (18U) |
#define | USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) |
#define | USB_OTGSC_BSVIS_MASK (0x80000U) |
#define | USB_OTGSC_BSVIS_SHIFT (19U) |
#define | USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) |
#define | USB_OTGSC_BSEIS_MASK (0x100000U) |
#define | USB_OTGSC_BSEIS_SHIFT (20U) |
#define | USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) |
#define | USB_OTGSC_STATUS_1MS_MASK (0x200000U) |
#define | USB_OTGSC_STATUS_1MS_SHIFT (21U) |
#define | USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) |
#define | USB_OTGSC_DPIS_MASK (0x400000U) |
#define | USB_OTGSC_DPIS_SHIFT (22U) |
#define | USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) |
#define | USB_OTGSC_IDIE_MASK (0x1000000U) |
#define | USB_OTGSC_IDIE_SHIFT (24U) |
#define | USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) |
#define | USB_OTGSC_AVVIE_MASK (0x2000000U) |
#define | USB_OTGSC_AVVIE_SHIFT (25U) |
#define | USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) |
#define | USB_OTGSC_ASVIE_MASK (0x4000000U) |
#define | USB_OTGSC_ASVIE_SHIFT (26U) |
#define | USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) |
#define | USB_OTGSC_BSVIE_MASK (0x8000000U) |
#define | USB_OTGSC_BSVIE_SHIFT (27U) |
#define | USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) |
#define | USB_OTGSC_BSEIE_MASK (0x10000000U) |
#define | USB_OTGSC_BSEIE_SHIFT (28U) |
#define | USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) |
#define | USB_OTGSC_EN_1MS_MASK (0x20000000U) |
#define | USB_OTGSC_EN_1MS_SHIFT (29U) |
#define | USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) |
#define | USB_OTGSC_DPIE_MASK (0x40000000U) |
#define | USB_OTGSC_DPIE_SHIFT (30U) |
#define | USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) |
USBMODE - USB Device Mode | |
#define | USB_USBMODE_CM_MASK (0x3U) |
#define | USB_USBMODE_CM_SHIFT (0U) |
#define | USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) |
#define | USB_USBMODE_ES_MASK (0x4U) |
#define | USB_USBMODE_ES_SHIFT (2U) |
#define | USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) |
#define | USB_USBMODE_SLOM_MASK (0x8U) |
#define | USB_USBMODE_SLOM_SHIFT (3U) |
#define | USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) |
#define | USB_USBMODE_SDIS_MASK (0x10U) |
#define | USB_USBMODE_SDIS_SHIFT (4U) |
#define | USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) |
ENDPTSETUPSTAT - Endpoint Setup Status | |
#define | USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) |
#define | USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) |
#define | USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) |
ENDPTPRIME - Endpoint Prime | |
#define | USB_ENDPTPRIME_PERB_MASK (0xFFU) |
#define | USB_ENDPTPRIME_PERB_SHIFT (0U) |
#define | USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) |
#define | USB_ENDPTPRIME_PETB_MASK (0xFF0000U) |
#define | USB_ENDPTPRIME_PETB_SHIFT (16U) |
#define | USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) |
ENDPTFLUSH - Endpoint Flush | |
#define | USB_ENDPTFLUSH_FERB_MASK (0xFFU) |
#define | USB_ENDPTFLUSH_FERB_SHIFT (0U) |
#define | USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) |
#define | USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) |
#define | USB_ENDPTFLUSH_FETB_SHIFT (16U) |
#define | USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) |
ENDPTSTAT - Endpoint Status | |
#define | USB_ENDPTSTAT_ERBR_MASK (0xFFU) |
#define | USB_ENDPTSTAT_ERBR_SHIFT (0U) |
#define | USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) |
#define | USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) |
#define | USB_ENDPTSTAT_ETBR_SHIFT (16U) |
#define | USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) |
ENDPTCOMPLETE - Endpoint Complete | |
#define | USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) |
#define | USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) |
#define | USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) |
#define | USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) |
#define | USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) |
#define | USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) |
ENDPTCTRL0 - Endpoint Control0 | |
#define | USB_ENDPTCTRL0_RXS_MASK (0x1U) |
#define | USB_ENDPTCTRL0_RXS_SHIFT (0U) |
#define | USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) |
#define | USB_ENDPTCTRL0_RXT_MASK (0xCU) |
#define | USB_ENDPTCTRL0_RXT_SHIFT (2U) |
#define | USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) |
#define | USB_ENDPTCTRL0_RXE_MASK (0x80U) |
#define | USB_ENDPTCTRL0_RXE_SHIFT (7U) |
#define | USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) |
#define | USB_ENDPTCTRL0_TXS_MASK (0x10000U) |
#define | USB_ENDPTCTRL0_TXS_SHIFT (16U) |
#define | USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) |
#define | USB_ENDPTCTRL0_TXT_MASK (0xC0000U) |
#define | USB_ENDPTCTRL0_TXT_SHIFT (18U) |
#define | USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) |
#define | USB_ENDPTCTRL0_TXE_MASK (0x800000U) |
#define | USB_ENDPTCTRL0_TXE_SHIFT (23U) |
#define | USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) |
ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 | |
#define | USB_ENDPTCTRL_RXS_MASK (0x1U) |
#define | USB_ENDPTCTRL_RXS_SHIFT (0U) |
#define | USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) |
#define | USB_ENDPTCTRL_RXD_MASK (0x2U) |
#define | USB_ENDPTCTRL_RXD_SHIFT (1U) |
#define | USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) |
#define | USB_ENDPTCTRL_RXT_MASK (0xCU) |
#define | USB_ENDPTCTRL_RXT_SHIFT (2U) |
#define | USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) |
#define | USB_ENDPTCTRL_RXI_MASK (0x20U) |
#define | USB_ENDPTCTRL_RXI_SHIFT (5U) |
#define | USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) |
#define | USB_ENDPTCTRL_RXR_MASK (0x40U) |
#define | USB_ENDPTCTRL_RXR_SHIFT (6U) |
#define | USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) |
#define | USB_ENDPTCTRL_RXE_MASK (0x80U) |
#define | USB_ENDPTCTRL_RXE_SHIFT (7U) |
#define | USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) |
#define | USB_ENDPTCTRL_TXS_MASK (0x10000U) |
#define | USB_ENDPTCTRL_TXS_SHIFT (16U) |
#define | USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) |
#define | USB_ENDPTCTRL_TXD_MASK (0x20000U) |
#define | USB_ENDPTCTRL_TXD_SHIFT (17U) |
#define | USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) |
#define | USB_ENDPTCTRL_TXT_MASK (0xC0000U) |
#define | USB_ENDPTCTRL_TXT_SHIFT (18U) |
#define | USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) |
#define | USB_ENDPTCTRL_TXI_MASK (0x200000U) |
#define | USB_ENDPTCTRL_TXI_SHIFT (21U) |
#define | USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) |
#define | USB_ENDPTCTRL_TXR_MASK (0x400000U) |
#define | USB_ENDPTCTRL_TXR_SHIFT (22U) |
#define | USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) |
#define | USB_ENDPTCTRL_TXE_MASK (0x800000U) |
#define | USB_ENDPTCTRL_TXE_SHIFT (23U) |
#define | USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) |
CONTROL - Control register | |
#define | USBHSDCD_CONTROL_IACK_MASK (0x1U) |
#define | USBHSDCD_CONTROL_IACK_SHIFT (0U) |
#define | USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK) |
#define | USBHSDCD_CONTROL_IF_MASK (0x100U) |
#define | USBHSDCD_CONTROL_IF_SHIFT (8U) |
#define | USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK) |
#define | USBHSDCD_CONTROL_IE_MASK (0x10000U) |
#define | USBHSDCD_CONTROL_IE_SHIFT (16U) |
#define | USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK) |
#define | USBHSDCD_CONTROL_BC12_MASK (0x20000U) |
#define | USBHSDCD_CONTROL_BC12_SHIFT (17U) |
#define | USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK) |
#define | USBHSDCD_CONTROL_START_MASK (0x1000000U) |
#define | USBHSDCD_CONTROL_START_SHIFT (24U) |
#define | USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK) |
#define | USBHSDCD_CONTROL_SR_MASK (0x2000000U) |
#define | USBHSDCD_CONTROL_SR_SHIFT (25U) |
#define | USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK) |
CLOCK - Clock register | |
#define | USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) |
#define | USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) |
#define | USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK) |
#define | USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) |
#define | USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) |
#define | USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK) |
STATUS - Status register | |
#define | USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U) |
#define | USBHSDCD_STATUS_SEQ_RES_SHIFT (16U) |
#define | USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK) |
#define | USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U) |
#define | USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U) |
#define | USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK) |
#define | USBHSDCD_STATUS_ERR_MASK (0x100000U) |
#define | USBHSDCD_STATUS_ERR_SHIFT (20U) |
#define | USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK) |
#define | USBHSDCD_STATUS_TO_MASK (0x200000U) |
#define | USBHSDCD_STATUS_TO_SHIFT (21U) |
#define | USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK) |
#define | USBHSDCD_STATUS_ACTIVE_MASK (0x400000U) |
#define | USBHSDCD_STATUS_ACTIVE_SHIFT (22U) |
#define | USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK) |
SIGNAL_OVERRIDE - Signal Override Register | |
#define | USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U) |
#define | USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U) |
#define | USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK) |
TIMER0 - TIMER0 register | |
#define | USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU) |
#define | USBHSDCD_TIMER0_TUNITCON_SHIFT (0U) |
#define | USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK) |
#define | USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) |
#define | USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U) |
#define | USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK) |
TIMER1 - TIMER1 register | |
#define | USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) |
#define | USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) |
#define | USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK) |
#define | USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) |
#define | USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U) |
#define | USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK) |
TIMER2_BC11 - TIMER2_BC11 register | |
#define | USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) |
#define | USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) |
#define | USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK) |
#define | USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) |
#define | USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) |
#define | USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK) |
TIMER2_BC12 - TIMER2_BC12 register | |
#define | USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) |
#define | USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) |
#define | USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK) |
#define | USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) |
#define | USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) |
#define | USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) |
CTRL1 - USB OTG Control 1 Register | |
#define | USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) |
#define | USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) |
#define | USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) |
#define | USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) |
#define | USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) |
#define | USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK) |
#define | USBNC_CTRL1_PWR_POL_MASK (0x200U) |
#define | USBNC_CTRL1_PWR_POL_SHIFT (9U) |
#define | USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK) |
#define | USBNC_CTRL1_WIE_MASK (0x400U) |
#define | USBNC_CTRL1_WIE_SHIFT (10U) |
#define | USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK) |
#define | USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) |
#define | USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) |
#define | USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) |
#define | USBNC_CTRL1_WKUP_SW_MASK (0x8000U) |
#define | USBNC_CTRL1_WKUP_SW_SHIFT (15U) |
#define | USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK) |
#define | USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) |
#define | USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) |
#define | USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) |
#define | USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) |
#define | USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) |
#define | USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) |
#define | USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) |
#define | USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) |
#define | USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) |
#define | USBNC_CTRL1_WIR_MASK (0x80000000U) |
#define | USBNC_CTRL1_WIR_SHIFT (31U) |
#define | USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) |
CTRL2 - USB OTG Control 2 Register | |
#define | USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) |
#define | USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) |
#define | USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK) |
#define | USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U) |
#define | USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U) |
#define | USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK) |
#define | USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) |
#define | USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) |
#define | USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) |
#define | USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) |
#define | USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) |
#define | USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) |
HSIC_CTRL - USB Host HSIC Control Register | |
#define | USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK (0x800U) |
#define | USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT (11U) |
#define | USBNC_HSIC_CTRL_HSIC_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK) |
#define | USBNC_HSIC_CTRL_HSIC_EN_MASK (0x1000U) |
#define | USBNC_HSIC_CTRL_HSIC_EN_SHIFT (12U) |
#define | USBNC_HSIC_CTRL_HSIC_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK) |
#define | USBNC_HSIC_CTRL_CLK_VLD_MASK (0x80000000U) |
#define | USBNC_HSIC_CTRL_CLK_VLD_SHIFT (31U) |
#define | USBNC_HSIC_CTRL_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK) |
PWD - USB PHY Power-Down Register | |
#define | USBPHY_PWD_TXPWDFS_MASK (0x400U) |
#define | USBPHY_PWD_TXPWDFS_SHIFT (10U) |
#define | USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) |
#define | USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) |
#define | USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) |
#define | USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) |
#define | USBPHY_PWD_TXPWDV2I_MASK (0x1000U) |
#define | USBPHY_PWD_TXPWDV2I_SHIFT (12U) |
#define | USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) |
#define | USBPHY_PWD_RXPWDENV_MASK (0x20000U) |
#define | USBPHY_PWD_RXPWDENV_SHIFT (17U) |
#define | USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) |
#define | USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) |
#define | USBPHY_PWD_RXPWD1PT1_SHIFT (18U) |
#define | USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) |
#define | USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) |
#define | USBPHY_PWD_RXPWDDIFF_SHIFT (19U) |
#define | USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) |
#define | USBPHY_PWD_RXPWDRX_MASK (0x100000U) |
#define | USBPHY_PWD_RXPWDRX_SHIFT (20U) |
#define | USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) |
PWD_SET - USB PHY Power-Down Register | |
#define | USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) |
#define | USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) |
#define | USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) |
#define | USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) |
#define | USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) |
#define | USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) |
#define | USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) |
#define | USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) |
#define | USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) |
#define | USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) |
#define | USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) |
#define | USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) |
#define | USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) |
#define | USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) |
#define | USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) |
#define | USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) |
#define | USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) |
#define | USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) |
#define | USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) |
#define | USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) |
#define | USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) |
PWD_CLR - USB PHY Power-Down Register | |
#define | USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) |
#define | USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) |
#define | USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) |
#define | USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) |
#define | USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) |
#define | USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) |
#define | USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) |
#define | USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) |
#define | USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) |
#define | USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) |
#define | USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) |
#define | USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) |
#define | USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) |
#define | USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) |
#define | USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) |
#define | USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) |
#define | USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) |
#define | USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) |
#define | USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) |
#define | USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) |
#define | USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) |
PWD_TOG - USB PHY Power-Down Register | |
#define | USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) |
#define | USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) |
#define | USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) |
#define | USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) |
#define | USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) |
#define | USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) |
#define | USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) |
#define | USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) |
#define | USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) |
#define | USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) |
#define | USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) |
#define | USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) |
#define | USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) |
#define | USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) |
#define | USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) |
#define | USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) |
#define | USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) |
#define | USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) |
#define | USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) |
#define | USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) |
#define | USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) |
TX - USB PHY Transmitter Control Register | |
#define | USBPHY_TX_D_CAL_MASK (0xFU) |
#define | USBPHY_TX_D_CAL_SHIFT (0U) |
#define | USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) |
#define | USBPHY_TX_TXCAL45DN_MASK (0xF00U) |
#define | USBPHY_TX_TXCAL45DN_SHIFT (8U) |
#define | USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) |
#define | USBPHY_TX_TXCAL45DP_MASK (0xF0000U) |
#define | USBPHY_TX_TXCAL45DP_SHIFT (16U) |
#define | USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) |
TX_SET - USB PHY Transmitter Control Register | |
#define | USBPHY_TX_SET_D_CAL_MASK (0xFU) |
#define | USBPHY_TX_SET_D_CAL_SHIFT (0U) |
#define | USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) |
#define | USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) |
#define | USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) |
#define | USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) |
#define | USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) |
#define | USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) |
#define | USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) |
TX_CLR - USB PHY Transmitter Control Register | |
#define | USBPHY_TX_CLR_D_CAL_MASK (0xFU) |
#define | USBPHY_TX_CLR_D_CAL_SHIFT (0U) |
#define | USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) |
#define | USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) |
#define | USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) |
#define | USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) |
#define | USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) |
#define | USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) |
#define | USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) |
TX_TOG - USB PHY Transmitter Control Register | |
#define | USBPHY_TX_TOG_D_CAL_MASK (0xFU) |
#define | USBPHY_TX_TOG_D_CAL_SHIFT (0U) |
#define | USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) |
#define | USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) |
#define | USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) |
#define | USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) |
#define | USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) |
#define | USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) |
#define | USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) |
RX - USB PHY Receiver Control Register | |
#define | USBPHY_RX_ENVADJ_MASK (0x7U) |
#define | USBPHY_RX_ENVADJ_SHIFT (0U) |
#define | USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) |
#define | USBPHY_RX_DISCONADJ_MASK (0x70U) |
#define | USBPHY_RX_DISCONADJ_SHIFT (4U) |
#define | USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) |
#define | USBPHY_RX_RXDBYPASS_MASK (0x400000U) |
#define | USBPHY_RX_RXDBYPASS_SHIFT (22U) |
#define | USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) |
RX_SET - USB PHY Receiver Control Register | |
#define | USBPHY_RX_SET_ENVADJ_MASK (0x7U) |
#define | USBPHY_RX_SET_ENVADJ_SHIFT (0U) |
#define | USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) |
#define | USBPHY_RX_SET_DISCONADJ_MASK (0x70U) |
#define | USBPHY_RX_SET_DISCONADJ_SHIFT (4U) |
#define | USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) |
#define | USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) |
#define | USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) |
#define | USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) |
RX_CLR - USB PHY Receiver Control Register | |
#define | USBPHY_RX_CLR_ENVADJ_MASK (0x7U) |
#define | USBPHY_RX_CLR_ENVADJ_SHIFT (0U) |
#define | USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) |
#define | USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) |
#define | USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) |
#define | USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) |
#define | USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) |
#define | USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) |
#define | USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) |
RX_TOG - USB PHY Receiver Control Register | |
#define | USBPHY_RX_TOG_ENVADJ_MASK (0x7U) |
#define | USBPHY_RX_TOG_ENVADJ_SHIFT (0U) |
#define | USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) |
#define | USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) |
#define | USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) |
#define | USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) |
#define | USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) |
#define | USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) |
#define | USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) |
CTRL - USB PHY General Control Register | |
#define | USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) |
#define | USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) |
#define | USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) |
#define | USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) |
#define | USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) |
#define | USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) |
#define | USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) |
#define | USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) |
#define | USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) |
#define | USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) |
#define | USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) |
#define | USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) |
#define | USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) |
#define | USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) |
#define | USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) |
#define | USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) |
#define | USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) |
#define | USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) |
#define | USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) |
#define | USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) |
#define | USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) |
#define | USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) |
#define | USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) |
#define | USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) |
#define | USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) |
#define | USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) |
#define | USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) |
#define | USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) |
#define | USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) |
#define | USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) |
#define | USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) |
#define | USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) |
#define | USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) |
#define | USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) |
#define | USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) |
#define | USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) |
#define | USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) |
#define | USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) |
#define | USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) |
#define | USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) |
#define | USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) |
#define | USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) |
#define | USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) |
#define | USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) |
#define | USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) |
#define | USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) |
#define | USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) |
#define | USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) |
#define | USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) |
#define | USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) |
#define | USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) |
#define | USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) |
#define | USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) |
#define | USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) |
#define | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) |
#define | USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) |
#define | USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) |
#define | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) |
#define | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) |
#define | USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) |
#define | USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) |
#define | USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) |
#define | USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) |
#define | USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) |
#define | USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) |
#define | USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) |
#define | USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) |
#define | USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) |
#define | USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) |
#define | USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) |
#define | USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) |
#define | USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) |
#define | USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) |
#define | USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) |
#define | USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) |
#define | USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) |
#define | USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) |
#define | USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) |
#define | USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) |
#define | USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) |
#define | USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) |
#define | USBPHY_CTRL_CLKGATE_MASK (0x40000000U) |
#define | USBPHY_CTRL_CLKGATE_SHIFT (30U) |
#define | USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) |
#define | USBPHY_CTRL_SFTRST_MASK (0x80000000U) |
#define | USBPHY_CTRL_SFTRST_SHIFT (31U) |
#define | USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) |
CTRL_SET - USB PHY General Control Register | |
#define | USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) |
#define | USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) |
#define | USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) |
#define | USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) |
#define | USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) |
#define | USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) |
#define | USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) |
#define | USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) |
#define | USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) |
#define | USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) |
#define | USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) |
#define | USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) |
#define | USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) |
#define | USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) |
#define | USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) |
#define | USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) |
#define | USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) |
#define | USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) |
#define | USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) |
#define | USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) |
#define | USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) |
#define | USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) |
#define | USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) |
#define | USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) |
#define | USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) |
#define | USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) |
#define | USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) |
#define | USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) |
#define | USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) |
#define | USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) |
#define | USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) |
#define | USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) |
#define | USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) |
#define | USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) |
#define | USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) |
#define | USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) |
#define | USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) |
#define | USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) |
#define | USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) |
#define | USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) |
#define | USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) |
#define | USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) |
#define | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) |
#define | USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) |
#define | USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) |
#define | USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) |
#define | USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) |
#define | USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) |
#define | USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) |
#define | USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) |
#define | USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) |
#define | USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) |
#define | USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) |
#define | USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) |
#define | USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) |
#define | USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) |
#define | USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) |
#define | USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) |
#define | USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) |
#define | USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) |
#define | USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) |
#define | USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) |
#define | USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) |
#define | USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) |
#define | USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) |
#define | USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) |
#define | USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) |
#define | USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) |
#define | USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) |
#define | USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) |
#define | USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) |
#define | USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) |
#define | USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) |
#define | USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) |
#define | USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) |
#define | USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) |
#define | USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) |
#define | USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) |
#define | USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) |
#define | USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) |
#define | USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) |
#define | USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) |
#define | USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) |
#define | USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) |
#define | USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) |
#define | USBPHY_CTRL_SET_SFTRST_SHIFT (31U) |
#define | USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) |
CTRL_CLR - USB PHY General Control Register | |
#define | USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) |
#define | USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) |
#define | USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) |
#define | USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) |
#define | USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) |
#define | USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) |
#define | USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) |
#define | USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) |
#define | USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) |
#define | USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) |
#define | USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) |
#define | USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) |
#define | USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) |
#define | USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) |
#define | USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) |
#define | USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) |
#define | USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) |
#define | USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) |
#define | USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) |
#define | USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) |
#define | USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) |
#define | USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) |
#define | USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) |
#define | USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) |
#define | USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) |
#define | USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) |
#define | USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) |
#define | USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) |
#define | USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) |
#define | USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) |
#define | USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) |
#define | USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) |
#define | USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) |
#define | USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) |
#define | USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) |
#define | USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) |
#define | USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) |
#define | USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) |
#define | USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) |
#define | USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) |
#define | USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) |
#define | USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) |
#define | USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) |
#define | USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) |
#define | USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) |
#define | USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) |
#define | USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) |
#define | USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) |
#define | USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) |
#define | USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) |
#define | USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) |
#define | USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) |
#define | USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) |
#define | USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) |
#define | USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) |
#define | USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) |
#define | USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) |
#define | USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) |
#define | USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) |
#define | USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) |
#define | USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) |
#define | USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) |
#define | USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) |
#define | USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) |
#define | USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) |
#define | USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) |
#define | USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) |
#define | USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) |
#define | USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) |
#define | USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) |
#define | USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) |
#define | USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) |
#define | USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) |
#define | USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) |
#define | USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) |
#define | USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) |
#define | USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) |
#define | USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) |
#define | USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) |
#define | USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) |
#define | USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) |
#define | USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) |
#define | USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) |
#define | USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) |
#define | USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) |
#define | USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) |
#define | USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) |
CTRL_TOG - USB PHY General Control Register | |
#define | USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) |
#define | USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) |
#define | USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) |
#define | USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) |
#define | USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) |
#define | USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) |
#define | USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) |
#define | USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) |
#define | USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) |
#define | USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) |
#define | USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) |
#define | USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) |
#define | USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) |
#define | USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) |
#define | USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) |
#define | USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) |
#define | USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) |
#define | USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) |
#define | USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) |
#define | USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) |
#define | USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) |
#define | USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) |
#define | USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) |
#define | USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) |
#define | USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) |
#define | USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) |
#define | USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) |
#define | USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) |
#define | USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) |
#define | USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) |
#define | USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) |
#define | USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) |
#define | USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) |
#define | USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) |
#define | USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) |
#define | USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) |
#define | USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) |
#define | USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) |
#define | USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) |
#define | USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) |
#define | USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) |
#define | USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) |
#define | USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) |
#define | USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) |
#define | USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) |
#define | USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) |
#define | USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) |
#define | USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) |
#define | USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) |
#define | USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) |
#define | USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) |
#define | USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) |
#define | USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) |
#define | USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) |
#define | USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) |
#define | USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) |
#define | USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) |
#define | USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) |
#define | USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) |
#define | USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) |
#define | USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) |
#define | USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) |
#define | USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) |
#define | USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) |
#define | USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) |
#define | USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) |
#define | USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) |
#define | USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) |
#define | USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) |
#define | USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) |
#define | USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) |
#define | USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) |
#define | USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) |
#define | USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) |
#define | USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) |
#define | USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) |
#define | USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) |
#define | USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) |
#define | USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) |
#define | USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) |
#define | USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) |
#define | USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) |
#define | USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) |
#define | USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) |
#define | USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) |
#define | USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) |
#define | USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) |
STATUS - USB PHY Status Register | |
#define | USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) |
#define | USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) |
#define | USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) |
#define | USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) |
#define | USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) |
#define | USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) |
#define | USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) |
#define | USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) |
#define | USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) |
#define | USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) |
#define | USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) |
#define | USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) |
DEBUG - USB PHY Debug Register | |
#define | USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) |
#define | USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) |
#define | USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) |
#define | USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) |
#define | USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) |
#define | USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) |
#define | USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) |
#define | USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) |
#define | USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) |
#define | USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) |
#define | USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) |
#define | USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) |
#define | USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) |
#define | USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) |
#define | USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) |
#define | USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) |
#define | USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) |
#define | USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) |
#define | USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) |
#define | USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) |
#define | USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) |
#define | USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) |
#define | USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) |
#define | USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) |
#define | USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) |
#define | USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) |
#define | USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) |
#define | USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) |
#define | USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) |
#define | USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) |
#define | USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) |
#define | USBPHY_DEBUG_CLKGATE_SHIFT (30U) |
#define | USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) |
DEBUG_SET - USB PHY Debug Register | |
#define | USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) |
#define | USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) |
#define | USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) |
#define | USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) |
#define | USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) |
#define | USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) |
#define | USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) |
#define | USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) |
#define | USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) |
#define | USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) |
#define | USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) |
#define | USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) |
#define | USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) |
#define | USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) |
#define | USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) |
#define | USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) |
#define | USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) |
#define | USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) |
#define | USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) |
#define | USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) |
#define | USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) |
#define | USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) |
#define | USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) |
#define | USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) |
#define | USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) |
#define | USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) |
#define | USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) |
#define | USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) |
#define | USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) |
#define | USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) |
#define | USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) |
#define | USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) |
#define | USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) |
DEBUG_CLR - USB PHY Debug Register | |
#define | USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) |
#define | USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) |
#define | USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) |
#define | USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) |
#define | USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) |
#define | USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) |
#define | USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) |
#define | USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) |
#define | USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) |
#define | USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) |
#define | USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) |
#define | USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) |
#define | USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) |
#define | USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) |
#define | USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) |
#define | USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) |
#define | USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) |
#define | USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) |
#define | USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) |
#define | USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) |
#define | USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) |
#define | USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) |
#define | USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) |
#define | USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) |
#define | USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) |
#define | USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) |
#define | USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) |
#define | USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) |
#define | USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) |
#define | USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) |
#define | USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) |
#define | USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) |
#define | USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) |
DEBUG_TOG - USB PHY Debug Register | |
#define | USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) |
#define | USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) |
#define | USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) |
#define | USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) |
#define | USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) |
#define | USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) |
#define | USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) |
#define | USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) |
#define | USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) |
#define | USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) |
#define | USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) |
#define | USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) |
#define | USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) |
#define | USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) |
#define | USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) |
#define | USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) |
#define | USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) |
#define | USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) |
#define | USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) |
#define | USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) |
#define | USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) |
#define | USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) |
#define | USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) |
#define | USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) |
#define | USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) |
#define | USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) |
#define | USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) |
#define | USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) |
#define | USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) |
#define | USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) |
#define | USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) |
#define | USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) |
#define | USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) |
DEBUG0_STATUS - UTMI Debug Status Register 0 | |
#define | USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) |
#define | USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) |
#define | USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) |
#define | USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) |
#define | USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) |
#define | USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) |
#define | USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) |
#define | USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) |
#define | USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) |
DEBUG1 - UTMI Debug Status Register 1 | |
#define | USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) |
#define | USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) |
#define | USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT (16U) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK (0x20000U) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT (17U) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U) |
#define | USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK) |
DEBUG1_SET - UTMI Debug Status Register 1 | |
#define | USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) |
#define | USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) |
#define | USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT (16U) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK (0x20000U) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT (17U) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U) |
#define | USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK) |
DEBUG1_CLR - UTMI Debug Status Register 1 | |
#define | USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) |
#define | USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) |
#define | USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT (16U) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK (0x20000U) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT (17U) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U) |
#define | USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK) |
DEBUG1_TOG - UTMI Debug Status Register 1 | |
#define | USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) |
#define | USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) |
#define | USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT (16U) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK (0x20000U) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT (17U) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U) |
#define | USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK) |
VERSION - UTMI RTL Version | |
#define | USBPHY_VERSION_STEP_MASK (0xFFFFU) |
#define | USBPHY_VERSION_STEP_SHIFT (0U) |
#define | USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) |
#define | USBPHY_VERSION_MINOR_MASK (0xFF0000U) |
#define | USBPHY_VERSION_MINOR_SHIFT (16U) |
#define | USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) |
#define | USBPHY_VERSION_MAJOR_MASK (0xFF000000U) |
#define | USBPHY_VERSION_MAJOR_SHIFT (24U) |
#define | USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) |
PLL_SIC - USB PHY PLL Control/Status Register | |
#define | USBPHY_PLL_SIC_PLL_POSTDIV_MASK (0x1CU) |
#define | USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT (2U) |
#define | USBPHY_PLL_SIC_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_POSTDIV_MASK) |
#define | USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) |
#define | USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) |
#define | USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) |
#define | USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) |
#define | USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) |
#define | USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) |
#define | USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) |
#define | USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) |
#define | USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) |
#define | USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) |
#define | USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) |
#define | USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) |
#define | USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) |
#define | USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) |
#define | USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) |
#define | USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) |
#define | USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) |
#define | USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) |
#define | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) |
#define | USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) |
#define | USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) |
#define | USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) |
#define | USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) |
#define | USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) |
#define | USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) |
#define | USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) |
#define | USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) |
PLL_SIC_SET - USB PHY PLL Control/Status Register | |
#define | USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK (0x1CU) |
#define | USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT (2U) |
#define | USBPHY_PLL_SIC_SET_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK) |
#define | USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) |
#define | USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) |
#define | USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) |
#define | USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) |
#define | USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) |
#define | USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) |
#define | USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) |
#define | USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) |
#define | USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) |
#define | USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) |
#define | USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) |
#define | USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) |
#define | USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) |
#define | USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) |
#define | USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) |
#define | USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) |
#define | USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) |
#define | USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) |
#define | USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) |
#define | USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) |
#define | USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) |
#define | USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) |
#define | USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) |
#define | USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) |
#define | USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) |
#define | USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) |
#define | USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) |
PLL_SIC_CLR - USB PHY PLL Control/Status Register | |
#define | USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK (0x1CU) |
#define | USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT (2U) |
#define | USBPHY_PLL_SIC_CLR_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK) |
#define | USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) |
#define | USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) |
#define | USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) |
#define | USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) |
#define | USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) |
#define | USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) |
#define | USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) |
#define | USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) |
#define | USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) |
#define | USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) |
#define | USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) |
#define | USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) |
#define | USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) |
#define | USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) |
#define | USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) |
#define | USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) |
#define | USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) |
#define | USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) |
#define | USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) |
#define | USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) |
#define | USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) |
#define | USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) |
#define | USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) |
#define | USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) |
#define | USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) |
#define | USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) |
#define | USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) |
PLL_SIC_TOG - USB PHY PLL Control/Status Register | |
#define | USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK (0x1CU) |
#define | USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT (2U) |
#define | USBPHY_PLL_SIC_TOG_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK) |
#define | USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) |
#define | USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) |
#define | USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) |
#define | USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) |
#define | USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) |
#define | USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) |
#define | USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) |
#define | USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) |
#define | USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) |
#define | USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) |
#define | USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) |
#define | USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) |
#define | USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) |
#define | USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) |
#define | USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) |
#define | USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) |
#define | USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) |
#define | USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) |
#define | USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) |
#define | USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) |
#define | USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) |
#define | USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) |
#define | USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) |
#define | USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) |
#define | USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) |
#define | USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) |
#define | USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) |
USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register | |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) |
#define | USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) |
#define | USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) |
#define | USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) |
#define | USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) |
#define | USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) |
#define | USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) |
#define | USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) |
#define | USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) |
#define | USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) |
#define | USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) |
#define | USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) |
#define | USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) |
#define | USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) |
#define | USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) |
#define | USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U) |
#define | USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U) |
#define | USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK) |
USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register | |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U) |
#define | USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK) |
USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register | |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U) |
#define | USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK) |
USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register | |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U) |
#define | USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK) |
USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register | |
#define | USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) |
#define | USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) |
#define | USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) |
#define | USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) |
#define | USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) |
#define | USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) |
#define | USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) |
#define | USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) |
#define | USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) |
#define | USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) |
#define | USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) |
#define | USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) |
#define | USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) |
#define | USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) |
#define | USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) |
USB1_CHRG_DETECT - USB PHY Charger Detect Control Register | |
#define | USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) |
#define | USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) |
#define | USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) |
#define | USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK (0x800000U) |
#define | USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT (23U) |
#define | USBPHY_USB1_CHRG_DETECT_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK) |
USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register | |
#define | USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) |
#define | USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) |
#define | USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) |
#define | USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK (0x800000U) |
#define | USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT (23U) |
#define | USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK) |
USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register | |
#define | USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) |
#define | USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) |
#define | USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) |
#define | USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK (0x800000U) |
#define | USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT (23U) |
#define | USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK) |
USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register | |
#define | USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) |
#define | USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) |
#define | USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) |
#define | USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK (0x800000U) |
#define | USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT (23U) |
#define | USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK) |
USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register | |
#define | USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) |
#define | USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) |
#define | USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) |
#define | USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) |
#define | USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) |
#define | USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) |
#define | USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK (0x4U) |
#define | USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT (2U) |
#define | USBPHY_USB1_CHRG_DET_STAT_DN_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK) |
#define | USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) |
#define | USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) |
#define | USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) |
#define | USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) |
#define | USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) |
#define | USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) |
ANACTRL - USB PHY Analog Control Register | |
#define | USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) |
#define | USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) |
#define | USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) |
ANACTRL_SET - USB PHY Analog Control Register | |
#define | USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) |
#define | USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) |
#define | USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) |
ANACTRL_CLR - USB PHY Analog Control Register | |
#define | USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) |
#define | USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) |
#define | USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) |
ANACTRL_TOG - USB PHY Analog Control Register | |
#define | USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) |
#define | USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) |
#define | USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) |
USB1_LOOPBACK - USB PHY Loopback Control/Status Register | |
#define | USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U) |
#define | USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U) |
#define | USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK) |
#define | USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U) |
#define | USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U) |
#define | USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK) |
#define | USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U) |
#define | USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U) |
#define | USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U) |
#define | USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK) |
#define | USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U) |
#define | USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U) |
#define | USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK) |
#define | USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U) |
#define | USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U) |
#define | USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK) |
#define | USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U) |
#define | USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U) |
#define | USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK) |
#define | USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U) |
#define | USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U) |
#define | USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK) |
USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register | |
#define | USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U) |
#define | USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U) |
#define | USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK) |
USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register | |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U) |
#define | USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U) |
#define | USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK) |
USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register | |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U) |
#define | USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U) |
#define | USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK) |
USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register | |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK) |
USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register | |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK) |
USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register | |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK) |
USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register | |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U) |
#define | USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK) |
TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register | |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK) |
TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register | |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U) |
#define | USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK) |
TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register | |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U) |
#define | USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK) |
TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register | |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U) |
#define | USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK) |
DS_ADDR - DMA System Address | |
#define | USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) |
#define | USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) |
#define | USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) |
BLK_ATT - Block Attributes | |
#define | USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) |
#define | USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) |
#define | USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) |
#define | USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) |
#define | USDHC_BLK_ATT_BLKCNT_SHIFT (16U) |
#define | USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) |
CMD_ARG - Command Argument | |
#define | USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) |
#define | USDHC_CMD_ARG_CMDARG_SHIFT (0U) |
#define | USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) |
CMD_XFR_TYP - Command Transfer Type | |
#define | USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) |
#define | USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) |
#define | USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) |
#define | USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) |
#define | USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) |
#define | USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) |
#define | USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) |
#define | USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) |
#define | USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) |
#define | USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) |
#define | USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) |
#define | USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) |
#define | USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) |
#define | USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) |
#define | USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) |
#define | USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) |
#define | USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) |
#define | USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) |
CMD_RSP0 - Command Response0 | |
#define | USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) |
#define | USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) |
#define | USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) |
CMD_RSP1 - Command Response1 | |
#define | USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) |
#define | USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) |
#define | USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) |
CMD_RSP2 - Command Response2 | |
#define | USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) |
#define | USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) |
#define | USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) |
CMD_RSP3 - Command Response3 | |
#define | USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) |
#define | USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) |
#define | USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) |
DATA_BUFF_ACC_PORT - Data Buffer Access Port | |
#define | USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) |
#define | USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) |
#define | USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) |
PRES_STATE - Present State | |
#define | USDHC_PRES_STATE_CIHB_MASK (0x1U) |
#define | USDHC_PRES_STATE_CIHB_SHIFT (0U) |
#define | USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) |
#define | USDHC_PRES_STATE_CDIHB_MASK (0x2U) |
#define | USDHC_PRES_STATE_CDIHB_SHIFT (1U) |
#define | USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) |
#define | USDHC_PRES_STATE_DLA_MASK (0x4U) |
#define | USDHC_PRES_STATE_DLA_SHIFT (2U) |
#define | USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) |
#define | USDHC_PRES_STATE_SDSTB_MASK (0x8U) |
#define | USDHC_PRES_STATE_SDSTB_SHIFT (3U) |
#define | USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) |
#define | USDHC_PRES_STATE_IPGOFF_MASK (0x10U) |
#define | USDHC_PRES_STATE_IPGOFF_SHIFT (4U) |
#define | USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) |
#define | USDHC_PRES_STATE_HCKOFF_MASK (0x20U) |
#define | USDHC_PRES_STATE_HCKOFF_SHIFT (5U) |
#define | USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) |
#define | USDHC_PRES_STATE_PEROFF_MASK (0x40U) |
#define | USDHC_PRES_STATE_PEROFF_SHIFT (6U) |
#define | USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) |
#define | USDHC_PRES_STATE_SDOFF_MASK (0x80U) |
#define | USDHC_PRES_STATE_SDOFF_SHIFT (7U) |
#define | USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) |
#define | USDHC_PRES_STATE_WTA_MASK (0x100U) |
#define | USDHC_PRES_STATE_WTA_SHIFT (8U) |
#define | USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) |
#define | USDHC_PRES_STATE_RTA_MASK (0x200U) |
#define | USDHC_PRES_STATE_RTA_SHIFT (9U) |
#define | USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) |
#define | USDHC_PRES_STATE_BWEN_MASK (0x400U) |
#define | USDHC_PRES_STATE_BWEN_SHIFT (10U) |
#define | USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) |
#define | USDHC_PRES_STATE_BREN_MASK (0x800U) |
#define | USDHC_PRES_STATE_BREN_SHIFT (11U) |
#define | USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) |
#define | USDHC_PRES_STATE_RTR_MASK (0x1000U) |
#define | USDHC_PRES_STATE_RTR_SHIFT (12U) |
#define | USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) |
#define | USDHC_PRES_STATE_TSCD_MASK (0x8000U) |
#define | USDHC_PRES_STATE_TSCD_SHIFT (15U) |
#define | USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) |
#define | USDHC_PRES_STATE_CINST_MASK (0x10000U) |
#define | USDHC_PRES_STATE_CINST_SHIFT (16U) |
#define | USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) |
#define | USDHC_PRES_STATE_CDPL_MASK (0x40000U) |
#define | USDHC_PRES_STATE_CDPL_SHIFT (18U) |
#define | USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) |
#define | USDHC_PRES_STATE_WPSPL_MASK (0x80000U) |
#define | USDHC_PRES_STATE_WPSPL_SHIFT (19U) |
#define | USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) |
#define | USDHC_PRES_STATE_CLSL_MASK (0x800000U) |
#define | USDHC_PRES_STATE_CLSL_SHIFT (23U) |
#define | USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) |
#define | USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) |
#define | USDHC_PRES_STATE_DLSL_SHIFT (24U) |
#define | USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) |
PROT_CTRL - Protocol Control | |
#define | USDHC_PROT_CTRL_DTW_MASK (0x6U) |
#define | USDHC_PROT_CTRL_DTW_SHIFT (1U) |
#define | USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) |
#define | USDHC_PROT_CTRL_D3CD_MASK (0x8U) |
#define | USDHC_PROT_CTRL_D3CD_SHIFT (3U) |
#define | USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) |
#define | USDHC_PROT_CTRL_EMODE_MASK (0x30U) |
#define | USDHC_PROT_CTRL_EMODE_SHIFT (4U) |
#define | USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) |
#define | USDHC_PROT_CTRL_CDTL_MASK (0x40U) |
#define | USDHC_PROT_CTRL_CDTL_SHIFT (6U) |
#define | USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) |
#define | USDHC_PROT_CTRL_CDSS_MASK (0x80U) |
#define | USDHC_PROT_CTRL_CDSS_SHIFT (7U) |
#define | USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) |
#define | USDHC_PROT_CTRL_DMASEL_MASK (0x300U) |
#define | USDHC_PROT_CTRL_DMASEL_SHIFT (8U) |
#define | USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) |
#define | USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) |
#define | USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) |
#define | USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) |
#define | USDHC_PROT_CTRL_CREQ_MASK (0x20000U) |
#define | USDHC_PROT_CTRL_CREQ_SHIFT (17U) |
#define | USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) |
#define | USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) |
#define | USDHC_PROT_CTRL_RWCTL_SHIFT (18U) |
#define | USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) |
#define | USDHC_PROT_CTRL_IABG_MASK (0x80000U) |
#define | USDHC_PROT_CTRL_IABG_SHIFT (19U) |
#define | USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) |
#define | USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) |
#define | USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) |
#define | USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) |
#define | USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) |
#define | USDHC_PROT_CTRL_WECINT_SHIFT (24U) |
#define | USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) |
#define | USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) |
#define | USDHC_PROT_CTRL_WECINS_SHIFT (25U) |
#define | USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) |
#define | USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) |
#define | USDHC_PROT_CTRL_WECRM_SHIFT (26U) |
#define | USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) |
#define | USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) |
#define | USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) |
#define | USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) |
SYS_CTRL - System Control | |
#define | USDHC_SYS_CTRL_DVS_MASK (0xF0U) |
#define | USDHC_SYS_CTRL_DVS_SHIFT (4U) |
#define | USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) |
#define | USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) |
#define | USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) |
#define | USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) |
#define | USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) |
#define | USDHC_SYS_CTRL_DTOCV_SHIFT (16U) |
#define | USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) |
#define | USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) |
#define | USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) |
#define | USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) |
#define | USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) |
#define | USDHC_SYS_CTRL_RSTA_SHIFT (24U) |
#define | USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) |
#define | USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) |
#define | USDHC_SYS_CTRL_RSTC_SHIFT (25U) |
#define | USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) |
#define | USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) |
#define | USDHC_SYS_CTRL_RSTD_SHIFT (26U) |
#define | USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) |
#define | USDHC_SYS_CTRL_INITA_MASK (0x8000000U) |
#define | USDHC_SYS_CTRL_INITA_SHIFT (27U) |
#define | USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) |
#define | USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) |
#define | USDHC_SYS_CTRL_RSTT_SHIFT (28U) |
#define | USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) |
INT_STATUS - Interrupt Status | |
#define | USDHC_INT_STATUS_CC_MASK (0x1U) |
#define | USDHC_INT_STATUS_CC_SHIFT (0U) |
#define | USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) |
#define | USDHC_INT_STATUS_TC_MASK (0x2U) |
#define | USDHC_INT_STATUS_TC_SHIFT (1U) |
#define | USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) |
#define | USDHC_INT_STATUS_BGE_MASK (0x4U) |
#define | USDHC_INT_STATUS_BGE_SHIFT (2U) |
#define | USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) |
#define | USDHC_INT_STATUS_DINT_MASK (0x8U) |
#define | USDHC_INT_STATUS_DINT_SHIFT (3U) |
#define | USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) |
#define | USDHC_INT_STATUS_BWR_MASK (0x10U) |
#define | USDHC_INT_STATUS_BWR_SHIFT (4U) |
#define | USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) |
#define | USDHC_INT_STATUS_BRR_MASK (0x20U) |
#define | USDHC_INT_STATUS_BRR_SHIFT (5U) |
#define | USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) |
#define | USDHC_INT_STATUS_CINS_MASK (0x40U) |
#define | USDHC_INT_STATUS_CINS_SHIFT (6U) |
#define | USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) |
#define | USDHC_INT_STATUS_CRM_MASK (0x80U) |
#define | USDHC_INT_STATUS_CRM_SHIFT (7U) |
#define | USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) |
#define | USDHC_INT_STATUS_CINT_MASK (0x100U) |
#define | USDHC_INT_STATUS_CINT_SHIFT (8U) |
#define | USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) |
#define | USDHC_INT_STATUS_RTE_MASK (0x1000U) |
#define | USDHC_INT_STATUS_RTE_SHIFT (12U) |
#define | USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) |
#define | USDHC_INT_STATUS_TP_MASK (0x4000U) |
#define | USDHC_INT_STATUS_TP_SHIFT (14U) |
#define | USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) |
#define | USDHC_INT_STATUS_CTOE_MASK (0x10000U) |
#define | USDHC_INT_STATUS_CTOE_SHIFT (16U) |
#define | USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) |
#define | USDHC_INT_STATUS_CCE_MASK (0x20000U) |
#define | USDHC_INT_STATUS_CCE_SHIFT (17U) |
#define | USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) |
#define | USDHC_INT_STATUS_CEBE_MASK (0x40000U) |
#define | USDHC_INT_STATUS_CEBE_SHIFT (18U) |
#define | USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) |
#define | USDHC_INT_STATUS_CIE_MASK (0x80000U) |
#define | USDHC_INT_STATUS_CIE_SHIFT (19U) |
#define | USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) |
#define | USDHC_INT_STATUS_DTOE_MASK (0x100000U) |
#define | USDHC_INT_STATUS_DTOE_SHIFT (20U) |
#define | USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) |
#define | USDHC_INT_STATUS_DCE_MASK (0x200000U) |
#define | USDHC_INT_STATUS_DCE_SHIFT (21U) |
#define | USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) |
#define | USDHC_INT_STATUS_DEBE_MASK (0x400000U) |
#define | USDHC_INT_STATUS_DEBE_SHIFT (22U) |
#define | USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) |
#define | USDHC_INT_STATUS_AC12E_MASK (0x1000000U) |
#define | USDHC_INT_STATUS_AC12E_SHIFT (24U) |
#define | USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) |
#define | USDHC_INT_STATUS_TNE_MASK (0x4000000U) |
#define | USDHC_INT_STATUS_TNE_SHIFT (26U) |
#define | USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) |
#define | USDHC_INT_STATUS_DMAE_MASK (0x10000000U) |
#define | USDHC_INT_STATUS_DMAE_SHIFT (28U) |
#define | USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) |
INT_STATUS_EN - Interrupt Status Enable | |
#define | USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) |
#define | USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) |
#define | USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) |
#define | USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) |
#define | USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) |
#define | USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) |
#define | USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) |
#define | USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) |
#define | USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) |
#define | USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) |
#define | USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) |
#define | USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) |
#define | USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) |
#define | USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) |
#define | USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) |
#define | USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) |
#define | USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) |
#define | USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) |
#define | USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) |
#define | USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) |
#define | USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) |
#define | USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) |
#define | USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) |
#define | USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) |
#define | USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) |
#define | USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) |
#define | USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) |
#define | USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) |
#define | USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) |
#define | USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) |
#define | USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) |
#define | USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) |
#define | USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) |
#define | USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) |
#define | USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) |
#define | USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) |
#define | USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) |
#define | USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) |
#define | USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) |
#define | USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) |
#define | USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) |
#define | USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) |
#define | USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) |
#define | USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) |
#define | USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) |
#define | USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) |
#define | USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) |
#define | USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) |
#define | USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) |
#define | USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) |
#define | USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) |
#define | USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) |
#define | USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) |
#define | USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) |
#define | USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) |
#define | USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) |
#define | USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) |
#define | USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) |
#define | USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) |
#define | USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) |
#define | USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) |
#define | USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) |
#define | USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) |
INT_SIGNAL_EN - Interrupt Signal Enable | |
#define | USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) |
#define | USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) |
#define | USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) |
#define | USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) |
#define | USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) |
#define | USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) |
#define | USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) |
#define | USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) |
#define | USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) |
#define | USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) |
#define | USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) |
#define | USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) |
#define | USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) |
#define | USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) |
#define | USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) |
#define | USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) |
#define | USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) |
#define | USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) |
#define | USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) |
#define | USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) |
#define | USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) |
#define | USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) |
#define | USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) |
#define | USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) |
#define | USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) |
#define | USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) |
#define | USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) |
#define | USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) |
#define | USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) |
#define | USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) |
#define | USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) |
#define | USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) |
#define | USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) |
#define | USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) |
#define | USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) |
#define | USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) |
#define | USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) |
#define | USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) |
#define | USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) |
#define | USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) |
#define | USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) |
#define | USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) |
#define | USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) |
#define | USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) |
AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status | |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) |
#define | USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) |
#define | USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) |
#define | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) |
#define | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) |
HOST_CTRL_CAP - Host Controller Capabilities | |
#define | USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) |
#define | USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) |
#define | USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) |
#define | USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) |
#define | USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) |
#define | USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) |
#define | USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) |
#define | USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) |
#define | USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) |
#define | USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) |
#define | USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) |
#define | USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) |
#define | USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) |
#define | USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) |
#define | USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) |
#define | USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) |
#define | USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) |
#define | USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) |
#define | USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) |
#define | USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) |
#define | USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) |
#define | USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) |
#define | USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) |
#define | USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) |
#define | USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) |
#define | USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) |
#define | USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) |
#define | USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) |
#define | USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) |
#define | USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) |
#define | USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) |
#define | USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) |
#define | USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) |
#define | USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) |
#define | USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) |
#define | USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) |
WTMK_LVL - Watermark Level | |
#define | USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) |
#define | USDHC_WTMK_LVL_RD_WML_SHIFT (0U) |
#define | USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) |
#define | USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) |
#define | USDHC_WTMK_LVL_WR_WML_SHIFT (16U) |
#define | USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) |
MIX_CTRL - Mixer Control | |
#define | USDHC_MIX_CTRL_DMAEN_MASK (0x1U) |
#define | USDHC_MIX_CTRL_DMAEN_SHIFT (0U) |
#define | USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) |
#define | USDHC_MIX_CTRL_BCEN_MASK (0x2U) |
#define | USDHC_MIX_CTRL_BCEN_SHIFT (1U) |
#define | USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) |
#define | USDHC_MIX_CTRL_AC12EN_MASK (0x4U) |
#define | USDHC_MIX_CTRL_AC12EN_SHIFT (2U) |
#define | USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) |
#define | USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) |
#define | USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) |
#define | USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) |
#define | USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) |
#define | USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) |
#define | USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) |
#define | USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) |
#define | USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) |
#define | USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) |
#define | USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) |
#define | USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) |
#define | USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) |
#define | USDHC_MIX_CTRL_AC23EN_MASK (0x80U) |
#define | USDHC_MIX_CTRL_AC23EN_SHIFT (7U) |
#define | USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) |
#define | USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) |
#define | USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) |
#define | USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) |
#define | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) |
#define | USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) |
#define | USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) |
#define | USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) |
#define | USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) |
#define | USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) |
#define | USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) |
#define | USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) |
#define | USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) |
#define | USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U) |
#define | USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U) |
#define | USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK) |
FORCE_EVENT - Force Event | |
#define | USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) |
#define | USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) |
#define | USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) |
#define | USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) |
#define | USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) |
#define | USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) |
#define | USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) |
#define | USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) |
#define | USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) |
#define | USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) |
#define | USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) |
#define | USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) |
#define | USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) |
#define | USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) |
#define | USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) |
#define | USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) |
#define | USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) |
#define | USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) |
#define | USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) |
#define | USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) |
#define | USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) |
#define | USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) |
#define | USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) |
#define | USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) |
#define | USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) |
#define | USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) |
#define | USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) |
#define | USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) |
#define | USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) |
#define | USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) |
#define | USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) |
#define | USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) |
#define | USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) |
#define | USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) |
#define | USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) |
#define | USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) |
#define | USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) |
#define | USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) |
ADMA_ERR_STATUS - ADMA Error Status | |
#define | USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) |
#define | USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) |
#define | USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) |
#define | USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) |
#define | USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) |
#define | USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) |
#define | USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) |
#define | USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) |
#define | USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) |
ADMA_SYS_ADDR - ADMA System Address | |
#define | USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) |
#define | USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) |
#define | USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) |
DLL_CTRL - DLL (Delay Line) Control | |
#define | USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) |
#define | USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) |
#define | USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) |
#define | USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) |
#define | USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) |
DLL_STATUS - DLL Status | |
#define | USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) |
#define | USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) |
#define | USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) |
#define | USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) |
#define | USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) |
#define | USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) |
#define | USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) |
#define | USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) |
#define | USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) |
#define | USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) |
#define | USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) |
#define | USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) |
CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status | |
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) |
#define | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) |
STROBE_DLL_CTRL - Strobe DLL control | |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) |
#define | USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK) |
STROBE_DLL_STATUS - Strobe DLL status | |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U) |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U) |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK) |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U) |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U) |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK) |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU) |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U) |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U) |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U) |
#define | USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK) |
VEND_SPEC - Vendor Specific Register | |
#define | USDHC_VEND_SPEC_VSELECT_MASK (0x2U) |
#define | USDHC_VEND_SPEC_VSELECT_SHIFT (1U) |
#define | USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) |
#define | USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) |
#define | USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) |
#define | USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) |
#define | USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) |
#define | USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) |
#define | USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) |
#define | USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) |
#define | USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) |
#define | USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) |
#define | USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) |
#define | USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) |
#define | USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) |
#define | USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) |
#define | USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) |
#define | USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) |
MMC_BOOT - MMC Boot | |
#define | USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) |
#define | USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) |
#define | USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) |
#define | USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) |
#define | USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) |
#define | USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) |
#define | USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) |
#define | USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) |
#define | USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) |
#define | USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) |
#define | USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) |
#define | USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) |
#define | USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) |
#define | USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) |
#define | USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) |
#define | USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) |
#define | USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) |
#define | USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) |
#define | USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) |
#define | USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) |
#define | USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) |
VEND_SPEC2 - Vendor Specific 2 Register | |
#define | USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) |
#define | USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) |
#define | USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) |
#define | USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) |
#define | USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) |
#define | USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) |
#define | USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) |
#define | USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) |
#define | USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) |
#define | USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) |
#define | USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) |
#define | USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) |
#define | USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U) |
#define | USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U) |
#define | USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK) |
#define | USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U) |
#define | USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U) |
#define | USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK) |
#define | USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) |
#define | USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) |
#define | USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) |
TUNING_CTRL - Tuning Control | |
#define | USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU) |
#define | USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) |
#define | USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) |
#define | USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U) |
#define | USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U) |
#define | USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK) |
#define | USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) |
#define | USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) |
#define | USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) |
#define | USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) |
#define | USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) |
#define | USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) |
#define | USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) |
#define | USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) |
#define | USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) |
#define | USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) |
#define | USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) |
#define | USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) |
VID_MUX_CTRL - Video mux Control Register | |
#define | VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK (0x1U) |
#define | VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT (0U) |
#define | VIDEO_MUX_VID_MUX_CTRL_CSI_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK) |
#define | VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK (0x2U) |
#define | VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT (1U) |
#define | VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK) |
#define | VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK (0x4U) |
#define | VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT (2U) |
#define | VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK) |
#define | VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK (0x8U) |
#define | VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT (3U) |
#define | VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK) |
PLM_CTRL - Pixel Link Master(PLM) Control Register | |
#define | VIDEO_MUX_PLM_CTRL_ENABLE_MASK (0x1U) |
#define | VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT (0U) |
#define | VIDEO_MUX_PLM_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT)) & VIDEO_MUX_PLM_CTRL_ENABLE_MASK) |
#define | VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK (0x2U) |
#define | VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT (1U) |
#define | VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK) |
#define | VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK (0x4U) |
#define | VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT (2U) |
#define | VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK) |
#define | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK (0x8U) |
#define | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT (3U) |
#define | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK) |
#define | VIDEO_MUX_PLM_CTRL_POLARITY_MASK (0x10U) |
#define | VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT (4U) |
#define | VIDEO_MUX_PLM_CTRL_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT)) & VIDEO_MUX_PLM_CTRL_POLARITY_MASK) |
YUV420_CTRL - YUV420 Control Register | |
#define | VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK (0x1U) |
#define | VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT (0U) |
#define | VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT)) & VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK) |
CFG_DT_DISABLE - Data Disable Register | |
#define | VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK (0xFFFFFFU) |
#define | VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT (0U) |
#define | VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK) |
MIPI_DSI_CTRL - MIPI DSI Control Register | |
#define | VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK (0x1U) |
#define | VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT (0U) |
#define | VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK) |
#define | VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK (0x2U) |
#define | VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT (1U) |
#define | VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK) |
WCR - Watchdog Control Register | |
#define | WDOG_WCR_WDZST_MASK (0x1U) |
#define | WDOG_WCR_WDZST_SHIFT (0U) |
#define | WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) |
#define | WDOG_WCR_WDBG_MASK (0x2U) |
#define | WDOG_WCR_WDBG_SHIFT (1U) |
#define | WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) |
#define | WDOG_WCR_WDE_MASK (0x4U) |
#define | WDOG_WCR_WDE_SHIFT (2U) |
#define | WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) |
#define | WDOG_WCR_WDT_MASK (0x8U) |
#define | WDOG_WCR_WDT_SHIFT (3U) |
#define | WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) |
#define | WDOG_WCR_SRS_MASK (0x10U) |
#define | WDOG_WCR_SRS_SHIFT (4U) |
#define | WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) |
#define | WDOG_WCR_WDA_MASK (0x20U) |
#define | WDOG_WCR_WDA_SHIFT (5U) |
#define | WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) |
#define | WDOG_WCR_SRE_MASK (0x40U) |
#define | WDOG_WCR_SRE_SHIFT (6U) |
#define | WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) |
#define | WDOG_WCR_WDW_MASK (0x80U) |
#define | WDOG_WCR_WDW_SHIFT (7U) |
#define | WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) |
#define | WDOG_WCR_WT_MASK (0xFF00U) |
#define | WDOG_WCR_WT_SHIFT (8U) |
#define | WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) |
WSR - Watchdog Service Register | |
#define | WDOG_WSR_WSR_MASK (0xFFFFU) |
#define | WDOG_WSR_WSR_SHIFT (0U) |
#define | WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) |
WRSR - Watchdog Reset Status Register | |
#define | WDOG_WRSR_SFTW_MASK (0x1U) |
#define | WDOG_WRSR_SFTW_SHIFT (0U) |
#define | WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) |
#define | WDOG_WRSR_TOUT_MASK (0x2U) |
#define | WDOG_WRSR_TOUT_SHIFT (1U) |
#define | WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) |
#define | WDOG_WRSR_POR_MASK (0x10U) |
#define | WDOG_WRSR_POR_SHIFT (4U) |
#define | WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) |
WICR - Watchdog Interrupt Control Register | |
#define | WDOG_WICR_WICT_MASK (0xFFU) |
#define | WDOG_WICR_WICT_SHIFT (0U) |
#define | WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) |
#define | WDOG_WICR_WTIS_MASK (0x4000U) |
#define | WDOG_WICR_WTIS_SHIFT (14U) |
#define | WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) |
#define | WDOG_WICR_WIE_MASK (0x8000U) |
#define | WDOG_WICR_WIE_SHIFT (15U) |
#define | WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) |
WMCR - Watchdog Miscellaneous Control Register | |
#define | WDOG_WMCR_PDE_MASK (0x1U) |
#define | WDOG_WMCR_PDE_SHIFT (0U) |
#define | WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) |
SEL0 - Crossbar A Select Register 0 | |
#define | XBARA_SEL0_SEL0_MASK (0xFFU) |
#define | XBARA_SEL0_SEL0_SHIFT (0U) |
#define | XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK) |
#define | XBARA_SEL0_SEL1_MASK (0xFF00U) |
#define | XBARA_SEL0_SEL1_SHIFT (8U) |
#define | XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK) |
SEL1 - Crossbar A Select Register 1 | |
#define | XBARA_SEL1_SEL2_MASK (0xFFU) |
#define | XBARA_SEL1_SEL2_SHIFT (0U) |
#define | XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK) |
#define | XBARA_SEL1_SEL3_MASK (0xFF00U) |
#define | XBARA_SEL1_SEL3_SHIFT (8U) |
#define | XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK) |
SEL2 - Crossbar A Select Register 2 | |
#define | XBARA_SEL2_SEL4_MASK (0xFFU) |
#define | XBARA_SEL2_SEL4_SHIFT (0U) |
#define | XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK) |
#define | XBARA_SEL2_SEL5_MASK (0xFF00U) |
#define | XBARA_SEL2_SEL5_SHIFT (8U) |
#define | XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK) |
SEL3 - Crossbar A Select Register 3 | |
#define | XBARA_SEL3_SEL6_MASK (0xFFU) |
#define | XBARA_SEL3_SEL6_SHIFT (0U) |
#define | XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK) |
#define | XBARA_SEL3_SEL7_MASK (0xFF00U) |
#define | XBARA_SEL3_SEL7_SHIFT (8U) |
#define | XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK) |
SEL4 - Crossbar A Select Register 4 | |
#define | XBARA_SEL4_SEL8_MASK (0xFFU) |
#define | XBARA_SEL4_SEL8_SHIFT (0U) |
#define | XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK) |
#define | XBARA_SEL4_SEL9_MASK (0xFF00U) |
#define | XBARA_SEL4_SEL9_SHIFT (8U) |
#define | XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK) |
SEL5 - Crossbar A Select Register 5 | |
#define | XBARA_SEL5_SEL10_MASK (0xFFU) |
#define | XBARA_SEL5_SEL10_SHIFT (0U) |
#define | XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK) |
#define | XBARA_SEL5_SEL11_MASK (0xFF00U) |
#define | XBARA_SEL5_SEL11_SHIFT (8U) |
#define | XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK) |
SEL6 - Crossbar A Select Register 6 | |
#define | XBARA_SEL6_SEL12_MASK (0xFFU) |
#define | XBARA_SEL6_SEL12_SHIFT (0U) |
#define | XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK) |
#define | XBARA_SEL6_SEL13_MASK (0xFF00U) |
#define | XBARA_SEL6_SEL13_SHIFT (8U) |
#define | XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK) |
SEL7 - Crossbar A Select Register 7 | |
#define | XBARA_SEL7_SEL14_MASK (0xFFU) |
#define | XBARA_SEL7_SEL14_SHIFT (0U) |
#define | XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK) |
#define | XBARA_SEL7_SEL15_MASK (0xFF00U) |
#define | XBARA_SEL7_SEL15_SHIFT (8U) |
#define | XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK) |
SEL8 - Crossbar A Select Register 8 | |
#define | XBARA_SEL8_SEL16_MASK (0xFFU) |
#define | XBARA_SEL8_SEL16_SHIFT (0U) |
#define | XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK) |
#define | XBARA_SEL8_SEL17_MASK (0xFF00U) |
#define | XBARA_SEL8_SEL17_SHIFT (8U) |
#define | XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK) |
SEL9 - Crossbar A Select Register 9 | |
#define | XBARA_SEL9_SEL18_MASK (0xFFU) |
#define | XBARA_SEL9_SEL18_SHIFT (0U) |
#define | XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK) |
#define | XBARA_SEL9_SEL19_MASK (0xFF00U) |
#define | XBARA_SEL9_SEL19_SHIFT (8U) |
#define | XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK) |
SEL10 - Crossbar A Select Register 10 | |
#define | XBARA_SEL10_SEL20_MASK (0xFFU) |
#define | XBARA_SEL10_SEL20_SHIFT (0U) |
#define | XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK) |
#define | XBARA_SEL10_SEL21_MASK (0xFF00U) |
#define | XBARA_SEL10_SEL21_SHIFT (8U) |
#define | XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK) |
SEL11 - Crossbar A Select Register 11 | |
#define | XBARA_SEL11_SEL22_MASK (0xFFU) |
#define | XBARA_SEL11_SEL22_SHIFT (0U) |
#define | XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK) |
#define | XBARA_SEL11_SEL23_MASK (0xFF00U) |
#define | XBARA_SEL11_SEL23_SHIFT (8U) |
#define | XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK) |
SEL12 - Crossbar A Select Register 12 | |
#define | XBARA_SEL12_SEL24_MASK (0xFFU) |
#define | XBARA_SEL12_SEL24_SHIFT (0U) |
#define | XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK) |
#define | XBARA_SEL12_SEL25_MASK (0xFF00U) |
#define | XBARA_SEL12_SEL25_SHIFT (8U) |
#define | XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK) |
SEL13 - Crossbar A Select Register 13 | |
#define | XBARA_SEL13_SEL26_MASK (0xFFU) |
#define | XBARA_SEL13_SEL26_SHIFT (0U) |
#define | XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK) |
#define | XBARA_SEL13_SEL27_MASK (0xFF00U) |
#define | XBARA_SEL13_SEL27_SHIFT (8U) |
#define | XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK) |
SEL14 - Crossbar A Select Register 14 | |
#define | XBARA_SEL14_SEL28_MASK (0xFFU) |
#define | XBARA_SEL14_SEL28_SHIFT (0U) |
#define | XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK) |
#define | XBARA_SEL14_SEL29_MASK (0xFF00U) |
#define | XBARA_SEL14_SEL29_SHIFT (8U) |
#define | XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK) |
SEL15 - Crossbar A Select Register 15 | |
#define | XBARA_SEL15_SEL30_MASK (0xFFU) |
#define | XBARA_SEL15_SEL30_SHIFT (0U) |
#define | XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK) |
#define | XBARA_SEL15_SEL31_MASK (0xFF00U) |
#define | XBARA_SEL15_SEL31_SHIFT (8U) |
#define | XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK) |
SEL16 - Crossbar A Select Register 16 | |
#define | XBARA_SEL16_SEL32_MASK (0xFFU) |
#define | XBARA_SEL16_SEL32_SHIFT (0U) |
#define | XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK) |
#define | XBARA_SEL16_SEL33_MASK (0xFF00U) |
#define | XBARA_SEL16_SEL33_SHIFT (8U) |
#define | XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK) |
SEL17 - Crossbar A Select Register 17 | |
#define | XBARA_SEL17_SEL34_MASK (0xFFU) |
#define | XBARA_SEL17_SEL34_SHIFT (0U) |
#define | XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK) |
#define | XBARA_SEL17_SEL35_MASK (0xFF00U) |
#define | XBARA_SEL17_SEL35_SHIFT (8U) |
#define | XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK) |
SEL18 - Crossbar A Select Register 18 | |
#define | XBARA_SEL18_SEL36_MASK (0xFFU) |
#define | XBARA_SEL18_SEL36_SHIFT (0U) |
#define | XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK) |
#define | XBARA_SEL18_SEL37_MASK (0xFF00U) |
#define | XBARA_SEL18_SEL37_SHIFT (8U) |
#define | XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK) |
SEL19 - Crossbar A Select Register 19 | |
#define | XBARA_SEL19_SEL38_MASK (0xFFU) |
#define | XBARA_SEL19_SEL38_SHIFT (0U) |
#define | XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK) |
#define | XBARA_SEL19_SEL39_MASK (0xFF00U) |
#define | XBARA_SEL19_SEL39_SHIFT (8U) |
#define | XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK) |
SEL20 - Crossbar A Select Register 20 | |
#define | XBARA_SEL20_SEL40_MASK (0xFFU) |
#define | XBARA_SEL20_SEL40_SHIFT (0U) |
#define | XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK) |
#define | XBARA_SEL20_SEL41_MASK (0xFF00U) |
#define | XBARA_SEL20_SEL41_SHIFT (8U) |
#define | XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK) |
SEL21 - Crossbar A Select Register 21 | |
#define | XBARA_SEL21_SEL42_MASK (0xFFU) |
#define | XBARA_SEL21_SEL42_SHIFT (0U) |
#define | XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK) |
#define | XBARA_SEL21_SEL43_MASK (0xFF00U) |
#define | XBARA_SEL21_SEL43_SHIFT (8U) |
#define | XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK) |
SEL22 - Crossbar A Select Register 22 | |
#define | XBARA_SEL22_SEL44_MASK (0xFFU) |
#define | XBARA_SEL22_SEL44_SHIFT (0U) |
#define | XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK) |
#define | XBARA_SEL22_SEL45_MASK (0xFF00U) |
#define | XBARA_SEL22_SEL45_SHIFT (8U) |
#define | XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK) |
SEL23 - Crossbar A Select Register 23 | |
#define | XBARA_SEL23_SEL46_MASK (0xFFU) |
#define | XBARA_SEL23_SEL46_SHIFT (0U) |
#define | XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK) |
#define | XBARA_SEL23_SEL47_MASK (0xFF00U) |
#define | XBARA_SEL23_SEL47_SHIFT (8U) |
#define | XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK) |
SEL24 - Crossbar A Select Register 24 | |
#define | XBARA_SEL24_SEL48_MASK (0xFFU) |
#define | XBARA_SEL24_SEL48_SHIFT (0U) |
#define | XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK) |
#define | XBARA_SEL24_SEL49_MASK (0xFF00U) |
#define | XBARA_SEL24_SEL49_SHIFT (8U) |
#define | XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK) |
SEL25 - Crossbar A Select Register 25 | |
#define | XBARA_SEL25_SEL50_MASK (0xFFU) |
#define | XBARA_SEL25_SEL50_SHIFT (0U) |
#define | XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK) |
#define | XBARA_SEL25_SEL51_MASK (0xFF00U) |
#define | XBARA_SEL25_SEL51_SHIFT (8U) |
#define | XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK) |
SEL26 - Crossbar A Select Register 26 | |
#define | XBARA_SEL26_SEL52_MASK (0xFFU) |
#define | XBARA_SEL26_SEL52_SHIFT (0U) |
#define | XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK) |
#define | XBARA_SEL26_SEL53_MASK (0xFF00U) |
#define | XBARA_SEL26_SEL53_SHIFT (8U) |
#define | XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK) |
SEL27 - Crossbar A Select Register 27 | |
#define | XBARA_SEL27_SEL54_MASK (0xFFU) |
#define | XBARA_SEL27_SEL54_SHIFT (0U) |
#define | XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK) |
#define | XBARA_SEL27_SEL55_MASK (0xFF00U) |
#define | XBARA_SEL27_SEL55_SHIFT (8U) |
#define | XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK) |
SEL28 - Crossbar A Select Register 28 | |
#define | XBARA_SEL28_SEL56_MASK (0xFFU) |
#define | XBARA_SEL28_SEL56_SHIFT (0U) |
#define | XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK) |
#define | XBARA_SEL28_SEL57_MASK (0xFF00U) |
#define | XBARA_SEL28_SEL57_SHIFT (8U) |
#define | XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK) |
SEL29 - Crossbar A Select Register 29 | |
#define | XBARA_SEL29_SEL58_MASK (0xFFU) |
#define | XBARA_SEL29_SEL58_SHIFT (0U) |
#define | XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK) |
#define | XBARA_SEL29_SEL59_MASK (0xFF00U) |
#define | XBARA_SEL29_SEL59_SHIFT (8U) |
#define | XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK) |
SEL30 - Crossbar A Select Register 30 | |
#define | XBARA_SEL30_SEL60_MASK (0xFFU) |
#define | XBARA_SEL30_SEL60_SHIFT (0U) |
#define | XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK) |
#define | XBARA_SEL30_SEL61_MASK (0xFF00U) |
#define | XBARA_SEL30_SEL61_SHIFT (8U) |
#define | XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK) |
SEL31 - Crossbar A Select Register 31 | |
#define | XBARA_SEL31_SEL62_MASK (0xFFU) |
#define | XBARA_SEL31_SEL62_SHIFT (0U) |
#define | XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK) |
#define | XBARA_SEL31_SEL63_MASK (0xFF00U) |
#define | XBARA_SEL31_SEL63_SHIFT (8U) |
#define | XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK) |
SEL32 - Crossbar A Select Register 32 | |
#define | XBARA_SEL32_SEL64_MASK (0xFFU) |
#define | XBARA_SEL32_SEL64_SHIFT (0U) |
#define | XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK) |
#define | XBARA_SEL32_SEL65_MASK (0xFF00U) |
#define | XBARA_SEL32_SEL65_SHIFT (8U) |
#define | XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK) |
SEL33 - Crossbar A Select Register 33 | |
#define | XBARA_SEL33_SEL66_MASK (0xFFU) |
#define | XBARA_SEL33_SEL66_SHIFT (0U) |
#define | XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK) |
#define | XBARA_SEL33_SEL67_MASK (0xFF00U) |
#define | XBARA_SEL33_SEL67_SHIFT (8U) |
#define | XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK) |
SEL34 - Crossbar A Select Register 34 | |
#define | XBARA_SEL34_SEL68_MASK (0xFFU) |
#define | XBARA_SEL34_SEL68_SHIFT (0U) |
#define | XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK) |
#define | XBARA_SEL34_SEL69_MASK (0xFF00U) |
#define | XBARA_SEL34_SEL69_SHIFT (8U) |
#define | XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK) |
SEL35 - Crossbar A Select Register 35 | |
#define | XBARA_SEL35_SEL70_MASK (0xFFU) |
#define | XBARA_SEL35_SEL70_SHIFT (0U) |
#define | XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK) |
#define | XBARA_SEL35_SEL71_MASK (0xFF00U) |
#define | XBARA_SEL35_SEL71_SHIFT (8U) |
#define | XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK) |
SEL36 - Crossbar A Select Register 36 | |
#define | XBARA_SEL36_SEL72_MASK (0xFFU) |
#define | XBARA_SEL36_SEL72_SHIFT (0U) |
#define | XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK) |
#define | XBARA_SEL36_SEL73_MASK (0xFF00U) |
#define | XBARA_SEL36_SEL73_SHIFT (8U) |
#define | XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK) |
SEL37 - Crossbar A Select Register 37 | |
#define | XBARA_SEL37_SEL74_MASK (0xFFU) |
#define | XBARA_SEL37_SEL74_SHIFT (0U) |
#define | XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK) |
#define | XBARA_SEL37_SEL75_MASK (0xFF00U) |
#define | XBARA_SEL37_SEL75_SHIFT (8U) |
#define | XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK) |
SEL38 - Crossbar A Select Register 38 | |
#define | XBARA_SEL38_SEL76_MASK (0xFFU) |
#define | XBARA_SEL38_SEL76_SHIFT (0U) |
#define | XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK) |
#define | XBARA_SEL38_SEL77_MASK (0xFF00U) |
#define | XBARA_SEL38_SEL77_SHIFT (8U) |
#define | XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK) |
SEL39 - Crossbar A Select Register 39 | |
#define | XBARA_SEL39_SEL78_MASK (0xFFU) |
#define | XBARA_SEL39_SEL78_SHIFT (0U) |
#define | XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK) |
#define | XBARA_SEL39_SEL79_MASK (0xFF00U) |
#define | XBARA_SEL39_SEL79_SHIFT (8U) |
#define | XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK) |
SEL40 - Crossbar A Select Register 40 | |
#define | XBARA_SEL40_SEL80_MASK (0xFFU) |
#define | XBARA_SEL40_SEL80_SHIFT (0U) |
#define | XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK) |
#define | XBARA_SEL40_SEL81_MASK (0xFF00U) |
#define | XBARA_SEL40_SEL81_SHIFT (8U) |
#define | XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK) |
SEL41 - Crossbar A Select Register 41 | |
#define | XBARA_SEL41_SEL82_MASK (0xFFU) |
#define | XBARA_SEL41_SEL82_SHIFT (0U) |
#define | XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK) |
#define | XBARA_SEL41_SEL83_MASK (0xFF00U) |
#define | XBARA_SEL41_SEL83_SHIFT (8U) |
#define | XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK) |
SEL42 - Crossbar A Select Register 42 | |
#define | XBARA_SEL42_SEL84_MASK (0xFFU) |
#define | XBARA_SEL42_SEL84_SHIFT (0U) |
#define | XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK) |
#define | XBARA_SEL42_SEL85_MASK (0xFF00U) |
#define | XBARA_SEL42_SEL85_SHIFT (8U) |
#define | XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK) |
SEL43 - Crossbar A Select Register 43 | |
#define | XBARA_SEL43_SEL86_MASK (0xFFU) |
#define | XBARA_SEL43_SEL86_SHIFT (0U) |
#define | XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK) |
#define | XBARA_SEL43_SEL87_MASK (0xFF00U) |
#define | XBARA_SEL43_SEL87_SHIFT (8U) |
#define | XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK) |
SEL44 - Crossbar A Select Register 44 | |
#define | XBARA_SEL44_SEL88_MASK (0xFFU) |
#define | XBARA_SEL44_SEL88_SHIFT (0U) |
#define | XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK) |
#define | XBARA_SEL44_SEL89_MASK (0xFF00U) |
#define | XBARA_SEL44_SEL89_SHIFT (8U) |
#define | XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK) |
SEL45 - Crossbar A Select Register 45 | |
#define | XBARA_SEL45_SEL90_MASK (0xFFU) |
#define | XBARA_SEL45_SEL90_SHIFT (0U) |
#define | XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK) |
#define | XBARA_SEL45_SEL91_MASK (0xFF00U) |
#define | XBARA_SEL45_SEL91_SHIFT (8U) |
#define | XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK) |
SEL46 - Crossbar A Select Register 46 | |
#define | XBARA_SEL46_SEL92_MASK (0xFFU) |
#define | XBARA_SEL46_SEL92_SHIFT (0U) |
#define | XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK) |
#define | XBARA_SEL46_SEL93_MASK (0xFF00U) |
#define | XBARA_SEL46_SEL93_SHIFT (8U) |
#define | XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK) |
SEL47 - Crossbar A Select Register 47 | |
#define | XBARA_SEL47_SEL94_MASK (0xFFU) |
#define | XBARA_SEL47_SEL94_SHIFT (0U) |
#define | XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK) |
#define | XBARA_SEL47_SEL95_MASK (0xFF00U) |
#define | XBARA_SEL47_SEL95_SHIFT (8U) |
#define | XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK) |
SEL48 - Crossbar A Select Register 48 | |
#define | XBARA_SEL48_SEL96_MASK (0xFFU) |
#define | XBARA_SEL48_SEL96_SHIFT (0U) |
#define | XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK) |
#define | XBARA_SEL48_SEL97_MASK (0xFF00U) |
#define | XBARA_SEL48_SEL97_SHIFT (8U) |
#define | XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK) |
SEL49 - Crossbar A Select Register 49 | |
#define | XBARA_SEL49_SEL98_MASK (0xFFU) |
#define | XBARA_SEL49_SEL98_SHIFT (0U) |
#define | XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK) |
#define | XBARA_SEL49_SEL99_MASK (0xFF00U) |
#define | XBARA_SEL49_SEL99_SHIFT (8U) |
#define | XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK) |
SEL50 - Crossbar A Select Register 50 | |
#define | XBARA_SEL50_SEL100_MASK (0xFFU) |
#define | XBARA_SEL50_SEL100_SHIFT (0U) |
#define | XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK) |
#define | XBARA_SEL50_SEL101_MASK (0xFF00U) |
#define | XBARA_SEL50_SEL101_SHIFT (8U) |
#define | XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK) |
SEL51 - Crossbar A Select Register 51 | |
#define | XBARA_SEL51_SEL102_MASK (0xFFU) |
#define | XBARA_SEL51_SEL102_SHIFT (0U) |
#define | XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK) |
#define | XBARA_SEL51_SEL103_MASK (0xFF00U) |
#define | XBARA_SEL51_SEL103_SHIFT (8U) |
#define | XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK) |
SEL52 - Crossbar A Select Register 52 | |
#define | XBARA_SEL52_SEL104_MASK (0xFFU) |
#define | XBARA_SEL52_SEL104_SHIFT (0U) |
#define | XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK) |
#define | XBARA_SEL52_SEL105_MASK (0xFF00U) |
#define | XBARA_SEL52_SEL105_SHIFT (8U) |
#define | XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK) |
SEL53 - Crossbar A Select Register 53 | |
#define | XBARA_SEL53_SEL106_MASK (0xFFU) |
#define | XBARA_SEL53_SEL106_SHIFT (0U) |
#define | XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK) |
#define | XBARA_SEL53_SEL107_MASK (0xFF00U) |
#define | XBARA_SEL53_SEL107_SHIFT (8U) |
#define | XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK) |
SEL54 - Crossbar A Select Register 54 | |
#define | XBARA_SEL54_SEL108_MASK (0xFFU) |
#define | XBARA_SEL54_SEL108_SHIFT (0U) |
#define | XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK) |
#define | XBARA_SEL54_SEL109_MASK (0xFF00U) |
#define | XBARA_SEL54_SEL109_SHIFT (8U) |
#define | XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK) |
SEL55 - Crossbar A Select Register 55 | |
#define | XBARA_SEL55_SEL110_MASK (0xFFU) |
#define | XBARA_SEL55_SEL110_SHIFT (0U) |
#define | XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK) |
#define | XBARA_SEL55_SEL111_MASK (0xFF00U) |
#define | XBARA_SEL55_SEL111_SHIFT (8U) |
#define | XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK) |
SEL56 - Crossbar A Select Register 56 | |
#define | XBARA_SEL56_SEL112_MASK (0xFFU) |
#define | XBARA_SEL56_SEL112_SHIFT (0U) |
#define | XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK) |
#define | XBARA_SEL56_SEL113_MASK (0xFF00U) |
#define | XBARA_SEL56_SEL113_SHIFT (8U) |
#define | XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK) |
SEL57 - Crossbar A Select Register 57 | |
#define | XBARA_SEL57_SEL114_MASK (0xFFU) |
#define | XBARA_SEL57_SEL114_SHIFT (0U) |
#define | XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK) |
#define | XBARA_SEL57_SEL115_MASK (0xFF00U) |
#define | XBARA_SEL57_SEL115_SHIFT (8U) |
#define | XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK) |
SEL58 - Crossbar A Select Register 58 | |
#define | XBARA_SEL58_SEL116_MASK (0xFFU) |
#define | XBARA_SEL58_SEL116_SHIFT (0U) |
#define | XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK) |
#define | XBARA_SEL58_SEL117_MASK (0xFF00U) |
#define | XBARA_SEL58_SEL117_SHIFT (8U) |
#define | XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK) |
SEL59 - Crossbar A Select Register 59 | |
#define | XBARA_SEL59_SEL118_MASK (0xFFU) |
#define | XBARA_SEL59_SEL118_SHIFT (0U) |
#define | XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK) |
#define | XBARA_SEL59_SEL119_MASK (0xFF00U) |
#define | XBARA_SEL59_SEL119_SHIFT (8U) |
#define | XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK) |
SEL60 - Crossbar A Select Register 60 | |
#define | XBARA_SEL60_SEL120_MASK (0xFFU) |
#define | XBARA_SEL60_SEL120_SHIFT (0U) |
#define | XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK) |
#define | XBARA_SEL60_SEL121_MASK (0xFF00U) |
#define | XBARA_SEL60_SEL121_SHIFT (8U) |
#define | XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK) |
SEL61 - Crossbar A Select Register 61 | |
#define | XBARA_SEL61_SEL122_MASK (0xFFU) |
#define | XBARA_SEL61_SEL122_SHIFT (0U) |
#define | XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK) |
#define | XBARA_SEL61_SEL123_MASK (0xFF00U) |
#define | XBARA_SEL61_SEL123_SHIFT (8U) |
#define | XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK) |
SEL62 - Crossbar A Select Register 62 | |
#define | XBARA_SEL62_SEL124_MASK (0xFFU) |
#define | XBARA_SEL62_SEL124_SHIFT (0U) |
#define | XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK) |
#define | XBARA_SEL62_SEL125_MASK (0xFF00U) |
#define | XBARA_SEL62_SEL125_SHIFT (8U) |
#define | XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK) |
SEL63 - Crossbar A Select Register 63 | |
#define | XBARA_SEL63_SEL126_MASK (0xFFU) |
#define | XBARA_SEL63_SEL126_SHIFT (0U) |
#define | XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK) |
#define | XBARA_SEL63_SEL127_MASK (0xFF00U) |
#define | XBARA_SEL63_SEL127_SHIFT (8U) |
#define | XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK) |
SEL64 - Crossbar A Select Register 64 | |
#define | XBARA_SEL64_SEL128_MASK (0xFFU) |
#define | XBARA_SEL64_SEL128_SHIFT (0U) |
#define | XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK) |
#define | XBARA_SEL64_SEL129_MASK (0xFF00U) |
#define | XBARA_SEL64_SEL129_SHIFT (8U) |
#define | XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK) |
SEL65 - Crossbar A Select Register 65 | |
#define | XBARA_SEL65_SEL130_MASK (0xFFU) |
#define | XBARA_SEL65_SEL130_SHIFT (0U) |
#define | XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK) |
#define | XBARA_SEL65_SEL131_MASK (0xFF00U) |
#define | XBARA_SEL65_SEL131_SHIFT (8U) |
#define | XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK) |
SEL66 - Crossbar A Select Register 66 | |
#define | XBARA_SEL66_SEL132_MASK (0xFFU) |
#define | XBARA_SEL66_SEL132_SHIFT (0U) |
#define | XBARA_SEL66_SEL132(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL132_SHIFT)) & XBARA_SEL66_SEL132_MASK) |
#define | XBARA_SEL66_SEL133_MASK (0xFF00U) |
#define | XBARA_SEL66_SEL133_SHIFT (8U) |
#define | XBARA_SEL66_SEL133(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL133_SHIFT)) & XBARA_SEL66_SEL133_MASK) |
SEL67 - Crossbar A Select Register 67 | |
#define | XBARA_SEL67_SEL134_MASK (0xFFU) |
#define | XBARA_SEL67_SEL134_SHIFT (0U) |
#define | XBARA_SEL67_SEL134(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL134_SHIFT)) & XBARA_SEL67_SEL134_MASK) |
#define | XBARA_SEL67_SEL135_MASK (0xFF00U) |
#define | XBARA_SEL67_SEL135_SHIFT (8U) |
#define | XBARA_SEL67_SEL135(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL135_SHIFT)) & XBARA_SEL67_SEL135_MASK) |
SEL68 - Crossbar A Select Register 68 | |
#define | XBARA_SEL68_SEL136_MASK (0xFFU) |
#define | XBARA_SEL68_SEL136_SHIFT (0U) |
#define | XBARA_SEL68_SEL136(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL136_SHIFT)) & XBARA_SEL68_SEL136_MASK) |
#define | XBARA_SEL68_SEL137_MASK (0xFF00U) |
#define | XBARA_SEL68_SEL137_SHIFT (8U) |
#define | XBARA_SEL68_SEL137(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL137_SHIFT)) & XBARA_SEL68_SEL137_MASK) |
SEL69 - Crossbar A Select Register 69 | |
#define | XBARA_SEL69_SEL138_MASK (0xFFU) |
#define | XBARA_SEL69_SEL138_SHIFT (0U) |
#define | XBARA_SEL69_SEL138(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL138_SHIFT)) & XBARA_SEL69_SEL138_MASK) |
#define | XBARA_SEL69_SEL139_MASK (0xFF00U) |
#define | XBARA_SEL69_SEL139_SHIFT (8U) |
#define | XBARA_SEL69_SEL139(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL139_SHIFT)) & XBARA_SEL69_SEL139_MASK) |
SEL70 - Crossbar A Select Register 70 | |
#define | XBARA_SEL70_SEL140_MASK (0xFFU) |
#define | XBARA_SEL70_SEL140_SHIFT (0U) |
#define | XBARA_SEL70_SEL140(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL140_SHIFT)) & XBARA_SEL70_SEL140_MASK) |
#define | XBARA_SEL70_SEL141_MASK (0xFF00U) |
#define | XBARA_SEL70_SEL141_SHIFT (8U) |
#define | XBARA_SEL70_SEL141(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL141_SHIFT)) & XBARA_SEL70_SEL141_MASK) |
SEL71 - Crossbar A Select Register 71 | |
#define | XBARA_SEL71_SEL142_MASK (0xFFU) |
#define | XBARA_SEL71_SEL142_SHIFT (0U) |
#define | XBARA_SEL71_SEL142(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL142_SHIFT)) & XBARA_SEL71_SEL142_MASK) |
#define | XBARA_SEL71_SEL143_MASK (0xFF00U) |
#define | XBARA_SEL71_SEL143_SHIFT (8U) |
#define | XBARA_SEL71_SEL143(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL143_SHIFT)) & XBARA_SEL71_SEL143_MASK) |
SEL72 - Crossbar A Select Register 72 | |
#define | XBARA_SEL72_SEL144_MASK (0xFFU) |
#define | XBARA_SEL72_SEL144_SHIFT (0U) |
#define | XBARA_SEL72_SEL144(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL144_SHIFT)) & XBARA_SEL72_SEL144_MASK) |
#define | XBARA_SEL72_SEL145_MASK (0xFF00U) |
#define | XBARA_SEL72_SEL145_SHIFT (8U) |
#define | XBARA_SEL72_SEL145(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL145_SHIFT)) & XBARA_SEL72_SEL145_MASK) |
SEL73 - Crossbar A Select Register 73 | |
#define | XBARA_SEL73_SEL146_MASK (0xFFU) |
#define | XBARA_SEL73_SEL146_SHIFT (0U) |
#define | XBARA_SEL73_SEL146(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL146_SHIFT)) & XBARA_SEL73_SEL146_MASK) |
#define | XBARA_SEL73_SEL147_MASK (0xFF00U) |
#define | XBARA_SEL73_SEL147_SHIFT (8U) |
#define | XBARA_SEL73_SEL147(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL147_SHIFT)) & XBARA_SEL73_SEL147_MASK) |
SEL74 - Crossbar A Select Register 74 | |
#define | XBARA_SEL74_SEL148_MASK (0xFFU) |
#define | XBARA_SEL74_SEL148_SHIFT (0U) |
#define | XBARA_SEL74_SEL148(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL148_SHIFT)) & XBARA_SEL74_SEL148_MASK) |
#define | XBARA_SEL74_SEL149_MASK (0xFF00U) |
#define | XBARA_SEL74_SEL149_SHIFT (8U) |
#define | XBARA_SEL74_SEL149(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL149_SHIFT)) & XBARA_SEL74_SEL149_MASK) |
SEL75 - Crossbar A Select Register 75 | |
#define | XBARA_SEL75_SEL150_MASK (0xFFU) |
#define | XBARA_SEL75_SEL150_SHIFT (0U) |
#define | XBARA_SEL75_SEL150(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL150_SHIFT)) & XBARA_SEL75_SEL150_MASK) |
#define | XBARA_SEL75_SEL151_MASK (0xFF00U) |
#define | XBARA_SEL75_SEL151_SHIFT (8U) |
#define | XBARA_SEL75_SEL151(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL151_SHIFT)) & XBARA_SEL75_SEL151_MASK) |
SEL76 - Crossbar A Select Register 76 | |
#define | XBARA_SEL76_SEL152_MASK (0xFFU) |
#define | XBARA_SEL76_SEL152_SHIFT (0U) |
#define | XBARA_SEL76_SEL152(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL152_SHIFT)) & XBARA_SEL76_SEL152_MASK) |
#define | XBARA_SEL76_SEL153_MASK (0xFF00U) |
#define | XBARA_SEL76_SEL153_SHIFT (8U) |
#define | XBARA_SEL76_SEL153(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL153_SHIFT)) & XBARA_SEL76_SEL153_MASK) |
SEL77 - Crossbar A Select Register 77 | |
#define | XBARA_SEL77_SEL154_MASK (0xFFU) |
#define | XBARA_SEL77_SEL154_SHIFT (0U) |
#define | XBARA_SEL77_SEL154(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL154_SHIFT)) & XBARA_SEL77_SEL154_MASK) |
#define | XBARA_SEL77_SEL155_MASK (0xFF00U) |
#define | XBARA_SEL77_SEL155_SHIFT (8U) |
#define | XBARA_SEL77_SEL155(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL155_SHIFT)) & XBARA_SEL77_SEL155_MASK) |
SEL78 - Crossbar A Select Register 78 | |
#define | XBARA_SEL78_SEL156_MASK (0xFFU) |
#define | XBARA_SEL78_SEL156_SHIFT (0U) |
#define | XBARA_SEL78_SEL156(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL156_SHIFT)) & XBARA_SEL78_SEL156_MASK) |
#define | XBARA_SEL78_SEL157_MASK (0xFF00U) |
#define | XBARA_SEL78_SEL157_SHIFT (8U) |
#define | XBARA_SEL78_SEL157(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL157_SHIFT)) & XBARA_SEL78_SEL157_MASK) |
SEL79 - Crossbar A Select Register 79 | |
#define | XBARA_SEL79_SEL158_MASK (0xFFU) |
#define | XBARA_SEL79_SEL158_SHIFT (0U) |
#define | XBARA_SEL79_SEL158(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL158_SHIFT)) & XBARA_SEL79_SEL158_MASK) |
#define | XBARA_SEL79_SEL159_MASK (0xFF00U) |
#define | XBARA_SEL79_SEL159_SHIFT (8U) |
#define | XBARA_SEL79_SEL159(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL159_SHIFT)) & XBARA_SEL79_SEL159_MASK) |
SEL80 - Crossbar A Select Register 80 | |
#define | XBARA_SEL80_SEL160_MASK (0xFFU) |
#define | XBARA_SEL80_SEL160_SHIFT (0U) |
#define | XBARA_SEL80_SEL160(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL160_SHIFT)) & XBARA_SEL80_SEL160_MASK) |
#define | XBARA_SEL80_SEL161_MASK (0xFF00U) |
#define | XBARA_SEL80_SEL161_SHIFT (8U) |
#define | XBARA_SEL80_SEL161(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL161_SHIFT)) & XBARA_SEL80_SEL161_MASK) |
SEL81 - Crossbar A Select Register 81 | |
#define | XBARA_SEL81_SEL162_MASK (0xFFU) |
#define | XBARA_SEL81_SEL162_SHIFT (0U) |
#define | XBARA_SEL81_SEL162(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL162_SHIFT)) & XBARA_SEL81_SEL162_MASK) |
#define | XBARA_SEL81_SEL163_MASK (0xFF00U) |
#define | XBARA_SEL81_SEL163_SHIFT (8U) |
#define | XBARA_SEL81_SEL163(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL163_SHIFT)) & XBARA_SEL81_SEL163_MASK) |
SEL82 - Crossbar A Select Register 82 | |
#define | XBARA_SEL82_SEL164_MASK (0xFFU) |
#define | XBARA_SEL82_SEL164_SHIFT (0U) |
#define | XBARA_SEL82_SEL164(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL164_SHIFT)) & XBARA_SEL82_SEL164_MASK) |
#define | XBARA_SEL82_SEL165_MASK (0xFF00U) |
#define | XBARA_SEL82_SEL165_SHIFT (8U) |
#define | XBARA_SEL82_SEL165(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL165_SHIFT)) & XBARA_SEL82_SEL165_MASK) |
SEL83 - Crossbar A Select Register 83 | |
#define | XBARA_SEL83_SEL166_MASK (0xFFU) |
#define | XBARA_SEL83_SEL166_SHIFT (0U) |
#define | XBARA_SEL83_SEL166(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL166_SHIFT)) & XBARA_SEL83_SEL166_MASK) |
#define | XBARA_SEL83_SEL167_MASK (0xFF00U) |
#define | XBARA_SEL83_SEL167_SHIFT (8U) |
#define | XBARA_SEL83_SEL167(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL167_SHIFT)) & XBARA_SEL83_SEL167_MASK) |
SEL84 - Crossbar A Select Register 84 | |
#define | XBARA_SEL84_SEL168_MASK (0xFFU) |
#define | XBARA_SEL84_SEL168_SHIFT (0U) |
#define | XBARA_SEL84_SEL168(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL168_SHIFT)) & XBARA_SEL84_SEL168_MASK) |
#define | XBARA_SEL84_SEL169_MASK (0xFF00U) |
#define | XBARA_SEL84_SEL169_SHIFT (8U) |
#define | XBARA_SEL84_SEL169(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL169_SHIFT)) & XBARA_SEL84_SEL169_MASK) |
SEL85 - Crossbar A Select Register 85 | |
#define | XBARA_SEL85_SEL170_MASK (0xFFU) |
#define | XBARA_SEL85_SEL170_SHIFT (0U) |
#define | XBARA_SEL85_SEL170(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL170_SHIFT)) & XBARA_SEL85_SEL170_MASK) |
#define | XBARA_SEL85_SEL171_MASK (0xFF00U) |
#define | XBARA_SEL85_SEL171_SHIFT (8U) |
#define | XBARA_SEL85_SEL171(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL171_SHIFT)) & XBARA_SEL85_SEL171_MASK) |
SEL86 - Crossbar A Select Register 86 | |
#define | XBARA_SEL86_SEL172_MASK (0xFFU) |
#define | XBARA_SEL86_SEL172_SHIFT (0U) |
#define | XBARA_SEL86_SEL172(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL172_SHIFT)) & XBARA_SEL86_SEL172_MASK) |
#define | XBARA_SEL86_SEL173_MASK (0xFF00U) |
#define | XBARA_SEL86_SEL173_SHIFT (8U) |
#define | XBARA_SEL86_SEL173(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL173_SHIFT)) & XBARA_SEL86_SEL173_MASK) |
SEL87 - Crossbar A Select Register 87 | |
#define | XBARA_SEL87_SEL174_MASK (0xFFU) |
#define | XBARA_SEL87_SEL174_SHIFT (0U) |
#define | XBARA_SEL87_SEL174(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL174_SHIFT)) & XBARA_SEL87_SEL174_MASK) |
#define | XBARA_SEL87_SEL175_MASK (0xFF00U) |
#define | XBARA_SEL87_SEL175_SHIFT (8U) |
#define | XBARA_SEL87_SEL175(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL175_SHIFT)) & XBARA_SEL87_SEL175_MASK) |
CTRL0 - Crossbar A Control Register 0 | |
#define | XBARA_CTRL0_DEN0_MASK (0x1U) |
#define | XBARA_CTRL0_DEN0_SHIFT (0U) |
#define | XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK) |
#define | XBARA_CTRL0_IEN0_MASK (0x2U) |
#define | XBARA_CTRL0_IEN0_SHIFT (1U) |
#define | XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK) |
#define | XBARA_CTRL0_EDGE0_MASK (0xCU) |
#define | XBARA_CTRL0_EDGE0_SHIFT (2U) |
#define | XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK) |
#define | XBARA_CTRL0_STS0_MASK (0x10U) |
#define | XBARA_CTRL0_STS0_SHIFT (4U) |
#define | XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK) |
#define | XBARA_CTRL0_DEN1_MASK (0x100U) |
#define | XBARA_CTRL0_DEN1_SHIFT (8U) |
#define | XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK) |
#define | XBARA_CTRL0_IEN1_MASK (0x200U) |
#define | XBARA_CTRL0_IEN1_SHIFT (9U) |
#define | XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK) |
#define | XBARA_CTRL0_EDGE1_MASK (0xC00U) |
#define | XBARA_CTRL0_EDGE1_SHIFT (10U) |
#define | XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK) |
#define | XBARA_CTRL0_STS1_MASK (0x1000U) |
#define | XBARA_CTRL0_STS1_SHIFT (12U) |
#define | XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK) |
CTRL1 - Crossbar A Control Register 1 | |
#define | XBARA_CTRL1_DEN2_MASK (0x1U) |
#define | XBARA_CTRL1_DEN2_SHIFT (0U) |
#define | XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK) |
#define | XBARA_CTRL1_IEN2_MASK (0x2U) |
#define | XBARA_CTRL1_IEN2_SHIFT (1U) |
#define | XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK) |
#define | XBARA_CTRL1_EDGE2_MASK (0xCU) |
#define | XBARA_CTRL1_EDGE2_SHIFT (2U) |
#define | XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK) |
#define | XBARA_CTRL1_STS2_MASK (0x10U) |
#define | XBARA_CTRL1_STS2_SHIFT (4U) |
#define | XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK) |
#define | XBARA_CTRL1_DEN3_MASK (0x100U) |
#define | XBARA_CTRL1_DEN3_SHIFT (8U) |
#define | XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK) |
#define | XBARA_CTRL1_IEN3_MASK (0x200U) |
#define | XBARA_CTRL1_IEN3_SHIFT (9U) |
#define | XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK) |
#define | XBARA_CTRL1_EDGE3_MASK (0xC00U) |
#define | XBARA_CTRL1_EDGE3_SHIFT (10U) |
#define | XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK) |
#define | XBARA_CTRL1_STS3_MASK (0x1000U) |
#define | XBARA_CTRL1_STS3_SHIFT (12U) |
#define | XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) |
SEL0 - Crossbar B Select Register 0 | |
#define | XBARB_SEL0_SEL0_MASK (0x7FU) |
#define | XBARB_SEL0_SEL0_SHIFT (0U) |
#define | XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK) |
#define | XBARB_SEL0_SEL1_MASK (0x7F00U) |
#define | XBARB_SEL0_SEL1_SHIFT (8U) |
#define | XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK) |
SEL1 - Crossbar B Select Register 1 | |
#define | XBARB_SEL1_SEL2_MASK (0x7FU) |
#define | XBARB_SEL1_SEL2_SHIFT (0U) |
#define | XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK) |
#define | XBARB_SEL1_SEL3_MASK (0x7F00U) |
#define | XBARB_SEL1_SEL3_SHIFT (8U) |
#define | XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK) |
SEL2 - Crossbar B Select Register 2 | |
#define | XBARB_SEL2_SEL4_MASK (0x7FU) |
#define | XBARB_SEL2_SEL4_SHIFT (0U) |
#define | XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK) |
#define | XBARB_SEL2_SEL5_MASK (0x7F00U) |
#define | XBARB_SEL2_SEL5_SHIFT (8U) |
#define | XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK) |
SEL3 - Crossbar B Select Register 3 | |
#define | XBARB_SEL3_SEL6_MASK (0x7FU) |
#define | XBARB_SEL3_SEL6_SHIFT (0U) |
#define | XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK) |
#define | XBARB_SEL3_SEL7_MASK (0x7F00U) |
#define | XBARB_SEL3_SEL7_SHIFT (8U) |
#define | XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK) |
SEL4 - Crossbar B Select Register 4 | |
#define | XBARB_SEL4_SEL8_MASK (0x7FU) |
#define | XBARB_SEL4_SEL8_SHIFT (0U) |
#define | XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK) |
#define | XBARB_SEL4_SEL9_MASK (0x7F00U) |
#define | XBARB_SEL4_SEL9_SHIFT (8U) |
#define | XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK) |
SEL5 - Crossbar B Select Register 5 | |
#define | XBARB_SEL5_SEL10_MASK (0x7FU) |
#define | XBARB_SEL5_SEL10_SHIFT (0U) |
#define | XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK) |
#define | XBARB_SEL5_SEL11_MASK (0x7F00U) |
#define | XBARB_SEL5_SEL11_SHIFT (8U) |
#define | XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK) |
SEL6 - Crossbar B Select Register 6 | |
#define | XBARB_SEL6_SEL12_MASK (0x7FU) |
#define | XBARB_SEL6_SEL12_SHIFT (0U) |
#define | XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK) |
#define | XBARB_SEL6_SEL13_MASK (0x7F00U) |
#define | XBARB_SEL6_SEL13_SHIFT (8U) |
#define | XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK) |
SEL7 - Crossbar B Select Register 7 | |
#define | XBARB_SEL7_SEL14_MASK (0x7FU) |
#define | XBARB_SEL7_SEL14_SHIFT (0U) |
#define | XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK) |
#define | XBARB_SEL7_SEL15_MASK (0x7F00U) |
#define | XBARB_SEL7_SEL15_SHIFT (8U) |
#define | XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) |
ECC_CTRL - ECC Control Register | |
#define | XECC_ECC_CTRL_ECC_EN_MASK (0x1U) |
#define | XECC_ECC_CTRL_ECC_EN_SHIFT (0U) |
#define | XECC_ECC_CTRL_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_ECC_EN_SHIFT)) & XECC_ECC_CTRL_ECC_EN_MASK) |
#define | XECC_ECC_CTRL_WECC_EN_MASK (0x2U) |
#define | XECC_ECC_CTRL_WECC_EN_SHIFT (1U) |
#define | XECC_ECC_CTRL_WECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_WECC_EN_SHIFT)) & XECC_ECC_CTRL_WECC_EN_MASK) |
#define | XECC_ECC_CTRL_RECC_EN_MASK (0x4U) |
#define | XECC_ECC_CTRL_RECC_EN_SHIFT (2U) |
#define | XECC_ECC_CTRL_RECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_RECC_EN_SHIFT)) & XECC_ECC_CTRL_RECC_EN_MASK) |
#define | XECC_ECC_CTRL_SWAP_EN_MASK (0x8U) |
#define | XECC_ECC_CTRL_SWAP_EN_SHIFT (3U) |
#define | XECC_ECC_CTRL_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_SWAP_EN_SHIFT)) & XECC_ECC_CTRL_SWAP_EN_MASK) |
ERR_DATA_INJ - Error Injection On Write Data | |
#define | XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK (0xFFFFFFFFU) |
#define | XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT (0U) |
#define | XECC_ERR_DATA_INJ_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT)) & XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK) |
ERR_ECC_INJ - Error Injection On ECC Code of Write Data | |
#define | XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK (0xFFFFFFFFU) |
#define | XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT (0U) |
#define | XECC_ERR_ECC_INJ_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT)) & XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK) |
SINGLE_ERR_ADDR - Single Error Address | |
#define | XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK (0xFFFFFFFFU) |
#define | XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT (0U) |
#define | XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT)) & XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK) |
SINGLE_ERR_DATA - Single Error Read Data | |
#define | XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT (0U) |
#define | XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT)) & XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK) |
SINGLE_ERR_ECC - Single Error ECC Code | |
#define | XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK (0xFFFFFFFFU) |
#define | XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT (0U) |
#define | XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT)) & XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK) |
SINGLE_ERR_POS - Single Error Bit Position | |
#define | XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) |
#define | XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT (0U) |
#define | XECC_SINGLE_ERR_POS_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT)) & XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK) |
SINGLE_ERR_BIT_FIELD - Single Error Bit Field | |
#define | XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK (0xFFU) |
#define | XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT (0U) |
#define | XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK) |
#define | XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK (0xFFFFFF00U) |
#define | XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT (8U) |
#define | XECC_SINGLE_ERR_BIT_FIELD_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK) |
MULTI_ERR_ADDR - Multiple Error Address | |
#define | XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK (0xFFFFFFFFU) |
#define | XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT (0U) |
#define | XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT)) & XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK) |
MULTI_ERR_DATA - Multiple Error Read Data | |
#define | XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) |
#define | XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT (0U) |
#define | XECC_MULTI_ERR_DATA_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT)) & XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK) |
MULTI_ERR_ECC - Multiple Error ECC code | |
#define | XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK (0xFFFFFFFFU) |
#define | XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT (0U) |
#define | XECC_MULTI_ERR_ECC_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT)) & XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK) |
MULTI_ERR_BIT_FIELD - Multiple Error Bit Field | |
#define | XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK (0xFFU) |
#define | XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT (0U) |
#define | XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK) |
#define | XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK (0xFFFFFF00U) |
#define | XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT (8U) |
#define | XECC_MULTI_ERR_BIT_FIELD_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK) |
ECC_BASE_ADDR0 - ECC Region 0 Base Address | |
#define | XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK (0xFFFFFFFFU) |
#define | XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT (0U) |
#define | XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT)) & XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK) |
ECC_END_ADDR0 - ECC Region 0 End Address | |
#define | XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK (0xFFFFFFFFU) |
#define | XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT (0U) |
#define | XECC_ECC_END_ADDR0_ECC_END_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT)) & XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK) |
ECC_BASE_ADDR1 - ECC Region 1 Base Address | |
#define | XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK (0xFFFFFFFFU) |
#define | XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT (0U) |
#define | XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT)) & XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK) |
ECC_END_ADDR1 - ECC Region 1 End Address | |
#define | XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK (0xFFFFFFFFU) |
#define | XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT (0U) |
#define | XECC_ECC_END_ADDR1_ECC_END_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT)) & XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK) |
ECC_BASE_ADDR2 - ECC Region 2 Base Address | |
#define | XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK (0xFFFFFFFFU) |
#define | XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT (0U) |
#define | XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT)) & XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK) |
ECC_END_ADDR2 - ECC Region 2 End Address | |
#define | XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK (0xFFFFFFFFU) |
#define | XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT (0U) |
#define | XECC_ECC_END_ADDR2_ECC_END_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT)) & XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK) |
ECC_BASE_ADDR3 - ECC Region 3 Base Address | |
#define | XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK (0xFFFFFFFFU) |
#define | XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT (0U) |
#define | XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT)) & XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK) |
ECC_END_ADDR3 - ECC Region 3 End Address | |
#define | XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK (0xFFFFFFFFU) |
#define | XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT (0U) |
#define | XECC_ECC_END_ADDR3_ECC_END_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT)) & XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK) |
MSC_MSAC_W0 - Memory Slot Access Control | |
#define | XRDC2_MSC_MSAC_W0_D0ACP_MASK (0x7U) |
#define | XRDC2_MSC_MSAC_W0_D0ACP_SHIFT (0U) |
#define | XRDC2_MSC_MSAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK) |
#define | XRDC2_MSC_MSAC_W0_D1ACP_MASK (0x38U) |
#define | XRDC2_MSC_MSAC_W0_D1ACP_SHIFT (3U) |
#define | XRDC2_MSC_MSAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK) |
#define | XRDC2_MSC_MSAC_W0_D2ACP_MASK (0x1C0U) |
#define | XRDC2_MSC_MSAC_W0_D2ACP_SHIFT (6U) |
#define | XRDC2_MSC_MSAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK) |
#define | XRDC2_MSC_MSAC_W0_D3ACP_MASK (0xE00U) |
#define | XRDC2_MSC_MSAC_W0_D3ACP_SHIFT (9U) |
#define | XRDC2_MSC_MSAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK) |
#define | XRDC2_MSC_MSAC_W0_D4ACP_MASK (0x7000U) |
#define | XRDC2_MSC_MSAC_W0_D4ACP_SHIFT (12U) |
#define | XRDC2_MSC_MSAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK) |
#define | XRDC2_MSC_MSAC_W0_D5ACP_MASK (0x38000U) |
#define | XRDC2_MSC_MSAC_W0_D5ACP_SHIFT (15U) |
#define | XRDC2_MSC_MSAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK) |
#define | XRDC2_MSC_MSAC_W0_D6ACP_MASK (0x1C0000U) |
#define | XRDC2_MSC_MSAC_W0_D6ACP_SHIFT (18U) |
#define | XRDC2_MSC_MSAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK) |
#define | XRDC2_MSC_MSAC_W0_D7ACP_MASK (0xE00000U) |
#define | XRDC2_MSC_MSAC_W0_D7ACP_SHIFT (21U) |
#define | XRDC2_MSC_MSAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK) |
#define | XRDC2_MSC_MSAC_W0_EALO_MASK (0xF000000U) |
#define | XRDC2_MSC_MSAC_W0_EALO_SHIFT (24U) |
#define | XRDC2_MSC_MSAC_W0_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_EALO_SHIFT)) & XRDC2_MSC_MSAC_W0_EALO_MASK) |
MSC_MSAC_W1 - Memory Slot Access Control | |
#define | XRDC2_MSC_MSAC_W1_D8ACP_MASK (0x7U) |
#define | XRDC2_MSC_MSAC_W1_D8ACP_SHIFT (0U) |
#define | XRDC2_MSC_MSAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK) |
#define | XRDC2_MSC_MSAC_W1_D9ACP_MASK (0x38U) |
#define | XRDC2_MSC_MSAC_W1_D9ACP_SHIFT (3U) |
#define | XRDC2_MSC_MSAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK) |
#define | XRDC2_MSC_MSAC_W1_D10ACP_MASK (0x1C0U) |
#define | XRDC2_MSC_MSAC_W1_D10ACP_SHIFT (6U) |
#define | XRDC2_MSC_MSAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK) |
#define | XRDC2_MSC_MSAC_W1_D11ACP_MASK (0xE00U) |
#define | XRDC2_MSC_MSAC_W1_D11ACP_SHIFT (9U) |
#define | XRDC2_MSC_MSAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK) |
#define | XRDC2_MSC_MSAC_W1_D12ACP_MASK (0x7000U) |
#define | XRDC2_MSC_MSAC_W1_D12ACP_SHIFT (12U) |
#define | XRDC2_MSC_MSAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK) |
#define | XRDC2_MSC_MSAC_W1_D13ACP_MASK (0x38000U) |
#define | XRDC2_MSC_MSAC_W1_D13ACP_SHIFT (15U) |
#define | XRDC2_MSC_MSAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK) |
#define | XRDC2_MSC_MSAC_W1_D14ACP_MASK (0x1C0000U) |
#define | XRDC2_MSC_MSAC_W1_D14ACP_SHIFT (18U) |
#define | XRDC2_MSC_MSAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK) |
#define | XRDC2_MSC_MSAC_W1_D15ACP_MASK (0xE00000U) |
#define | XRDC2_MSC_MSAC_W1_D15ACP_SHIFT (21U) |
#define | XRDC2_MSC_MSAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK) |
#define | XRDC2_MSC_MSAC_W1_EAL_MASK (0x3000000U) |
#define | XRDC2_MSC_MSAC_W1_EAL_SHIFT (24U) |
#define | XRDC2_MSC_MSAC_W1_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK) |
#define | XRDC2_MSC_MSAC_W1_DL2_MASK (0x60000000U) |
#define | XRDC2_MSC_MSAC_W1_DL2_SHIFT (29U) |
#define | XRDC2_MSC_MSAC_W1_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK) |
#define | XRDC2_MSC_MSAC_W1_VLD_MASK (0x80000000U) |
#define | XRDC2_MSC_MSAC_W1_VLD_SHIFT (31U) |
#define | XRDC2_MSC_MSAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_VLD_SHIFT)) & XRDC2_MSC_MSAC_W1_VLD_MASK) |
MDAC_MDA_W0 - Master Domain Assignment | |
#define | XRDC2_MDAC_MDA_W0_MASK_MASK (0xFFFFU) |
#define | XRDC2_MDAC_MDA_W0_MASK_SHIFT (0U) |
#define | XRDC2_MDAC_MDA_W0_MASK(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK) |
#define | XRDC2_MDAC_MDA_W0_MATCH_MASK (0xFFFF0000U) |
#define | XRDC2_MDAC_MDA_W0_MATCH_SHIFT (16U) |
#define | XRDC2_MDAC_MDA_W0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MATCH_SHIFT)) & XRDC2_MDAC_MDA_W0_MATCH_MASK) |
MDAC_MDA_W1 - Master Domain Assignment | |
#define | XRDC2_MDAC_MDA_W1_DID_MASK (0xF0000U) |
#define | XRDC2_MDAC_MDA_W1_DID_SHIFT (16U) |
#define | XRDC2_MDAC_MDA_W1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK) |
#define | XRDC2_MDAC_MDA_W1_PA_MASK (0x3000000U) |
#define | XRDC2_MDAC_MDA_W1_PA_SHIFT (24U) |
#define | XRDC2_MDAC_MDA_W1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK) |
#define | XRDC2_MDAC_MDA_W1_SA_MASK (0xC000000U) |
#define | XRDC2_MDAC_MDA_W1_SA_SHIFT (26U) |
#define | XRDC2_MDAC_MDA_W1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK) |
#define | XRDC2_MDAC_MDA_W1_DL_MASK (0x40000000U) |
#define | XRDC2_MDAC_MDA_W1_DL_SHIFT (30U) |
#define | XRDC2_MDAC_MDA_W1_DL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK) |
#define | XRDC2_MDAC_MDA_W1_VLD_MASK (0x80000000U) |
#define | XRDC2_MDAC_MDA_W1_VLD_SHIFT (31U) |
#define | XRDC2_MDAC_MDA_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_VLD_SHIFT)) & XRDC2_MDAC_MDA_W1_VLD_MASK) |
PAC_PDAC_W0 - Peripheral Domain Access Control | |
#define | XRDC2_PAC_PDAC_W0_D0ACP_MASK (0x7U) |
#define | XRDC2_PAC_PDAC_W0_D0ACP_SHIFT (0U) |
#define | XRDC2_PAC_PDAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK) |
#define | XRDC2_PAC_PDAC_W0_D1ACP_MASK (0x38U) |
#define | XRDC2_PAC_PDAC_W0_D1ACP_SHIFT (3U) |
#define | XRDC2_PAC_PDAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK) |
#define | XRDC2_PAC_PDAC_W0_D2ACP_MASK (0x1C0U) |
#define | XRDC2_PAC_PDAC_W0_D2ACP_SHIFT (6U) |
#define | XRDC2_PAC_PDAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK) |
#define | XRDC2_PAC_PDAC_W0_D3ACP_MASK (0xE00U) |
#define | XRDC2_PAC_PDAC_W0_D3ACP_SHIFT (9U) |
#define | XRDC2_PAC_PDAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK) |
#define | XRDC2_PAC_PDAC_W0_D4ACP_MASK (0x7000U) |
#define | XRDC2_PAC_PDAC_W0_D4ACP_SHIFT (12U) |
#define | XRDC2_PAC_PDAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK) |
#define | XRDC2_PAC_PDAC_W0_D5ACP_MASK (0x38000U) |
#define | XRDC2_PAC_PDAC_W0_D5ACP_SHIFT (15U) |
#define | XRDC2_PAC_PDAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK) |
#define | XRDC2_PAC_PDAC_W0_D6ACP_MASK (0x1C0000U) |
#define | XRDC2_PAC_PDAC_W0_D6ACP_SHIFT (18U) |
#define | XRDC2_PAC_PDAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK) |
#define | XRDC2_PAC_PDAC_W0_D7ACP_MASK (0xE00000U) |
#define | XRDC2_PAC_PDAC_W0_D7ACP_SHIFT (21U) |
#define | XRDC2_PAC_PDAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK) |
#define | XRDC2_PAC_PDAC_W0_EALO_MASK (0xF000000U) |
#define | XRDC2_PAC_PDAC_W0_EALO_SHIFT (24U) |
#define | XRDC2_PAC_PDAC_W0_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_EALO_SHIFT)) & XRDC2_PAC_PDAC_W0_EALO_MASK) |
PAC_PDAC_W1 - Peripheral Domain Access Control | |
#define | XRDC2_PAC_PDAC_W1_D8ACP_MASK (0x7U) |
#define | XRDC2_PAC_PDAC_W1_D8ACP_SHIFT (0U) |
#define | XRDC2_PAC_PDAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK) |
#define | XRDC2_PAC_PDAC_W1_D9ACP_MASK (0x38U) |
#define | XRDC2_PAC_PDAC_W1_D9ACP_SHIFT (3U) |
#define | XRDC2_PAC_PDAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK) |
#define | XRDC2_PAC_PDAC_W1_D10ACP_MASK (0x1C0U) |
#define | XRDC2_PAC_PDAC_W1_D10ACP_SHIFT (6U) |
#define | XRDC2_PAC_PDAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK) |
#define | XRDC2_PAC_PDAC_W1_D11ACP_MASK (0xE00U) |
#define | XRDC2_PAC_PDAC_W1_D11ACP_SHIFT (9U) |
#define | XRDC2_PAC_PDAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK) |
#define | XRDC2_PAC_PDAC_W1_D12ACP_MASK (0x7000U) |
#define | XRDC2_PAC_PDAC_W1_D12ACP_SHIFT (12U) |
#define | XRDC2_PAC_PDAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK) |
#define | XRDC2_PAC_PDAC_W1_D13ACP_MASK (0x38000U) |
#define | XRDC2_PAC_PDAC_W1_D13ACP_SHIFT (15U) |
#define | XRDC2_PAC_PDAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK) |
#define | XRDC2_PAC_PDAC_W1_D14ACP_MASK (0x1C0000U) |
#define | XRDC2_PAC_PDAC_W1_D14ACP_SHIFT (18U) |
#define | XRDC2_PAC_PDAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK) |
#define | XRDC2_PAC_PDAC_W1_D15ACP_MASK (0xE00000U) |
#define | XRDC2_PAC_PDAC_W1_D15ACP_SHIFT (21U) |
#define | XRDC2_PAC_PDAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK) |
#define | XRDC2_PAC_PDAC_W1_EAL_MASK (0x3000000U) |
#define | XRDC2_PAC_PDAC_W1_EAL_SHIFT (24U) |
#define | XRDC2_PAC_PDAC_W1_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK) |
#define | XRDC2_PAC_PDAC_W1_DL2_MASK (0x60000000U) |
#define | XRDC2_PAC_PDAC_W1_DL2_SHIFT (29U) |
#define | XRDC2_PAC_PDAC_W1_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK) |
#define | XRDC2_PAC_PDAC_W1_VLD_MASK (0x80000000U) |
#define | XRDC2_PAC_PDAC_W1_VLD_SHIFT (31U) |
#define | XRDC2_PAC_PDAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_VLD_SHIFT)) & XRDC2_PAC_PDAC_W1_VLD_MASK) |
MRC_MRGD_W0 - Memory Region Descriptor | |
#define | XRDC2_MRC_MRGD_W0_SRTADDR_MASK (0xFFFFF000U) |
#define | XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT (12U) |
#define | XRDC2_MRC_MRGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W0_SRTADDR_MASK) |
MRC_MRGD_W1 - Memory Region Descriptor | |
#define | XRDC2_MRC_MRGD_W1_SRTADDR_MASK (0xFU) |
#define | XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT (0U) |
#define | XRDC2_MRC_MRGD_W1_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W1_SRTADDR_MASK) |
MRC_MRGD_W2 - Memory Region Descriptor | |
#define | XRDC2_MRC_MRGD_W2_ENDADDR_MASK (0xFFFFF000U) |
#define | XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT (12U) |
#define | XRDC2_MRC_MRGD_W2_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W2_ENDADDR_MASK) |
MRC_MRGD_W3 - Memory Region Descriptor | |
#define | XRDC2_MRC_MRGD_W3_ENDADDR_MASK (0xFU) |
#define | XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT (0U) |
#define | XRDC2_MRC_MRGD_W3_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W3_ENDADDR_MASK) |
MRC_MRGD_W5 - Memory Region Descriptor | |
#define | XRDC2_MRC_MRGD_W5_D0ACP_MASK (0x7U) |
#define | XRDC2_MRC_MRGD_W5_D0ACP_SHIFT (0U) |
#define | XRDC2_MRC_MRGD_W5_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK) |
#define | XRDC2_MRC_MRGD_W5_D1ACP_MASK (0x38U) |
#define | XRDC2_MRC_MRGD_W5_D1ACP_SHIFT (3U) |
#define | XRDC2_MRC_MRGD_W5_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK) |
#define | XRDC2_MRC_MRGD_W5_D2ACP_MASK (0x1C0U) |
#define | XRDC2_MRC_MRGD_W5_D2ACP_SHIFT (6U) |
#define | XRDC2_MRC_MRGD_W5_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK) |
#define | XRDC2_MRC_MRGD_W5_D3ACP_MASK (0xE00U) |
#define | XRDC2_MRC_MRGD_W5_D3ACP_SHIFT (9U) |
#define | XRDC2_MRC_MRGD_W5_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK) |
#define | XRDC2_MRC_MRGD_W5_D4ACP_MASK (0x7000U) |
#define | XRDC2_MRC_MRGD_W5_D4ACP_SHIFT (12U) |
#define | XRDC2_MRC_MRGD_W5_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK) |
#define | XRDC2_MRC_MRGD_W5_D5ACP_MASK (0x38000U) |
#define | XRDC2_MRC_MRGD_W5_D5ACP_SHIFT (15U) |
#define | XRDC2_MRC_MRGD_W5_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK) |
#define | XRDC2_MRC_MRGD_W5_D6ACP_MASK (0x1C0000U) |
#define | XRDC2_MRC_MRGD_W5_D6ACP_SHIFT (18U) |
#define | XRDC2_MRC_MRGD_W5_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK) |
#define | XRDC2_MRC_MRGD_W5_D7ACP_MASK (0xE00000U) |
#define | XRDC2_MRC_MRGD_W5_D7ACP_SHIFT (21U) |
#define | XRDC2_MRC_MRGD_W5_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK) |
#define | XRDC2_MRC_MRGD_W5_EALO_MASK (0xF000000U) |
#define | XRDC2_MRC_MRGD_W5_EALO_SHIFT (24U) |
#define | XRDC2_MRC_MRGD_W5_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_EALO_SHIFT)) & XRDC2_MRC_MRGD_W5_EALO_MASK) |
MRC_MRGD_W6 - Memory Region Descriptor | |
#define | XRDC2_MRC_MRGD_W6_D8ACP_MASK (0x7U) |
#define | XRDC2_MRC_MRGD_W6_D8ACP_SHIFT (0U) |
#define | XRDC2_MRC_MRGD_W6_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK) |
#define | XRDC2_MRC_MRGD_W6_D9ACP_MASK (0x38U) |
#define | XRDC2_MRC_MRGD_W6_D9ACP_SHIFT (3U) |
#define | XRDC2_MRC_MRGD_W6_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK) |
#define | XRDC2_MRC_MRGD_W6_D10ACP_MASK (0x1C0U) |
#define | XRDC2_MRC_MRGD_W6_D10ACP_SHIFT (6U) |
#define | XRDC2_MRC_MRGD_W6_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK) |
#define | XRDC2_MRC_MRGD_W6_D11ACP_MASK (0xE00U) |
#define | XRDC2_MRC_MRGD_W6_D11ACP_SHIFT (9U) |
#define | XRDC2_MRC_MRGD_W6_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK) |
#define | XRDC2_MRC_MRGD_W6_D12ACP_MASK (0x7000U) |
#define | XRDC2_MRC_MRGD_W6_D12ACP_SHIFT (12U) |
#define | XRDC2_MRC_MRGD_W6_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK) |
#define | XRDC2_MRC_MRGD_W6_D13ACP_MASK (0x38000U) |
#define | XRDC2_MRC_MRGD_W6_D13ACP_SHIFT (15U) |
#define | XRDC2_MRC_MRGD_W6_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK) |
#define | XRDC2_MRC_MRGD_W6_D14ACP_MASK (0x1C0000U) |
#define | XRDC2_MRC_MRGD_W6_D14ACP_SHIFT (18U) |
#define | XRDC2_MRC_MRGD_W6_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK) |
#define | XRDC2_MRC_MRGD_W6_D15ACP_MASK (0xE00000U) |
#define | XRDC2_MRC_MRGD_W6_D15ACP_SHIFT (21U) |
#define | XRDC2_MRC_MRGD_W6_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK) |
#define | XRDC2_MRC_MRGD_W6_EAL_MASK (0x3000000U) |
#define | XRDC2_MRC_MRGD_W6_EAL_SHIFT (24U) |
#define | XRDC2_MRC_MRGD_W6_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK) |
#define | XRDC2_MRC_MRGD_W6_DL2_MASK (0x60000000U) |
#define | XRDC2_MRC_MRGD_W6_DL2_SHIFT (29U) |
#define | XRDC2_MRC_MRGD_W6_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK) |
#define | XRDC2_MRC_MRGD_W6_VLD_MASK (0x80000000U) |
#define | XRDC2_MRC_MRGD_W6_VLD_SHIFT (31U) |
#define | XRDC2_MRC_MRGD_W6_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_VLD_SHIFT)) & XRDC2_MRC_MRGD_W6_VLD_MASK) |
Typedefs | |
typedef enum IRQn | IRQn_Type |
typedef enum _rdc_master | rdc_master_t |
Structure for the RDC mapping. | |
typedef enum _rdc_mem | rdc_mem_t |
typedef enum _rdc_periph | rdc_periph_t |
typedef enum _xbar_input_signal | xbar_input_signal_t |
typedef enum _xbar_output_signal | xbar_output_signal_t |
typedef enum _dma_request_source | dma_request_source_t |
Structure for the DMA hardware request. | |
typedef enum _iomuxc_lpsr_sw_mux_ctl_pad | iomuxc_lpsr_sw_mux_ctl_pad_t |
Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD. | |
typedef enum _iomuxc_lpsr_sw_pad_ctl_pad | iomuxc_lpsr_sw_pad_ctl_pad_t |
Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD. | |
typedef enum _iomuxc_lpsr_select_input | iomuxc_lpsr_select_input_t |
Enumeration for the IOMUXC_LPSR select input. | |
typedef enum _ssarc_power_domain_name | ssarc_power_domain_name_t |
Structure for the SSARC mapping. | |
typedef enum _ssarc_cpu_domain_name | ssarc_cpu_domain_name_t |
typedef enum _xrdc2_master | xrdc2_master_t |
Structure for the XRDC2 mapping. | |
typedef enum _xrdc2_mem | xrdc2_mem_t |
typedef enum _xrdc2_mem_slot | xrdc2_mem_slot_t |
typedef enum _xrdc2_periph | xrdc2_periph_t |
typedef enum _asrc_clock_source | asrc_clock_source_t |
The ASRC clock source. | |
typedef enum _iomuxc_sw_mux_ctl_pad | iomuxc_sw_mux_ctl_pad_t |
Enumeration for the IOMUXC SW_MUX_CTL_PAD. | |
typedef enum _iomuxc_sw_pad_ctl_pad | iomuxc_sw_pad_ctl_pad_t |
Enumeration for the IOMUXC SW_PAD_CTL_PAD. | |
typedef enum _iomuxc_select_input | iomuxc_select_input_t |
Enumeration for the IOMUXC select input. | |
CMSIS Peripheral Access Layer for MIMXRT1166_cm4.
CMSIS Peripheral Access Layer for MIMXRT1166_cm4
#define _MIMXRT1166_CM4_H_ |
Symbol preventing repeated inclusion
#define MCU_MEM_MAP_VERSION 0x0000U |
Memory map major version (memory maps with equal major version number are compatible)
#define MCU_MEM_MAP_VERSION_MINOR 0x0001U |
Memory map minor version