Macros
#define	IEE_REGATTR_COUNT (8U)

#define	IEE_REGPO_COUNT (8U)

#define	IEE_REGKEY1_COUNT (8U)

#define	IEE_REGKEY1_COUNT2 (8U)

#define	IEE_REGKEY2_COUNT (8U)

#define	IEE_REGKEY2_COUNT2 (8U)

#define	IEE_AES_TST_DB_COUNT (32U)

#define	IEE_REGATTR_COUNT (8U)

#define	IEE_REGPO_COUNT (8U)

#define	IEE_REGKEY1_COUNT (8U)

#define	IEE_REGKEY1_COUNT2 (8U)

#define	IEE_REGKEY2_COUNT (8U)

#define	IEE_REGKEY2_COUNT2 (8U)

#define	IEE_AES_TST_DB_COUNT (32U)

GCFG - IEE Global Configuration
#define	IEE_GCFG_RL0_MASK (0x1U)

#define	IEE_GCFG_RL0_SHIFT (0U)

#define	IEE_GCFG_RL0(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK)

#define	IEE_GCFG_RL1_MASK (0x2U)

#define	IEE_GCFG_RL1_SHIFT (1U)

#define	IEE_GCFG_RL1(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK)

#define	IEE_GCFG_RL2_MASK (0x4U)

#define	IEE_GCFG_RL2_SHIFT (2U)

#define	IEE_GCFG_RL2(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK)

#define	IEE_GCFG_RL3_MASK (0x8U)

#define	IEE_GCFG_RL3_SHIFT (3U)

#define	IEE_GCFG_RL3(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK)

#define	IEE_GCFG_RL4_MASK (0x10U)

#define	IEE_GCFG_RL4_SHIFT (4U)

#define	IEE_GCFG_RL4(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK)

#define	IEE_GCFG_RL5_MASK (0x20U)

#define	IEE_GCFG_RL5_SHIFT (5U)

#define	IEE_GCFG_RL5(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK)

#define	IEE_GCFG_RL6_MASK (0x40U)

#define	IEE_GCFG_RL6_SHIFT (6U)

#define	IEE_GCFG_RL6(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK)

#define	IEE_GCFG_RL7_MASK (0x80U)

#define	IEE_GCFG_RL7_SHIFT (7U)

#define	IEE_GCFG_RL7(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK)

#define	IEE_GCFG_TME_MASK (0x10000U)

#define	IEE_GCFG_TME_SHIFT (16U)

#define	IEE_GCFG_TME(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK)

#define	IEE_GCFG_TMD_MASK (0x20000U)

#define	IEE_GCFG_TMD_SHIFT (17U)

#define	IEE_GCFG_TMD(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK)

#define	IEE_GCFG_KEY_RD_DIS_MASK (0x2000000U)

#define	IEE_GCFG_KEY_RD_DIS_SHIFT (25U)

#define	IEE_GCFG_KEY_RD_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK)

#define	IEE_GCFG_MON_EN_MASK (0x10000000U)

#define	IEE_GCFG_MON_EN_SHIFT (28U)

#define	IEE_GCFG_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK)

#define	IEE_GCFG_CLR_MON_MASK (0x20000000U)

#define	IEE_GCFG_CLR_MON_SHIFT (29U)

#define	IEE_GCFG_CLR_MON(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK)

#define	IEE_GCFG_RST_MASK (0x80000000U)

#define	IEE_GCFG_RST_SHIFT (31U)

#define	IEE_GCFG_RST(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RST_SHIFT)) & IEE_GCFG_RST_MASK)

STA - IEE Status
#define	IEE_STA_DSR_MASK (0x1U)

#define	IEE_STA_DSR_SHIFT (0U)

#define	IEE_STA_DSR(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK)

#define	IEE_STA_AFD_MASK (0x10U)

#define	IEE_STA_AFD_SHIFT (4U)

#define	IEE_STA_AFD(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK)

TSTMD - IEE Test Mode Register
#define	IEE_TSTMD_TMRDY_MASK (0x1U)

#define	IEE_TSTMD_TMRDY_SHIFT (0U)

#define	IEE_TSTMD_TMRDY(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK)

#define	IEE_TSTMD_TMR_MASK (0x2U)

#define	IEE_TSTMD_TMR_SHIFT (1U)

#define	IEE_TSTMD_TMR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK)

#define	IEE_TSTMD_TMENCR_MASK (0x4U)

#define	IEE_TSTMD_TMENCR_SHIFT (2U)

#define	IEE_TSTMD_TMENCR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK)

#define	IEE_TSTMD_TMCONT_MASK (0x8U)

#define	IEE_TSTMD_TMCONT_SHIFT (3U)

#define	IEE_TSTMD_TMCONT(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK)

#define	IEE_TSTMD_TMDONE_MASK (0x10U)

#define	IEE_TSTMD_TMDONE_SHIFT (4U)

#define	IEE_TSTMD_TMDONE(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK)

#define	IEE_TSTMD_TMLEN_MASK (0xF00U)

#define	IEE_TSTMD_TMLEN_SHIFT (8U)

#define	IEE_TSTMD_TMLEN(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMLEN_SHIFT)) & IEE_TSTMD_TMLEN_MASK)

DPAMS - AES Mask Generation Seed
#define	IEE_DPAMS_DPAMS_MASK (0xFFFFFFFFU)

#define	IEE_DPAMS_DPAMS_SHIFT (0U)

#define	IEE_DPAMS_DPAMS(x) (((uint32_t)(((uint32_t)(x)) << IEE_DPAMS_DPAMS_SHIFT)) & IEE_DPAMS_DPAMS_MASK)

PC_S_LT - Performance Counter, AES Slave Latency Threshold Value
#define	IEE_PC_S_LT_SW_LT_MASK (0xFFFFU)

#define	IEE_PC_S_LT_SW_LT_SHIFT (0U)

#define	IEE_PC_S_LT_SW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SW_LT_SHIFT)) & IEE_PC_S_LT_SW_LT_MASK)

#define	IEE_PC_S_LT_SR_LT_MASK (0xFFFF0000U)

#define	IEE_PC_S_LT_SR_LT_SHIFT (16U)

#define	IEE_PC_S_LT_SR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SR_LT_SHIFT)) & IEE_PC_S_LT_SR_LT_MASK)

PC_M_LT - Performance Counter, AES Master Latency Threshold
#define	IEE_PC_M_LT_MW_LT_MASK (0xFFFU)

#define	IEE_PC_M_LT_MW_LT_SHIFT (0U)

#define	IEE_PC_M_LT_MW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MW_LT_SHIFT)) & IEE_PC_M_LT_MW_LT_MASK)

#define	IEE_PC_M_LT_MR_LT_MASK (0xFFF0000U)

#define	IEE_PC_M_LT_MR_LT_SHIFT (16U)

#define	IEE_PC_M_LT_MR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MR_LT_SHIFT)) & IEE_PC_M_LT_MR_LT_MASK)

PC_BLK_ENC - Performance Counter, Number of AES Block Encryptions
#define	IEE_PC_BLK_ENC_BLK_ENC_MASK (0xFFFFFFFFU)

#define	IEE_PC_BLK_ENC_BLK_ENC_SHIFT (0U)

#define	IEE_PC_BLK_ENC_BLK_ENC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_ENC_BLK_ENC_SHIFT)) & IEE_PC_BLK_ENC_BLK_ENC_MASK)

PC_BLK_DEC - Performance Counter, Number of AES Block Decryptions
#define	IEE_PC_BLK_DEC_BLK_DEC_MASK (0xFFFFFFFFU)

#define	IEE_PC_BLK_DEC_BLK_DEC_SHIFT (0U)

#define	IEE_PC_BLK_DEC_BLK_DEC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_DEC_BLK_DEC_SHIFT)) & IEE_PC_BLK_DEC_BLK_DEC_MASK)

PC_SR_TRANS - Performance Counter, Number of AXI Slave Read Transactions
#define	IEE_PC_SR_TRANS_SR_TRANS_MASK (0xFFFFFFFFU)

#define	IEE_PC_SR_TRANS_SR_TRANS_SHIFT (0U)

#define	IEE_PC_SR_TRANS_SR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TRANS_SR_TRANS_SHIFT)) & IEE_PC_SR_TRANS_SR_TRANS_MASK)

PC_SW_TRANS - Performance Counter, Number of AXI Slave Write Transactions
#define	IEE_PC_SW_TRANS_SW_TRANS_MASK (0xFFFFFFFFU)

#define	IEE_PC_SW_TRANS_SW_TRANS_SHIFT (0U)

#define	IEE_PC_SW_TRANS_SW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TRANS_SW_TRANS_SHIFT)) & IEE_PC_SW_TRANS_SW_TRANS_MASK)

PC_MR_TRANS - Performance Counter, Number of AXI Master Read Transactions
#define	IEE_PC_MR_TRANS_MR_TRANS_MASK (0xFFFFFFFFU)

#define	IEE_PC_MR_TRANS_MR_TRANS_SHIFT (0U)

#define	IEE_PC_MR_TRANS_MR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TRANS_MR_TRANS_SHIFT)) & IEE_PC_MR_TRANS_MR_TRANS_MASK)

PC_MW_TRANS - Performance Counter, Number of AXI Master Write Transactions
#define	IEE_PC_MW_TRANS_MW_TRANS_MASK (0xFFFFFFFFU)

#define	IEE_PC_MW_TRANS_MW_TRANS_SHIFT (0U)

#define	IEE_PC_MW_TRANS_MW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TRANS_MW_TRANS_SHIFT)) & IEE_PC_MW_TRANS_MW_TRANS_MASK)

PC_M_MBR - Performance Counter, Number of AXI Master Merge Buffer Read Transactions
#define	IEE_PC_M_MBR_M_MBR_MASK (0xFFFFFFFFU)

#define	IEE_PC_M_MBR_M_MBR_SHIFT (0U)

#define	IEE_PC_M_MBR_M_MBR(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_MBR_M_MBR_SHIFT)) & IEE_PC_M_MBR_M_MBR_MASK)

PC_SR_TBC_U - Performance Counter, Upper Slave Read Transactions Byte Count
#define	IEE_PC_SR_TBC_U_SR_TBC_MASK (0xFFFFU)

#define	IEE_PC_SR_TBC_U_SR_TBC_SHIFT (0U)

#define	IEE_PC_SR_TBC_U_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_U_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_U_SR_TBC_MASK)

PC_SR_TBC_L - Performance Counter, Lower Slave Read Transactions Byte Count
#define	IEE_PC_SR_TBC_L_SR_TBC_MASK (0xFFFFFFFFU)

#define	IEE_PC_SR_TBC_L_SR_TBC_SHIFT (0U)

#define	IEE_PC_SR_TBC_L_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_L_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_L_SR_TBC_MASK)

PC_SW_TBC_U - Performance Counter, Upper Slave Write Transactions Byte Count
#define	IEE_PC_SW_TBC_U_SW_TBC_MASK (0xFFFFU)

#define	IEE_PC_SW_TBC_U_SW_TBC_SHIFT (0U)

#define	IEE_PC_SW_TBC_U_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_U_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_U_SW_TBC_MASK)

PC_SW_TBC_L - Performance Counter, Lower Slave Write Transactions Byte Count
#define	IEE_PC_SW_TBC_L_SW_TBC_MASK (0xFFFFFFFFU)

#define	IEE_PC_SW_TBC_L_SW_TBC_SHIFT (0U)

#define	IEE_PC_SW_TBC_L_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_L_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_L_SW_TBC_MASK)

PC_MR_TBC_U - Performance Counter, Upper Master Read Transactions Byte Count
#define	IEE_PC_MR_TBC_U_MR_TBC_MASK (0xFFFFU)

#define	IEE_PC_MR_TBC_U_MR_TBC_SHIFT (0U)

#define	IEE_PC_MR_TBC_U_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_U_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_U_MR_TBC_MASK)

PC_MR_TBC_L - Performance Counter, Lower Master Read Transactions Byte Count
#define	IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK (0xFU)

#define	IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT (0U)

#define	IEE_PC_MR_TBC_L_MR_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK)

#define	IEE_PC_MR_TBC_L_MR_TBC_MASK (0xFFFFFFF0U)

#define	IEE_PC_MR_TBC_L_MR_TBC_SHIFT (4U)

#define	IEE_PC_MR_TBC_L_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_MASK)

PC_MW_TBC_U - Performance Counter, Upper Master Write Transactions Byte Count
#define	IEE_PC_MW_TBC_U_MW_TBC_MASK (0xFFFFU)

#define	IEE_PC_MW_TBC_U_MW_TBC_SHIFT (0U)

#define	IEE_PC_MW_TBC_U_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_U_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_U_MW_TBC_MASK)

PC_MW_TBC_L - Performance Counter, Lower Master Write Transactions Byte Count
#define	IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK (0xFU)

#define	IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT (0U)

#define	IEE_PC_MW_TBC_L_MW_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK)

#define	IEE_PC_MW_TBC_L_MW_TBC_MASK (0xFFFFFFF0U)

#define	IEE_PC_MW_TBC_L_MW_TBC_SHIFT (4U)

#define	IEE_PC_MW_TBC_L_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_MASK)

PC_SR_TLGTT - Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold
#define	IEE_PC_SR_TLGTT_SR_TLGTT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT (0U)

#define	IEE_PC_SR_TLGTT_SR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT)) & IEE_PC_SR_TLGTT_SR_TLGTT_MASK)

PC_SW_TLGTT - Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold
#define	IEE_PC_SW_TLGTT_SW_TLGTT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT (0U)

#define	IEE_PC_SW_TLGTT_SW_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT)) & IEE_PC_SW_TLGTT_SW_TLGTT_MASK)

PC_MR_TLGTT - Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold
#define	IEE_PC_MR_TLGTT_MR_TLGTT_MASK (0xFFFFFFFFU)

#define	IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT (0U)

#define	IEE_PC_MR_TLGTT_MR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT)) & IEE_PC_MR_TLGTT_MR_TLGTT_MASK)

PC_MW_TLGTT - Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold
#define	IEE_PC_MW_TLGTT_MW_TGTT_MASK (0xFFFFFFFFU)

#define	IEE_PC_MW_TLGTT_MW_TGTT_SHIFT (0U)

#define	IEE_PC_MW_TLGTT_MW_TGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLGTT_MW_TGTT_SHIFT)) & IEE_PC_MW_TLGTT_MW_TGTT_MASK)

PC_SR_TLAT_U - Performance Counter, Upper Slave Read Latency Count
#define	IEE_PC_SR_TLAT_U_SR_TLAT_MASK (0xFFFFU)

#define	IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT (0U)

#define	IEE_PC_SR_TLAT_U_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_U_SR_TLAT_MASK)

PC_SR_TLAT_L - Performance Counter, Lower Slave Read Latency Count
#define	IEE_PC_SR_TLAT_L_SR_TLAT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT (0U)

#define	IEE_PC_SR_TLAT_L_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_L_SR_TLAT_MASK)

PC_SW_TLAT_U - Performance Counter, Upper Slave Write Latency Count
#define	IEE_PC_SW_TLAT_U_SW_TLAT_MASK (0xFFFFU)

#define	IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT (0U)

#define	IEE_PC_SW_TLAT_U_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_U_SW_TLAT_MASK)

PC_SW_TLAT_L - Performance Counter, Lower Slave Write Latency Count
#define	IEE_PC_SW_TLAT_L_SW_TLAT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT (0U)

#define	IEE_PC_SW_TLAT_L_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_L_SW_TLAT_MASK)

PC_MR_TLAT_U - Performance Counter, Upper Master Read Latency Count
#define	IEE_PC_MR_TLAT_U_MR_TLAT_MASK (0xFFFFU)

#define	IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT (0U)

#define	IEE_PC_MR_TLAT_U_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_U_MR_TLAT_MASK)

PC_MR_TLAT_L - Performance Counter, Lower Master Read Latency Count
#define	IEE_PC_MR_TLAT_L_MR_TLAT_MASK (0xFFFFFFFFU)

#define	IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT (0U)

#define	IEE_PC_MR_TLAT_L_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_L_MR_TLAT_MASK)

PC_MW_TLAT_U - Performance Counter, Upper Master Write Latency Count
#define	IEE_PC_MW_TLAT_U_MW_TLAT_MASK (0xFFFFU)

#define	IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT (0U)

#define	IEE_PC_MW_TLAT_U_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_U_MW_TLAT_MASK)

PC_MW_TLAT_L - Performance Counter, Lower Master Write Latency Count
#define	IEE_PC_MW_TLAT_L_MW_TLAT_MASK (0xFFFFFFFFU)

#define	IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT (0U)

#define	IEE_PC_MW_TLAT_L_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_L_MW_TLAT_MASK)

PC_SR_TNRT_U - Performance Counter, Upper Slave Read Total Non-Responding Time
#define	IEE_PC_SR_TNRT_U_SR_TNRT_MASK (0xFFFFU)

#define	IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT (0U)

#define	IEE_PC_SR_TNRT_U_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_U_SR_TNRT_MASK)

PC_SR_TNRT_L - Performance Counter, Lower Slave Read Total Non-Responding Time
#define	IEE_PC_SR_TNRT_L_SR_TNRT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT (0U)

#define	IEE_PC_SR_TNRT_L_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_L_SR_TNRT_MASK)

PC_SW_TNRT_U - Performance Counter, Upper Slave Write Total Non-Responding Time
#define	IEE_PC_SW_TNRT_U_SW_TNRT_MASK (0xFFFFU)

#define	IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT (0U)

#define	IEE_PC_SW_TNRT_U_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_U_SW_TNRT_MASK)

PC_SW_TNRT_L - Performance Counter, Lower Slave Write Total Non-Responding Time
#define	IEE_PC_SW_TNRT_L_SW_TNRT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT (0U)

#define	IEE_PC_SW_TNRT_L_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_L_SW_TNRT_MASK)

VIDR1 - IEE Version ID Register 1
#define	IEE_VIDR1_MIN_REV_MASK (0xFFU)

#define	IEE_VIDR1_MIN_REV_SHIFT (0U)

#define	IEE_VIDR1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MIN_REV_SHIFT)) & IEE_VIDR1_MIN_REV_MASK)

#define	IEE_VIDR1_MAJ_REV_MASK (0xFF00U)

#define	IEE_VIDR1_MAJ_REV_SHIFT (8U)

#define	IEE_VIDR1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MAJ_REV_SHIFT)) & IEE_VIDR1_MAJ_REV_MASK)

#define	IEE_VIDR1_IP_ID_MASK (0xFFFF0000U)

#define	IEE_VIDR1_IP_ID_SHIFT (16U)

#define	IEE_VIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_IP_ID_SHIFT)) & IEE_VIDR1_IP_ID_MASK)

AESVID - IEE AES Version ID Register
#define	IEE_AESVID_AESRN_MASK (0xFU)

#define	IEE_AESVID_AESRN_SHIFT (0U)

#define	IEE_AESVID_AESRN(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESRN_SHIFT)) & IEE_AESVID_AESRN_MASK)

#define	IEE_AESVID_AESVID_MASK (0xF0U)

#define	IEE_AESVID_AESVID_SHIFT (4U)

#define	IEE_AESVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESVID_SHIFT)) & IEE_AESVID_AESVID_MASK)

REGATTR - IEE Region 0 Attribute Register...IEE Region 7 Attribute Register.
#define	IEE_REGATTR_KS_MASK (0x1U)

#define	IEE_REGATTR_KS_SHIFT (0U)

#define	IEE_REGATTR_KS(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK)

#define	IEE_REGATTR_MD_MASK (0x70U)

#define	IEE_REGATTR_MD_SHIFT (4U)

#define	IEE_REGATTR_MD(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK)

#define	IEE_REGATTR_BYP_MASK (0x80U)

#define	IEE_REGATTR_BYP_SHIFT (7U)

#define	IEE_REGATTR_BYP(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_BYP_SHIFT)) & IEE_REGATTR_BYP_MASK)

REGPO - IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register
#define	IEE_REGPO_PGOFF_MASK (0xFFFFFFU)

#define	IEE_REGPO_PGOFF_SHIFT (0U)

#define	IEE_REGPO_PGOFF(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGPO_PGOFF_SHIFT)) & IEE_REGPO_PGOFF_MASK)

REGKEY1 - IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register
#define	IEE_REGKEY1_KEY1_MASK (0xFFFFFFFFU)

#define	IEE_REGKEY1_KEY1_SHIFT (0U)

#define	IEE_REGKEY1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY1_KEY1_SHIFT)) & IEE_REGKEY1_KEY1_MASK)

REGKEY2 - IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register
#define	IEE_REGKEY2_KEY2_MASK (0xFFFFFFFFU)

#define	IEE_REGKEY2_KEY2_SHIFT (0U)

#define	IEE_REGKEY2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY2_KEY2_SHIFT)) & IEE_REGKEY2_KEY2_MASK)

AES_TST_DB - IEE AES Test Mode Data Buffer
#define	IEE_AES_TST_DB_AES_TST_DB0_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB0_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB0(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB0_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB0_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB1_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB1_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB1(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB1_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB1_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB2_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB2_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB2(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB2_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB2_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB3_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB3_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB3(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB3_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB3_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB4_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB4_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB4(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB4_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB4_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB5_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB5_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB5(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB5_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB5_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB6_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB6_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB6(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB6_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB6_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB7_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB7_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB7(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB7_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB7_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB8_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB8_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB8(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB8_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB8_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB9_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB9_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB9(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB9_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB9_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB10_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB10_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB10(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB10_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB10_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB11_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB11_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB11(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB11_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB11_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB12_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB12_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB12(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB12_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB12_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB13_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB13_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB13(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB13_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB13_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB14_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB14_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB14(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB14_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB14_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB15_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB15_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB15(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB15_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB15_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB16_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB16_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB16(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB16_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB16_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB17_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB17_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB17(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB17_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB17_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB18_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB18_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB18(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB18_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB18_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB19_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB19_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB19(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB19_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB19_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB20_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB20_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB20(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB20_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB20_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB21_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB21_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB21(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB21_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB21_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB22_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB22_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB22(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB22_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB22_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB23_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB23_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB23(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB23_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB23_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB24_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB24_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB24(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB24_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB24_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB25_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB25_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB25(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB25_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB25_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB26_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB26_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB26(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB26_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB26_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB27_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB27_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB27(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB27_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB27_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB28_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB28_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB28(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB28_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB28_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB29_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB29_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB29(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB29_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB29_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB30_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB30_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB30(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB30_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB30_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB31_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB31_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB31(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB31_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB31_MASK)

GCFG - IEE Global Configuration
#define	IEE_GCFG_RL0_MASK (0x1U)

#define	IEE_GCFG_RL0_SHIFT (0U)

#define	IEE_GCFG_RL0(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK)

#define	IEE_GCFG_RL1_MASK (0x2U)

#define	IEE_GCFG_RL1_SHIFT (1U)

#define	IEE_GCFG_RL1(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK)

#define	IEE_GCFG_RL2_MASK (0x4U)

#define	IEE_GCFG_RL2_SHIFT (2U)

#define	IEE_GCFG_RL2(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK)

#define	IEE_GCFG_RL3_MASK (0x8U)

#define	IEE_GCFG_RL3_SHIFT (3U)

#define	IEE_GCFG_RL3(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK)

#define	IEE_GCFG_RL4_MASK (0x10U)

#define	IEE_GCFG_RL4_SHIFT (4U)

#define	IEE_GCFG_RL4(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK)

#define	IEE_GCFG_RL5_MASK (0x20U)

#define	IEE_GCFG_RL5_SHIFT (5U)

#define	IEE_GCFG_RL5(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK)

#define	IEE_GCFG_RL6_MASK (0x40U)

#define	IEE_GCFG_RL6_SHIFT (6U)

#define	IEE_GCFG_RL6(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK)

#define	IEE_GCFG_RL7_MASK (0x80U)

#define	IEE_GCFG_RL7_SHIFT (7U)

#define	IEE_GCFG_RL7(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK)

#define	IEE_GCFG_TME_MASK (0x10000U)

#define	IEE_GCFG_TME_SHIFT (16U)

#define	IEE_GCFG_TME(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK)

#define	IEE_GCFG_TMD_MASK (0x20000U)

#define	IEE_GCFG_TMD_SHIFT (17U)

#define	IEE_GCFG_TMD(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK)

#define	IEE_GCFG_KEY_RD_DIS_MASK (0x2000000U)

#define	IEE_GCFG_KEY_RD_DIS_SHIFT (25U)

#define	IEE_GCFG_KEY_RD_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK)

#define	IEE_GCFG_MON_EN_MASK (0x10000000U)

#define	IEE_GCFG_MON_EN_SHIFT (28U)

#define	IEE_GCFG_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK)

#define	IEE_GCFG_CLR_MON_MASK (0x20000000U)

#define	IEE_GCFG_CLR_MON_SHIFT (29U)

#define	IEE_GCFG_CLR_MON(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK)

#define	IEE_GCFG_RST_MASK (0x80000000U)

#define	IEE_GCFG_RST_SHIFT (31U)

#define	IEE_GCFG_RST(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RST_SHIFT)) & IEE_GCFG_RST_MASK)

STA - IEE Status
#define	IEE_STA_DSR_MASK (0x1U)

#define	IEE_STA_DSR_SHIFT (0U)

#define	IEE_STA_DSR(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK)

#define	IEE_STA_AFD_MASK (0x10U)

#define	IEE_STA_AFD_SHIFT (4U)

#define	IEE_STA_AFD(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK)

TSTMD - IEE Test Mode Register
#define	IEE_TSTMD_TMRDY_MASK (0x1U)

#define	IEE_TSTMD_TMRDY_SHIFT (0U)

#define	IEE_TSTMD_TMRDY(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK)

#define	IEE_TSTMD_TMR_MASK (0x2U)

#define	IEE_TSTMD_TMR_SHIFT (1U)

#define	IEE_TSTMD_TMR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK)

#define	IEE_TSTMD_TMENCR_MASK (0x4U)

#define	IEE_TSTMD_TMENCR_SHIFT (2U)

#define	IEE_TSTMD_TMENCR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK)

#define	IEE_TSTMD_TMCONT_MASK (0x8U)

#define	IEE_TSTMD_TMCONT_SHIFT (3U)

#define	IEE_TSTMD_TMCONT(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK)

#define	IEE_TSTMD_TMDONE_MASK (0x10U)

#define	IEE_TSTMD_TMDONE_SHIFT (4U)

#define	IEE_TSTMD_TMDONE(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK)

#define	IEE_TSTMD_TMLEN_MASK (0xF00U)

#define	IEE_TSTMD_TMLEN_SHIFT (8U)

#define	IEE_TSTMD_TMLEN(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMLEN_SHIFT)) & IEE_TSTMD_TMLEN_MASK)

DPAMS - AES Mask Generation Seed
#define	IEE_DPAMS_DPAMS_MASK (0xFFFFFFFFU)

#define	IEE_DPAMS_DPAMS_SHIFT (0U)

#define	IEE_DPAMS_DPAMS(x) (((uint32_t)(((uint32_t)(x)) << IEE_DPAMS_DPAMS_SHIFT)) & IEE_DPAMS_DPAMS_MASK)

PC_S_LT - Performance Counter, AES Slave Latency Threshold Value
#define	IEE_PC_S_LT_SW_LT_MASK (0xFFFFU)

#define	IEE_PC_S_LT_SW_LT_SHIFT (0U)

#define	IEE_PC_S_LT_SW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SW_LT_SHIFT)) & IEE_PC_S_LT_SW_LT_MASK)

#define	IEE_PC_S_LT_SR_LT_MASK (0xFFFF0000U)

#define	IEE_PC_S_LT_SR_LT_SHIFT (16U)

#define	IEE_PC_S_LT_SR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SR_LT_SHIFT)) & IEE_PC_S_LT_SR_LT_MASK)

PC_M_LT - Performance Counter, AES Master Latency Threshold
#define	IEE_PC_M_LT_MW_LT_MASK (0xFFFU)

#define	IEE_PC_M_LT_MW_LT_SHIFT (0U)

#define	IEE_PC_M_LT_MW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MW_LT_SHIFT)) & IEE_PC_M_LT_MW_LT_MASK)

#define	IEE_PC_M_LT_MR_LT_MASK (0xFFF0000U)

#define	IEE_PC_M_LT_MR_LT_SHIFT (16U)

#define	IEE_PC_M_LT_MR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MR_LT_SHIFT)) & IEE_PC_M_LT_MR_LT_MASK)

PC_BLK_ENC - Performance Counter, Number of AES Block Encryptions
#define	IEE_PC_BLK_ENC_BLK_ENC_MASK (0xFFFFFFFFU)

#define	IEE_PC_BLK_ENC_BLK_ENC_SHIFT (0U)

#define	IEE_PC_BLK_ENC_BLK_ENC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_ENC_BLK_ENC_SHIFT)) & IEE_PC_BLK_ENC_BLK_ENC_MASK)

PC_BLK_DEC - Performance Counter, Number of AES Block Decryptions
#define	IEE_PC_BLK_DEC_BLK_DEC_MASK (0xFFFFFFFFU)

#define	IEE_PC_BLK_DEC_BLK_DEC_SHIFT (0U)

#define	IEE_PC_BLK_DEC_BLK_DEC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_DEC_BLK_DEC_SHIFT)) & IEE_PC_BLK_DEC_BLK_DEC_MASK)

PC_SR_TRANS - Performance Counter, Number of AXI Slave Read Transactions
#define	IEE_PC_SR_TRANS_SR_TRANS_MASK (0xFFFFFFFFU)

#define	IEE_PC_SR_TRANS_SR_TRANS_SHIFT (0U)

#define	IEE_PC_SR_TRANS_SR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TRANS_SR_TRANS_SHIFT)) & IEE_PC_SR_TRANS_SR_TRANS_MASK)

PC_SW_TRANS - Performance Counter, Number of AXI Slave Write Transactions
#define	IEE_PC_SW_TRANS_SW_TRANS_MASK (0xFFFFFFFFU)

#define	IEE_PC_SW_TRANS_SW_TRANS_SHIFT (0U)

#define	IEE_PC_SW_TRANS_SW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TRANS_SW_TRANS_SHIFT)) & IEE_PC_SW_TRANS_SW_TRANS_MASK)

PC_MR_TRANS - Performance Counter, Number of AXI Master Read Transactions
#define	IEE_PC_MR_TRANS_MR_TRANS_MASK (0xFFFFFFFFU)

#define	IEE_PC_MR_TRANS_MR_TRANS_SHIFT (0U)

#define	IEE_PC_MR_TRANS_MR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TRANS_MR_TRANS_SHIFT)) & IEE_PC_MR_TRANS_MR_TRANS_MASK)

PC_MW_TRANS - Performance Counter, Number of AXI Master Write Transactions
#define	IEE_PC_MW_TRANS_MW_TRANS_MASK (0xFFFFFFFFU)

#define	IEE_PC_MW_TRANS_MW_TRANS_SHIFT (0U)

#define	IEE_PC_MW_TRANS_MW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TRANS_MW_TRANS_SHIFT)) & IEE_PC_MW_TRANS_MW_TRANS_MASK)

PC_M_MBR - Performance Counter, Number of AXI Master Merge Buffer Read Transactions
#define	IEE_PC_M_MBR_M_MBR_MASK (0xFFFFFFFFU)

#define	IEE_PC_M_MBR_M_MBR_SHIFT (0U)

#define	IEE_PC_M_MBR_M_MBR(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_MBR_M_MBR_SHIFT)) & IEE_PC_M_MBR_M_MBR_MASK)

PC_SR_TBC_U - Performance Counter, Upper Slave Read Transactions Byte Count
#define	IEE_PC_SR_TBC_U_SR_TBC_MASK (0xFFFFU)

#define	IEE_PC_SR_TBC_U_SR_TBC_SHIFT (0U)

#define	IEE_PC_SR_TBC_U_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_U_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_U_SR_TBC_MASK)

PC_SR_TBC_L - Performance Counter, Lower Slave Read Transactions Byte Count
#define	IEE_PC_SR_TBC_L_SR_TBC_MASK (0xFFFFFFFFU)

#define	IEE_PC_SR_TBC_L_SR_TBC_SHIFT (0U)

#define	IEE_PC_SR_TBC_L_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_L_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_L_SR_TBC_MASK)

PC_SW_TBC_U - Performance Counter, Upper Slave Write Transactions Byte Count
#define	IEE_PC_SW_TBC_U_SW_TBC_MASK (0xFFFFU)

#define	IEE_PC_SW_TBC_U_SW_TBC_SHIFT (0U)

#define	IEE_PC_SW_TBC_U_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_U_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_U_SW_TBC_MASK)

PC_SW_TBC_L - Performance Counter, Lower Slave Write Transactions Byte Count
#define	IEE_PC_SW_TBC_L_SW_TBC_MASK (0xFFFFFFFFU)

#define	IEE_PC_SW_TBC_L_SW_TBC_SHIFT (0U)

#define	IEE_PC_SW_TBC_L_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_L_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_L_SW_TBC_MASK)

PC_MR_TBC_U - Performance Counter, Upper Master Read Transactions Byte Count
#define	IEE_PC_MR_TBC_U_MR_TBC_MASK (0xFFFFU)

#define	IEE_PC_MR_TBC_U_MR_TBC_SHIFT (0U)

#define	IEE_PC_MR_TBC_U_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_U_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_U_MR_TBC_MASK)

PC_MR_TBC_L - Performance Counter, Lower Master Read Transactions Byte Count
#define	IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK (0xFU)

#define	IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT (0U)

#define	IEE_PC_MR_TBC_L_MR_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK)

#define	IEE_PC_MR_TBC_L_MR_TBC_MASK (0xFFFFFFF0U)

#define	IEE_PC_MR_TBC_L_MR_TBC_SHIFT (4U)

#define	IEE_PC_MR_TBC_L_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_MASK)

PC_MW_TBC_U - Performance Counter, Upper Master Write Transactions Byte Count
#define	IEE_PC_MW_TBC_U_MW_TBC_MASK (0xFFFFU)

#define	IEE_PC_MW_TBC_U_MW_TBC_SHIFT (0U)

#define	IEE_PC_MW_TBC_U_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_U_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_U_MW_TBC_MASK)

PC_MW_TBC_L - Performance Counter, Lower Master Write Transactions Byte Count
#define	IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK (0xFU)

#define	IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT (0U)

#define	IEE_PC_MW_TBC_L_MW_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK)

#define	IEE_PC_MW_TBC_L_MW_TBC_MASK (0xFFFFFFF0U)

#define	IEE_PC_MW_TBC_L_MW_TBC_SHIFT (4U)

#define	IEE_PC_MW_TBC_L_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_MASK)

PC_SR_TLGTT - Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold
#define	IEE_PC_SR_TLGTT_SR_TLGTT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT (0U)

#define	IEE_PC_SR_TLGTT_SR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT)) & IEE_PC_SR_TLGTT_SR_TLGTT_MASK)

PC_SW_TLGTT - Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold
#define	IEE_PC_SW_TLGTT_SW_TLGTT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT (0U)

#define	IEE_PC_SW_TLGTT_SW_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT)) & IEE_PC_SW_TLGTT_SW_TLGTT_MASK)

PC_MR_TLGTT - Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold
#define	IEE_PC_MR_TLGTT_MR_TLGTT_MASK (0xFFFFFFFFU)

#define	IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT (0U)

#define	IEE_PC_MR_TLGTT_MR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT)) & IEE_PC_MR_TLGTT_MR_TLGTT_MASK)

PC_MW_TLGTT - Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold
#define	IEE_PC_MW_TLGTT_MW_TGTT_MASK (0xFFFFFFFFU)

#define	IEE_PC_MW_TLGTT_MW_TGTT_SHIFT (0U)

#define	IEE_PC_MW_TLGTT_MW_TGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLGTT_MW_TGTT_SHIFT)) & IEE_PC_MW_TLGTT_MW_TGTT_MASK)

PC_SR_TLAT_U - Performance Counter, Upper Slave Read Latency Count
#define	IEE_PC_SR_TLAT_U_SR_TLAT_MASK (0xFFFFU)

#define	IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT (0U)

#define	IEE_PC_SR_TLAT_U_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_U_SR_TLAT_MASK)

PC_SR_TLAT_L - Performance Counter, Lower Slave Read Latency Count
#define	IEE_PC_SR_TLAT_L_SR_TLAT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT (0U)

#define	IEE_PC_SR_TLAT_L_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_L_SR_TLAT_MASK)

PC_SW_TLAT_U - Performance Counter, Upper Slave Write Latency Count
#define	IEE_PC_SW_TLAT_U_SW_TLAT_MASK (0xFFFFU)

#define	IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT (0U)

#define	IEE_PC_SW_TLAT_U_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_U_SW_TLAT_MASK)

PC_SW_TLAT_L - Performance Counter, Lower Slave Write Latency Count
#define	IEE_PC_SW_TLAT_L_SW_TLAT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT (0U)

#define	IEE_PC_SW_TLAT_L_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_L_SW_TLAT_MASK)

PC_MR_TLAT_U - Performance Counter, Upper Master Read Latency Count
#define	IEE_PC_MR_TLAT_U_MR_TLAT_MASK (0xFFFFU)

#define	IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT (0U)

#define	IEE_PC_MR_TLAT_U_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_U_MR_TLAT_MASK)

PC_MR_TLAT_L - Performance Counter, Lower Master Read Latency Count
#define	IEE_PC_MR_TLAT_L_MR_TLAT_MASK (0xFFFFFFFFU)

#define	IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT (0U)

#define	IEE_PC_MR_TLAT_L_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_L_MR_TLAT_MASK)

PC_MW_TLAT_U - Performance Counter, Upper Master Write Latency Count
#define	IEE_PC_MW_TLAT_U_MW_TLAT_MASK (0xFFFFU)

#define	IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT (0U)

#define	IEE_PC_MW_TLAT_U_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_U_MW_TLAT_MASK)

PC_MW_TLAT_L - Performance Counter, Lower Master Write Latency Count
#define	IEE_PC_MW_TLAT_L_MW_TLAT_MASK (0xFFFFFFFFU)

#define	IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT (0U)

#define	IEE_PC_MW_TLAT_L_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_L_MW_TLAT_MASK)

PC_SR_TNRT_U - Performance Counter, Upper Slave Read Total Non-Responding Time
#define	IEE_PC_SR_TNRT_U_SR_TNRT_MASK (0xFFFFU)

#define	IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT (0U)

#define	IEE_PC_SR_TNRT_U_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_U_SR_TNRT_MASK)

PC_SR_TNRT_L - Performance Counter, Lower Slave Read Total Non-Responding Time
#define	IEE_PC_SR_TNRT_L_SR_TNRT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT (0U)

#define	IEE_PC_SR_TNRT_L_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_L_SR_TNRT_MASK)

PC_SW_TNRT_U - Performance Counter, Upper Slave Write Total Non-Responding Time
#define	IEE_PC_SW_TNRT_U_SW_TNRT_MASK (0xFFFFU)

#define	IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT (0U)

#define	IEE_PC_SW_TNRT_U_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_U_SW_TNRT_MASK)

PC_SW_TNRT_L - Performance Counter, Lower Slave Write Total Non-Responding Time
#define	IEE_PC_SW_TNRT_L_SW_TNRT_MASK (0xFFFFFFFFU)

#define	IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT (0U)

#define	IEE_PC_SW_TNRT_L_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_L_SW_TNRT_MASK)

VIDR1 - IEE Version ID Register 1
#define	IEE_VIDR1_MIN_REV_MASK (0xFFU)

#define	IEE_VIDR1_MIN_REV_SHIFT (0U)

#define	IEE_VIDR1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MIN_REV_SHIFT)) & IEE_VIDR1_MIN_REV_MASK)

#define	IEE_VIDR1_MAJ_REV_MASK (0xFF00U)

#define	IEE_VIDR1_MAJ_REV_SHIFT (8U)

#define	IEE_VIDR1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MAJ_REV_SHIFT)) & IEE_VIDR1_MAJ_REV_MASK)

#define	IEE_VIDR1_IP_ID_MASK (0xFFFF0000U)

#define	IEE_VIDR1_IP_ID_SHIFT (16U)

#define	IEE_VIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_IP_ID_SHIFT)) & IEE_VIDR1_IP_ID_MASK)

AESVID - IEE AES Version ID Register
#define	IEE_AESVID_AESRN_MASK (0xFU)

#define	IEE_AESVID_AESRN_SHIFT (0U)

#define	IEE_AESVID_AESRN(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESRN_SHIFT)) & IEE_AESVID_AESRN_MASK)

#define	IEE_AESVID_AESVID_MASK (0xF0U)

#define	IEE_AESVID_AESVID_SHIFT (4U)

#define	IEE_AESVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESVID_SHIFT)) & IEE_AESVID_AESVID_MASK)

REGATTR - IEE Region 0 Attribute Register...IEE Region 7 Attribute Register.
#define	IEE_REGATTR_KS_MASK (0x1U)

#define	IEE_REGATTR_KS_SHIFT (0U)

#define	IEE_REGATTR_KS(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK)

#define	IEE_REGATTR_MD_MASK (0x70U)

#define	IEE_REGATTR_MD_SHIFT (4U)

#define	IEE_REGATTR_MD(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK)

#define	IEE_REGATTR_BYP_MASK (0x80U)

#define	IEE_REGATTR_BYP_SHIFT (7U)

#define	IEE_REGATTR_BYP(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_BYP_SHIFT)) & IEE_REGATTR_BYP_MASK)

REGPO - IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register
#define	IEE_REGPO_PGOFF_MASK (0xFFFFFFU)

#define	IEE_REGPO_PGOFF_SHIFT (0U)

#define	IEE_REGPO_PGOFF(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGPO_PGOFF_SHIFT)) & IEE_REGPO_PGOFF_MASK)

REGKEY1 - IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register
#define	IEE_REGKEY1_KEY1_MASK (0xFFFFFFFFU)

#define	IEE_REGKEY1_KEY1_SHIFT (0U)

#define	IEE_REGKEY1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY1_KEY1_SHIFT)) & IEE_REGKEY1_KEY1_MASK)

REGKEY2 - IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register
#define	IEE_REGKEY2_KEY2_MASK (0xFFFFFFFFU)

#define	IEE_REGKEY2_KEY2_SHIFT (0U)

#define	IEE_REGKEY2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY2_KEY2_SHIFT)) & IEE_REGKEY2_KEY2_MASK)

AES_TST_DB - IEE AES Test Mode Data Buffer
#define	IEE_AES_TST_DB_AES_TST_DB0_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB0_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB0(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB0_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB0_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB1_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB1_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB1(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB1_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB1_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB2_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB2_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB2(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB2_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB2_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB3_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB3_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB3(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB3_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB3_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB4_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB4_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB4(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB4_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB4_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB5_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB5_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB5(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB5_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB5_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB6_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB6_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB6(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB6_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB6_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB7_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB7_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB7(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB7_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB7_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB8_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB8_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB8(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB8_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB8_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB9_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB9_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB9(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB9_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB9_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB10_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB10_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB10(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB10_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB10_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB11_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB11_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB11(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB11_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB11_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB12_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB12_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB12(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB12_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB12_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB13_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB13_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB13(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB13_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB13_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB14_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB14_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB14(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB14_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB14_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB15_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB15_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB15(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB15_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB15_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB16_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB16_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB16(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB16_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB16_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB17_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB17_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB17(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB17_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB17_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB18_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB18_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB18(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB18_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB18_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB19_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB19_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB19(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB19_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB19_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB20_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB20_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB20(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB20_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB20_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB21_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB21_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB21(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB21_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB21_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB22_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB22_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB22(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB22_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB22_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB23_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB23_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB23(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB23_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB23_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB24_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB24_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB24(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB24_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB24_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB25_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB25_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB25(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB25_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB25_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB26_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB26_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB26(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB26_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB26_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB27_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB27_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB27(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB27_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB27_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB28_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB28_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB28(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB28_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB28_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB29_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB29_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB29(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB29_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB29_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB30_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB30_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB30(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB30_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB30_MASK)

#define	IEE_AES_TST_DB_AES_TST_DB31_MASK (0xFFFFFFFFU)

#define	IEE_AES_TST_DB_AES_TST_DB31_SHIFT (0U)

#define	IEE_AES_TST_DB_AES_TST_DB31(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB31_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB31_MASK)

Detailed Description

Macro Definition Documentation

◆ IEE_GCFG_CLR_MON [1/2]

#define IEE_GCFG_CLR_MON ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK)

CLR_MON 0b0..Do not reset. 0b1..Reset performance counters.

◆ IEE_GCFG_CLR_MON [2/2]

#define IEE_GCFG_CLR_MON ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK)

CLR_MON 0b0..Do not reset. 0b1..Reset performance counters.

◆ IEE_GCFG_KEY_RD_DIS [1/2]

#define IEE_GCFG_KEY_RD_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK)

KEY_RD_DIS 0b0..Key read enabled. Reading the key registers is allowed. 0b1..Key read disabled. Reading the key registers is disabled.

◆ IEE_GCFG_KEY_RD_DIS [2/2]

#define IEE_GCFG_KEY_RD_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK)

KEY_RD_DIS 0b0..Key read enabled. Reading the key registers is allowed. 0b1..Key read disabled. Reading the key registers is disabled.

◆ IEE_GCFG_MON_EN [1/2]

#define IEE_GCFG_MON_EN ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK)

MON_EN 0b0..Performance monitoring disabled. Writing of the performance counter registers is enabled. 0b1..Performance monitoring enabled. Writing of the performance counter registers is disabled.

◆ IEE_GCFG_MON_EN [2/2]

#define IEE_GCFG_MON_EN ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK)

MON_EN 0b0..Performance monitoring disabled. Writing of the performance counter registers is enabled. 0b1..Performance monitoring enabled. Writing of the performance counter registers is disabled.

◆ IEE_GCFG_RL0 [1/2]

#define IEE_GCFG_RL0 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK)

RL0 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL0 [2/2]

#define IEE_GCFG_RL0 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK)

RL0 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL1 [1/2]

#define IEE_GCFG_RL1 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK)

RL1 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL1 [2/2]

#define IEE_GCFG_RL1 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK)

RL1 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL2 [1/2]

#define IEE_GCFG_RL2 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK)

RL2 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL2 [2/2]

#define IEE_GCFG_RL2 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK)

RL2 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL3 [1/2]

#define IEE_GCFG_RL3 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK)

RL3 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL3 [2/2]

#define IEE_GCFG_RL3 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK)

RL3 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL4 [1/2]

#define IEE_GCFG_RL4 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK)

RL4 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL4 [2/2]

#define IEE_GCFG_RL4 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK)

RL4 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL5 [1/2]

#define IEE_GCFG_RL5 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK)

RL5 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL5 [2/2]

#define IEE_GCFG_RL5 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK)

RL5 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL6 [1/2]

#define IEE_GCFG_RL6 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK)

RL6 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL6 [2/2]

#define IEE_GCFG_RL6 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK)

RL6 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL7 [1/2]

#define IEE_GCFG_RL7 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK)

RL7 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RL7 [2/2]

#define IEE_GCFG_RL7 ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK)

RL7 0b0..Unlocked. 0b1..Key, Offset and Attribute registers are locked.

◆ IEE_GCFG_RST [1/2]

#define IEE_GCFG_RST ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RST_SHIFT)) & IEE_GCFG_RST_MASK)

RST 0b0..Do Not Reset. 0b1..Reset IEE.

◆ IEE_GCFG_RST [2/2]

#define IEE_GCFG_RST ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RST_SHIFT)) & IEE_GCFG_RST_MASK)

RST 0b0..Do Not Reset. 0b1..Reset IEE.

◆ IEE_GCFG_TMD [1/2]

#define IEE_GCFG_TMD ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK)

TMD 0b0..Test mode is usable. 0b1..Test mode is disabled.

◆ IEE_GCFG_TMD [2/2]

#define IEE_GCFG_TMD ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK)

TMD 0b0..Test mode is usable. 0b1..Test mode is disabled.

◆ IEE_GCFG_TME [1/2]

#define IEE_GCFG_TME ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK)

TME 0b0..Disabled. 0b1..Enabled.

◆ IEE_GCFG_TME [2/2]

#define IEE_GCFG_TME ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK)

TME 0b0..Disabled. 0b1..Enabled.

◆ IEE_REGATTR_BYP [1/2]

#define IEE_REGATTR_BYP ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_BYP_SHIFT)) & IEE_REGATTR_BYP_MASK)

BYP 0b0..use MD field 0b1..Bypass AES, no encrypt/decrypt

◆ IEE_REGATTR_BYP [2/2]

#define IEE_REGATTR_BYP ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_BYP_SHIFT)) & IEE_REGATTR_BYP_MASK)

BYP 0b0..use MD field 0b1..Bypass AES, no encrypt/decrypt

◆ IEE_REGATTR_KS [1/2]

#define IEE_REGATTR_KS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK)

KS 0b0..128 bits (CTR), 256 bits (XTS). 0b1..256 bits (CTR), 512 bits (XTS).

◆ IEE_REGATTR_KS [2/2]

#define IEE_REGATTR_KS ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK)

KS 0b0..128 bits (CTR), 256 bits (XTS). 0b1..256 bits (CTR), 512 bits (XTS).

◆ IEE_REGATTR_MD [1/2]

#define IEE_REGATTR_MD ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK)

MD 0b000..None (AXI error if accessed) 0b001..XTS 0b010..CTR w/ address binding 0b011..CTR w/o address binding 0b100..CTR keystream only 0b101..Undefined, AXI error if used 0b110..Undefined, AXI error if used 0b111..Undefined, AXI error if used

◆ IEE_REGATTR_MD [2/2]

#define IEE_REGATTR_MD ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK)

MD 0b000..None (AXI error if accessed) 0b001..XTS 0b010..CTR w/ address binding 0b011..CTR w/o address binding 0b100..CTR keystream only 0b101..Undefined, AXI error if used 0b110..Undefined, AXI error if used 0b111..Undefined, AXI error if used

◆ IEE_STA_AFD [1/2]

#define IEE_STA_AFD ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK)

AFD 0b0..No fault detected 0b1..Fault detected

◆ IEE_STA_AFD [2/2]

#define IEE_STA_AFD ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK)

AFD 0b0..No fault detected 0b1..Fault detected

◆ IEE_STA_DSR [1/2]

#define IEE_STA_DSR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK)

DSR 0b0..No seed request present 0b1..Seed request present

◆ IEE_STA_DSR [2/2]

#define IEE_STA_DSR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK)

DSR 0b0..No seed request present 0b1..Seed request present

◆ IEE_TSTMD_TMCONT [1/2]

#define IEE_TSTMD_TMCONT ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK)

TMCONT 0b0..Do not continue. This is the last block of data for AES. 0b1..Continue. Do not initialize AES after this block.

◆ IEE_TSTMD_TMCONT [2/2]

#define IEE_TSTMD_TMCONT ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK)

TMCONT 0b0..Do not continue. This is the last block of data for AES. 0b1..Continue. Do not initialize AES after this block.

◆ IEE_TSTMD_TMDONE [1/2]

#define IEE_TSTMD_TMDONE ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK)

TMDONE 0b0..Not Done. 0b1..Test Done.

◆ IEE_TSTMD_TMDONE [2/2]

#define IEE_TSTMD_TMDONE ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK)

TMDONE 0b0..Not Done. 0b1..Test Done.

◆ IEE_TSTMD_TMENCR [1/2]

#define IEE_TSTMD_TMENCR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK)

TMENCR 0b0..AES Test mode will do decryption. 0b1..AES Test mode will do encryption.

◆ IEE_TSTMD_TMENCR [2/2]

#define IEE_TSTMD_TMENCR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK)

TMENCR 0b0..AES Test mode will do decryption. 0b1..AES Test mode will do encryption.

◆ IEE_TSTMD_TMR [1/2]

#define IEE_TSTMD_TMR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK)

TMR 0b0..Not running. May be written if IEE_GCFG[TME] = 1 0b1..Run AES Test until TMDONE is indicated.

◆ IEE_TSTMD_TMR [2/2]

#define IEE_TSTMD_TMR ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK)

TMR 0b0..Not running. May be written if IEE_GCFG[TME] = 1 0b1..Run AES Test until TMDONE is indicated.

◆ IEE_TSTMD_TMRDY [1/2]

#define IEE_TSTMD_TMRDY ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK)

TMRDY 0b0..Not Ready. 0b1..Ready.

◆ IEE_TSTMD_TMRDY [2/2]

#define IEE_TSTMD_TMRDY ( x ) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK)

TMRDY 0b0..Not Ready. 0b1..Ready.

Macros

GCFG - IEE Global Configuration

STA - IEE Status

TSTMD - IEE Test Mode Register

DPAMS - AES Mask Generation Seed

PC_S_LT - Performance Counter, AES Slave Latency Threshold Value

PC_M_LT - Performance Counter, AES Master Latency Threshold

PC_BLK_ENC - Performance Counter, Number of AES Block Encryptions

PC_BLK_DEC - Performance Counter, Number of AES Block Decryptions

PC_SR_TRANS - Performance Counter, Number of AXI Slave Read Transactions

PC_SW_TRANS - Performance Counter, Number of AXI Slave Write Transactions

PC_MR_TRANS - Performance Counter, Number of AXI Master Read Transactions

PC_MW_TRANS - Performance Counter, Number of AXI Master Write Transactions

PC_M_MBR - Performance Counter, Number of AXI Master Merge Buffer Read Transactions

PC_SR_TBC_U - Performance Counter, Upper Slave Read Transactions Byte Count

PC_SR_TBC_L - Performance Counter, Lower Slave Read Transactions Byte Count

PC_SW_TBC_U - Performance Counter, Upper Slave Write Transactions Byte Count

PC_SW_TBC_L - Performance Counter, Lower Slave Write Transactions Byte Count

PC_MR_TBC_U - Performance Counter, Upper Master Read Transactions Byte Count

PC_MR_TBC_L - Performance Counter, Lower Master Read Transactions Byte Count

PC_MW_TBC_U - Performance Counter, Upper Master Write Transactions Byte Count

PC_MW_TBC_L - Performance Counter, Lower Master Write Transactions Byte Count

PC_SR_TLGTT - Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold

PC_SW_TLGTT - Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold

PC_MR_TLGTT - Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold

PC_MW_TLGTT - Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold

PC_SR_TLAT_U - Performance Counter, Upper Slave Read Latency Count

PC_SR_TLAT_L - Performance Counter, Lower Slave Read Latency Count

PC_SW_TLAT_U - Performance Counter, Upper Slave Write Latency Count

PC_SW_TLAT_L - Performance Counter, Lower Slave Write Latency Count

PC_MR_TLAT_U - Performance Counter, Upper Master Read Latency Count

PC_MR_TLAT_L - Performance Counter, Lower Master Read Latency Count

PC_MW_TLAT_U - Performance Counter, Upper Master Write Latency Count

PC_MW_TLAT_L - Performance Counter, Lower Master Write Latency Count

PC_SR_TNRT_U - Performance Counter, Upper Slave Read Total Non-Responding Time

PC_SR_TNRT_L - Performance Counter, Lower Slave Read Total Non-Responding Time

PC_SW_TNRT_U - Performance Counter, Upper Slave Write Total Non-Responding Time

PC_SW_TNRT_L - Performance Counter, Lower Slave Write Total Non-Responding Time

VIDR1 - IEE Version ID Register 1

AESVID - IEE AES Version ID Register

REGATTR - IEE Region 0 Attribute Register...IEE Region 7 Attribute Register.

REGPO - IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register

REGKEY1 - IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register

REGKEY2 - IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register

AES_TST_DB - IEE AES Test Mode Data Buffer