RTEMS 6.1-rc4
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Macros | |
#define | SEMC_BR_COUNT (9U) |
#define | SEMC_BR_COUNT (9U) |
#define | SEMC_BR_COUNT (9U) |
MCR - Module Control Register | |
#define | SEMC_MCR_SWRST_MASK (0x1U) |
#define | SEMC_MCR_SWRST_SHIFT (0U) |
#define | SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) |
#define | SEMC_MCR_MDIS_MASK (0x2U) |
#define | SEMC_MCR_MDIS_SHIFT (1U) |
#define | SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) |
#define | SEMC_MCR_DQSMD_MASK (0x4U) |
#define | SEMC_MCR_DQSMD_SHIFT (2U) |
#define | SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) |
#define | SEMC_MCR_WPOL0_MASK (0x40U) |
#define | SEMC_MCR_WPOL0_SHIFT (6U) |
#define | SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) |
#define | SEMC_MCR_WPOL1_MASK (0x80U) |
#define | SEMC_MCR_WPOL1_SHIFT (7U) |
#define | SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) |
#define | SEMC_MCR_CTO_MASK (0xFF0000U) |
#define | SEMC_MCR_CTO_SHIFT (16U) |
#define | SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) |
#define | SEMC_MCR_BTO_MASK (0x1F000000U) |
#define | SEMC_MCR_BTO_SHIFT (24U) |
#define | SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) |
IOCR - IO Mux Control Register | |
#define | SEMC_IOCR_MUX_A8_MASK (0x7U) |
#define | SEMC_IOCR_MUX_A8_SHIFT (0U) |
#define | SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) |
#define | SEMC_IOCR_MUX_CSX0_MASK (0x38U) |
#define | SEMC_IOCR_MUX_CSX0_SHIFT (3U) |
#define | SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) |
#define | SEMC_IOCR_MUX_CSX1_MASK (0x1C0U) |
#define | SEMC_IOCR_MUX_CSX1_SHIFT (6U) |
#define | SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) |
#define | SEMC_IOCR_MUX_CSX2_MASK (0xE00U) |
#define | SEMC_IOCR_MUX_CSX2_SHIFT (9U) |
#define | SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) |
#define | SEMC_IOCR_MUX_CSX3_MASK (0x7000U) |
#define | SEMC_IOCR_MUX_CSX3_SHIFT (12U) |
#define | SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) |
#define | SEMC_IOCR_MUX_RDY_MASK (0x38000U) |
#define | SEMC_IOCR_MUX_RDY_SHIFT (15U) |
#define | SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) |
BMCR0 - Bus (AXI) Master Control Register 0 | |
#define | SEMC_BMCR0_WQOS_MASK (0xFU) |
#define | SEMC_BMCR0_WQOS_SHIFT (0U) |
#define | SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) |
#define | SEMC_BMCR0_WAGE_MASK (0xF0U) |
#define | SEMC_BMCR0_WAGE_SHIFT (4U) |
#define | SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) |
#define | SEMC_BMCR0_WSH_MASK (0xFF00U) |
#define | SEMC_BMCR0_WSH_SHIFT (8U) |
#define | SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) |
#define | SEMC_BMCR0_WRWS_MASK (0xFF0000U) |
#define | SEMC_BMCR0_WRWS_SHIFT (16U) |
#define | SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) |
BMCR1 - Bus (AXI) Master Control Register 1 | |
#define | SEMC_BMCR1_WQOS_MASK (0xFU) |
#define | SEMC_BMCR1_WQOS_SHIFT (0U) |
#define | SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) |
#define | SEMC_BMCR1_WAGE_MASK (0xF0U) |
#define | SEMC_BMCR1_WAGE_SHIFT (4U) |
#define | SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) |
#define | SEMC_BMCR1_WPH_MASK (0xFF00U) |
#define | SEMC_BMCR1_WPH_SHIFT (8U) |
#define | SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) |
#define | SEMC_BMCR1_WRWS_MASK (0xFF0000U) |
#define | SEMC_BMCR1_WRWS_SHIFT (16U) |
#define | SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) |
#define | SEMC_BMCR1_WBR_MASK (0xFF000000U) |
#define | SEMC_BMCR1_WBR_SHIFT (24U) |
#define | SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) |
BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) | |
#define | SEMC_BR_VLD_MASK (0x1U) |
#define | SEMC_BR_VLD_SHIFT (0U) |
#define | SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) |
#define | SEMC_BR_MS_MASK (0x3EU) |
#define | SEMC_BR_MS_SHIFT (1U) |
#define | SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) |
#define | SEMC_BR_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR_BA_SHIFT (12U) |
#define | SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) |
INTEN - Interrupt Enable Register | |
#define | SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) |
#define | SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) |
#define | SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
#define | SEMC_INTEN_IPCMDERREN_MASK (0x2U) |
#define | SEMC_INTEN_IPCMDERREN_SHIFT (1U) |
#define | SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
#define | SEMC_INTEN_AXICMDERREN_MASK (0x4U) |
#define | SEMC_INTEN_AXICMDERREN_SHIFT (2U) |
#define | SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
#define | SEMC_INTEN_AXIBUSERREN_MASK (0x8U) |
#define | SEMC_INTEN_AXIBUSERREN_SHIFT (3U) |
#define | SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
#define | SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) |
#define | SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) |
#define | SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
#define | SEMC_INTEN_NDNOPENDEN_MASK (0x20U) |
#define | SEMC_INTEN_NDNOPENDEN_SHIFT (5U) |
#define | SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
INTR - Interrupt Enable Register | |
#define | SEMC_INTR_IPCMDDONE_MASK (0x1U) |
#define | SEMC_INTR_IPCMDDONE_SHIFT (0U) |
#define | SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) |
#define | SEMC_INTR_IPCMDERR_MASK (0x2U) |
#define | SEMC_INTR_IPCMDERR_SHIFT (1U) |
#define | SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) |
#define | SEMC_INTR_AXICMDERR_MASK (0x4U) |
#define | SEMC_INTR_AXICMDERR_SHIFT (2U) |
#define | SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) |
#define | SEMC_INTR_AXIBUSERR_MASK (0x8U) |
#define | SEMC_INTR_AXIBUSERR_SHIFT (3U) |
#define | SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) |
#define | SEMC_INTR_NDPAGEEND_MASK (0x10U) |
#define | SEMC_INTR_NDPAGEEND_SHIFT (4U) |
#define | SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) |
#define | SEMC_INTR_NDNOPEND_MASK (0x20U) |
#define | SEMC_INTR_NDNOPEND_SHIFT (5U) |
#define | SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) |
SDRAMCR0 - SDRAM control register 0 | |
#define | SEMC_SDRAMCR0_PS_MASK (0x1U) |
#define | SEMC_SDRAMCR0_PS_SHIFT (0U) |
#define | SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) |
#define | SEMC_SDRAMCR0_BL_MASK (0x70U) |
#define | SEMC_SDRAMCR0_BL_SHIFT (4U) |
#define | SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) |
#define | SEMC_SDRAMCR0_COL_MASK (0x300U) |
#define | SEMC_SDRAMCR0_COL_SHIFT (8U) |
#define | SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) |
#define | SEMC_SDRAMCR0_CL_MASK (0xC00U) |
#define | SEMC_SDRAMCR0_CL_SHIFT (10U) |
#define | SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) |
SDRAMCR1 - SDRAM control register 1 | |
#define | SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) |
#define | SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) |
#define | SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) |
#define | SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U) |
#define | SEMC_SDRAMCR1_ACT2RW_SHIFT (4U) |
#define | SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) |
#define | SEMC_SDRAMCR1_RFRC_MASK (0x1F00U) |
#define | SEMC_SDRAMCR1_RFRC_SHIFT (8U) |
#define | SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) |
#define | SEMC_SDRAMCR1_WRC_MASK (0xE000U) |
#define | SEMC_SDRAMCR1_WRC_SHIFT (13U) |
#define | SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) |
#define | SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U) |
#define | SEMC_SDRAMCR1_CKEOFF_SHIFT (16U) |
#define | SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) |
#define | SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) |
#define | SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) |
#define | SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) |
SDRAMCR2 - SDRAM control register 2 | |
#define | SEMC_SDRAMCR2_SRRC_MASK (0xFFU) |
#define | SEMC_SDRAMCR2_SRRC_SHIFT (0U) |
#define | SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) |
#define | SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U) |
#define | SEMC_SDRAMCR2_REF2REF_SHIFT (8U) |
#define | SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) |
#define | SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U) |
#define | SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U) |
#define | SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) |
#define | SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) |
#define | SEMC_SDRAMCR2_ITO_SHIFT (24U) |
#define | SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) |
SDRAMCR3 - SDRAM control register 3 | |
#define | SEMC_SDRAMCR3_REN_MASK (0x1U) |
#define | SEMC_SDRAMCR3_REN_SHIFT (0U) |
#define | SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) |
#define | SEMC_SDRAMCR3_REBL_MASK (0xEU) |
#define | SEMC_SDRAMCR3_REBL_SHIFT (1U) |
#define | SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) |
#define | SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) |
#define | SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) |
#define | SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) |
#define | SEMC_SDRAMCR3_RT_MASK (0xFF0000U) |
#define | SEMC_SDRAMCR3_RT_SHIFT (16U) |
#define | SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) |
#define | SEMC_SDRAMCR3_UT_MASK (0xFF000000U) |
#define | SEMC_SDRAMCR3_UT_SHIFT (24U) |
#define | SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) |
NANDCR0 - NAND control register 0 | |
#define | SEMC_NANDCR0_PS_MASK (0x1U) |
#define | SEMC_NANDCR0_PS_SHIFT (0U) |
#define | SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) |
#define | SEMC_NANDCR0_BL_MASK (0x70U) |
#define | SEMC_NANDCR0_BL_SHIFT (4U) |
#define | SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) |
#define | SEMC_NANDCR0_EDO_MASK (0x80U) |
#define | SEMC_NANDCR0_EDO_SHIFT (7U) |
#define | SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) |
#define | SEMC_NANDCR0_COL_MASK (0x700U) |
#define | SEMC_NANDCR0_COL_SHIFT (8U) |
#define | SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) |
NANDCR1 - NAND control register 1 | |
#define | SEMC_NANDCR1_CES_MASK (0xFU) |
#define | SEMC_NANDCR1_CES_SHIFT (0U) |
#define | SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) |
#define | SEMC_NANDCR1_CEH_MASK (0xF0U) |
#define | SEMC_NANDCR1_CEH_SHIFT (4U) |
#define | SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) |
#define | SEMC_NANDCR1_WEL_MASK (0xF00U) |
#define | SEMC_NANDCR1_WEL_SHIFT (8U) |
#define | SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) |
#define | SEMC_NANDCR1_WEH_MASK (0xF000U) |
#define | SEMC_NANDCR1_WEH_SHIFT (12U) |
#define | SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) |
#define | SEMC_NANDCR1_REL_MASK (0xF0000U) |
#define | SEMC_NANDCR1_REL_SHIFT (16U) |
#define | SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) |
#define | SEMC_NANDCR1_REH_MASK (0xF00000U) |
#define | SEMC_NANDCR1_REH_SHIFT (20U) |
#define | SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) |
#define | SEMC_NANDCR1_TA_MASK (0xF000000U) |
#define | SEMC_NANDCR1_TA_SHIFT (24U) |
#define | SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) |
#define | SEMC_NANDCR1_CEITV_MASK (0xF0000000U) |
#define | SEMC_NANDCR1_CEITV_SHIFT (28U) |
#define | SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) |
NANDCR2 - NAND control register 2 | |
#define | SEMC_NANDCR2_TWHR_MASK (0x3FU) |
#define | SEMC_NANDCR2_TWHR_SHIFT (0U) |
#define | SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) |
#define | SEMC_NANDCR2_TRHW_MASK (0xFC0U) |
#define | SEMC_NANDCR2_TRHW_SHIFT (6U) |
#define | SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) |
#define | SEMC_NANDCR2_TADL_MASK (0x3F000U) |
#define | SEMC_NANDCR2_TADL_SHIFT (12U) |
#define | SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) |
#define | SEMC_NANDCR2_TRR_MASK (0xFC0000U) |
#define | SEMC_NANDCR2_TRR_SHIFT (18U) |
#define | SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) |
#define | SEMC_NANDCR2_TWB_MASK (0x3F000000U) |
#define | SEMC_NANDCR2_TWB_SHIFT (24U) |
#define | SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) |
NANDCR3 - NAND control register 3 | |
#define | SEMC_NANDCR3_NDOPT1_MASK (0x1U) |
#define | SEMC_NANDCR3_NDOPT1_SHIFT (0U) |
#define | SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) |
#define | SEMC_NANDCR3_NDOPT2_MASK (0x2U) |
#define | SEMC_NANDCR3_NDOPT2_SHIFT (1U) |
#define | SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) |
#define | SEMC_NANDCR3_NDOPT3_MASK (0x4U) |
#define | SEMC_NANDCR3_NDOPT3_SHIFT (2U) |
#define | SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) |
NORCR0 - NOR control register 0 | |
#define | SEMC_NORCR0_PS_MASK (0x1U) |
#define | SEMC_NORCR0_PS_SHIFT (0U) |
#define | SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) |
#define | SEMC_NORCR0_BL_MASK (0x70U) |
#define | SEMC_NORCR0_BL_SHIFT (4U) |
#define | SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) |
#define | SEMC_NORCR0_AM_MASK (0x300U) |
#define | SEMC_NORCR0_AM_SHIFT (8U) |
#define | SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) |
#define | SEMC_NORCR0_ADVP_MASK (0x400U) |
#define | SEMC_NORCR0_ADVP_SHIFT (10U) |
#define | SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) |
#define | SEMC_NORCR0_COL_MASK (0xF000U) |
#define | SEMC_NORCR0_COL_SHIFT (12U) |
#define | SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) |
NORCR1 - NOR control register 1 | |
#define | SEMC_NORCR1_CES_MASK (0xFU) |
#define | SEMC_NORCR1_CES_SHIFT (0U) |
#define | SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) |
#define | SEMC_NORCR1_CEH_MASK (0xF0U) |
#define | SEMC_NORCR1_CEH_SHIFT (4U) |
#define | SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) |
#define | SEMC_NORCR1_AS_MASK (0xF00U) |
#define | SEMC_NORCR1_AS_SHIFT (8U) |
#define | SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) |
#define | SEMC_NORCR1_AH_MASK (0xF000U) |
#define | SEMC_NORCR1_AH_SHIFT (12U) |
#define | SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) |
#define | SEMC_NORCR1_WEL_MASK (0xF0000U) |
#define | SEMC_NORCR1_WEL_SHIFT (16U) |
#define | SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) |
#define | SEMC_NORCR1_WEH_MASK (0xF00000U) |
#define | SEMC_NORCR1_WEH_SHIFT (20U) |
#define | SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) |
#define | SEMC_NORCR1_REL_MASK (0xF000000U) |
#define | SEMC_NORCR1_REL_SHIFT (24U) |
#define | SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) |
#define | SEMC_NORCR1_REH_MASK (0xF0000000U) |
#define | SEMC_NORCR1_REH_SHIFT (28U) |
#define | SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) |
NORCR2 - NOR control register 2 | |
#define | SEMC_NORCR2_TA_MASK (0xF00U) |
#define | SEMC_NORCR2_TA_SHIFT (8U) |
#define | SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) |
#define | SEMC_NORCR2_AWDH_MASK (0xF000U) |
#define | SEMC_NORCR2_AWDH_SHIFT (12U) |
#define | SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) |
#define | SEMC_NORCR2_CEITV_MASK (0xF000000U) |
#define | SEMC_NORCR2_CEITV_SHIFT (24U) |
#define | SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) |
SRAMCR0 - SRAM control register 0 | |
#define | SEMC_SRAMCR0_PS_MASK (0x1U) |
#define | SEMC_SRAMCR0_PS_SHIFT (0U) |
#define | SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) |
#define | SEMC_SRAMCR0_BL_MASK (0x70U) |
#define | SEMC_SRAMCR0_BL_SHIFT (4U) |
#define | SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) |
#define | SEMC_SRAMCR0_AM_MASK (0x300U) |
#define | SEMC_SRAMCR0_AM_SHIFT (8U) |
#define | SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) |
#define | SEMC_SRAMCR0_ADVP_MASK (0x400U) |
#define | SEMC_SRAMCR0_ADVP_SHIFT (10U) |
#define | SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) |
#define | SEMC_SRAMCR0_COL_MASK (0xF000U) |
#define | SEMC_SRAMCR0_COL_SHIFT (12U) |
#define | SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) |
SRAMCR1 - SRAM control register 1 | |
#define | SEMC_SRAMCR1_CES_MASK (0xFU) |
#define | SEMC_SRAMCR1_CES_SHIFT (0U) |
#define | SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) |
#define | SEMC_SRAMCR1_CEH_MASK (0xF0U) |
#define | SEMC_SRAMCR1_CEH_SHIFT (4U) |
#define | SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) |
#define | SEMC_SRAMCR1_AS_MASK (0xF00U) |
#define | SEMC_SRAMCR1_AS_SHIFT (8U) |
#define | SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) |
#define | SEMC_SRAMCR1_AH_MASK (0xF000U) |
#define | SEMC_SRAMCR1_AH_SHIFT (12U) |
#define | SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) |
#define | SEMC_SRAMCR1_WEL_MASK (0xF0000U) |
#define | SEMC_SRAMCR1_WEL_SHIFT (16U) |
#define | SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) |
#define | SEMC_SRAMCR1_WEH_MASK (0xF00000U) |
#define | SEMC_SRAMCR1_WEH_SHIFT (20U) |
#define | SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) |
#define | SEMC_SRAMCR1_REL_MASK (0xF000000U) |
#define | SEMC_SRAMCR1_REL_SHIFT (24U) |
#define | SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) |
#define | SEMC_SRAMCR1_REH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR1_REH_SHIFT (28U) |
#define | SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) |
SRAMCR2 - SRAM control register 2 | |
#define | SEMC_SRAMCR2_TA_MASK (0xF00U) |
#define | SEMC_SRAMCR2_TA_SHIFT (8U) |
#define | SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) |
#define | SEMC_SRAMCR2_AWDH_MASK (0xF000U) |
#define | SEMC_SRAMCR2_AWDH_SHIFT (12U) |
#define | SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) |
#define | SEMC_SRAMCR2_CEITV_MASK (0xF000000U) |
#define | SEMC_SRAMCR2_CEITV_SHIFT (24U) |
#define | SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) |
DBICR0 - DBI-B control register 0 | |
#define | SEMC_DBICR0_PS_MASK (0x1U) |
#define | SEMC_DBICR0_PS_SHIFT (0U) |
#define | SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) |
#define | SEMC_DBICR0_BL_MASK (0x70U) |
#define | SEMC_DBICR0_BL_SHIFT (4U) |
#define | SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) |
#define | SEMC_DBICR0_COL_MASK (0xF000U) |
#define | SEMC_DBICR0_COL_SHIFT (12U) |
#define | SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) |
DBICR1 - DBI-B control register 1 | |
#define | SEMC_DBICR1_CES_MASK (0xFU) |
#define | SEMC_DBICR1_CES_SHIFT (0U) |
#define | SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) |
#define | SEMC_DBICR1_CEH_MASK (0xF0U) |
#define | SEMC_DBICR1_CEH_SHIFT (4U) |
#define | SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) |
#define | SEMC_DBICR1_WEL_MASK (0xF00U) |
#define | SEMC_DBICR1_WEL_SHIFT (8U) |
#define | SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) |
#define | SEMC_DBICR1_WEH_MASK (0xF000U) |
#define | SEMC_DBICR1_WEH_SHIFT (12U) |
#define | SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) |
#define | SEMC_DBICR1_REL_MASK (0xF0000U) |
#define | SEMC_DBICR1_REL_SHIFT (16U) |
#define | SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) |
#define | SEMC_DBICR1_REH_MASK (0xF00000U) |
#define | SEMC_DBICR1_REH_SHIFT (20U) |
#define | SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) |
#define | SEMC_DBICR1_CEITV_MASK (0xF000000U) |
#define | SEMC_DBICR1_CEITV_SHIFT (24U) |
#define | SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK) |
#define | SEMC_DBICR1_REL2_MASK (0x30000000U) |
#define | SEMC_DBICR1_REL2_SHIFT (28U) |
#define | SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK) |
#define | SEMC_DBICR1_REH2_MASK (0xC0000000U) |
#define | SEMC_DBICR1_REH2_SHIFT (30U) |
#define | SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK) |
IPCR0 - IP Command control register 0 | |
#define | SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) |
#define | SEMC_IPCR0_SA_SHIFT (0U) |
#define | SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) |
IPCR1 - IP Command control register 1 | |
#define | SEMC_IPCR1_DATSZ_MASK (0x7U) |
#define | SEMC_IPCR1_DATSZ_SHIFT (0U) |
#define | SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) |
IPCR2 - IP Command control register 2 | |
#define | SEMC_IPCR2_BM0_MASK (0x1U) |
#define | SEMC_IPCR2_BM0_SHIFT (0U) |
#define | SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) |
#define | SEMC_IPCR2_BM1_MASK (0x2U) |
#define | SEMC_IPCR2_BM1_SHIFT (1U) |
#define | SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) |
#define | SEMC_IPCR2_BM2_MASK (0x4U) |
#define | SEMC_IPCR2_BM2_SHIFT (2U) |
#define | SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) |
#define | SEMC_IPCR2_BM3_MASK (0x8U) |
#define | SEMC_IPCR2_BM3_SHIFT (3U) |
#define | SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) |
IPCMD - IP Command Register | |
#define | SEMC_IPCMD_CMD_MASK (0xFFFFU) |
#define | SEMC_IPCMD_CMD_SHIFT (0U) |
#define | SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) |
#define | SEMC_IPCMD_KEY_MASK (0xFFFF0000U) |
#define | SEMC_IPCMD_KEY_SHIFT (16U) |
#define | SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) |
IPTXDAT - TX DATA register (for IP Command) | |
#define | SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU) |
#define | SEMC_IPTXDAT_DAT_SHIFT (0U) |
#define | SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) |
IPRXDAT - RX DATA register (for IP Command) | |
#define | SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU) |
#define | SEMC_IPRXDAT_DAT_SHIFT (0U) |
#define | SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) |
STS0 - Status Register 0 | |
#define | SEMC_STS0_IDLE_MASK (0x1U) |
#define | SEMC_STS0_IDLE_SHIFT (0U) |
#define | SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
#define | SEMC_STS0_NARDY_MASK (0x2U) |
#define | SEMC_STS0_NARDY_SHIFT (1U) |
#define | SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
STS2 - Status Register 2 | |
#define | SEMC_STS2_NDWRPEND_MASK (0x8U) |
#define | SEMC_STS2_NDWRPEND_SHIFT (3U) |
#define | SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
STS12 - Status register 12 | |
#define | SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) |
#define | SEMC_STS12_NDADDR_SHIFT (0U) |
#define | SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) |
MCR - Module Control Register | |
#define | SEMC_MCR_SWRST_MASK (0x1U) |
#define | SEMC_MCR_SWRST_SHIFT (0U) |
#define | SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) |
#define | SEMC_MCR_MDIS_MASK (0x2U) |
#define | SEMC_MCR_MDIS_SHIFT (1U) |
#define | SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) |
#define | SEMC_MCR_DQSMD_MASK (0x4U) |
#define | SEMC_MCR_DQSMD_SHIFT (2U) |
#define | SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) |
#define | SEMC_MCR_WPOL0_MASK (0x40U) |
#define | SEMC_MCR_WPOL0_SHIFT (6U) |
#define | SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) |
#define | SEMC_MCR_WPOL1_MASK (0x80U) |
#define | SEMC_MCR_WPOL1_SHIFT (7U) |
#define | SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) |
#define | SEMC_MCR_CTO_MASK (0xFF0000U) |
#define | SEMC_MCR_CTO_SHIFT (16U) |
#define | SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) |
#define | SEMC_MCR_BTO_MASK (0x1F000000U) |
#define | SEMC_MCR_BTO_SHIFT (24U) |
#define | SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) |
#define | XRDC2_MCR_GVLDM_MASK (0x1U) |
#define | XRDC2_MCR_GVLDM_SHIFT (0U) |
#define | XRDC2_MCR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK) |
#define | XRDC2_MCR_GVLDC_MASK (0x2U) |
#define | XRDC2_MCR_GVLDC_SHIFT (1U) |
#define | XRDC2_MCR_GVLDC(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK) |
#define | XRDC2_MCR_GCL_MASK (0x30U) |
#define | XRDC2_MCR_GCL_SHIFT (4U) |
#define | XRDC2_MCR_GCL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK) |
IOCR - IO MUX Control Register | |
#define | SEMC_IOCR_MUX_A8_MASK (0xFU) |
#define | SEMC_IOCR_MUX_A8_SHIFT (0U) |
#define | SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) |
#define | SEMC_IOCR_MUX_CSX0_MASK (0xF0U) |
#define | SEMC_IOCR_MUX_CSX0_SHIFT (4U) |
#define | SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) |
#define | SEMC_IOCR_MUX_CSX1_MASK (0xF00U) |
#define | SEMC_IOCR_MUX_CSX1_SHIFT (8U) |
#define | SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) |
#define | SEMC_IOCR_MUX_CSX2_MASK (0xF000U) |
#define | SEMC_IOCR_MUX_CSX2_SHIFT (12U) |
#define | SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) |
#define | SEMC_IOCR_MUX_CSX3_MASK (0xF0000U) |
#define | SEMC_IOCR_MUX_CSX3_SHIFT (16U) |
#define | SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) |
#define | SEMC_IOCR_MUX_RDY_MASK (0xF00000U) |
#define | SEMC_IOCR_MUX_RDY_SHIFT (20U) |
#define | SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) |
#define | SEMC_IOCR_MUX_CLKX0_MASK (0x3000000U) |
#define | SEMC_IOCR_MUX_CLKX0_SHIFT (24U) |
#define | SEMC_IOCR_MUX_CLKX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK) |
#define | SEMC_IOCR_MUX_CLKX1_MASK (0xC000000U) |
#define | SEMC_IOCR_MUX_CLKX1_SHIFT (26U) |
#define | SEMC_IOCR_MUX_CLKX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK) |
#define | SEMC_IOCR_CLKX0_AO_MASK (0x10000000U) |
#define | SEMC_IOCR_CLKX0_AO_SHIFT (28U) |
#define | SEMC_IOCR_CLKX0_AO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX0_AO_SHIFT)) & SEMC_IOCR_CLKX0_AO_MASK) |
#define | SEMC_IOCR_CLKX1_AO_MASK (0x20000000U) |
#define | SEMC_IOCR_CLKX1_AO_SHIFT (29U) |
#define | SEMC_IOCR_CLKX1_AO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX1_AO_SHIFT)) & SEMC_IOCR_CLKX1_AO_MASK) |
BMCR0 - Bus (AXI) Master Control Register 0 | |
#define | SEMC_BMCR0_WQOS_MASK (0xFU) |
#define | SEMC_BMCR0_WQOS_SHIFT (0U) |
#define | SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) |
#define | SEMC_BMCR0_WAGE_MASK (0xF0U) |
#define | SEMC_BMCR0_WAGE_SHIFT (4U) |
#define | SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) |
#define | SEMC_BMCR0_WSH_MASK (0xFF00U) |
#define | SEMC_BMCR0_WSH_SHIFT (8U) |
#define | SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) |
#define | SEMC_BMCR0_WRWS_MASK (0xFF0000U) |
#define | SEMC_BMCR0_WRWS_SHIFT (16U) |
#define | SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) |
BMCR1 - Bus (AXI) Master Control Register 1 | |
#define | SEMC_BMCR1_WQOS_MASK (0xFU) |
#define | SEMC_BMCR1_WQOS_SHIFT (0U) |
#define | SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) |
#define | SEMC_BMCR1_WAGE_MASK (0xF0U) |
#define | SEMC_BMCR1_WAGE_SHIFT (4U) |
#define | SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) |
#define | SEMC_BMCR1_WPH_MASK (0xFF00U) |
#define | SEMC_BMCR1_WPH_SHIFT (8U) |
#define | SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) |
#define | SEMC_BMCR1_WRWS_MASK (0xFF0000U) |
#define | SEMC_BMCR1_WRWS_SHIFT (16U) |
#define | SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) |
#define | SEMC_BMCR1_WBR_MASK (0xFF000000U) |
#define | SEMC_BMCR1_WBR_SHIFT (24U) |
#define | SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) |
BR - Base Register 0..Base Register 8 | |
#define | SEMC_BR_VLD_MASK (0x1U) |
#define | SEMC_BR_VLD_SHIFT (0U) |
#define | SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) |
#define | SEMC_BR_MS_MASK (0x3EU) |
#define | SEMC_BR_MS_SHIFT (1U) |
#define | SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) |
#define | SEMC_BR_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR_BA_SHIFT (12U) |
#define | SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) |
DLLCR - DLL Control Register | |
#define | SEMC_DLLCR_DLLEN_MASK (0x1U) |
#define | SEMC_DLLCR_DLLEN_SHIFT (0U) |
#define | SEMC_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK) |
#define | SEMC_DLLCR_DLLRESET_MASK (0x2U) |
#define | SEMC_DLLCR_DLLRESET_SHIFT (1U) |
#define | SEMC_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK) |
#define | SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U) |
#define | SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U) |
#define | SEMC_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK) |
#define | SEMC_DLLCR_OVRDEN_MASK (0x100U) |
#define | SEMC_DLLCR_OVRDEN_SHIFT (8U) |
#define | SEMC_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK) |
#define | SEMC_DLLCR_OVRDVAL_MASK (0x7E00U) |
#define | SEMC_DLLCR_OVRDVAL_SHIFT (9U) |
#define | SEMC_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK) |
INTEN - Interrupt Enable Register | |
#define | SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) |
#define | SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) |
#define | SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
#define | SEMC_INTEN_IPCMDERREN_MASK (0x2U) |
#define | SEMC_INTEN_IPCMDERREN_SHIFT (1U) |
#define | SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
#define | SEMC_INTEN_AXICMDERREN_MASK (0x4U) |
#define | SEMC_INTEN_AXICMDERREN_SHIFT (2U) |
#define | SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
#define | SEMC_INTEN_AXIBUSERREN_MASK (0x8U) |
#define | SEMC_INTEN_AXIBUSERREN_SHIFT (3U) |
#define | SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
#define | SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) |
#define | SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) |
#define | SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
#define | SEMC_INTEN_NDNOPENDEN_MASK (0x20U) |
#define | SEMC_INTEN_NDNOPENDEN_SHIFT (5U) |
#define | SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
INTR - Interrupt Register | |
#define | SEMC_INTR_IPCMDDONE_MASK (0x1U) |
#define | SEMC_INTR_IPCMDDONE_SHIFT (0U) |
#define | SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) |
#define | SEMC_INTR_IPCMDERR_MASK (0x2U) |
#define | SEMC_INTR_IPCMDERR_SHIFT (1U) |
#define | SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) |
#define | SEMC_INTR_AXICMDERR_MASK (0x4U) |
#define | SEMC_INTR_AXICMDERR_SHIFT (2U) |
#define | SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) |
#define | SEMC_INTR_AXIBUSERR_MASK (0x8U) |
#define | SEMC_INTR_AXIBUSERR_SHIFT (3U) |
#define | SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) |
#define | SEMC_INTR_NDPAGEEND_MASK (0x10U) |
#define | SEMC_INTR_NDPAGEEND_SHIFT (4U) |
#define | SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) |
#define | SEMC_INTR_NDNOPEND_MASK (0x20U) |
#define | SEMC_INTR_NDNOPEND_SHIFT (5U) |
#define | SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) |
SDRAMCR0 - SDRAM Control Register 0 | |
#define | SEMC_SDRAMCR0_PS_MASK (0x3U) |
#define | SEMC_SDRAMCR0_PS_SHIFT (0U) |
#define | SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) |
#define | SEMC_SDRAMCR0_BL_MASK (0x70U) |
#define | SEMC_SDRAMCR0_BL_SHIFT (4U) |
#define | SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) |
#define | SEMC_SDRAMCR0_COL8_MASK (0x80U) |
#define | SEMC_SDRAMCR0_COL8_SHIFT (7U) |
#define | SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK) |
#define | SEMC_SDRAMCR0_COL_MASK (0x300U) |
#define | SEMC_SDRAMCR0_COL_SHIFT (8U) |
#define | SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) |
#define | SEMC_SDRAMCR0_CL_MASK (0xC00U) |
#define | SEMC_SDRAMCR0_CL_SHIFT (10U) |
#define | SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) |
#define | SEMC_SDRAMCR0_BANK2_MASK (0x4000U) |
#define | SEMC_SDRAMCR0_BANK2_SHIFT (14U) |
#define | SEMC_SDRAMCR0_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK) |
SDRAMCR1 - SDRAM Control Register 1 | |
#define | SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) |
#define | SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) |
#define | SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) |
#define | SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U) |
#define | SEMC_SDRAMCR1_ACT2RW_SHIFT (4U) |
#define | SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) |
#define | SEMC_SDRAMCR1_RFRC_MASK (0x1F00U) |
#define | SEMC_SDRAMCR1_RFRC_SHIFT (8U) |
#define | SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) |
#define | SEMC_SDRAMCR1_WRC_MASK (0xE000U) |
#define | SEMC_SDRAMCR1_WRC_SHIFT (13U) |
#define | SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) |
#define | SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U) |
#define | SEMC_SDRAMCR1_CKEOFF_SHIFT (16U) |
#define | SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) |
#define | SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) |
#define | SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) |
#define | SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) |
SDRAMCR2 - SDRAM Control Register 2 | |
#define | SEMC_SDRAMCR2_SRRC_MASK (0xFFU) |
#define | SEMC_SDRAMCR2_SRRC_SHIFT (0U) |
#define | SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) |
#define | SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U) |
#define | SEMC_SDRAMCR2_REF2REF_SHIFT (8U) |
#define | SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) |
#define | SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U) |
#define | SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U) |
#define | SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) |
#define | SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) |
#define | SEMC_SDRAMCR2_ITO_SHIFT (24U) |
#define | SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) |
SDRAMCR3 - SDRAM Control Register 3 | |
#define | SEMC_SDRAMCR3_REN_MASK (0x1U) |
#define | SEMC_SDRAMCR3_REN_SHIFT (0U) |
#define | SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) |
#define | SEMC_SDRAMCR3_REBL_MASK (0xEU) |
#define | SEMC_SDRAMCR3_REBL_SHIFT (1U) |
#define | SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) |
#define | SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) |
#define | SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) |
#define | SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) |
#define | SEMC_SDRAMCR3_RT_MASK (0xFF0000U) |
#define | SEMC_SDRAMCR3_RT_SHIFT (16U) |
#define | SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) |
#define | SEMC_SDRAMCR3_UT_MASK (0xFF000000U) |
#define | SEMC_SDRAMCR3_UT_SHIFT (24U) |
#define | SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) |
NANDCR0 - NAND Control Register 0 | |
#define | SEMC_NANDCR0_PS_MASK (0x1U) |
#define | SEMC_NANDCR0_PS_SHIFT (0U) |
#define | SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) |
#define | SEMC_NANDCR0_SYNCEN_MASK (0x2U) |
#define | SEMC_NANDCR0_SYNCEN_SHIFT (1U) |
#define | SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK) |
#define | SEMC_NANDCR0_BL_MASK (0x70U) |
#define | SEMC_NANDCR0_BL_SHIFT (4U) |
#define | SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) |
#define | SEMC_NANDCR0_EDO_MASK (0x80U) |
#define | SEMC_NANDCR0_EDO_SHIFT (7U) |
#define | SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) |
#define | SEMC_NANDCR0_COL_MASK (0x700U) |
#define | SEMC_NANDCR0_COL_SHIFT (8U) |
#define | SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) |
NANDCR1 - NAND Control Register 1 | |
#define | SEMC_NANDCR1_CES_MASK (0xFU) |
#define | SEMC_NANDCR1_CES_SHIFT (0U) |
#define | SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) |
#define | SEMC_NANDCR1_CEH_MASK (0xF0U) |
#define | SEMC_NANDCR1_CEH_SHIFT (4U) |
#define | SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) |
#define | SEMC_NANDCR1_WEL_MASK (0xF00U) |
#define | SEMC_NANDCR1_WEL_SHIFT (8U) |
#define | SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) |
#define | SEMC_NANDCR1_WEH_MASK (0xF000U) |
#define | SEMC_NANDCR1_WEH_SHIFT (12U) |
#define | SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) |
#define | SEMC_NANDCR1_REL_MASK (0xF0000U) |
#define | SEMC_NANDCR1_REL_SHIFT (16U) |
#define | SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) |
#define | SEMC_NANDCR1_REH_MASK (0xF00000U) |
#define | SEMC_NANDCR1_REH_SHIFT (20U) |
#define | SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) |
#define | SEMC_NANDCR1_TA_MASK (0xF000000U) |
#define | SEMC_NANDCR1_TA_SHIFT (24U) |
#define | SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) |
#define | SEMC_NANDCR1_CEITV_MASK (0xF0000000U) |
#define | SEMC_NANDCR1_CEITV_SHIFT (28U) |
#define | SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) |
NANDCR2 - NAND Control Register 2 | |
#define | SEMC_NANDCR2_TWHR_MASK (0x3FU) |
#define | SEMC_NANDCR2_TWHR_SHIFT (0U) |
#define | SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) |
#define | SEMC_NANDCR2_TRHW_MASK (0xFC0U) |
#define | SEMC_NANDCR2_TRHW_SHIFT (6U) |
#define | SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) |
#define | SEMC_NANDCR2_TADL_MASK (0x3F000U) |
#define | SEMC_NANDCR2_TADL_SHIFT (12U) |
#define | SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) |
#define | SEMC_NANDCR2_TRR_MASK (0xFC0000U) |
#define | SEMC_NANDCR2_TRR_SHIFT (18U) |
#define | SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) |
#define | SEMC_NANDCR2_TWB_MASK (0x3F000000U) |
#define | SEMC_NANDCR2_TWB_SHIFT (24U) |
#define | SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) |
NANDCR3 - NAND Control Register 3 | |
#define | SEMC_NANDCR3_NDOPT1_MASK (0x1U) |
#define | SEMC_NANDCR3_NDOPT1_SHIFT (0U) |
#define | SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) |
#define | SEMC_NANDCR3_NDOPT2_MASK (0x2U) |
#define | SEMC_NANDCR3_NDOPT2_SHIFT (1U) |
#define | SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) |
#define | SEMC_NANDCR3_NDOPT3_MASK (0x4U) |
#define | SEMC_NANDCR3_NDOPT3_SHIFT (2U) |
#define | SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) |
#define | SEMC_NANDCR3_CLE_MASK (0x8U) |
#define | SEMC_NANDCR3_CLE_SHIFT (3U) |
#define | SEMC_NANDCR3_CLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK) |
#define | SEMC_NANDCR3_RDS_MASK (0xF0000U) |
#define | SEMC_NANDCR3_RDS_SHIFT (16U) |
#define | SEMC_NANDCR3_RDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK) |
#define | SEMC_NANDCR3_RDH_MASK (0xF00000U) |
#define | SEMC_NANDCR3_RDH_SHIFT (20U) |
#define | SEMC_NANDCR3_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK) |
#define | SEMC_NANDCR3_WDS_MASK (0xF000000U) |
#define | SEMC_NANDCR3_WDS_SHIFT (24U) |
#define | SEMC_NANDCR3_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK) |
#define | SEMC_NANDCR3_WDH_MASK (0xF0000000U) |
#define | SEMC_NANDCR3_WDH_SHIFT (28U) |
#define | SEMC_NANDCR3_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK) |
NORCR0 - NOR Control Register 0 | |
#define | SEMC_NORCR0_PS_MASK (0x1U) |
#define | SEMC_NORCR0_PS_SHIFT (0U) |
#define | SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) |
#define | SEMC_NORCR0_SYNCEN_MASK (0x2U) |
#define | SEMC_NORCR0_SYNCEN_SHIFT (1U) |
#define | SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK) |
#define | SEMC_NORCR0_BL_MASK (0x70U) |
#define | SEMC_NORCR0_BL_SHIFT (4U) |
#define | SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) |
#define | SEMC_NORCR0_AM_MASK (0x300U) |
#define | SEMC_NORCR0_AM_SHIFT (8U) |
#define | SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) |
#define | SEMC_NORCR0_ADVP_MASK (0x400U) |
#define | SEMC_NORCR0_ADVP_SHIFT (10U) |
#define | SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) |
#define | SEMC_NORCR0_ADVH_MASK (0x800U) |
#define | SEMC_NORCR0_ADVH_SHIFT (11U) |
#define | SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK) |
#define | SEMC_NORCR0_COL_MASK (0xF000U) |
#define | SEMC_NORCR0_COL_SHIFT (12U) |
#define | SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) |
NORCR1 - NOR Control Register 1 | |
#define | SEMC_NORCR1_CES_MASK (0xFU) |
#define | SEMC_NORCR1_CES_SHIFT (0U) |
#define | SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) |
#define | SEMC_NORCR1_CEH_MASK (0xF0U) |
#define | SEMC_NORCR1_CEH_SHIFT (4U) |
#define | SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) |
#define | SEMC_NORCR1_AS_MASK (0xF00U) |
#define | SEMC_NORCR1_AS_SHIFT (8U) |
#define | SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) |
#define | SEMC_NORCR1_AH_MASK (0xF000U) |
#define | SEMC_NORCR1_AH_SHIFT (12U) |
#define | SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) |
#define | SEMC_NORCR1_WEL_MASK (0xF0000U) |
#define | SEMC_NORCR1_WEL_SHIFT (16U) |
#define | SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) |
#define | SEMC_NORCR1_WEH_MASK (0xF00000U) |
#define | SEMC_NORCR1_WEH_SHIFT (20U) |
#define | SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) |
#define | SEMC_NORCR1_REL_MASK (0xF000000U) |
#define | SEMC_NORCR1_REL_SHIFT (24U) |
#define | SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) |
#define | SEMC_NORCR1_REH_MASK (0xF0000000U) |
#define | SEMC_NORCR1_REH_SHIFT (28U) |
#define | SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) |
NORCR2 - NOR Control Register 2 | |
#define | SEMC_NORCR2_TA_MASK (0xF00U) |
#define | SEMC_NORCR2_TA_SHIFT (8U) |
#define | SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) |
#define | SEMC_NORCR2_AWDH_MASK (0xF000U) |
#define | SEMC_NORCR2_AWDH_SHIFT (12U) |
#define | SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) |
#define | SEMC_NORCR2_LC_MASK (0xF0000U) |
#define | SEMC_NORCR2_LC_SHIFT (16U) |
#define | SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK) |
#define | SEMC_NORCR2_RD_MASK (0xF00000U) |
#define | SEMC_NORCR2_RD_SHIFT (20U) |
#define | SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK) |
#define | SEMC_NORCR2_CEITV_MASK (0xF000000U) |
#define | SEMC_NORCR2_CEITV_SHIFT (24U) |
#define | SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) |
#define | SEMC_NORCR2_RDH_MASK (0xF0000000U) |
#define | SEMC_NORCR2_RDH_SHIFT (28U) |
#define | SEMC_NORCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK) |
NORCR3 - NOR Control Register 3 | |
#define | SEMC_NORCR3_ASSR_MASK (0xFU) |
#define | SEMC_NORCR3_ASSR_SHIFT (0U) |
#define | SEMC_NORCR3_ASSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK) |
#define | SEMC_NORCR3_AHSR_MASK (0xF0U) |
#define | SEMC_NORCR3_AHSR_SHIFT (4U) |
#define | SEMC_NORCR3_AHSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK) |
SRAMCR0 - SRAM Control Register 0 | |
#define | SEMC_SRAMCR0_PS_MASK (0x1U) |
#define | SEMC_SRAMCR0_PS_SHIFT (0U) |
#define | SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) |
#define | SEMC_SRAMCR0_SYNCEN_MASK (0x2U) |
#define | SEMC_SRAMCR0_SYNCEN_SHIFT (1U) |
#define | SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK) |
#define | SEMC_SRAMCR0_WAITEN_MASK (0x4U) |
#define | SEMC_SRAMCR0_WAITEN_SHIFT (2U) |
#define | SEMC_SRAMCR0_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITEN_SHIFT)) & SEMC_SRAMCR0_WAITEN_MASK) |
#define | SEMC_SRAMCR0_WAITSP_MASK (0x8U) |
#define | SEMC_SRAMCR0_WAITSP_SHIFT (3U) |
#define | SEMC_SRAMCR0_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITSP_SHIFT)) & SEMC_SRAMCR0_WAITSP_MASK) |
#define | SEMC_SRAMCR0_BL_MASK (0x70U) |
#define | SEMC_SRAMCR0_BL_SHIFT (4U) |
#define | SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) |
#define | SEMC_SRAMCR0_AM_MASK (0x300U) |
#define | SEMC_SRAMCR0_AM_SHIFT (8U) |
#define | SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) |
#define | SEMC_SRAMCR0_ADVP_MASK (0x400U) |
#define | SEMC_SRAMCR0_ADVP_SHIFT (10U) |
#define | SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) |
#define | SEMC_SRAMCR0_ADVH_MASK (0x800U) |
#define | SEMC_SRAMCR0_ADVH_SHIFT (11U) |
#define | SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK) |
#define | SEMC_SRAMCR0_COL_MASK (0xF000U) |
#define | SEMC_SRAMCR0_COL_SHIFT (12U) |
#define | SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) |
SRAMCR1 - SRAM Control Register 1 | |
#define | SEMC_SRAMCR1_CES_MASK (0xFU) |
#define | SEMC_SRAMCR1_CES_SHIFT (0U) |
#define | SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) |
#define | SEMC_SRAMCR1_CEH_MASK (0xF0U) |
#define | SEMC_SRAMCR1_CEH_SHIFT (4U) |
#define | SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) |
#define | SEMC_SRAMCR1_AS_MASK (0xF00U) |
#define | SEMC_SRAMCR1_AS_SHIFT (8U) |
#define | SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) |
#define | SEMC_SRAMCR1_AH_MASK (0xF000U) |
#define | SEMC_SRAMCR1_AH_SHIFT (12U) |
#define | SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) |
#define | SEMC_SRAMCR1_WEL_MASK (0xF0000U) |
#define | SEMC_SRAMCR1_WEL_SHIFT (16U) |
#define | SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) |
#define | SEMC_SRAMCR1_WEH_MASK (0xF00000U) |
#define | SEMC_SRAMCR1_WEH_SHIFT (20U) |
#define | SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) |
#define | SEMC_SRAMCR1_REL_MASK (0xF000000U) |
#define | SEMC_SRAMCR1_REL_SHIFT (24U) |
#define | SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) |
#define | SEMC_SRAMCR1_REH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR1_REH_SHIFT (28U) |
#define | SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) |
SRAMCR2 - SRAM Control Register 2 | |
#define | SEMC_SRAMCR2_WDS_MASK (0xFU) |
#define | SEMC_SRAMCR2_WDS_SHIFT (0U) |
#define | SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) |
#define | SEMC_SRAMCR2_WDH_MASK (0xF0U) |
#define | SEMC_SRAMCR2_WDH_SHIFT (4U) |
#define | SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK) |
#define | SEMC_SRAMCR2_TA_MASK (0xF00U) |
#define | SEMC_SRAMCR2_TA_SHIFT (8U) |
#define | SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) |
#define | SEMC_SRAMCR2_AWDH_MASK (0xF000U) |
#define | SEMC_SRAMCR2_AWDH_SHIFT (12U) |
#define | SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) |
#define | SEMC_SRAMCR2_LC_MASK (0xF0000U) |
#define | SEMC_SRAMCR2_LC_SHIFT (16U) |
#define | SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK) |
#define | SEMC_SRAMCR2_RD_MASK (0xF00000U) |
#define | SEMC_SRAMCR2_RD_SHIFT (20U) |
#define | SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK) |
#define | SEMC_SRAMCR2_CEITV_MASK (0xF000000U) |
#define | SEMC_SRAMCR2_CEITV_SHIFT (24U) |
#define | SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) |
#define | SEMC_SRAMCR2_RDH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR2_RDH_SHIFT (28U) |
#define | SEMC_SRAMCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK) |
DBICR0 - DBI-B Control Register 0 | |
#define | SEMC_DBICR0_PS_MASK (0x1U) |
#define | SEMC_DBICR0_PS_SHIFT (0U) |
#define | SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) |
#define | SEMC_DBICR0_BL_MASK (0x70U) |
#define | SEMC_DBICR0_BL_SHIFT (4U) |
#define | SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) |
#define | SEMC_DBICR0_COL_MASK (0xF000U) |
#define | SEMC_DBICR0_COL_SHIFT (12U) |
#define | SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) |
DBICR1 - DBI-B Control Register 1 | |
#define | SEMC_DBICR1_CES_MASK (0xFU) |
#define | SEMC_DBICR1_CES_SHIFT (0U) |
#define | SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) |
#define | SEMC_DBICR1_CEH_MASK (0xF0U) |
#define | SEMC_DBICR1_CEH_SHIFT (4U) |
#define | SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) |
#define | SEMC_DBICR1_WEL_MASK (0xF00U) |
#define | SEMC_DBICR1_WEL_SHIFT (8U) |
#define | SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) |
#define | SEMC_DBICR1_WEH_MASK (0xF000U) |
#define | SEMC_DBICR1_WEH_SHIFT (12U) |
#define | SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) |
#define | SEMC_DBICR1_REL_MASK (0x7F0000U) |
#define | SEMC_DBICR1_REL_SHIFT (16U) |
#define | SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) |
#define | SEMC_DBICR1_REH_MASK (0x7F000000U) |
#define | SEMC_DBICR1_REH_SHIFT (24U) |
#define | SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) |
DBICR2 - DBI-B Control Register 2 | |
#define | SEMC_DBICR2_CEITV_MASK (0xFU) |
#define | SEMC_DBICR2_CEITV_SHIFT (0U) |
#define | SEMC_DBICR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR2_CEITV_SHIFT)) & SEMC_DBICR2_CEITV_MASK) |
IPCR0 - IP Command Control Register 0 | |
#define | SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) |
#define | SEMC_IPCR0_SA_SHIFT (0U) |
#define | SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) |
IPCR1 - IP Command Control Register 1 | |
#define | SEMC_IPCR1_DATSZ_MASK (0x7U) |
#define | SEMC_IPCR1_DATSZ_SHIFT (0U) |
#define | SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) |
#define | SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U) |
#define | SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U) |
#define | SEMC_IPCR1_NAND_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK) |
IPCR2 - IP Command Control Register 2 | |
#define | SEMC_IPCR2_BM0_MASK (0x1U) |
#define | SEMC_IPCR2_BM0_SHIFT (0U) |
#define | SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) |
#define | SEMC_IPCR2_BM1_MASK (0x2U) |
#define | SEMC_IPCR2_BM1_SHIFT (1U) |
#define | SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) |
#define | SEMC_IPCR2_BM2_MASK (0x4U) |
#define | SEMC_IPCR2_BM2_SHIFT (2U) |
#define | SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) |
#define | SEMC_IPCR2_BM3_MASK (0x8U) |
#define | SEMC_IPCR2_BM3_SHIFT (3U) |
#define | SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) |
STS0 - Status Register 0 | |
#define | SEMC_STS0_IDLE_MASK (0x1U) |
#define | SEMC_STS0_IDLE_SHIFT (0U) |
#define | SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
#define | SEMC_STS0_NARDY_MASK (0x2U) |
#define | SEMC_STS0_NARDY_SHIFT (1U) |
#define | SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
STS2 - Status Register 2 | |
#define | SEMC_STS2_NDWRPEND_MASK (0x8U) |
#define | SEMC_STS2_NDWRPEND_SHIFT (3U) |
#define | SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
STS12 - Status Register 12 | |
#define | SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) |
#define | SEMC_STS12_NDADDR_SHIFT (0U) |
#define | SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) |
STS13 - Status Register 13 | |
#define | SEMC_STS13_SLVLOCK_MASK (0x1U) |
#define | SEMC_STS13_SLVLOCK_SHIFT (0U) |
#define | SEMC_STS13_SLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK) |
#define | SEMC_STS13_REFLOCK_MASK (0x2U) |
#define | SEMC_STS13_REFLOCK_SHIFT (1U) |
#define | SEMC_STS13_REFLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK) |
#define | SEMC_STS13_SLVSEL_MASK (0xFCU) |
#define | SEMC_STS13_SLVSEL_SHIFT (2U) |
#define | SEMC_STS13_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK) |
#define | SEMC_STS13_REFSEL_MASK (0x3F00U) |
#define | SEMC_STS13_REFSEL_SHIFT (8U) |
#define | SEMC_STS13_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK) |
BR9 - Base Register 9 | |
#define | SEMC_BR9_VLD_MASK (0x1U) |
#define | SEMC_BR9_VLD_SHIFT (0U) |
#define | SEMC_BR9_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_VLD_SHIFT)) & SEMC_BR9_VLD_MASK) |
#define | SEMC_BR9_MS_MASK (0x3EU) |
#define | SEMC_BR9_MS_SHIFT (1U) |
#define | SEMC_BR9_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_MS_SHIFT)) & SEMC_BR9_MS_MASK) |
#define | SEMC_BR9_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR9_BA_SHIFT (12U) |
#define | SEMC_BR9_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_BA_SHIFT)) & SEMC_BR9_BA_MASK) |
BR10 - Base Register 10 | |
#define | SEMC_BR10_VLD_MASK (0x1U) |
#define | SEMC_BR10_VLD_SHIFT (0U) |
#define | SEMC_BR10_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_VLD_SHIFT)) & SEMC_BR10_VLD_MASK) |
#define | SEMC_BR10_MS_MASK (0x3EU) |
#define | SEMC_BR10_MS_SHIFT (1U) |
#define | SEMC_BR10_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_MS_SHIFT)) & SEMC_BR10_MS_MASK) |
#define | SEMC_BR10_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR10_BA_SHIFT (12U) |
#define | SEMC_BR10_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_BA_SHIFT)) & SEMC_BR10_BA_MASK) |
BR11 - Base Register 11 | |
#define | SEMC_BR11_VLD_MASK (0x1U) |
#define | SEMC_BR11_VLD_SHIFT (0U) |
#define | SEMC_BR11_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_VLD_SHIFT)) & SEMC_BR11_VLD_MASK) |
#define | SEMC_BR11_MS_MASK (0x3EU) |
#define | SEMC_BR11_MS_SHIFT (1U) |
#define | SEMC_BR11_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_MS_SHIFT)) & SEMC_BR11_MS_MASK) |
#define | SEMC_BR11_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR11_BA_SHIFT (12U) |
#define | SEMC_BR11_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_BA_SHIFT)) & SEMC_BR11_BA_MASK) |
SRAMCR4 - SRAM Control Register 4 | |
#define | SEMC_SRAMCR4_PS_MASK (0x1U) |
#define | SEMC_SRAMCR4_PS_SHIFT (0U) |
#define | SEMC_SRAMCR4_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_PS_SHIFT)) & SEMC_SRAMCR4_PS_MASK) |
#define | SEMC_SRAMCR4_SYNCEN_MASK (0x2U) |
#define | SEMC_SRAMCR4_SYNCEN_SHIFT (1U) |
#define | SEMC_SRAMCR4_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK) |
#define | SEMC_SRAMCR4_WAITEN_MASK (0x4U) |
#define | SEMC_SRAMCR4_WAITEN_SHIFT (2U) |
#define | SEMC_SRAMCR4_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITEN_SHIFT)) & SEMC_SRAMCR4_WAITEN_MASK) |
#define | SEMC_SRAMCR4_WAITSP_MASK (0x8U) |
#define | SEMC_SRAMCR4_WAITSP_SHIFT (3U) |
#define | SEMC_SRAMCR4_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITSP_SHIFT)) & SEMC_SRAMCR4_WAITSP_MASK) |
#define | SEMC_SRAMCR4_BL_MASK (0x70U) |
#define | SEMC_SRAMCR4_BL_SHIFT (4U) |
#define | SEMC_SRAMCR4_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK) |
#define | SEMC_SRAMCR4_AM_MASK (0x300U) |
#define | SEMC_SRAMCR4_AM_SHIFT (8U) |
#define | SEMC_SRAMCR4_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_AM_SHIFT)) & SEMC_SRAMCR4_AM_MASK) |
#define | SEMC_SRAMCR4_ADVP_MASK (0x400U) |
#define | SEMC_SRAMCR4_ADVP_SHIFT (10U) |
#define | SEMC_SRAMCR4_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVP_SHIFT)) & SEMC_SRAMCR4_ADVP_MASK) |
#define | SEMC_SRAMCR4_ADVH_MASK (0x800U) |
#define | SEMC_SRAMCR4_ADVH_SHIFT (11U) |
#define | SEMC_SRAMCR4_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVH_SHIFT)) & SEMC_SRAMCR4_ADVH_MASK) |
#define | SEMC_SRAMCR4_COL_MASK (0xF000U) |
#define | SEMC_SRAMCR4_COL_SHIFT (12U) |
#define | SEMC_SRAMCR4_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_COL_SHIFT)) & SEMC_SRAMCR4_COL_MASK) |
SRAMCR5 - SRAM Control Register 5 | |
#define | SEMC_SRAMCR5_CES_MASK (0xFU) |
#define | SEMC_SRAMCR5_CES_SHIFT (0U) |
#define | SEMC_SRAMCR5_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CES_SHIFT)) & SEMC_SRAMCR5_CES_MASK) |
#define | SEMC_SRAMCR5_CEH_MASK (0xF0U) |
#define | SEMC_SRAMCR5_CEH_SHIFT (4U) |
#define | SEMC_SRAMCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_SRAMCR5_CEH_MASK) |
#define | SEMC_SRAMCR5_AS_MASK (0xF00U) |
#define | SEMC_SRAMCR5_AS_SHIFT (8U) |
#define | SEMC_SRAMCR5_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AS_SHIFT)) & SEMC_SRAMCR5_AS_MASK) |
#define | SEMC_SRAMCR5_AH_MASK (0xF000U) |
#define | SEMC_SRAMCR5_AH_SHIFT (12U) |
#define | SEMC_SRAMCR5_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AH_SHIFT)) & SEMC_SRAMCR5_AH_MASK) |
#define | SEMC_SRAMCR5_WEL_MASK (0xF0000U) |
#define | SEMC_SRAMCR5_WEL_SHIFT (16U) |
#define | SEMC_SRAMCR5_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEL_SHIFT)) & SEMC_SRAMCR5_WEL_MASK) |
#define | SEMC_SRAMCR5_WEH_MASK (0xF00000U) |
#define | SEMC_SRAMCR5_WEH_SHIFT (20U) |
#define | SEMC_SRAMCR5_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEH_SHIFT)) & SEMC_SRAMCR5_WEH_MASK) |
#define | SEMC_SRAMCR5_REL_MASK (0xF000000U) |
#define | SEMC_SRAMCR5_REL_SHIFT (24U) |
#define | SEMC_SRAMCR5_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REL_SHIFT)) & SEMC_SRAMCR5_REL_MASK) |
#define | SEMC_SRAMCR5_REH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR5_REH_SHIFT (28U) |
#define | SEMC_SRAMCR5_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REH_SHIFT)) & SEMC_SRAMCR5_REH_MASK) |
SRAMCR6 - SRAM Control Register 6 | |
#define | SEMC_SRAMCR6_WDS_MASK (0xFU) |
#define | SEMC_SRAMCR6_WDS_SHIFT (0U) |
#define | SEMC_SRAMCR6_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDS_SHIFT)) & SEMC_SRAMCR6_WDS_MASK) |
#define | SEMC_SRAMCR6_WDH_MASK (0xF0U) |
#define | SEMC_SRAMCR6_WDH_SHIFT (4U) |
#define | SEMC_SRAMCR6_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDH_SHIFT)) & SEMC_SRAMCR6_WDH_MASK) |
#define | SEMC_SRAMCR6_TA_MASK (0xF00U) |
#define | SEMC_SRAMCR6_TA_SHIFT (8U) |
#define | SEMC_SRAMCR6_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_TA_SHIFT)) & SEMC_SRAMCR6_TA_MASK) |
#define | SEMC_SRAMCR6_AWDH_MASK (0xF000U) |
#define | SEMC_SRAMCR6_AWDH_SHIFT (12U) |
#define | SEMC_SRAMCR6_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_AWDH_SHIFT)) & SEMC_SRAMCR6_AWDH_MASK) |
#define | SEMC_SRAMCR6_LC_MASK (0xF0000U) |
#define | SEMC_SRAMCR6_LC_SHIFT (16U) |
#define | SEMC_SRAMCR6_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_LC_SHIFT)) & SEMC_SRAMCR6_LC_MASK) |
#define | SEMC_SRAMCR6_RD_MASK (0xF00000U) |
#define | SEMC_SRAMCR6_RD_SHIFT (20U) |
#define | SEMC_SRAMCR6_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RD_SHIFT)) & SEMC_SRAMCR6_RD_MASK) |
#define | SEMC_SRAMCR6_CEITV_MASK (0xF000000U) |
#define | SEMC_SRAMCR6_CEITV_SHIFT (24U) |
#define | SEMC_SRAMCR6_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_CEITV_SHIFT)) & SEMC_SRAMCR6_CEITV_MASK) |
#define | SEMC_SRAMCR6_RDH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR6_RDH_SHIFT (28U) |
#define | SEMC_SRAMCR6_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RDH_SHIFT)) & SEMC_SRAMCR6_RDH_MASK) |
DCCR - Delay Chain Control Register | |
#define | SEMC_DCCR_SDRAMEN_MASK (0x1U) |
#define | SEMC_DCCR_SDRAMEN_SHIFT (0U) |
#define | SEMC_DCCR_SDRAMEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMEN_SHIFT)) & SEMC_DCCR_SDRAMEN_MASK) |
#define | SEMC_DCCR_SDRAMVAL_MASK (0x3EU) |
#define | SEMC_DCCR_SDRAMVAL_SHIFT (1U) |
#define | SEMC_DCCR_SDRAMVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMVAL_SHIFT)) & SEMC_DCCR_SDRAMVAL_MASK) |
#define | SEMC_DCCR_NOREN_MASK (0x100U) |
#define | SEMC_DCCR_NOREN_SHIFT (8U) |
#define | SEMC_DCCR_NOREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NOREN_SHIFT)) & SEMC_DCCR_NOREN_MASK) |
#define | SEMC_DCCR_NORVAL_MASK (0x3E00U) |
#define | SEMC_DCCR_NORVAL_SHIFT (9U) |
#define | SEMC_DCCR_NORVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NORVAL_SHIFT)) & SEMC_DCCR_NORVAL_MASK) |
#define | SEMC_DCCR_SRAM0EN_MASK (0x10000U) |
#define | SEMC_DCCR_SRAM0EN_SHIFT (16U) |
#define | SEMC_DCCR_SRAM0EN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0EN_SHIFT)) & SEMC_DCCR_SRAM0EN_MASK) |
#define | SEMC_DCCR_SRAM0VAL_MASK (0x3E0000U) |
#define | SEMC_DCCR_SRAM0VAL_SHIFT (17U) |
#define | SEMC_DCCR_SRAM0VAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0VAL_SHIFT)) & SEMC_DCCR_SRAM0VAL_MASK) |
#define | SEMC_DCCR_SRAMXEN_MASK (0x1000000U) |
#define | SEMC_DCCR_SRAMXEN_SHIFT (24U) |
#define | SEMC_DCCR_SRAMXEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXEN_SHIFT)) & SEMC_DCCR_SRAMXEN_MASK) |
#define | SEMC_DCCR_SRAMXVAL_MASK (0x3E000000U) |
#define | SEMC_DCCR_SRAMXVAL_SHIFT (25U) |
#define | SEMC_DCCR_SRAMXVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXVAL_SHIFT)) & SEMC_DCCR_SRAMXVAL_MASK) |
MCR - Module Control Register | |
#define | SEMC_MCR_SWRST_MASK (0x1U) |
#define | SEMC_MCR_SWRST_SHIFT (0U) |
#define | SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) |
#define | SEMC_MCR_MDIS_MASK (0x2U) |
#define | SEMC_MCR_MDIS_SHIFT (1U) |
#define | SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) |
#define | SEMC_MCR_DQSMD_MASK (0x4U) |
#define | SEMC_MCR_DQSMD_SHIFT (2U) |
#define | SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) |
#define | SEMC_MCR_WPOL0_MASK (0x40U) |
#define | SEMC_MCR_WPOL0_SHIFT (6U) |
#define | SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) |
#define | SEMC_MCR_WPOL1_MASK (0x80U) |
#define | SEMC_MCR_WPOL1_SHIFT (7U) |
#define | SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) |
#define | SEMC_MCR_CTO_MASK (0xFF0000U) |
#define | SEMC_MCR_CTO_SHIFT (16U) |
#define | SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) |
#define | SEMC_MCR_BTO_MASK (0x1F000000U) |
#define | SEMC_MCR_BTO_SHIFT (24U) |
#define | SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) |
#define | XRDC2_MCR_GVLDM_MASK (0x1U) |
#define | XRDC2_MCR_GVLDM_SHIFT (0U) |
#define | XRDC2_MCR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK) |
#define | XRDC2_MCR_GVLDC_MASK (0x2U) |
#define | XRDC2_MCR_GVLDC_SHIFT (1U) |
#define | XRDC2_MCR_GVLDC(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK) |
#define | XRDC2_MCR_GCL_MASK (0x30U) |
#define | XRDC2_MCR_GCL_SHIFT (4U) |
#define | XRDC2_MCR_GCL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK) |
IOCR - IO MUX Control Register | |
#define | SEMC_IOCR_MUX_A8_MASK (0xFU) |
#define | SEMC_IOCR_MUX_A8_SHIFT (0U) |
#define | SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) |
#define | SEMC_IOCR_MUX_CSX0_MASK (0xF0U) |
#define | SEMC_IOCR_MUX_CSX0_SHIFT (4U) |
#define | SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) |
#define | SEMC_IOCR_MUX_CSX1_MASK (0xF00U) |
#define | SEMC_IOCR_MUX_CSX1_SHIFT (8U) |
#define | SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) |
#define | SEMC_IOCR_MUX_CSX2_MASK (0xF000U) |
#define | SEMC_IOCR_MUX_CSX2_SHIFT (12U) |
#define | SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) |
#define | SEMC_IOCR_MUX_CSX3_MASK (0xF0000U) |
#define | SEMC_IOCR_MUX_CSX3_SHIFT (16U) |
#define | SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) |
#define | SEMC_IOCR_MUX_RDY_MASK (0xF00000U) |
#define | SEMC_IOCR_MUX_RDY_SHIFT (20U) |
#define | SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) |
#define | SEMC_IOCR_MUX_CLKX0_MASK (0x3000000U) |
#define | SEMC_IOCR_MUX_CLKX0_SHIFT (24U) |
#define | SEMC_IOCR_MUX_CLKX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK) |
#define | SEMC_IOCR_MUX_CLKX1_MASK (0xC000000U) |
#define | SEMC_IOCR_MUX_CLKX1_SHIFT (26U) |
#define | SEMC_IOCR_MUX_CLKX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK) |
#define | SEMC_IOCR_CLKX0_AO_MASK (0x10000000U) |
#define | SEMC_IOCR_CLKX0_AO_SHIFT (28U) |
#define | SEMC_IOCR_CLKX0_AO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX0_AO_SHIFT)) & SEMC_IOCR_CLKX0_AO_MASK) |
#define | SEMC_IOCR_CLKX1_AO_MASK (0x20000000U) |
#define | SEMC_IOCR_CLKX1_AO_SHIFT (29U) |
#define | SEMC_IOCR_CLKX1_AO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX1_AO_SHIFT)) & SEMC_IOCR_CLKX1_AO_MASK) |
BMCR0 - Bus (AXI) Master Control Register 0 | |
#define | SEMC_BMCR0_WQOS_MASK (0xFU) |
#define | SEMC_BMCR0_WQOS_SHIFT (0U) |
#define | SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) |
#define | SEMC_BMCR0_WAGE_MASK (0xF0U) |
#define | SEMC_BMCR0_WAGE_SHIFT (4U) |
#define | SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) |
#define | SEMC_BMCR0_WSH_MASK (0xFF00U) |
#define | SEMC_BMCR0_WSH_SHIFT (8U) |
#define | SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) |
#define | SEMC_BMCR0_WRWS_MASK (0xFF0000U) |
#define | SEMC_BMCR0_WRWS_SHIFT (16U) |
#define | SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) |
BMCR1 - Bus (AXI) Master Control Register 1 | |
#define | SEMC_BMCR1_WQOS_MASK (0xFU) |
#define | SEMC_BMCR1_WQOS_SHIFT (0U) |
#define | SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) |
#define | SEMC_BMCR1_WAGE_MASK (0xF0U) |
#define | SEMC_BMCR1_WAGE_SHIFT (4U) |
#define | SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) |
#define | SEMC_BMCR1_WPH_MASK (0xFF00U) |
#define | SEMC_BMCR1_WPH_SHIFT (8U) |
#define | SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) |
#define | SEMC_BMCR1_WRWS_MASK (0xFF0000U) |
#define | SEMC_BMCR1_WRWS_SHIFT (16U) |
#define | SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) |
#define | SEMC_BMCR1_WBR_MASK (0xFF000000U) |
#define | SEMC_BMCR1_WBR_SHIFT (24U) |
#define | SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) |
BR - Base Register 0..Base Register 8 | |
#define | SEMC_BR_VLD_MASK (0x1U) |
#define | SEMC_BR_VLD_SHIFT (0U) |
#define | SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) |
#define | SEMC_BR_MS_MASK (0x3EU) |
#define | SEMC_BR_MS_SHIFT (1U) |
#define | SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) |
#define | SEMC_BR_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR_BA_SHIFT (12U) |
#define | SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) |
DLLCR - DLL Control Register | |
#define | SEMC_DLLCR_DLLEN_MASK (0x1U) |
#define | SEMC_DLLCR_DLLEN_SHIFT (0U) |
#define | SEMC_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK) |
#define | SEMC_DLLCR_DLLRESET_MASK (0x2U) |
#define | SEMC_DLLCR_DLLRESET_SHIFT (1U) |
#define | SEMC_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK) |
#define | SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U) |
#define | SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U) |
#define | SEMC_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK) |
#define | SEMC_DLLCR_OVRDEN_MASK (0x100U) |
#define | SEMC_DLLCR_OVRDEN_SHIFT (8U) |
#define | SEMC_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK) |
#define | SEMC_DLLCR_OVRDVAL_MASK (0x7E00U) |
#define | SEMC_DLLCR_OVRDVAL_SHIFT (9U) |
#define | SEMC_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK) |
INTEN - Interrupt Enable Register | |
#define | SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) |
#define | SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) |
#define | SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
#define | SEMC_INTEN_IPCMDERREN_MASK (0x2U) |
#define | SEMC_INTEN_IPCMDERREN_SHIFT (1U) |
#define | SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
#define | SEMC_INTEN_AXICMDERREN_MASK (0x4U) |
#define | SEMC_INTEN_AXICMDERREN_SHIFT (2U) |
#define | SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
#define | SEMC_INTEN_AXIBUSERREN_MASK (0x8U) |
#define | SEMC_INTEN_AXIBUSERREN_SHIFT (3U) |
#define | SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
#define | SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) |
#define | SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) |
#define | SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
#define | SEMC_INTEN_NDNOPENDEN_MASK (0x20U) |
#define | SEMC_INTEN_NDNOPENDEN_SHIFT (5U) |
#define | SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
INTR - Interrupt Register | |
#define | SEMC_INTR_IPCMDDONE_MASK (0x1U) |
#define | SEMC_INTR_IPCMDDONE_SHIFT (0U) |
#define | SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) |
#define | SEMC_INTR_IPCMDERR_MASK (0x2U) |
#define | SEMC_INTR_IPCMDERR_SHIFT (1U) |
#define | SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) |
#define | SEMC_INTR_AXICMDERR_MASK (0x4U) |
#define | SEMC_INTR_AXICMDERR_SHIFT (2U) |
#define | SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) |
#define | SEMC_INTR_AXIBUSERR_MASK (0x8U) |
#define | SEMC_INTR_AXIBUSERR_SHIFT (3U) |
#define | SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) |
#define | SEMC_INTR_NDPAGEEND_MASK (0x10U) |
#define | SEMC_INTR_NDPAGEEND_SHIFT (4U) |
#define | SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) |
#define | SEMC_INTR_NDNOPEND_MASK (0x20U) |
#define | SEMC_INTR_NDNOPEND_SHIFT (5U) |
#define | SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) |
SDRAMCR0 - SDRAM Control Register 0 | |
#define | SEMC_SDRAMCR0_PS_MASK (0x3U) |
#define | SEMC_SDRAMCR0_PS_SHIFT (0U) |
#define | SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) |
#define | SEMC_SDRAMCR0_BL_MASK (0x70U) |
#define | SEMC_SDRAMCR0_BL_SHIFT (4U) |
#define | SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) |
#define | SEMC_SDRAMCR0_COL8_MASK (0x80U) |
#define | SEMC_SDRAMCR0_COL8_SHIFT (7U) |
#define | SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK) |
#define | SEMC_SDRAMCR0_COL_MASK (0x300U) |
#define | SEMC_SDRAMCR0_COL_SHIFT (8U) |
#define | SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) |
#define | SEMC_SDRAMCR0_CL_MASK (0xC00U) |
#define | SEMC_SDRAMCR0_CL_SHIFT (10U) |
#define | SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) |
#define | SEMC_SDRAMCR0_BANK2_MASK (0x4000U) |
#define | SEMC_SDRAMCR0_BANK2_SHIFT (14U) |
#define | SEMC_SDRAMCR0_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK) |
SDRAMCR1 - SDRAM Control Register 1 | |
#define | SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) |
#define | SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) |
#define | SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) |
#define | SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U) |
#define | SEMC_SDRAMCR1_ACT2RW_SHIFT (4U) |
#define | SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) |
#define | SEMC_SDRAMCR1_RFRC_MASK (0x1F00U) |
#define | SEMC_SDRAMCR1_RFRC_SHIFT (8U) |
#define | SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) |
#define | SEMC_SDRAMCR1_WRC_MASK (0xE000U) |
#define | SEMC_SDRAMCR1_WRC_SHIFT (13U) |
#define | SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) |
#define | SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U) |
#define | SEMC_SDRAMCR1_CKEOFF_SHIFT (16U) |
#define | SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) |
#define | SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) |
#define | SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) |
#define | SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) |
SDRAMCR2 - SDRAM Control Register 2 | |
#define | SEMC_SDRAMCR2_SRRC_MASK (0xFFU) |
#define | SEMC_SDRAMCR2_SRRC_SHIFT (0U) |
#define | SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) |
#define | SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U) |
#define | SEMC_SDRAMCR2_REF2REF_SHIFT (8U) |
#define | SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) |
#define | SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U) |
#define | SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U) |
#define | SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) |
#define | SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) |
#define | SEMC_SDRAMCR2_ITO_SHIFT (24U) |
#define | SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) |
SDRAMCR3 - SDRAM Control Register 3 | |
#define | SEMC_SDRAMCR3_REN_MASK (0x1U) |
#define | SEMC_SDRAMCR3_REN_SHIFT (0U) |
#define | SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) |
#define | SEMC_SDRAMCR3_REBL_MASK (0xEU) |
#define | SEMC_SDRAMCR3_REBL_SHIFT (1U) |
#define | SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) |
#define | SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) |
#define | SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) |
#define | SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) |
#define | SEMC_SDRAMCR3_RT_MASK (0xFF0000U) |
#define | SEMC_SDRAMCR3_RT_SHIFT (16U) |
#define | SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) |
#define | SEMC_SDRAMCR3_UT_MASK (0xFF000000U) |
#define | SEMC_SDRAMCR3_UT_SHIFT (24U) |
#define | SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) |
NANDCR0 - NAND Control Register 0 | |
#define | SEMC_NANDCR0_PS_MASK (0x1U) |
#define | SEMC_NANDCR0_PS_SHIFT (0U) |
#define | SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) |
#define | SEMC_NANDCR0_SYNCEN_MASK (0x2U) |
#define | SEMC_NANDCR0_SYNCEN_SHIFT (1U) |
#define | SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK) |
#define | SEMC_NANDCR0_BL_MASK (0x70U) |
#define | SEMC_NANDCR0_BL_SHIFT (4U) |
#define | SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) |
#define | SEMC_NANDCR0_EDO_MASK (0x80U) |
#define | SEMC_NANDCR0_EDO_SHIFT (7U) |
#define | SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) |
#define | SEMC_NANDCR0_COL_MASK (0x700U) |
#define | SEMC_NANDCR0_COL_SHIFT (8U) |
#define | SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) |
NANDCR1 - NAND Control Register 1 | |
#define | SEMC_NANDCR1_CES_MASK (0xFU) |
#define | SEMC_NANDCR1_CES_SHIFT (0U) |
#define | SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) |
#define | SEMC_NANDCR1_CEH_MASK (0xF0U) |
#define | SEMC_NANDCR1_CEH_SHIFT (4U) |
#define | SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) |
#define | SEMC_NANDCR1_WEL_MASK (0xF00U) |
#define | SEMC_NANDCR1_WEL_SHIFT (8U) |
#define | SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) |
#define | SEMC_NANDCR1_WEH_MASK (0xF000U) |
#define | SEMC_NANDCR1_WEH_SHIFT (12U) |
#define | SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) |
#define | SEMC_NANDCR1_REL_MASK (0xF0000U) |
#define | SEMC_NANDCR1_REL_SHIFT (16U) |
#define | SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) |
#define | SEMC_NANDCR1_REH_MASK (0xF00000U) |
#define | SEMC_NANDCR1_REH_SHIFT (20U) |
#define | SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) |
#define | SEMC_NANDCR1_TA_MASK (0xF000000U) |
#define | SEMC_NANDCR1_TA_SHIFT (24U) |
#define | SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) |
#define | SEMC_NANDCR1_CEITV_MASK (0xF0000000U) |
#define | SEMC_NANDCR1_CEITV_SHIFT (28U) |
#define | SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) |
NANDCR2 - NAND Control Register 2 | |
#define | SEMC_NANDCR2_TWHR_MASK (0x3FU) |
#define | SEMC_NANDCR2_TWHR_SHIFT (0U) |
#define | SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) |
#define | SEMC_NANDCR2_TRHW_MASK (0xFC0U) |
#define | SEMC_NANDCR2_TRHW_SHIFT (6U) |
#define | SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) |
#define | SEMC_NANDCR2_TADL_MASK (0x3F000U) |
#define | SEMC_NANDCR2_TADL_SHIFT (12U) |
#define | SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) |
#define | SEMC_NANDCR2_TRR_MASK (0xFC0000U) |
#define | SEMC_NANDCR2_TRR_SHIFT (18U) |
#define | SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) |
#define | SEMC_NANDCR2_TWB_MASK (0x3F000000U) |
#define | SEMC_NANDCR2_TWB_SHIFT (24U) |
#define | SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) |
NANDCR3 - NAND Control Register 3 | |
#define | SEMC_NANDCR3_NDOPT1_MASK (0x1U) |
#define | SEMC_NANDCR3_NDOPT1_SHIFT (0U) |
#define | SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) |
#define | SEMC_NANDCR3_NDOPT2_MASK (0x2U) |
#define | SEMC_NANDCR3_NDOPT2_SHIFT (1U) |
#define | SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) |
#define | SEMC_NANDCR3_NDOPT3_MASK (0x4U) |
#define | SEMC_NANDCR3_NDOPT3_SHIFT (2U) |
#define | SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) |
#define | SEMC_NANDCR3_CLE_MASK (0x8U) |
#define | SEMC_NANDCR3_CLE_SHIFT (3U) |
#define | SEMC_NANDCR3_CLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK) |
#define | SEMC_NANDCR3_RDS_MASK (0xF0000U) |
#define | SEMC_NANDCR3_RDS_SHIFT (16U) |
#define | SEMC_NANDCR3_RDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK) |
#define | SEMC_NANDCR3_RDH_MASK (0xF00000U) |
#define | SEMC_NANDCR3_RDH_SHIFT (20U) |
#define | SEMC_NANDCR3_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK) |
#define | SEMC_NANDCR3_WDS_MASK (0xF000000U) |
#define | SEMC_NANDCR3_WDS_SHIFT (24U) |
#define | SEMC_NANDCR3_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK) |
#define | SEMC_NANDCR3_WDH_MASK (0xF0000000U) |
#define | SEMC_NANDCR3_WDH_SHIFT (28U) |
#define | SEMC_NANDCR3_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK) |
NORCR0 - NOR Control Register 0 | |
#define | SEMC_NORCR0_PS_MASK (0x1U) |
#define | SEMC_NORCR0_PS_SHIFT (0U) |
#define | SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) |
#define | SEMC_NORCR0_SYNCEN_MASK (0x2U) |
#define | SEMC_NORCR0_SYNCEN_SHIFT (1U) |
#define | SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK) |
#define | SEMC_NORCR0_BL_MASK (0x70U) |
#define | SEMC_NORCR0_BL_SHIFT (4U) |
#define | SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) |
#define | SEMC_NORCR0_AM_MASK (0x300U) |
#define | SEMC_NORCR0_AM_SHIFT (8U) |
#define | SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) |
#define | SEMC_NORCR0_ADVP_MASK (0x400U) |
#define | SEMC_NORCR0_ADVP_SHIFT (10U) |
#define | SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) |
#define | SEMC_NORCR0_ADVH_MASK (0x800U) |
#define | SEMC_NORCR0_ADVH_SHIFT (11U) |
#define | SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK) |
#define | SEMC_NORCR0_COL_MASK (0xF000U) |
#define | SEMC_NORCR0_COL_SHIFT (12U) |
#define | SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) |
NORCR1 - NOR Control Register 1 | |
#define | SEMC_NORCR1_CES_MASK (0xFU) |
#define | SEMC_NORCR1_CES_SHIFT (0U) |
#define | SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) |
#define | SEMC_NORCR1_CEH_MASK (0xF0U) |
#define | SEMC_NORCR1_CEH_SHIFT (4U) |
#define | SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) |
#define | SEMC_NORCR1_AS_MASK (0xF00U) |
#define | SEMC_NORCR1_AS_SHIFT (8U) |
#define | SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) |
#define | SEMC_NORCR1_AH_MASK (0xF000U) |
#define | SEMC_NORCR1_AH_SHIFT (12U) |
#define | SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) |
#define | SEMC_NORCR1_WEL_MASK (0xF0000U) |
#define | SEMC_NORCR1_WEL_SHIFT (16U) |
#define | SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) |
#define | SEMC_NORCR1_WEH_MASK (0xF00000U) |
#define | SEMC_NORCR1_WEH_SHIFT (20U) |
#define | SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) |
#define | SEMC_NORCR1_REL_MASK (0xF000000U) |
#define | SEMC_NORCR1_REL_SHIFT (24U) |
#define | SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) |
#define | SEMC_NORCR1_REH_MASK (0xF0000000U) |
#define | SEMC_NORCR1_REH_SHIFT (28U) |
#define | SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) |
NORCR2 - NOR Control Register 2 | |
#define | SEMC_NORCR2_TA_MASK (0xF00U) |
#define | SEMC_NORCR2_TA_SHIFT (8U) |
#define | SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) |
#define | SEMC_NORCR2_AWDH_MASK (0xF000U) |
#define | SEMC_NORCR2_AWDH_SHIFT (12U) |
#define | SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) |
#define | SEMC_NORCR2_LC_MASK (0xF0000U) |
#define | SEMC_NORCR2_LC_SHIFT (16U) |
#define | SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK) |
#define | SEMC_NORCR2_RD_MASK (0xF00000U) |
#define | SEMC_NORCR2_RD_SHIFT (20U) |
#define | SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK) |
#define | SEMC_NORCR2_CEITV_MASK (0xF000000U) |
#define | SEMC_NORCR2_CEITV_SHIFT (24U) |
#define | SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) |
#define | SEMC_NORCR2_RDH_MASK (0xF0000000U) |
#define | SEMC_NORCR2_RDH_SHIFT (28U) |
#define | SEMC_NORCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK) |
NORCR3 - NOR Control Register 3 | |
#define | SEMC_NORCR3_ASSR_MASK (0xFU) |
#define | SEMC_NORCR3_ASSR_SHIFT (0U) |
#define | SEMC_NORCR3_ASSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK) |
#define | SEMC_NORCR3_AHSR_MASK (0xF0U) |
#define | SEMC_NORCR3_AHSR_SHIFT (4U) |
#define | SEMC_NORCR3_AHSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK) |
SRAMCR0 - SRAM Control Register 0 | |
#define | SEMC_SRAMCR0_PS_MASK (0x1U) |
#define | SEMC_SRAMCR0_PS_SHIFT (0U) |
#define | SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) |
#define | SEMC_SRAMCR0_SYNCEN_MASK (0x2U) |
#define | SEMC_SRAMCR0_SYNCEN_SHIFT (1U) |
#define | SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK) |
#define | SEMC_SRAMCR0_WAITEN_MASK (0x4U) |
#define | SEMC_SRAMCR0_WAITEN_SHIFT (2U) |
#define | SEMC_SRAMCR0_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITEN_SHIFT)) & SEMC_SRAMCR0_WAITEN_MASK) |
#define | SEMC_SRAMCR0_WAITSP_MASK (0x8U) |
#define | SEMC_SRAMCR0_WAITSP_SHIFT (3U) |
#define | SEMC_SRAMCR0_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITSP_SHIFT)) & SEMC_SRAMCR0_WAITSP_MASK) |
#define | SEMC_SRAMCR0_BL_MASK (0x70U) |
#define | SEMC_SRAMCR0_BL_SHIFT (4U) |
#define | SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) |
#define | SEMC_SRAMCR0_AM_MASK (0x300U) |
#define | SEMC_SRAMCR0_AM_SHIFT (8U) |
#define | SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) |
#define | SEMC_SRAMCR0_ADVP_MASK (0x400U) |
#define | SEMC_SRAMCR0_ADVP_SHIFT (10U) |
#define | SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) |
#define | SEMC_SRAMCR0_ADVH_MASK (0x800U) |
#define | SEMC_SRAMCR0_ADVH_SHIFT (11U) |
#define | SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK) |
#define | SEMC_SRAMCR0_COL_MASK (0xF000U) |
#define | SEMC_SRAMCR0_COL_SHIFT (12U) |
#define | SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) |
SRAMCR1 - SRAM Control Register 1 | |
#define | SEMC_SRAMCR1_CES_MASK (0xFU) |
#define | SEMC_SRAMCR1_CES_SHIFT (0U) |
#define | SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) |
#define | SEMC_SRAMCR1_CEH_MASK (0xF0U) |
#define | SEMC_SRAMCR1_CEH_SHIFT (4U) |
#define | SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) |
#define | SEMC_SRAMCR1_AS_MASK (0xF00U) |
#define | SEMC_SRAMCR1_AS_SHIFT (8U) |
#define | SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) |
#define | SEMC_SRAMCR1_AH_MASK (0xF000U) |
#define | SEMC_SRAMCR1_AH_SHIFT (12U) |
#define | SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) |
#define | SEMC_SRAMCR1_WEL_MASK (0xF0000U) |
#define | SEMC_SRAMCR1_WEL_SHIFT (16U) |
#define | SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) |
#define | SEMC_SRAMCR1_WEH_MASK (0xF00000U) |
#define | SEMC_SRAMCR1_WEH_SHIFT (20U) |
#define | SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) |
#define | SEMC_SRAMCR1_REL_MASK (0xF000000U) |
#define | SEMC_SRAMCR1_REL_SHIFT (24U) |
#define | SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) |
#define | SEMC_SRAMCR1_REH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR1_REH_SHIFT (28U) |
#define | SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) |
SRAMCR2 - SRAM Control Register 2 | |
#define | SEMC_SRAMCR2_WDS_MASK (0xFU) |
#define | SEMC_SRAMCR2_WDS_SHIFT (0U) |
#define | SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) |
#define | SEMC_SRAMCR2_WDH_MASK (0xF0U) |
#define | SEMC_SRAMCR2_WDH_SHIFT (4U) |
#define | SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK) |
#define | SEMC_SRAMCR2_TA_MASK (0xF00U) |
#define | SEMC_SRAMCR2_TA_SHIFT (8U) |
#define | SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) |
#define | SEMC_SRAMCR2_AWDH_MASK (0xF000U) |
#define | SEMC_SRAMCR2_AWDH_SHIFT (12U) |
#define | SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) |
#define | SEMC_SRAMCR2_LC_MASK (0xF0000U) |
#define | SEMC_SRAMCR2_LC_SHIFT (16U) |
#define | SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK) |
#define | SEMC_SRAMCR2_RD_MASK (0xF00000U) |
#define | SEMC_SRAMCR2_RD_SHIFT (20U) |
#define | SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK) |
#define | SEMC_SRAMCR2_CEITV_MASK (0xF000000U) |
#define | SEMC_SRAMCR2_CEITV_SHIFT (24U) |
#define | SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) |
#define | SEMC_SRAMCR2_RDH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR2_RDH_SHIFT (28U) |
#define | SEMC_SRAMCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK) |
DBICR0 - DBI-B Control Register 0 | |
#define | SEMC_DBICR0_PS_MASK (0x1U) |
#define | SEMC_DBICR0_PS_SHIFT (0U) |
#define | SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) |
#define | SEMC_DBICR0_BL_MASK (0x70U) |
#define | SEMC_DBICR0_BL_SHIFT (4U) |
#define | SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) |
#define | SEMC_DBICR0_COL_MASK (0xF000U) |
#define | SEMC_DBICR0_COL_SHIFT (12U) |
#define | SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) |
DBICR1 - DBI-B Control Register 1 | |
#define | SEMC_DBICR1_CES_MASK (0xFU) |
#define | SEMC_DBICR1_CES_SHIFT (0U) |
#define | SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) |
#define | SEMC_DBICR1_CEH_MASK (0xF0U) |
#define | SEMC_DBICR1_CEH_SHIFT (4U) |
#define | SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) |
#define | SEMC_DBICR1_WEL_MASK (0xF00U) |
#define | SEMC_DBICR1_WEL_SHIFT (8U) |
#define | SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) |
#define | SEMC_DBICR1_WEH_MASK (0xF000U) |
#define | SEMC_DBICR1_WEH_SHIFT (12U) |
#define | SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) |
#define | SEMC_DBICR1_REL_MASK (0x7F0000U) |
#define | SEMC_DBICR1_REL_SHIFT (16U) |
#define | SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) |
#define | SEMC_DBICR1_REH_MASK (0x7F000000U) |
#define | SEMC_DBICR1_REH_SHIFT (24U) |
#define | SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) |
DBICR2 - DBI-B Control Register 2 | |
#define | SEMC_DBICR2_CEITV_MASK (0xFU) |
#define | SEMC_DBICR2_CEITV_SHIFT (0U) |
#define | SEMC_DBICR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR2_CEITV_SHIFT)) & SEMC_DBICR2_CEITV_MASK) |
IPCR0 - IP Command Control Register 0 | |
#define | SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) |
#define | SEMC_IPCR0_SA_SHIFT (0U) |
#define | SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) |
IPCR1 - IP Command Control Register 1 | |
#define | SEMC_IPCR1_DATSZ_MASK (0x7U) |
#define | SEMC_IPCR1_DATSZ_SHIFT (0U) |
#define | SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) |
#define | SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U) |
#define | SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U) |
#define | SEMC_IPCR1_NAND_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK) |
IPCR2 - IP Command Control Register 2 | |
#define | SEMC_IPCR2_BM0_MASK (0x1U) |
#define | SEMC_IPCR2_BM0_SHIFT (0U) |
#define | SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) |
#define | SEMC_IPCR2_BM1_MASK (0x2U) |
#define | SEMC_IPCR2_BM1_SHIFT (1U) |
#define | SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) |
#define | SEMC_IPCR2_BM2_MASK (0x4U) |
#define | SEMC_IPCR2_BM2_SHIFT (2U) |
#define | SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) |
#define | SEMC_IPCR2_BM3_MASK (0x8U) |
#define | SEMC_IPCR2_BM3_SHIFT (3U) |
#define | SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) |
STS0 - Status Register 0 | |
#define | SEMC_STS0_IDLE_MASK (0x1U) |
#define | SEMC_STS0_IDLE_SHIFT (0U) |
#define | SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
#define | SEMC_STS0_NARDY_MASK (0x2U) |
#define | SEMC_STS0_NARDY_SHIFT (1U) |
#define | SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
STS2 - Status Register 2 | |
#define | SEMC_STS2_NDWRPEND_MASK (0x8U) |
#define | SEMC_STS2_NDWRPEND_SHIFT (3U) |
#define | SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
STS12 - Status Register 12 | |
#define | SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) |
#define | SEMC_STS12_NDADDR_SHIFT (0U) |
#define | SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) |
STS13 - Status Register 13 | |
#define | SEMC_STS13_SLVLOCK_MASK (0x1U) |
#define | SEMC_STS13_SLVLOCK_SHIFT (0U) |
#define | SEMC_STS13_SLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK) |
#define | SEMC_STS13_REFLOCK_MASK (0x2U) |
#define | SEMC_STS13_REFLOCK_SHIFT (1U) |
#define | SEMC_STS13_REFLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK) |
#define | SEMC_STS13_SLVSEL_MASK (0xFCU) |
#define | SEMC_STS13_SLVSEL_SHIFT (2U) |
#define | SEMC_STS13_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK) |
#define | SEMC_STS13_REFSEL_MASK (0x3F00U) |
#define | SEMC_STS13_REFSEL_SHIFT (8U) |
#define | SEMC_STS13_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK) |
BR9 - Base Register 9 | |
#define | SEMC_BR9_VLD_MASK (0x1U) |
#define | SEMC_BR9_VLD_SHIFT (0U) |
#define | SEMC_BR9_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_VLD_SHIFT)) & SEMC_BR9_VLD_MASK) |
#define | SEMC_BR9_MS_MASK (0x3EU) |
#define | SEMC_BR9_MS_SHIFT (1U) |
#define | SEMC_BR9_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_MS_SHIFT)) & SEMC_BR9_MS_MASK) |
#define | SEMC_BR9_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR9_BA_SHIFT (12U) |
#define | SEMC_BR9_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_BA_SHIFT)) & SEMC_BR9_BA_MASK) |
BR10 - Base Register 10 | |
#define | SEMC_BR10_VLD_MASK (0x1U) |
#define | SEMC_BR10_VLD_SHIFT (0U) |
#define | SEMC_BR10_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_VLD_SHIFT)) & SEMC_BR10_VLD_MASK) |
#define | SEMC_BR10_MS_MASK (0x3EU) |
#define | SEMC_BR10_MS_SHIFT (1U) |
#define | SEMC_BR10_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_MS_SHIFT)) & SEMC_BR10_MS_MASK) |
#define | SEMC_BR10_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR10_BA_SHIFT (12U) |
#define | SEMC_BR10_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_BA_SHIFT)) & SEMC_BR10_BA_MASK) |
BR11 - Base Register 11 | |
#define | SEMC_BR11_VLD_MASK (0x1U) |
#define | SEMC_BR11_VLD_SHIFT (0U) |
#define | SEMC_BR11_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_VLD_SHIFT)) & SEMC_BR11_VLD_MASK) |
#define | SEMC_BR11_MS_MASK (0x3EU) |
#define | SEMC_BR11_MS_SHIFT (1U) |
#define | SEMC_BR11_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_MS_SHIFT)) & SEMC_BR11_MS_MASK) |
#define | SEMC_BR11_BA_MASK (0xFFFFF000U) |
#define | SEMC_BR11_BA_SHIFT (12U) |
#define | SEMC_BR11_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_BA_SHIFT)) & SEMC_BR11_BA_MASK) |
SRAMCR4 - SRAM Control Register 4 | |
#define | SEMC_SRAMCR4_PS_MASK (0x1U) |
#define | SEMC_SRAMCR4_PS_SHIFT (0U) |
#define | SEMC_SRAMCR4_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_PS_SHIFT)) & SEMC_SRAMCR4_PS_MASK) |
#define | SEMC_SRAMCR4_SYNCEN_MASK (0x2U) |
#define | SEMC_SRAMCR4_SYNCEN_SHIFT (1U) |
#define | SEMC_SRAMCR4_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK) |
#define | SEMC_SRAMCR4_WAITEN_MASK (0x4U) |
#define | SEMC_SRAMCR4_WAITEN_SHIFT (2U) |
#define | SEMC_SRAMCR4_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITEN_SHIFT)) & SEMC_SRAMCR4_WAITEN_MASK) |
#define | SEMC_SRAMCR4_WAITSP_MASK (0x8U) |
#define | SEMC_SRAMCR4_WAITSP_SHIFT (3U) |
#define | SEMC_SRAMCR4_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITSP_SHIFT)) & SEMC_SRAMCR4_WAITSP_MASK) |
#define | SEMC_SRAMCR4_BL_MASK (0x70U) |
#define | SEMC_SRAMCR4_BL_SHIFT (4U) |
#define | SEMC_SRAMCR4_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK) |
#define | SEMC_SRAMCR4_AM_MASK (0x300U) |
#define | SEMC_SRAMCR4_AM_SHIFT (8U) |
#define | SEMC_SRAMCR4_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_AM_SHIFT)) & SEMC_SRAMCR4_AM_MASK) |
#define | SEMC_SRAMCR4_ADVP_MASK (0x400U) |
#define | SEMC_SRAMCR4_ADVP_SHIFT (10U) |
#define | SEMC_SRAMCR4_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVP_SHIFT)) & SEMC_SRAMCR4_ADVP_MASK) |
#define | SEMC_SRAMCR4_ADVH_MASK (0x800U) |
#define | SEMC_SRAMCR4_ADVH_SHIFT (11U) |
#define | SEMC_SRAMCR4_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVH_SHIFT)) & SEMC_SRAMCR4_ADVH_MASK) |
#define | SEMC_SRAMCR4_COL_MASK (0xF000U) |
#define | SEMC_SRAMCR4_COL_SHIFT (12U) |
#define | SEMC_SRAMCR4_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_COL_SHIFT)) & SEMC_SRAMCR4_COL_MASK) |
SRAMCR5 - SRAM Control Register 5 | |
#define | SEMC_SRAMCR5_CES_MASK (0xFU) |
#define | SEMC_SRAMCR5_CES_SHIFT (0U) |
#define | SEMC_SRAMCR5_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CES_SHIFT)) & SEMC_SRAMCR5_CES_MASK) |
#define | SEMC_SRAMCR5_CEH_MASK (0xF0U) |
#define | SEMC_SRAMCR5_CEH_SHIFT (4U) |
#define | SEMC_SRAMCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_SRAMCR5_CEH_MASK) |
#define | SEMC_SRAMCR5_AS_MASK (0xF00U) |
#define | SEMC_SRAMCR5_AS_SHIFT (8U) |
#define | SEMC_SRAMCR5_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AS_SHIFT)) & SEMC_SRAMCR5_AS_MASK) |
#define | SEMC_SRAMCR5_AH_MASK (0xF000U) |
#define | SEMC_SRAMCR5_AH_SHIFT (12U) |
#define | SEMC_SRAMCR5_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AH_SHIFT)) & SEMC_SRAMCR5_AH_MASK) |
#define | SEMC_SRAMCR5_WEL_MASK (0xF0000U) |
#define | SEMC_SRAMCR5_WEL_SHIFT (16U) |
#define | SEMC_SRAMCR5_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEL_SHIFT)) & SEMC_SRAMCR5_WEL_MASK) |
#define | SEMC_SRAMCR5_WEH_MASK (0xF00000U) |
#define | SEMC_SRAMCR5_WEH_SHIFT (20U) |
#define | SEMC_SRAMCR5_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEH_SHIFT)) & SEMC_SRAMCR5_WEH_MASK) |
#define | SEMC_SRAMCR5_REL_MASK (0xF000000U) |
#define | SEMC_SRAMCR5_REL_SHIFT (24U) |
#define | SEMC_SRAMCR5_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REL_SHIFT)) & SEMC_SRAMCR5_REL_MASK) |
#define | SEMC_SRAMCR5_REH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR5_REH_SHIFT (28U) |
#define | SEMC_SRAMCR5_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REH_SHIFT)) & SEMC_SRAMCR5_REH_MASK) |
SRAMCR6 - SRAM Control Register 6 | |
#define | SEMC_SRAMCR6_WDS_MASK (0xFU) |
#define | SEMC_SRAMCR6_WDS_SHIFT (0U) |
#define | SEMC_SRAMCR6_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDS_SHIFT)) & SEMC_SRAMCR6_WDS_MASK) |
#define | SEMC_SRAMCR6_WDH_MASK (0xF0U) |
#define | SEMC_SRAMCR6_WDH_SHIFT (4U) |
#define | SEMC_SRAMCR6_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDH_SHIFT)) & SEMC_SRAMCR6_WDH_MASK) |
#define | SEMC_SRAMCR6_TA_MASK (0xF00U) |
#define | SEMC_SRAMCR6_TA_SHIFT (8U) |
#define | SEMC_SRAMCR6_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_TA_SHIFT)) & SEMC_SRAMCR6_TA_MASK) |
#define | SEMC_SRAMCR6_AWDH_MASK (0xF000U) |
#define | SEMC_SRAMCR6_AWDH_SHIFT (12U) |
#define | SEMC_SRAMCR6_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_AWDH_SHIFT)) & SEMC_SRAMCR6_AWDH_MASK) |
#define | SEMC_SRAMCR6_LC_MASK (0xF0000U) |
#define | SEMC_SRAMCR6_LC_SHIFT (16U) |
#define | SEMC_SRAMCR6_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_LC_SHIFT)) & SEMC_SRAMCR6_LC_MASK) |
#define | SEMC_SRAMCR6_RD_MASK (0xF00000U) |
#define | SEMC_SRAMCR6_RD_SHIFT (20U) |
#define | SEMC_SRAMCR6_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RD_SHIFT)) & SEMC_SRAMCR6_RD_MASK) |
#define | SEMC_SRAMCR6_CEITV_MASK (0xF000000U) |
#define | SEMC_SRAMCR6_CEITV_SHIFT (24U) |
#define | SEMC_SRAMCR6_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_CEITV_SHIFT)) & SEMC_SRAMCR6_CEITV_MASK) |
#define | SEMC_SRAMCR6_RDH_MASK (0xF0000000U) |
#define | SEMC_SRAMCR6_RDH_SHIFT (28U) |
#define | SEMC_SRAMCR6_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RDH_SHIFT)) & SEMC_SRAMCR6_RDH_MASK) |
DCCR - Delay Chain Control Register | |
#define | SEMC_DCCR_SDRAMEN_MASK (0x1U) |
#define | SEMC_DCCR_SDRAMEN_SHIFT (0U) |
#define | SEMC_DCCR_SDRAMEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMEN_SHIFT)) & SEMC_DCCR_SDRAMEN_MASK) |
#define | SEMC_DCCR_SDRAMVAL_MASK (0x3EU) |
#define | SEMC_DCCR_SDRAMVAL_SHIFT (1U) |
#define | SEMC_DCCR_SDRAMVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMVAL_SHIFT)) & SEMC_DCCR_SDRAMVAL_MASK) |
#define | SEMC_DCCR_NOREN_MASK (0x100U) |
#define | SEMC_DCCR_NOREN_SHIFT (8U) |
#define | SEMC_DCCR_NOREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NOREN_SHIFT)) & SEMC_DCCR_NOREN_MASK) |
#define | SEMC_DCCR_NORVAL_MASK (0x3E00U) |
#define | SEMC_DCCR_NORVAL_SHIFT (9U) |
#define | SEMC_DCCR_NORVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NORVAL_SHIFT)) & SEMC_DCCR_NORVAL_MASK) |
#define | SEMC_DCCR_SRAM0EN_MASK (0x10000U) |
#define | SEMC_DCCR_SRAM0EN_SHIFT (16U) |
#define | SEMC_DCCR_SRAM0EN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0EN_SHIFT)) & SEMC_DCCR_SRAM0EN_MASK) |
#define | SEMC_DCCR_SRAM0VAL_MASK (0x3E0000U) |
#define | SEMC_DCCR_SRAM0VAL_SHIFT (17U) |
#define | SEMC_DCCR_SRAM0VAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0VAL_SHIFT)) & SEMC_DCCR_SRAM0VAL_MASK) |
#define | SEMC_DCCR_SRAMXEN_MASK (0x1000000U) |
#define | SEMC_DCCR_SRAMXEN_SHIFT (24U) |
#define | SEMC_DCCR_SRAMXEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXEN_SHIFT)) & SEMC_DCCR_SRAMXEN_MASK) |
#define | SEMC_DCCR_SRAMXVAL_MASK (0x3E000000U) |
#define | SEMC_DCCR_SRAMXVAL_SHIFT (25U) |
#define | SEMC_DCCR_SRAMXVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXVAL_SHIFT)) & SEMC_DCCR_SRAMXVAL_MASK) |
#define SEMC_BMCR0_WAGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) |
WAGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is multiplied by WAGE to get weight score.
#define SEMC_BMCR0_WAGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) |
WAGE - Weight of AGE
#define SEMC_BMCR0_WAGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) |
WAGE - Weight of AGE
#define SEMC_BMCR0_WQOS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) |
WQOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS is multiplied by WQOS to get weight score.
#define SEMC_BMCR0_WQOS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) |
WQOS - Weight of QOS
#define SEMC_BMCR0_WQOS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) |
WQOS - Weight of QOS
#define SEMC_BMCR0_WRWS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) |
WRWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is same as current executing command with read/write operation switch.
#define SEMC_BMCR0_WRWS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) |
WRWS - Weight of slave hit with Read/Write Switch
#define SEMC_BMCR0_WRWS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) |
WRWS - Weight of slave hit with Read/Write Switch
#define SEMC_BMCR0_WSH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) |
WSH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is same as current executing command without read/write operation switch.
#define SEMC_BMCR0_WSH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) |
WSH - Weight of Slave Hit without read/write switch
#define SEMC_BMCR0_WSH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) |
WSH - Weight of Slave Hit without read/write switch
#define SEMC_BMCR1_WAGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) |
WAGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is multiplied by WAGE to get weight score.
#define SEMC_BMCR1_WAGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) |
WAGE - Weight of AGE
#define SEMC_BMCR1_WAGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) |
WAGE - Weight of AGE
#define SEMC_BMCR1_WBR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) |
WBR - Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current executing command.
#define SEMC_BMCR1_WBR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) |
WBR - Weight of Bank Rotation
#define SEMC_BMCR1_WBR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) |
WBR - Weight of Bank Rotation
#define SEMC_BMCR1_WPH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) |
WPH - Weight of Page Hit. This weight score is valid when queue command's page hits current executing command.
#define SEMC_BMCR1_WPH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) |
WPH - Weight of Page Hit
#define SEMC_BMCR1_WPH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) |
WPH - Weight of Page Hit
#define SEMC_BMCR1_WQOS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) |
WQOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS is multiplied by WQOS to get weight score.
#define SEMC_BMCR1_WQOS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) |
WQOS - Weight of QOS
#define SEMC_BMCR1_WQOS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) |
WQOS - Weight of QOS
#define SEMC_BMCR1_WRWS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) |
WRWS - Weight of slave hit without Read/Write Switch. This weight score is valid when queue command's read/write operation is same as current executing command.
#define SEMC_BMCR1_WRWS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) |
WRWS - Weight of slave hit without Read/Write Switch
#define SEMC_BMCR1_WRWS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) |
WRWS - Weight of slave hit without Read/Write Switch
#define SEMC_BR10_BA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_BA_SHIFT)) & SEMC_BR10_BA_MASK) |
BA - Base Address
#define SEMC_BR10_BA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_BA_SHIFT)) & SEMC_BR10_BA_MASK) |
BA - Base Address
#define SEMC_BR10_MS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_MS_SHIFT)) & SEMC_BR10_MS_MASK) |
MS - Memory size 0b00000..4KB 0b00001..8KB 0b00010..16KB 0b00011..32KB 0b00100..64KB 0b00101..128KB 0b00110..256KB 0b00111..512KB 0b01000..1MB 0b01001..2MB 0b01010..4MB 0b01011..8MB 0b01100..16MB 0b01101..32MB 0b01110..64MB 0b01111..128MB 0b10000..256MB 0b10001..512MB 0b10010..1GB 0b10011..2GB 0b10100-0b11111..4GB
#define SEMC_BR10_MS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_MS_SHIFT)) & SEMC_BR10_MS_MASK) |
MS - Memory size 0b00000..4KB 0b00001..8KB 0b00010..16KB 0b00011..32KB 0b00100..64KB 0b00101..128KB 0b00110..256KB 0b00111..512KB 0b01000..1MB 0b01001..2MB 0b01010..4MB 0b01011..8MB 0b01100..16MB 0b01101..32MB 0b01110..64MB 0b01111..128MB 0b10000..256MB 0b10001..512MB 0b10010..1GB 0b10011..2GB 0b10100-0b11111..4GB
#define SEMC_BR10_VLD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_VLD_SHIFT)) & SEMC_BR10_VLD_MASK) |
VLD - Valid 0b0..The memory is invalid, can not be accessed. 0b1..The memory is valid, can be accessed.
#define SEMC_BR10_VLD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_VLD_SHIFT)) & SEMC_BR10_VLD_MASK) |
VLD - Valid 0b0..The memory is invalid, can not be accessed. 0b1..The memory is valid, can be accessed.
#define SEMC_BR11_BA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_BA_SHIFT)) & SEMC_BR11_BA_MASK) |
BA - Base Address
#define SEMC_BR11_BA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_BA_SHIFT)) & SEMC_BR11_BA_MASK) |
BA - Base Address
#define SEMC_BR11_MS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_MS_SHIFT)) & SEMC_BR11_MS_MASK) |
MS - Memory size 0b00000..4KB 0b00001..8KB 0b00010..16KB 0b00011..32KB 0b00100..64KB 0b00101..128KB 0b00110..256KB 0b00111..512KB 0b01000..1MB 0b01001..2MB 0b01010..4MB 0b01011..8MB 0b01100..16MB 0b01101..32MB 0b01110..64MB 0b01111..128MB 0b10000..256MB 0b10001..512MB 0b10010..1GB 0b10011..2GB 0b10100-0b11111..4GB
#define SEMC_BR11_MS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_MS_SHIFT)) & SEMC_BR11_MS_MASK) |
MS - Memory size 0b00000..4KB 0b00001..8KB 0b00010..16KB 0b00011..32KB 0b00100..64KB 0b00101..128KB 0b00110..256KB 0b00111..512KB 0b01000..1MB 0b01001..2MB 0b01010..4MB 0b01011..8MB 0b01100..16MB 0b01101..32MB 0b01110..64MB 0b01111..128MB 0b10000..256MB 0b10001..512MB 0b10010..1GB 0b10011..2GB 0b10100-0b11111..4GB
#define SEMC_BR11_VLD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_VLD_SHIFT)) & SEMC_BR11_VLD_MASK) |
VLD - Valid 0b0..The memory is invalid, can not be accessed. 0b1..The memory is valid, can be accessed.
#define SEMC_BR11_VLD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_VLD_SHIFT)) & SEMC_BR11_VLD_MASK) |
VLD - Valid 0b0..The memory is invalid, can not be accessed. 0b1..The memory is valid, can be accessed.
#define SEMC_BR9_BA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_BA_SHIFT)) & SEMC_BR9_BA_MASK) |
BA - Base Address
#define SEMC_BR9_BA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_BA_SHIFT)) & SEMC_BR9_BA_MASK) |
BA - Base Address
#define SEMC_BR9_MS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_MS_SHIFT)) & SEMC_BR9_MS_MASK) |
MS - Memory size 0b00000..4KB 0b00001..8KB 0b00010..16KB 0b00011..32KB 0b00100..64KB 0b00101..128KB 0b00110..256KB 0b00111..512KB 0b01000..1MB 0b01001..2MB 0b01010..4MB 0b01011..8MB 0b01100..16MB 0b01101..32MB 0b01110..64MB 0b01111..128MB 0b10000..256MB 0b10001..512MB 0b10010..1GB 0b10011..2GB 0b10100-0b11111..4GB
#define SEMC_BR9_MS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_MS_SHIFT)) & SEMC_BR9_MS_MASK) |
MS - Memory size 0b00000..4KB 0b00001..8KB 0b00010..16KB 0b00011..32KB 0b00100..64KB 0b00101..128KB 0b00110..256KB 0b00111..512KB 0b01000..1MB 0b01001..2MB 0b01010..4MB 0b01011..8MB 0b01100..16MB 0b01101..32MB 0b01110..64MB 0b01111..128MB 0b10000..256MB 0b10001..512MB 0b10010..1GB 0b10011..2GB 0b10100-0b11111..4GB
#define SEMC_BR9_VLD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_VLD_SHIFT)) & SEMC_BR9_VLD_MASK) |
VLD - Valid 0b0..The memory is invalid, can not be accessed. 0b1..The memory is valid, can be accessed.
#define SEMC_BR9_VLD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_VLD_SHIFT)) & SEMC_BR9_VLD_MASK) |
VLD - Valid 0b0..The memory is invalid, can not be accessed. 0b1..The memory is valid, can be accessed.
#define SEMC_BR_BA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) |
BA - Base Address
#define SEMC_BR_BA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) |
BA - Base Address
#define SEMC_BR_BA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) |
BA - Base Address
#define SEMC_BR_MS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) |
MS - Memory size 0b00000..4KB 0b00001..8KB 0b00010..16KB 0b00011..32KB 0b00100..64KB 0b00101..128KB 0b00110..256KB 0b00111..512KB 0b01000..1MB 0b01001..2MB 0b01010..4MB 0b01011..8MB 0b01100..16MB 0b01101..32MB 0b01110..64MB 0b01111..128MB 0b10000..256MB 0b10001..512MB 0b10010..1GB 0b10011..2GB 0b10100-0b11111..4GB
#define SEMC_BR_MS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) |
MS - Memory size 0b00000..4KB 0b00001..8KB 0b00010..16KB 0b00011..32KB 0b00100..64KB 0b00101..128KB 0b00110..256KB 0b00111..512KB 0b01000..1MB 0b01001..2MB 0b01010..4MB 0b01011..8MB 0b01100..16MB 0b01101..32MB 0b01110..64MB 0b01111..128MB 0b10000..256MB 0b10001..512MB 0b10010..1GB 0b10011..2GB 0b10100-0b11111..4GB
#define SEMC_BR_MS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) |
MS - Memory size 0b00000..4KB 0b00001..8KB 0b00010..16KB 0b00011..32KB 0b00100..64KB 0b00101..128KB 0b00110..256KB 0b00111..512KB 0b01000..1MB 0b01001..2MB 0b01010..4MB 0b01011..8MB 0b01100..16MB 0b01101..32MB 0b01110..64MB 0b01111..128MB 0b10000..256MB 0b10001..512MB 0b10010..1GB 0b10011..2GB 0b10100-0b11111..4GB
#define SEMC_BR_VLD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) |
VLD - Valid
#define SEMC_BR_VLD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) |
VLD - Valid 0b0..The memory is invalid, can not be accessed. 0b1..The memory is valid, can be accessed.
#define SEMC_BR_VLD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) |
VLD - Valid 0b0..The memory is invalid, can not be accessed. 0b1..The memory is valid, can be accessed.
#define SEMC_DBICR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_DBICR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_DBICR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_DBICR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) |
COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits
#define SEMC_DBICR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) |
COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits
#define SEMC_DBICR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) |
COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits
#define SEMC_DBICR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_DBICR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_DBICR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_DBICR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) |
CEH - CSX Hold Time
#define SEMC_DBICR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) |
CEH - CSX Hold Time
#define SEMC_DBICR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) |
CEH - CSX Hold Time
#define SEMC_DBICR1_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK) |
CEITV - CSX interval time
#define SEMC_DBICR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) |
CES - CSX Setup Time
#define SEMC_DBICR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) |
CES - CSX Setup Time
#define SEMC_DBICR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) |
CES - CSX Setup Time
#define SEMC_DBICR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) |
REH - RDX High Time bit [3:0]
#define SEMC_DBICR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) |
REH - RDX High Time
#define SEMC_DBICR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) |
REH - RDX High Time
#define SEMC_DBICR1_REH2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK) |
REH2 - RDX High Time bit [5:4]
#define SEMC_DBICR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) |
REL - RDX Low Time bit [3:0]
#define SEMC_DBICR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) |
REL - RDX Low Time
#define SEMC_DBICR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) |
REL - RDX Low Time
#define SEMC_DBICR1_REL2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK) |
REL2 - RDX Low Time bit [5:4]
#define SEMC_DBICR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) |
WEH - WRX High Time
#define SEMC_DBICR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) |
WEH - WRX High Time
#define SEMC_DBICR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) |
WEH - WRX High Time
#define SEMC_DBICR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) |
WEL - WRX Low Time
#define SEMC_DBICR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) |
WEL - WRX Low Time
#define SEMC_DBICR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) |
WEL - WRX Low Time
#define SEMC_DBICR2_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR2_CEITV_SHIFT)) & SEMC_DBICR2_CEITV_MASK) |
CEITV - CSX interval time
#define SEMC_DBICR2_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR2_CEITV_SHIFT)) & SEMC_DBICR2_CEITV_MASK) |
CEITV - CSX interval time
#define SEMC_DCCR_NOREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NOREN_SHIFT)) & SEMC_DCCR_NOREN_MASK) |
NOREN - Delay chain insertion enable for NOR device. 0b0..Delay chain is not inserted. 0b1..Delay chain is inserted.
#define SEMC_DCCR_NOREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NOREN_SHIFT)) & SEMC_DCCR_NOREN_MASK) |
NOREN - Delay chain insertion enable for NOR device. 0b0..Delay chain is not inserted. 0b1..Delay chain is inserted.
#define SEMC_DCCR_NORVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NORVAL_SHIFT)) & SEMC_DCCR_NORVAL_MASK) |
NORVAL - Clock delay line delay cell number selection value for NOR device.
#define SEMC_DCCR_NORVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NORVAL_SHIFT)) & SEMC_DCCR_NORVAL_MASK) |
NORVAL - Clock delay line delay cell number selection value for NOR device.
#define SEMC_DCCR_SDRAMEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMEN_SHIFT)) & SEMC_DCCR_SDRAMEN_MASK) |
SDRAMEN - Delay chain insertion enable for SRAM device. 0b0..Delay chain is not inserted. 0b1..Delay chain is inserted.
#define SEMC_DCCR_SDRAMEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMEN_SHIFT)) & SEMC_DCCR_SDRAMEN_MASK) |
SDRAMEN - Delay chain insertion enable for SRAM device. 0b0..Delay chain is not inserted. 0b1..Delay chain is inserted.
#define SEMC_DCCR_SDRAMVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMVAL_SHIFT)) & SEMC_DCCR_SDRAMVAL_MASK) |
SDRAMVAL - Clock delay line delay cell number selection value for SDRAM device.
#define SEMC_DCCR_SDRAMVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMVAL_SHIFT)) & SEMC_DCCR_SDRAMVAL_MASK) |
SDRAMVAL - Clock delay line delay cell number selection value for SDRAM device.
#define SEMC_DCCR_SRAM0EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0EN_SHIFT)) & SEMC_DCCR_SRAM0EN_MASK) |
SRAM0EN - Delay chain insertion enable for SRAM device 0. 0b0..Delay chain is not inserted. 0b1..Delay chain is inserted.
#define SEMC_DCCR_SRAM0EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0EN_SHIFT)) & SEMC_DCCR_SRAM0EN_MASK) |
SRAM0EN - Delay chain insertion enable for SRAM device 0. 0b0..Delay chain is not inserted. 0b1..Delay chain is inserted.
#define SEMC_DCCR_SRAM0VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0VAL_SHIFT)) & SEMC_DCCR_SRAM0VAL_MASK) |
SRAM0VAL - Clock delay line delay cell number selection value for SRAM device 0.
#define SEMC_DCCR_SRAM0VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0VAL_SHIFT)) & SEMC_DCCR_SRAM0VAL_MASK) |
SRAM0VAL - Clock delay line delay cell number selection value for SRAM device 0.
#define SEMC_DCCR_SRAMXEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXEN_SHIFT)) & SEMC_DCCR_SRAMXEN_MASK) |
SRAMXEN - Delay chain insertion enable for SRAM device 1-3. 0b0..Delay chain is not inserted. 0b1..Delay chain is inserted.
#define SEMC_DCCR_SRAMXEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXEN_SHIFT)) & SEMC_DCCR_SRAMXEN_MASK) |
SRAMXEN - Delay chain insertion enable for SRAM device 1-3. 0b0..Delay chain is not inserted. 0b1..Delay chain is inserted.
#define SEMC_DCCR_SRAMXVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXVAL_SHIFT)) & SEMC_DCCR_SRAMXVAL_MASK) |
SRAMXVAL - Clock delay line delay cell number selection value for SRAM device 1-3.
#define SEMC_DCCR_SRAMXVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXVAL_SHIFT)) & SEMC_DCCR_SRAMXVAL_MASK) |
SRAMXVAL - Clock delay line delay cell number selection value for SRAM device 1-3.
#define SEMC_DLLCR_DLLEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK) |
DLLEN - DLL calibration enable 0b0..DLL calibration is disabled. 0b1..DLL calibration is enabled.
#define SEMC_DLLCR_DLLEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK) |
DLLEN - DLL calibration enable 0b0..DLL calibration is disabled. 0b1..DLL calibration is enabled.
#define SEMC_DLLCR_DLLRESET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK) |
DLLRESET - DLL Reset 0b0..DLL is not reset. 0b1..DLL is reset.
#define SEMC_DLLCR_DLLRESET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK) |
DLLRESET - DLL Reset 0b0..DLL is not reset. 0b1..DLL is reset.
#define SEMC_DLLCR_OVRDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK) |
OVRDEN - Override Enable 0b0..The delay cell number is not overridden. 0b1..The delay cell number is overridden.
#define SEMC_DLLCR_OVRDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK) |
OVRDEN - Override Enable 0b0..The delay cell number is not overridden. 0b1..The delay cell number is overridden.
#define SEMC_DLLCR_OVRDVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK) |
OVRDVAL - Override Value
#define SEMC_DLLCR_OVRDVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK) |
OVRDVAL - Override Value
#define SEMC_DLLCR_SLVDLYTARGET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK) |
SLVDLYTARGET - Delay Target for Slave
#define SEMC_DLLCR_SLVDLYTARGET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK) |
SLVDLYTARGET - Delay Target for Slave
#define SEMC_INTEN_AXIBUSERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
AXIBUSERREN - AXI bus error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_AXIBUSERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
AXIBUSERREN - AXI bus error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_AXIBUSERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
AXIBUSERREN - AXI bus error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_AXICMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
AXICMDERREN - AXI command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_AXICMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
AXICMDERREN - AXI command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_AXICMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
AXICMDERREN - AXI command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDDONEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
IPCMDDONEEN - IP command done interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDDONEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
IPCMDDONEEN - IP command done interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDDONEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
IPCMDDONEEN - IP command done interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
IPCMDERREN - IP command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
IPCMDERREN - IP command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
IPCMDERREN - IP command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDNOPENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
NDNOPENDEN - NAND no pending AXI access interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDNOPENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
NDNOPENDEN - NAND no pending AXI access interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDNOPENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
NDNOPENDEN - NAND no pending AXI access interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDPAGEENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
NDPAGEENDEN - NAND page end interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDPAGEENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
NDPAGEENDEN - NAND page end interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDPAGEENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
NDPAGEENDEN - NAND page end interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTR_AXIBUSERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) |
AXIBUSERR - AXI bus error interrupt
#define SEMC_INTR_AXIBUSERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) |
AXIBUSERR - AXI bus error interrupt 0b0..No AXI bus error. 0b1..AXI bus error occurs.
#define SEMC_INTR_AXIBUSERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) |
AXIBUSERR - AXI bus error interrupt 0b0..No AXI bus error. 0b1..AXI bus error occurs.
#define SEMC_INTR_AXICMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) |
AXICMDERR - AXI command error interrupt
#define SEMC_INTR_AXICMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) |
AXICMDERR - AXI command error interrupt 0b0..No AXI command error. 0b1..AXI command error occurs.
#define SEMC_INTR_AXICMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) |
AXICMDERR - AXI command error interrupt 0b0..No AXI command error. 0b1..AXI command error occurs.
#define SEMC_INTR_IPCMDDONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) |
IPCMDDONE - IP command normal done interrupt
#define SEMC_INTR_IPCMDDONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) |
IPCMDDONE - IP command normal done interrupt 0b0..IP command is not done. 0b1..IP command is done.
#define SEMC_INTR_IPCMDDONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) |
IPCMDDONE - IP command normal done interrupt 0b0..IP command is not done. 0b1..IP command is done.
#define SEMC_INTR_IPCMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) |
IPCMDERR - IP command error done interrupt
#define SEMC_INTR_IPCMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) |
IPCMDERR - IP command error done interrupt 0b0..No IP command error. 0b1..IP command error occurs.
#define SEMC_INTR_IPCMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) |
IPCMDERR - IP command error done interrupt 0b0..No IP command error. 0b1..IP command error occurs.
#define SEMC_INTR_NDNOPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) |
NDNOPEND - NAND no pending AXI access interrupt
#define SEMC_INTR_NDNOPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) |
NDNOPEND - NAND no pending AXI write transaction interrupt 0b0..At least one NAND AXI write transaction is pending or no NAND write transaction is sent to the queue. 0b1..All NAND AXI write pending transactions are finished.
#define SEMC_INTR_NDNOPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) |
NDNOPEND - NAND no pending AXI write transaction interrupt 0b0..At least one NAND AXI write transaction is pending or no NAND write transaction is sent to the queue. 0b1..All NAND AXI write pending transactions are finished.
#define SEMC_INTR_NDPAGEEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) |
NDPAGEEND - NAND page end interrupt
#define SEMC_INTR_NDPAGEEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) |
NDPAGEEND - NAND page end interrupt 0b0..The last address of main space in the NAND is not written by AXI command. 0b1..The last address of main space in the NAND is written by AXI command.
#define SEMC_INTR_NDPAGEEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) |
NDPAGEEND - NAND page end interrupt 0b0..The last address of main space in the NAND is not written by AXI command. 0b1..The last address of main space in the NAND is written by AXI command.
#define SEMC_IOCR_CLKX0_AO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX0_AO_SHIFT)) & SEMC_IOCR_CLKX0_AO_MASK) |
CLKX0_AO - SEMC_CLKX0 Always On 0b0..SEMC_CLKX0 is controlled by MUX_CLKX0 0b1..SEMC_CLKX0 is always on
#define SEMC_IOCR_CLKX0_AO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX0_AO_SHIFT)) & SEMC_IOCR_CLKX0_AO_MASK) |
CLKX0_AO - SEMC_CLKX0 Always On 0b0..SEMC_CLKX0 is controlled by MUX_CLKX0 0b1..SEMC_CLKX0 is always on
#define SEMC_IOCR_CLKX1_AO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX1_AO_SHIFT)) & SEMC_IOCR_CLKX1_AO_MASK) |
CLKX1_AO - SEMC_CLKX1 Always On 0b0..SEMC_CLKX1 is controlled by MUX_CLKX1 0b1..SEMC_CLKX1 is always on
#define SEMC_IOCR_CLKX1_AO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX1_AO_SHIFT)) & SEMC_IOCR_CLKX1_AO_MASK) |
CLKX1_AO - SEMC_CLKX1 Always On 0b0..SEMC_CLKX1 is controlled by MUX_CLKX1 0b1..SEMC_CLKX1 is always on
#define SEMC_IOCR_MUX_A8 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) |
MUX_A8 - SEMC_A8 output selection 0b000..SDRAM Address bit (A8) 0b001..NAND CE# 0b010..NOR CE# 0b011..PSRAM CE# 0b100..DBI CSX 0b101..SDRAM Address bit (A8) 0b110..SDRAM Address bit (A8) 0b111..SDRAM Address bit (A8)
#define SEMC_IOCR_MUX_A8 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) |
MUX_A8 - SEMC_ADDR08 output selection 0b0000-0b0011..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode 0b0100..NAND CE# 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode
#define SEMC_IOCR_MUX_A8 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) |
MUX_A8 - SEMC_ADDR08 output selection 0b0000-0b0011..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode 0b0100..NAND CE# 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode
#define SEMC_IOCR_MUX_CLKX0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK) |
MUX_CLKX0 - SEMC_CLKX0 function selection 0b00..Keep low 0b01..NOR clock 0b10..SRAM clock 0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
#define SEMC_IOCR_MUX_CLKX0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK) |
MUX_CLKX0 - SEMC_CLKX0 function selection 0b00..Keep low 0b01..NOR clock 0b10..SRAM clock 0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
#define SEMC_IOCR_MUX_CLKX1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK) |
MUX_CLKX1 - SEMC_CLKX1 function selection 0b00..Keep low 0b01..NOR clock 0b10..SRAM clock 0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
#define SEMC_IOCR_MUX_CLKX1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK) |
MUX_CLKX1 - SEMC_CLKX1 function selection 0b00..Keep low 0b01..NOR clock 0b10..SRAM clock 0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
#define SEMC_IOCR_MUX_CSX0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) |
MUX_CSX0 - SEMC_CSX0 output selection 0b000..NOR/PSRAM Address bit 24 (A24) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX
#define SEMC_IOCR_MUX_CSX0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) |
MUX_CSX0 - SEMC_CSX0 output selection 0b0000..NOR/SRAM Address bit 24 (A24) in Non-ADMUX mode 0b0001..SDRAM CS1 0b0010..SDRAM CS2 0b0011..SDRAM CS3 0b0100..NAND CE# 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..NOR/SRAM Address bit 24 (A24)
#define SEMC_IOCR_MUX_CSX0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) |
MUX_CSX0 - SEMC_CSX0 output selection 0b0000..NOR/SRAM Address bit 24 (A24) in Non-ADMUX mode 0b0001..SDRAM CS1 0b0010..SDRAM CS2 0b0011..SDRAM CS3 0b0100..NAND CE# 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..NOR/SRAM Address bit 24 (A24)
#define SEMC_IOCR_MUX_CSX1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) |
MUX_CSX1 - SEMC_CSX1 output selection 0b000..NOR/PSRAM Address bit 25 (A25) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX
#define SEMC_IOCR_MUX_CSX1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) |
MUX_CSX1 - SEMC_CSX1 output selection 0b0000..NOR/SRAM Address bit 25 (A25) in Non-ADMUX mode 0b0001..SDRAM CS1 0b0010..SDRAM CS2 0b0011..SDRAM CS3 0b0100..NAND CE# 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..NOR/SRAM Address bit 25 (A25)
#define SEMC_IOCR_MUX_CSX1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) |
MUX_CSX1 - SEMC_CSX1 output selection 0b0000..NOR/SRAM Address bit 25 (A25) in Non-ADMUX mode 0b0001..SDRAM CS1 0b0010..SDRAM CS2 0b0011..SDRAM CS3 0b0100..NAND CE# 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..NOR/SRAM Address bit 25 (A25)
#define SEMC_IOCR_MUX_CSX2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) |
MUX_CSX2 - SEMC_CSX2 output selection 0b000..NOR/PSRAM Address bit 26 (A26) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX
#define SEMC_IOCR_MUX_CSX2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) |
MUX_CSX2 - SEMC_CSX2 output selection 0b0000..NOR/SRAM Address bit 26 (A26) in Non-ADMUX mode 0b0001..SDRAM CS1 0b0010..SDRAM CS2 0b0011..SDRAM CS3 0b0100..NAND CE# 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..NOR/SRAM Address bit 26 (A26)
#define SEMC_IOCR_MUX_CSX2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) |
MUX_CSX2 - SEMC_CSX2 output selection 0b0000..NOR/SRAM Address bit 26 (A26) in Non-ADMUX mode 0b0001..SDRAM CS1 0b0010..SDRAM CS2 0b0011..SDRAM CS3 0b0100..NAND CE# 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..NOR/SRAM Address bit 26 (A26)
#define SEMC_IOCR_MUX_CSX3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) |
MUX_CSX3 - SEMC_CSX3 output selection 0b000..NOR/PSRAM Address bit 27 (A27) 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NAND CE# 0b101..NOR CE# 0b110..PSRAM CE# 0b111..DBI CSX
#define SEMC_IOCR_MUX_CSX3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) |
MUX_CSX3 - SEMC_CSX3 output selection 0b0000..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode 0b0001..SDRAM CS1 0b0010..SDRAM CS2 0b0011..SDRAM CS3 0b0100..NAND CE# 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..NOR/SRAM Address bit 27 (A27)
#define SEMC_IOCR_MUX_CSX3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) |
MUX_CSX3 - SEMC_CSX3 output selection 0b0000..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode 0b0001..SDRAM CS1 0b0010..SDRAM CS2 0b0011..SDRAM CS3 0b0100..NAND CE# 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..NOR/SRAM Address bit 27 (A27)
#define SEMC_IOCR_MUX_RDY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) |
MUX_RDY - SEMC_RDY function selection 0b000..NAND Ready/Wait# input 0b001..SDRAM CS1 0b010..SDRAM CS2 0b011..SDRAM CS3 0b100..NOR CE# 0b101..PSRAM CE# 0b110..DBI CSX 0b111..NOR/PSRAM Address bit 27
#define SEMC_IOCR_MUX_RDY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) |
MUX_RDY - SEMC_RDY function selection 0b0000..NAND R/B# input 0b0001..SDRAM CS1 0b0010..SDRAM CS2 0b0011..SDRAM CS3 0b0100..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..NOR/SRAM Address bit 27
#define SEMC_IOCR_MUX_RDY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) |
MUX_RDY - SEMC_RDY function selection 0b0000..NAND R/B# input 0b0001..SDRAM CS1 0b0010..SDRAM CS2 0b0011..SDRAM CS3 0b0100..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode 0b0101..NOR CE# 0b0110..SRAM CE# 0 0b0111..DBI CSX 0b1000..SRAM CE# 1 0b1001..SRAM CE# 2 0b1010..SRAM CE# 3 0b1011-0b1111..NOR/SRAM Address bit 27
#define SEMC_IPCMD_KEY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) |
KEY - This field should be written with 0xA55A when trigging an IP command.
#define SEMC_IPCR0_SA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) |
SA - Slave address
#define SEMC_IPCR0_SA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) |
SA - Slave address
#define SEMC_IPCR0_SA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) |
SA - Slave address
#define SEMC_IPCR1_DATSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) |
DATSZ - Data Size in Byte 0b000..4 0b001..1 0b010..2 0b011..3 0b100..4 0b101..4 0b110..4 0b111..4
#define SEMC_IPCR1_DATSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) |
DATSZ - Data Size in Byte 0b000..4 0b001..1 0b010..2 0b011..3 0b100..4 0b101..4 0b110..4 0b111..4
#define SEMC_IPCR1_DATSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) |
DATSZ - Data Size in Byte 0b000..4 0b001..1 0b010..2 0b011..3 0b100..4 0b101..4 0b110..4 0b111..4
#define SEMC_IPCR1_NAND_EXT_ADDR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK) |
NAND_EXT_ADDR - NAND Extended Address
#define SEMC_IPCR1_NAND_EXT_ADDR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK) |
NAND_EXT_ADDR - NAND Extended Address
#define SEMC_IPCR2_BM0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) |
BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) 0b0..Byte Unmasked 0b1..Byte Masked
#define SEMC_IPCR2_BM0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) |
BM0 - Byte Mask for Byte 0 (IPTXDAT bit 7:0) 0b0..Byte is unmasked 0b1..Byte is masked
#define SEMC_IPCR2_BM0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) |
BM0 - Byte Mask for Byte 0 (IPTXDAT bit 7:0) 0b0..Byte is unmasked 0b1..Byte is masked
#define SEMC_IPCR2_BM1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) |
BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) 0b0..Byte Unmasked 0b1..Byte Masked
#define SEMC_IPCR2_BM1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) |
BM1 - Byte Mask for Byte 1 (IPTXDAT bit 15:8) 0b0..Byte is unmasked 0b1..Byte is masked
#define SEMC_IPCR2_BM1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) |
BM1 - Byte Mask for Byte 1 (IPTXDAT bit 15:8) 0b0..Byte is unmasked 0b1..Byte is masked
#define SEMC_IPCR2_BM2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) |
BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) 0b0..Byte Unmasked 0b1..Byte Masked
#define SEMC_IPCR2_BM2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) |
BM2 - Byte Mask for Byte 2 (IPTXDAT bit 23:16) 0b0..Byte is unmasked 0b1..Byte is masked
#define SEMC_IPCR2_BM2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) |
BM2 - Byte Mask for Byte 2 (IPTXDAT bit 23:16) 0b0..Byte is unmasked 0b1..Byte is masked
#define SEMC_IPCR2_BM3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) |
BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) 0b0..Byte Unmasked 0b1..Byte Masked
#define SEMC_IPCR2_BM3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) |
BM3 - Byte Mask for Byte 3 (IPTXDAT bit 31:24) 0b0..Byte is unmasked 0b1..Byte is masked
#define SEMC_IPCR2_BM3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) |
BM3 - Byte Mask for Byte 3 (IPTXDAT bit 31:24) 0b0..Byte is unmasked 0b1..Byte is masked
#define SEMC_IPRXDAT_DAT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) |
DAT - data
#define SEMC_IPTXDAT_DAT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) |
DAT - data
#define SEMC_MCR_BTO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) |
BTO - Bus timeout cycles 0b00000..255*1 0b00001-0b11110..255*2 - 255*2^30 0b11111..255*2^31
#define SEMC_MCR_BTO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) |
BTO - Bus timeout cycles 0b00000..255*1 0b00001..255*2 0b11111..255*231
#define SEMC_MCR_BTO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) |
BTO - Bus timeout cycles 0b00000..255*1 0b00001..255*2 0b11111..255*231
#define SEMC_MCR_CTO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) |
CTO - Command Execution timeout cycles
#define SEMC_MCR_CTO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) |
CTO - Command Execution timeout cycles
#define SEMC_MCR_CTO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) |
CTO - Command Execution timeout cycles
#define SEMC_MCR_DQSMD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) |
DQSMD - DQS (read strobe) mode 0b0..Dummy read strobe loopbacked internally 0b1..Dummy read strobe loopbacked from DQS pad
#define SEMC_MCR_DQSMD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) |
DQSMD - DQS (read strobe) mode 0b0..Dummy read strobe loopbacked internally 0b1..Dummy read strobe loopbacked from DQS pad
#define SEMC_MCR_DQSMD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) |
DQSMD - DQS (read strobe) mode 0b0..Dummy read strobe loopbacked internally 0b1..Dummy read strobe loopbacked from DQS pad
#define SEMC_MCR_MDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) |
MDIS - Module Disable 0b0..Module enabled 0b1..Module disabled
#define SEMC_MCR_MDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) |
MDIS - Module Disable 0b0..Module enabled 0b1..Module disabled
#define SEMC_MCR_MDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) |
MDIS - Module Disable 0b0..Module enabled 0b1..Module disabled
#define SEMC_MCR_SWRST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) |
SWRST - Software Reset
#define SEMC_MCR_SWRST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) |
SWRST - Software Reset 0b0..No reset 0b1..Reset
#define SEMC_MCR_SWRST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) |
SWRST - Software Reset 0b0..No reset 0b1..Reset
#define SEMC_MCR_WPOL0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) |
WPOL0 - WAIT/RDY# polarity for NOR/PSRAM 0b0..Active low 0b1..Active high
#define SEMC_MCR_WPOL0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) |
WPOL0 - WAIT/RDY polarity for SRAM/NOR 0b0..WAIT/RDY polarity is not changed. 0b1..WAIT/RDY polarity is inverted.
#define SEMC_MCR_WPOL0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) |
WPOL0 - WAIT/RDY polarity for SRAM/NOR 0b0..WAIT/RDY polarity is not changed. 0b1..WAIT/RDY polarity is inverted.
#define SEMC_MCR_WPOL1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) |
WPOL1 - WAIT/RDY# polarity for NAND 0b0..Active low 0b1..Active high
#define SEMC_MCR_WPOL1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) |
WPOL1 - R/B# polarity for NAND device 0b0..R/B# polarity is not changed. 0b1..R/B# polarity is inverted.
#define SEMC_MCR_WPOL1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) |
WPOL1 - R/B# polarity for NAND device 0b0..R/B# polarity is not changed. 0b1..R/B# polarity is inverted.
#define SEMC_NANDCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_NANDCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_NANDCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_NANDCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) |
COL - Column address bit number 0b000..16 0b001..15 0b010..14 0b011..13 0b100..12 0b101..11 0b110..10 0b111..9
#define SEMC_NANDCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) |
COL - Column address bit number 0b000..16 0b001..15 0b010..14 0b011..13 0b100..12 0b101..11 0b110..10 0b111..9
#define SEMC_NANDCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) |
COL - Column address bit number 0b000..16 0b001..15 0b010..14 0b011..13 0b100..12 0b101..11 0b110..10 0b111..9
#define SEMC_NANDCR0_EDO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) |
EDO - EDO mode enabled 0b0..EDO mode disabled 0b1..EDO mode enabled
#define SEMC_NANDCR0_EDO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) |
EDO - EDO mode enabled 0b0..EDO mode disabled 0b1..EDO mode enabled
#define SEMC_NANDCR0_EDO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) |
EDO - EDO mode enabled 0b0..EDO mode disabled 0b1..EDO mode enabled
#define SEMC_NANDCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_NANDCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_NANDCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_NANDCR0_SYNCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK) |
SYNCEN - Synchronous Mode Enable 0b0..Asynchronous mode is enabled. 0b1..Synchronous mode is enabled.
#define SEMC_NANDCR0_SYNCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK) |
SYNCEN - Synchronous Mode Enable 0b0..Asynchronous mode is enabled. 0b1..Synchronous mode is enabled.
#define SEMC_NANDCR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) |
CEH - CE hold time
#define SEMC_NANDCR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) |
CEH - CE# hold time
#define SEMC_NANDCR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) |
CEH - CE# hold time
#define SEMC_NANDCR1_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) |
CEITV - CE# interval time
#define SEMC_NANDCR1_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) |
CEITV - CE# interval time
#define SEMC_NANDCR1_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) |
CEITV - CE# interval time
#define SEMC_NANDCR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) |
CES - CE setup time
#define SEMC_NANDCR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) |
CES - CE# setup time
#define SEMC_NANDCR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) |
CES - CE# setup time
#define SEMC_NANDCR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) |
REH - RE# high time
#define SEMC_NANDCR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) |
REH - RE# high time
#define SEMC_NANDCR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) |
REH - RE# high time
#define SEMC_NANDCR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) |
REL - RE# low time
#define SEMC_NANDCR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) |
REL - RE# low time
#define SEMC_NANDCR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) |
REL - RE# low time
#define SEMC_NANDCR1_TA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) |
TA - Turnaround time
#define SEMC_NANDCR1_TA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) |
TA - Turnaround time
#define SEMC_NANDCR1_TA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) |
TA - Turnaround time
#define SEMC_NANDCR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) |
WEH - WE# high time
#define SEMC_NANDCR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) |
WEH - WE# high time
#define SEMC_NANDCR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) |
WEH - WE# high time
#define SEMC_NANDCR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) |
WEL - WE# low time
#define SEMC_NANDCR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) |
WEL - WE# low time
#define SEMC_NANDCR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) |
WEL - WE# low time
#define SEMC_NANDCR2_TADL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) |
TADL - ALE to write data start wait time
#define SEMC_NANDCR2_TADL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) |
TADL - Address cycle to data loading time
#define SEMC_NANDCR2_TADL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) |
TADL - Address cycle to data loading time
#define SEMC_NANDCR2_TRHW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) |
TRHW - RE# high to WE# low wait time
#define SEMC_NANDCR2_TRHW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) |
TRHW - RE# high to WE# low time
#define SEMC_NANDCR2_TRHW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) |
TRHW - RE# high to WE# low time
#define SEMC_NANDCR2_TRR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) |
TRR - Ready to RE# low wait time
#define SEMC_NANDCR2_TRR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) |
TRR - Ready to RE# low time
#define SEMC_NANDCR2_TRR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) |
TRR - Ready to RE# low time
#define SEMC_NANDCR2_TWB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) |
TWB - WE# high to busy wait time
#define SEMC_NANDCR2_TWB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) |
TWB - WE# high to busy time
#define SEMC_NANDCR2_TWB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) |
TWB - WE# high to busy time
#define SEMC_NANDCR2_TWHR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) |
TWHR - WE# high to RE# low wait time
#define SEMC_NANDCR2_TWHR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) |
TWHR - WE# high to RE# low time
#define SEMC_NANDCR2_TWHR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) |
TWHR - WE# high to RE# low time
#define SEMC_NANDCR3_CLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK) |
CLE - NAND CLE Option
#define SEMC_NANDCR3_CLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK) |
CLE - NAND CLE Option
#define SEMC_NANDCR3_NDOPT1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) |
NDOPT1 - NAND option bit 1
#define SEMC_NANDCR3_NDOPT1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) |
NDOPT1 - NAND option bit 1
#define SEMC_NANDCR3_NDOPT1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) |
NDOPT1 - NAND option bit 1
#define SEMC_NANDCR3_NDOPT2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) |
NDOPT2 - NAND option bit 2
#define SEMC_NANDCR3_NDOPT2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) |
NDOPT2 - NAND option bit 2
#define SEMC_NANDCR3_NDOPT2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) |
NDOPT2 - NAND option bit 2
#define SEMC_NANDCR3_NDOPT3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) |
NDOPT3 - NAND option bit 3
#define SEMC_NANDCR3_NDOPT3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) |
NDOPT3 - NAND option bit 3
#define SEMC_NANDCR3_NDOPT3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) |
NDOPT3 - NAND option bit 3
#define SEMC_NANDCR3_RDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK) |
RDH - Read Data Hold time
#define SEMC_NANDCR3_RDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK) |
RDH - Read Data Hold time
#define SEMC_NANDCR3_RDS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK) |
RDS - Read Data Setup time
#define SEMC_NANDCR3_RDS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK) |
RDS - Read Data Setup time
#define SEMC_NANDCR3_WDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK) |
WDH - Write Data Hold time
#define SEMC_NANDCR3_WDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK) |
WDH - Write Data Hold time
#define SEMC_NANDCR3_WDS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK) |
WDS - Write Data Setup time
#define SEMC_NANDCR3_WDS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK) |
WDS - Write Data Setup time
#define SEMC_NORCR0_ADVH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK) |
ADVH - ADV# level control during address hold state 0b0..ADV# is high during address hold state. 0b1..ADV# is low during address hold state.
#define SEMC_NORCR0_ADVH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK) |
ADVH - ADV# level control during address hold state 0b0..ADV# is high during address hold state. 0b1..ADV# is low during address hold state.
#define SEMC_NORCR0_ADVP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) |
ADVP - ADV# polarity 0b0..ADV# is active low. 0b1..ADV# is active high.
#define SEMC_NORCR0_ADVP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) |
ADVP - ADV# Polarity 0b0..ADV# is active low. 0b1..ADV# is active high.
#define SEMC_NORCR0_ADVP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) |
ADVP - ADV# Polarity 0b0..ADV# is active low. 0b1..ADV# is active high.
#define SEMC_NORCR0_AM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) |
AM - Address Mode 0b00..Address/Data MUX mode (ADMUX) 0b01..Advanced Address/Data MUX mode (AADM) 0b10..Reserved 0b11..Reserved
#define SEMC_NORCR0_AM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) |
AM - Address Mode 0b00..Address/Data MUX mode (ADMUX) 0b01..Advanced Address/Data MUX mode (AADM) 0b10..Address/Data non-MUX mode (Non-ADMUX) 0b11..Address/Data non-MUX mode (Non-ADMUX)
#define SEMC_NORCR0_AM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) |
AM - Address Mode 0b00..Address/Data MUX mode (ADMUX) 0b01..Advanced Address/Data MUX mode (AADM) 0b10..Address/Data non-MUX mode (Non-ADMUX) 0b11..Address/Data non-MUX mode (Non-ADMUX)
#define SEMC_NORCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_NORCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_NORCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_NORCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) |
COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits
#define SEMC_NORCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) |
COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits
#define SEMC_NORCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) |
COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits
#define SEMC_NORCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_NORCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_NORCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_NORCR0_SYNCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK) |
SYNCEN - Synchronous Mode Enable 0b0..Asynchronous mode is enabled. 0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
#define SEMC_NORCR0_SYNCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK) |
SYNCEN - Synchronous Mode Enable 0b0..Asynchronous mode is enabled. 0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
#define SEMC_NORCR1_AH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) |
AH - Address hold time
#define SEMC_NORCR1_AH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) |
AH - Address hold time
#define SEMC_NORCR1_AH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) |
AH - Address hold time
#define SEMC_NORCR1_AS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) |
AS - Address setup time
#define SEMC_NORCR1_AS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) |
AS - Address setup time
#define SEMC_NORCR1_AS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) |
AS - Address setup time
#define SEMC_NORCR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) |
CEH - CE hold time
#define SEMC_NORCR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) |
CEH - CE hold time
#define SEMC_NORCR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) |
CEH - CE hold time
#define SEMC_NORCR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) |
CES - CE setup time
#define SEMC_NORCR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) |
CES - CE setup time
#define SEMC_NORCR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) |
CES - CE setup time
#define SEMC_NORCR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) |
REH - RE high time
#define SEMC_NORCR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) |
REH - RE high time
#define SEMC_NORCR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) |
REH - RE high time
#define SEMC_NORCR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) |
REL - RE low time
#define SEMC_NORCR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) |
REL - RE low time
#define SEMC_NORCR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) |
REL - RE low time
#define SEMC_NORCR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) |
WEH - WE high time
#define SEMC_NORCR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) |
WEH - WE high time
#define SEMC_NORCR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) |
WEH - WE high time
#define SEMC_NORCR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) |
WEL - WE low time
#define SEMC_NORCR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) |
WEL - WE low time
#define SEMC_NORCR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) |
WEL - WE low time
#define SEMC_NORCR2_AWDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) |
AWDH - Address to write data hold time
#define SEMC_NORCR2_AWDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) |
AWDH - Address to write data hold time
#define SEMC_NORCR2_AWDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) |
AWDH - Address to write data hold time
#define SEMC_NORCR2_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) |
CEITV - CE# interval time
#define SEMC_NORCR2_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) |
CEITV - CE# interval time
#define SEMC_NORCR2_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) |
CEITV - CE# interval time
#define SEMC_NORCR2_LC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK) |
LC - Latency count
#define SEMC_NORCR2_LC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK) |
LC - Latency count
#define SEMC_NORCR2_RD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK) |
RD - Read time
#define SEMC_NORCR2_RD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK) |
RD - Read time
#define SEMC_NORCR2_RDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK) |
RDH - Read hold time
#define SEMC_NORCR2_RDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK) |
RDH - Read hold time
#define SEMC_NORCR2_TA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) |
TA - Turnaround time
#define SEMC_NORCR2_TA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) |
TA - Turnaround time
#define SEMC_NORCR2_TA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) |
TA - Turnaround time
#define SEMC_NORCR3_AHSR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK) |
AHSR - Address hold time for SYNC read
#define SEMC_NORCR3_AHSR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK) |
AHSR - Address hold time for SYNC read
#define SEMC_NORCR3_ASSR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK) |
ASSR - Address setup time for SYNC read
#define SEMC_NORCR3_ASSR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK) |
ASSR - Address setup time for SYNC read
#define SEMC_SDRAMCR0_BANK2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK) |
BANK2 - 2 Bank selection bit 0b0..SDRAM device has 4 banks. 0b1..SDRAM device has 2 banks.
#define SEMC_SDRAMCR0_BANK2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK) |
BANK2 - 2 Bank selection bit 0b0..SDRAM device has 4 banks. 0b1..SDRAM device has 2 banks.
#define SEMC_SDRAMCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..8 0b101..8 0b110..8 0b111..8
#define SEMC_SDRAMCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..8 0b101..8 0b110..8 0b111..8
#define SEMC_SDRAMCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..8 0b101..8 0b110..8 0b111..8
#define SEMC_SDRAMCR0_CL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) |
CL - CAS Latency 0b00..1 0b01..1 0b10..2 0b11..3
#define SEMC_SDRAMCR0_CL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) |
CL - CAS Latency 0b00..1 0b01..1 0b10..2 0b11..3
#define SEMC_SDRAMCR0_CL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) |
CL - CAS Latency 0b00..1 0b01..1 0b10..2 0b11..3
#define SEMC_SDRAMCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) |
COL - Column address bit number 0b00..12 bit 0b01..11 bit 0b10..10 bit 0b11..9 bit
#define SEMC_SDRAMCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) |
COL - Column address bit number 0b00..12 0b01..11 0b10..10 0b11..9
#define SEMC_SDRAMCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) |
COL - Column address bit number 0b00..12 0b01..11 0b10..10 0b11..9
#define SEMC_SDRAMCR0_COL8 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK) |
COL8 - Column 8 selection 0b0..Column address bit number is decided by COL field. 0b1..Column address bit number is 8. COL field is ignored.
#define SEMC_SDRAMCR0_COL8 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK) |
COL8 - Column 8 selection 0b0..Column address bit number is decided by COL field. 0b1..Column address bit number is 8. COL field is ignored.
#define SEMC_SDRAMCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_SDRAMCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) |
PS - Port Size 0b00..8bit 0b01..16bit 0b10..32bit 0b11..Reserved
#define SEMC_SDRAMCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) |
PS - Port Size 0b00..8bit 0b01..16bit 0b10..32bit 0b11..Reserved
#define SEMC_SDRAMCR1_ACT2PRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) |
ACT2PRE - ACT to Precharge minimum time
#define SEMC_SDRAMCR1_ACT2PRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) |
ACT2PRE - ACTIVE to PRECHARGE minimum time
#define SEMC_SDRAMCR1_ACT2PRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) |
ACT2PRE - ACTIVE to PRECHARGE minimum time
#define SEMC_SDRAMCR1_ACT2RW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) |
ACT2RW - ACT to Read/Write wait time
#define SEMC_SDRAMCR1_ACT2RW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) |
ACT2RW - ACTIVE to READ/WRITE delay
#define SEMC_SDRAMCR1_ACT2RW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) |
ACT2RW - ACTIVE to READ/WRITE delay
#define SEMC_SDRAMCR1_CKEOFF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) |
CKEOFF - CKE OFF minimum time
#define SEMC_SDRAMCR1_CKEOFF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) |
CKEOFF - CKE off minimum time
#define SEMC_SDRAMCR1_CKEOFF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) |
CKEOFF - CKE off minimum time
#define SEMC_SDRAMCR1_PRE2ACT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) |
PRE2ACT - PRECHARGE to ACT/Refresh wait time
#define SEMC_SDRAMCR1_PRE2ACT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) |
PRE2ACT - PRECHARGE to ACTIVE/REFRESH command wait time
#define SEMC_SDRAMCR1_PRE2ACT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) |
PRE2ACT - PRECHARGE to ACTIVE/REFRESH command wait time
#define SEMC_SDRAMCR1_RFRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) |
RFRC - Refresh recovery time
#define SEMC_SDRAMCR1_RFRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) |
RFRC - REFRESH recovery time
#define SEMC_SDRAMCR1_RFRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) |
RFRC - REFRESH recovery time
#define SEMC_SDRAMCR1_WRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) |
WRC - Write recovery time
#define SEMC_SDRAMCR1_WRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) |
WRC - WRITE recovery time
#define SEMC_SDRAMCR1_WRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) |
WRC - WRITE recovery time
#define SEMC_SDRAMCR2_ACT2ACT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) |
ACT2ACT - ACT to ACT wait time
#define SEMC_SDRAMCR2_ACT2ACT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) |
ACT2ACT - ACTIVE to ACTIVE delay
#define SEMC_SDRAMCR2_ACT2ACT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) |
ACT2ACT - ACTIVE to ACTIVE delay
#define SEMC_SDRAMCR2_ITO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) |
ITO - SDRAM Idle timeout 0b00000000..IDLE timeout period is 256*Prescale period. 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.
#define SEMC_SDRAMCR2_ITO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) |
ITO - SDRAM idle timeout 0b00000000..IDLE timeout period is 256*Prescale period. 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.
#define SEMC_SDRAMCR2_ITO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) |
ITO - SDRAM idle timeout 0b00000000..IDLE timeout period is 256*Prescale period. 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.
#define SEMC_SDRAMCR2_REF2REF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) |
REF2REF - Refresh to Refresh wait time
#define SEMC_SDRAMCR2_REF2REF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) |
REF2REF - REFRESH to REFRESH delay
#define SEMC_SDRAMCR2_REF2REF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) |
REF2REF - REFRESH to REFRESH delay
#define SEMC_SDRAMCR2_SRRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) |
SRRC - Self Refresh Recovery time
#define SEMC_SDRAMCR2_SRRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) |
SRRC - SELF REFRESH recovery time
#define SEMC_SDRAMCR2_SRRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) |
SRRC - SELF REFRESH recovery time
#define SEMC_SDRAMCR3_PRESCALE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) |
PRESCALE - Prescaler timer period 0b00000000..256*16 clock cycles 0b00000001-0b11111111..PRESCALE*16 clock cycles
#define SEMC_SDRAMCR3_PRESCALE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) |
PRESCALE - Prescaler period 0b00000000..(256*16+1) clock cycles 0b00000001-0b11111111..(PRESCALE*16+1) clock cycles
#define SEMC_SDRAMCR3_PRESCALE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) |
PRESCALE - Prescaler period 0b00000000..(256*16+1) clock cycles 0b00000001-0b11111111..(PRESCALE*16+1) clock cycles
#define SEMC_SDRAMCR3_REBL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) |
REBL - Refresh burst length 0b000..1 0b001..2 0b010..3 0b011..4 0b100..5 0b101..6 0b110..7 0b111..8
#define SEMC_SDRAMCR3_REBL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) |
REBL - Refresh burst length 0b000..1 0b001..2 0b010..3 0b011..4 0b100..5 0b101..6 0b110..7 0b111..8
#define SEMC_SDRAMCR3_REBL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) |
REBL - Refresh burst length 0b000..1 0b001..2 0b010..3 0b011..4 0b100..5 0b101..6 0b110..7 0b111..8
#define SEMC_SDRAMCR3_REN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) |
REN - Refresh enable
#define SEMC_SDRAMCR3_REN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) |
REN - Refresh enable 0b0..The SEMC does not send AUTO REFRESH command automatically 0b1..The SEMC sends AUTO REFRESH command automatically
#define SEMC_SDRAMCR3_REN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) |
REN - Refresh enable 0b0..The SEMC does not send AUTO REFRESH command automatically 0b1..The SEMC sends AUTO REFRESH command automatically
#define SEMC_SDRAMCR3_RT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) |
RT - Refresh timer period 0b00000000..256*Prescaler period 0b00000001-0b11111111..RT*Prescaler period
#define SEMC_SDRAMCR3_RT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) |
RT - Refresh timer period 0b00000000..(256+1)*(Prescaler period) 0b00000001-0b11111111..(RT+1)*(Prescaler period)
#define SEMC_SDRAMCR3_RT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) |
RT - Refresh timer period 0b00000000..(256+1)*(Prescaler period) 0b00000001-0b11111111..(RT+1)*(Prescaler period)
#define SEMC_SDRAMCR3_UT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) |
UT - Refresh urgent threshold 0b00000000..256*Prescaler period 0b00000001-0b11111111..UT*Prescaler period
#define SEMC_SDRAMCR3_UT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) |
UT - Urgent refresh threshold 0b00000000..256*(Prescaler period) 0b00000001-0b11111111..UT*(Prescaler period)
#define SEMC_SDRAMCR3_UT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) |
UT - Urgent refresh threshold 0b00000000..256*(Prescaler period) 0b00000001-0b11111111..UT*(Prescaler period)
#define SEMC_SRAMCR0_ADVH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK) |
ADVH - ADV# level control during address hold state 0b0..ADV# is high during address hold state. 0b1..ADV# is low during address hold state.
#define SEMC_SRAMCR0_ADVH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK) |
ADVH - ADV# level control during address hold state 0b0..ADV# is high during address hold state. 0b1..ADV# is low during address hold state.
#define SEMC_SRAMCR0_ADVP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) |
ADVP - ADV# polarity 0b0..ADV# is active low. 0b1..ADV# is active high.
#define SEMC_SRAMCR0_ADVP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) |
ADVP - ADV# polarity 0b0..ADV# is active low. 0b1..ADV# is active high.
#define SEMC_SRAMCR0_ADVP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) |
ADVP - ADV# polarity 0b0..ADV# is active low. 0b1..ADV# is active high.
#define SEMC_SRAMCR0_AM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) |
AM - Address Mode 0b00..Address/Data MUX mode (ADMUX) 0b01..Advanced Address/Data MUX mode (AADM) 0b10..Reserved 0b11..Reserved
#define SEMC_SRAMCR0_AM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) |
AM - Address Mode 0b00..Address/Data MUX mode (ADMUX) 0b01..Advanced Address/Data MUX mode (AADM) 0b10..Address/Data non-MUX mode (Non-ADMUX) 0b11..Address/Data non-MUX mode (Non-ADMUX)
#define SEMC_SRAMCR0_AM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) |
AM - Address Mode 0b00..Address/Data MUX mode (ADMUX) 0b01..Advanced Address/Data MUX mode (AADM) 0b10..Address/Data non-MUX mode (Non-ADMUX) 0b11..Address/Data non-MUX mode (Non-ADMUX)
#define SEMC_SRAMCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_SRAMCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_SRAMCR0_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_SRAMCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) |
COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits
#define SEMC_SRAMCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) |
COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits
#define SEMC_SRAMCR0_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) |
COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits
#define SEMC_SRAMCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_SRAMCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_SRAMCR0_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_SRAMCR0_SYNCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK) |
SYNCEN - Synchronous Mode Enable 0b0..Asynchronous mode is enabled. 0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
#define SEMC_SRAMCR0_SYNCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK) |
SYNCEN - Synchronous Mode Enable 0b0..Asynchronous mode is enabled. 0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
#define SEMC_SRAMCR0_WAITEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITEN_SHIFT)) & SEMC_SRAMCR0_WAITEN_MASK) |
WAITEN - Wait Enable 0b0..The SEMC does not monitor wait pin. 0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
#define SEMC_SRAMCR0_WAITEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITEN_SHIFT)) & SEMC_SRAMCR0_WAITEN_MASK) |
WAITEN - Wait Enable 0b0..The SEMC does not monitor wait pin. 0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
#define SEMC_SRAMCR0_WAITSP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITSP_SHIFT)) & SEMC_SRAMCR0_WAITSP_MASK) |
WAITSP - Wait Sample 0b0..Wait pin is directly used by the SEMC. 0b1..Wait pin is sampled by internal clock before it is used.
#define SEMC_SRAMCR0_WAITSP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITSP_SHIFT)) & SEMC_SRAMCR0_WAITSP_MASK) |
WAITSP - Wait Sample 0b0..Wait pin is directly used by the SEMC. 0b1..Wait pin is sampled by internal clock before it is used.
#define SEMC_SRAMCR1_AH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) |
AH - Address hold time
#define SEMC_SRAMCR1_AH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) |
AH - Address hold time
#define SEMC_SRAMCR1_AH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) |
AH - Address hold time
#define SEMC_SRAMCR1_AS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) |
AS - Address setup time
#define SEMC_SRAMCR1_AS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) |
AS - Address setup time
#define SEMC_SRAMCR1_AS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) |
AS - Address setup time
#define SEMC_SRAMCR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) |
CEH - CE hold time
#define SEMC_SRAMCR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) |
CEH - CE hold time
#define SEMC_SRAMCR1_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) |
CEH - CE hold time
#define SEMC_SRAMCR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) |
CES - CE setup time
#define SEMC_SRAMCR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) |
CES - CE setup time
#define SEMC_SRAMCR1_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) |
CES - CE setup time
#define SEMC_SRAMCR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) |
REH - RE high time
#define SEMC_SRAMCR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) |
REH - RE high time
#define SEMC_SRAMCR1_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) |
REH - RE high time
#define SEMC_SRAMCR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) |
REL - RE low time
#define SEMC_SRAMCR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) |
REL - RE low time
#define SEMC_SRAMCR1_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) |
REL - RE low time
#define SEMC_SRAMCR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) |
WEH - WE high time
#define SEMC_SRAMCR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) |
WEH - WE high time
#define SEMC_SRAMCR1_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) |
WEH - WE high time
#define SEMC_SRAMCR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) |
WEL - WE low time
#define SEMC_SRAMCR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) |
WEL - WE low time
#define SEMC_SRAMCR1_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) |
WEL - WE low time
#define SEMC_SRAMCR2_AWDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) |
AWDH - Address to write data hold time
#define SEMC_SRAMCR2_AWDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) |
AWDH - Address to write data hold time
#define SEMC_SRAMCR2_AWDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) |
AWDH - Address to write data hold time
#define SEMC_SRAMCR2_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) |
CEITV - CE# interval time
#define SEMC_SRAMCR2_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) |
CEITV - CE# interval time
#define SEMC_SRAMCR2_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) |
CEITV - CE# interval time
#define SEMC_SRAMCR2_LC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK) |
LC - Latency count
#define SEMC_SRAMCR2_LC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK) |
LC - Latency count
#define SEMC_SRAMCR2_RD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK) |
RD - Read time
#define SEMC_SRAMCR2_RD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK) |
RD - Read time
#define SEMC_SRAMCR2_RDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK) |
RDH - Read hold time
#define SEMC_SRAMCR2_RDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK) |
RDH - Read hold time
#define SEMC_SRAMCR2_TA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) |
TA - Turnaround time
#define SEMC_SRAMCR2_TA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) |
TA - Turnaround time
#define SEMC_SRAMCR2_TA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) |
TA - Turnaround time
#define SEMC_SRAMCR2_WDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK) |
WDH - Write Data hold time
#define SEMC_SRAMCR2_WDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK) |
WDH - Write Data hold time
#define SEMC_SRAMCR2_WDS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) |
WDS - Write Data setup time
#define SEMC_SRAMCR2_WDS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) |
WDS - Write Data setup time
#define SEMC_SRAMCR4_ADVH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVH_SHIFT)) & SEMC_SRAMCR4_ADVH_MASK) |
ADVH - ADV# level control during address hold state 0b0..ADV# is high during address hold state. 0b1..ADV# is low during address hold state.
#define SEMC_SRAMCR4_ADVH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVH_SHIFT)) & SEMC_SRAMCR4_ADVH_MASK) |
ADVH - ADV# level control during address hold state 0b0..ADV# is high during address hold state. 0b1..ADV# is low during address hold state.
#define SEMC_SRAMCR4_ADVP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVP_SHIFT)) & SEMC_SRAMCR4_ADVP_MASK) |
ADVP - ADV# polarity 0b0..ADV# is active low. 0b1..ADV# is active high.
#define SEMC_SRAMCR4_ADVP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVP_SHIFT)) & SEMC_SRAMCR4_ADVP_MASK) |
ADVP - ADV# polarity 0b0..ADV# is active low. 0b1..ADV# is active high.
#define SEMC_SRAMCR4_AM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_AM_SHIFT)) & SEMC_SRAMCR4_AM_MASK) |
AM - Address Mode 0b00..Address/Data MUX mode (ADMUX) 0b01..Advanced Address/Data MUX mode (AADM) 0b10..Address/Data non-MUX mode (Non-ADMUX) 0b11..Address/Data non-MUX mode (Non-ADMUX)
#define SEMC_SRAMCR4_AM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_AM_SHIFT)) & SEMC_SRAMCR4_AM_MASK) |
AM - Address Mode 0b00..Address/Data MUX mode (ADMUX) 0b01..Advanced Address/Data MUX mode (AADM) 0b10..Address/Data non-MUX mode (Non-ADMUX) 0b11..Address/Data non-MUX mode (Non-ADMUX)
#define SEMC_SRAMCR4_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_SRAMCR4_BL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK) |
BL - Burst Length 0b000..1 0b001..2 0b010..4 0b011..8 0b100..16 0b101..32 0b110..64 0b111..64
#define SEMC_SRAMCR4_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_COL_SHIFT)) & SEMC_SRAMCR4_COL_MASK) |
COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits
#define SEMC_SRAMCR4_COL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_COL_SHIFT)) & SEMC_SRAMCR4_COL_MASK) |
COL - Column Address bit width 0b0000..12 Bits 0b0001..11 Bits 0b0010..10 Bits 0b0011..9 Bits 0b0100..8 Bits 0b0101..7 Bits 0b0110..6 Bits 0b0111..5 Bits 0b1000..4 Bits 0b1001..3 Bits 0b1010..2 Bits 0b1011..12 Bits 0b1100..12 Bits 0b1101..12 Bits 0b1110..12 Bits 0b1111..12 Bits
#define SEMC_SRAMCR4_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_PS_SHIFT)) & SEMC_SRAMCR4_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_SRAMCR4_PS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_PS_SHIFT)) & SEMC_SRAMCR4_PS_MASK) |
PS - Port Size 0b0..8bit 0b1..16bit
#define SEMC_SRAMCR4_SYNCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK) |
SYNCEN - Synchronous Mode Enable 0b0..Asynchronous mode is enabled. 0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
#define SEMC_SRAMCR4_SYNCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK) |
SYNCEN - Synchronous Mode Enable 0b0..Asynchronous mode is enabled. 0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
#define SEMC_SRAMCR4_WAITEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITEN_SHIFT)) & SEMC_SRAMCR4_WAITEN_MASK) |
WAITEN - Wait Enable 0b0..The SEMC does not monitor wait pin. 0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
#define SEMC_SRAMCR4_WAITEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITEN_SHIFT)) & SEMC_SRAMCR4_WAITEN_MASK) |
WAITEN - Wait Enable 0b0..The SEMC does not monitor wait pin. 0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
#define SEMC_SRAMCR4_WAITSP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITSP_SHIFT)) & SEMC_SRAMCR4_WAITSP_MASK) |
WAITSP - Wait Sample 0b0..Wait pin is directly used by the SEMC. 0b1..Wait pin is sampled by internal clock before it is used.
#define SEMC_SRAMCR4_WAITSP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITSP_SHIFT)) & SEMC_SRAMCR4_WAITSP_MASK) |
WAITSP - Wait Sample 0b0..Wait pin is directly used by the SEMC. 0b1..Wait pin is sampled by internal clock before it is used.
#define SEMC_SRAMCR5_AH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AH_SHIFT)) & SEMC_SRAMCR5_AH_MASK) |
AH - Address hold time
#define SEMC_SRAMCR5_AH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AH_SHIFT)) & SEMC_SRAMCR5_AH_MASK) |
AH - Address hold time
#define SEMC_SRAMCR5_AS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AS_SHIFT)) & SEMC_SRAMCR5_AS_MASK) |
AS - Address setup time
#define SEMC_SRAMCR5_AS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AS_SHIFT)) & SEMC_SRAMCR5_AS_MASK) |
AS - Address setup time
#define SEMC_SRAMCR5_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_SRAMCR5_CEH_MASK) |
CEH - CE hold time
#define SEMC_SRAMCR5_CEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_SRAMCR5_CEH_MASK) |
CEH - CE hold time
#define SEMC_SRAMCR5_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CES_SHIFT)) & SEMC_SRAMCR5_CES_MASK) |
CES - CE setup time
#define SEMC_SRAMCR5_CES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CES_SHIFT)) & SEMC_SRAMCR5_CES_MASK) |
CES - CE setup time
#define SEMC_SRAMCR5_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REH_SHIFT)) & SEMC_SRAMCR5_REH_MASK) |
REH - RE high time
#define SEMC_SRAMCR5_REH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REH_SHIFT)) & SEMC_SRAMCR5_REH_MASK) |
REH - RE high time
#define SEMC_SRAMCR5_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REL_SHIFT)) & SEMC_SRAMCR5_REL_MASK) |
REL - RE low time
#define SEMC_SRAMCR5_REL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REL_SHIFT)) & SEMC_SRAMCR5_REL_MASK) |
REL - RE low time
#define SEMC_SRAMCR5_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEH_SHIFT)) & SEMC_SRAMCR5_WEH_MASK) |
WEH - WE high time
#define SEMC_SRAMCR5_WEH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEH_SHIFT)) & SEMC_SRAMCR5_WEH_MASK) |
WEH - WE high time
#define SEMC_SRAMCR5_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEL_SHIFT)) & SEMC_SRAMCR5_WEL_MASK) |
WEL - WE low time
#define SEMC_SRAMCR5_WEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEL_SHIFT)) & SEMC_SRAMCR5_WEL_MASK) |
WEL - WE low time
#define SEMC_SRAMCR6_AWDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_AWDH_SHIFT)) & SEMC_SRAMCR6_AWDH_MASK) |
AWDH - Address to write data hold time
#define SEMC_SRAMCR6_AWDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_AWDH_SHIFT)) & SEMC_SRAMCR6_AWDH_MASK) |
AWDH - Address to write data hold time
#define SEMC_SRAMCR6_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_CEITV_SHIFT)) & SEMC_SRAMCR6_CEITV_MASK) |
CEITV - CE# interval time
#define SEMC_SRAMCR6_CEITV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_CEITV_SHIFT)) & SEMC_SRAMCR6_CEITV_MASK) |
CEITV - CE# interval time
#define SEMC_SRAMCR6_LC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_LC_SHIFT)) & SEMC_SRAMCR6_LC_MASK) |
LC - Latency count
#define SEMC_SRAMCR6_LC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_LC_SHIFT)) & SEMC_SRAMCR6_LC_MASK) |
LC - Latency count
#define SEMC_SRAMCR6_RD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RD_SHIFT)) & SEMC_SRAMCR6_RD_MASK) |
RD - Read time
#define SEMC_SRAMCR6_RD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RD_SHIFT)) & SEMC_SRAMCR6_RD_MASK) |
RD - Read time
#define SEMC_SRAMCR6_RDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RDH_SHIFT)) & SEMC_SRAMCR6_RDH_MASK) |
RDH - Read hold time
#define SEMC_SRAMCR6_RDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RDH_SHIFT)) & SEMC_SRAMCR6_RDH_MASK) |
RDH - Read hold time
#define SEMC_SRAMCR6_TA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_TA_SHIFT)) & SEMC_SRAMCR6_TA_MASK) |
TA - Turnaround time
#define SEMC_SRAMCR6_TA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_TA_SHIFT)) & SEMC_SRAMCR6_TA_MASK) |
TA - Turnaround time
#define SEMC_SRAMCR6_WDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDH_SHIFT)) & SEMC_SRAMCR6_WDH_MASK) |
WDH - Write Data hold time
#define SEMC_SRAMCR6_WDH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDH_SHIFT)) & SEMC_SRAMCR6_WDH_MASK) |
WDH - Write Data hold time
#define SEMC_SRAMCR6_WDS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDS_SHIFT)) & SEMC_SRAMCR6_WDS_MASK) |
WDS - Write Data setup time
#define SEMC_SRAMCR6_WDS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDS_SHIFT)) & SEMC_SRAMCR6_WDS_MASK) |
WDS - Write Data setup time
#define SEMC_STS0_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
IDLE - Indicating whether SEMC is in IDLE state.
#define SEMC_STS0_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
IDLE - Indicating whether the SEMC is in idle state.
#define SEMC_STS0_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
IDLE - Indicating whether the SEMC is in idle state.
#define SEMC_STS0_NARDY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
NARDY - Indicating NAND device Ready/WAIT# pin level. 0b0..NAND device is not ready 0b1..NAND device is ready
#define SEMC_STS0_NARDY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
NARDY - Indicating NAND device Ready/WAIT# pin level. 0b0..NAND device is not ready 0b1..NAND device is ready
#define SEMC_STS0_NARDY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
NARDY - Indicating NAND device Ready/WAIT# pin level. 0b0..NAND device is not ready 0b1..NAND device is ready
#define SEMC_STS12_NDADDR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) |
NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4).
#define SEMC_STS12_NDADDR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) |
NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4).
#define SEMC_STS12_NDADDR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) |
NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4).
#define SEMC_STS13_REFLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK) |
REFLOCK - Sample clock reference delay line locked. 0b0..Reference delay line is not locked. 0b1..Reference delay line is locked.
#define SEMC_STS13_REFLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK) |
REFLOCK - Sample clock reference delay line locked. 0b0..Reference delay line is not locked. 0b1..Reference delay line is locked.
#define SEMC_STS13_REFSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK) |
REFSEL - Sample clock reference delay line delay cell number selection.
#define SEMC_STS13_REFSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK) |
REFSEL - Sample clock reference delay line delay cell number selection.
#define SEMC_STS13_SLVLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK) |
SLVLOCK - Sample clock slave delay line locked. 0b0..Slave delay line is not locked. 0b1..Slave delay line is locked.
#define SEMC_STS13_SLVLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK) |
SLVLOCK - Sample clock slave delay line locked. 0b0..Slave delay line is not locked. 0b1..Slave delay line is locked.
#define SEMC_STS13_SLVSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK) |
SLVSEL - Sample clock slave delay line delay cell number selection.
#define SEMC_STS13_SLVSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK) |
SLVSEL - Sample clock slave delay line delay cell number selection.
#define SEMC_STS2_NDWRPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. 0b0..No pending 0b1..Pending
#define SEMC_STS2_NDWRPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. 0b0..No pending 0b1..Pending
#define SEMC_STS2_NDWRPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. 0b0..No pending 0b1..Pending
#define XRDC2_MCR_GCL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK) |
GCL - Global Configuration Lock 0b00..Lock disabled, registers can be written by any domain. 0b01..Lock disabled until the next reset, registers can be written by any domain. 0b10..Lock enabled, only the global configuration lock owner (SR[GCLO]) can write to registers. 0b11..Lock enabled, all registers are read only until the next reset.
#define XRDC2_MCR_GCL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK) |
GCL - Global Configuration Lock 0b00..Lock disabled, registers can be written by any domain. 0b01..Lock disabled until the next reset, registers can be written by any domain. 0b10..Lock enabled, only the global configuration lock owner (SR[GCLO]) can write to registers. 0b11..Lock enabled, all registers are read only until the next reset.
#define XRDC2_MCR_GVLDC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK) |
GVLDC - Global Valid Access Control 0b0..Access controls are disabled, XRDC2 allows all transactions. 0b1..Access controls are enabled.
#define XRDC2_MCR_GVLDC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK) |
GVLDC - Global Valid Access Control 0b0..Access controls are disabled, XRDC2 allows all transactions. 0b1..Access controls are enabled.
#define XRDC2_MCR_GVLDM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK) |
GVLDM - Global Valid MDAC 0b0..MDACs are disabled. 0b1..MDACs are enabled.
#define XRDC2_MCR_GVLDM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK) |
GVLDM - Global Valid MDAC 0b0..MDACs are disabled. 0b1..MDACs are enabled.