XRDC2 Register Masks

Macros
#define	XRDC2_MSC_MSAC_W0_COUNT   (128U)
#define	XRDC2_MSC_MSAC_W1_COUNT   (128U)
#define	XRDC2_MDAC_MDA_W0_COUNT   (32U)
#define	XRDC2_MDAC_MDA_W0_COUNT2   (32U)
#define	XRDC2_MDAC_MDA_W1_COUNT   (32U)
#define	XRDC2_MDAC_MDA_W1_COUNT2   (32U)
#define	XRDC2_PAC_PDAC_W0_COUNT   (8U)
#define	XRDC2_PAC_PDAC_W0_COUNT2   (256U)
#define	XRDC2_PAC_PDAC_W1_COUNT   (8U)
#define	XRDC2_PAC_PDAC_W1_COUNT2   (256U)
#define	XRDC2_MRC_MRGD_W0_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W0_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W1_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W1_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W2_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W2_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W3_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W3_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W5_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W5_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W6_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W6_COUNT2   (32U)
#define	XRDC2_MSC_MSAC_W0_COUNT   (128U)
#define	XRDC2_MSC_MSAC_W1_COUNT   (128U)
#define	XRDC2_MDAC_MDA_W0_COUNT   (32U)
#define	XRDC2_MDAC_MDA_W0_COUNT2   (32U)
#define	XRDC2_MDAC_MDA_W1_COUNT   (32U)
#define	XRDC2_MDAC_MDA_W1_COUNT2   (32U)
#define	XRDC2_PAC_PDAC_W0_COUNT   (8U)
#define	XRDC2_PAC_PDAC_W0_COUNT2   (256U)
#define	XRDC2_PAC_PDAC_W1_COUNT   (8U)
#define	XRDC2_PAC_PDAC_W1_COUNT2   (256U)
#define	XRDC2_MRC_MRGD_W0_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W0_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W1_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W1_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W2_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W2_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W3_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W3_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W5_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W5_COUNT2   (32U)
#define	XRDC2_MRC_MRGD_W6_COUNT   (32U)
#define	XRDC2_MRC_MRGD_W6_COUNT2   (32U)

MCR - Module Control Register
#define	XRDC2_MCR_GVLDM_MASK   (0x1U)
#define	XRDC2_MCR_GVLDM_SHIFT   (0U)
#define	XRDC2_MCR_GVLDM(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK)
#define	XRDC2_MCR_GVLDC_MASK   (0x2U)
#define	XRDC2_MCR_GVLDC_SHIFT   (1U)
#define	XRDC2_MCR_GVLDC(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK)
#define	XRDC2_MCR_GCL_MASK   (0x30U)
#define	XRDC2_MCR_GCL_SHIFT   (4U)
#define	XRDC2_MCR_GCL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK)

SR - Status Register
#define	XRDC2_SR_DIN_MASK   (0xFU)
#define	XRDC2_SR_DIN_SHIFT   (0U)
#define	XRDC2_SR_DIN(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)
#define	XRDC2_SR_HRL_MASK   (0xF0U)
#define	XRDC2_SR_HRL_SHIFT   (4U)
#define	XRDC2_SR_HRL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)
#define	XRDC2_SR_GCLO_MASK   (0xF00U)
#define	XRDC2_SR_GCLO_SHIFT   (8U)
#define	XRDC2_SR_GCLO(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)

MSC_MSAC_W0 - Memory Slot Access Control
#define	XRDC2_MSC_MSAC_W0_D0ACP_MASK   (0x7U)
#define	XRDC2_MSC_MSAC_W0_D0ACP_SHIFT   (0U)
#define	XRDC2_MSC_MSAC_W0_D0ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D1ACP_MASK   (0x38U)
#define	XRDC2_MSC_MSAC_W0_D1ACP_SHIFT   (3U)
#define	XRDC2_MSC_MSAC_W0_D1ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D2ACP_MASK   (0x1C0U)
#define	XRDC2_MSC_MSAC_W0_D2ACP_SHIFT   (6U)
#define	XRDC2_MSC_MSAC_W0_D2ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D3ACP_MASK   (0xE00U)
#define	XRDC2_MSC_MSAC_W0_D3ACP_SHIFT   (9U)
#define	XRDC2_MSC_MSAC_W0_D3ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D4ACP_MASK   (0x7000U)
#define	XRDC2_MSC_MSAC_W0_D4ACP_SHIFT   (12U)
#define	XRDC2_MSC_MSAC_W0_D4ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D5ACP_MASK   (0x38000U)
#define	XRDC2_MSC_MSAC_W0_D5ACP_SHIFT   (15U)
#define	XRDC2_MSC_MSAC_W0_D5ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D6ACP_MASK   (0x1C0000U)
#define	XRDC2_MSC_MSAC_W0_D6ACP_SHIFT   (18U)
#define	XRDC2_MSC_MSAC_W0_D6ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D7ACP_MASK   (0xE00000U)
#define	XRDC2_MSC_MSAC_W0_D7ACP_SHIFT   (21U)
#define	XRDC2_MSC_MSAC_W0_D7ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_EALO_MASK   (0xF000000U)
#define	XRDC2_MSC_MSAC_W0_EALO_SHIFT   (24U)
#define	XRDC2_MSC_MSAC_W0_EALO(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_EALO_SHIFT)) & XRDC2_MSC_MSAC_W0_EALO_MASK)

MSC_MSAC_W1 - Memory Slot Access Control
#define	XRDC2_MSC_MSAC_W1_D8ACP_MASK   (0x7U)
#define	XRDC2_MSC_MSAC_W1_D8ACP_SHIFT   (0U)
#define	XRDC2_MSC_MSAC_W1_D8ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D9ACP_MASK   (0x38U)
#define	XRDC2_MSC_MSAC_W1_D9ACP_SHIFT   (3U)
#define	XRDC2_MSC_MSAC_W1_D9ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D10ACP_MASK   (0x1C0U)
#define	XRDC2_MSC_MSAC_W1_D10ACP_SHIFT   (6U)
#define	XRDC2_MSC_MSAC_W1_D10ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D11ACP_MASK   (0xE00U)
#define	XRDC2_MSC_MSAC_W1_D11ACP_SHIFT   (9U)
#define	XRDC2_MSC_MSAC_W1_D11ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D12ACP_MASK   (0x7000U)
#define	XRDC2_MSC_MSAC_W1_D12ACP_SHIFT   (12U)
#define	XRDC2_MSC_MSAC_W1_D12ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D13ACP_MASK   (0x38000U)
#define	XRDC2_MSC_MSAC_W1_D13ACP_SHIFT   (15U)
#define	XRDC2_MSC_MSAC_W1_D13ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D14ACP_MASK   (0x1C0000U)
#define	XRDC2_MSC_MSAC_W1_D14ACP_SHIFT   (18U)
#define	XRDC2_MSC_MSAC_W1_D14ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D15ACP_MASK   (0xE00000U)
#define	XRDC2_MSC_MSAC_W1_D15ACP_SHIFT   (21U)
#define	XRDC2_MSC_MSAC_W1_D15ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_EAL_MASK   (0x3000000U)
#define	XRDC2_MSC_MSAC_W1_EAL_SHIFT   (24U)
#define	XRDC2_MSC_MSAC_W1_EAL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK)
#define	XRDC2_MSC_MSAC_W1_DL2_MASK   (0x60000000U)
#define	XRDC2_MSC_MSAC_W1_DL2_SHIFT   (29U)
#define	XRDC2_MSC_MSAC_W1_DL2(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK)
#define	XRDC2_MSC_MSAC_W1_VLD_MASK   (0x80000000U)
#define	XRDC2_MSC_MSAC_W1_VLD_SHIFT   (31U)
#define	XRDC2_MSC_MSAC_W1_VLD(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_VLD_SHIFT)) & XRDC2_MSC_MSAC_W1_VLD_MASK)

MDAC_MDA_W0 - Master Domain Assignment
#define	XRDC2_MDAC_MDA_W0_MASK_MASK   (0xFFFFU)
#define	XRDC2_MDAC_MDA_W0_MASK_SHIFT   (0U)
#define	XRDC2_MDAC_MDA_W0_MASK(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK)
#define	XRDC2_MDAC_MDA_W0_MATCH_MASK   (0xFFFF0000U)
#define	XRDC2_MDAC_MDA_W0_MATCH_SHIFT   (16U)
#define	XRDC2_MDAC_MDA_W0_MATCH(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MATCH_SHIFT)) & XRDC2_MDAC_MDA_W0_MATCH_MASK)

MDAC_MDA_W1 - Master Domain Assignment
#define	XRDC2_MDAC_MDA_W1_DID_MASK   (0xF0000U)
#define	XRDC2_MDAC_MDA_W1_DID_SHIFT   (16U)
#define	XRDC2_MDAC_MDA_W1_DID(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK)
#define	XRDC2_MDAC_MDA_W1_PA_MASK   (0x3000000U)
#define	XRDC2_MDAC_MDA_W1_PA_SHIFT   (24U)
#define	XRDC2_MDAC_MDA_W1_PA(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK)
#define	XRDC2_MDAC_MDA_W1_SA_MASK   (0xC000000U)
#define	XRDC2_MDAC_MDA_W1_SA_SHIFT   (26U)
#define	XRDC2_MDAC_MDA_W1_SA(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK)
#define	XRDC2_MDAC_MDA_W1_DL_MASK   (0x40000000U)
#define	XRDC2_MDAC_MDA_W1_DL_SHIFT   (30U)
#define	XRDC2_MDAC_MDA_W1_DL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK)
#define	XRDC2_MDAC_MDA_W1_VLD_MASK   (0x80000000U)
#define	XRDC2_MDAC_MDA_W1_VLD_SHIFT   (31U)
#define	XRDC2_MDAC_MDA_W1_VLD(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_VLD_SHIFT)) & XRDC2_MDAC_MDA_W1_VLD_MASK)

PAC_PDAC_W0 - Peripheral Domain Access Control
#define	XRDC2_PAC_PDAC_W0_D0ACP_MASK   (0x7U)
#define	XRDC2_PAC_PDAC_W0_D0ACP_SHIFT   (0U)
#define	XRDC2_PAC_PDAC_W0_D0ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D1ACP_MASK   (0x38U)
#define	XRDC2_PAC_PDAC_W0_D1ACP_SHIFT   (3U)
#define	XRDC2_PAC_PDAC_W0_D1ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D2ACP_MASK   (0x1C0U)
#define	XRDC2_PAC_PDAC_W0_D2ACP_SHIFT   (6U)
#define	XRDC2_PAC_PDAC_W0_D2ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D3ACP_MASK   (0xE00U)
#define	XRDC2_PAC_PDAC_W0_D3ACP_SHIFT   (9U)
#define	XRDC2_PAC_PDAC_W0_D3ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D4ACP_MASK   (0x7000U)
#define	XRDC2_PAC_PDAC_W0_D4ACP_SHIFT   (12U)
#define	XRDC2_PAC_PDAC_W0_D4ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D5ACP_MASK   (0x38000U)
#define	XRDC2_PAC_PDAC_W0_D5ACP_SHIFT   (15U)
#define	XRDC2_PAC_PDAC_W0_D5ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D6ACP_MASK   (0x1C0000U)
#define	XRDC2_PAC_PDAC_W0_D6ACP_SHIFT   (18U)
#define	XRDC2_PAC_PDAC_W0_D6ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D7ACP_MASK   (0xE00000U)
#define	XRDC2_PAC_PDAC_W0_D7ACP_SHIFT   (21U)
#define	XRDC2_PAC_PDAC_W0_D7ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_EALO_MASK   (0xF000000U)
#define	XRDC2_PAC_PDAC_W0_EALO_SHIFT   (24U)
#define	XRDC2_PAC_PDAC_W0_EALO(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_EALO_SHIFT)) & XRDC2_PAC_PDAC_W0_EALO_MASK)

PAC_PDAC_W1 - Peripheral Domain Access Control
#define	XRDC2_PAC_PDAC_W1_D8ACP_MASK   (0x7U)
#define	XRDC2_PAC_PDAC_W1_D8ACP_SHIFT   (0U)
#define	XRDC2_PAC_PDAC_W1_D8ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D9ACP_MASK   (0x38U)
#define	XRDC2_PAC_PDAC_W1_D9ACP_SHIFT   (3U)
#define	XRDC2_PAC_PDAC_W1_D9ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D10ACP_MASK   (0x1C0U)
#define	XRDC2_PAC_PDAC_W1_D10ACP_SHIFT   (6U)
#define	XRDC2_PAC_PDAC_W1_D10ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D11ACP_MASK   (0xE00U)
#define	XRDC2_PAC_PDAC_W1_D11ACP_SHIFT   (9U)
#define	XRDC2_PAC_PDAC_W1_D11ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D12ACP_MASK   (0x7000U)
#define	XRDC2_PAC_PDAC_W1_D12ACP_SHIFT   (12U)
#define	XRDC2_PAC_PDAC_W1_D12ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D13ACP_MASK   (0x38000U)
#define	XRDC2_PAC_PDAC_W1_D13ACP_SHIFT   (15U)
#define	XRDC2_PAC_PDAC_W1_D13ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D14ACP_MASK   (0x1C0000U)
#define	XRDC2_PAC_PDAC_W1_D14ACP_SHIFT   (18U)
#define	XRDC2_PAC_PDAC_W1_D14ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D15ACP_MASK   (0xE00000U)
#define	XRDC2_PAC_PDAC_W1_D15ACP_SHIFT   (21U)
#define	XRDC2_PAC_PDAC_W1_D15ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_EAL_MASK   (0x3000000U)
#define	XRDC2_PAC_PDAC_W1_EAL_SHIFT   (24U)
#define	XRDC2_PAC_PDAC_W1_EAL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK)
#define	XRDC2_PAC_PDAC_W1_DL2_MASK   (0x60000000U)
#define	XRDC2_PAC_PDAC_W1_DL2_SHIFT   (29U)
#define	XRDC2_PAC_PDAC_W1_DL2(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK)
#define	XRDC2_PAC_PDAC_W1_VLD_MASK   (0x80000000U)
#define	XRDC2_PAC_PDAC_W1_VLD_SHIFT   (31U)
#define	XRDC2_PAC_PDAC_W1_VLD(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_VLD_SHIFT)) & XRDC2_PAC_PDAC_W1_VLD_MASK)

MRC_MRGD_W0 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W0_SRTADDR_MASK   (0xFFFFF000U)
#define	XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W0_SRTADDR(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W0_SRTADDR_MASK)

MRC_MRGD_W1 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W1_SRTADDR_MASK   (0xFU)
#define	XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W1_SRTADDR(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W1_SRTADDR_MASK)

MRC_MRGD_W2 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W2_ENDADDR_MASK   (0xFFFFF000U)
#define	XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W2_ENDADDR(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W2_ENDADDR_MASK)

MRC_MRGD_W3 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W3_ENDADDR_MASK   (0xFU)
#define	XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W3_ENDADDR(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W3_ENDADDR_MASK)

MRC_MRGD_W5 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W5_D0ACP_MASK   (0x7U)
#define	XRDC2_MRC_MRGD_W5_D0ACP_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W5_D0ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D1ACP_MASK   (0x38U)
#define	XRDC2_MRC_MRGD_W5_D1ACP_SHIFT   (3U)
#define	XRDC2_MRC_MRGD_W5_D1ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D2ACP_MASK   (0x1C0U)
#define	XRDC2_MRC_MRGD_W5_D2ACP_SHIFT   (6U)
#define	XRDC2_MRC_MRGD_W5_D2ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D3ACP_MASK   (0xE00U)
#define	XRDC2_MRC_MRGD_W5_D3ACP_SHIFT   (9U)
#define	XRDC2_MRC_MRGD_W5_D3ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D4ACP_MASK   (0x7000U)
#define	XRDC2_MRC_MRGD_W5_D4ACP_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W5_D4ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D5ACP_MASK   (0x38000U)
#define	XRDC2_MRC_MRGD_W5_D5ACP_SHIFT   (15U)
#define	XRDC2_MRC_MRGD_W5_D5ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D6ACP_MASK   (0x1C0000U)
#define	XRDC2_MRC_MRGD_W5_D6ACP_SHIFT   (18U)
#define	XRDC2_MRC_MRGD_W5_D6ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D7ACP_MASK   (0xE00000U)
#define	XRDC2_MRC_MRGD_W5_D7ACP_SHIFT   (21U)
#define	XRDC2_MRC_MRGD_W5_D7ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_EALO_MASK   (0xF000000U)
#define	XRDC2_MRC_MRGD_W5_EALO_SHIFT   (24U)
#define	XRDC2_MRC_MRGD_W5_EALO(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_EALO_SHIFT)) & XRDC2_MRC_MRGD_W5_EALO_MASK)

MRC_MRGD_W6 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W6_D8ACP_MASK   (0x7U)
#define	XRDC2_MRC_MRGD_W6_D8ACP_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W6_D8ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D9ACP_MASK   (0x38U)
#define	XRDC2_MRC_MRGD_W6_D9ACP_SHIFT   (3U)
#define	XRDC2_MRC_MRGD_W6_D9ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D10ACP_MASK   (0x1C0U)
#define	XRDC2_MRC_MRGD_W6_D10ACP_SHIFT   (6U)
#define	XRDC2_MRC_MRGD_W6_D10ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D11ACP_MASK   (0xE00U)
#define	XRDC2_MRC_MRGD_W6_D11ACP_SHIFT   (9U)
#define	XRDC2_MRC_MRGD_W6_D11ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D12ACP_MASK   (0x7000U)
#define	XRDC2_MRC_MRGD_W6_D12ACP_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W6_D12ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D13ACP_MASK   (0x38000U)
#define	XRDC2_MRC_MRGD_W6_D13ACP_SHIFT   (15U)
#define	XRDC2_MRC_MRGD_W6_D13ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D14ACP_MASK   (0x1C0000U)
#define	XRDC2_MRC_MRGD_W6_D14ACP_SHIFT   (18U)
#define	XRDC2_MRC_MRGD_W6_D14ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D15ACP_MASK   (0xE00000U)
#define	XRDC2_MRC_MRGD_W6_D15ACP_SHIFT   (21U)
#define	XRDC2_MRC_MRGD_W6_D15ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_EAL_MASK   (0x3000000U)
#define	XRDC2_MRC_MRGD_W6_EAL_SHIFT   (24U)
#define	XRDC2_MRC_MRGD_W6_EAL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK)
#define	XRDC2_MRC_MRGD_W6_DL2_MASK   (0x60000000U)
#define	XRDC2_MRC_MRGD_W6_DL2_SHIFT   (29U)
#define	XRDC2_MRC_MRGD_W6_DL2(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK)
#define	XRDC2_MRC_MRGD_W6_VLD_MASK   (0x80000000U)
#define	XRDC2_MRC_MRGD_W6_VLD_SHIFT   (31U)
#define	XRDC2_MRC_MRGD_W6_VLD(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_VLD_SHIFT)) & XRDC2_MRC_MRGD_W6_VLD_MASK)

MCR - Module Control Register
#define	XRDC2_MCR_GVLDM_MASK   (0x1U)
#define	XRDC2_MCR_GVLDM_SHIFT   (0U)
#define	XRDC2_MCR_GVLDM(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK)
#define	XRDC2_MCR_GVLDC_MASK   (0x2U)
#define	XRDC2_MCR_GVLDC_SHIFT   (1U)
#define	XRDC2_MCR_GVLDC(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK)
#define	XRDC2_MCR_GCL_MASK   (0x30U)
#define	XRDC2_MCR_GCL_SHIFT   (4U)
#define	XRDC2_MCR_GCL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK)

SR - Status Register
#define	XRDC2_SR_DIN_MASK   (0xFU)
#define	XRDC2_SR_DIN_SHIFT   (0U)
#define	XRDC2_SR_DIN(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)
#define	XRDC2_SR_HRL_MASK   (0xF0U)
#define	XRDC2_SR_HRL_SHIFT   (4U)
#define	XRDC2_SR_HRL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)
#define	XRDC2_SR_GCLO_MASK   (0xF00U)
#define	XRDC2_SR_GCLO_SHIFT   (8U)
#define	XRDC2_SR_GCLO(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)

MSC_MSAC_W0 - Memory Slot Access Control
#define	XRDC2_MSC_MSAC_W0_D0ACP_MASK   (0x7U)
#define	XRDC2_MSC_MSAC_W0_D0ACP_SHIFT   (0U)
#define	XRDC2_MSC_MSAC_W0_D0ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D1ACP_MASK   (0x38U)
#define	XRDC2_MSC_MSAC_W0_D1ACP_SHIFT   (3U)
#define	XRDC2_MSC_MSAC_W0_D1ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D2ACP_MASK   (0x1C0U)
#define	XRDC2_MSC_MSAC_W0_D2ACP_SHIFT   (6U)
#define	XRDC2_MSC_MSAC_W0_D2ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D3ACP_MASK   (0xE00U)
#define	XRDC2_MSC_MSAC_W0_D3ACP_SHIFT   (9U)
#define	XRDC2_MSC_MSAC_W0_D3ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D4ACP_MASK   (0x7000U)
#define	XRDC2_MSC_MSAC_W0_D4ACP_SHIFT   (12U)
#define	XRDC2_MSC_MSAC_W0_D4ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D5ACP_MASK   (0x38000U)
#define	XRDC2_MSC_MSAC_W0_D5ACP_SHIFT   (15U)
#define	XRDC2_MSC_MSAC_W0_D5ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D6ACP_MASK   (0x1C0000U)
#define	XRDC2_MSC_MSAC_W0_D6ACP_SHIFT   (18U)
#define	XRDC2_MSC_MSAC_W0_D6ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_D7ACP_MASK   (0xE00000U)
#define	XRDC2_MSC_MSAC_W0_D7ACP_SHIFT   (21U)
#define	XRDC2_MSC_MSAC_W0_D7ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK)
#define	XRDC2_MSC_MSAC_W0_EALO_MASK   (0xF000000U)
#define	XRDC2_MSC_MSAC_W0_EALO_SHIFT   (24U)
#define	XRDC2_MSC_MSAC_W0_EALO(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_EALO_SHIFT)) & XRDC2_MSC_MSAC_W0_EALO_MASK)

MSC_MSAC_W1 - Memory Slot Access Control
#define	XRDC2_MSC_MSAC_W1_D8ACP_MASK   (0x7U)
#define	XRDC2_MSC_MSAC_W1_D8ACP_SHIFT   (0U)
#define	XRDC2_MSC_MSAC_W1_D8ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D9ACP_MASK   (0x38U)
#define	XRDC2_MSC_MSAC_W1_D9ACP_SHIFT   (3U)
#define	XRDC2_MSC_MSAC_W1_D9ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D10ACP_MASK   (0x1C0U)
#define	XRDC2_MSC_MSAC_W1_D10ACP_SHIFT   (6U)
#define	XRDC2_MSC_MSAC_W1_D10ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D11ACP_MASK   (0xE00U)
#define	XRDC2_MSC_MSAC_W1_D11ACP_SHIFT   (9U)
#define	XRDC2_MSC_MSAC_W1_D11ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D12ACP_MASK   (0x7000U)
#define	XRDC2_MSC_MSAC_W1_D12ACP_SHIFT   (12U)
#define	XRDC2_MSC_MSAC_W1_D12ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D13ACP_MASK   (0x38000U)
#define	XRDC2_MSC_MSAC_W1_D13ACP_SHIFT   (15U)
#define	XRDC2_MSC_MSAC_W1_D13ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D14ACP_MASK   (0x1C0000U)
#define	XRDC2_MSC_MSAC_W1_D14ACP_SHIFT   (18U)
#define	XRDC2_MSC_MSAC_W1_D14ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_D15ACP_MASK   (0xE00000U)
#define	XRDC2_MSC_MSAC_W1_D15ACP_SHIFT   (21U)
#define	XRDC2_MSC_MSAC_W1_D15ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK)
#define	XRDC2_MSC_MSAC_W1_EAL_MASK   (0x3000000U)
#define	XRDC2_MSC_MSAC_W1_EAL_SHIFT   (24U)
#define	XRDC2_MSC_MSAC_W1_EAL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK)
#define	XRDC2_MSC_MSAC_W1_DL2_MASK   (0x60000000U)
#define	XRDC2_MSC_MSAC_W1_DL2_SHIFT   (29U)
#define	XRDC2_MSC_MSAC_W1_DL2(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK)
#define	XRDC2_MSC_MSAC_W1_VLD_MASK   (0x80000000U)
#define	XRDC2_MSC_MSAC_W1_VLD_SHIFT   (31U)
#define	XRDC2_MSC_MSAC_W1_VLD(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_VLD_SHIFT)) & XRDC2_MSC_MSAC_W1_VLD_MASK)

MDAC_MDA_W0 - Master Domain Assignment
#define	XRDC2_MDAC_MDA_W0_MASK_MASK   (0xFFFFU)
#define	XRDC2_MDAC_MDA_W0_MASK_SHIFT   (0U)
#define	XRDC2_MDAC_MDA_W0_MASK(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK)
#define	XRDC2_MDAC_MDA_W0_MATCH_MASK   (0xFFFF0000U)
#define	XRDC2_MDAC_MDA_W0_MATCH_SHIFT   (16U)
#define	XRDC2_MDAC_MDA_W0_MATCH(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MATCH_SHIFT)) & XRDC2_MDAC_MDA_W0_MATCH_MASK)

MDAC_MDA_W1 - Master Domain Assignment
#define	XRDC2_MDAC_MDA_W1_DID_MASK   (0xF0000U)
#define	XRDC2_MDAC_MDA_W1_DID_SHIFT   (16U)
#define	XRDC2_MDAC_MDA_W1_DID(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK)
#define	XRDC2_MDAC_MDA_W1_PA_MASK   (0x3000000U)
#define	XRDC2_MDAC_MDA_W1_PA_SHIFT   (24U)
#define	XRDC2_MDAC_MDA_W1_PA(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK)
#define	XRDC2_MDAC_MDA_W1_SA_MASK   (0xC000000U)
#define	XRDC2_MDAC_MDA_W1_SA_SHIFT   (26U)
#define	XRDC2_MDAC_MDA_W1_SA(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK)
#define	XRDC2_MDAC_MDA_W1_DL_MASK   (0x40000000U)
#define	XRDC2_MDAC_MDA_W1_DL_SHIFT   (30U)
#define	XRDC2_MDAC_MDA_W1_DL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK)
#define	XRDC2_MDAC_MDA_W1_VLD_MASK   (0x80000000U)
#define	XRDC2_MDAC_MDA_W1_VLD_SHIFT   (31U)
#define	XRDC2_MDAC_MDA_W1_VLD(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_VLD_SHIFT)) & XRDC2_MDAC_MDA_W1_VLD_MASK)

PAC_PDAC_W0 - Peripheral Domain Access Control
#define	XRDC2_PAC_PDAC_W0_D0ACP_MASK   (0x7U)
#define	XRDC2_PAC_PDAC_W0_D0ACP_SHIFT   (0U)
#define	XRDC2_PAC_PDAC_W0_D0ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D1ACP_MASK   (0x38U)
#define	XRDC2_PAC_PDAC_W0_D1ACP_SHIFT   (3U)
#define	XRDC2_PAC_PDAC_W0_D1ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D2ACP_MASK   (0x1C0U)
#define	XRDC2_PAC_PDAC_W0_D2ACP_SHIFT   (6U)
#define	XRDC2_PAC_PDAC_W0_D2ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D3ACP_MASK   (0xE00U)
#define	XRDC2_PAC_PDAC_W0_D3ACP_SHIFT   (9U)
#define	XRDC2_PAC_PDAC_W0_D3ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D4ACP_MASK   (0x7000U)
#define	XRDC2_PAC_PDAC_W0_D4ACP_SHIFT   (12U)
#define	XRDC2_PAC_PDAC_W0_D4ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D5ACP_MASK   (0x38000U)
#define	XRDC2_PAC_PDAC_W0_D5ACP_SHIFT   (15U)
#define	XRDC2_PAC_PDAC_W0_D5ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D6ACP_MASK   (0x1C0000U)
#define	XRDC2_PAC_PDAC_W0_D6ACP_SHIFT   (18U)
#define	XRDC2_PAC_PDAC_W0_D6ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_D7ACP_MASK   (0xE00000U)
#define	XRDC2_PAC_PDAC_W0_D7ACP_SHIFT   (21U)
#define	XRDC2_PAC_PDAC_W0_D7ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK)
#define	XRDC2_PAC_PDAC_W0_EALO_MASK   (0xF000000U)
#define	XRDC2_PAC_PDAC_W0_EALO_SHIFT   (24U)
#define	XRDC2_PAC_PDAC_W0_EALO(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_EALO_SHIFT)) & XRDC2_PAC_PDAC_W0_EALO_MASK)

PAC_PDAC_W1 - Peripheral Domain Access Control
#define	XRDC2_PAC_PDAC_W1_D8ACP_MASK   (0x7U)
#define	XRDC2_PAC_PDAC_W1_D8ACP_SHIFT   (0U)
#define	XRDC2_PAC_PDAC_W1_D8ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D9ACP_MASK   (0x38U)
#define	XRDC2_PAC_PDAC_W1_D9ACP_SHIFT   (3U)
#define	XRDC2_PAC_PDAC_W1_D9ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D10ACP_MASK   (0x1C0U)
#define	XRDC2_PAC_PDAC_W1_D10ACP_SHIFT   (6U)
#define	XRDC2_PAC_PDAC_W1_D10ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D11ACP_MASK   (0xE00U)
#define	XRDC2_PAC_PDAC_W1_D11ACP_SHIFT   (9U)
#define	XRDC2_PAC_PDAC_W1_D11ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D12ACP_MASK   (0x7000U)
#define	XRDC2_PAC_PDAC_W1_D12ACP_SHIFT   (12U)
#define	XRDC2_PAC_PDAC_W1_D12ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D13ACP_MASK   (0x38000U)
#define	XRDC2_PAC_PDAC_W1_D13ACP_SHIFT   (15U)
#define	XRDC2_PAC_PDAC_W1_D13ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D14ACP_MASK   (0x1C0000U)
#define	XRDC2_PAC_PDAC_W1_D14ACP_SHIFT   (18U)
#define	XRDC2_PAC_PDAC_W1_D14ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_D15ACP_MASK   (0xE00000U)
#define	XRDC2_PAC_PDAC_W1_D15ACP_SHIFT   (21U)
#define	XRDC2_PAC_PDAC_W1_D15ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK)
#define	XRDC2_PAC_PDAC_W1_EAL_MASK   (0x3000000U)
#define	XRDC2_PAC_PDAC_W1_EAL_SHIFT   (24U)
#define	XRDC2_PAC_PDAC_W1_EAL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK)
#define	XRDC2_PAC_PDAC_W1_DL2_MASK   (0x60000000U)
#define	XRDC2_PAC_PDAC_W1_DL2_SHIFT   (29U)
#define	XRDC2_PAC_PDAC_W1_DL2(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK)
#define	XRDC2_PAC_PDAC_W1_VLD_MASK   (0x80000000U)
#define	XRDC2_PAC_PDAC_W1_VLD_SHIFT   (31U)
#define	XRDC2_PAC_PDAC_W1_VLD(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_VLD_SHIFT)) & XRDC2_PAC_PDAC_W1_VLD_MASK)

MRC_MRGD_W0 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W0_SRTADDR_MASK   (0xFFFFF000U)
#define	XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W0_SRTADDR(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W0_SRTADDR_MASK)

MRC_MRGD_W1 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W1_SRTADDR_MASK   (0xFU)
#define	XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W1_SRTADDR(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W1_SRTADDR_MASK)

MRC_MRGD_W2 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W2_ENDADDR_MASK   (0xFFFFF000U)
#define	XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W2_ENDADDR(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W2_ENDADDR_MASK)

MRC_MRGD_W3 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W3_ENDADDR_MASK   (0xFU)
#define	XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W3_ENDADDR(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W3_ENDADDR_MASK)

MRC_MRGD_W5 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W5_D0ACP_MASK   (0x7U)
#define	XRDC2_MRC_MRGD_W5_D0ACP_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W5_D0ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D1ACP_MASK   (0x38U)
#define	XRDC2_MRC_MRGD_W5_D1ACP_SHIFT   (3U)
#define	XRDC2_MRC_MRGD_W5_D1ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D2ACP_MASK   (0x1C0U)
#define	XRDC2_MRC_MRGD_W5_D2ACP_SHIFT   (6U)
#define	XRDC2_MRC_MRGD_W5_D2ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D3ACP_MASK   (0xE00U)
#define	XRDC2_MRC_MRGD_W5_D3ACP_SHIFT   (9U)
#define	XRDC2_MRC_MRGD_W5_D3ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D4ACP_MASK   (0x7000U)
#define	XRDC2_MRC_MRGD_W5_D4ACP_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W5_D4ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D5ACP_MASK   (0x38000U)
#define	XRDC2_MRC_MRGD_W5_D5ACP_SHIFT   (15U)
#define	XRDC2_MRC_MRGD_W5_D5ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D6ACP_MASK   (0x1C0000U)
#define	XRDC2_MRC_MRGD_W5_D6ACP_SHIFT   (18U)
#define	XRDC2_MRC_MRGD_W5_D6ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_D7ACP_MASK   (0xE00000U)
#define	XRDC2_MRC_MRGD_W5_D7ACP_SHIFT   (21U)
#define	XRDC2_MRC_MRGD_W5_D7ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK)
#define	XRDC2_MRC_MRGD_W5_EALO_MASK   (0xF000000U)
#define	XRDC2_MRC_MRGD_W5_EALO_SHIFT   (24U)
#define	XRDC2_MRC_MRGD_W5_EALO(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_EALO_SHIFT)) & XRDC2_MRC_MRGD_W5_EALO_MASK)

MRC_MRGD_W6 - Memory Region Descriptor
#define	XRDC2_MRC_MRGD_W6_D8ACP_MASK   (0x7U)
#define	XRDC2_MRC_MRGD_W6_D8ACP_SHIFT   (0U)
#define	XRDC2_MRC_MRGD_W6_D8ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D9ACP_MASK   (0x38U)
#define	XRDC2_MRC_MRGD_W6_D9ACP_SHIFT   (3U)
#define	XRDC2_MRC_MRGD_W6_D9ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D10ACP_MASK   (0x1C0U)
#define	XRDC2_MRC_MRGD_W6_D10ACP_SHIFT   (6U)
#define	XRDC2_MRC_MRGD_W6_D10ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D11ACP_MASK   (0xE00U)
#define	XRDC2_MRC_MRGD_W6_D11ACP_SHIFT   (9U)
#define	XRDC2_MRC_MRGD_W6_D11ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D12ACP_MASK   (0x7000U)
#define	XRDC2_MRC_MRGD_W6_D12ACP_SHIFT   (12U)
#define	XRDC2_MRC_MRGD_W6_D12ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D13ACP_MASK   (0x38000U)
#define	XRDC2_MRC_MRGD_W6_D13ACP_SHIFT   (15U)
#define	XRDC2_MRC_MRGD_W6_D13ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D14ACP_MASK   (0x1C0000U)
#define	XRDC2_MRC_MRGD_W6_D14ACP_SHIFT   (18U)
#define	XRDC2_MRC_MRGD_W6_D14ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_D15ACP_MASK   (0xE00000U)
#define	XRDC2_MRC_MRGD_W6_D15ACP_SHIFT   (21U)
#define	XRDC2_MRC_MRGD_W6_D15ACP(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK)
#define	XRDC2_MRC_MRGD_W6_EAL_MASK   (0x3000000U)
#define	XRDC2_MRC_MRGD_W6_EAL_SHIFT   (24U)
#define	XRDC2_MRC_MRGD_W6_EAL(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK)
#define	XRDC2_MRC_MRGD_W6_DL2_MASK   (0x60000000U)
#define	XRDC2_MRC_MRGD_W6_DL2_SHIFT   (29U)
#define	XRDC2_MRC_MRGD_W6_DL2(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK)
#define	XRDC2_MRC_MRGD_W6_VLD_MASK   (0x80000000U)
#define	XRDC2_MRC_MRGD_W6_VLD_SHIFT   (31U)
#define	XRDC2_MRC_MRGD_W6_VLD(x)   (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_VLD_SHIFT)) & XRDC2_MRC_MRGD_W6_VLD_MASK)

Detailed Description

Macro Definition Documentation

XRDC2_MCR_GCL [1/2]

#define XRDC2_MCR_GCL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK)

GCL - Global Configuration Lock 0b00..Lock disabled, registers can be written by any domain. 0b01..Lock disabled until the next reset, registers can be written by any domain. 0b10..Lock enabled, only the global configuration lock owner (SR[GCLO]) can write to registers. 0b11..Lock enabled, all registers are read only until the next reset.

XRDC2_MCR_GCL [2/2]

#define XRDC2_MCR_GCL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK)

GCL - Global Configuration Lock 0b00..Lock disabled, registers can be written by any domain. 0b01..Lock disabled until the next reset, registers can be written by any domain. 0b10..Lock enabled, only the global configuration lock owner (SR[GCLO]) can write to registers. 0b11..Lock enabled, all registers are read only until the next reset.

XRDC2_MCR_GVLDC [1/2]

#define XRDC2_MCR_GVLDC

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK)

GVLDC - Global Valid Access Control 0b0..Access controls are disabled, XRDC2 allows all transactions. 0b1..Access controls are enabled.

XRDC2_MCR_GVLDC [2/2]

#define XRDC2_MCR_GVLDC

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK)

GVLDC - Global Valid Access Control 0b0..Access controls are disabled, XRDC2 allows all transactions. 0b1..Access controls are enabled.

XRDC2_MCR_GVLDM [1/2]

#define XRDC2_MCR_GVLDM

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK)

GVLDM - Global Valid MDAC 0b0..MDACs are disabled. 0b1..MDACs are enabled.

XRDC2_MCR_GVLDM [2/2]

#define XRDC2_MCR_GVLDM

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK)

GVLDM - Global Valid MDAC 0b0..MDACs are disabled. 0b1..MDACs are enabled.

XRDC2_MDAC_MDA_W0_MASK [1/2]

#define XRDC2_MDAC_MDA_W0_MASK

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK)

MASK - Mask

XRDC2_MDAC_MDA_W0_MASK [2/2]

#define XRDC2_MDAC_MDA_W0_MASK

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK)

MASK - Mask

XRDC2_MDAC_MDA_W0_MATCH [1/2]

#define XRDC2_MDAC_MDA_W0_MATCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MATCH_SHIFT)) & XRDC2_MDAC_MDA_W0_MATCH_MASK)

MATCH - Match

XRDC2_MDAC_MDA_W0_MATCH [2/2]

#define XRDC2_MDAC_MDA_W0_MATCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MATCH_SHIFT)) & XRDC2_MDAC_MDA_W0_MATCH_MASK)

MATCH - Match

XRDC2_MDAC_MDA_W1_DID [1/2]

#define XRDC2_MDAC_MDA_W1_DID

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK)

DID - Domain Identifier

XRDC2_MDAC_MDA_W1_DID [2/2]

#define XRDC2_MDAC_MDA_W1_DID

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK)

DID - Domain Identifier

XRDC2_MDAC_MDA_W1_DL [1/2]

#define XRDC2_MDAC_MDA_W1_DL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK)

DL - Descriptor Lock 0b0..Lock disabled, registers can be written. 0b1..Lock enabled, registers are read-only until the next reset.

XRDC2_MDAC_MDA_W1_DL [2/2]

#define XRDC2_MDAC_MDA_W1_DL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK)

DL - Descriptor Lock 0b0..Lock disabled, registers can be written. 0b1..Lock enabled, registers are read-only until the next reset.

XRDC2_MDAC_MDA_W1_PA [1/2]

#define XRDC2_MDAC_MDA_W1_PA

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK)

PA - Privileged attribute 0b00..Use the bus master's privileged/user attribute directly. 0b01..Use the bus master's privileged/user attribute directly. 0b10..Force the bus attribute for this master to user. 0b11..Force the bus attribute for this master to privileged.

XRDC2_MDAC_MDA_W1_PA [2/2]

#define XRDC2_MDAC_MDA_W1_PA

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK)

PA - Privileged attribute 0b00..Use the bus master's privileged/user attribute directly. 0b01..Use the bus master's privileged/user attribute directly. 0b10..Force the bus attribute for this master to user. 0b11..Force the bus attribute for this master to privileged.

XRDC2_MDAC_MDA_W1_SA [1/2]

#define XRDC2_MDAC_MDA_W1_SA

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK)

SA - Secure attribute 0b00..Use the bus master's secure/nonsecure attribute directly. 0b01..Use the bus master's secure/nonsecure attribute directly. 0b10..Force the bus attribute for this master to secure. 0b11..Force the bus attribute for this master to nonsecure.

XRDC2_MDAC_MDA_W1_SA [2/2]

#define XRDC2_MDAC_MDA_W1_SA

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK)

SA - Secure attribute 0b00..Use the bus master's secure/nonsecure attribute directly. 0b01..Use the bus master's secure/nonsecure attribute directly. 0b10..Force the bus attribute for this master to secure. 0b11..Force the bus attribute for this master to nonsecure.

XRDC2_MDAC_MDA_W1_VLD [1/2]

#define XRDC2_MDAC_MDA_W1_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_VLD_SHIFT)) & XRDC2_MDAC_MDA_W1_VLD_MASK)

VLD - Valid 0b0..The MDA is invalid. 0b1..The MDA is valid.

XRDC2_MDAC_MDA_W1_VLD [2/2]

#define XRDC2_MDAC_MDA_W1_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_VLD_SHIFT)) & XRDC2_MDAC_MDA_W1_VLD_MASK)

VLD - Valid 0b0..The MDA is invalid. 0b1..The MDA is valid.

XRDC2_MRC_MRGD_W0_SRTADDR [1/2]

#define XRDC2_MRC_MRGD_W0_SRTADDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W0_SRTADDR_MASK)

SRTADDR - Start Address

XRDC2_MRC_MRGD_W0_SRTADDR [2/2]

#define XRDC2_MRC_MRGD_W0_SRTADDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W0_SRTADDR_MASK)

SRTADDR - Start Address

XRDC2_MRC_MRGD_W1_SRTADDR [1/2]

#define XRDC2_MRC_MRGD_W1_SRTADDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W1_SRTADDR_MASK)

SRTADDR - Start Address

XRDC2_MRC_MRGD_W1_SRTADDR [2/2]

#define XRDC2_MRC_MRGD_W1_SRTADDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W1_SRTADDR_MASK)

SRTADDR - Start Address

XRDC2_MRC_MRGD_W2_ENDADDR [1/2]

#define XRDC2_MRC_MRGD_W2_ENDADDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W2_ENDADDR_MASK)

ENDADDR - End Address

XRDC2_MRC_MRGD_W2_ENDADDR [2/2]

#define XRDC2_MRC_MRGD_W2_ENDADDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W2_ENDADDR_MASK)

ENDADDR - End Address

XRDC2_MRC_MRGD_W3_ENDADDR [1/2]

#define XRDC2_MRC_MRGD_W3_ENDADDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W3_ENDADDR_MASK)

ENDADDR - End Address

XRDC2_MRC_MRGD_W3_ENDADDR [2/2]

#define XRDC2_MRC_MRGD_W3_ENDADDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W3_ENDADDR_MASK)

ENDADDR - End Address

XRDC2_MRC_MRGD_W5_D0ACP [1/2]

#define XRDC2_MRC_MRGD_W5_D0ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK)

D0ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D0ACP [2/2]

#define XRDC2_MRC_MRGD_W5_D0ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK)

D0ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D1ACP [1/2]

#define XRDC2_MRC_MRGD_W5_D1ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK)

D1ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D1ACP [2/2]

#define XRDC2_MRC_MRGD_W5_D1ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK)

D1ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D2ACP [1/2]

#define XRDC2_MRC_MRGD_W5_D2ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK)

D2ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D2ACP [2/2]

#define XRDC2_MRC_MRGD_W5_D2ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK)

D2ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D3ACP [1/2]

#define XRDC2_MRC_MRGD_W5_D3ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK)

D3ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D3ACP [2/2]

#define XRDC2_MRC_MRGD_W5_D3ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK)

D3ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D4ACP [1/2]

#define XRDC2_MRC_MRGD_W5_D4ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK)

D4ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D4ACP [2/2]

#define XRDC2_MRC_MRGD_W5_D4ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK)

D4ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D5ACP [1/2]

#define XRDC2_MRC_MRGD_W5_D5ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK)

D5ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D5ACP [2/2]

#define XRDC2_MRC_MRGD_W5_D5ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK)

D5ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D6ACP [1/2]

#define XRDC2_MRC_MRGD_W5_D6ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK)

D6ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D6ACP [2/2]

#define XRDC2_MRC_MRGD_W5_D6ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK)

D6ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D7ACP [1/2]

#define XRDC2_MRC_MRGD_W5_D7ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK)

D7ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_D7ACP [2/2]

#define XRDC2_MRC_MRGD_W5_D7ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK)

D7ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W5_EALO [1/2]

#define XRDC2_MRC_MRGD_W5_EALO

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_EALO_SHIFT)) & XRDC2_MRC_MRGD_W5_EALO_MASK)

EALO - Exclusive Access Lock Owner

XRDC2_MRC_MRGD_W5_EALO [2/2]

#define XRDC2_MRC_MRGD_W5_EALO

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_EALO_SHIFT)) & XRDC2_MRC_MRGD_W5_EALO_MASK)

EALO - Exclusive Access Lock Owner

XRDC2_MRC_MRGD_W6_D10ACP [1/2]

#define XRDC2_MRC_MRGD_W6_D10ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK)

D10ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D10ACP [2/2]

#define XRDC2_MRC_MRGD_W6_D10ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK)

D10ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D11ACP [1/2]

#define XRDC2_MRC_MRGD_W6_D11ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK)

D11ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D11ACP [2/2]

#define XRDC2_MRC_MRGD_W6_D11ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK)

D11ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D12ACP [1/2]

#define XRDC2_MRC_MRGD_W6_D12ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK)

D12ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D12ACP [2/2]

#define XRDC2_MRC_MRGD_W6_D12ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK)

D12ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D13ACP [1/2]

#define XRDC2_MRC_MRGD_W6_D13ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK)

D13ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D13ACP [2/2]

#define XRDC2_MRC_MRGD_W6_D13ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK)

D13ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D14ACP [1/2]

#define XRDC2_MRC_MRGD_W6_D14ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK)

D14ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D14ACP [2/2]

#define XRDC2_MRC_MRGD_W6_D14ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK)

D14ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D15ACP [1/2]

#define XRDC2_MRC_MRGD_W6_D15ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK)

D15ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D15ACP [2/2]

#define XRDC2_MRC_MRGD_W6_D15ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK)

D15ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D8ACP [1/2]

#define XRDC2_MRC_MRGD_W6_D8ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK)

D8ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D8ACP [2/2]

#define XRDC2_MRC_MRGD_W6_D8ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK)

D8ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D9ACP [1/2]

#define XRDC2_MRC_MRGD_W6_D9ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK)

D9ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_D9ACP [2/2]

#define XRDC2_MRC_MRGD_W6_D9ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK)

D9ACP - Domain "x" access control policy

XRDC2_MRC_MRGD_W6_DL2 [1/2]

#define XRDC2_MRC_MRGD_W6_DL2

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK)

DL2 - Descriptor Lock 0b00..Lock disabled, descriptor registers can be written. 0b01..Lock disabled until the next reset, descriptor registers can be written. 0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written. 0b11..Lock enabled, descriptor registers are read-only until the next reset.

XRDC2_MRC_MRGD_W6_DL2 [2/2]

#define XRDC2_MRC_MRGD_W6_DL2

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK)

DL2 - Descriptor Lock 0b00..Lock disabled, descriptor registers can be written. 0b01..Lock disabled until the next reset, descriptor registers can be written. 0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written. 0b11..Lock enabled, descriptor registers are read-only until the next reset.

XRDC2_MRC_MRGD_W6_EAL [1/2]

#define XRDC2_MRC_MRGD_W6_EAL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK)

EAL - Exclusive Access Lock 0b00..Lock disabled. 0b01..Lock disabled until next reset. 0b10..Lock enabled, lock state = available. 0b11..Lock enabled, lock state = not available.

XRDC2_MRC_MRGD_W6_EAL [2/2]

#define XRDC2_MRC_MRGD_W6_EAL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK)

EAL - Exclusive Access Lock 0b00..Lock disabled. 0b01..Lock disabled until next reset. 0b10..Lock enabled, lock state = available. 0b11..Lock enabled, lock state = not available.

XRDC2_MRC_MRGD_W6_VLD [1/2]

#define XRDC2_MRC_MRGD_W6_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_VLD_SHIFT)) & XRDC2_MRC_MRGD_W6_VLD_MASK)

VLD - Valid 0b0..The MRGD is invalid. 0b1..The MRGD is valid.

XRDC2_MRC_MRGD_W6_VLD [2/2]

#define XRDC2_MRC_MRGD_W6_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_VLD_SHIFT)) & XRDC2_MRC_MRGD_W6_VLD_MASK)

VLD - Valid 0b0..The MRGD is invalid. 0b1..The MRGD is valid.

XRDC2_MSC_MSAC_W0_D0ACP [1/2]

#define XRDC2_MSC_MSAC_W0_D0ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK)

D0ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D0ACP [2/2]

#define XRDC2_MSC_MSAC_W0_D0ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK)

D0ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D1ACP [1/2]

#define XRDC2_MSC_MSAC_W0_D1ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK)

D1ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D1ACP [2/2]

#define XRDC2_MSC_MSAC_W0_D1ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK)

D1ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D2ACP [1/2]

#define XRDC2_MSC_MSAC_W0_D2ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK)

D2ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D2ACP [2/2]

#define XRDC2_MSC_MSAC_W0_D2ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK)

D2ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D3ACP [1/2]

#define XRDC2_MSC_MSAC_W0_D3ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK)

D3ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D3ACP [2/2]

#define XRDC2_MSC_MSAC_W0_D3ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK)

D3ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D4ACP [1/2]

#define XRDC2_MSC_MSAC_W0_D4ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK)

D4ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D4ACP [2/2]

#define XRDC2_MSC_MSAC_W0_D4ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK)

D4ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D5ACP [1/2]

#define XRDC2_MSC_MSAC_W0_D5ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK)

D5ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D5ACP [2/2]

#define XRDC2_MSC_MSAC_W0_D5ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK)

D5ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D6ACP [1/2]

#define XRDC2_MSC_MSAC_W0_D6ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK)

D6ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D6ACP [2/2]

#define XRDC2_MSC_MSAC_W0_D6ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK)

D6ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D7ACP [1/2]

#define XRDC2_MSC_MSAC_W0_D7ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK)

D7ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_D7ACP [2/2]

#define XRDC2_MSC_MSAC_W0_D7ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK)

D7ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W0_EALO [1/2]

#define XRDC2_MSC_MSAC_W0_EALO

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_EALO_SHIFT)) & XRDC2_MSC_MSAC_W0_EALO_MASK)

EALO - Exclusive Access Lock Owner

XRDC2_MSC_MSAC_W0_EALO [2/2]

#define XRDC2_MSC_MSAC_W0_EALO

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_EALO_SHIFT)) & XRDC2_MSC_MSAC_W0_EALO_MASK)

EALO - Exclusive Access Lock Owner

XRDC2_MSC_MSAC_W1_D10ACP [1/2]

#define XRDC2_MSC_MSAC_W1_D10ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK)

D10ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D10ACP [2/2]

#define XRDC2_MSC_MSAC_W1_D10ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK)

D10ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D11ACP [1/2]

#define XRDC2_MSC_MSAC_W1_D11ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK)

D11ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D11ACP [2/2]

#define XRDC2_MSC_MSAC_W1_D11ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK)

D11ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D12ACP [1/2]

#define XRDC2_MSC_MSAC_W1_D12ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK)

D12ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D12ACP [2/2]

#define XRDC2_MSC_MSAC_W1_D12ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK)

D12ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D13ACP [1/2]

#define XRDC2_MSC_MSAC_W1_D13ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK)

D13ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D13ACP [2/2]

#define XRDC2_MSC_MSAC_W1_D13ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK)

D13ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D14ACP [1/2]

#define XRDC2_MSC_MSAC_W1_D14ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK)

D14ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D14ACP [2/2]

#define XRDC2_MSC_MSAC_W1_D14ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK)

D14ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D15ACP [1/2]

#define XRDC2_MSC_MSAC_W1_D15ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK)

D15ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D15ACP [2/2]

#define XRDC2_MSC_MSAC_W1_D15ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK)

D15ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D8ACP [1/2]

#define XRDC2_MSC_MSAC_W1_D8ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK)

D8ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D8ACP [2/2]

#define XRDC2_MSC_MSAC_W1_D8ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK)

D8ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D9ACP [1/2]

#define XRDC2_MSC_MSAC_W1_D9ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK)

D9ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_D9ACP [2/2]

#define XRDC2_MSC_MSAC_W1_D9ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK)

D9ACP - Domain "x" access control policy

XRDC2_MSC_MSAC_W1_DL2 [1/2]

#define XRDC2_MSC_MSAC_W1_DL2

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK)

DL2 - Descriptor Lock 0b00..Lock disabled, descriptor registers can be written. 0b01..Lock disabled until the next reset, descriptor registers can be written. 0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written. 0b11..Lock enabled, descriptor registers are read-only until the next reset.

XRDC2_MSC_MSAC_W1_DL2 [2/2]

#define XRDC2_MSC_MSAC_W1_DL2

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK)

DL2 - Descriptor Lock 0b00..Lock disabled, descriptor registers can be written. 0b01..Lock disabled until the next reset, descriptor registers can be written. 0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written. 0b11..Lock enabled, descriptor registers are read-only until the next reset.

XRDC2_MSC_MSAC_W1_EAL [1/2]

#define XRDC2_MSC_MSAC_W1_EAL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK)

EAL - Exclusive Access Lock 0b00..Lock disabled. 0b01..Lock disabled until next reset. 0b10..Lock enabled, lock state = available. 0b11..Lock enabled, lock state = not available.

XRDC2_MSC_MSAC_W1_EAL [2/2]

#define XRDC2_MSC_MSAC_W1_EAL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK)

EAL - Exclusive Access Lock 0b00..Lock disabled. 0b01..Lock disabled until next reset. 0b10..Lock enabled, lock state = available. 0b11..Lock enabled, lock state = not available.

XRDC2_MSC_MSAC_W1_VLD [1/2]

#define XRDC2_MSC_MSAC_W1_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_VLD_SHIFT)) & XRDC2_MSC_MSAC_W1_VLD_MASK)

VLD - Valid 0b0..The MSAC assignment is invalid. 0b1..The MSAC assignment is valid.

XRDC2_MSC_MSAC_W1_VLD [2/2]

#define XRDC2_MSC_MSAC_W1_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_VLD_SHIFT)) & XRDC2_MSC_MSAC_W1_VLD_MASK)

VLD - Valid 0b0..The MSAC assignment is invalid. 0b1..The MSAC assignment is valid.

XRDC2_PAC_PDAC_W0_D0ACP [1/2]

#define XRDC2_PAC_PDAC_W0_D0ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK)

D0ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D0ACP [2/2]

#define XRDC2_PAC_PDAC_W0_D0ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK)

D0ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D1ACP [1/2]

#define XRDC2_PAC_PDAC_W0_D1ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK)

D1ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D1ACP [2/2]

#define XRDC2_PAC_PDAC_W0_D1ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK)

D1ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D2ACP [1/2]

#define XRDC2_PAC_PDAC_W0_D2ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK)

D2ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D2ACP [2/2]

#define XRDC2_PAC_PDAC_W0_D2ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK)

D2ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D3ACP [1/2]

#define XRDC2_PAC_PDAC_W0_D3ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK)

D3ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D3ACP [2/2]

#define XRDC2_PAC_PDAC_W0_D3ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK)

D3ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D4ACP [1/2]

#define XRDC2_PAC_PDAC_W0_D4ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK)

D4ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D4ACP [2/2]

#define XRDC2_PAC_PDAC_W0_D4ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK)

D4ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D5ACP [1/2]

#define XRDC2_PAC_PDAC_W0_D5ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK)

D5ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D5ACP [2/2]

#define XRDC2_PAC_PDAC_W0_D5ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK)

D5ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D6ACP [1/2]

#define XRDC2_PAC_PDAC_W0_D6ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK)

D6ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D6ACP [2/2]

#define XRDC2_PAC_PDAC_W0_D6ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK)

D6ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D7ACP [1/2]

#define XRDC2_PAC_PDAC_W0_D7ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK)

D7ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_D7ACP [2/2]

#define XRDC2_PAC_PDAC_W0_D7ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK)

D7ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W0_EALO [1/2]

#define XRDC2_PAC_PDAC_W0_EALO

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_EALO_SHIFT)) & XRDC2_PAC_PDAC_W0_EALO_MASK)

EALO - Exclusive Access Lock Owner

XRDC2_PAC_PDAC_W0_EALO [2/2]

#define XRDC2_PAC_PDAC_W0_EALO

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_EALO_SHIFT)) & XRDC2_PAC_PDAC_W0_EALO_MASK)

EALO - Exclusive Access Lock Owner

XRDC2_PAC_PDAC_W1_D10ACP [1/2]

#define XRDC2_PAC_PDAC_W1_D10ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK)

D10ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D10ACP [2/2]

#define XRDC2_PAC_PDAC_W1_D10ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK)

D10ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D11ACP [1/2]

#define XRDC2_PAC_PDAC_W1_D11ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK)

D11ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D11ACP [2/2]

#define XRDC2_PAC_PDAC_W1_D11ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK)

D11ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D12ACP [1/2]

#define XRDC2_PAC_PDAC_W1_D12ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK)

D12ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D12ACP [2/2]

#define XRDC2_PAC_PDAC_W1_D12ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK)

D12ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D13ACP [1/2]

#define XRDC2_PAC_PDAC_W1_D13ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK)

D13ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D13ACP [2/2]

#define XRDC2_PAC_PDAC_W1_D13ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK)

D13ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D14ACP [1/2]

#define XRDC2_PAC_PDAC_W1_D14ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK)

D14ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D14ACP [2/2]

#define XRDC2_PAC_PDAC_W1_D14ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK)

D14ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D15ACP [1/2]

#define XRDC2_PAC_PDAC_W1_D15ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK)

D15ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D15ACP [2/2]

#define XRDC2_PAC_PDAC_W1_D15ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK)

D15ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D8ACP [1/2]

#define XRDC2_PAC_PDAC_W1_D8ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK)

D8ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D8ACP [2/2]

#define XRDC2_PAC_PDAC_W1_D8ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK)

D8ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D9ACP [1/2]

#define XRDC2_PAC_PDAC_W1_D9ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK)

D9ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_D9ACP [2/2]

#define XRDC2_PAC_PDAC_W1_D9ACP

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK)

D9ACP - Domain "x" access control policy

XRDC2_PAC_PDAC_W1_DL2 [1/2]

#define XRDC2_PAC_PDAC_W1_DL2

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK)

DL2 - Descriptor Lock 0b00..Lock disabled, descriptor registers can be written.. 0b01..Lock disabled until the next reset, descriptor registers can be written.. 0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written.. 0b11..Lock enabled, descriptor registers are read-only until the next reset.

XRDC2_PAC_PDAC_W1_DL2 [2/2]

#define XRDC2_PAC_PDAC_W1_DL2

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK)

DL2 - Descriptor Lock 0b00..Lock disabled, descriptor registers can be written.. 0b01..Lock disabled until the next reset, descriptor registers can be written.. 0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written.. 0b11..Lock enabled, descriptor registers are read-only until the next reset.

XRDC2_PAC_PDAC_W1_EAL [1/2]

#define XRDC2_PAC_PDAC_W1_EAL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK)

EAL - Exclusive Access Lock 0b00..Lock disabled. 0b01..Lock disabled until next reset. 0b10..Lock enabled, lock state = available. 0b11..Lock enabled, lock state = not available.

XRDC2_PAC_PDAC_W1_EAL [2/2]

#define XRDC2_PAC_PDAC_W1_EAL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK)

EAL - Exclusive Access Lock 0b00..Lock disabled. 0b01..Lock disabled until next reset. 0b10..Lock enabled, lock state = available. 0b11..Lock enabled, lock state = not available.

XRDC2_PAC_PDAC_W1_VLD [1/2]

#define XRDC2_PAC_PDAC_W1_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_VLD_SHIFT)) & XRDC2_PAC_PDAC_W1_VLD_MASK)

VLD - Valid 0b0..The PDAC assignment is invalid. 0b1..The PDAC assignment is valid.

XRDC2_PAC_PDAC_W1_VLD [2/2]

#define XRDC2_PAC_PDAC_W1_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_VLD_SHIFT)) & XRDC2_PAC_PDAC_W1_VLD_MASK)

VLD - Valid 0b0..The PDAC assignment is invalid. 0b1..The PDAC assignment is valid.

XRDC2_SR_DIN [1/2]

#define XRDC2_SR_DIN

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)

DIN - Domain Identifier Number

XRDC2_SR_DIN [2/2]

#define XRDC2_SR_DIN

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)

DIN - Domain Identifier Number

XRDC2_SR_GCLO [1/2]

#define XRDC2_SR_GCLO

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)

GCLO - Global Configuration Lock Owner

XRDC2_SR_GCLO [2/2]

#define XRDC2_SR_GCLO

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)

GCLO - Global Configuration Lock Owner

XRDC2_SR_HRL [1/2]

#define XRDC2_SR_HRL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)

HRL - Hardware Revision Level

XRDC2_SR_HRL [2/2]

#define XRDC2_SR_HRL

(

x

)

(((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)

HRL - Hardware Revision Level