FLEXIO Register Masks

Macros
#define	FLEXIO_SHIFTCTL_COUNT   (4U)
#define	FLEXIO_SHIFTCFG_COUNT   (4U)
#define	FLEXIO_SHIFTBUF_COUNT   (4U)
#define	FLEXIO_SHIFTBUFBIS_COUNT   (4U)
#define	FLEXIO_SHIFTBUFBYS_COUNT   (4U)
#define	FLEXIO_SHIFTBUFBBS_COUNT   (4U)
#define	FLEXIO_TIMCTL_COUNT   (4U)
#define	FLEXIO_TIMCFG_COUNT   (4U)
#define	FLEXIO_TIMCMP_COUNT   (4U)
#define	FLEXIO_SHIFTBUFNBS_COUNT   (4U)
#define	FLEXIO_SHIFTBUFHWS_COUNT   (4U)
#define	FLEXIO_SHIFTBUFNIS_COUNT   (4U)
#define	FLEXIO_SHIFTCTL_COUNT   (8U)
#define	FLEXIO_SHIFTCFG_COUNT   (8U)
#define	FLEXIO_SHIFTBUF_COUNT   (8U)
#define	FLEXIO_SHIFTBUFBIS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFBYS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFBBS_COUNT   (8U)
#define	FLEXIO_TIMCTL_COUNT   (8U)
#define	FLEXIO_TIMCFG_COUNT   (8U)
#define	FLEXIO_TIMCMP_COUNT   (8U)
#define	FLEXIO_SHIFTBUFNBS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFHWS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFNIS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFOES_COUNT   (8U)
#define	FLEXIO_SHIFTBUFEOS_COUNT   (8U)
#define	FLEXIO_SHIFTCTL_COUNT   (8U)
#define	FLEXIO_SHIFTCFG_COUNT   (8U)
#define	FLEXIO_SHIFTBUF_COUNT   (8U)
#define	FLEXIO_SHIFTBUFBIS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFBYS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFBBS_COUNT   (8U)
#define	FLEXIO_TIMCTL_COUNT   (8U)
#define	FLEXIO_TIMCFG_COUNT   (8U)
#define	FLEXIO_TIMCMP_COUNT   (8U)
#define	FLEXIO_SHIFTBUFNBS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFHWS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFNIS_COUNT   (8U)
#define	FLEXIO_SHIFTBUFOES_COUNT   (8U)
#define	FLEXIO_SHIFTBUFEOS_COUNT   (8U)

VERID - Version ID Register
#define	FLEXIO_VERID_FEATURE_MASK   (0xFFFFU)
#define	FLEXIO_VERID_FEATURE_SHIFT   (0U)
#define	FLEXIO_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
#define	FLEXIO_VERID_MINOR_MASK   (0xFF0000U)
#define	FLEXIO_VERID_MINOR_SHIFT   (16U)
#define	FLEXIO_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
#define	FLEXIO_VERID_MAJOR_MASK   (0xFF000000U)
#define	FLEXIO_VERID_MAJOR_SHIFT   (24U)
#define	FLEXIO_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
#define	I2S_VERID_FEATURE_MASK   (0xFFFFU)
#define	I2S_VERID_FEATURE_SHIFT   (0U)
#define	I2S_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
#define	I2S_VERID_MINOR_MASK   (0xFF0000U)
#define	I2S_VERID_MINOR_SHIFT   (16U)
#define	I2S_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
#define	I2S_VERID_MAJOR_MASK   (0xFF000000U)
#define	I2S_VERID_MAJOR_SHIFT   (24U)
#define	I2S_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
#define	LPI2C_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPI2C_VERID_FEATURE_SHIFT   (0U)
#define	LPI2C_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
#define	LPI2C_VERID_MINOR_MASK   (0xFF0000U)
#define	LPI2C_VERID_MINOR_SHIFT   (16U)
#define	LPI2C_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
#define	LPI2C_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPI2C_VERID_MAJOR_SHIFT   (24U)
#define	LPI2C_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
#define	LPSPI_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPSPI_VERID_FEATURE_SHIFT   (0U)
#define	LPSPI_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
#define	LPSPI_VERID_MINOR_MASK   (0xFF0000U)
#define	LPSPI_VERID_MINOR_SHIFT   (16U)
#define	LPSPI_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
#define	LPSPI_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPSPI_VERID_MAJOR_SHIFT   (24U)
#define	LPSPI_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
#define	LPUART_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPUART_VERID_FEATURE_SHIFT   (0U)
#define	LPUART_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
#define	LPUART_VERID_MINOR_MASK   (0xFF0000U)
#define	LPUART_VERID_MINOR_SHIFT   (16U)
#define	LPUART_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
#define	LPUART_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPUART_VERID_MAJOR_SHIFT   (24U)
#define	LPUART_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	FLEXIO_PARAM_SHIFTER_MASK   (0xFFU)
#define	FLEXIO_PARAM_SHIFTER_SHIFT   (0U)
#define	FLEXIO_PARAM_SHIFTER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
#define	FLEXIO_PARAM_TIMER_MASK   (0xFF00U)
#define	FLEXIO_PARAM_TIMER_SHIFT   (8U)
#define	FLEXIO_PARAM_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
#define	FLEXIO_PARAM_PIN_MASK   (0xFF0000U)
#define	FLEXIO_PARAM_PIN_SHIFT   (16U)
#define	FLEXIO_PARAM_PIN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
#define	FLEXIO_PARAM_TRIGGER_MASK   (0xFF000000U)
#define	FLEXIO_PARAM_TRIGGER_SHIFT   (24U)
#define	FLEXIO_PARAM_TRIGGER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
#define	I2S_PARAM_DATALINE_MASK   (0xFU)
#define	I2S_PARAM_DATALINE_SHIFT   (0U)
#define	I2S_PARAM_DATALINE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
#define	I2S_PARAM_FIFO_MASK   (0xF00U)
#define	I2S_PARAM_FIFO_SHIFT   (8U)
#define	I2S_PARAM_FIFO(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
#define	I2S_PARAM_FRAME_MASK   (0xF0000U)
#define	I2S_PARAM_FRAME_SHIFT   (16U)
#define	I2S_PARAM_FRAME(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
#define	LPI2C_PARAM_MTXFIFO_MASK   (0xFU)
#define	LPI2C_PARAM_MTXFIFO_SHIFT   (0U)
#define	LPI2C_PARAM_MTXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
#define	LPI2C_PARAM_MRXFIFO_MASK   (0xF00U)
#define	LPI2C_PARAM_MRXFIFO_SHIFT   (8U)
#define	LPI2C_PARAM_MRXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
#define	LPSPI_PARAM_TXFIFO_MASK   (0xFFU)
#define	LPSPI_PARAM_TXFIFO_SHIFT   (0U)
#define	LPSPI_PARAM_TXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
#define	LPSPI_PARAM_RXFIFO_MASK   (0xFF00U)
#define	LPSPI_PARAM_RXFIFO_SHIFT   (8U)
#define	LPSPI_PARAM_RXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
#define	LPUART_PARAM_TXFIFO_MASK   (0xFFU)
#define	LPUART_PARAM_TXFIFO_SHIFT   (0U)
#define	LPUART_PARAM_TXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
#define	LPUART_PARAM_RXFIFO_MASK   (0xFF00U)
#define	LPUART_PARAM_RXFIFO_SHIFT   (8U)
#define	LPUART_PARAM_RXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

CTRL - FlexIO Control Register
#define	FLEXIO_CTRL_FLEXEN_MASK   (0x1U)
#define	FLEXIO_CTRL_FLEXEN_SHIFT   (0U)
#define	FLEXIO_CTRL_FLEXEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
#define	FLEXIO_CTRL_SWRST_MASK   (0x2U)
#define	FLEXIO_CTRL_SWRST_SHIFT   (1U)
#define	FLEXIO_CTRL_SWRST(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
#define	FLEXIO_CTRL_FASTACC_MASK   (0x4U)
#define	FLEXIO_CTRL_FASTACC_SHIFT   (2U)
#define	FLEXIO_CTRL_FASTACC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
#define	FLEXIO_CTRL_DBGE_MASK   (0x40000000U)
#define	FLEXIO_CTRL_DBGE_SHIFT   (30U)
#define	FLEXIO_CTRL_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
#define	FLEXIO_CTRL_DOZEN_MASK   (0x80000000U)
#define	FLEXIO_CTRL_DOZEN_SHIFT   (31U)
#define	FLEXIO_CTRL_DOZEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)

PIN - Pin State Register
#define	FLEXIO_PIN_PDI_MASK   (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
#define	FLEXIO_PIN_PDI_SHIFT   (0U)
#define	FLEXIO_PIN_PDI(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */

SHIFTSTAT - Shifter Status Register
#define	FLEXIO_SHIFTSTAT_SSF_MASK   (0xFU)
#define	FLEXIO_SHIFTSTAT_SSF_SHIFT   (0U)
#define	FLEXIO_SHIFTSTAT_SSF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)

SHIFTERR - Shifter Error Register
#define	FLEXIO_SHIFTERR_SEF_MASK   (0xFU)
#define	FLEXIO_SHIFTERR_SEF_SHIFT   (0U)
#define	FLEXIO_SHIFTERR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)

TIMSTAT - Timer Status Register
#define	FLEXIO_TIMSTAT_TSF_MASK   (0xFU)
#define	FLEXIO_TIMSTAT_TSF_SHIFT   (0U)
#define	FLEXIO_TIMSTAT_TSF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)

SHIFTSIEN - Shifter Status Interrupt Enable
#define	FLEXIO_SHIFTSIEN_SSIE_MASK   (0xFU)
#define	FLEXIO_SHIFTSIEN_SSIE_SHIFT   (0U)
#define	FLEXIO_SHIFTSIEN_SSIE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)

SHIFTEIEN - Shifter Error Interrupt Enable
#define	FLEXIO_SHIFTEIEN_SEIE_MASK   (0xFU)
#define	FLEXIO_SHIFTEIEN_SEIE_SHIFT   (0U)
#define	FLEXIO_SHIFTEIEN_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)

TIMIEN - Timer Interrupt Enable Register
#define	FLEXIO_TIMIEN_TEIE_MASK   (0xFU)
#define	FLEXIO_TIMIEN_TEIE_SHIFT   (0U)
#define	FLEXIO_TIMIEN_TEIE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)

SHIFTSDEN - Shifter Status DMA Enable
#define	FLEXIO_SHIFTSDEN_SSDE_MASK   (0xFU)
#define	FLEXIO_SHIFTSDEN_SSDE_SHIFT   (0U)
#define	FLEXIO_SHIFTSDEN_SSDE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)

SHIFTSTATE - Shifter State Register
#define	FLEXIO_SHIFTSTATE_STATE_MASK   (0x7U)
#define	FLEXIO_SHIFTSTATE_STATE_SHIFT   (0U)
#define	FLEXIO_SHIFTSTATE_STATE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)

SHIFTCTL - Shifter Control N Register
#define	FLEXIO_SHIFTCTL_SMOD_MASK   (0x7U)
#define	FLEXIO_SHIFTCTL_SMOD_SHIFT   (0U)
#define	FLEXIO_SHIFTCTL_SMOD(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
#define	FLEXIO_SHIFTCTL_PINPOL_MASK   (0x80U)
#define	FLEXIO_SHIFTCTL_PINPOL_SHIFT   (7U)
#define	FLEXIO_SHIFTCTL_PINPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
#define	FLEXIO_SHIFTCTL_PINSEL_MASK   (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
#define	FLEXIO_SHIFTCTL_PINSEL_SHIFT   (8U)
#define	FLEXIO_SHIFTCTL_PINSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
#define	FLEXIO_SHIFTCTL_PINCFG_MASK   (0x30000U)
#define	FLEXIO_SHIFTCTL_PINCFG_SHIFT   (16U)
#define	FLEXIO_SHIFTCTL_PINCFG(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
#define	FLEXIO_SHIFTCTL_TIMPOL_MASK   (0x800000U)
#define	FLEXIO_SHIFTCTL_TIMPOL_SHIFT   (23U)
#define	FLEXIO_SHIFTCTL_TIMPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
#define	FLEXIO_SHIFTCTL_TIMSEL_MASK   (0x3000000U)
#define	FLEXIO_SHIFTCTL_TIMSEL_SHIFT   (24U)
#define	FLEXIO_SHIFTCTL_TIMSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)

SHIFTCFG - Shifter Configuration N Register
#define	FLEXIO_SHIFTCFG_SSTART_MASK   (0x3U)
#define	FLEXIO_SHIFTCFG_SSTART_SHIFT   (0U)
#define	FLEXIO_SHIFTCFG_SSTART(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
#define	FLEXIO_SHIFTCFG_SSTOP_MASK   (0x30U)
#define	FLEXIO_SHIFTCFG_SSTOP_SHIFT   (4U)
#define	FLEXIO_SHIFTCFG_SSTOP(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
#define	FLEXIO_SHIFTCFG_INSRC_MASK   (0x100U)
#define	FLEXIO_SHIFTCFG_INSRC_SHIFT   (8U)
#define	FLEXIO_SHIFTCFG_INSRC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
#define	FLEXIO_SHIFTCFG_PWIDTH_MASK   (0x1F0000U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
#define	FLEXIO_SHIFTCFG_PWIDTH_SHIFT   (16U)
#define	FLEXIO_SHIFTCFG_PWIDTH(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */

SHIFTBUF - Shifter Buffer N Register
#define	FLEXIO_SHIFTBUF_SHIFTBUF_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT   (0U)
#define	FLEXIO_SHIFTBUF_SHIFTBUF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)

SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)

SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)

SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)

TIMCTL - Timer Control N Register
#define	FLEXIO_TIMCTL_TIMOD_MASK   (0x3U)
#define	FLEXIO_TIMCTL_TIMOD_SHIFT   (0U)
#define	FLEXIO_TIMCTL_TIMOD(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
#define	FLEXIO_TIMCTL_PINPOL_MASK   (0x80U)
#define	FLEXIO_TIMCTL_PINPOL_SHIFT   (7U)
#define	FLEXIO_TIMCTL_PINPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
#define	FLEXIO_TIMCTL_PINSEL_MASK   (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
#define	FLEXIO_TIMCTL_PINSEL_SHIFT   (8U)
#define	FLEXIO_TIMCTL_PINSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
#define	FLEXIO_TIMCTL_PINCFG_MASK   (0x30000U)
#define	FLEXIO_TIMCTL_PINCFG_SHIFT   (16U)
#define	FLEXIO_TIMCTL_PINCFG(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
#define	FLEXIO_TIMCTL_TRGSRC_MASK   (0x400000U)
#define	FLEXIO_TIMCTL_TRGSRC_SHIFT   (22U)
#define	FLEXIO_TIMCTL_TRGSRC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
#define	FLEXIO_TIMCTL_TRGPOL_MASK   (0x800000U)
#define	FLEXIO_TIMCTL_TRGPOL_SHIFT   (23U)
#define	FLEXIO_TIMCTL_TRGPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
#define	FLEXIO_TIMCTL_TRGSEL_MASK   (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
#define	FLEXIO_TIMCTL_TRGSEL_SHIFT   (24U)
#define	FLEXIO_TIMCTL_TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */

TIMCFG - Timer Configuration N Register
#define	FLEXIO_TIMCFG_TSTART_MASK   (0x2U)
#define	FLEXIO_TIMCFG_TSTART_SHIFT   (1U)
#define	FLEXIO_TIMCFG_TSTART(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
#define	FLEXIO_TIMCFG_TSTOP_MASK   (0x30U)
#define	FLEXIO_TIMCFG_TSTOP_SHIFT   (4U)
#define	FLEXIO_TIMCFG_TSTOP(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
#define	FLEXIO_TIMCFG_TIMENA_MASK   (0x700U)
#define	FLEXIO_TIMCFG_TIMENA_SHIFT   (8U)
#define	FLEXIO_TIMCFG_TIMENA(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
#define	FLEXIO_TIMCFG_TIMDIS_MASK   (0x7000U)
#define	FLEXIO_TIMCFG_TIMDIS_SHIFT   (12U)
#define	FLEXIO_TIMCFG_TIMDIS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
#define	FLEXIO_TIMCFG_TIMRST_MASK   (0x70000U)
#define	FLEXIO_TIMCFG_TIMRST_SHIFT   (16U)
#define	FLEXIO_TIMCFG_TIMRST(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
#define	FLEXIO_TIMCFG_TIMDEC_MASK   (0x300000U)
#define	FLEXIO_TIMCFG_TIMDEC_SHIFT   (20U)
#define	FLEXIO_TIMCFG_TIMDEC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
#define	FLEXIO_TIMCFG_TIMOUT_MASK   (0x3000000U)
#define	FLEXIO_TIMCFG_TIMOUT_SHIFT   (24U)
#define	FLEXIO_TIMCFG_TIMOUT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)

TIMCMP - Timer Compare N Register
#define	FLEXIO_TIMCMP_CMP_MASK   (0xFFFFU)
#define	FLEXIO_TIMCMP_CMP_SHIFT   (0U)
#define	FLEXIO_TIMCMP_CMP(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)

SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)

SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)

SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)

VERID - Version ID Register
#define	FLEXIO_VERID_FEATURE_MASK   (0xFFFFU)
#define	FLEXIO_VERID_FEATURE_SHIFT   (0U)
#define	FLEXIO_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
#define	FLEXIO_VERID_MINOR_MASK   (0xFF0000U)
#define	FLEXIO_VERID_MINOR_SHIFT   (16U)
#define	FLEXIO_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
#define	FLEXIO_VERID_MAJOR_MASK   (0xFF000000U)
#define	FLEXIO_VERID_MAJOR_SHIFT   (24U)
#define	FLEXIO_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	FLEXIO_PARAM_SHIFTER_MASK   (0xFFU)
#define	FLEXIO_PARAM_SHIFTER_SHIFT   (0U)
#define	FLEXIO_PARAM_SHIFTER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
#define	FLEXIO_PARAM_TIMER_MASK   (0xFF00U)
#define	FLEXIO_PARAM_TIMER_SHIFT   (8U)
#define	FLEXIO_PARAM_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
#define	FLEXIO_PARAM_PIN_MASK   (0xFF0000U)
#define	FLEXIO_PARAM_PIN_SHIFT   (16U)
#define	FLEXIO_PARAM_PIN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
#define	FLEXIO_PARAM_TRIGGER_MASK   (0xFF000000U)
#define	FLEXIO_PARAM_TRIGGER_SHIFT   (24U)
#define	FLEXIO_PARAM_TRIGGER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)

CTRL - FlexIO Control Register
#define	FLEXIO_CTRL_FLEXEN_MASK   (0x1U)
#define	FLEXIO_CTRL_FLEXEN_SHIFT   (0U)
#define	FLEXIO_CTRL_FLEXEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
#define	FLEXIO_CTRL_SWRST_MASK   (0x2U)
#define	FLEXIO_CTRL_SWRST_SHIFT   (1U)
#define	FLEXIO_CTRL_SWRST(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
#define	FLEXIO_CTRL_FASTACC_MASK   (0x4U)
#define	FLEXIO_CTRL_FASTACC_SHIFT   (2U)
#define	FLEXIO_CTRL_FASTACC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
#define	FLEXIO_CTRL_DBGE_MASK   (0x40000000U)
#define	FLEXIO_CTRL_DBGE_SHIFT   (30U)
#define	FLEXIO_CTRL_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
#define	FLEXIO_CTRL_DOZEN_MASK   (0x80000000U)
#define	FLEXIO_CTRL_DOZEN_SHIFT   (31U)
#define	FLEXIO_CTRL_DOZEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)

PIN - Pin State Register
#define	FLEXIO_PIN_PDI_MASK   (0xFFFFFFFFU)
#define	FLEXIO_PIN_PDI_SHIFT   (0U)
#define	FLEXIO_PIN_PDI(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)

SHIFTSTAT - Shifter Status Register
#define	FLEXIO_SHIFTSTAT_SSF_MASK   (0xFFU)
#define	FLEXIO_SHIFTSTAT_SSF_SHIFT   (0U)
#define	FLEXIO_SHIFTSTAT_SSF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)

SHIFTERR - Shifter Error Register
#define	FLEXIO_SHIFTERR_SEF_MASK   (0xFFU)
#define	FLEXIO_SHIFTERR_SEF_SHIFT   (0U)
#define	FLEXIO_SHIFTERR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)

TIMSTAT - Timer Status Register
#define	FLEXIO_TIMSTAT_TSF_MASK   (0xFFU)
#define	FLEXIO_TIMSTAT_TSF_SHIFT   (0U)
#define	FLEXIO_TIMSTAT_TSF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)

SHIFTSIEN - Shifter Status Interrupt Enable
#define	FLEXIO_SHIFTSIEN_SSIE_MASK   (0xFFU)
#define	FLEXIO_SHIFTSIEN_SSIE_SHIFT   (0U)
#define	FLEXIO_SHIFTSIEN_SSIE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)

SHIFTEIEN - Shifter Error Interrupt Enable
#define	FLEXIO_SHIFTEIEN_SEIE_MASK   (0xFFU)
#define	FLEXIO_SHIFTEIEN_SEIE_SHIFT   (0U)
#define	FLEXIO_SHIFTEIEN_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)

TIMIEN - Timer Interrupt Enable Register
#define	FLEXIO_TIMIEN_TEIE_MASK   (0xFFU)
#define	FLEXIO_TIMIEN_TEIE_SHIFT   (0U)
#define	FLEXIO_TIMIEN_TEIE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)

SHIFTSDEN - Shifter Status DMA Enable
#define	FLEXIO_SHIFTSDEN_SSDE_MASK   (0xFFU)
#define	FLEXIO_SHIFTSDEN_SSDE_SHIFT   (0U)
#define	FLEXIO_SHIFTSDEN_SSDE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)

TIMERSDEN - Timer Status DMA Enable
#define	FLEXIO_TIMERSDEN_TSDE_MASK   (0xFFU)
#define	FLEXIO_TIMERSDEN_TSDE_SHIFT   (0U)
#define	FLEXIO_TIMERSDEN_TSDE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)

SHIFTSTATE - Shifter State Register
#define	FLEXIO_SHIFTSTATE_STATE_MASK   (0x7U)
#define	FLEXIO_SHIFTSTATE_STATE_SHIFT   (0U)
#define	FLEXIO_SHIFTSTATE_STATE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)

SHIFTCTL - Shifter Control N Register
#define	FLEXIO_SHIFTCTL_SMOD_MASK   (0x7U)
#define	FLEXIO_SHIFTCTL_SMOD_SHIFT   (0U)
#define	FLEXIO_SHIFTCTL_SMOD(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
#define	FLEXIO_SHIFTCTL_PINPOL_MASK   (0x80U)
#define	FLEXIO_SHIFTCTL_PINPOL_SHIFT   (7U)
#define	FLEXIO_SHIFTCTL_PINPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
#define	FLEXIO_SHIFTCTL_PINSEL_MASK   (0x1F00U)
#define	FLEXIO_SHIFTCTL_PINSEL_SHIFT   (8U)
#define	FLEXIO_SHIFTCTL_PINSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
#define	FLEXIO_SHIFTCTL_PINCFG_MASK   (0x30000U)
#define	FLEXIO_SHIFTCTL_PINCFG_SHIFT   (16U)
#define	FLEXIO_SHIFTCTL_PINCFG(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
#define	FLEXIO_SHIFTCTL_TIMPOL_MASK   (0x800000U)
#define	FLEXIO_SHIFTCTL_TIMPOL_SHIFT   (23U)
#define	FLEXIO_SHIFTCTL_TIMPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
#define	FLEXIO_SHIFTCTL_TIMSEL_MASK   (0x7000000U)
#define	FLEXIO_SHIFTCTL_TIMSEL_SHIFT   (24U)
#define	FLEXIO_SHIFTCTL_TIMSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)

SHIFTCFG - Shifter Configuration N Register
#define	FLEXIO_SHIFTCFG_SSTART_MASK   (0x3U)
#define	FLEXIO_SHIFTCFG_SSTART_SHIFT   (0U)
#define	FLEXIO_SHIFTCFG_SSTART(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
#define	FLEXIO_SHIFTCFG_SSTOP_MASK   (0x30U)
#define	FLEXIO_SHIFTCFG_SSTOP_SHIFT   (4U)
#define	FLEXIO_SHIFTCFG_SSTOP(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
#define	FLEXIO_SHIFTCFG_INSRC_MASK   (0x100U)
#define	FLEXIO_SHIFTCFG_INSRC_SHIFT   (8U)
#define	FLEXIO_SHIFTCFG_INSRC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
#define	FLEXIO_SHIFTCFG_LATST_MASK   (0x200U)
#define	FLEXIO_SHIFTCFG_LATST_SHIFT   (9U)
#define	FLEXIO_SHIFTCFG_LATST(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)
#define	FLEXIO_SHIFTCFG_PWIDTH_MASK   (0x1F0000U)
#define	FLEXIO_SHIFTCFG_PWIDTH_SHIFT   (16U)
#define	FLEXIO_SHIFTCFG_PWIDTH(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)

SHIFTBUF - Shifter Buffer N Register
#define	FLEXIO_SHIFTBUF_SHIFTBUF_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT   (0U)
#define	FLEXIO_SHIFTBUF_SHIFTBUF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)

SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)

SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)

SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)

TIMCTL - Timer Control N Register
#define	FLEXIO_TIMCTL_TIMOD_MASK   (0x7U)
#define	FLEXIO_TIMCTL_TIMOD_SHIFT   (0U)
#define	FLEXIO_TIMCTL_TIMOD(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
#define	FLEXIO_TIMCTL_ONETIM_MASK   (0x20U)
#define	FLEXIO_TIMCTL_ONETIM_SHIFT   (5U)
#define	FLEXIO_TIMCTL_ONETIM(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)
#define	FLEXIO_TIMCTL_PININS_MASK   (0x40U)
#define	FLEXIO_TIMCTL_PININS_SHIFT   (6U)
#define	FLEXIO_TIMCTL_PININS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)
#define	FLEXIO_TIMCTL_PINPOL_MASK   (0x80U)
#define	FLEXIO_TIMCTL_PINPOL_SHIFT   (7U)
#define	FLEXIO_TIMCTL_PINPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
#define	FLEXIO_TIMCTL_PINSEL_MASK   (0x1F00U)
#define	FLEXIO_TIMCTL_PINSEL_SHIFT   (8U)
#define	FLEXIO_TIMCTL_PINSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
#define	FLEXIO_TIMCTL_PINCFG_MASK   (0x30000U)
#define	FLEXIO_TIMCTL_PINCFG_SHIFT   (16U)
#define	FLEXIO_TIMCTL_PINCFG(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
#define	FLEXIO_TIMCTL_TRGSRC_MASK   (0x400000U)
#define	FLEXIO_TIMCTL_TRGSRC_SHIFT   (22U)
#define	FLEXIO_TIMCTL_TRGSRC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
#define	FLEXIO_TIMCTL_TRGPOL_MASK   (0x800000U)
#define	FLEXIO_TIMCTL_TRGPOL_SHIFT   (23U)
#define	FLEXIO_TIMCTL_TRGPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
#define	FLEXIO_TIMCTL_TRGSEL_MASK   (0x3F000000U)
#define	FLEXIO_TIMCTL_TRGSEL_SHIFT   (24U)
#define	FLEXIO_TIMCTL_TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)

TIMCFG - Timer Configuration N Register
#define	FLEXIO_TIMCFG_TSTART_MASK   (0x2U)
#define	FLEXIO_TIMCFG_TSTART_SHIFT   (1U)
#define	FLEXIO_TIMCFG_TSTART(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
#define	FLEXIO_TIMCFG_TSTOP_MASK   (0x30U)
#define	FLEXIO_TIMCFG_TSTOP_SHIFT   (4U)
#define	FLEXIO_TIMCFG_TSTOP(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
#define	FLEXIO_TIMCFG_TIMENA_MASK   (0x700U)
#define	FLEXIO_TIMCFG_TIMENA_SHIFT   (8U)
#define	FLEXIO_TIMCFG_TIMENA(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
#define	FLEXIO_TIMCFG_TIMDIS_MASK   (0x7000U)
#define	FLEXIO_TIMCFG_TIMDIS_SHIFT   (12U)
#define	FLEXIO_TIMCFG_TIMDIS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
#define	FLEXIO_TIMCFG_TIMRST_MASK   (0x70000U)
#define	FLEXIO_TIMCFG_TIMRST_SHIFT   (16U)
#define	FLEXIO_TIMCFG_TIMRST(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
#define	FLEXIO_TIMCFG_TIMDEC_MASK   (0x700000U)
#define	FLEXIO_TIMCFG_TIMDEC_SHIFT   (20U)
#define	FLEXIO_TIMCFG_TIMDEC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
#define	FLEXIO_TIMCFG_TIMOUT_MASK   (0x3000000U)
#define	FLEXIO_TIMCFG_TIMOUT_SHIFT   (24U)
#define	FLEXIO_TIMCFG_TIMOUT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)

TIMCMP - Timer Compare N Register
#define	FLEXIO_TIMCMP_CMP_MASK   (0xFFFFU)
#define	FLEXIO_TIMCMP_CMP_SHIFT   (0U)
#define	FLEXIO_TIMCMP_CMP(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)

SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)

SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)

SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)

SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register
#define	FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)

SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register
#define	FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)

VERID - Version ID Register
#define	FLEXIO_VERID_FEATURE_MASK   (0xFFFFU)
#define	FLEXIO_VERID_FEATURE_SHIFT   (0U)
#define	FLEXIO_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
#define	FLEXIO_VERID_MINOR_MASK   (0xFF0000U)
#define	FLEXIO_VERID_MINOR_SHIFT   (16U)
#define	FLEXIO_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
#define	FLEXIO_VERID_MAJOR_MASK   (0xFF000000U)
#define	FLEXIO_VERID_MAJOR_SHIFT   (24U)
#define	FLEXIO_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	FLEXIO_PARAM_SHIFTER_MASK   (0xFFU)
#define	FLEXIO_PARAM_SHIFTER_SHIFT   (0U)
#define	FLEXIO_PARAM_SHIFTER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
#define	FLEXIO_PARAM_TIMER_MASK   (0xFF00U)
#define	FLEXIO_PARAM_TIMER_SHIFT   (8U)
#define	FLEXIO_PARAM_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
#define	FLEXIO_PARAM_PIN_MASK   (0xFF0000U)
#define	FLEXIO_PARAM_PIN_SHIFT   (16U)
#define	FLEXIO_PARAM_PIN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
#define	FLEXIO_PARAM_TRIGGER_MASK   (0xFF000000U)
#define	FLEXIO_PARAM_TRIGGER_SHIFT   (24U)
#define	FLEXIO_PARAM_TRIGGER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)

CTRL - FlexIO Control Register
#define	FLEXIO_CTRL_FLEXEN_MASK   (0x1U)
#define	FLEXIO_CTRL_FLEXEN_SHIFT   (0U)
#define	FLEXIO_CTRL_FLEXEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
#define	FLEXIO_CTRL_SWRST_MASK   (0x2U)
#define	FLEXIO_CTRL_SWRST_SHIFT   (1U)
#define	FLEXIO_CTRL_SWRST(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
#define	FLEXIO_CTRL_FASTACC_MASK   (0x4U)
#define	FLEXIO_CTRL_FASTACC_SHIFT   (2U)
#define	FLEXIO_CTRL_FASTACC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
#define	FLEXIO_CTRL_DBGE_MASK   (0x40000000U)
#define	FLEXIO_CTRL_DBGE_SHIFT   (30U)
#define	FLEXIO_CTRL_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
#define	FLEXIO_CTRL_DOZEN_MASK   (0x80000000U)
#define	FLEXIO_CTRL_DOZEN_SHIFT   (31U)
#define	FLEXIO_CTRL_DOZEN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)

PIN - Pin State Register
#define	FLEXIO_PIN_PDI_MASK   (0xFFFFFFFFU)
#define	FLEXIO_PIN_PDI_SHIFT   (0U)
#define	FLEXIO_PIN_PDI(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)

SHIFTSTAT - Shifter Status Register
#define	FLEXIO_SHIFTSTAT_SSF_MASK   (0xFFU)
#define	FLEXIO_SHIFTSTAT_SSF_SHIFT   (0U)
#define	FLEXIO_SHIFTSTAT_SSF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)

SHIFTERR - Shifter Error Register
#define	FLEXIO_SHIFTERR_SEF_MASK   (0xFFU)
#define	FLEXIO_SHIFTERR_SEF_SHIFT   (0U)
#define	FLEXIO_SHIFTERR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)

TIMSTAT - Timer Status Register
#define	FLEXIO_TIMSTAT_TSF_MASK   (0xFFU)
#define	FLEXIO_TIMSTAT_TSF_SHIFT   (0U)
#define	FLEXIO_TIMSTAT_TSF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)

SHIFTSIEN - Shifter Status Interrupt Enable
#define	FLEXIO_SHIFTSIEN_SSIE_MASK   (0xFFU)
#define	FLEXIO_SHIFTSIEN_SSIE_SHIFT   (0U)
#define	FLEXIO_SHIFTSIEN_SSIE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)

SHIFTEIEN - Shifter Error Interrupt Enable
#define	FLEXIO_SHIFTEIEN_SEIE_MASK   (0xFFU)
#define	FLEXIO_SHIFTEIEN_SEIE_SHIFT   (0U)
#define	FLEXIO_SHIFTEIEN_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)

TIMIEN - Timer Interrupt Enable Register
#define	FLEXIO_TIMIEN_TEIE_MASK   (0xFFU)
#define	FLEXIO_TIMIEN_TEIE_SHIFT   (0U)
#define	FLEXIO_TIMIEN_TEIE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)

SHIFTSDEN - Shifter Status DMA Enable
#define	FLEXIO_SHIFTSDEN_SSDE_MASK   (0xFFU)
#define	FLEXIO_SHIFTSDEN_SSDE_SHIFT   (0U)
#define	FLEXIO_SHIFTSDEN_SSDE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)

TIMERSDEN - Timer Status DMA Enable
#define	FLEXIO_TIMERSDEN_TSDE_MASK   (0xFFU)
#define	FLEXIO_TIMERSDEN_TSDE_SHIFT   (0U)
#define	FLEXIO_TIMERSDEN_TSDE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)

SHIFTSTATE - Shifter State Register
#define	FLEXIO_SHIFTSTATE_STATE_MASK   (0x7U)
#define	FLEXIO_SHIFTSTATE_STATE_SHIFT   (0U)
#define	FLEXIO_SHIFTSTATE_STATE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)

SHIFTCTL - Shifter Control N Register
#define	FLEXIO_SHIFTCTL_SMOD_MASK   (0x7U)
#define	FLEXIO_SHIFTCTL_SMOD_SHIFT   (0U)
#define	FLEXIO_SHIFTCTL_SMOD(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
#define	FLEXIO_SHIFTCTL_PINPOL_MASK   (0x80U)
#define	FLEXIO_SHIFTCTL_PINPOL_SHIFT   (7U)
#define	FLEXIO_SHIFTCTL_PINPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
#define	FLEXIO_SHIFTCTL_PINSEL_MASK   (0x1F00U)
#define	FLEXIO_SHIFTCTL_PINSEL_SHIFT   (8U)
#define	FLEXIO_SHIFTCTL_PINSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
#define	FLEXIO_SHIFTCTL_PINCFG_MASK   (0x30000U)
#define	FLEXIO_SHIFTCTL_PINCFG_SHIFT   (16U)
#define	FLEXIO_SHIFTCTL_PINCFG(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
#define	FLEXIO_SHIFTCTL_TIMPOL_MASK   (0x800000U)
#define	FLEXIO_SHIFTCTL_TIMPOL_SHIFT   (23U)
#define	FLEXIO_SHIFTCTL_TIMPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
#define	FLEXIO_SHIFTCTL_TIMSEL_MASK   (0x7000000U)
#define	FLEXIO_SHIFTCTL_TIMSEL_SHIFT   (24U)
#define	FLEXIO_SHIFTCTL_TIMSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)

SHIFTCFG - Shifter Configuration N Register
#define	FLEXIO_SHIFTCFG_SSTART_MASK   (0x3U)
#define	FLEXIO_SHIFTCFG_SSTART_SHIFT   (0U)
#define	FLEXIO_SHIFTCFG_SSTART(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
#define	FLEXIO_SHIFTCFG_SSTOP_MASK   (0x30U)
#define	FLEXIO_SHIFTCFG_SSTOP_SHIFT   (4U)
#define	FLEXIO_SHIFTCFG_SSTOP(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
#define	FLEXIO_SHIFTCFG_INSRC_MASK   (0x100U)
#define	FLEXIO_SHIFTCFG_INSRC_SHIFT   (8U)
#define	FLEXIO_SHIFTCFG_INSRC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
#define	FLEXIO_SHIFTCFG_LATST_MASK   (0x200U)
#define	FLEXIO_SHIFTCFG_LATST_SHIFT   (9U)
#define	FLEXIO_SHIFTCFG_LATST(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)
#define	FLEXIO_SHIFTCFG_PWIDTH_MASK   (0x1F0000U)
#define	FLEXIO_SHIFTCFG_PWIDTH_SHIFT   (16U)
#define	FLEXIO_SHIFTCFG_PWIDTH(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)

SHIFTBUF - Shifter Buffer N Register
#define	FLEXIO_SHIFTBUF_SHIFTBUF_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT   (0U)
#define	FLEXIO_SHIFTBUF_SHIFTBUF(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)

SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)

SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)

SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)

TIMCTL - Timer Control N Register
#define	FLEXIO_TIMCTL_TIMOD_MASK   (0x7U)
#define	FLEXIO_TIMCTL_TIMOD_SHIFT   (0U)
#define	FLEXIO_TIMCTL_TIMOD(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
#define	FLEXIO_TIMCTL_ONETIM_MASK   (0x20U)
#define	FLEXIO_TIMCTL_ONETIM_SHIFT   (5U)
#define	FLEXIO_TIMCTL_ONETIM(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)
#define	FLEXIO_TIMCTL_PININS_MASK   (0x40U)
#define	FLEXIO_TIMCTL_PININS_SHIFT   (6U)
#define	FLEXIO_TIMCTL_PININS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)
#define	FLEXIO_TIMCTL_PINPOL_MASK   (0x80U)
#define	FLEXIO_TIMCTL_PINPOL_SHIFT   (7U)
#define	FLEXIO_TIMCTL_PINPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
#define	FLEXIO_TIMCTL_PINSEL_MASK   (0x1F00U)
#define	FLEXIO_TIMCTL_PINSEL_SHIFT   (8U)
#define	FLEXIO_TIMCTL_PINSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
#define	FLEXIO_TIMCTL_PINCFG_MASK   (0x30000U)
#define	FLEXIO_TIMCTL_PINCFG_SHIFT   (16U)
#define	FLEXIO_TIMCTL_PINCFG(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
#define	FLEXIO_TIMCTL_TRGSRC_MASK   (0x400000U)
#define	FLEXIO_TIMCTL_TRGSRC_SHIFT   (22U)
#define	FLEXIO_TIMCTL_TRGSRC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
#define	FLEXIO_TIMCTL_TRGPOL_MASK   (0x800000U)
#define	FLEXIO_TIMCTL_TRGPOL_SHIFT   (23U)
#define	FLEXIO_TIMCTL_TRGPOL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
#define	FLEXIO_TIMCTL_TRGSEL_MASK   (0x3F000000U)
#define	FLEXIO_TIMCTL_TRGSEL_SHIFT   (24U)
#define	FLEXIO_TIMCTL_TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)

TIMCFG - Timer Configuration N Register
#define	FLEXIO_TIMCFG_TSTART_MASK   (0x2U)
#define	FLEXIO_TIMCFG_TSTART_SHIFT   (1U)
#define	FLEXIO_TIMCFG_TSTART(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
#define	FLEXIO_TIMCFG_TSTOP_MASK   (0x30U)
#define	FLEXIO_TIMCFG_TSTOP_SHIFT   (4U)
#define	FLEXIO_TIMCFG_TSTOP(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
#define	FLEXIO_TIMCFG_TIMENA_MASK   (0x700U)
#define	FLEXIO_TIMCFG_TIMENA_SHIFT   (8U)
#define	FLEXIO_TIMCFG_TIMENA(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
#define	FLEXIO_TIMCFG_TIMDIS_MASK   (0x7000U)
#define	FLEXIO_TIMCFG_TIMDIS_SHIFT   (12U)
#define	FLEXIO_TIMCFG_TIMDIS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
#define	FLEXIO_TIMCFG_TIMRST_MASK   (0x70000U)
#define	FLEXIO_TIMCFG_TIMRST_SHIFT   (16U)
#define	FLEXIO_TIMCFG_TIMRST(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
#define	FLEXIO_TIMCFG_TIMDEC_MASK   (0x700000U)
#define	FLEXIO_TIMCFG_TIMDEC_SHIFT   (20U)
#define	FLEXIO_TIMCFG_TIMDEC(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
#define	FLEXIO_TIMCFG_TIMOUT_MASK   (0x3000000U)
#define	FLEXIO_TIMCFG_TIMOUT_SHIFT   (24U)
#define	FLEXIO_TIMCFG_TIMOUT(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)

TIMCMP - Timer Compare N Register
#define	FLEXIO_TIMCMP_CMP_MASK   (0xFFFFU)
#define	FLEXIO_TIMCMP_CMP_SHIFT   (0U)
#define	FLEXIO_TIMCMP_CMP(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)

SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)

SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)

SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)

SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register
#define	FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)

SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register
#define	FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK   (0xFFFFFFFFU)
#define	FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT   (0U)
#define	FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)

Detailed Description

Macro Definition Documentation

FLEXIO_CTRL_DBGE [1/3]

#define FLEXIO_CTRL_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)

DBGE - Debug Enable 0b0..FlexIO is disabled in debug modes. 0b1..FlexIO is enabled in debug modes

FLEXIO_CTRL_DBGE [2/3]

#define FLEXIO_CTRL_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)

DBGE - Debug Enable 0b0..FlexIO is disabled in debug modes. 0b1..FlexIO is enabled in debug modes

FLEXIO_CTRL_DBGE [3/3]

#define FLEXIO_CTRL_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)

DBGE - Debug Enable 0b0..FlexIO is disabled in debug modes. 0b1..FlexIO is enabled in debug modes

FLEXIO_CTRL_DOZEN [1/3]

#define FLEXIO_CTRL_DOZEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)

DOZEN - Doze Enable 0b0..FlexIO enabled in Doze modes. 0b1..FlexIO disabled in Doze modes.

FLEXIO_CTRL_DOZEN [2/3]

#define FLEXIO_CTRL_DOZEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)

DOZEN - Doze Enable 0b0..FlexIO enabled in Doze modes. 0b1..FlexIO disabled in Doze modes.

FLEXIO_CTRL_DOZEN [3/3]

#define FLEXIO_CTRL_DOZEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)

DOZEN - Doze Enable 0b0..FlexIO enabled in Doze modes. 0b1..FlexIO disabled in Doze modes.

FLEXIO_CTRL_FASTACC [1/3]

#define FLEXIO_CTRL_FASTACC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)

FASTACC - Fast Access 0b0..Configures for normal register accesses to FlexIO 0b1..Configures for fast register accesses to FlexIO

FLEXIO_CTRL_FASTACC [2/3]

#define FLEXIO_CTRL_FASTACC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)

FASTACC - Fast Access 0b0..Configures for normal register accesses to FlexIO 0b1..Configures for fast register accesses to FlexIO

FLEXIO_CTRL_FASTACC [3/3]

#define FLEXIO_CTRL_FASTACC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)

FASTACC - Fast Access 0b0..Configures for normal register accesses to FlexIO 0b1..Configures for fast register accesses to FlexIO

FLEXIO_CTRL_FLEXEN [1/3]

#define FLEXIO_CTRL_FLEXEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)

FLEXEN - FlexIO Enable 0b0..FlexIO module is disabled. 0b1..FlexIO module is enabled.

FLEXIO_CTRL_FLEXEN [2/3]

#define FLEXIO_CTRL_FLEXEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)

FLEXEN - FlexIO Enable 0b0..FlexIO module is disabled. 0b1..FlexIO module is enabled.

FLEXIO_CTRL_FLEXEN [3/3]

#define FLEXIO_CTRL_FLEXEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)

FLEXEN - FlexIO Enable 0b0..FlexIO module is disabled. 0b1..FlexIO module is enabled.

FLEXIO_CTRL_SWRST [1/3]

#define FLEXIO_CTRL_SWRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)

SWRST - Software Reset 0b0..Software reset is disabled 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.

FLEXIO_CTRL_SWRST [2/3]

#define FLEXIO_CTRL_SWRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)

SWRST - Software Reset 0b0..Software reset is disabled 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.

FLEXIO_CTRL_SWRST [3/3]

#define FLEXIO_CTRL_SWRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)

SWRST - Software Reset 0b0..Software reset is disabled 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.

FLEXIO_PARAM_PIN [1/3]

#define FLEXIO_PARAM_PIN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)

PIN - Pin Number

FLEXIO_PARAM_PIN [2/3]

#define FLEXIO_PARAM_PIN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)

PIN - Pin Number

FLEXIO_PARAM_PIN [3/3]

#define FLEXIO_PARAM_PIN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)

PIN - Pin Number

FLEXIO_PARAM_SHIFTER [1/3]

#define FLEXIO_PARAM_SHIFTER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)

SHIFTER - Shifter Number

FLEXIO_PARAM_SHIFTER [2/3]

#define FLEXIO_PARAM_SHIFTER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)

SHIFTER - Shifter Number

FLEXIO_PARAM_SHIFTER [3/3]

#define FLEXIO_PARAM_SHIFTER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)

SHIFTER - Shifter Number

FLEXIO_PARAM_TIMER [1/3]

#define FLEXIO_PARAM_TIMER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)

TIMER - Timer Number

FLEXIO_PARAM_TIMER [2/3]

#define FLEXIO_PARAM_TIMER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)

TIMER - Timer Number

FLEXIO_PARAM_TIMER [3/3]

#define FLEXIO_PARAM_TIMER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)

TIMER - Timer Number

FLEXIO_PARAM_TRIGGER [1/3]

#define FLEXIO_PARAM_TRIGGER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)

TRIGGER - Trigger Number

FLEXIO_PARAM_TRIGGER [2/3]

#define FLEXIO_PARAM_TRIGGER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)

TRIGGER - Trigger Number

FLEXIO_PARAM_TRIGGER [3/3]

#define FLEXIO_PARAM_TRIGGER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)

TRIGGER - Trigger Number

FLEXIO_PIN_PDI [1/3]

#define FLEXIO_PIN_PDI

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */

PDI - Pin Data Input

FLEXIO_PIN_PDI [2/3]

#define FLEXIO_PIN_PDI

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)

PDI - Pin Data Input

FLEXIO_PIN_PDI [3/3]

#define FLEXIO_PIN_PDI

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)

PDI - Pin Data Input

FLEXIO_SHIFTBUF_SHIFTBUF [1/3]

#define FLEXIO_SHIFTBUF_SHIFTBUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)

SHIFTBUF - Shift Buffer

FLEXIO_SHIFTBUF_SHIFTBUF [2/3]

#define FLEXIO_SHIFTBUF_SHIFTBUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)

SHIFTBUF - Shift Buffer

FLEXIO_SHIFTBUF_SHIFTBUF [3/3]

#define FLEXIO_SHIFTBUF_SHIFTBUF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)

SHIFTBUF - Shift Buffer

FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS [1/3]

#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)

SHIFTBUFBBS - Shift Buffer

FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS [2/3]

#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)

SHIFTBUFBBS - Shift Buffer

FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS [3/3]

#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)

SHIFTBUFBBS - Shift Buffer

FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS [1/3]

#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)

SHIFTBUFBIS - Shift Buffer

FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS [2/3]

#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)

SHIFTBUFBIS - Shift Buffer

FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS [3/3]

#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)

SHIFTBUFBIS - Shift Buffer

FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS [1/3]

#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)

SHIFTBUFBYS - Shift Buffer

FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS [2/3]

#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)

SHIFTBUFBYS - Shift Buffer

FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS [3/3]

#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)

SHIFTBUFBYS - Shift Buffer

FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS [1/2]

#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)

SHIFTBUFEOS - Shift Buffer

FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS [2/2]

#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)

SHIFTBUFEOS - Shift Buffer

FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS [1/3]

#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)

SHIFTBUFHWS - Shift Buffer

FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS [2/3]

#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)

SHIFTBUFHWS - Shift Buffer

FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS [3/3]

#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)

SHIFTBUFHWS - Shift Buffer

FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS [1/3]

#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)

SHIFTBUFNBS - Shift Buffer

FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS [2/3]

#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)

SHIFTBUFNBS - Shift Buffer

FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS [3/3]

#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)

SHIFTBUFNBS - Shift Buffer

FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS [1/3]

#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)

SHIFTBUFNIS - Shift Buffer

FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS [2/3]

#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)

SHIFTBUFNIS - Shift Buffer

FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS [3/3]

#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)

SHIFTBUFNIS - Shift Buffer

FLEXIO_SHIFTBUFOES_SHIFTBUFOES [1/2]

#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)

SHIFTBUFOES - Shift Buffer

FLEXIO_SHIFTBUFOES_SHIFTBUFOES [2/2]

#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)

SHIFTBUFOES - Shift Buffer

FLEXIO_SHIFTCFG_INSRC [1/3]

#define FLEXIO_SHIFTCFG_INSRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)

INSRC - Input Source 0b0..Pin 0b1..Shifter N+1 Output

FLEXIO_SHIFTCFG_INSRC [2/3]

#define FLEXIO_SHIFTCFG_INSRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)

INSRC - Input Source 0b0..Pin 0b1..Shifter N+1 Output

FLEXIO_SHIFTCFG_INSRC [3/3]

#define FLEXIO_SHIFTCFG_INSRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)

INSRC - Input Source 0b0..Pin 0b1..Shifter N+1 Output

FLEXIO_SHIFTCFG_LATST [1/2]

#define FLEXIO_SHIFTCFG_LATST

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)

LATST - Late Store 0b0..Shift register stores the pre-shift register state. 0b1..Shift register stores the post-shift register state.

FLEXIO_SHIFTCFG_LATST [2/2]

#define FLEXIO_SHIFTCFG_LATST

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)

LATST - Late Store 0b0..Shift register stores the pre-shift register state. 0b1..Shift register stores the post-shift register state.

FLEXIO_SHIFTCFG_PWIDTH [1/3]

#define FLEXIO_SHIFTCFG_PWIDTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */

PWIDTH - Parallel Width

FLEXIO_SHIFTCFG_PWIDTH [2/3]

#define FLEXIO_SHIFTCFG_PWIDTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)

PWIDTH - Parallel Width

FLEXIO_SHIFTCFG_PWIDTH [3/3]

#define FLEXIO_SHIFTCFG_PWIDTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)

PWIDTH - Parallel Width

FLEXIO_SHIFTCFG_SSTART [1/3]

#define FLEXIO_SHIFTCFG_SSTART

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)

SSTART - Shifter Start bit 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1

FLEXIO_SHIFTCFG_SSTART [2/3]

#define FLEXIO_SHIFTCFG_SSTART

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)

SSTART - Shifter Start bit 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1

FLEXIO_SHIFTCFG_SSTART [3/3]

#define FLEXIO_SHIFTCFG_SSTART

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)

SSTART - Shifter Start bit 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1

FLEXIO_SHIFTCFG_SSTOP [1/3]

#define FLEXIO_SHIFTCFG_SSTOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)

SSTOP - Shifter Stop bit 0b00..Stop bit disabled for transmitter/receiver/match store 0b01..Reserved for transmitter/receiver/match store 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1

FLEXIO_SHIFTCFG_SSTOP [2/3]

#define FLEXIO_SHIFTCFG_SSTOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)

SSTOP - Shifter Stop bit 0b00..Stop bit disabled for transmitter/receiver/match store 0b01..Reserved for transmitter/receiver/match store 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1

FLEXIO_SHIFTCFG_SSTOP [3/3]

#define FLEXIO_SHIFTCFG_SSTOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)

SSTOP - Shifter Stop bit 0b00..Stop bit disabled for transmitter/receiver/match store 0b01..Reserved for transmitter/receiver/match store 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1

FLEXIO_SHIFTCTL_PINCFG [1/3]

#define FLEXIO_SHIFTCTL_PINCFG

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)

PINCFG - Shifter Pin Configuration 0b00..Shifter pin output disabled 0b01..Shifter pin open drain or bidirectional output enable 0b10..Shifter pin bidirectional output data 0b11..Shifter pin output

FLEXIO_SHIFTCTL_PINCFG [2/3]

#define FLEXIO_SHIFTCTL_PINCFG

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)

PINCFG - Shifter Pin Configuration 0b00..Shifter pin output disabled 0b01..Shifter pin open drain or bidirectional output enable 0b10..Shifter pin bidirectional output data 0b11..Shifter pin output

FLEXIO_SHIFTCTL_PINCFG [3/3]

#define FLEXIO_SHIFTCTL_PINCFG

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)

PINCFG - Shifter Pin Configuration 0b00..Shifter pin output disabled 0b01..Shifter pin open drain or bidirectional output enable 0b10..Shifter pin bidirectional output data 0b11..Shifter pin output

FLEXIO_SHIFTCTL_PINPOL [1/3]

#define FLEXIO_SHIFTCTL_PINPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)

PINPOL - Shifter Pin Polarity 0b0..Pin is active high 0b1..Pin is active low

FLEXIO_SHIFTCTL_PINPOL [2/3]

#define FLEXIO_SHIFTCTL_PINPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)

PINPOL - Shifter Pin Polarity 0b0..Pin is active high 0b1..Pin is active low

FLEXIO_SHIFTCTL_PINPOL [3/3]

#define FLEXIO_SHIFTCTL_PINPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)

PINPOL - Shifter Pin Polarity 0b0..Pin is active high 0b1..Pin is active low

FLEXIO_SHIFTCTL_PINSEL [1/3]

#define FLEXIO_SHIFTCTL_PINSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */

PINSEL - Shifter Pin Select

FLEXIO_SHIFTCTL_PINSEL [2/3]

#define FLEXIO_SHIFTCTL_PINSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)

PINSEL - Shifter Pin Select

FLEXIO_SHIFTCTL_PINSEL [3/3]

#define FLEXIO_SHIFTCTL_PINSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)

PINSEL - Shifter Pin Select

FLEXIO_SHIFTCTL_SMOD [1/3]

#define FLEXIO_SHIFTCTL_SMOD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)

SMOD - Shifter Mode 0b000..Disabled. 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0b011..Reserved. 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.

FLEXIO_SHIFTCTL_SMOD [2/3]

#define FLEXIO_SHIFTCTL_SMOD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)

SMOD - Shifter Mode 0b000..Disabled. 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0b011..Reserved. 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.

FLEXIO_SHIFTCTL_SMOD [3/3]

#define FLEXIO_SHIFTCTL_SMOD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)

SMOD - Shifter Mode 0b000..Disabled. 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0b011..Reserved. 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.

FLEXIO_SHIFTCTL_TIMPOL [1/3]

#define FLEXIO_SHIFTCTL_TIMPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)

TIMPOL - Timer Polarity 0b0..Shift on posedge of Shift clock 0b1..Shift on negedge of Shift clock

FLEXIO_SHIFTCTL_TIMPOL [2/3]

#define FLEXIO_SHIFTCTL_TIMPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)

TIMPOL - Timer Polarity 0b0..Shift on posedge of Shift clock 0b1..Shift on negedge of Shift clock

FLEXIO_SHIFTCTL_TIMPOL [3/3]

#define FLEXIO_SHIFTCTL_TIMPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)

TIMPOL - Timer Polarity 0b0..Shift on posedge of Shift clock 0b1..Shift on negedge of Shift clock

FLEXIO_SHIFTCTL_TIMSEL [1/3]

#define FLEXIO_SHIFTCTL_TIMSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)

TIMSEL - Timer Select

FLEXIO_SHIFTCTL_TIMSEL [2/3]

#define FLEXIO_SHIFTCTL_TIMSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)

TIMSEL - Timer Select

FLEXIO_SHIFTCTL_TIMSEL [3/3]

#define FLEXIO_SHIFTCTL_TIMSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)

TIMSEL - Timer Select

FLEXIO_SHIFTEIEN_SEIE [1/3]

#define FLEXIO_SHIFTEIEN_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)

SEIE - Shifter Error Interrupt Enable

FLEXIO_SHIFTEIEN_SEIE [2/3]

#define FLEXIO_SHIFTEIEN_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)

SEIE - Shifter Error Interrupt Enable

FLEXIO_SHIFTEIEN_SEIE [3/3]

#define FLEXIO_SHIFTEIEN_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)

SEIE - Shifter Error Interrupt Enable

FLEXIO_SHIFTERR_SEF [1/3]

#define FLEXIO_SHIFTERR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)

SEF - Shifter Error Flags

FLEXIO_SHIFTERR_SEF [2/3]

#define FLEXIO_SHIFTERR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)

SEF - Shifter Error Flags

FLEXIO_SHIFTERR_SEF [3/3]

#define FLEXIO_SHIFTERR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)

SEF - Shifter Error Flags

FLEXIO_SHIFTSDEN_SSDE [1/3]

#define FLEXIO_SHIFTSDEN_SSDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)

SSDE - Shifter Status DMA Enable

FLEXIO_SHIFTSDEN_SSDE [2/3]

#define FLEXIO_SHIFTSDEN_SSDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)

SSDE - Shifter Status DMA Enable

FLEXIO_SHIFTSDEN_SSDE [3/3]

#define FLEXIO_SHIFTSDEN_SSDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)

SSDE - Shifter Status DMA Enable

FLEXIO_SHIFTSIEN_SSIE [1/3]

#define FLEXIO_SHIFTSIEN_SSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)

SSIE - Shifter Status Interrupt Enable

FLEXIO_SHIFTSIEN_SSIE [2/3]

#define FLEXIO_SHIFTSIEN_SSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)

SSIE - Shifter Status Interrupt Enable

FLEXIO_SHIFTSIEN_SSIE [3/3]

#define FLEXIO_SHIFTSIEN_SSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)

SSIE - Shifter Status Interrupt Enable

FLEXIO_SHIFTSTAT_SSF [1/3]

#define FLEXIO_SHIFTSTAT_SSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)

SSF - Shifter Status Flag

FLEXIO_SHIFTSTAT_SSF [2/3]

#define FLEXIO_SHIFTSTAT_SSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)

SSF - Shifter Status Flag

FLEXIO_SHIFTSTAT_SSF [3/3]

#define FLEXIO_SHIFTSTAT_SSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)

SSF - Shifter Status Flag

FLEXIO_SHIFTSTATE_STATE [1/3]

#define FLEXIO_SHIFTSTATE_STATE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)

STATE - Current State Pointer

FLEXIO_SHIFTSTATE_STATE [2/3]

#define FLEXIO_SHIFTSTATE_STATE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)

STATE - Current State Pointer

FLEXIO_SHIFTSTATE_STATE [3/3]

#define FLEXIO_SHIFTSTATE_STATE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)

STATE - Current State Pointer

FLEXIO_TIMCFG_TIMDEC [1/3]

#define FLEXIO_TIMCFG_TIMDEC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)

TIMDEC - Timer Decrement 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.

FLEXIO_TIMCFG_TIMDEC [2/3]

#define FLEXIO_TIMCFG_TIMDEC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)

TIMDEC - Timer Decrement 0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output. 0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output. 0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output. 0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input. 0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.

FLEXIO_TIMCFG_TIMDEC [3/3]

#define FLEXIO_TIMCFG_TIMDEC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)

TIMDEC - Timer Decrement 0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output. 0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output. 0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output. 0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input. 0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.

FLEXIO_TIMCFG_TIMDIS [1/3]

#define FLEXIO_TIMCFG_TIMDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)

TIMDIS - Timer Disable 0b000..Timer never disabled 0b001..Timer disabled on Timer N-1 disable 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0b100..Timer disabled on Pin rising or falling edge 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high 0b110..Timer disabled on Trigger falling edge 0b111..Reserved

FLEXIO_TIMCFG_TIMDIS [2/3]

#define FLEXIO_TIMCFG_TIMDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)

TIMDIS - Timer Disable 0b000..Timer never disabled 0b001..Timer disabled on Timer N-1 disable 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0b100..Timer disabled on Pin rising or falling edge 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high 0b110..Timer disabled on Trigger falling edge 0b111..Reserved

FLEXIO_TIMCFG_TIMDIS [3/3]

#define FLEXIO_TIMCFG_TIMDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)

TIMDIS - Timer Disable 0b000..Timer never disabled 0b001..Timer disabled on Timer N-1 disable 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0b100..Timer disabled on Pin rising or falling edge 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high 0b110..Timer disabled on Trigger falling edge 0b111..Reserved

FLEXIO_TIMCFG_TIMENA [1/3]

#define FLEXIO_TIMCFG_TIMENA

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)

TIMENA - Timer Enable 0b000..Timer always enabled 0b001..Timer enabled on Timer N-1 enable 0b010..Timer enabled on Trigger high 0b011..Timer enabled on Trigger high and Pin high 0b100..Timer enabled on Pin rising edge 0b101..Timer enabled on Pin rising edge and Trigger high 0b110..Timer enabled on Trigger rising edge 0b111..Timer enabled on Trigger rising or falling edge

FLEXIO_TIMCFG_TIMENA [2/3]

#define FLEXIO_TIMCFG_TIMENA

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)

TIMENA - Timer Enable 0b000..Timer always enabled 0b001..Timer enabled on Timer N-1 enable 0b010..Timer enabled on Trigger high 0b011..Timer enabled on Trigger high and Pin high 0b100..Timer enabled on Pin rising edge 0b101..Timer enabled on Pin rising edge and Trigger high 0b110..Timer enabled on Trigger rising edge 0b111..Timer enabled on Trigger rising or falling edge

FLEXIO_TIMCFG_TIMENA [3/3]

#define FLEXIO_TIMCFG_TIMENA

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)

TIMENA - Timer Enable 0b000..Timer always enabled 0b001..Timer enabled on Timer N-1 enable 0b010..Timer enabled on Trigger high 0b011..Timer enabled on Trigger high and Pin high 0b100..Timer enabled on Pin rising edge 0b101..Timer enabled on Pin rising edge and Trigger high 0b110..Timer enabled on Trigger rising edge 0b111..Timer enabled on Trigger rising or falling edge

FLEXIO_TIMCFG_TIMOUT [1/3]

#define FLEXIO_TIMCFG_TIMOUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)

TIMOUT - Timer Output 0b00..Timer output is logic one when enabled and is not affected by timer reset 0b01..Timer output is logic zero when enabled and is not affected by timer reset 0b10..Timer output is logic one when enabled and on timer reset 0b11..Timer output is logic zero when enabled and on timer reset

FLEXIO_TIMCFG_TIMOUT [2/3]

#define FLEXIO_TIMCFG_TIMOUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)

TIMOUT - Timer Output 0b00..Timer output is logic one when enabled and is not affected by timer reset 0b01..Timer output is logic zero when enabled and is not affected by timer reset 0b10..Timer output is logic one when enabled and on timer reset 0b11..Timer output is logic zero when enabled and on timer reset

FLEXIO_TIMCFG_TIMOUT [3/3]

#define FLEXIO_TIMCFG_TIMOUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)

TIMOUT - Timer Output 0b00..Timer output is logic one when enabled and is not affected by timer reset 0b01..Timer output is logic zero when enabled and is not affected by timer reset 0b10..Timer output is logic one when enabled and on timer reset 0b11..Timer output is logic zero when enabled and on timer reset

FLEXIO_TIMCFG_TIMRST [1/3]

#define FLEXIO_TIMCFG_TIMRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)

TIMRST - Timer Reset 0b000..Timer never reset 0b001..Reserved 0b010..Timer reset on Timer Pin equal to Timer Output 0b011..Timer reset on Timer Trigger equal to Timer Output 0b100..Timer reset on Timer Pin rising edge 0b101..Reserved 0b110..Timer reset on Trigger rising edge 0b111..Timer reset on Trigger rising or falling edge

FLEXIO_TIMCFG_TIMRST [2/3]

#define FLEXIO_TIMCFG_TIMRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)

TIMRST - Timer Reset 0b000..Timer never reset 0b001..Timer reset on Timer Output high. 0b010..Timer reset on Timer Pin equal to Timer Output 0b011..Timer reset on Timer Trigger equal to Timer Output 0b100..Timer reset on Timer Pin rising edge 0b101..Reserved 0b110..Timer reset on Trigger rising edge 0b111..Timer reset on Trigger rising or falling edge

FLEXIO_TIMCFG_TIMRST [3/3]

#define FLEXIO_TIMCFG_TIMRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)

TIMRST - Timer Reset 0b000..Timer never reset 0b001..Timer reset on Timer Output high. 0b010..Timer reset on Timer Pin equal to Timer Output 0b011..Timer reset on Timer Trigger equal to Timer Output 0b100..Timer reset on Timer Pin rising edge 0b101..Reserved 0b110..Timer reset on Trigger rising edge 0b111..Timer reset on Trigger rising or falling edge

FLEXIO_TIMCFG_TSTART [1/3]

#define FLEXIO_TIMCFG_TSTART

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)

TSTART - Timer Start Bit 0b0..Start bit disabled 0b1..Start bit enabled

FLEXIO_TIMCFG_TSTART [2/3]

#define FLEXIO_TIMCFG_TSTART

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)

TSTART - Timer Start Bit 0b0..Start bit disabled 0b1..Start bit enabled

FLEXIO_TIMCFG_TSTART [3/3]

#define FLEXIO_TIMCFG_TSTART

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)

TSTART - Timer Start Bit 0b0..Start bit disabled 0b1..Start bit enabled

FLEXIO_TIMCFG_TSTOP [1/3]

#define FLEXIO_TIMCFG_TSTOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)

TSTOP - Timer Stop Bit 0b00..Stop bit disabled 0b01..Stop bit is enabled on timer compare 0b10..Stop bit is enabled on timer disable 0b11..Stop bit is enabled on timer compare and timer disable

FLEXIO_TIMCFG_TSTOP [2/3]

#define FLEXIO_TIMCFG_TSTOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)

TSTOP - Timer Stop Bit 0b00..Stop bit disabled 0b01..Stop bit is enabled on timer compare 0b10..Stop bit is enabled on timer disable 0b11..Stop bit is enabled on timer compare and timer disable

FLEXIO_TIMCFG_TSTOP [3/3]

#define FLEXIO_TIMCFG_TSTOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)

TSTOP - Timer Stop Bit 0b00..Stop bit disabled 0b01..Stop bit is enabled on timer compare 0b10..Stop bit is enabled on timer disable 0b11..Stop bit is enabled on timer compare and timer disable

FLEXIO_TIMCMP_CMP [1/3]

#define FLEXIO_TIMCMP_CMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)

CMP - Timer Compare Value

FLEXIO_TIMCMP_CMP [2/3]

#define FLEXIO_TIMCMP_CMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)

CMP - Timer Compare Value

FLEXIO_TIMCMP_CMP [3/3]

#define FLEXIO_TIMCMP_CMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)

CMP - Timer Compare Value

FLEXIO_TIMCTL_ONETIM [1/2]

#define FLEXIO_TIMCTL_ONETIM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)

ONETIM - Timer One Time Operation 0b0..The timer enable event is generated as normal. 0b1..The timer enable event is blocked unless timer status flag is clear.

FLEXIO_TIMCTL_ONETIM [2/2]

#define FLEXIO_TIMCTL_ONETIM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)

ONETIM - Timer One Time Operation 0b0..The timer enable event is generated as normal. 0b1..The timer enable event is blocked unless timer status flag is clear.

FLEXIO_TIMCTL_PINCFG [1/3]

#define FLEXIO_TIMCTL_PINCFG

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)

PINCFG - Timer Pin Configuration 0b00..Timer pin output disabled 0b01..Timer pin open drain or bidirectional output enable 0b10..Timer pin bidirectional output data 0b11..Timer pin output

FLEXIO_TIMCTL_PINCFG [2/3]

#define FLEXIO_TIMCTL_PINCFG

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)

PINCFG - Timer Pin Configuration 0b00..Timer pin output disabled 0b01..Timer pin open drain or bidirectional output enable 0b10..Timer pin bidirectional output data 0b11..Timer pin output

FLEXIO_TIMCTL_PINCFG [3/3]

#define FLEXIO_TIMCTL_PINCFG

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)

PINCFG - Timer Pin Configuration 0b00..Timer pin output disabled 0b01..Timer pin open drain or bidirectional output enable 0b10..Timer pin bidirectional output data 0b11..Timer pin output

FLEXIO_TIMCTL_PININS [1/2]

#define FLEXIO_TIMCTL_PININS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)

PININS - Timer Pin Input Select 0b0..Timer pin input and output are selected by PINSEL. 0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.

FLEXIO_TIMCTL_PININS [2/2]

#define FLEXIO_TIMCTL_PININS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)

PININS - Timer Pin Input Select 0b0..Timer pin input and output are selected by PINSEL. 0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.

FLEXIO_TIMCTL_PINPOL [1/3]

#define FLEXIO_TIMCTL_PINPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)

PINPOL - Timer Pin Polarity 0b0..Pin is active high 0b1..Pin is active low

FLEXIO_TIMCTL_PINPOL [2/3]

#define FLEXIO_TIMCTL_PINPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)

PINPOL - Timer Pin Polarity 0b0..Pin is active high 0b1..Pin is active low

FLEXIO_TIMCTL_PINPOL [3/3]

#define FLEXIO_TIMCTL_PINPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)

PINPOL - Timer Pin Polarity 0b0..Pin is active high 0b1..Pin is active low

FLEXIO_TIMCTL_PINSEL [1/3]

#define FLEXIO_TIMCTL_PINSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */

PINSEL - Timer Pin Select

FLEXIO_TIMCTL_PINSEL [2/3]

#define FLEXIO_TIMCTL_PINSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)

PINSEL - Timer Pin Select

FLEXIO_TIMCTL_PINSEL [3/3]

#define FLEXIO_TIMCTL_PINSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)

PINSEL - Timer Pin Select

FLEXIO_TIMCTL_TIMOD [1/3]

#define FLEXIO_TIMCTL_TIMOD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)

TIMOD - Timer Mode 0b00..Timer Disabled. 0b01..Dual 8-bit counters baud mode. 0b10..Dual 8-bit counters PWM high mode. 0b11..Single 16-bit counter mode.

FLEXIO_TIMCTL_TIMOD [2/3]

#define FLEXIO_TIMCTL_TIMOD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)

TIMOD - Timer Mode 0b000..Timer Disabled. 0b001..Dual 8-bit counters baud mode. 0b010..Dual 8-bit counters PWM high mode. 0b011..Single 16-bit counter mode. 0b100..Single 16-bit counter disable mode. 0b101..Dual 8-bit counters word mode. 0b110..Dual 8-bit counters PWM low mode. 0b111..Single 16-bit input capture mode.

FLEXIO_TIMCTL_TIMOD [3/3]

#define FLEXIO_TIMCTL_TIMOD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)

TIMOD - Timer Mode 0b000..Timer Disabled. 0b001..Dual 8-bit counters baud mode. 0b010..Dual 8-bit counters PWM high mode. 0b011..Single 16-bit counter mode. 0b100..Single 16-bit counter disable mode. 0b101..Dual 8-bit counters word mode. 0b110..Dual 8-bit counters PWM low mode. 0b111..Single 16-bit input capture mode.

FLEXIO_TIMCTL_TRGPOL [1/3]

#define FLEXIO_TIMCTL_TRGPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)

TRGPOL - Trigger Polarity 0b0..Trigger active high 0b1..Trigger active low

FLEXIO_TIMCTL_TRGPOL [2/3]

#define FLEXIO_TIMCTL_TRGPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)

TRGPOL - Trigger Polarity 0b0..Trigger active high 0b1..Trigger active low

FLEXIO_TIMCTL_TRGPOL [3/3]

#define FLEXIO_TIMCTL_TRGPOL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)

TRGPOL - Trigger Polarity 0b0..Trigger active high 0b1..Trigger active low

FLEXIO_TIMCTL_TRGSEL [1/3]

#define FLEXIO_TIMCTL_TRGSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */

TRGSEL - Trigger Select

FLEXIO_TIMCTL_TRGSEL [2/3]

#define FLEXIO_TIMCTL_TRGSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)

TRGSEL - Trigger Select

FLEXIO_TIMCTL_TRGSEL [3/3]

#define FLEXIO_TIMCTL_TRGSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)

TRGSEL - Trigger Select

FLEXIO_TIMCTL_TRGSRC [1/3]

#define FLEXIO_TIMCTL_TRGSRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)

TRGSRC - Trigger Source 0b0..External trigger selected 0b1..Internal trigger selected

FLEXIO_TIMCTL_TRGSRC [2/3]

#define FLEXIO_TIMCTL_TRGSRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)

TRGSRC - Trigger Source 0b0..External trigger selected 0b1..Internal trigger selected

FLEXIO_TIMCTL_TRGSRC [3/3]

#define FLEXIO_TIMCTL_TRGSRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)

TRGSRC - Trigger Source 0b0..External trigger selected 0b1..Internal trigger selected

FLEXIO_TIMERSDEN_TSDE [1/2]

#define FLEXIO_TIMERSDEN_TSDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)

TSDE - Timer Status DMA Enable

FLEXIO_TIMERSDEN_TSDE [2/2]

#define FLEXIO_TIMERSDEN_TSDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)

TSDE - Timer Status DMA Enable

FLEXIO_TIMIEN_TEIE [1/3]

#define FLEXIO_TIMIEN_TEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)

TEIE - Timer Status Interrupt Enable

FLEXIO_TIMIEN_TEIE [2/3]

#define FLEXIO_TIMIEN_TEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)

TEIE - Timer Status Interrupt Enable

FLEXIO_TIMIEN_TEIE [3/3]

#define FLEXIO_TIMIEN_TEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)

TEIE - Timer Status Interrupt Enable

FLEXIO_TIMSTAT_TSF [1/3]

#define FLEXIO_TIMSTAT_TSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)

TSF - Timer Status Flags

FLEXIO_TIMSTAT_TSF [2/3]

#define FLEXIO_TIMSTAT_TSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)

TSF - Timer Status Flags

FLEXIO_TIMSTAT_TSF [3/3]

#define FLEXIO_TIMSTAT_TSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)

TSF - Timer Status Flags

FLEXIO_VERID_FEATURE [1/3]

#define FLEXIO_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000000..Standard features implemented. 0b0000000000000001..Supports state, logic and parallel modes.

FLEXIO_VERID_FEATURE [2/3]

#define FLEXIO_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000000..Standard features implemented. 0b0000000000000001..Supports state, logic and parallel modes. 0b0000000000000010..Supports pin control registers. 0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.

FLEXIO_VERID_FEATURE [3/3]

#define FLEXIO_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000000..Standard features implemented. 0b0000000000000001..Supports state, logic and parallel modes. 0b0000000000000010..Supports pin control registers. 0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.

FLEXIO_VERID_MAJOR [1/3]

#define FLEXIO_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)

MAJOR - Major Version Number

FLEXIO_VERID_MAJOR [2/3]

#define FLEXIO_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)

MAJOR - Major Version Number

FLEXIO_VERID_MAJOR [3/3]

#define FLEXIO_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)

MAJOR - Major Version Number

FLEXIO_VERID_MINOR [1/3]

#define FLEXIO_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)

MINOR - Minor Version Number

FLEXIO_VERID_MINOR [2/3]

#define FLEXIO_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)

MINOR - Minor Version Number

FLEXIO_VERID_MINOR [3/3]

#define FLEXIO_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)

MINOR - Minor Version Number

I2S_PARAM_DATALINE

#define I2S_PARAM_DATALINE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)

DATALINE - Number of Datalines

I2S_PARAM_FIFO

#define I2S_PARAM_FIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)

FIFO - FIFO Size

I2S_PARAM_FRAME

#define I2S_PARAM_FRAME

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)

FRAME - Frame Size

I2S_VERID_FEATURE

#define I2S_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000000..Standard feature set.

I2S_VERID_MAJOR

#define I2S_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)

MAJOR - Major Version Number

I2S_VERID_MINOR

#define I2S_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)

MINOR - Minor Version Number

LPI2C_PARAM_MRXFIFO

#define LPI2C_PARAM_MRXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)

MRXFIFO - Master Receive FIFO Size

LPI2C_PARAM_MTXFIFO

#define LPI2C_PARAM_MTXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

MTXFIFO - Master Transmit FIFO Size

LPI2C_VERID_FEATURE

#define LPI2C_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000010..Master only, with standard feature set 0b0000000000000011..Master and slave, with standard feature set

LPI2C_VERID_MAJOR

#define LPI2C_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)

MAJOR - Major Version Number

LPI2C_VERID_MINOR

#define LPI2C_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

MINOR - Minor Version Number

LPSPI_PARAM_RXFIFO

#define LPSPI_PARAM_RXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)

RXFIFO - Receive FIFO Size

LPSPI_PARAM_TXFIFO

#define LPSPI_PARAM_TXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)

TXFIFO - Transmit FIFO Size

LPSPI_VERID_FEATURE

#define LPSPI_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)

FEATURE - Module Identification Number 0b0000000000000100..Standard feature set supporting a 32-bit shift register.

LPSPI_VERID_MAJOR

#define LPSPI_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)

MAJOR - Major Version Number

LPSPI_VERID_MINOR

#define LPSPI_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)

MINOR - Minor Version Number

LPUART_PARAM_RXFIFO

#define LPUART_PARAM_RXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

RXFIFO - Receive FIFO Size

LPUART_PARAM_TXFIFO

#define LPUART_PARAM_TXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

TXFIFO - Transmit FIFO Size

LPUART_VERID_FEATURE

#define LPUART_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

FEATURE - Feature Identification Number 0b0000000000000001..Standard feature set. 0b0000000000000011..Standard feature set with MODEM/IrDA support.

LPUART_VERID_MAJOR

#define LPUART_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

MAJOR - Major Version Number

LPUART_VERID_MINOR

#define LPUART_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

MINOR - Minor Version Number