RTEMS 6.1-rc4
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CS - Watchdog Control and Status Register | |
#define | RTWDOG_CS_STOP_MASK (0x1U) |
#define | RTWDOG_CS_STOP_SHIFT (0U) |
#define | RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) |
#define | RTWDOG_CS_WAIT_MASK (0x2U) |
#define | RTWDOG_CS_WAIT_SHIFT (1U) |
#define | RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) |
#define | RTWDOG_CS_DBG_MASK (0x4U) |
#define | RTWDOG_CS_DBG_SHIFT (2U) |
#define | RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) |
#define | RTWDOG_CS_TST_MASK (0x18U) |
#define | RTWDOG_CS_TST_SHIFT (3U) |
#define | RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) |
#define | RTWDOG_CS_UPDATE_MASK (0x20U) |
#define | RTWDOG_CS_UPDATE_SHIFT (5U) |
#define | RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) |
#define | RTWDOG_CS_INT_MASK (0x40U) |
#define | RTWDOG_CS_INT_SHIFT (6U) |
#define | RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) |
#define | RTWDOG_CS_EN_MASK (0x80U) |
#define | RTWDOG_CS_EN_SHIFT (7U) |
#define | RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) |
#define | RTWDOG_CS_CLK_MASK (0x300U) |
#define | RTWDOG_CS_CLK_SHIFT (8U) |
#define | RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) |
#define | RTWDOG_CS_RCS_MASK (0x400U) |
#define | RTWDOG_CS_RCS_SHIFT (10U) |
#define | RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) |
#define | RTWDOG_CS_ULK_MASK (0x800U) |
#define | RTWDOG_CS_ULK_SHIFT (11U) |
#define | RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) |
#define | RTWDOG_CS_PRES_MASK (0x1000U) |
#define | RTWDOG_CS_PRES_SHIFT (12U) |
#define | RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) |
#define | RTWDOG_CS_CMD32EN_MASK (0x2000U) |
#define | RTWDOG_CS_CMD32EN_SHIFT (13U) |
#define | RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) |
#define | RTWDOG_CS_FLG_MASK (0x4000U) |
#define | RTWDOG_CS_FLG_SHIFT (14U) |
#define | RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) |
#define | RTWDOG_CS_WIN_MASK (0x8000U) |
#define | RTWDOG_CS_WIN_SHIFT (15U) |
#define | RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) |
CNT - Watchdog Counter Register | |
#define | RTWDOG_CNT_CNTLOW_MASK (0xFFU) |
#define | RTWDOG_CNT_CNTLOW_SHIFT (0U) |
#define | RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) |
#define | RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) |
#define | RTWDOG_CNT_CNTHIGH_SHIFT (8U) |
#define | RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) |
TOVAL - Watchdog Timeout Value Register | |
#define | RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) |
#define | RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) |
#define | RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) |
#define | RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) |
#define | RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) |
#define | RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) |
WIN - Watchdog Window Register | |
#define | RTWDOG_WIN_WINLOW_MASK (0xFFU) |
#define | RTWDOG_WIN_WINLOW_SHIFT (0U) |
#define | RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) |
#define | RTWDOG_WIN_WINHIGH_MASK (0xFF00U) |
#define | RTWDOG_WIN_WINHIGH_SHIFT (8U) |
#define | RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) |
CS - Watchdog Control and Status Register | |
#define | RTWDOG_CS_STOP_MASK (0x1U) |
#define | RTWDOG_CS_STOP_SHIFT (0U) |
#define | RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) |
#define | RTWDOG_CS_WAIT_MASK (0x2U) |
#define | RTWDOG_CS_WAIT_SHIFT (1U) |
#define | RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) |
#define | RTWDOG_CS_DBG_MASK (0x4U) |
#define | RTWDOG_CS_DBG_SHIFT (2U) |
#define | RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) |
#define | RTWDOG_CS_TST_MASK (0x18U) |
#define | RTWDOG_CS_TST_SHIFT (3U) |
#define | RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) |
#define | RTWDOG_CS_UPDATE_MASK (0x20U) |
#define | RTWDOG_CS_UPDATE_SHIFT (5U) |
#define | RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) |
#define | RTWDOG_CS_INT_MASK (0x40U) |
#define | RTWDOG_CS_INT_SHIFT (6U) |
#define | RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) |
#define | RTWDOG_CS_EN_MASK (0x80U) |
#define | RTWDOG_CS_EN_SHIFT (7U) |
#define | RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) |
#define | RTWDOG_CS_CLK_MASK (0x300U) |
#define | RTWDOG_CS_CLK_SHIFT (8U) |
#define | RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) |
#define | RTWDOG_CS_RCS_MASK (0x400U) |
#define | RTWDOG_CS_RCS_SHIFT (10U) |
#define | RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) |
#define | RTWDOG_CS_ULK_MASK (0x800U) |
#define | RTWDOG_CS_ULK_SHIFT (11U) |
#define | RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) |
#define | RTWDOG_CS_PRES_MASK (0x1000U) |
#define | RTWDOG_CS_PRES_SHIFT (12U) |
#define | RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) |
#define | RTWDOG_CS_CMD32EN_MASK (0x2000U) |
#define | RTWDOG_CS_CMD32EN_SHIFT (13U) |
#define | RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) |
#define | RTWDOG_CS_FLG_MASK (0x4000U) |
#define | RTWDOG_CS_FLG_SHIFT (14U) |
#define | RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) |
#define | RTWDOG_CS_WIN_MASK (0x8000U) |
#define | RTWDOG_CS_WIN_SHIFT (15U) |
#define | RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) |
CNT - Watchdog Counter Register | |
#define | RTWDOG_CNT_CNTLOW_MASK (0xFFU) |
#define | RTWDOG_CNT_CNTLOW_SHIFT (0U) |
#define | RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) |
#define | RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) |
#define | RTWDOG_CNT_CNTHIGH_SHIFT (8U) |
#define | RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) |
TOVAL - Watchdog Timeout Value Register | |
#define | RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) |
#define | RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) |
#define | RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) |
#define | RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) |
#define | RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) |
#define | RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) |
WIN - Watchdog Window Register | |
#define | RTWDOG_WIN_WINLOW_MASK (0xFFU) |
#define | RTWDOG_WIN_WINLOW_SHIFT (0U) |
#define | RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) |
#define | RTWDOG_WIN_WINHIGH_MASK (0xFF00U) |
#define | RTWDOG_WIN_WINHIGH_SHIFT (8U) |
#define | RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) |
CS - Watchdog Control and Status Register | |
#define | RTWDOG_CS_STOP_MASK (0x1U) |
#define | RTWDOG_CS_STOP_SHIFT (0U) |
#define | RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) |
#define | RTWDOG_CS_WAIT_MASK (0x2U) |
#define | RTWDOG_CS_WAIT_SHIFT (1U) |
#define | RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) |
#define | RTWDOG_CS_DBG_MASK (0x4U) |
#define | RTWDOG_CS_DBG_SHIFT (2U) |
#define | RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) |
#define | RTWDOG_CS_TST_MASK (0x18U) |
#define | RTWDOG_CS_TST_SHIFT (3U) |
#define | RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) |
#define | RTWDOG_CS_UPDATE_MASK (0x20U) |
#define | RTWDOG_CS_UPDATE_SHIFT (5U) |
#define | RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) |
#define | RTWDOG_CS_INT_MASK (0x40U) |
#define | RTWDOG_CS_INT_SHIFT (6U) |
#define | RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) |
#define | RTWDOG_CS_EN_MASK (0x80U) |
#define | RTWDOG_CS_EN_SHIFT (7U) |
#define | RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) |
#define | RTWDOG_CS_CLK_MASK (0x300U) |
#define | RTWDOG_CS_CLK_SHIFT (8U) |
#define | RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) |
#define | RTWDOG_CS_RCS_MASK (0x400U) |
#define | RTWDOG_CS_RCS_SHIFT (10U) |
#define | RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) |
#define | RTWDOG_CS_ULK_MASK (0x800U) |
#define | RTWDOG_CS_ULK_SHIFT (11U) |
#define | RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) |
#define | RTWDOG_CS_PRES_MASK (0x1000U) |
#define | RTWDOG_CS_PRES_SHIFT (12U) |
#define | RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) |
#define | RTWDOG_CS_CMD32EN_MASK (0x2000U) |
#define | RTWDOG_CS_CMD32EN_SHIFT (13U) |
#define | RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) |
#define | RTWDOG_CS_FLG_MASK (0x4000U) |
#define | RTWDOG_CS_FLG_SHIFT (14U) |
#define | RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) |
#define | RTWDOG_CS_WIN_MASK (0x8000U) |
#define | RTWDOG_CS_WIN_SHIFT (15U) |
#define | RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) |
CNT - Watchdog Counter Register | |
#define | RTWDOG_CNT_CNTLOW_MASK (0xFFU) |
#define | RTWDOG_CNT_CNTLOW_SHIFT (0U) |
#define | RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) |
#define | RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) |
#define | RTWDOG_CNT_CNTHIGH_SHIFT (8U) |
#define | RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) |
TOVAL - Watchdog Timeout Value Register | |
#define | RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) |
#define | RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) |
#define | RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) |
#define | RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) |
#define | RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) |
#define | RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) |
WIN - Watchdog Window Register | |
#define | RTWDOG_WIN_WINLOW_MASK (0xFFU) |
#define | RTWDOG_WIN_WINLOW_SHIFT (0U) |
#define | RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) |
#define | RTWDOG_WIN_WINHIGH_MASK (0xFF00U) |
#define | RTWDOG_WIN_WINHIGH_SHIFT (8U) |
#define | RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) |
#define RTWDOG_CNT_CNTHIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) |
CNTHIGH - High byte of the Watchdog Counter
#define RTWDOG_CNT_CNTHIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) |
CNTHIGH - High byte of the Watchdog Counter
#define RTWDOG_CNT_CNTHIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) |
CNTHIGH - High byte of the Watchdog Counter
#define RTWDOG_CNT_CNTLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) |
CNTLOW - Low byte of the Watchdog Counter
#define RTWDOG_CNT_CNTLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) |
CNTLOW - Low byte of the Watchdog Counter
#define RTWDOG_CNT_CNTLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) |
CNTLOW - Low byte of the Watchdog Counter
#define RTWDOG_CS_CLK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) |
CLK - Watchdog Clock
#define RTWDOG_CS_CLK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) |
CLK - Watchdog Clock
#define RTWDOG_CS_CLK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) |
CLK - Watchdog Clock
#define RTWDOG_CS_CMD32EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) |
CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
#define RTWDOG_CS_CMD32EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) |
CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
#define RTWDOG_CS_CMD32EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) |
CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
#define RTWDOG_CS_DBG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) |
DBG - Debug Enable 0b0..Watchdog disabled in chip debug mode. 0b1..Watchdog enabled in chip debug mode.
#define RTWDOG_CS_DBG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) |
DBG - Debug Enable 0b0..Watchdog disabled in chip debug mode. 0b1..Watchdog enabled in chip debug mode.
#define RTWDOG_CS_DBG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) |
DBG - Debug Enable 0b0..Watchdog disabled in chip debug mode. 0b1..Watchdog enabled in chip debug mode.
#define RTWDOG_CS_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) |
EN - Watchdog Enable 0b0..Watchdog disabled. 0b1..Watchdog enabled.
#define RTWDOG_CS_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) |
EN - Watchdog Enable 0b0..Watchdog disabled. 0b1..Watchdog enabled.
#define RTWDOG_CS_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) |
EN - Watchdog Enable 0b0..Watchdog disabled. 0b1..Watchdog enabled.
#define RTWDOG_CS_FLG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) |
FLG - Watchdog Interrupt Flag 0b0..No interrupt occurred. 0b1..An interrupt occurred.
#define RTWDOG_CS_FLG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) |
FLG - Watchdog Interrupt Flag 0b0..No interrupt occurred. 0b1..An interrupt occurred.
#define RTWDOG_CS_FLG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) |
FLG - Watchdog Interrupt Flag 0b0..No interrupt occurred. 0b1..An interrupt occurred.
#define RTWDOG_CS_INT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) |
INT - Watchdog Interrupt 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 255 bus clocks from the interrupt vector fetch.
#define RTWDOG_CS_INT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) |
INT - Watchdog Interrupt 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 255 bus clocks from the interrupt vector fetch.
#define RTWDOG_CS_INT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) |
INT - Watchdog Interrupt 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 255 bus clocks from the interrupt vector fetch.
#define RTWDOG_CS_PRES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) |
PRES - Watchdog prescaler 0b0..256 prescaler disabled. 0b1..256 prescaler enabled.
#define RTWDOG_CS_PRES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) |
PRES - Watchdog prescaler 0b0..256 prescaler disabled. 0b1..256 prescaler enabled.
#define RTWDOG_CS_PRES | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) |
PRES - Watchdog prescaler 0b0..256 prescaler disabled. 0b1..256 prescaler enabled.
#define RTWDOG_CS_RCS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) |
RCS - Reconfiguration Success 0b0..Reconfiguring WDOG. 0b1..Reconfiguration is successful.
#define RTWDOG_CS_RCS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) |
RCS - Reconfiguration Success 0b0..Reconfiguring WDOG. 0b1..Reconfiguration is successful.
#define RTWDOG_CS_RCS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) |
RCS - Reconfiguration Success 0b0..Reconfiguring WDOG. 0b1..Reconfiguration is successful.
#define RTWDOG_CS_STOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) |
STOP - Stop Enable 0b0..Watchdog disabled in chip stop mode. 0b1..Watchdog enabled in chip stop mode.
#define RTWDOG_CS_STOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) |
STOP - Stop Enable 0b0..Watchdog disabled in chip stop mode. 0b1..Watchdog enabled in chip stop mode.
#define RTWDOG_CS_STOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) |
STOP - Stop Enable 0b0..Watchdog disabled in chip stop mode. 0b1..Watchdog enabled in chip stop mode.
#define RTWDOG_CS_TST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) |
TST - Watchdog Test 0b00..Watchdog test mode disabled. 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
#define RTWDOG_CS_TST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) |
TST - Watchdog Test 0b00..Watchdog test mode disabled. 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
#define RTWDOG_CS_TST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) |
TST - Watchdog Test 0b00..Watchdog test mode disabled. 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
#define RTWDOG_CS_ULK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) |
ULK - Unlock status 0b0..WDOG is locked. 0b1..WDOG is unlocked.
#define RTWDOG_CS_ULK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) |
ULK - Unlock status 0b0..WDOG is locked. 0b1..WDOG is unlocked.
#define RTWDOG_CS_ULK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) |
ULK - Unlock status 0b0..WDOG is locked. 0b1..WDOG is unlocked.
#define RTWDOG_CS_UPDATE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) |
UPDATE - Allow updates 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 0b1..Updates allowed. Software can modify the watchdog configuration registers within 255 bus clocks after performing the unlock write sequence.
#define RTWDOG_CS_UPDATE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) |
UPDATE - Allow updates 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 0b1..Updates allowed. Software can modify the watchdog configuration registers within 255 bus clocks after performing the unlock write sequence.
#define RTWDOG_CS_UPDATE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) |
UPDATE - Allow updates 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 0b1..Updates allowed. Software can modify the watchdog configuration registers within 255 bus clocks after performing the unlock write sequence.
#define RTWDOG_CS_WAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) |
WAIT - Wait Enable 0b0..Watchdog disabled in chip wait mode. 0b1..Watchdog enabled in chip wait mode.
#define RTWDOG_CS_WAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) |
WAIT - Wait Enable 0b0..Watchdog disabled in chip wait mode. 0b1..Watchdog enabled in chip wait mode.
#define RTWDOG_CS_WAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) |
WAIT - Wait Enable 0b0..Watchdog disabled in chip wait mode. 0b1..Watchdog enabled in chip wait mode.
#define RTWDOG_CS_WIN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) |
WIN - Watchdog Window 0b0..Window mode disabled. 0b1..Window mode enabled.
#define RTWDOG_CS_WIN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) |
WIN - Watchdog Window 0b0..Window mode disabled. 0b1..Window mode enabled.
#define RTWDOG_CS_WIN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) |
WIN - Watchdog Window 0b0..Window mode disabled. 0b1..Window mode enabled.
#define RTWDOG_TOVAL_TOVALHIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) |
TOVALHIGH - High byte of the timeout value
#define RTWDOG_TOVAL_TOVALHIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) |
TOVALHIGH - High byte of the timeout value
#define RTWDOG_TOVAL_TOVALHIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) |
TOVALHIGH - High byte of the timeout value
#define RTWDOG_TOVAL_TOVALLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) |
TOVALLOW - Low byte of the timeout value
#define RTWDOG_TOVAL_TOVALLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) |
TOVALLOW - Low byte of the timeout value
#define RTWDOG_TOVAL_TOVALLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) |
TOVALLOW - Low byte of the timeout value
#define RTWDOG_WIN_WINHIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) |
WINHIGH - High byte of Watchdog Window
#define RTWDOG_WIN_WINHIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) |
WINHIGH - High byte of Watchdog Window
#define RTWDOG_WIN_WINHIGH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) |
WINHIGH - High byte of Watchdog Window
#define RTWDOG_WIN_WINLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) |
WINLOW - Low byte of Watchdog Window
#define RTWDOG_WIN_WINLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) |
WINLOW - Low byte of Watchdog Window
#define RTWDOG_WIN_WINLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) |
WINLOW - Low byte of Watchdog Window