Macros
#define	RDC_SEMAPHORE_GATE_COUNT (64U)

#define	RDC_SEMAPHORE_GATE_COUNT (64U)

GATE - Gate Register
#define	RDC_SEMAPHORE_GATE_GTFSM_MASK (0xFU)

#define	RDC_SEMAPHORE_GATE_GTFSM_SHIFT (0U)

#define	RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE_GTFSM_MASK)

#define	RDC_SEMAPHORE_GATE_LDOM_MASK (0x30U)

#define	RDC_SEMAPHORE_GATE_LDOM_SHIFT (4U)

#define	RDC_SEMAPHORE_GATE_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE_LDOM_MASK)

RSTGT_R - Reset Gate Read
#define	RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)

RSTGT_W - Reset Gate Write
#define	RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU)

#define	RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U)

#define	RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)

#define	RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U)

#define	RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U)

#define	RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)

GATE - Gate Register
#define	RDC_SEMAPHORE_GATE_GTFSM_MASK (0xFU)

#define	RDC_SEMAPHORE_GATE_GTFSM_SHIFT (0U)

#define	RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE_GTFSM_MASK)

#define	RDC_SEMAPHORE_GATE_LDOM_MASK (0x30U)

#define	RDC_SEMAPHORE_GATE_LDOM_SHIFT (4U)

#define	RDC_SEMAPHORE_GATE_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE_LDOM_MASK)

RSTGT_R - Reset Gate Read
#define	RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U)

#define	RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)

RSTGT_W - Reset Gate Write
#define	RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU)

#define	RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U)

#define	RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)

#define	RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U)

#define	RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U)

#define	RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)

Detailed Description

Macro Definition Documentation

◆ RDC_SEMAPHORE_GATE_GTFSM [1/2]

#define RDC_SEMAPHORE_GATE_GTFSM ( x ) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE_GTFSM_MASK)

GTFSM - Gate Finite State Machine. 0b0000..The gate is unlocked (free). 0b0001..The gate has been locked by processor with master_index = 0. 0b0010..The gate has been locked by processor with master_index = 1. 0b0011..The gate has been locked by processor with master_index = 2. 0b0100..The gate has been locked by processor with master_index = 3. 0b0101..The gate has been locked by processor with master_index = 4. 0b0110..The gate has been locked by processor with master_index = 5. 0b0111..The gate has been locked by processor with master_index = 6. 0b1000..The gate has been locked by processor with master_index = 7. 0b1001..The gate has been locked by processor with master_index = 8. 0b1010..The gate has been locked by processor with master_index = 9. 0b1011..The gate has been locked by processor with master_index = 10. 0b1100..The gate has been locked by processor with master_index = 11. 0b1101..The gate has been locked by processor with master_index = 12. 0b1110..The gate has been locked by processor with master_index = 13. 0b1111..The gate has been locked by processor with master_index = 14.

◆ RDC_SEMAPHORE_GATE_GTFSM [2/2]

#define RDC_SEMAPHORE_GATE_GTFSM ( x ) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE_GTFSM_MASK)

GTFSM - Gate Finite State Machine. 0b0000..The gate is unlocked (free). 0b0001..The gate has been locked by processor with master_index = 0. 0b0010..The gate has been locked by processor with master_index = 1. 0b0011..The gate has been locked by processor with master_index = 2. 0b0100..The gate has been locked by processor with master_index = 3. 0b0101..The gate has been locked by processor with master_index = 4. 0b0110..The gate has been locked by processor with master_index = 5. 0b0111..The gate has been locked by processor with master_index = 6. 0b1000..The gate has been locked by processor with master_index = 7. 0b1001..The gate has been locked by processor with master_index = 8. 0b1010..The gate has been locked by processor with master_index = 9. 0b1011..The gate has been locked by processor with master_index = 10. 0b1100..The gate has been locked by processor with master_index = 11. 0b1101..The gate has been locked by processor with master_index = 12. 0b1110..The gate has been locked by processor with master_index = 13. 0b1111..The gate has been locked by processor with master_index = 14.

◆ RDC_SEMAPHORE_GATE_LDOM [1/2]

#define RDC_SEMAPHORE_GATE_LDOM ( x ) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE_LDOM_MASK)

LDOM 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.) 0b01..The gate has been locked by domain 1. 0b10..Reserved 0b11..Reserved

◆ RDC_SEMAPHORE_GATE_LDOM [2/2]

#define RDC_SEMAPHORE_GATE_LDOM ( x ) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE_LDOM_MASK)

LDOM 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.) 0b01..The gate has been locked by domain 1. 0b10..Reserved 0b11..Reserved

◆ RDC_SEMAPHORE_RSTGT_R_RSTGSM [1/2]

#define RDC_SEMAPHORE_RSTGT_R_RSTGSM ( x ) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)

RSTGSM 0b00..Idle, waiting for the first data pattern write. 0b01..Waiting for the second data pattern write. 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists for only one clock cycle. Software will never be able to observe this state. 0b11..This state encoding is never used and therefore reserved.

◆ RDC_SEMAPHORE_RSTGT_R_RSTGSM [2/2]