I2S Peripheral Access Layer

Modules
	I2S Register Masks

Data Structures
struct	I2S_Type

Macros
#define	SAI1_BASE   (0x40384000u)
#define	SAI1   ((I2S_Type *)SAI1_BASE)
#define	SAI2_BASE   (0x40388000u)
#define	SAI2   ((I2S_Type *)SAI2_BASE)
#define	SAI3_BASE   (0x4038C000u)
#define	SAI3   ((I2S_Type *)SAI3_BASE)
#define	I2S_BASE_ADDRS   { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }
#define	I2S_BASE_PTRS   { (I2S_Type *)0u, SAI1, SAI2, SAI3 }
#define	I2S_RX_IRQS   { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }
#define	I2S_TX_IRQS   { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }
#define	SAI1_BASE   (0x40404000u)
#define	SAI1   ((I2S_Type *)SAI1_BASE)
#define	SAI2_BASE   (0x40408000u)
#define	SAI2   ((I2S_Type *)SAI2_BASE)
#define	SAI3_BASE   (0x4040C000u)
#define	SAI3   ((I2S_Type *)SAI3_BASE)
#define	SAI4_BASE   (0x40C40000u)
#define	SAI4   ((I2S_Type *)SAI4_BASE)
#define	I2S_BASE_ADDRS   { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }
#define	I2S_BASE_PTRS   { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }
#define	I2S_RX_IRQS   { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn, SAI4_RX_IRQn }
#define	I2S_TX_IRQS   { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn, SAI4_TX_IRQn }
#define	SAI1_BASE   (0x40404000u)
#define	SAI1   ((I2S_Type *)SAI1_BASE)
#define	SAI2_BASE   (0x40408000u)
#define	SAI2   ((I2S_Type *)SAI2_BASE)
#define	SAI3_BASE   (0x4040C000u)
#define	SAI3   ((I2S_Type *)SAI3_BASE)
#define	SAI4_BASE   (0x40C40000u)
#define	SAI4   ((I2S_Type *)SAI4_BASE)
#define	I2S_BASE_ADDRS   { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }
#define	I2S_BASE_PTRS   { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }
#define	I2S_RX_IRQS   { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn, SAI4_RX_IRQn }
#define	I2S_TX_IRQS   { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn, SAI4_TX_IRQn }

Detailed Description

Macro Definition Documentation

I2S_BASE_ADDRS [1/3]

#define I2S_BASE_ADDRS   { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }

Array initializer of I2S peripheral base addresses

I2S_BASE_ADDRS [2/3]

#define I2S_BASE_ADDRS   { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }

Array initializer of I2S peripheral base addresses

I2S_BASE_ADDRS [3/3]

#define I2S_BASE_ADDRS   { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }

Array initializer of I2S peripheral base addresses

I2S_BASE_PTRS [1/3]

#define I2S_BASE_PTRS   { (I2S_Type *)0u, SAI1, SAI2, SAI3 }

Array initializer of I2S peripheral base pointers

I2S_BASE_PTRS [2/3]

#define I2S_BASE_PTRS   { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }

Array initializer of I2S peripheral base pointers

I2S_BASE_PTRS [3/3]

#define I2S_BASE_PTRS   { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }

Array initializer of I2S peripheral base pointers

I2S_RX_IRQS [1/3]

#define I2S_RX_IRQS   { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }

Interrupt vectors for the I2S peripheral type

I2S_RX_IRQS [2/3]

#define I2S_RX_IRQS   { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn, SAI4_RX_IRQn }

Interrupt vectors for the I2S peripheral type

I2S_RX_IRQS [3/3]

#define I2S_RX_IRQS   { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn, SAI4_RX_IRQn }

Interrupt vectors for the I2S peripheral type

SAI1 [1/3]

#define SAI1   ((I2S_Type *)SAI1_BASE)

Peripheral SAI1 base pointer

SAI1 [2/3]

#define SAI1   ((I2S_Type *)SAI1_BASE)

Peripheral SAI1 base pointer

SAI1 [3/3]

#define SAI1   ((I2S_Type *)SAI1_BASE)

Peripheral SAI1 base pointer

SAI1_BASE [1/3]

#define SAI1_BASE   (0x40384000u)

Peripheral SAI1 base address

SAI1_BASE [2/3]

#define SAI1_BASE   (0x40404000u)

Peripheral SAI1 base address

SAI1_BASE [3/3]

#define SAI1_BASE   (0x40404000u)

Peripheral SAI1 base address

SAI2 [1/3]

#define SAI2   ((I2S_Type *)SAI2_BASE)

Peripheral SAI2 base pointer

SAI2 [2/3]

#define SAI2   ((I2S_Type *)SAI2_BASE)

Peripheral SAI2 base pointer

SAI2 [3/3]

#define SAI2   ((I2S_Type *)SAI2_BASE)

Peripheral SAI2 base pointer

SAI2_BASE [1/3]

#define SAI2_BASE   (0x40388000u)

Peripheral SAI2 base address

SAI2_BASE [2/3]

#define SAI2_BASE   (0x40408000u)

Peripheral SAI2 base address

SAI2_BASE [3/3]

#define SAI2_BASE   (0x40408000u)

Peripheral SAI2 base address

SAI3 [1/3]

#define SAI3   ((I2S_Type *)SAI3_BASE)

Peripheral SAI3 base pointer

SAI3 [2/3]

#define SAI3   ((I2S_Type *)SAI3_BASE)

Peripheral SAI3 base pointer

SAI3 [3/3]

#define SAI3   ((I2S_Type *)SAI3_BASE)

Peripheral SAI3 base pointer

SAI3_BASE [1/3]

#define SAI3_BASE   (0x4038C000u)

Peripheral SAI3 base address

SAI3_BASE [2/3]

#define SAI3_BASE   (0x4040C000u)

Peripheral SAI3 base address

SAI3_BASE [3/3]

#define SAI3_BASE   (0x4040C000u)

Peripheral SAI3 base address

SAI4 [1/2]

#define SAI4   ((I2S_Type *)SAI4_BASE)

Peripheral SAI4 base pointer

SAI4 [2/2]

#define SAI4   ((I2S_Type *)SAI4_BASE)

Peripheral SAI4 base pointer

SAI4_BASE [1/2]

#define SAI4_BASE   (0x40C40000u)

Peripheral SAI4 base address

SAI4_BASE [2/2]

#define SAI4_BASE   (0x40C40000u)

Peripheral SAI4 base address