RTEMS 6.1-rc4
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VIDEO_MUX Register Masks
Mapping Information » Iomuxc_pads » Device Peripheral Access Layer » VIDEO_MUX Peripheral Access Layer

VID_MUX_CTRL - Video mux Control Register

#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK   (0x1U)
 
#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT   (0U)
 
#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK)
 
#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK   (0x2U)
 
#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT   (1U)
 
#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK)
 
#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK   (0x4U)
 
#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT   (2U)
 
#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK)
 
#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK   (0x8U)
 
#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT   (3U)
 
#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK)
 

PLM_CTRL - Pixel Link Master(PLM) Control Register

#define VIDEO_MUX_PLM_CTRL_ENABLE_MASK   (0x1U)
 
#define VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT   (0U)
 
#define VIDEO_MUX_PLM_CTRL_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT)) & VIDEO_MUX_PLM_CTRL_ENABLE_MASK)
 
#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK   (0x2U)
 
#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT   (1U)
 
#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK)
 
#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK   (0x4U)
 
#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT   (2U)
 
#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK)
 
#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK   (0x8U)
 
#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT   (3U)
 
#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK)
 
#define VIDEO_MUX_PLM_CTRL_POLARITY_MASK   (0x10U)
 
#define VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT   (4U)
 
#define VIDEO_MUX_PLM_CTRL_POLARITY(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT)) & VIDEO_MUX_PLM_CTRL_POLARITY_MASK)
 

YUV420_CTRL - YUV420 Control Register

#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK   (0x1U)
 
#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT   (0U)
 
#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT)) & VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK)
 

CFG_DT_DISABLE - Data Disable Register

#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK   (0xFFFFFFU)
 
#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT   (0U)
 
#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK)
 

MIPI_DSI_CTRL - MIPI DSI Control Register

#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK   (0x1U)
 
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT   (0U)
 
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK)
 
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK   (0x2U)
 
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT   (1U)
 
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK)
 

VID_MUX_CTRL - Video mux Control Register

#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK   (0x1U)
 
#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT   (0U)
 
#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK)
 
#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK   (0x2U)
 
#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT   (1U)
 
#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK)
 
#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK   (0x4U)
 
#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT   (2U)
 
#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK)
 
#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK   (0x8U)
 
#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT   (3U)
 
#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK)
 

PLM_CTRL - Pixel Link Master(PLM) Control Register

#define VIDEO_MUX_PLM_CTRL_ENABLE_MASK   (0x1U)
 
#define VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT   (0U)
 
#define VIDEO_MUX_PLM_CTRL_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT)) & VIDEO_MUX_PLM_CTRL_ENABLE_MASK)
 
#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK   (0x2U)
 
#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT   (1U)
 
#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK)
 
#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK   (0x4U)
 
#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT   (2U)
 
#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK)
 
#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK   (0x8U)
 
#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT   (3U)
 
#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK)
 
#define VIDEO_MUX_PLM_CTRL_POLARITY_MASK   (0x10U)
 
#define VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT   (4U)
 
#define VIDEO_MUX_PLM_CTRL_POLARITY(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT)) & VIDEO_MUX_PLM_CTRL_POLARITY_MASK)
 

YUV420_CTRL - YUV420 Control Register

#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK   (0x1U)
 
#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT   (0U)
 
#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT)) & VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK)
 

CFG_DT_DISABLE - Data Disable Register

#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK   (0xFFFFFFU)
 
#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT   (0U)
 
#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK)
 

MIPI_DSI_CTRL - MIPI DSI Control Register

#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK   (0x1U)
 
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT   (0U)
 
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK)
 
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK   (0x2U)
 
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT   (1U)
 
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK)
 

Detailed Description

Macro Definition Documentation

◆ VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE [1/2]

#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK)

CFG_DT_DISABLE - Data Type Disable

◆ VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE [2/2]

#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK)

CFG_DT_DISABLE - Data Type Disable

◆ VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM [1/2]

#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK)

DPI_CM - Color Mode control 0b0..Normal Mode 0b1..Low-color mode

◆ VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM [2/2]

#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK)

DPI_CM - Color Mode control 0b0..Normal Mode 0b1..Low-color mode

◆ VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD [1/2]

#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK)

DPI_SD - Shut Down - Control to shutdown display (type 4 only) 0b0..No effect 0b1..Send shutdown command

◆ VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD [2/2]

#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK)

DPI_SD - Shut Down - Control to shutdown display (type 4 only) 0b0..No effect 0b1..Send shutdown command

◆ VIDEO_MUX_PLM_CTRL_ENABLE [1/2]

#define VIDEO_MUX_PLM_CTRL_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT)) & VIDEO_MUX_PLM_CTRL_ENABLE_MASK)

ENABLE - Enable the output of HYSNC and VSYNC 0b0..No active HSYNC and VSYNC output 0b1..Active HSYNC and VSYNC output

◆ VIDEO_MUX_PLM_CTRL_ENABLE [2/2]

#define VIDEO_MUX_PLM_CTRL_ENABLE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT)) & VIDEO_MUX_PLM_CTRL_ENABLE_MASK)

ENABLE - Enable the output of HYSNC and VSYNC 0b0..No active HSYNC and VSYNC output 0b1..Active HSYNC and VSYNC output

◆ VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE [1/2]

#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK)

HSYNC_OVERRIDE - HSYNC override 0b1..HSYNC is asserted 0b0..HSYNC is not asserted

◆ VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE [2/2]

#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK)

HSYNC_OVERRIDE - HSYNC override 0b1..HSYNC is asserted 0b0..HSYNC is not asserted

◆ VIDEO_MUX_PLM_CTRL_POLARITY [1/2]

#define VIDEO_MUX_PLM_CTRL_POLARITY (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT)) & VIDEO_MUX_PLM_CTRL_POLARITY_MASK)

POLARITY - Polarity of HYSNC/VSYNC 0b0..Keep the current polarity of HSYNC and VSYNC 0b1..Invert the polarity of HSYNC and VSYNC

◆ VIDEO_MUX_PLM_CTRL_POLARITY [2/2]

#define VIDEO_MUX_PLM_CTRL_POLARITY (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT)) & VIDEO_MUX_PLM_CTRL_POLARITY_MASK)

POLARITY - Polarity of HYSNC/VSYNC 0b0..Keep the current polarity of HSYNC and VSYNC 0b1..Invert the polarity of HSYNC and VSYNC

◆ VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE [1/2]

#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK)

VALID_OVERRIDE - Valid override 0b0..HSYNC and VSYNC is asserted 0b1..HSYNC and VSYNC is not asserted

◆ VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE [2/2]

#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK)

VALID_OVERRIDE - Valid override 0b0..HSYNC and VSYNC is asserted 0b1..HSYNC and VSYNC is not asserted

◆ VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE [1/2]

#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK)

VSYNC_OVERRIDE - VSYNC override 0b1..VSYNC is asserted 0b0..VSYNC is not asserted

◆ VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE [2/2]

#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK)

VSYNC_OVERRIDE - VSYNC override 0b1..VSYNC is asserted 0b0..VSYNC is not asserted

◆ VIDEO_MUX_VID_MUX_CTRL_CSI_SEL [1/2]

#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK)

CSI_SEL - CSI sensor data input mux selector 0b0..CSI sensor data is from Parallel CSI 0b1..CSI sensor data is from MIPI CSI

◆ VIDEO_MUX_VID_MUX_CTRL_CSI_SEL [2/2]

#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK)

CSI_SEL - CSI sensor data input mux selector 0b0..CSI sensor data is from Parallel CSI 0b1..CSI sensor data is from MIPI CSI

◆ VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL [1/2]

#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK)

LCDIF2_SEL - LCDIF2 sensor data input mux selector 0b0..LCDIFv2 sensor data is from Parallel CSI 0b1..LCDIFv2 sensor data is from MIPI CSI

◆ VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL [2/2]

#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK)

LCDIF2_SEL - LCDIF2 sensor data input mux selector 0b0..LCDIFv2 sensor data is from Parallel CSI 0b1..LCDIFv2 sensor data is from MIPI CSI

◆ VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL [1/2]

#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK)

MIPI_DSI_SEL - MIPI DSI video data input mux selector 0b0..MIPI DSI video data is from eLCDIF 0b1..MIPI DSI video data is from LCDIFv2

◆ VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL [2/2]

#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK)

MIPI_DSI_SEL - MIPI DSI video data input mux selector 0b0..MIPI DSI video data is from eLCDIF 0b1..MIPI DSI video data is from LCDIFv2

◆ VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL [1/2]

#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK)

PARA_LCD_SEL - Parallel LCDIF video data input mux selector 0b0..Parallel LCDIF video data is from eLCDIF 0b1..Parallel LCDIF video data is from LCDIFv2

◆ VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL [2/2]

#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK)

PARA_LCD_SEL - Parallel LCDIF video data input mux selector 0b0..Parallel LCDIF video data is from eLCDIF 0b1..Parallel LCDIF video data is from LCDIFv2

◆ VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE [1/2]

#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT)) & VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK)

FST_LN_DATA_TYPE - Data type of First Line 0b0..Odd (default) 0b1..Even

◆ VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE [2/2]

#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE (   x)    (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT)) & VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK)

FST_LN_DATA_TYPE - Data type of First Line 0b0..Odd (default) 0b1..Even

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