Macros
#define	CAN_CS_COUNT (64U)

#define	CAN_ID_COUNT (64U)

#define	CAN_WORD0_COUNT (64U)

#define	CAN_WORD1_COUNT (64U)

#define	CAN_RXIMR_COUNT (64U)

#define	CAN_CS_COUNT_MB8B (64U)

#define	CAN_ID_COUNT_MB8B (64U)

#define	CAN_WORD_COUNT_MB8B (64U)

#define	CAN_WORD_COUNT_MB8B2 (2U)

#define	CAN_CS_COUNT_MB16B_L (21U)

#define	CAN_ID_COUNT_MB16B_L (21U)

#define	CAN_WORD_COUNT_MB16B_L (21U)

#define	CAN_WORD_COUNT_MB16B_L2 (4U)

#define	CAN_CS_COUNT_MB16B_H (21U)

#define	CAN_ID_COUNT_MB16B_H (21U)

#define	CAN_WORD_COUNT_MB16B_H (21U)

#define	CAN_WORD_COUNT_MB16B_H2 (4U)

#define	CAN_CS_COUNT_MB32B_L (12U)

#define	CAN_ID_COUNT_MB32B_L (12U)

#define	CAN_WORD_COUNT_MB32B_L (12U)

#define	CAN_WORD_COUNT_MB32B_L2 (8U)

#define	CAN_CS_COUNT_MB32B_H (12U)

#define	CAN_ID_COUNT_MB32B_H (12U)

#define	CAN_WORD_COUNT_MB32B_H (12U)

#define	CAN_WORD_COUNT_MB32B_H2 (8U)

#define	CAN_CS_COUNT_MB64B_L (7U)

#define	CAN_ID_COUNT_MB64B_L (7U)

#define	CAN_WORD_COUNT_MB64B_L (7U)

#define	CAN_WORD_COUNT_MB64B_L2 (16U)

#define	CAN_CS_COUNT_MB64B_H (7U)

#define	CAN_ID_COUNT_MB64B_H (7U)

#define	CAN_WORD_COUNT_MB64B_H (7U)

#define	CAN_WORD_COUNT_MB64B_H2 (16U)

#define	CAN_CS_COUNT (64U)

#define	CAN_ID_COUNT (64U)

#define	CAN_WORD0_COUNT (64U)

#define	CAN_WORD1_COUNT (64U)

#define	CAN_RXIMR_COUNT (64U)

#define	CAN_CS_COUNT_MB8B (64U)

#define	CAN_ID_COUNT_MB8B (64U)

#define	CAN_WORD_COUNT_MB8B (64U)

#define	CAN_WORD_COUNT_MB8B2 (2U)

#define	CAN_CS_COUNT_MB16B_L (21U)

#define	CAN_ID_COUNT_MB16B_L (21U)

#define	CAN_WORD_COUNT_MB16B_L (21U)

#define	CAN_WORD_COUNT_MB16B_L2 (4U)

#define	CAN_CS_COUNT_MB16B_H (21U)

#define	CAN_ID_COUNT_MB16B_H (21U)

#define	CAN_WORD_COUNT_MB16B_H (21U)

#define	CAN_WORD_COUNT_MB16B_H2 (4U)

#define	CAN_CS_COUNT_MB32B_L (12U)

#define	CAN_ID_COUNT_MB32B_L (12U)

#define	CAN_WORD_COUNT_MB32B_L (12U)

#define	CAN_WORD_COUNT_MB32B_L2 (8U)

#define	CAN_CS_COUNT_MB32B_H (12U)

#define	CAN_ID_COUNT_MB32B_H (12U)

#define	CAN_WORD_COUNT_MB32B_H (12U)

#define	CAN_WORD_COUNT_MB32B_H2 (8U)

#define	CAN_CS_COUNT_MB64B_L (7U)

#define	CAN_ID_COUNT_MB64B_L (7U)

#define	CAN_WORD_COUNT_MB64B_L (7U)

#define	CAN_WORD_COUNT_MB64B_L2 (16U)

#define	CAN_CS_COUNT_MB64B_H (7U)

#define	CAN_ID_COUNT_MB64B_H (7U)

#define	CAN_WORD_COUNT_MB64B_H (7U)

#define	CAN_WORD_COUNT_MB64B_H2 (16U)

#define	CAN_CS_COUNT (64U)

#define	CAN_ID_COUNT (64U)

#define	CAN_WORD0_COUNT (64U)

#define	CAN_WORD1_COUNT (64U)

#define	CAN_RXIMR_COUNT (64U)

MCR - Module Configuration Register
#define	CAN_MCR_MAXMB_MASK (0x7FU)

#define	CAN_MCR_MAXMB_SHIFT (0U)

#define	CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)

#define	CAN_MCR_IDAM_MASK (0x300U)

#define	CAN_MCR_IDAM_SHIFT (8U)

#define	CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

#define	CAN_MCR_AEN_MASK (0x1000U)

#define	CAN_MCR_AEN_SHIFT (12U)

#define	CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

#define	CAN_MCR_LPRIOEN_MASK (0x2000U)

#define	CAN_MCR_LPRIOEN_SHIFT (13U)

#define	CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

#define	CAN_MCR_IRMQ_MASK (0x10000U)

#define	CAN_MCR_IRMQ_SHIFT (16U)

#define	CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

#define	CAN_MCR_SRXDIS_MASK (0x20000U)

#define	CAN_MCR_SRXDIS_SHIFT (17U)

#define	CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

#define	CAN_MCR_WAKSRC_MASK (0x80000U)

#define	CAN_MCR_WAKSRC_SHIFT (19U)

#define	CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

#define	CAN_MCR_LPMACK_MASK (0x100000U)

#define	CAN_MCR_LPMACK_SHIFT (20U)

#define	CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

#define	CAN_MCR_WRNEN_MASK (0x200000U)

#define	CAN_MCR_WRNEN_SHIFT (21U)

#define	CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

#define	CAN_MCR_SLFWAK_MASK (0x400000U)

#define	CAN_MCR_SLFWAK_SHIFT (22U)

#define	CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

#define	CAN_MCR_SUPV_MASK (0x800000U)

#define	CAN_MCR_SUPV_SHIFT (23U)

#define	CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

#define	CAN_MCR_FRZACK_MASK (0x1000000U)

#define	CAN_MCR_FRZACK_SHIFT (24U)

#define	CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

#define	CAN_MCR_SOFTRST_MASK (0x2000000U)

#define	CAN_MCR_SOFTRST_SHIFT (25U)

#define	CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

#define	CAN_MCR_WAKMSK_MASK (0x4000000U)

#define	CAN_MCR_WAKMSK_SHIFT (26U)

#define	CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

#define	CAN_MCR_NOTRDY_MASK (0x8000000U)

#define	CAN_MCR_NOTRDY_SHIFT (27U)

#define	CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

#define	CAN_MCR_HALT_MASK (0x10000000U)

#define	CAN_MCR_HALT_SHIFT (28U)

#define	CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

#define	CAN_MCR_RFEN_MASK (0x20000000U)

#define	CAN_MCR_RFEN_SHIFT (29U)

#define	CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

#define	CAN_MCR_FRZ_MASK (0x40000000U)

#define	CAN_MCR_FRZ_SHIFT (30U)

#define	CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

#define	CAN_MCR_MDIS_MASK (0x80000000U)

#define	CAN_MCR_MDIS_SHIFT (31U)

#define	CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

CTRL1 - Control 1 Register
#define	CAN_CTRL1_PROPSEG_MASK (0x7U)

#define	CAN_CTRL1_PROPSEG_SHIFT (0U)

#define	CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)

#define	CAN_CTRL1_LOM_MASK (0x8U)

#define	CAN_CTRL1_LOM_SHIFT (3U)

#define	CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

#define	CAN_CTRL1_LBUF_MASK (0x10U)

#define	CAN_CTRL1_LBUF_SHIFT (4U)

#define	CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

#define	CAN_CTRL1_TSYN_MASK (0x20U)

#define	CAN_CTRL1_TSYN_SHIFT (5U)

#define	CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

#define	CAN_CTRL1_BOFFREC_MASK (0x40U)

#define	CAN_CTRL1_BOFFREC_SHIFT (6U)

#define	CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

#define	CAN_CTRL1_SMP_MASK (0x80U)

#define	CAN_CTRL1_SMP_SHIFT (7U)

#define	CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

#define	CAN_CTRL1_RWRNMSK_MASK (0x400U)

#define	CAN_CTRL1_RWRNMSK_SHIFT (10U)

#define	CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

#define	CAN_CTRL1_TWRNMSK_MASK (0x800U)

#define	CAN_CTRL1_TWRNMSK_SHIFT (11U)

#define	CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

#define	CAN_CTRL1_LPB_MASK (0x1000U)

#define	CAN_CTRL1_LPB_SHIFT (12U)

#define	CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

#define	CAN_CTRL1_ERRMSK_MASK (0x4000U)

#define	CAN_CTRL1_ERRMSK_SHIFT (14U)

#define	CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

#define	CAN_CTRL1_BOFFMSK_MASK (0x8000U)

#define	CAN_CTRL1_BOFFMSK_SHIFT (15U)

#define	CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

#define	CAN_CTRL1_PSEG2_MASK (0x70000U)

#define	CAN_CTRL1_PSEG2_SHIFT (16U)

#define	CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)

#define	CAN_CTRL1_PSEG1_MASK (0x380000U)

#define	CAN_CTRL1_PSEG1_SHIFT (19U)

#define	CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)

#define	CAN_CTRL1_RJW_MASK (0xC00000U)

#define	CAN_CTRL1_RJW_SHIFT (22U)

#define	CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)

#define	CAN_CTRL1_PRESDIV_MASK (0xFF000000U)

#define	CAN_CTRL1_PRESDIV_SHIFT (24U)

#define	CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)

TIMER - Free Running Timer Register
#define	CAN_TIMER_TIMER_MASK (0xFFFFU)

#define	CAN_TIMER_TIMER_SHIFT (0U)

#define	CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)

RXMGMASK - Rx Mailboxes Global Mask Register
#define	CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)

#define	CAN_RXMGMASK_MG_SHIFT (0U)

#define	CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

RX14MASK - Rx Buffer 14 Mask Register
#define	CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)

#define	CAN_RX14MASK_RX14M_SHIFT (0U)

#define	CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX15MASK - Rx Buffer 15 Mask Register
#define	CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)

#define	CAN_RX15MASK_RX15M_SHIFT (0U)

#define	CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

ECR - Error Counter Register
#define	CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)

#define	CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)

#define	CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)

#define	CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)

#define	CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)

#define	CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)

ESR1 - Error and Status 1 Register
#define	CAN_ESR1_WAKINT_MASK (0x1U)

#define	CAN_ESR1_WAKINT_SHIFT (0U)

#define	CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

#define	CAN_ESR1_ERRINT_MASK (0x2U)

#define	CAN_ESR1_ERRINT_SHIFT (1U)

#define	CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

#define	CAN_ESR1_BOFFINT_MASK (0x4U)

#define	CAN_ESR1_BOFFINT_SHIFT (2U)

#define	CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

#define	CAN_ESR1_RX_MASK (0x8U)

#define	CAN_ESR1_RX_SHIFT (3U)

#define	CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

#define	CAN_ESR1_FLTCONF_MASK (0x30U)

#define	CAN_ESR1_FLTCONF_SHIFT (4U)

#define	CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

#define	CAN_ESR1_TX_MASK (0x40U)

#define	CAN_ESR1_TX_SHIFT (6U)

#define	CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

#define	CAN_ESR1_IDLE_MASK (0x80U)

#define	CAN_ESR1_IDLE_SHIFT (7U)

#define	CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

#define	CAN_ESR1_RXWRN_MASK (0x100U)

#define	CAN_ESR1_RXWRN_SHIFT (8U)

#define	CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

#define	CAN_ESR1_TXWRN_MASK (0x200U)

#define	CAN_ESR1_TXWRN_SHIFT (9U)

#define	CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

#define	CAN_ESR1_STFERR_MASK (0x400U)

#define	CAN_ESR1_STFERR_SHIFT (10U)

#define	CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

#define	CAN_ESR1_FRMERR_MASK (0x800U)

#define	CAN_ESR1_FRMERR_SHIFT (11U)

#define	CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

#define	CAN_ESR1_CRCERR_MASK (0x1000U)

#define	CAN_ESR1_CRCERR_SHIFT (12U)

#define	CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

#define	CAN_ESR1_ACKERR_MASK (0x2000U)

#define	CAN_ESR1_ACKERR_SHIFT (13U)

#define	CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

#define	CAN_ESR1_BIT0ERR_MASK (0x4000U)

#define	CAN_ESR1_BIT0ERR_SHIFT (14U)

#define	CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

#define	CAN_ESR1_BIT1ERR_MASK (0x8000U)

#define	CAN_ESR1_BIT1ERR_SHIFT (15U)

#define	CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

#define	CAN_ESR1_RWRNINT_MASK (0x10000U)

#define	CAN_ESR1_RWRNINT_SHIFT (16U)

#define	CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

#define	CAN_ESR1_TWRNINT_MASK (0x20000U)

#define	CAN_ESR1_TWRNINT_SHIFT (17U)

#define	CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

#define	CAN_ESR1_SYNCH_MASK (0x40000U)

#define	CAN_ESR1_SYNCH_SHIFT (18U)

#define	CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

IMASK2 - Interrupt Masks 2 Register
#define	CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)

#define	CAN_IMASK2_BUFHM_SHIFT (0U)

#define	CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)

IMASK1 - Interrupt Masks 1 Register
#define	CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)

#define	CAN_IMASK1_BUFLM_SHIFT (0U)

#define	CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)

IFLAG2 - Interrupt Flags 2 Register
#define	CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)

#define	CAN_IFLAG2_BUFHI_SHIFT (0U)

#define	CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)

IFLAG1 - Interrupt Flags 1 Register
#define	CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)

#define	CAN_IFLAG1_BUF4TO0I_SHIFT (0U)

#define	CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)

#define	CAN_IFLAG1_BUF5I_MASK (0x20U)

#define	CAN_IFLAG1_BUF5I_SHIFT (5U)

#define	CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

#define	CAN_IFLAG1_BUF6I_MASK (0x40U)

#define	CAN_IFLAG1_BUF6I_SHIFT (6U)

#define	CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

#define	CAN_IFLAG1_BUF7I_MASK (0x80U)

#define	CAN_IFLAG1_BUF7I_SHIFT (7U)

#define	CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

#define	CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)

#define	CAN_IFLAG1_BUF31TO8I_SHIFT (8U)

#define	CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

CTRL2 - Control 2 Register
#define	CAN_CTRL2_EACEN_MASK (0x10000U)

#define	CAN_CTRL2_EACEN_SHIFT (16U)

#define	CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

#define	CAN_CTRL2_RRS_MASK (0x20000U)

#define	CAN_CTRL2_RRS_SHIFT (17U)

#define	CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

#define	CAN_CTRL2_MRP_MASK (0x40000U)

#define	CAN_CTRL2_MRP_SHIFT (18U)

#define	CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

#define	CAN_CTRL2_TASD_MASK (0xF80000U)

#define	CAN_CTRL2_TASD_SHIFT (19U)

#define	CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)

#define	CAN_CTRL2_RFFN_MASK (0xF000000U)

#define	CAN_CTRL2_RFFN_SHIFT (24U)

#define	CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)

#define	CAN_CTRL2_WRMFRZ_MASK (0x10000000U)

#define	CAN_CTRL2_WRMFRZ_SHIFT (28U)

#define	CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)

#define	ENC_CTRL2_UPDHLD_MASK (0x1U)

#define	ENC_CTRL2_UPDHLD_SHIFT (0U)

#define	ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

#define	ENC_CTRL2_UPDPOS_MASK (0x2U)

#define	ENC_CTRL2_UPDPOS_SHIFT (1U)

#define	ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

#define	ENC_CTRL2_MOD_MASK (0x4U)

#define	ENC_CTRL2_MOD_SHIFT (2U)

#define	ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

#define	ENC_CTRL2_DIR_MASK (0x8U)

#define	ENC_CTRL2_DIR_SHIFT (3U)

#define	ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

#define	ENC_CTRL2_RUIE_MASK (0x10U)

#define	ENC_CTRL2_RUIE_SHIFT (4U)

#define	ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

#define	ENC_CTRL2_RUIRQ_MASK (0x20U)

#define	ENC_CTRL2_RUIRQ_SHIFT (5U)

#define	ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

#define	ENC_CTRL2_ROIE_MASK (0x40U)

#define	ENC_CTRL2_ROIE_SHIFT (6U)

#define	ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

#define	ENC_CTRL2_ROIRQ_MASK (0x80U)

#define	ENC_CTRL2_ROIRQ_SHIFT (7U)

#define	ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

#define	ENC_CTRL2_REVMOD_MASK (0x100U)

#define	ENC_CTRL2_REVMOD_SHIFT (8U)

#define	ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

#define	ENC_CTRL2_OUTCTL_MASK (0x200U)

#define	ENC_CTRL2_OUTCTL_SHIFT (9U)

#define	ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

#define	PWM_CTRL2_CLK_SEL_MASK (0x3U)

#define	PWM_CTRL2_CLK_SEL_SHIFT (0U)

#define	PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)

#define	PWM_CTRL2_RELOAD_SEL_MASK (0x4U)

#define	PWM_CTRL2_RELOAD_SEL_SHIFT (2U)

#define	PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)

#define	PWM_CTRL2_FORCE_SEL_MASK (0x38U)

#define	PWM_CTRL2_FORCE_SEL_SHIFT (3U)

#define	PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)

#define	PWM_CTRL2_FORCE_MASK (0x40U)

#define	PWM_CTRL2_FORCE_SHIFT (6U)

#define	PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)

#define	PWM_CTRL2_FRCEN_MASK (0x80U)

#define	PWM_CTRL2_FRCEN_SHIFT (7U)

#define	PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)

#define	PWM_CTRL2_INIT_SEL_MASK (0x300U)

#define	PWM_CTRL2_INIT_SEL_SHIFT (8U)

#define	PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)

#define	PWM_CTRL2_PWMX_INIT_MASK (0x400U)

#define	PWM_CTRL2_PWMX_INIT_SHIFT (10U)

#define	PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)

#define	PWM_CTRL2_PWM45_INIT_MASK (0x800U)

#define	PWM_CTRL2_PWM45_INIT_SHIFT (11U)

#define	PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)

#define	PWM_CTRL2_PWM23_INIT_MASK (0x1000U)

#define	PWM_CTRL2_PWM23_INIT_SHIFT (12U)

#define	PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)

#define	PWM_CTRL2_INDEP_MASK (0x2000U)

#define	PWM_CTRL2_INDEP_SHIFT (13U)

#define	PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)

#define	PWM_CTRL2_WAITEN_MASK (0x4000U)

#define	PWM_CTRL2_WAITEN_SHIFT (14U)

#define	PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)

#define	PWM_CTRL2_DBGEN_MASK (0x8000U)

#define	PWM_CTRL2_DBGEN_SHIFT (15U)

#define	PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)

ESR2 - Error and Status 2 Register
#define	CAN_ESR2_IMB_MASK (0x2000U)

#define	CAN_ESR2_IMB_SHIFT (13U)

#define	CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

#define	CAN_ESR2_VPS_MASK (0x4000U)

#define	CAN_ESR2_VPS_SHIFT (14U)

#define	CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

#define	CAN_ESR2_LPTM_MASK (0x7F0000U)

#define	CAN_ESR2_LPTM_SHIFT (16U)

#define	CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)

CRCR - CRC Register
#define	CAN_CRCR_TXCRC_MASK (0x7FFFU)

#define	CAN_CRCR_TXCRC_SHIFT (0U)

#define	CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)

#define	CAN_CRCR_MBCRC_MASK (0x7F0000U)

#define	CAN_CRCR_MBCRC_SHIFT (16U)

#define	CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)

RXFGMASK - Rx FIFO Global Mask Register
#define	CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)

#define	CAN_RXFGMASK_FGM_SHIFT (0U)

#define	CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

RXFIR - Rx FIFO Information Register
#define	CAN_RXFIR_IDHIT_MASK (0x1FFU)

#define	CAN_RXFIR_IDHIT_SHIFT (0U)

#define	CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)

DBG1 - Debug 1 register
#define	CAN_DBG1_CFSM_MASK (0x3FU)

#define	CAN_DBG1_CFSM_SHIFT (0U)

#define	CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)

#define	CAN_DBG1_CBN_MASK (0x1F000000U)

#define	CAN_DBG1_CBN_SHIFT (24U)

#define	CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)

DBG2 - Debug 2 register
#define	CAN_DBG2_RMP_MASK (0x7FU)

#define	CAN_DBG2_RMP_SHIFT (0U)

#define	CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)

#define	CAN_DBG2_MPP_MASK (0x80U)

#define	CAN_DBG2_MPP_SHIFT (7U)

#define	CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)

#define	CAN_DBG2_TAP_MASK (0x7F00U)

#define	CAN_DBG2_TAP_SHIFT (8U)

#define	CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)

#define	CAN_DBG2_APP_MASK (0x8000U)

#define	CAN_DBG2_APP_SHIFT (15U)

#define	CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)

CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register
#define	CAN_CS_TIME_STAMP_MASK (0xFFFFU)

#define	CAN_CS_TIME_STAMP_SHIFT (0U)

#define	CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

#define	CAN_CS_DLC_MASK (0xF0000U)

#define	CAN_CS_DLC_SHIFT (16U)

#define	CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

#define	CAN_CS_RTR_MASK (0x100000U)

#define	CAN_CS_RTR_SHIFT (20U)

#define	CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

#define	CAN_CS_IDE_MASK (0x200000U)

#define	CAN_CS_IDE_SHIFT (21U)

#define	CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

#define	CAN_CS_SRR_MASK (0x400000U)

#define	CAN_CS_SRR_SHIFT (22U)

#define	CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

#define	CAN_CS_CODE_MASK (0xF000000U)

#define	CAN_CS_CODE_SHIFT (24U)

#define	CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register
#define	CAN_ID_EXT_MASK (0x3FFFFU)

#define	CAN_ID_EXT_SHIFT (0U)

#define	CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

#define	CAN_ID_STD_MASK (0x1FFC0000U)

#define	CAN_ID_STD_SHIFT (18U)

#define	CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

#define	CAN_ID_PRIO_MASK (0xE0000000U)

#define	CAN_ID_PRIO_SHIFT (29U)

#define	CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)

WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register
#define	CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)

#define	CAN_WORD0_DATA_BYTE_3_SHIFT (0U)

#define	CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)

#define	CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)

#define	CAN_WORD0_DATA_BYTE_2_SHIFT (8U)

#define	CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)

#define	CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)

#define	CAN_WORD0_DATA_BYTE_1_SHIFT (16U)

#define	CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)

#define	CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)

#define	CAN_WORD0_DATA_BYTE_0_SHIFT (24U)

#define	CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)

WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register
#define	CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)

#define	CAN_WORD1_DATA_BYTE_7_SHIFT (0U)

#define	CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)

#define	CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)

#define	CAN_WORD1_DATA_BYTE_6_SHIFT (8U)

#define	CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)

#define	CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)

#define	CAN_WORD1_DATA_BYTE_5_SHIFT (16U)

#define	CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)

#define	CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)

#define	CAN_WORD1_DATA_BYTE_4_SHIFT (24U)

#define	CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)

RXIMR - Rx Individual Mask Registers
#define	CAN_RXIMR_MI_MASK (0xFFFFFFFFU)

#define	CAN_RXIMR_MI_SHIFT (0U)

#define	CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

GFWR - Glitch Filter Width Registers
#define	CAN_GFWR_GFWR_MASK (0xFFU)

#define	CAN_GFWR_GFWR_SHIFT (0U)

#define	CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)

MCR - Module Configuration register
#define	CAN_MCR_MAXMB_MASK (0x7FU)

#define	CAN_MCR_MAXMB_SHIFT (0U)

#define	CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)

#define	CAN_MCR_IDAM_MASK (0x300U)

#define	CAN_MCR_IDAM_SHIFT (8U)

#define	CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

#define	CAN_MCR_FDEN_MASK (0x800U)

#define	CAN_MCR_FDEN_SHIFT (11U)

#define	CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)

#define	CAN_MCR_AEN_MASK (0x1000U)

#define	CAN_MCR_AEN_SHIFT (12U)

#define	CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

#define	CAN_MCR_LPRIOEN_MASK (0x2000U)

#define	CAN_MCR_LPRIOEN_SHIFT (13U)

#define	CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

#define	CAN_MCR_DMA_MASK (0x8000U)

#define	CAN_MCR_DMA_SHIFT (15U)

#define	CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)

#define	CAN_MCR_IRMQ_MASK (0x10000U)

#define	CAN_MCR_IRMQ_SHIFT (16U)

#define	CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

#define	CAN_MCR_SRXDIS_MASK (0x20000U)

#define	CAN_MCR_SRXDIS_SHIFT (17U)

#define	CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

#define	CAN_MCR_DOZE_MASK (0x40000U)

#define	CAN_MCR_DOZE_SHIFT (18U)

#define	CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)

#define	CAN_MCR_WAKSRC_MASK (0x80000U)

#define	CAN_MCR_WAKSRC_SHIFT (19U)

#define	CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

#define	CAN_MCR_LPMACK_MASK (0x100000U)

#define	CAN_MCR_LPMACK_SHIFT (20U)

#define	CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

#define	CAN_MCR_WRNEN_MASK (0x200000U)

#define	CAN_MCR_WRNEN_SHIFT (21U)

#define	CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

#define	CAN_MCR_SLFWAK_MASK (0x400000U)

#define	CAN_MCR_SLFWAK_SHIFT (22U)

#define	CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

#define	CAN_MCR_SUPV_MASK (0x800000U)

#define	CAN_MCR_SUPV_SHIFT (23U)

#define	CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

#define	CAN_MCR_FRZACK_MASK (0x1000000U)

#define	CAN_MCR_FRZACK_SHIFT (24U)

#define	CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

#define	CAN_MCR_SOFTRST_MASK (0x2000000U)

#define	CAN_MCR_SOFTRST_SHIFT (25U)

#define	CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

#define	CAN_MCR_WAKMSK_MASK (0x4000000U)

#define	CAN_MCR_WAKMSK_SHIFT (26U)

#define	CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

#define	CAN_MCR_NOTRDY_MASK (0x8000000U)

#define	CAN_MCR_NOTRDY_SHIFT (27U)

#define	CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

#define	CAN_MCR_HALT_MASK (0x10000000U)

#define	CAN_MCR_HALT_SHIFT (28U)

#define	CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

#define	CAN_MCR_RFEN_MASK (0x20000000U)

#define	CAN_MCR_RFEN_SHIFT (29U)

#define	CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

#define	CAN_MCR_FRZ_MASK (0x40000000U)

#define	CAN_MCR_FRZ_SHIFT (30U)

#define	CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

#define	CAN_MCR_MDIS_MASK (0x80000000U)

#define	CAN_MCR_MDIS_SHIFT (31U)

#define	CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

CTRL1 - Control 1 register
#define	CAN_CTRL1_PROPSEG_MASK (0x7U)

#define	CAN_CTRL1_PROPSEG_SHIFT (0U)

#define	CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)

#define	CAN_CTRL1_LOM_MASK (0x8U)

#define	CAN_CTRL1_LOM_SHIFT (3U)

#define	CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

#define	CAN_CTRL1_LBUF_MASK (0x10U)

#define	CAN_CTRL1_LBUF_SHIFT (4U)

#define	CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

#define	CAN_CTRL1_TSYN_MASK (0x20U)

#define	CAN_CTRL1_TSYN_SHIFT (5U)

#define	CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

#define	CAN_CTRL1_BOFFREC_MASK (0x40U)

#define	CAN_CTRL1_BOFFREC_SHIFT (6U)

#define	CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

#define	CAN_CTRL1_SMP_MASK (0x80U)

#define	CAN_CTRL1_SMP_SHIFT (7U)

#define	CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

#define	CAN_CTRL1_RWRNMSK_MASK (0x400U)

#define	CAN_CTRL1_RWRNMSK_SHIFT (10U)

#define	CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

#define	CAN_CTRL1_TWRNMSK_MASK (0x800U)

#define	CAN_CTRL1_TWRNMSK_SHIFT (11U)

#define	CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

#define	CAN_CTRL1_LPB_MASK (0x1000U)

#define	CAN_CTRL1_LPB_SHIFT (12U)

#define	CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

#define	CAN_CTRL1_CLKSRC_MASK (0x2000U)

#define	CAN_CTRL1_CLKSRC_SHIFT (13U)

#define	CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)

#define	CAN_CTRL1_ERRMSK_MASK (0x4000U)

#define	CAN_CTRL1_ERRMSK_SHIFT (14U)

#define	CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

#define	CAN_CTRL1_BOFFMSK_MASK (0x8000U)

#define	CAN_CTRL1_BOFFMSK_SHIFT (15U)

#define	CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

#define	CAN_CTRL1_PSEG2_MASK (0x70000U)

#define	CAN_CTRL1_PSEG2_SHIFT (16U)

#define	CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)

#define	CAN_CTRL1_PSEG1_MASK (0x380000U)

#define	CAN_CTRL1_PSEG1_SHIFT (19U)

#define	CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)

#define	CAN_CTRL1_RJW_MASK (0xC00000U)

#define	CAN_CTRL1_RJW_SHIFT (22U)

#define	CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)

#define	CAN_CTRL1_PRESDIV_MASK (0xFF000000U)

#define	CAN_CTRL1_PRESDIV_SHIFT (24U)

#define	CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)

TIMER - Free Running Timer
#define	CAN_TIMER_TIMER_MASK (0xFFFFU)

#define	CAN_TIMER_TIMER_SHIFT (0U)

#define	CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)

RXMGMASK - Rx Mailboxes Global Mask register
#define	CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)

#define	CAN_RXMGMASK_MG_SHIFT (0U)

#define	CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

RX14MASK - Rx 14 Mask register
#define	CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)

#define	CAN_RX14MASK_RX14M_SHIFT (0U)

#define	CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX15MASK - Rx 15 Mask register
#define	CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)

#define	CAN_RX15MASK_RX15M_SHIFT (0U)

#define	CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

ECR - Error Counter
#define	CAN_ECR_TXERRCNT_MASK (0xFFU)

#define	CAN_ECR_TXERRCNT_SHIFT (0U)

#define	CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)

#define	CAN_ECR_RXERRCNT_MASK (0xFF00U)

#define	CAN_ECR_RXERRCNT_SHIFT (8U)

#define	CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)

#define	CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)

#define	CAN_ECR_TXERRCNT_FAST_SHIFT (16U)

#define	CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)

#define	CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)

#define	CAN_ECR_RXERRCNT_FAST_SHIFT (24U)

#define	CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)

ESR1 - Error and Status 1 register
#define	CAN_ESR1_WAKINT_MASK (0x1U)

#define	CAN_ESR1_WAKINT_SHIFT (0U)

#define	CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

#define	CAN_ESR1_ERRINT_MASK (0x2U)

#define	CAN_ESR1_ERRINT_SHIFT (1U)

#define	CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

#define	CAN_ESR1_BOFFINT_MASK (0x4U)

#define	CAN_ESR1_BOFFINT_SHIFT (2U)

#define	CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

#define	CAN_ESR1_RX_MASK (0x8U)

#define	CAN_ESR1_RX_SHIFT (3U)

#define	CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

#define	CAN_ESR1_FLTCONF_MASK (0x30U)

#define	CAN_ESR1_FLTCONF_SHIFT (4U)

#define	CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

#define	CAN_ESR1_TX_MASK (0x40U)

#define	CAN_ESR1_TX_SHIFT (6U)

#define	CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

#define	CAN_ESR1_IDLE_MASK (0x80U)

#define	CAN_ESR1_IDLE_SHIFT (7U)

#define	CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

#define	CAN_ESR1_RXWRN_MASK (0x100U)

#define	CAN_ESR1_RXWRN_SHIFT (8U)

#define	CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

#define	CAN_ESR1_TXWRN_MASK (0x200U)

#define	CAN_ESR1_TXWRN_SHIFT (9U)

#define	CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

#define	CAN_ESR1_STFERR_MASK (0x400U)

#define	CAN_ESR1_STFERR_SHIFT (10U)

#define	CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

#define	CAN_ESR1_FRMERR_MASK (0x800U)

#define	CAN_ESR1_FRMERR_SHIFT (11U)

#define	CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

#define	CAN_ESR1_CRCERR_MASK (0x1000U)

#define	CAN_ESR1_CRCERR_SHIFT (12U)

#define	CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

#define	CAN_ESR1_ACKERR_MASK (0x2000U)

#define	CAN_ESR1_ACKERR_SHIFT (13U)

#define	CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

#define	CAN_ESR1_BIT0ERR_MASK (0x4000U)

#define	CAN_ESR1_BIT0ERR_SHIFT (14U)

#define	CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

#define	CAN_ESR1_BIT1ERR_MASK (0x8000U)

#define	CAN_ESR1_BIT1ERR_SHIFT (15U)

#define	CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

#define	CAN_ESR1_RWRNINT_MASK (0x10000U)

#define	CAN_ESR1_RWRNINT_SHIFT (16U)

#define	CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

#define	CAN_ESR1_TWRNINT_MASK (0x20000U)

#define	CAN_ESR1_TWRNINT_SHIFT (17U)

#define	CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

#define	CAN_ESR1_SYNCH_MASK (0x40000U)

#define	CAN_ESR1_SYNCH_SHIFT (18U)

#define	CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

#define	CAN_ESR1_BOFFDONEINT_MASK (0x80000U)

#define	CAN_ESR1_BOFFDONEINT_SHIFT (19U)

#define	CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)

#define	CAN_ESR1_ERRINT_FAST_MASK (0x100000U)

#define	CAN_ESR1_ERRINT_FAST_SHIFT (20U)

#define	CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)

#define	CAN_ESR1_ERROVR_MASK (0x200000U)

#define	CAN_ESR1_ERROVR_SHIFT (21U)

#define	CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)

#define	CAN_ESR1_STFERR_FAST_MASK (0x4000000U)

#define	CAN_ESR1_STFERR_FAST_SHIFT (26U)

#define	CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)

#define	CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)

#define	CAN_ESR1_FRMERR_FAST_SHIFT (27U)

#define	CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)

#define	CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)

#define	CAN_ESR1_CRCERR_FAST_SHIFT (28U)

#define	CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)

#define	CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)

#define	CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)

#define	CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)

#define	CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)

#define	CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)

#define	CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)

IMASK2 - Interrupt Masks 2 register
#define	CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)

#define	CAN_IMASK2_BUF63TO32M_SHIFT (0U)

#define	CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)

IMASK1 - Interrupt Masks 1 register
#define	CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)

#define	CAN_IMASK1_BUF31TO0M_SHIFT (0U)

#define	CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)

IFLAG2 - Interrupt Flags 2 register
#define	CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)

#define	CAN_IFLAG2_BUF63TO32I_SHIFT (0U)

#define	CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)

IFLAG1 - Interrupt Flags 1 register
#define	CAN_IFLAG1_BUF0I_MASK (0x1U)

#define	CAN_IFLAG1_BUF0I_SHIFT (0U)

#define	CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)

#define	CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)

#define	CAN_IFLAG1_BUF4TO1I_SHIFT (1U)

#define	CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)

#define	CAN_IFLAG1_BUF5I_MASK (0x20U)

#define	CAN_IFLAG1_BUF5I_SHIFT (5U)

#define	CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

#define	CAN_IFLAG1_BUF6I_MASK (0x40U)

#define	CAN_IFLAG1_BUF6I_SHIFT (6U)

#define	CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

#define	CAN_IFLAG1_BUF7I_MASK (0x80U)

#define	CAN_IFLAG1_BUF7I_SHIFT (7U)

#define	CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

#define	CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)

#define	CAN_IFLAG1_BUF31TO8I_SHIFT (8U)

#define	CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

CTRL2 - Control 2 register
#define	CAN_CTRL2_EDFLTDIS_MASK (0x800U)

#define	CAN_CTRL2_EDFLTDIS_SHIFT (11U)

#define	CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)

#define	CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)

#define	CAN_CTRL2_ISOCANFDEN_SHIFT (12U)

#define	CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)

#define	CAN_CTRL2_PREXCEN_MASK (0x4000U)

#define	CAN_CTRL2_PREXCEN_SHIFT (14U)

#define	CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)

#define	CAN_CTRL2_TIMER_SRC_MASK (0x8000U)

#define	CAN_CTRL2_TIMER_SRC_SHIFT (15U)

#define	CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)

#define	CAN_CTRL2_EACEN_MASK (0x10000U)

#define	CAN_CTRL2_EACEN_SHIFT (16U)

#define	CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

#define	CAN_CTRL2_RRS_MASK (0x20000U)

#define	CAN_CTRL2_RRS_SHIFT (17U)

#define	CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

#define	CAN_CTRL2_MRP_MASK (0x40000U)

#define	CAN_CTRL2_MRP_SHIFT (18U)

#define	CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

#define	CAN_CTRL2_TASD_MASK (0xF80000U)

#define	CAN_CTRL2_TASD_SHIFT (19U)

#define	CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)

#define	CAN_CTRL2_RFFN_MASK (0xF000000U)

#define	CAN_CTRL2_RFFN_SHIFT (24U)

#define	CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)

#define	CAN_CTRL2_WRMFRZ_MASK (0x10000000U)

#define	CAN_CTRL2_WRMFRZ_SHIFT (28U)

#define	CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)

#define	CAN_CTRL2_ECRWRE_MASK (0x20000000U)

#define	CAN_CTRL2_ECRWRE_SHIFT (29U)

#define	CAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)

#define	CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)

#define	CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)

#define	CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)

#define	CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)

#define	CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)

#define	CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)

#define	ENC_CTRL2_UPDHLD_MASK (0x1U)

#define	ENC_CTRL2_UPDHLD_SHIFT (0U)

#define	ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

#define	ENC_CTRL2_UPDPOS_MASK (0x2U)

#define	ENC_CTRL2_UPDPOS_SHIFT (1U)

#define	ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

#define	ENC_CTRL2_MOD_MASK (0x4U)

#define	ENC_CTRL2_MOD_SHIFT (2U)

#define	ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

#define	ENC_CTRL2_DIR_MASK (0x8U)

#define	ENC_CTRL2_DIR_SHIFT (3U)

#define	ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

#define	ENC_CTRL2_RUIE_MASK (0x10U)

#define	ENC_CTRL2_RUIE_SHIFT (4U)

#define	ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

#define	ENC_CTRL2_RUIRQ_MASK (0x20U)

#define	ENC_CTRL2_RUIRQ_SHIFT (5U)

#define	ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

#define	ENC_CTRL2_ROIE_MASK (0x40U)

#define	ENC_CTRL2_ROIE_SHIFT (6U)

#define	ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

#define	ENC_CTRL2_ROIRQ_MASK (0x80U)

#define	ENC_CTRL2_ROIRQ_SHIFT (7U)

#define	ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

#define	ENC_CTRL2_REVMOD_MASK (0x100U)

#define	ENC_CTRL2_REVMOD_SHIFT (8U)

#define	ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

#define	ENC_CTRL2_OUTCTL_MASK (0x200U)

#define	ENC_CTRL2_OUTCTL_SHIFT (9U)

#define	ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

#define	ENC_CTRL2_SABIE_MASK (0x400U)

#define	ENC_CTRL2_SABIE_SHIFT (10U)

#define	ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)

#define	ENC_CTRL2_SABIRQ_MASK (0x800U)

#define	ENC_CTRL2_SABIRQ_SHIFT (11U)

#define	ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)

#define	PWM_CTRL2_CLK_SEL_MASK (0x3U)

#define	PWM_CTRL2_CLK_SEL_SHIFT (0U)

#define	PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)

#define	PWM_CTRL2_RELOAD_SEL_MASK (0x4U)

#define	PWM_CTRL2_RELOAD_SEL_SHIFT (2U)

#define	PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)

#define	PWM_CTRL2_FORCE_SEL_MASK (0x38U)

#define	PWM_CTRL2_FORCE_SEL_SHIFT (3U)

#define	PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)

#define	PWM_CTRL2_FORCE_MASK (0x40U)

#define	PWM_CTRL2_FORCE_SHIFT (6U)

#define	PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)

#define	PWM_CTRL2_FRCEN_MASK (0x80U)

#define	PWM_CTRL2_FRCEN_SHIFT (7U)

#define	PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)

#define	PWM_CTRL2_INIT_SEL_MASK (0x300U)

#define	PWM_CTRL2_INIT_SEL_SHIFT (8U)

#define	PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)

#define	PWM_CTRL2_PWMX_INIT_MASK (0x400U)

#define	PWM_CTRL2_PWMX_INIT_SHIFT (10U)

#define	PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)

#define	PWM_CTRL2_PWM45_INIT_MASK (0x800U)

#define	PWM_CTRL2_PWM45_INIT_SHIFT (11U)

#define	PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)

#define	PWM_CTRL2_PWM23_INIT_MASK (0x1000U)

#define	PWM_CTRL2_PWM23_INIT_SHIFT (12U)

#define	PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)

#define	PWM_CTRL2_INDEP_MASK (0x2000U)

#define	PWM_CTRL2_INDEP_SHIFT (13U)

#define	PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)

#define	PWM_CTRL2_WAITEN_MASK (0x4000U)

#define	PWM_CTRL2_WAITEN_SHIFT (14U)

#define	PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)

#define	PWM_CTRL2_DBGEN_MASK (0x8000U)

#define	PWM_CTRL2_DBGEN_SHIFT (15U)

#define	PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)

ESR2 - Error and Status 2 register
#define	CAN_ESR2_IMB_MASK (0x2000U)

#define	CAN_ESR2_IMB_SHIFT (13U)

#define	CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

#define	CAN_ESR2_VPS_MASK (0x4000U)

#define	CAN_ESR2_VPS_SHIFT (14U)

#define	CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

#define	CAN_ESR2_LPTM_MASK (0x7F0000U)

#define	CAN_ESR2_LPTM_SHIFT (16U)

#define	CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)

CRCR - CRC register
#define	CAN_CRCR_TXCRC_MASK (0x7FFFU)

#define	CAN_CRCR_TXCRC_SHIFT (0U)

#define	CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)

#define	CAN_CRCR_MBCRC_MASK (0x7F0000U)

#define	CAN_CRCR_MBCRC_SHIFT (16U)

#define	CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)

RXFGMASK - Rx FIFO Global Mask register
#define	CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)

#define	CAN_RXFGMASK_FGM_SHIFT (0U)

#define	CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

RXFIR - Rx FIFO Information register
#define	CAN_RXFIR_IDHIT_MASK (0x1FFU)

#define	CAN_RXFIR_IDHIT_SHIFT (0U)

#define	CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)

CBT - CAN Bit Timing register
#define	CAN_CBT_EPSEG2_MASK (0x1FU)

#define	CAN_CBT_EPSEG2_SHIFT (0U)

#define	CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)

#define	CAN_CBT_EPSEG1_MASK (0x3E0U)

#define	CAN_CBT_EPSEG1_SHIFT (5U)

#define	CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)

#define	CAN_CBT_EPROPSEG_MASK (0xFC00U)

#define	CAN_CBT_EPROPSEG_SHIFT (10U)

#define	CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)

#define	CAN_CBT_ERJW_MASK (0x1F0000U)

#define	CAN_CBT_ERJW_SHIFT (16U)

#define	CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)

#define	CAN_CBT_EPRESDIV_MASK (0x7FE00000U)

#define	CAN_CBT_EPRESDIV_SHIFT (21U)

#define	CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)

#define	CAN_CBT_BTF_MASK (0x80000000U)

#define	CAN_CBT_BTF_SHIFT (31U)

#define	CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)

CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register
#define	CAN_CS_TIME_STAMP_MASK (0xFFFFU)

#define	CAN_CS_TIME_STAMP_MASK (0xFFFFU)

#define	CAN_CS_TIME_STAMP_SHIFT (0U)

#define	CAN_CS_TIME_STAMP_SHIFT (0U)

#define	CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

#define	CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

#define	CAN_CS_DLC_MASK (0xF0000U)

#define	CAN_CS_DLC_MASK (0xF0000U)

#define	CAN_CS_DLC_SHIFT (16U)

#define	CAN_CS_DLC_SHIFT (16U)

#define	CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

#define	CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

#define	CAN_CS_RTR_MASK (0x100000U)

#define	CAN_CS_RTR_MASK (0x100000U)

#define	CAN_CS_RTR_SHIFT (20U)

#define	CAN_CS_RTR_SHIFT (20U)

#define	CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

#define	CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

#define	CAN_CS_IDE_MASK (0x200000U)

#define	CAN_CS_IDE_MASK (0x200000U)

#define	CAN_CS_IDE_SHIFT (21U)

#define	CAN_CS_IDE_SHIFT (21U)

#define	CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

#define	CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

#define	CAN_CS_SRR_MASK (0x400000U)

#define	CAN_CS_SRR_MASK (0x400000U)

#define	CAN_CS_SRR_SHIFT (22U)

#define	CAN_CS_SRR_SHIFT (22U)

#define	CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

#define	CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

#define	CAN_CS_CODE_MASK (0xF000000U)

#define	CAN_CS_CODE_MASK (0xF000000U)

#define	CAN_CS_CODE_SHIFT (24U)

#define	CAN_CS_CODE_SHIFT (24U)

#define	CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

#define	CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

#define	CAN_CS_ESI_MASK (0x20000000U)

#define	CAN_CS_ESI_MASK (0x20000000U)

#define	CAN_CS_ESI_SHIFT (29U)

#define	CAN_CS_ESI_SHIFT (29U)

#define	CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)

#define	CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)

#define	CAN_CS_BRS_MASK (0x40000000U)

#define	CAN_CS_BRS_MASK (0x40000000U)

#define	CAN_CS_BRS_SHIFT (30U)

#define	CAN_CS_BRS_SHIFT (30U)

#define	CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)

#define	CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)

#define	CAN_CS_EDL_MASK (0x80000000U)

#define	CAN_CS_EDL_MASK (0x80000000U)

#define	CAN_CS_EDL_SHIFT (31U)

#define	CAN_CS_EDL_SHIFT (31U)

#define	CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)

#define	CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)

ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register
#define	CAN_ID_EXT_MASK (0x3FFFFU)

#define	CAN_ID_EXT_MASK (0x3FFFFU)

#define	CAN_ID_EXT_SHIFT (0U)

#define	CAN_ID_EXT_SHIFT (0U)

#define	CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

#define	CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

#define	CAN_ID_STD_MASK (0x1FFC0000U)

#define	CAN_ID_STD_MASK (0x1FFC0000U)

#define	CAN_ID_STD_SHIFT (18U)

#define	CAN_ID_STD_SHIFT (18U)

#define	CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

#define	CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

#define	CAN_ID_PRIO_MASK (0xE0000000U)

#define	CAN_ID_PRIO_MASK (0xE0000000U)

#define	CAN_ID_PRIO_SHIFT (29U)

#define	CAN_ID_PRIO_SHIFT (29U)

#define	CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)

#define	CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)

WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register
#define	CAN_WORD_DATA_BYTE_3_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_3_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_3_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_3_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)

#define	CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)

#define	CAN_WORD_DATA_BYTE_7_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_7_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_7_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_7_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)

#define	CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)

#define	CAN_WORD_DATA_BYTE_11_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_11_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_11_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_11_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)

#define	CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)

#define	CAN_WORD_DATA_BYTE_15_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_15_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_15_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_15_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)

#define	CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)

#define	CAN_WORD_DATA_BYTE_19_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_19_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_19_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_19_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)

#define	CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)

#define	CAN_WORD_DATA_BYTE_23_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_23_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_23_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_23_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)

#define	CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)

#define	CAN_WORD_DATA_BYTE_27_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_27_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_27_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_27_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)

#define	CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)

#define	CAN_WORD_DATA_BYTE_31_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_31_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_31_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_31_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)

#define	CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)

#define	CAN_WORD_DATA_BYTE_35_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_35_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_35_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_35_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)

#define	CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)

#define	CAN_WORD_DATA_BYTE_39_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_39_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_39_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_39_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)

#define	CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)

#define	CAN_WORD_DATA_BYTE_43_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_43_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_43_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_43_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)

#define	CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)

#define	CAN_WORD_DATA_BYTE_47_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_47_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_47_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_47_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)

#define	CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)

#define	CAN_WORD_DATA_BYTE_51_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_51_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_51_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_51_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)

#define	CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)

#define	CAN_WORD_DATA_BYTE_55_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_55_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_55_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_55_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)

#define	CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)

#define	CAN_WORD_DATA_BYTE_59_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_59_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_59_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_59_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)

#define	CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)

#define	CAN_WORD_DATA_BYTE_63_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_63_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_63_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_63_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)

#define	CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)

#define	CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_2_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_2_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)

#define	CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)

#define	CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_6_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_6_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)

#define	CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)

#define	CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_10_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_10_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)

#define	CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)

#define	CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_14_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_14_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)

#define	CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)

#define	CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_18_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_18_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)

#define	CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)

#define	CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_22_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_22_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)

#define	CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)

#define	CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_26_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_26_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)

#define	CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)

#define	CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_30_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_30_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)

#define	CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)

#define	CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_34_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_34_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)

#define	CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)

#define	CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_38_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_38_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)

#define	CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)

#define	CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_42_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_42_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)

#define	CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)

#define	CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_46_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_46_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)

#define	CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)

#define	CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_50_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_50_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)

#define	CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)

#define	CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_54_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_54_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)

#define	CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)

#define	CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_58_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_58_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)

#define	CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)

#define	CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_62_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_62_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)

#define	CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)

#define	CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_1_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_1_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)

#define	CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)

#define	CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_5_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_5_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)

#define	CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)

#define	CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_9_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_9_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)

#define	CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)

#define	CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_13_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_13_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)

#define	CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)

#define	CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_17_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_17_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)

#define	CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)

#define	CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_21_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_21_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)

#define	CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)

#define	CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_25_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_25_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)

#define	CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)

#define	CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_29_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_29_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)

#define	CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)

#define	CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_33_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_33_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)

#define	CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)

#define	CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_37_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_37_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)

#define	CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)

#define	CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_41_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_41_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)

#define	CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)

#define	CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_45_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_45_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)

#define	CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)

#define	CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_49_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_49_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)

#define	CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)

#define	CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_53_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_53_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)

#define	CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)

#define	CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_57_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_57_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)

#define	CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)

#define	CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_61_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_61_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)

#define	CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)

#define	CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_0_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_0_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)

#define	CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)

#define	CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_4_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_4_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)

#define	CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)

#define	CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_8_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_8_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)

#define	CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)

#define	CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_12_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_12_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)

#define	CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)

#define	CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_16_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_16_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)

#define	CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)

#define	CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_20_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_20_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)

#define	CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)

#define	CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_24_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_24_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)

#define	CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)

#define	CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_28_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_28_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)

#define	CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)

#define	CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_32_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_32_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)

#define	CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)

#define	CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_36_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_36_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)

#define	CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)

#define	CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_40_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_40_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)

#define	CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)

#define	CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_44_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_44_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)

#define	CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)

#define	CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_48_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_48_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)

#define	CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)

#define	CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_52_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_52_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)

#define	CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)

#define	CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_56_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_56_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)

#define	CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)

#define	CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_60_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_60_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)

#define	CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)

WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register
#define	CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)

#define	CAN_WORD0_DATA_BYTE_3_SHIFT (0U)

#define	CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)

#define	CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)

#define	CAN_WORD0_DATA_BYTE_2_SHIFT (8U)

#define	CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)

#define	CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)

#define	CAN_WORD0_DATA_BYTE_1_SHIFT (16U)

#define	CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)

#define	CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)

#define	CAN_WORD0_DATA_BYTE_0_SHIFT (24U)

#define	CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)

WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register
#define	CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)

#define	CAN_WORD1_DATA_BYTE_7_SHIFT (0U)

#define	CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)

#define	CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)

#define	CAN_WORD1_DATA_BYTE_6_SHIFT (8U)

#define	CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)

#define	CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)

#define	CAN_WORD1_DATA_BYTE_5_SHIFT (16U)

#define	CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)

#define	CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)

#define	CAN_WORD1_DATA_BYTE_4_SHIFT (24U)

#define	CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)

RXIMR - Rx Individual Mask registers
#define	CAN_RXIMR_MI_MASK (0xFFFFFFFFU)

#define	CAN_RXIMR_MI_SHIFT (0U)

#define	CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

MECR - Memory Error Control register
#define	CAN_MECR_NCEFAFRZ_MASK (0x80U)

#define	CAN_MECR_NCEFAFRZ_SHIFT (7U)

#define	CAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)

#define	CAN_MECR_ECCDIS_MASK (0x100U)

#define	CAN_MECR_ECCDIS_SHIFT (8U)

#define	CAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)

#define	CAN_MECR_RERRDIS_MASK (0x200U)

#define	CAN_MECR_RERRDIS_SHIFT (9U)

#define	CAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)

#define	CAN_MECR_EXTERRIE_MASK (0x2000U)

#define	CAN_MECR_EXTERRIE_SHIFT (13U)

#define	CAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)

#define	CAN_MECR_FAERRIE_MASK (0x4000U)

#define	CAN_MECR_FAERRIE_SHIFT (14U)

#define	CAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)

#define	CAN_MECR_HAERRIE_MASK (0x8000U)

#define	CAN_MECR_HAERRIE_SHIFT (15U)

#define	CAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)

#define	CAN_MECR_CEI_MSK_MASK (0x10000U)

#define	CAN_MECR_CEI_MSK_SHIFT (16U)

#define	CAN_MECR_CEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)

#define	CAN_MECR_FANCEI_MSK_MASK (0x40000U)

#define	CAN_MECR_FANCEI_MSK_SHIFT (18U)

#define	CAN_MECR_FANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)

#define	CAN_MECR_HANCEI_MSK_MASK (0x80000U)

#define	CAN_MECR_HANCEI_MSK_SHIFT (19U)

#define	CAN_MECR_HANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)

#define	CAN_MECR_ECRWRDIS_MASK (0x80000000U)

#define	CAN_MECR_ECRWRDIS_SHIFT (31U)

#define	CAN_MECR_ECRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)

ERRIAR - Error Injection Address register
#define	CAN_ERRIAR_INJADDR_L_MASK (0x3U)

#define	CAN_ERRIAR_INJADDR_L_SHIFT (0U)

#define	CAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)

#define	CAN_ERRIAR_INJADDR_H_MASK (0x3FFCU)

#define	CAN_ERRIAR_INJADDR_H_SHIFT (2U)

#define	CAN_ERRIAR_INJADDR_H(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)

ERRIDPR - Error Injection Data Pattern register
#define	CAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU)

#define	CAN_ERRIDPR_DFLIP_SHIFT (0U)

#define	CAN_ERRIDPR_DFLIP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)

ERRIPPR - Error Injection Parity Pattern register
#define	CAN_ERRIPPR_PFLIP0_MASK (0x1FU)

#define	CAN_ERRIPPR_PFLIP0_SHIFT (0U)

#define	CAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)

#define	CAN_ERRIPPR_PFLIP1_MASK (0x1F00U)

#define	CAN_ERRIPPR_PFLIP1_SHIFT (8U)

#define	CAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)

#define	CAN_ERRIPPR_PFLIP2_MASK (0x1F0000U)

#define	CAN_ERRIPPR_PFLIP2_SHIFT (16U)

#define	CAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)

#define	CAN_ERRIPPR_PFLIP3_MASK (0x1F000000U)

#define	CAN_ERRIPPR_PFLIP3_SHIFT (24U)

#define	CAN_ERRIPPR_PFLIP3(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)

RERRAR - Error Report Address register
#define	CAN_RERRAR_ERRADDR_MASK (0x3FFFU)

#define	CAN_RERRAR_ERRADDR_SHIFT (0U)

#define	CAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)

#define	CAN_RERRAR_SAID_MASK (0x70000U)

#define	CAN_RERRAR_SAID_SHIFT (16U)

#define	CAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)

#define	CAN_RERRAR_NCE_MASK (0x1000000U)

#define	CAN_RERRAR_NCE_SHIFT (24U)

#define	CAN_RERRAR_NCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)

RERRDR - Error Report Data register
#define	CAN_RERRDR_RDATA_MASK (0xFFFFFFFFU)

#define	CAN_RERRDR_RDATA_SHIFT (0U)

#define	CAN_RERRDR_RDATA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)

RERRSYNR - Error Report Syndrome register
#define	CAN_RERRSYNR_SYND0_MASK (0x1FU)

#define	CAN_RERRSYNR_SYND0_SHIFT (0U)

#define	CAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)

#define	CAN_RERRSYNR_BE0_MASK (0x80U)

#define	CAN_RERRSYNR_BE0_SHIFT (7U)

#define	CAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)

#define	CAN_RERRSYNR_SYND1_MASK (0x1F00U)

#define	CAN_RERRSYNR_SYND1_SHIFT (8U)

#define	CAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)

#define	CAN_RERRSYNR_BE1_MASK (0x8000U)

#define	CAN_RERRSYNR_BE1_SHIFT (15U)

#define	CAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)

#define	CAN_RERRSYNR_SYND2_MASK (0x1F0000U)

#define	CAN_RERRSYNR_SYND2_SHIFT (16U)

#define	CAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)

#define	CAN_RERRSYNR_BE2_MASK (0x800000U)

#define	CAN_RERRSYNR_BE2_SHIFT (23U)

#define	CAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)

#define	CAN_RERRSYNR_SYND3_MASK (0x1F000000U)

#define	CAN_RERRSYNR_SYND3_SHIFT (24U)

#define	CAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)

#define	CAN_RERRSYNR_BE3_MASK (0x80000000U)

#define	CAN_RERRSYNR_BE3_SHIFT (31U)

#define	CAN_RERRSYNR_BE3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)

ERRSR - Error Status register
#define	CAN_ERRSR_CEIOF_MASK (0x1U)

#define	CAN_ERRSR_CEIOF_SHIFT (0U)

#define	CAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)

#define	CAN_ERRSR_FANCEIOF_MASK (0x4U)

#define	CAN_ERRSR_FANCEIOF_SHIFT (2U)

#define	CAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)

#define	CAN_ERRSR_HANCEIOF_MASK (0x8U)

#define	CAN_ERRSR_HANCEIOF_SHIFT (3U)

#define	CAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)

#define	CAN_ERRSR_CEIF_MASK (0x10000U)

#define	CAN_ERRSR_CEIF_SHIFT (16U)

#define	CAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)

#define	CAN_ERRSR_FANCEIF_MASK (0x40000U)

#define	CAN_ERRSR_FANCEIF_SHIFT (18U)

#define	CAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)

#define	CAN_ERRSR_HANCEIF_MASK (0x80000U)

#define	CAN_ERRSR_HANCEIF_SHIFT (19U)

#define	CAN_ERRSR_HANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)

FDCTRL - CAN FD Control register
#define	CAN_FDCTRL_TDCVAL_MASK (0x3FU)

#define	CAN_FDCTRL_TDCVAL_SHIFT (0U)

#define	CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)

#define	CAN_FDCTRL_TDCOFF_MASK (0x1F00U)

#define	CAN_FDCTRL_TDCOFF_SHIFT (8U)

#define	CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)

#define	CAN_FDCTRL_TDCFAIL_MASK (0x4000U)

#define	CAN_FDCTRL_TDCFAIL_SHIFT (14U)

#define	CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)

#define	CAN_FDCTRL_TDCEN_MASK (0x8000U)

#define	CAN_FDCTRL_TDCEN_SHIFT (15U)

#define	CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)

#define	CAN_FDCTRL_MBDSR0_MASK (0x30000U)

#define	CAN_FDCTRL_MBDSR0_SHIFT (16U)

#define	CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)

#define	CAN_FDCTRL_MBDSR1_MASK (0x180000U)

#define	CAN_FDCTRL_MBDSR1_SHIFT (19U)

#define	CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)

#define	CAN_FDCTRL_FDRATE_MASK (0x80000000U)

#define	CAN_FDCTRL_FDRATE_SHIFT (31U)

#define	CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)

FDCBT - CAN FD Bit Timing register
#define	CAN_FDCBT_FPSEG2_MASK (0x7U)

#define	CAN_FDCBT_FPSEG2_SHIFT (0U)

#define	CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)

#define	CAN_FDCBT_FPSEG1_MASK (0xE0U)

#define	CAN_FDCBT_FPSEG1_SHIFT (5U)

#define	CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)

#define	CAN_FDCBT_FPROPSEG_MASK (0x7C00U)

#define	CAN_FDCBT_FPROPSEG_SHIFT (10U)

#define	CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)

#define	CAN_FDCBT_FRJW_MASK (0x70000U)

#define	CAN_FDCBT_FRJW_SHIFT (16U)

#define	CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)

#define	CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)

#define	CAN_FDCBT_FPRESDIV_SHIFT (20U)

#define	CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)

FDCRC - CAN FD CRC register
#define	CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)

#define	CAN_FDCRC_FD_TXCRC_SHIFT (0U)

#define	CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)

#define	CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)

#define	CAN_FDCRC_FD_MBCRC_SHIFT (24U)

#define	CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)

MCR - Module Configuration register
#define	CAN_MCR_MAXMB_MASK (0x7FU)

#define	CAN_MCR_MAXMB_SHIFT (0U)

#define	CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)

#define	CAN_MCR_IDAM_MASK (0x300U)

#define	CAN_MCR_IDAM_SHIFT (8U)

#define	CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

#define	CAN_MCR_FDEN_MASK (0x800U)

#define	CAN_MCR_FDEN_SHIFT (11U)

#define	CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)

#define	CAN_MCR_AEN_MASK (0x1000U)

#define	CAN_MCR_AEN_SHIFT (12U)

#define	CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

#define	CAN_MCR_LPRIOEN_MASK (0x2000U)

#define	CAN_MCR_LPRIOEN_SHIFT (13U)

#define	CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

#define	CAN_MCR_DMA_MASK (0x8000U)

#define	CAN_MCR_DMA_SHIFT (15U)

#define	CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)

#define	CAN_MCR_IRMQ_MASK (0x10000U)

#define	CAN_MCR_IRMQ_SHIFT (16U)

#define	CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

#define	CAN_MCR_SRXDIS_MASK (0x20000U)

#define	CAN_MCR_SRXDIS_SHIFT (17U)

#define	CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

#define	CAN_MCR_DOZE_MASK (0x40000U)

#define	CAN_MCR_DOZE_SHIFT (18U)

#define	CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)

#define	CAN_MCR_WAKSRC_MASK (0x80000U)

#define	CAN_MCR_WAKSRC_SHIFT (19U)

#define	CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

#define	CAN_MCR_LPMACK_MASK (0x100000U)

#define	CAN_MCR_LPMACK_SHIFT (20U)

#define	CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

#define	CAN_MCR_WRNEN_MASK (0x200000U)

#define	CAN_MCR_WRNEN_SHIFT (21U)

#define	CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

#define	CAN_MCR_SLFWAK_MASK (0x400000U)

#define	CAN_MCR_SLFWAK_SHIFT (22U)

#define	CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

#define	CAN_MCR_SUPV_MASK (0x800000U)

#define	CAN_MCR_SUPV_SHIFT (23U)

#define	CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

#define	CAN_MCR_FRZACK_MASK (0x1000000U)

#define	CAN_MCR_FRZACK_SHIFT (24U)

#define	CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

#define	CAN_MCR_SOFTRST_MASK (0x2000000U)

#define	CAN_MCR_SOFTRST_SHIFT (25U)

#define	CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

#define	CAN_MCR_WAKMSK_MASK (0x4000000U)

#define	CAN_MCR_WAKMSK_SHIFT (26U)

#define	CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

#define	CAN_MCR_NOTRDY_MASK (0x8000000U)

#define	CAN_MCR_NOTRDY_SHIFT (27U)

#define	CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

#define	CAN_MCR_HALT_MASK (0x10000000U)

#define	CAN_MCR_HALT_SHIFT (28U)

#define	CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

#define	CAN_MCR_RFEN_MASK (0x20000000U)

#define	CAN_MCR_RFEN_SHIFT (29U)

#define	CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

#define	CAN_MCR_FRZ_MASK (0x40000000U)

#define	CAN_MCR_FRZ_SHIFT (30U)

#define	CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

#define	CAN_MCR_MDIS_MASK (0x80000000U)

#define	CAN_MCR_MDIS_SHIFT (31U)

#define	CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

CTRL1 - Control 1 register
#define	CAN_CTRL1_PROPSEG_MASK (0x7U)

#define	CAN_CTRL1_PROPSEG_SHIFT (0U)

#define	CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)

#define	CAN_CTRL1_LOM_MASK (0x8U)

#define	CAN_CTRL1_LOM_SHIFT (3U)

#define	CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

#define	CAN_CTRL1_LBUF_MASK (0x10U)

#define	CAN_CTRL1_LBUF_SHIFT (4U)

#define	CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

#define	CAN_CTRL1_TSYN_MASK (0x20U)

#define	CAN_CTRL1_TSYN_SHIFT (5U)

#define	CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

#define	CAN_CTRL1_BOFFREC_MASK (0x40U)

#define	CAN_CTRL1_BOFFREC_SHIFT (6U)

#define	CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

#define	CAN_CTRL1_SMP_MASK (0x80U)

#define	CAN_CTRL1_SMP_SHIFT (7U)

#define	CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

#define	CAN_CTRL1_RWRNMSK_MASK (0x400U)

#define	CAN_CTRL1_RWRNMSK_SHIFT (10U)

#define	CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

#define	CAN_CTRL1_TWRNMSK_MASK (0x800U)

#define	CAN_CTRL1_TWRNMSK_SHIFT (11U)

#define	CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

#define	CAN_CTRL1_LPB_MASK (0x1000U)

#define	CAN_CTRL1_LPB_SHIFT (12U)

#define	CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

#define	CAN_CTRL1_CLKSRC_MASK (0x2000U)

#define	CAN_CTRL1_CLKSRC_SHIFT (13U)

#define	CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)

#define	CAN_CTRL1_ERRMSK_MASK (0x4000U)

#define	CAN_CTRL1_ERRMSK_SHIFT (14U)

#define	CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

#define	CAN_CTRL1_BOFFMSK_MASK (0x8000U)

#define	CAN_CTRL1_BOFFMSK_SHIFT (15U)

#define	CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

#define	CAN_CTRL1_PSEG2_MASK (0x70000U)

#define	CAN_CTRL1_PSEG2_SHIFT (16U)

#define	CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)

#define	CAN_CTRL1_PSEG1_MASK (0x380000U)

#define	CAN_CTRL1_PSEG1_SHIFT (19U)

#define	CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)

#define	CAN_CTRL1_RJW_MASK (0xC00000U)

#define	CAN_CTRL1_RJW_SHIFT (22U)

#define	CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)

#define	CAN_CTRL1_PRESDIV_MASK (0xFF000000U)

#define	CAN_CTRL1_PRESDIV_SHIFT (24U)

#define	CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)

TIMER - Free Running Timer
#define	CAN_TIMER_TIMER_MASK (0xFFFFU)

#define	CAN_TIMER_TIMER_SHIFT (0U)

#define	CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)

RXMGMASK - Rx Mailboxes Global Mask register
#define	CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)

#define	CAN_RXMGMASK_MG_SHIFT (0U)

#define	CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

RX14MASK - Rx 14 Mask register
#define	CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)

#define	CAN_RX14MASK_RX14M_SHIFT (0U)

#define	CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX15MASK - Rx 15 Mask register
#define	CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)

#define	CAN_RX15MASK_RX15M_SHIFT (0U)

#define	CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

ECR - Error Counter
#define	CAN_ECR_TXERRCNT_MASK (0xFFU)

#define	CAN_ECR_TXERRCNT_SHIFT (0U)

#define	CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)

#define	CAN_ECR_RXERRCNT_MASK (0xFF00U)

#define	CAN_ECR_RXERRCNT_SHIFT (8U)

#define	CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)

#define	CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)

#define	CAN_ECR_TXERRCNT_FAST_SHIFT (16U)

#define	CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)

#define	CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)

#define	CAN_ECR_RXERRCNT_FAST_SHIFT (24U)

#define	CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)

ESR1 - Error and Status 1 register
#define	CAN_ESR1_WAKINT_MASK (0x1U)

#define	CAN_ESR1_WAKINT_SHIFT (0U)

#define	CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

#define	CAN_ESR1_ERRINT_MASK (0x2U)

#define	CAN_ESR1_ERRINT_SHIFT (1U)

#define	CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

#define	CAN_ESR1_BOFFINT_MASK (0x4U)

#define	CAN_ESR1_BOFFINT_SHIFT (2U)

#define	CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

#define	CAN_ESR1_RX_MASK (0x8U)

#define	CAN_ESR1_RX_SHIFT (3U)

#define	CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

#define	CAN_ESR1_FLTCONF_MASK (0x30U)

#define	CAN_ESR1_FLTCONF_SHIFT (4U)

#define	CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

#define	CAN_ESR1_TX_MASK (0x40U)

#define	CAN_ESR1_TX_SHIFT (6U)

#define	CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

#define	CAN_ESR1_IDLE_MASK (0x80U)

#define	CAN_ESR1_IDLE_SHIFT (7U)

#define	CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

#define	CAN_ESR1_RXWRN_MASK (0x100U)

#define	CAN_ESR1_RXWRN_SHIFT (8U)

#define	CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

#define	CAN_ESR1_TXWRN_MASK (0x200U)

#define	CAN_ESR1_TXWRN_SHIFT (9U)

#define	CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

#define	CAN_ESR1_STFERR_MASK (0x400U)

#define	CAN_ESR1_STFERR_SHIFT (10U)

#define	CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

#define	CAN_ESR1_FRMERR_MASK (0x800U)

#define	CAN_ESR1_FRMERR_SHIFT (11U)

#define	CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

#define	CAN_ESR1_CRCERR_MASK (0x1000U)

#define	CAN_ESR1_CRCERR_SHIFT (12U)

#define	CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

#define	CAN_ESR1_ACKERR_MASK (0x2000U)

#define	CAN_ESR1_ACKERR_SHIFT (13U)

#define	CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

#define	CAN_ESR1_BIT0ERR_MASK (0x4000U)

#define	CAN_ESR1_BIT0ERR_SHIFT (14U)

#define	CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

#define	CAN_ESR1_BIT1ERR_MASK (0x8000U)

#define	CAN_ESR1_BIT1ERR_SHIFT (15U)

#define	CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

#define	CAN_ESR1_RWRNINT_MASK (0x10000U)

#define	CAN_ESR1_RWRNINT_SHIFT (16U)

#define	CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

#define	CAN_ESR1_TWRNINT_MASK (0x20000U)

#define	CAN_ESR1_TWRNINT_SHIFT (17U)

#define	CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

#define	CAN_ESR1_SYNCH_MASK (0x40000U)

#define	CAN_ESR1_SYNCH_SHIFT (18U)

#define	CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

#define	CAN_ESR1_BOFFDONEINT_MASK (0x80000U)

#define	CAN_ESR1_BOFFDONEINT_SHIFT (19U)

#define	CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)

#define	CAN_ESR1_ERRINT_FAST_MASK (0x100000U)

#define	CAN_ESR1_ERRINT_FAST_SHIFT (20U)

#define	CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)

#define	CAN_ESR1_ERROVR_MASK (0x200000U)

#define	CAN_ESR1_ERROVR_SHIFT (21U)

#define	CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)

#define	CAN_ESR1_STFERR_FAST_MASK (0x4000000U)

#define	CAN_ESR1_STFERR_FAST_SHIFT (26U)

#define	CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)

#define	CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)

#define	CAN_ESR1_FRMERR_FAST_SHIFT (27U)

#define	CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)

#define	CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)

#define	CAN_ESR1_CRCERR_FAST_SHIFT (28U)

#define	CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)

#define	CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)

#define	CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)

#define	CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)

#define	CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)

#define	CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)

#define	CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)

IMASK2 - Interrupt Masks 2 register
#define	CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)

#define	CAN_IMASK2_BUF63TO32M_SHIFT (0U)

#define	CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)

IMASK1 - Interrupt Masks 1 register
#define	CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)

#define	CAN_IMASK1_BUF31TO0M_SHIFT (0U)

#define	CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)

IFLAG2 - Interrupt Flags 2 register
#define	CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)

#define	CAN_IFLAG2_BUF63TO32I_SHIFT (0U)

#define	CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)

IFLAG1 - Interrupt Flags 1 register
#define	CAN_IFLAG1_BUF0I_MASK (0x1U)

#define	CAN_IFLAG1_BUF0I_SHIFT (0U)

#define	CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)

#define	CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)

#define	CAN_IFLAG1_BUF4TO1I_SHIFT (1U)

#define	CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)

#define	CAN_IFLAG1_BUF5I_MASK (0x20U)

#define	CAN_IFLAG1_BUF5I_SHIFT (5U)

#define	CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

#define	CAN_IFLAG1_BUF6I_MASK (0x40U)

#define	CAN_IFLAG1_BUF6I_SHIFT (6U)

#define	CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

#define	CAN_IFLAG1_BUF7I_MASK (0x80U)

#define	CAN_IFLAG1_BUF7I_SHIFT (7U)

#define	CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

#define	CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)

#define	CAN_IFLAG1_BUF31TO8I_SHIFT (8U)

#define	CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

CTRL2 - Control 2 register
#define	CAN_CTRL2_EDFLTDIS_MASK (0x800U)

#define	CAN_CTRL2_EDFLTDIS_SHIFT (11U)

#define	CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)

#define	CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)

#define	CAN_CTRL2_ISOCANFDEN_SHIFT (12U)

#define	CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)

#define	CAN_CTRL2_PREXCEN_MASK (0x4000U)

#define	CAN_CTRL2_PREXCEN_SHIFT (14U)

#define	CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)

#define	CAN_CTRL2_TIMER_SRC_MASK (0x8000U)

#define	CAN_CTRL2_TIMER_SRC_SHIFT (15U)

#define	CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)

#define	CAN_CTRL2_EACEN_MASK (0x10000U)

#define	CAN_CTRL2_EACEN_SHIFT (16U)

#define	CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

#define	CAN_CTRL2_RRS_MASK (0x20000U)

#define	CAN_CTRL2_RRS_SHIFT (17U)

#define	CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

#define	CAN_CTRL2_MRP_MASK (0x40000U)

#define	CAN_CTRL2_MRP_SHIFT (18U)

#define	CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

#define	CAN_CTRL2_TASD_MASK (0xF80000U)

#define	CAN_CTRL2_TASD_SHIFT (19U)

#define	CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)

#define	CAN_CTRL2_RFFN_MASK (0xF000000U)

#define	CAN_CTRL2_RFFN_SHIFT (24U)

#define	CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)

#define	CAN_CTRL2_WRMFRZ_MASK (0x10000000U)

#define	CAN_CTRL2_WRMFRZ_SHIFT (28U)

#define	CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)

#define	CAN_CTRL2_ECRWRE_MASK (0x20000000U)

#define	CAN_CTRL2_ECRWRE_SHIFT (29U)

#define	CAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)

#define	CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)

#define	CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)

#define	CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)

#define	CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)

#define	CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)

#define	CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)

#define	ENC_CTRL2_UPDHLD_MASK (0x1U)

#define	ENC_CTRL2_UPDHLD_SHIFT (0U)

#define	ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

#define	ENC_CTRL2_UPDPOS_MASK (0x2U)

#define	ENC_CTRL2_UPDPOS_SHIFT (1U)

#define	ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

#define	ENC_CTRL2_MOD_MASK (0x4U)

#define	ENC_CTRL2_MOD_SHIFT (2U)

#define	ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

#define	ENC_CTRL2_DIR_MASK (0x8U)

#define	ENC_CTRL2_DIR_SHIFT (3U)

#define	ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

#define	ENC_CTRL2_RUIE_MASK (0x10U)

#define	ENC_CTRL2_RUIE_SHIFT (4U)

#define	ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

#define	ENC_CTRL2_RUIRQ_MASK (0x20U)

#define	ENC_CTRL2_RUIRQ_SHIFT (5U)

#define	ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

#define	ENC_CTRL2_ROIE_MASK (0x40U)

#define	ENC_CTRL2_ROIE_SHIFT (6U)

#define	ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

#define	ENC_CTRL2_ROIRQ_MASK (0x80U)

#define	ENC_CTRL2_ROIRQ_SHIFT (7U)

#define	ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

#define	ENC_CTRL2_REVMOD_MASK (0x100U)

#define	ENC_CTRL2_REVMOD_SHIFT (8U)

#define	ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

#define	ENC_CTRL2_OUTCTL_MASK (0x200U)

#define	ENC_CTRL2_OUTCTL_SHIFT (9U)

#define	ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

#define	ENC_CTRL2_SABIE_MASK (0x400U)

#define	ENC_CTRL2_SABIE_SHIFT (10U)

#define	ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)

#define	ENC_CTRL2_SABIRQ_MASK (0x800U)

#define	ENC_CTRL2_SABIRQ_SHIFT (11U)

#define	ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)

#define	PWM_CTRL2_CLK_SEL_MASK (0x3U)

#define	PWM_CTRL2_CLK_SEL_SHIFT (0U)

#define	PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)

#define	PWM_CTRL2_RELOAD_SEL_MASK (0x4U)

#define	PWM_CTRL2_RELOAD_SEL_SHIFT (2U)

#define	PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)

#define	PWM_CTRL2_FORCE_SEL_MASK (0x38U)

#define	PWM_CTRL2_FORCE_SEL_SHIFT (3U)

#define	PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)

#define	PWM_CTRL2_FORCE_MASK (0x40U)

#define	PWM_CTRL2_FORCE_SHIFT (6U)

#define	PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)

#define	PWM_CTRL2_FRCEN_MASK (0x80U)

#define	PWM_CTRL2_FRCEN_SHIFT (7U)

#define	PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)

#define	PWM_CTRL2_INIT_SEL_MASK (0x300U)

#define	PWM_CTRL2_INIT_SEL_SHIFT (8U)

#define	PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)

#define	PWM_CTRL2_PWMX_INIT_MASK (0x400U)

#define	PWM_CTRL2_PWMX_INIT_SHIFT (10U)

#define	PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)

#define	PWM_CTRL2_PWM45_INIT_MASK (0x800U)

#define	PWM_CTRL2_PWM45_INIT_SHIFT (11U)

#define	PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)

#define	PWM_CTRL2_PWM23_INIT_MASK (0x1000U)

#define	PWM_CTRL2_PWM23_INIT_SHIFT (12U)

#define	PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)

#define	PWM_CTRL2_INDEP_MASK (0x2000U)

#define	PWM_CTRL2_INDEP_SHIFT (13U)

#define	PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)

#define	PWM_CTRL2_WAITEN_MASK (0x4000U)

#define	PWM_CTRL2_WAITEN_SHIFT (14U)

#define	PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)

#define	PWM_CTRL2_DBGEN_MASK (0x8000U)

#define	PWM_CTRL2_DBGEN_SHIFT (15U)

#define	PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)

ESR2 - Error and Status 2 register
#define	CAN_ESR2_IMB_MASK (0x2000U)

#define	CAN_ESR2_IMB_SHIFT (13U)

#define	CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

#define	CAN_ESR2_VPS_MASK (0x4000U)

#define	CAN_ESR2_VPS_SHIFT (14U)

#define	CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

#define	CAN_ESR2_LPTM_MASK (0x7F0000U)

#define	CAN_ESR2_LPTM_SHIFT (16U)

#define	CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)

CRCR - CRC register
#define	CAN_CRCR_TXCRC_MASK (0x7FFFU)

#define	CAN_CRCR_TXCRC_SHIFT (0U)

#define	CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)

#define	CAN_CRCR_MBCRC_MASK (0x7F0000U)

#define	CAN_CRCR_MBCRC_SHIFT (16U)

#define	CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)

RXFGMASK - Rx FIFO Global Mask register
#define	CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)

#define	CAN_RXFGMASK_FGM_SHIFT (0U)

#define	CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

RXFIR - Rx FIFO Information register
#define	CAN_RXFIR_IDHIT_MASK (0x1FFU)

#define	CAN_RXFIR_IDHIT_SHIFT (0U)

#define	CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)

CBT - CAN Bit Timing register
#define	CAN_CBT_EPSEG2_MASK (0x1FU)

#define	CAN_CBT_EPSEG2_SHIFT (0U)

#define	CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)

#define	CAN_CBT_EPSEG1_MASK (0x3E0U)

#define	CAN_CBT_EPSEG1_SHIFT (5U)

#define	CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)

#define	CAN_CBT_EPROPSEG_MASK (0xFC00U)

#define	CAN_CBT_EPROPSEG_SHIFT (10U)

#define	CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)

#define	CAN_CBT_ERJW_MASK (0x1F0000U)

#define	CAN_CBT_ERJW_SHIFT (16U)

#define	CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)

#define	CAN_CBT_EPRESDIV_MASK (0x7FE00000U)

#define	CAN_CBT_EPRESDIV_SHIFT (21U)

#define	CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)

#define	CAN_CBT_BTF_MASK (0x80000000U)

#define	CAN_CBT_BTF_SHIFT (31U)

#define	CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)

CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register
#define	CAN_CS_TIME_STAMP_MASK (0xFFFFU)

#define	CAN_CS_TIME_STAMP_MASK (0xFFFFU)

#define	CAN_CS_TIME_STAMP_SHIFT (0U)

#define	CAN_CS_TIME_STAMP_SHIFT (0U)

#define	CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

#define	CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

#define	CAN_CS_DLC_MASK (0xF0000U)

#define	CAN_CS_DLC_MASK (0xF0000U)

#define	CAN_CS_DLC_SHIFT (16U)

#define	CAN_CS_DLC_SHIFT (16U)

#define	CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

#define	CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

#define	CAN_CS_RTR_MASK (0x100000U)

#define	CAN_CS_RTR_MASK (0x100000U)

#define	CAN_CS_RTR_SHIFT (20U)

#define	CAN_CS_RTR_SHIFT (20U)

#define	CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

#define	CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

#define	CAN_CS_IDE_MASK (0x200000U)

#define	CAN_CS_IDE_MASK (0x200000U)

#define	CAN_CS_IDE_SHIFT (21U)

#define	CAN_CS_IDE_SHIFT (21U)

#define	CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

#define	CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

#define	CAN_CS_SRR_MASK (0x400000U)

#define	CAN_CS_SRR_MASK (0x400000U)

#define	CAN_CS_SRR_SHIFT (22U)

#define	CAN_CS_SRR_SHIFT (22U)

#define	CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

#define	CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

#define	CAN_CS_CODE_MASK (0xF000000U)

#define	CAN_CS_CODE_MASK (0xF000000U)

#define	CAN_CS_CODE_SHIFT (24U)

#define	CAN_CS_CODE_SHIFT (24U)

#define	CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

#define	CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

#define	CAN_CS_ESI_MASK (0x20000000U)

#define	CAN_CS_ESI_MASK (0x20000000U)

#define	CAN_CS_ESI_SHIFT (29U)

#define	CAN_CS_ESI_SHIFT (29U)

#define	CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)

#define	CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)

#define	CAN_CS_BRS_MASK (0x40000000U)

#define	CAN_CS_BRS_MASK (0x40000000U)

#define	CAN_CS_BRS_SHIFT (30U)

#define	CAN_CS_BRS_SHIFT (30U)

#define	CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)

#define	CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)

#define	CAN_CS_EDL_MASK (0x80000000U)

#define	CAN_CS_EDL_MASK (0x80000000U)

#define	CAN_CS_EDL_SHIFT (31U)

#define	CAN_CS_EDL_SHIFT (31U)

#define	CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)

#define	CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)

ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register
#define	CAN_ID_EXT_MASK (0x3FFFFU)

#define	CAN_ID_EXT_MASK (0x3FFFFU)

#define	CAN_ID_EXT_SHIFT (0U)

#define	CAN_ID_EXT_SHIFT (0U)

#define	CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

#define	CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

#define	CAN_ID_STD_MASK (0x1FFC0000U)

#define	CAN_ID_STD_MASK (0x1FFC0000U)

#define	CAN_ID_STD_SHIFT (18U)

#define	CAN_ID_STD_SHIFT (18U)

#define	CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

#define	CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

#define	CAN_ID_PRIO_MASK (0xE0000000U)

#define	CAN_ID_PRIO_MASK (0xE0000000U)

#define	CAN_ID_PRIO_SHIFT (29U)

#define	CAN_ID_PRIO_SHIFT (29U)

#define	CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)

#define	CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)

WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register
#define	CAN_WORD_DATA_BYTE_3_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_3_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_3_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_3_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)

#define	CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)

#define	CAN_WORD_DATA_BYTE_7_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_7_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_7_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_7_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)

#define	CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)

#define	CAN_WORD_DATA_BYTE_11_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_11_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_11_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_11_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)

#define	CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)

#define	CAN_WORD_DATA_BYTE_15_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_15_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_15_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_15_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)

#define	CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)

#define	CAN_WORD_DATA_BYTE_19_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_19_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_19_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_19_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)

#define	CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)

#define	CAN_WORD_DATA_BYTE_23_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_23_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_23_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_23_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)

#define	CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)

#define	CAN_WORD_DATA_BYTE_27_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_27_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_27_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_27_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)

#define	CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)

#define	CAN_WORD_DATA_BYTE_31_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_31_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_31_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_31_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)

#define	CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)

#define	CAN_WORD_DATA_BYTE_35_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_35_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_35_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_35_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)

#define	CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)

#define	CAN_WORD_DATA_BYTE_39_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_39_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_39_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_39_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)

#define	CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)

#define	CAN_WORD_DATA_BYTE_43_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_43_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_43_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_43_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)

#define	CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)

#define	CAN_WORD_DATA_BYTE_47_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_47_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_47_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_47_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)

#define	CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)

#define	CAN_WORD_DATA_BYTE_51_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_51_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_51_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_51_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)

#define	CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)

#define	CAN_WORD_DATA_BYTE_55_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_55_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_55_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_55_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)

#define	CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)

#define	CAN_WORD_DATA_BYTE_59_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_59_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_59_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_59_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)

#define	CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)

#define	CAN_WORD_DATA_BYTE_63_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_63_MASK (0xFFU)

#define	CAN_WORD_DATA_BYTE_63_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_63_SHIFT (0U)

#define	CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)

#define	CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)

#define	CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_2_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_2_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)

#define	CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)

#define	CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_6_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_6_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)

#define	CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)

#define	CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_10_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_10_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)

#define	CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)

#define	CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_14_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_14_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)

#define	CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)

#define	CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_18_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_18_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)

#define	CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)

#define	CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_22_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_22_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)

#define	CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)

#define	CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_26_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_26_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)

#define	CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)

#define	CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_30_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_30_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)

#define	CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)

#define	CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_34_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_34_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)

#define	CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)

#define	CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_38_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_38_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)

#define	CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)

#define	CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_42_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_42_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)

#define	CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)

#define	CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_46_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_46_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)

#define	CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)

#define	CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_50_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_50_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)

#define	CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)

#define	CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_54_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_54_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)

#define	CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)

#define	CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_58_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_58_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)

#define	CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)

#define	CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)

#define	CAN_WORD_DATA_BYTE_62_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_62_SHIFT (8U)

#define	CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)

#define	CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)

#define	CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_1_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_1_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)

#define	CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)

#define	CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_5_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_5_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)

#define	CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)

#define	CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_9_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_9_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)

#define	CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)

#define	CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_13_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_13_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)

#define	CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)

#define	CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_17_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_17_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)

#define	CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)

#define	CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_21_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_21_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)

#define	CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)

#define	CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_25_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_25_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)

#define	CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)

#define	CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_29_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_29_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)

#define	CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)

#define	CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_33_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_33_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)

#define	CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)

#define	CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_37_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_37_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)

#define	CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)

#define	CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_41_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_41_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)

#define	CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)

#define	CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_45_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_45_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)

#define	CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)

#define	CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_49_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_49_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)

#define	CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)

#define	CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_53_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_53_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)

#define	CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)

#define	CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_57_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_57_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)

#define	CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)

#define	CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)

#define	CAN_WORD_DATA_BYTE_61_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_61_SHIFT (16U)

#define	CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)

#define	CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)

#define	CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_0_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_0_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)

#define	CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)

#define	CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_4_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_4_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)

#define	CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)

#define	CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_8_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_8_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)

#define	CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)

#define	CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_12_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_12_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)

#define	CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)

#define	CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_16_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_16_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)

#define	CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)

#define	CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_20_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_20_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)

#define	CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)

#define	CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_24_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_24_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)

#define	CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)

#define	CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_28_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_28_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)

#define	CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)

#define	CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_32_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_32_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)

#define	CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)

#define	CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_36_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_36_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)

#define	CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)

#define	CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_40_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_40_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)

#define	CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)

#define	CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_44_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_44_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)

#define	CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)

#define	CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_48_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_48_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)

#define	CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)

#define	CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_52_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_52_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)

#define	CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)

#define	CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_56_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_56_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)

#define	CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)

#define	CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)

#define	CAN_WORD_DATA_BYTE_60_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_60_SHIFT (24U)

#define	CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)

#define	CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)

WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register
#define	CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)

#define	CAN_WORD0_DATA_BYTE_3_SHIFT (0U)

#define	CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)

#define	CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)

#define	CAN_WORD0_DATA_BYTE_2_SHIFT (8U)

#define	CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)

#define	CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)

#define	CAN_WORD0_DATA_BYTE_1_SHIFT (16U)

#define	CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)

#define	CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)

#define	CAN_WORD0_DATA_BYTE_0_SHIFT (24U)

#define	CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)

WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register
#define	CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)

#define	CAN_WORD1_DATA_BYTE_7_SHIFT (0U)

#define	CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)

#define	CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)

#define	CAN_WORD1_DATA_BYTE_6_SHIFT (8U)

#define	CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)

#define	CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)

#define	CAN_WORD1_DATA_BYTE_5_SHIFT (16U)

#define	CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)

#define	CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)

#define	CAN_WORD1_DATA_BYTE_4_SHIFT (24U)

#define	CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)

RXIMR - Rx Individual Mask registers
#define	CAN_RXIMR_MI_MASK (0xFFFFFFFFU)

#define	CAN_RXIMR_MI_SHIFT (0U)

#define	CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

MECR - Memory Error Control register
#define	CAN_MECR_NCEFAFRZ_MASK (0x80U)

#define	CAN_MECR_NCEFAFRZ_SHIFT (7U)

#define	CAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)

#define	CAN_MECR_ECCDIS_MASK (0x100U)

#define	CAN_MECR_ECCDIS_SHIFT (8U)

#define	CAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)

#define	CAN_MECR_RERRDIS_MASK (0x200U)

#define	CAN_MECR_RERRDIS_SHIFT (9U)

#define	CAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)

#define	CAN_MECR_EXTERRIE_MASK (0x2000U)

#define	CAN_MECR_EXTERRIE_SHIFT (13U)

#define	CAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)

#define	CAN_MECR_FAERRIE_MASK (0x4000U)

#define	CAN_MECR_FAERRIE_SHIFT (14U)

#define	CAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)

#define	CAN_MECR_HAERRIE_MASK (0x8000U)

#define	CAN_MECR_HAERRIE_SHIFT (15U)

#define	CAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)

#define	CAN_MECR_CEI_MSK_MASK (0x10000U)

#define	CAN_MECR_CEI_MSK_SHIFT (16U)

#define	CAN_MECR_CEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)

#define	CAN_MECR_FANCEI_MSK_MASK (0x40000U)

#define	CAN_MECR_FANCEI_MSK_SHIFT (18U)

#define	CAN_MECR_FANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)

#define	CAN_MECR_HANCEI_MSK_MASK (0x80000U)

#define	CAN_MECR_HANCEI_MSK_SHIFT (19U)

#define	CAN_MECR_HANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)

#define	CAN_MECR_ECRWRDIS_MASK (0x80000000U)

#define	CAN_MECR_ECRWRDIS_SHIFT (31U)

#define	CAN_MECR_ECRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)

ERRIAR - Error Injection Address register
#define	CAN_ERRIAR_INJADDR_L_MASK (0x3U)

#define	CAN_ERRIAR_INJADDR_L_SHIFT (0U)

#define	CAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)

#define	CAN_ERRIAR_INJADDR_H_MASK (0x3FFCU)

#define	CAN_ERRIAR_INJADDR_H_SHIFT (2U)

#define	CAN_ERRIAR_INJADDR_H(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)

ERRIDPR - Error Injection Data Pattern register
#define	CAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU)

#define	CAN_ERRIDPR_DFLIP_SHIFT (0U)

#define	CAN_ERRIDPR_DFLIP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)

ERRIPPR - Error Injection Parity Pattern register
#define	CAN_ERRIPPR_PFLIP0_MASK (0x1FU)

#define	CAN_ERRIPPR_PFLIP0_SHIFT (0U)

#define	CAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)

#define	CAN_ERRIPPR_PFLIP1_MASK (0x1F00U)

#define	CAN_ERRIPPR_PFLIP1_SHIFT (8U)

#define	CAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)

#define	CAN_ERRIPPR_PFLIP2_MASK (0x1F0000U)

#define	CAN_ERRIPPR_PFLIP2_SHIFT (16U)

#define	CAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)

#define	CAN_ERRIPPR_PFLIP3_MASK (0x1F000000U)

#define	CAN_ERRIPPR_PFLIP3_SHIFT (24U)

#define	CAN_ERRIPPR_PFLIP3(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)

RERRAR - Error Report Address register
#define	CAN_RERRAR_ERRADDR_MASK (0x3FFFU)

#define	CAN_RERRAR_ERRADDR_SHIFT (0U)

#define	CAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)

#define	CAN_RERRAR_SAID_MASK (0x70000U)

#define	CAN_RERRAR_SAID_SHIFT (16U)

#define	CAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)

#define	CAN_RERRAR_NCE_MASK (0x1000000U)

#define	CAN_RERRAR_NCE_SHIFT (24U)

#define	CAN_RERRAR_NCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)

RERRDR - Error Report Data register
#define	CAN_RERRDR_RDATA_MASK (0xFFFFFFFFU)

#define	CAN_RERRDR_RDATA_SHIFT (0U)

#define	CAN_RERRDR_RDATA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)

RERRSYNR - Error Report Syndrome register
#define	CAN_RERRSYNR_SYND0_MASK (0x1FU)

#define	CAN_RERRSYNR_SYND0_SHIFT (0U)

#define	CAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)

#define	CAN_RERRSYNR_BE0_MASK (0x80U)

#define	CAN_RERRSYNR_BE0_SHIFT (7U)

#define	CAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)

#define	CAN_RERRSYNR_SYND1_MASK (0x1F00U)

#define	CAN_RERRSYNR_SYND1_SHIFT (8U)

#define	CAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)

#define	CAN_RERRSYNR_BE1_MASK (0x8000U)

#define	CAN_RERRSYNR_BE1_SHIFT (15U)

#define	CAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)

#define	CAN_RERRSYNR_SYND2_MASK (0x1F0000U)

#define	CAN_RERRSYNR_SYND2_SHIFT (16U)

#define	CAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)

#define	CAN_RERRSYNR_BE2_MASK (0x800000U)

#define	CAN_RERRSYNR_BE2_SHIFT (23U)

#define	CAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)

#define	CAN_RERRSYNR_SYND3_MASK (0x1F000000U)

#define	CAN_RERRSYNR_SYND3_SHIFT (24U)

#define	CAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)

#define	CAN_RERRSYNR_BE3_MASK (0x80000000U)

#define	CAN_RERRSYNR_BE3_SHIFT (31U)

#define	CAN_RERRSYNR_BE3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)

ERRSR - Error Status register
#define	CAN_ERRSR_CEIOF_MASK (0x1U)

#define	CAN_ERRSR_CEIOF_SHIFT (0U)

#define	CAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)

#define	CAN_ERRSR_FANCEIOF_MASK (0x4U)

#define	CAN_ERRSR_FANCEIOF_SHIFT (2U)

#define	CAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)

#define	CAN_ERRSR_HANCEIOF_MASK (0x8U)

#define	CAN_ERRSR_HANCEIOF_SHIFT (3U)

#define	CAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)

#define	CAN_ERRSR_CEIF_MASK (0x10000U)

#define	CAN_ERRSR_CEIF_SHIFT (16U)

#define	CAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)

#define	CAN_ERRSR_FANCEIF_MASK (0x40000U)

#define	CAN_ERRSR_FANCEIF_SHIFT (18U)

#define	CAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)

#define	CAN_ERRSR_HANCEIF_MASK (0x80000U)

#define	CAN_ERRSR_HANCEIF_SHIFT (19U)

#define	CAN_ERRSR_HANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)

FDCTRL - CAN FD Control register
#define	CAN_FDCTRL_TDCVAL_MASK (0x3FU)

#define	CAN_FDCTRL_TDCVAL_SHIFT (0U)

#define	CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)

#define	CAN_FDCTRL_TDCOFF_MASK (0x1F00U)

#define	CAN_FDCTRL_TDCOFF_SHIFT (8U)

#define	CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)

#define	CAN_FDCTRL_TDCFAIL_MASK (0x4000U)

#define	CAN_FDCTRL_TDCFAIL_SHIFT (14U)

#define	CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)

#define	CAN_FDCTRL_TDCEN_MASK (0x8000U)

#define	CAN_FDCTRL_TDCEN_SHIFT (15U)

#define	CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)

#define	CAN_FDCTRL_MBDSR0_MASK (0x30000U)

#define	CAN_FDCTRL_MBDSR0_SHIFT (16U)

#define	CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)

#define	CAN_FDCTRL_MBDSR1_MASK (0x180000U)

#define	CAN_FDCTRL_MBDSR1_SHIFT (19U)

#define	CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)

#define	CAN_FDCTRL_FDRATE_MASK (0x80000000U)

#define	CAN_FDCTRL_FDRATE_SHIFT (31U)

#define	CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)

FDCBT - CAN FD Bit Timing register
#define	CAN_FDCBT_FPSEG2_MASK (0x7U)

#define	CAN_FDCBT_FPSEG2_SHIFT (0U)

#define	CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)

#define	CAN_FDCBT_FPSEG1_MASK (0xE0U)

#define	CAN_FDCBT_FPSEG1_SHIFT (5U)

#define	CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)

#define	CAN_FDCBT_FPROPSEG_MASK (0x7C00U)

#define	CAN_FDCBT_FPROPSEG_SHIFT (10U)

#define	CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)

#define	CAN_FDCBT_FRJW_MASK (0x70000U)

#define	CAN_FDCBT_FRJW_SHIFT (16U)

#define	CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)

#define	CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)

#define	CAN_FDCBT_FPRESDIV_SHIFT (20U)

#define	CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)

FDCRC - CAN FD CRC register
#define	CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)

#define	CAN_FDCRC_FD_TXCRC_SHIFT (0U)

#define	CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)

#define	CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)

#define	CAN_FDCRC_FD_MBCRC_SHIFT (24U)

#define	CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)

Detailed Description

Macro Definition Documentation

◆ CAN_CBT_BTF [1/2]

#define CAN_CBT_BTF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)

BTF - Bit Timing Format Enable 0b0..Extended bit time definitions disabled. 0b1..Extended bit time definitions enabled.

◆ CAN_CBT_BTF [2/2]

#define CAN_CBT_BTF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)

BTF - Bit Timing Format Enable 0b0..Extended bit time definitions disabled. 0b1..Extended bit time definitions enabled.

◆ CAN_CBT_EPRESDIV [1/2]

#define CAN_CBT_EPRESDIV ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)

EPRESDIV - Extended Prescaler Division Factor

◆ CAN_CBT_EPRESDIV [2/2]

#define CAN_CBT_EPRESDIV ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)

EPRESDIV - Extended Prescaler Division Factor

◆ CAN_CBT_EPROPSEG [1/2]

#define CAN_CBT_EPROPSEG ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)

EPROPSEG - Extended Propagation Segment

◆ CAN_CBT_EPROPSEG [2/2]

#define CAN_CBT_EPROPSEG ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)

EPROPSEG - Extended Propagation Segment

◆ CAN_CBT_EPSEG1 [1/2]

#define CAN_CBT_EPSEG1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)

EPSEG1 - Extended Phase Segment 1

◆ CAN_CBT_EPSEG1 [2/2]

#define CAN_CBT_EPSEG1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)

EPSEG1 - Extended Phase Segment 1

◆ CAN_CBT_EPSEG2 [1/2]

#define CAN_CBT_EPSEG2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)

EPSEG2 - Extended Phase Segment 2

◆ CAN_CBT_EPSEG2 [2/2]

#define CAN_CBT_EPSEG2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)

EPSEG2 - Extended Phase Segment 2

◆ CAN_CBT_ERJW [1/2]

#define CAN_CBT_ERJW ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)

ERJW - Extended Resync Jump Width

◆ CAN_CBT_ERJW [2/2]

#define CAN_CBT_ERJW ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)

ERJW - Extended Resync Jump Width

◆ CAN_CRCR_MBCRC [1/2]

#define CAN_CRCR_MBCRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)

MBCRC - CRC Mailbox

◆ CAN_CRCR_MBCRC [2/2]

#define CAN_CRCR_MBCRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)

MBCRC - CRC Mailbox

◆ CAN_CRCR_TXCRC [1/2]

#define CAN_CRCR_TXCRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)

TXCRC - Transmitted CRC value

◆ CAN_CRCR_TXCRC [2/2]

#define CAN_CRCR_TXCRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)

TXCRC - Transmitted CRC value

◆ CAN_CS_BRS [1/4]

#define CAN_CS_BRS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)

BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.

◆ CAN_CS_BRS [2/4]

#define CAN_CS_BRS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)

BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.

◆ CAN_CS_BRS [3/4]

#define CAN_CS_BRS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)

BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.

◆ CAN_CS_BRS [4/4]

#define CAN_CS_BRS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)

BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.

◆ CAN_CS_CODE [1/5]

#define CAN_CS_CODE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

CODE - Reserved

◆ CAN_CS_CODE [2/5]

#define CAN_CS_CODE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.

◆ CAN_CS_CODE [3/5]

#define CAN_CS_CODE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.

◆ CAN_CS_CODE [4/5]

#define CAN_CS_CODE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.

◆ CAN_CS_CODE [5/5]

#define CAN_CS_CODE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process.

◆ CAN_CS_DLC [1/5]

#define CAN_CS_DLC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

DLC - Length of the data to be stored/transmitted.

◆ CAN_CS_DLC [2/5]

#define CAN_CS_DLC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

DLC - Length of the data to be stored/transmitted.

◆ CAN_CS_DLC [3/5]

#define CAN_CS_DLC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

DLC - Length of the data to be stored/transmitted.

◆ CAN_CS_DLC [4/5]

#define CAN_CS_DLC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

DLC - Length of the data to be stored/transmitted.

◆ CAN_CS_DLC [5/5]

#define CAN_CS_DLC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

DLC - Length of the data to be stored/transmitted.

◆ CAN_CS_EDL [1/4]

#define CAN_CS_EDL ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)

EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.

◆ CAN_CS_EDL [2/4]

#define CAN_CS_EDL ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)

EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.

◆ CAN_CS_EDL [3/4]

#define CAN_CS_EDL ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)

EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.

◆ CAN_CS_EDL [4/4]

#define CAN_CS_EDL ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)

EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.

◆ CAN_CS_ESI [1/4]

#define CAN_CS_ESI ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)

ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.

◆ CAN_CS_ESI [2/4]

#define CAN_CS_ESI ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)

ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.

◆ CAN_CS_ESI [3/4]

#define CAN_CS_ESI ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)

ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.

◆ CAN_CS_ESI [4/4]

#define CAN_CS_ESI ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)

ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.

◆ CAN_CS_IDE [1/5]

#define CAN_CS_IDE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

IDE - ID Extended. One/zero for extended/standard format frame.

◆ CAN_CS_IDE [2/5]

#define CAN_CS_IDE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

IDE - ID Extended. One/zero for extended/standard format frame.

◆ CAN_CS_IDE [3/5]

#define CAN_CS_IDE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

IDE - ID Extended. One/zero for extended/standard format frame.

◆ CAN_CS_IDE [4/5]

#define CAN_CS_IDE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

IDE - ID Extended. One/zero for extended/standard format frame.

◆ CAN_CS_IDE [5/5]

#define CAN_CS_IDE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

IDE - ID Extended. One/zero for extended/standard format frame.

◆ CAN_CS_RTR [1/5]

#define CAN_CS_RTR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

RTR - Remote Transmission Request. One/zero for remote/data frame.

◆ CAN_CS_RTR [2/5]

#define CAN_CS_RTR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

RTR - Remote Transmission Request. One/zero for remote/data frame.

◆ CAN_CS_RTR [3/5]

#define CAN_CS_RTR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

RTR - Remote Transmission Request. One/zero for remote/data frame.

◆ CAN_CS_RTR [4/5]

#define CAN_CS_RTR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

RTR - Remote Transmission Request. One/zero for remote/data frame.

◆ CAN_CS_RTR [5/5]

#define CAN_CS_RTR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

RTR - Remote Transmission Request. One/zero for remote/data frame.

◆ CAN_CS_SRR [1/5]

#define CAN_CS_SRR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

SRR - Substitute Remote Request. Contains a fixed recessive bit.

◆ CAN_CS_SRR [2/5]

#define CAN_CS_SRR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

SRR - Substitute Remote Request. Contains a fixed recessive bit.

◆ CAN_CS_SRR [3/5]

#define CAN_CS_SRR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

SRR - Substitute Remote Request. Contains a fixed recessive bit.

◆ CAN_CS_SRR [4/5]

#define CAN_CS_SRR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

SRR - Substitute Remote Request. Contains a fixed recessive bit.

◆ CAN_CS_SRR [5/5]

#define CAN_CS_SRR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

SRR - Substitute Remote Request. Contains a fixed recessive bit.

◆ CAN_CS_TIME_STAMP [1/5]

#define CAN_CS_TIME_STAMP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

◆ CAN_CS_TIME_STAMP [2/5]

#define CAN_CS_TIME_STAMP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

◆ CAN_CS_TIME_STAMP [3/5]

#define CAN_CS_TIME_STAMP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

◆ CAN_CS_TIME_STAMP [4/5]

#define CAN_CS_TIME_STAMP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

◆ CAN_CS_TIME_STAMP [5/5]

#define CAN_CS_TIME_STAMP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

◆ CAN_CTRL1_BOFFMSK [1/3]

#define CAN_CTRL1_BOFFMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

BOFFMSK 0b1..Bus Off interrupt enabled 0b0..Bus Off interrupt disabled

◆ CAN_CTRL1_BOFFMSK [2/3]

#define CAN_CTRL1_BOFFMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

BOFFMSK - Bus Off Interrupt Mask 0b0..Bus Off interrupt disabled. 0b1..Bus Off interrupt enabled.

◆ CAN_CTRL1_BOFFMSK [3/3]

#define CAN_CTRL1_BOFFMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

BOFFMSK - Bus Off Interrupt Mask 0b0..Bus Off interrupt disabled. 0b1..Bus Off interrupt enabled.

◆ CAN_CTRL1_BOFFREC [1/3]

#define CAN_CTRL1_BOFFREC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

BOFFREC 0b1..Automatic recovering from Bus Off state disabled 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B

◆ CAN_CTRL1_BOFFREC [2/3]

#define CAN_CTRL1_BOFFREC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

BOFFREC - Bus Off Recovery 0b0..Automatic recovering from Bus Off state enabled. 0b1..Automatic recovering from Bus Off state disabled.

◆ CAN_CTRL1_BOFFREC [3/3]

#define CAN_CTRL1_BOFFREC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

BOFFREC - Bus Off Recovery 0b0..Automatic recovering from Bus Off state enabled. 0b1..Automatic recovering from Bus Off state disabled.

◆ CAN_CTRL1_CLKSRC [1/2]

#define CAN_CTRL1_CLKSRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)

CLKSRC - CAN Engine Clock Source 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. 0b1..The CAN engine clock source is the peripheral clock.

◆ CAN_CTRL1_CLKSRC [2/2]

#define CAN_CTRL1_CLKSRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)

CLKSRC - CAN Engine Clock Source 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. 0b1..The CAN engine clock source is the peripheral clock.

◆ CAN_CTRL1_ERRMSK [1/3]

#define CAN_CTRL1_ERRMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

ERRMSK 0b1..Error interrupt enabled 0b0..Error interrupt disabled

◆ CAN_CTRL1_ERRMSK [2/3]

#define CAN_CTRL1_ERRMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

ERRMSK - Error Interrupt Mask 0b0..Error interrupt disabled. 0b1..Error interrupt enabled.

◆ CAN_CTRL1_ERRMSK [3/3]

#define CAN_CTRL1_ERRMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

ERRMSK - Error Interrupt Mask 0b0..Error interrupt disabled. 0b1..Error interrupt enabled.

◆ CAN_CTRL1_LBUF [1/3]

#define CAN_CTRL1_LBUF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

LBUF 0b1..Lowest number buffer is transmitted first 0b0..Buffer with highest priority is transmitted first

◆ CAN_CTRL1_LBUF [2/3]

#define CAN_CTRL1_LBUF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

LBUF - Lowest Buffer Transmitted First 0b0..Buffer with highest priority is transmitted first. 0b1..Lowest number buffer is transmitted first.

◆ CAN_CTRL1_LBUF [3/3]

#define CAN_CTRL1_LBUF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

LBUF - Lowest Buffer Transmitted First 0b0..Buffer with highest priority is transmitted first. 0b1..Lowest number buffer is transmitted first.

◆ CAN_CTRL1_LOM [1/3]

#define CAN_CTRL1_LOM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

LOM 0b1..FLEXCAN module operates in Listen Only Mode 0b0..Listen Only Mode is deactivated

◆ CAN_CTRL1_LOM [2/3]

#define CAN_CTRL1_LOM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

LOM - Listen-Only Mode 0b0..Listen-Only mode is deactivated. 0b1..FlexCAN module operates in Listen-Only mode.

◆ CAN_CTRL1_LOM [3/3]

#define CAN_CTRL1_LOM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

LOM - Listen-Only Mode 0b0..Listen-Only mode is deactivated. 0b1..FlexCAN module operates in Listen-Only mode.

◆ CAN_CTRL1_LPB [1/3]

#define CAN_CTRL1_LPB ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

LPB 0b1..Loop Back enabled 0b0..Loop Back disabled

◆ CAN_CTRL1_LPB [2/3]

#define CAN_CTRL1_LPB ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

LPB - Loop Back Mode 0b0..Loop Back disabled. 0b1..Loop Back enabled.

◆ CAN_CTRL1_LPB [3/3]

#define CAN_CTRL1_LPB ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

LPB - Loop Back Mode 0b0..Loop Back disabled. 0b1..Loop Back enabled.

◆ CAN_CTRL1_PRESDIV [1/2]

#define CAN_CTRL1_PRESDIV ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)

PRESDIV - Prescaler Division Factor

◆ CAN_CTRL1_PRESDIV [2/2]

#define CAN_CTRL1_PRESDIV ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)

PRESDIV - Prescaler Division Factor

◆ CAN_CTRL1_PROPSEG [1/2]

#define CAN_CTRL1_PROPSEG ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)

PROPSEG - Propagation Segment

◆ CAN_CTRL1_PROPSEG [2/2]

#define CAN_CTRL1_PROPSEG ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)

PROPSEG - Propagation Segment

◆ CAN_CTRL1_PSEG1 [1/2]

#define CAN_CTRL1_PSEG1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)

PSEG1 - Phase Segment 1

◆ CAN_CTRL1_PSEG1 [2/2]

#define CAN_CTRL1_PSEG1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)

PSEG1 - Phase Segment 1

◆ CAN_CTRL1_PSEG2 [1/2]

#define CAN_CTRL1_PSEG2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)

PSEG2 - Phase Segment 2

◆ CAN_CTRL1_PSEG2 [2/2]

#define CAN_CTRL1_PSEG2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)

PSEG2 - Phase Segment 2

◆ CAN_CTRL1_RJW [1/2]

#define CAN_CTRL1_RJW ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)

RJW - Resync Jump Width

◆ CAN_CTRL1_RJW [2/2]

#define CAN_CTRL1_RJW ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)

RJW - Resync Jump Width

◆ CAN_CTRL1_RWRNMSK [1/3]

#define CAN_CTRL1_RWRNMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

RWRNMSK 0b1..Rx Warning Interrupt enabled 0b0..Rx Warning Interrupt disabled

◆ CAN_CTRL1_RWRNMSK [2/3]

#define CAN_CTRL1_RWRNMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

RWRNMSK - Rx Warning Interrupt Mask 0b0..Rx Warning interrupt disabled. 0b1..Rx Warning interrupt enabled.

◆ CAN_CTRL1_RWRNMSK [3/3]

#define CAN_CTRL1_RWRNMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

RWRNMSK - Rx Warning Interrupt Mask 0b0..Rx Warning interrupt disabled. 0b1..Rx Warning interrupt enabled.

◆ CAN_CTRL1_SMP [1/3]

#define CAN_CTRL1_SMP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

SMP 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used 0b0..Just one sample is used to determine the bit value

◆ CAN_CTRL1_SMP [2/3]

#define CAN_CTRL1_SMP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

SMP - CAN Bit Sampling 0b0..Just one sample is used to determine the bit value. 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples; a majority rule is used.

◆ CAN_CTRL1_SMP [3/3]

#define CAN_CTRL1_SMP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

SMP - CAN Bit Sampling 0b0..Just one sample is used to determine the bit value. 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples; a majority rule is used.

◆ CAN_CTRL1_TSYN [1/3]

#define CAN_CTRL1_TSYN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

TSYN 0b1..Timer Sync feature enabled 0b0..Timer Sync feature disabled

◆ CAN_CTRL1_TSYN [2/3]

#define CAN_CTRL1_TSYN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

TSYN - Timer Sync 0b0..Timer sync feature disabled 0b1..Timer sync feature enabled

◆ CAN_CTRL1_TSYN [3/3]

#define CAN_CTRL1_TSYN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

TSYN - Timer Sync 0b0..Timer sync feature disabled 0b1..Timer sync feature enabled

◆ CAN_CTRL1_TWRNMSK [1/3]

#define CAN_CTRL1_TWRNMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

TWRNMSK 0b1..Tx Warning Interrupt enabled 0b0..Tx Warning Interrupt disabled

◆ CAN_CTRL1_TWRNMSK [2/3]

#define CAN_CTRL1_TWRNMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

TWRNMSK - Tx Warning Interrupt Mask 0b0..Tx Warning interrupt disabled. 0b1..Tx Warning interrupt enabled.

◆ CAN_CTRL1_TWRNMSK [3/3]

#define CAN_CTRL1_TWRNMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

TWRNMSK - Tx Warning Interrupt Mask 0b0..Tx Warning interrupt disabled. 0b1..Tx Warning interrupt enabled.

◆ CAN_CTRL2_BOFFDONEMSK [1/2]

#define CAN_CTRL2_BOFFDONEMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)

BOFFDONEMSK - Bus Off Done Interrupt Mask 0b0..Bus off done interrupt disabled. 0b1..Bus off done interrupt enabled.

◆ CAN_CTRL2_BOFFDONEMSK [2/2]

#define CAN_CTRL2_BOFFDONEMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)

BOFFDONEMSK - Bus Off Done Interrupt Mask 0b0..Bus off done interrupt disabled. 0b1..Bus off done interrupt enabled.

◆ CAN_CTRL2_EACEN [1/3]

#define CAN_CTRL2_EACEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

EACEN 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.

◆ CAN_CTRL2_EACEN [2/3]

#define CAN_CTRL2_EACEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.

◆ CAN_CTRL2_EACEN [3/3]

#define CAN_CTRL2_EACEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.

◆ CAN_CTRL2_ECRWRE [1/2]

#define CAN_CTRL2_ECRWRE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)

ECRWRE - Error-correction Configuration Register Write Enable 0b0..Disable update. 0b1..Enable update.

◆ CAN_CTRL2_ECRWRE [2/2]

#define CAN_CTRL2_ECRWRE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)

ECRWRE - Error-correction Configuration Register Write Enable 0b0..Disable update. 0b1..Enable update.

◆ CAN_CTRL2_EDFLTDIS [1/2]

#define CAN_CTRL2_EDFLTDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)

EDFLTDIS - Edge Filter Disable 0b0..Edge filter is enabled 0b1..Edge filter is disabled

◆ CAN_CTRL2_EDFLTDIS [2/2]

#define CAN_CTRL2_EDFLTDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)

EDFLTDIS - Edge Filter Disable 0b0..Edge filter is enabled 0b1..Edge filter is disabled

◆ CAN_CTRL2_ERRMSK_FAST [1/2]

#define CAN_CTRL2_ERRMSK_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)

ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames 0b0..ERRINT_FAST error interrupt disabled. 0b1..ERRINT_FAST error interrupt enabled.

◆ CAN_CTRL2_ERRMSK_FAST [2/2]

#define CAN_CTRL2_ERRMSK_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)

ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames 0b0..ERRINT_FAST error interrupt disabled. 0b1..ERRINT_FAST error interrupt enabled.

◆ CAN_CTRL2_ISOCANFDEN [1/2]

#define CAN_CTRL2_ISOCANFDEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)

ISOCANFDEN - ISO CAN FD Enable 0b0..FlexCAN operates using the non-ISO CAN FD protocol. 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).

◆ CAN_CTRL2_ISOCANFDEN [2/2]

#define CAN_CTRL2_ISOCANFDEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)

ISOCANFDEN - ISO CAN FD Enable 0b0..FlexCAN operates using the non-ISO CAN FD protocol. 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).

◆ CAN_CTRL2_MRP [1/3]

#define CAN_CTRL2_MRP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

MRP 0b1..Matching starts from Mailboxes and continues on Rx FIFO 0b0..Matching starts from Rx FIFO and continues on Mailboxes

◆ CAN_CTRL2_MRP [2/3]

#define CAN_CTRL2_MRP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

MRP - Mailboxes Reception Priority 0b0..Matching starts from Rx FIFO and continues on mailboxes. 0b1..Matching starts from mailboxes and continues on Rx FIFO.

◆ CAN_CTRL2_MRP [3/3]

#define CAN_CTRL2_MRP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

MRP - Mailboxes Reception Priority 0b0..Matching starts from Rx FIFO and continues on mailboxes. 0b1..Matching starts from mailboxes and continues on Rx FIFO.

◆ CAN_CTRL2_PREXCEN [1/2]

#define CAN_CTRL2_PREXCEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)

PREXCEN - Protocol Exception Enable 0b0..Protocol exception is disabled. 0b1..Protocol exception is enabled.

◆ CAN_CTRL2_PREXCEN [2/2]

#define CAN_CTRL2_PREXCEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)

PREXCEN - Protocol Exception Enable 0b0..Protocol exception is disabled. 0b1..Protocol exception is enabled.

◆ CAN_CTRL2_RFFN [1/2]

#define CAN_CTRL2_RFFN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)

RFFN - Number Of Rx FIFO Filters

◆ CAN_CTRL2_RFFN [2/2]

#define CAN_CTRL2_RFFN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)

RFFN - Number Of Rx FIFO Filters

◆ CAN_CTRL2_RRS [1/3]

#define CAN_CTRL2_RRS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

RRS 0b1..Remote Request Frame is stored 0b0..Remote Response Frame is generated

◆ CAN_CTRL2_RRS [2/3]

#define CAN_CTRL2_RRS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

RRS - Remote Request Storing 0b0..Remote response frame is generated. 0b1..Remote request frame is stored.

◆ CAN_CTRL2_RRS [3/3]

#define CAN_CTRL2_RRS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

RRS - Remote Request Storing 0b0..Remote response frame is generated. 0b1..Remote request frame is stored.

◆ CAN_CTRL2_TASD [1/2]

#define CAN_CTRL2_TASD ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)

TASD - Tx Arbitration Start Delay

◆ CAN_CTRL2_TASD [2/2]

#define CAN_CTRL2_TASD ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)

TASD - Tx Arbitration Start Delay

◆ CAN_CTRL2_TIMER_SRC [1/2]

#define CAN_CTRL2_TIMER_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)

TIMER_SRC - Timer Source 0b0..The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. 0b1..The free running timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device-specific section for details about the external time tick.

◆ CAN_CTRL2_TIMER_SRC [2/2]

#define CAN_CTRL2_TIMER_SRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)

TIMER_SRC - Timer Source 0b0..The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. 0b1..The free running timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device-specific section for details about the external time tick.

◆ CAN_CTRL2_WRMFRZ [1/3]

#define CAN_CTRL2_WRMFRZ ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)

WRMFRZ 0b1..Enable unrestricted write access to FlexCAN memory 0b0..Keep the write access restricted in some regions of FlexCAN memory

◆ CAN_CTRL2_WRMFRZ [2/3]

#define CAN_CTRL2_WRMFRZ ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)

WRMFRZ - Write-Access To Memory In Freeze Mode 0b0..Maintain the write access restrictions. 0b1..Enable unrestricted write access to FlexCAN memory.

◆ CAN_CTRL2_WRMFRZ [3/3]

#define CAN_CTRL2_WRMFRZ ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)

WRMFRZ - Write-Access To Memory In Freeze Mode 0b0..Maintain the write access restrictions. 0b1..Enable unrestricted write access to FlexCAN memory.

◆ CAN_DBG1_CBN

#define CAN_DBG1_CBN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)

CBN - CAN Bit Number

◆ CAN_DBG1_CFSM

#define CAN_DBG1_CFSM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)

CFSM - CAN Finite State Machine

◆ CAN_DBG2_APP

#define CAN_DBG2_APP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)

APP - Arbitration Process in Progress 0b0..No matching process ongoing. 0b1..Matching process is in progress.

◆ CAN_DBG2_MPP

#define CAN_DBG2_MPP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)

MPP - Matching Process in Progress 0b0..No matching process ongoing. 0b1..Matching process is in progress.

◆ CAN_DBG2_RMP

#define CAN_DBG2_RMP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)

RMP - Rx Matching Pointer

◆ CAN_DBG2_TAP

#define CAN_DBG2_TAP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)

TAP - Tx Arbitration Pointer

◆ CAN_ECR_RXERRCNT [1/2]

#define CAN_ECR_RXERRCNT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)

RXERRCNT - Receive Error Counter

◆ CAN_ECR_RXERRCNT [2/2]

#define CAN_ECR_RXERRCNT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)

RXERRCNT - Receive Error Counter

◆ CAN_ECR_RXERRCNT_FAST [1/2]

#define CAN_ECR_RXERRCNT_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)

RXERRCNT_FAST - Receive Error Counter for fast bits

◆ CAN_ECR_RXERRCNT_FAST [2/2]

#define CAN_ECR_RXERRCNT_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)

RXERRCNT_FAST - Receive Error Counter for fast bits

◆ CAN_ECR_TXERRCNT [1/2]

#define CAN_ECR_TXERRCNT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)

TXERRCNT - Transmit Error Counter

◆ CAN_ECR_TXERRCNT [2/2]

#define CAN_ECR_TXERRCNT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)

TXERRCNT - Transmit Error Counter

◆ CAN_ECR_TXERRCNT_FAST [1/2]

#define CAN_ECR_TXERRCNT_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)

TXERRCNT_FAST - Transmit Error Counter for fast bits

◆ CAN_ECR_TXERRCNT_FAST [2/2]

#define CAN_ECR_TXERRCNT_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)

TXERRCNT_FAST - Transmit Error Counter for fast bits

◆ CAN_ERRIAR_INJADDR_H [1/2]

#define CAN_ERRIAR_INJADDR_H ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)

INJADDR_H - Error Injection Address High

◆ CAN_ERRIAR_INJADDR_H [2/2]

#define CAN_ERRIAR_INJADDR_H ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)

INJADDR_H - Error Injection Address High

◆ CAN_ERRIAR_INJADDR_L [1/2]

#define CAN_ERRIAR_INJADDR_L ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)

INJADDR_L - Error Injection Address Low

◆ CAN_ERRIAR_INJADDR_L [2/2]

#define CAN_ERRIAR_INJADDR_L ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)

INJADDR_L - Error Injection Address Low

◆ CAN_ERRIDPR_DFLIP [1/2]

#define CAN_ERRIDPR_DFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)

DFLIP - Data flip pattern

◆ CAN_ERRIDPR_DFLIP [2/2]

#define CAN_ERRIDPR_DFLIP ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)

DFLIP - Data flip pattern

◆ CAN_ERRIPPR_PFLIP0 [1/2]

#define CAN_ERRIPPR_PFLIP0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)

PFLIP0 - Parity Flip Pattern For Byte 0 (Least Significant)

◆ CAN_ERRIPPR_PFLIP0 [2/2]

#define CAN_ERRIPPR_PFLIP0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)

PFLIP0 - Parity Flip Pattern For Byte 0 (Least Significant)

◆ CAN_ERRIPPR_PFLIP1 [1/2]

#define CAN_ERRIPPR_PFLIP1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)

PFLIP1 - Parity Flip Pattern For Byte 1

◆ CAN_ERRIPPR_PFLIP1 [2/2]

#define CAN_ERRIPPR_PFLIP1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)

PFLIP1 - Parity Flip Pattern For Byte 1

◆ CAN_ERRIPPR_PFLIP2 [1/2]

#define CAN_ERRIPPR_PFLIP2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)

PFLIP2 - Parity Flip Pattern For Byte 2

◆ CAN_ERRIPPR_PFLIP2 [2/2]

#define CAN_ERRIPPR_PFLIP2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)

PFLIP2 - Parity Flip Pattern For Byte 2

◆ CAN_ERRIPPR_PFLIP3 [1/2]

#define CAN_ERRIPPR_PFLIP3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)

PFLIP3 - Parity Flip Pattern For Byte 3 (most significant)

◆ CAN_ERRIPPR_PFLIP3 [2/2]

#define CAN_ERRIPPR_PFLIP3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)

PFLIP3 - Parity Flip Pattern For Byte 3 (most significant)

◆ CAN_ERRSR_CEIF [1/2]

#define CAN_ERRSR_CEIF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)

CEIF - Correctable Error Interrupt Flag 0b0..No correctable errors were detected so far. 0b1..A correctable error was detected.

◆ CAN_ERRSR_CEIF [2/2]

#define CAN_ERRSR_CEIF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)

CEIF - Correctable Error Interrupt Flag 0b0..No correctable errors were detected so far. 0b1..A correctable error was detected.

◆ CAN_ERRSR_CEIOF [1/2]

#define CAN_ERRSR_CEIOF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)

CEIOF - Correctable Error Interrupt Overrun Flag 0b0..No overrun on correctable errors 0b1..Overrun on correctable errors

◆ CAN_ERRSR_CEIOF [2/2]

#define CAN_ERRSR_CEIOF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)

CEIOF - Correctable Error Interrupt Overrun Flag 0b0..No overrun on correctable errors 0b1..Overrun on correctable errors

◆ CAN_ERRSR_FANCEIF [1/2]

#define CAN_ERRSR_FANCEIF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)

FANCEIF - FlexCAN Access With Non-Correctable Error Interrupt Flag 0b0..No non-correctable errors were detected in FlexCAN accesses so far. 0b1..A non-correctable error was detected in a FlexCAN access.

◆ CAN_ERRSR_FANCEIF [2/2]

#define CAN_ERRSR_FANCEIF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)

FANCEIF - FlexCAN Access With Non-Correctable Error Interrupt Flag 0b0..No non-correctable errors were detected in FlexCAN accesses so far. 0b1..A non-correctable error was detected in a FlexCAN access.

◆ CAN_ERRSR_FANCEIOF [1/2]

#define CAN_ERRSR_FANCEIOF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)

FANCEIOF - FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag 0b0..No overrun on non-correctable errors in FlexCAN access 0b1..Overrun on non-correctable errors in FlexCAN access

◆ CAN_ERRSR_FANCEIOF [2/2]

#define CAN_ERRSR_FANCEIOF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)

FANCEIOF - FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag 0b0..No overrun on non-correctable errors in FlexCAN access 0b1..Overrun on non-correctable errors in FlexCAN access

◆ CAN_ERRSR_HANCEIF [1/2]

#define CAN_ERRSR_HANCEIF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)

HANCEIF - Host Access With Non-Correctable Error Interrupt Flag 0b0..No non-correctable errors were detected in host accesses so far. 0b1..A non-correctable error was detected in a host access.

◆ CAN_ERRSR_HANCEIF [2/2]

#define CAN_ERRSR_HANCEIF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)

HANCEIF - Host Access With Non-Correctable Error Interrupt Flag 0b0..No non-correctable errors were detected in host accesses so far. 0b1..A non-correctable error was detected in a host access.

◆ CAN_ERRSR_HANCEIOF [1/2]

#define CAN_ERRSR_HANCEIOF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)

HANCEIOF - Host Access With Non-Correctable Error Interrupt Overrun Flag 0b0..No overrun on non-correctable errors in host access 0b1..Overrun on non-correctable errors in host access

◆ CAN_ERRSR_HANCEIOF [2/2]

#define CAN_ERRSR_HANCEIOF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)

HANCEIOF - Host Access With Non-Correctable Error Interrupt Overrun Flag 0b0..No overrun on non-correctable errors in host access 0b1..Overrun on non-correctable errors in host access

◆ CAN_ESR1_ACKERR [1/3]

#define CAN_ESR1_ACKERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

ACKERR 0b1..An ACK error occurred since last read of this register 0b0..No such occurrence

◆ CAN_ESR1_ACKERR [2/3]

#define CAN_ESR1_ACKERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

ACKERR - Acknowledge Error 0b0..No such occurrence. 0b1..An ACK error occurred since last read of this register.

◆ CAN_ESR1_ACKERR [3/3]

#define CAN_ESR1_ACKERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

ACKERR - Acknowledge Error 0b0..No such occurrence. 0b1..An ACK error occurred since last read of this register.

◆ CAN_ESR1_BIT0ERR [1/3]

#define CAN_ESR1_BIT0ERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

BIT0ERR 0b1..At least one bit sent as dominant is received as recessive 0b0..No such occurrence

◆ CAN_ESR1_BIT0ERR [2/3]

#define CAN_ESR1_BIT0ERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

BIT0ERR - Bit0 Error 0b0..No such occurrence. 0b1..At least one bit sent as dominant is received as recessive.

◆ CAN_ESR1_BIT0ERR [3/3]

#define CAN_ESR1_BIT0ERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

BIT0ERR - Bit0 Error 0b0..No such occurrence. 0b1..At least one bit sent as dominant is received as recessive.

◆ CAN_ESR1_BIT0ERR_FAST [1/2]

#define CAN_ESR1_BIT0ERR_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)

BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set 0b0..No such occurrence. 0b1..At least one bit sent as dominant is received as recessive.

◆ CAN_ESR1_BIT0ERR_FAST [2/2]

#define CAN_ESR1_BIT0ERR_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)

BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set 0b0..No such occurrence. 0b1..At least one bit sent as dominant is received as recessive.

◆ CAN_ESR1_BIT1ERR [1/3]

#define CAN_ESR1_BIT1ERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

BIT1ERR 0b1..At least one bit sent as recessive is received as dominant 0b0..No such occurrence

◆ CAN_ESR1_BIT1ERR [2/3]

#define CAN_ESR1_BIT1ERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

BIT1ERR - Bit1 Error 0b0..No such occurrence. 0b1..At least one bit sent as recessive is received as dominant.

◆ CAN_ESR1_BIT1ERR [3/3]

#define CAN_ESR1_BIT1ERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

BIT1ERR - Bit1 Error 0b0..No such occurrence. 0b1..At least one bit sent as recessive is received as dominant.

◆ CAN_ESR1_BIT1ERR_FAST [1/2]

#define CAN_ESR1_BIT1ERR_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)

BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set 0b0..No such occurrence. 0b1..At least one bit sent as recessive is received as dominant.

◆ CAN_ESR1_BIT1ERR_FAST [2/2]

#define CAN_ESR1_BIT1ERR_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)

BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set 0b0..No such occurrence. 0b1..At least one bit sent as recessive is received as dominant.

◆ CAN_ESR1_BOFFDONEINT [1/2]

#define CAN_ESR1_BOFFDONEINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)

BOFFDONEINT - Bus Off Done Interrupt 0b0..No such occurrence. 0b1..FlexCAN module has completed Bus Off process.

◆ CAN_ESR1_BOFFDONEINT [2/2]

#define CAN_ESR1_BOFFDONEINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)

BOFFDONEINT - Bus Off Done Interrupt 0b0..No such occurrence. 0b1..FlexCAN module has completed Bus Off process.

◆ CAN_ESR1_BOFFINT [1/3]

#define CAN_ESR1_BOFFINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

BOFFINT 0b1..FLEXCAN module entered 'Bus Off' state 0b0..No such occurrence

◆ CAN_ESR1_BOFFINT [2/3]

#define CAN_ESR1_BOFFINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

BOFFINT - Bus Off Interrupt 0b0..No such occurrence. 0b1..FlexCAN module entered Bus Off state.

◆ CAN_ESR1_BOFFINT [3/3]

#define CAN_ESR1_BOFFINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

BOFFINT - Bus Off Interrupt 0b0..No such occurrence. 0b1..FlexCAN module entered Bus Off state.

◆ CAN_ESR1_CRCERR [1/3]

#define CAN_ESR1_CRCERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

CRCERR 0b1..A CRC error occurred since last read of this register. 0b0..No such occurrence

◆ CAN_ESR1_CRCERR [2/3]

#define CAN_ESR1_CRCERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

CRCERR - Cyclic Redundancy Check Error 0b0..No such occurrence. 0b1..A CRC error occurred since last read of this register.

◆ CAN_ESR1_CRCERR [3/3]

#define CAN_ESR1_CRCERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

CRCERR - Cyclic Redundancy Check Error 0b0..No such occurrence. 0b1..A CRC error occurred since last read of this register.

◆ CAN_ESR1_CRCERR_FAST [1/2]

#define CAN_ESR1_CRCERR_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)

CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set 0b0..No such occurrence. 0b1..A CRC error occurred since last read of this register.

◆ CAN_ESR1_CRCERR_FAST [2/2]

#define CAN_ESR1_CRCERR_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)

CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set 0b0..No such occurrence. 0b1..A CRC error occurred since last read of this register.

◆ CAN_ESR1_ERRINT [1/3]

#define CAN_ESR1_ERRINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

ERRINT 0b1..Indicates setting of any Error Bit in the Error and Status Register 0b0..No such occurrence

◆ CAN_ESR1_ERRINT [2/3]

#define CAN_ESR1_ERRINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

ERRINT - Error Interrupt 0b0..No such occurrence. 0b1..Indicates setting of any error bit in the Error and Status register.

◆ CAN_ESR1_ERRINT [3/3]

#define CAN_ESR1_ERRINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

ERRINT - Error Interrupt 0b0..No such occurrence. 0b1..Indicates setting of any error bit in the Error and Status register.

◆ CAN_ESR1_ERRINT_FAST [1/2]

#define CAN_ESR1_ERRINT_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)

ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set 0b0..No such occurrence. 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.

◆ CAN_ESR1_ERRINT_FAST [2/2]

#define CAN_ESR1_ERRINT_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)

ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set 0b0..No such occurrence. 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.

◆ CAN_ESR1_ERROVR [1/2]

#define CAN_ESR1_ERROVR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)

ERROVR - Error Overrun 0b0..Overrun has not occurred. 0b1..Overrun has occurred.

◆ CAN_ESR1_ERROVR [2/2]

#define CAN_ESR1_ERROVR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)

ERROVR - Error Overrun 0b0..Overrun has not occurred. 0b1..Overrun has occurred.

◆ CAN_ESR1_FLTCONF [1/3]

#define CAN_ESR1_FLTCONF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

FLTCONF 0b00..Error Active 0b01..Error Passive 0b1x..Bus off

◆ CAN_ESR1_FLTCONF [2/3]

#define CAN_ESR1_FLTCONF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

FLTCONF - Fault Confinement State 0b00..Error Active 0b01..Error Passive 0b1x..Bus Off

◆ CAN_ESR1_FLTCONF [3/3]

#define CAN_ESR1_FLTCONF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

FLTCONF - Fault Confinement State 0b00..Error Active 0b01..Error Passive 0b1x..Bus Off

◆ CAN_ESR1_FRMERR [1/3]

#define CAN_ESR1_FRMERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

FRMERR 0b1..A Form Error occurred since last read of this register 0b0..No such occurrence

◆ CAN_ESR1_FRMERR [2/3]

#define CAN_ESR1_FRMERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

FRMERR - Form Error 0b0..No such occurrence. 0b1..A Form Error occurred since last read of this register.

◆ CAN_ESR1_FRMERR [3/3]

#define CAN_ESR1_FRMERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

FRMERR - Form Error 0b0..No such occurrence. 0b1..A Form Error occurred since last read of this register.

◆ CAN_ESR1_FRMERR_FAST [1/2]

#define CAN_ESR1_FRMERR_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)

FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set 0b0..No such occurrence. 0b1..A form error occurred since last read of this register.

◆ CAN_ESR1_FRMERR_FAST [2/2]

#define CAN_ESR1_FRMERR_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)

FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set 0b0..No such occurrence. 0b1..A form error occurred since last read of this register.

◆ CAN_ESR1_IDLE [1/3]

#define CAN_ESR1_IDLE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

IDLE 0b1..CAN bus is now IDLE 0b0..No such occurrence

◆ CAN_ESR1_IDLE [2/3]

#define CAN_ESR1_IDLE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

IDLE - IDLE 0b0..No such occurrence. 0b1..CAN bus is now IDLE.

◆ CAN_ESR1_IDLE [3/3]

#define CAN_ESR1_IDLE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

IDLE - IDLE 0b0..No such occurrence. 0b1..CAN bus is now IDLE.

◆ CAN_ESR1_RWRNINT [1/3]

#define CAN_ESR1_RWRNINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

RWRNINT 0b1..The Rx error counter transition from < 96 to >= 96 0b0..No such occurrence

◆ CAN_ESR1_RWRNINT [2/3]

#define CAN_ESR1_RWRNINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

RWRNINT - Rx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_RWRNINT [3/3]

#define CAN_ESR1_RWRNINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

RWRNINT - Rx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_RX [1/3]

#define CAN_ESR1_RX ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

RX 0b1..FLEXCAN is transmitting a message 0b0..FLEXCAN is receiving a message

◆ CAN_ESR1_RX [2/3]

#define CAN_ESR1_RX ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

RX - FlexCAN In Reception 0b0..FlexCAN is not receiving a message. 0b1..FlexCAN is receiving a message.

◆ CAN_ESR1_RX [3/3]

#define CAN_ESR1_RX ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

RX - FlexCAN In Reception 0b0..FlexCAN is not receiving a message. 0b1..FlexCAN is receiving a message.

◆ CAN_ESR1_RXWRN [1/3]

#define CAN_ESR1_RXWRN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

RXWRN 0b1..Rx_Err_Counter >= 96 0b0..No such occurrence

◆ CAN_ESR1_RXWRN [2/3]

#define CAN_ESR1_RXWRN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

RXWRN - Rx Error Warning 0b0..No such occurrence. 0b1..RXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_RXWRN [3/3]

#define CAN_ESR1_RXWRN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

RXWRN - Rx Error Warning 0b0..No such occurrence. 0b1..RXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_STFERR [1/3]

#define CAN_ESR1_STFERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

STFERR 0b1..A Stuffing Error occurred since last read of this register. 0b0..No such occurrence.

◆ CAN_ESR1_STFERR [2/3]

#define CAN_ESR1_STFERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

STFERR - Stuffing Error 0b0..No such occurrence. 0b1..A stuffing error occurred since last read of this register.

◆ CAN_ESR1_STFERR [3/3]

#define CAN_ESR1_STFERR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

STFERR - Stuffing Error 0b0..No such occurrence. 0b1..A stuffing error occurred since last read of this register.

◆ CAN_ESR1_STFERR_FAST [1/2]

#define CAN_ESR1_STFERR_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)

STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set 0b0..No such occurrence. 0b1..A stuffing error occurred since last read of this register.

◆ CAN_ESR1_STFERR_FAST [2/2]

#define CAN_ESR1_STFERR_FAST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)

STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set 0b0..No such occurrence. 0b1..A stuffing error occurred since last read of this register.

◆ CAN_ESR1_SYNCH [1/3]

#define CAN_ESR1_SYNCH ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

SYNCH 0b1..FlexCAN is synchronized to the CAN bus 0b0..FlexCAN is not synchronized to the CAN bus

◆ CAN_ESR1_SYNCH [2/3]

#define CAN_ESR1_SYNCH ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

SYNCH - CAN Synchronization Status 0b0..FlexCAN is not synchronized to the CAN bus. 0b1..FlexCAN is synchronized to the CAN bus.

◆ CAN_ESR1_SYNCH [3/3]

#define CAN_ESR1_SYNCH ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

SYNCH - CAN Synchronization Status 0b0..FlexCAN is not synchronized to the CAN bus. 0b1..FlexCAN is synchronized to the CAN bus.

◆ CAN_ESR1_TWRNINT [1/3]

#define CAN_ESR1_TWRNINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

TWRNINT 0b1..The Tx error counter transition from < 96 to >= 96 0b0..No such occurrence

◆ CAN_ESR1_TWRNINT [2/3]

#define CAN_ESR1_TWRNINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

TWRNINT - Tx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_TWRNINT [3/3]

#define CAN_ESR1_TWRNINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

TWRNINT - Tx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_TX [1/3]

#define CAN_ESR1_TX ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

TX 0b1..FLEXCAN is transmitting a message 0b0..FLEXCAN is receiving a message

◆ CAN_ESR1_TX [2/3]

#define CAN_ESR1_TX ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

TX - FlexCAN In Transmission 0b0..FlexCAN is not transmitting a message. 0b1..FlexCAN is transmitting a message.

◆ CAN_ESR1_TX [3/3]

#define CAN_ESR1_TX ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

TX - FlexCAN In Transmission 0b0..FlexCAN is not transmitting a message. 0b1..FlexCAN is transmitting a message.

◆ CAN_ESR1_TXWRN [1/3]

#define CAN_ESR1_TXWRN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

TXWRN 0b1..TX_Err_Counter >= 96 0b0..No such occurrence

◆ CAN_ESR1_TXWRN [2/3]

#define CAN_ESR1_TXWRN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

TXWRN - TX Error Warning 0b0..No such occurrence. 0b1..TXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_TXWRN [3/3]

#define CAN_ESR1_TXWRN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

TXWRN - TX Error Warning 0b0..No such occurrence. 0b1..TXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_WAKINT [1/3]

#define CAN_ESR1_WAKINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

WAKINT 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode 0b0..No such occurrence

◆ CAN_ESR1_WAKINT [2/3]

#define CAN_ESR1_WAKINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

WAKINT - Wake-Up Interrupt 0b0..No such occurrence. 0b1..Indicates a recessive to dominant transition was received on the CAN bus.

◆ CAN_ESR1_WAKINT [3/3]

#define CAN_ESR1_WAKINT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

WAKINT - Wake-Up Interrupt 0b0..No such occurrence. 0b1..Indicates a recessive to dominant transition was received on the CAN bus.

◆ CAN_ESR2_IMB [1/3]

#define CAN_ESR2_IMB ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

IMB 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.

◆ CAN_ESR2_IMB [2/3]

#define CAN_ESR2_IMB ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

IMB - Inactive Mailbox 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox. 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.

◆ CAN_ESR2_IMB [3/3]

#define CAN_ESR2_IMB ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

IMB - Inactive Mailbox 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox. 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.

◆ CAN_ESR2_LPTM [1/2]

#define CAN_ESR2_LPTM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)

LPTM - Lowest Priority Tx Mailbox

◆ CAN_ESR2_LPTM [2/2]

#define CAN_ESR2_LPTM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)

LPTM - Lowest Priority Tx Mailbox

◆ CAN_ESR2_VPS [1/3]

#define CAN_ESR2_VPS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

VPS 0b1..Contents of IMB and LPTM are valid 0b0..Contents of IMB and LPTM are invalid

◆ CAN_ESR2_VPS [2/3]

#define CAN_ESR2_VPS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

VPS - Valid Priority Status 0b0..Contents of IMB and LPTM are invalid. 0b1..Contents of IMB and LPTM are valid.

◆ CAN_ESR2_VPS [3/3]

#define CAN_ESR2_VPS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

VPS - Valid Priority Status 0b0..Contents of IMB and LPTM are invalid. 0b1..Contents of IMB and LPTM are valid.

◆ CAN_FDCBT_FPRESDIV [1/2]

#define CAN_FDCBT_FPRESDIV ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)

FPRESDIV - Fast Prescaler Division Factor

◆ CAN_FDCBT_FPRESDIV [2/2]

#define CAN_FDCBT_FPRESDIV ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)

FPRESDIV - Fast Prescaler Division Factor

◆ CAN_FDCBT_FPROPSEG [1/2]

#define CAN_FDCBT_FPROPSEG ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)

FPROPSEG - Fast Propagation Segment

◆ CAN_FDCBT_FPROPSEG [2/2]

#define CAN_FDCBT_FPROPSEG ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)

FPROPSEG - Fast Propagation Segment

◆ CAN_FDCBT_FPSEG1 [1/2]

#define CAN_FDCBT_FPSEG1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)

FPSEG1 - Fast Phase Segment 1

◆ CAN_FDCBT_FPSEG1 [2/2]

#define CAN_FDCBT_FPSEG1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)

FPSEG1 - Fast Phase Segment 1

◆ CAN_FDCBT_FPSEG2 [1/2]

#define CAN_FDCBT_FPSEG2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)

FPSEG2 - Fast Phase Segment 2

◆ CAN_FDCBT_FPSEG2 [2/2]

#define CAN_FDCBT_FPSEG2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)

FPSEG2 - Fast Phase Segment 2

◆ CAN_FDCBT_FRJW [1/2]

#define CAN_FDCBT_FRJW ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)

FRJW - Fast Resync Jump Width

◆ CAN_FDCBT_FRJW [2/2]

#define CAN_FDCBT_FRJW ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)

FRJW - Fast Resync Jump Width

◆ CAN_FDCRC_FD_MBCRC [1/2]

#define CAN_FDCRC_FD_MBCRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)

FD_MBCRC - CRC Mailbox Number for FD_TXCRC

◆ CAN_FDCRC_FD_MBCRC [2/2]

#define CAN_FDCRC_FD_MBCRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)

FD_MBCRC - CRC Mailbox Number for FD_TXCRC

◆ CAN_FDCRC_FD_TXCRC [1/2]

#define CAN_FDCRC_FD_TXCRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)

FD_TXCRC - Extended Transmitted CRC value

◆ CAN_FDCRC_FD_TXCRC [2/2]

#define CAN_FDCRC_FD_TXCRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)

FD_TXCRC - Extended Transmitted CRC value

◆ CAN_FDCTRL_FDRATE [1/2]

#define CAN_FDCTRL_FDRATE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)

FDRATE - Bit Rate Switch Enable 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.

◆ CAN_FDCTRL_FDRATE [2/2]

#define CAN_FDCTRL_FDRATE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)

FDRATE - Bit Rate Switch Enable 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.

◆ CAN_FDCTRL_MBDSR0 [1/2]

#define CAN_FDCTRL_MBDSR0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)

MBDSR0 - Message Buffer Data Size for Region 0 0b00..Selects 8 bytes per message buffer. 0b01..Selects 16 bytes per message buffer. 0b10..Selects 32 bytes per message buffer. 0b11..Selects 64 bytes per message buffer.

◆ CAN_FDCTRL_MBDSR0 [2/2]

#define CAN_FDCTRL_MBDSR0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)

MBDSR0 - Message Buffer Data Size for Region 0 0b00..Selects 8 bytes per message buffer. 0b01..Selects 16 bytes per message buffer. 0b10..Selects 32 bytes per message buffer. 0b11..Selects 64 bytes per message buffer.

◆ CAN_FDCTRL_MBDSR1 [1/2]

#define CAN_FDCTRL_MBDSR1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)

MBDSR1 - Message Buffer Data Size for Region 1 0b00..Selects 8 bytes per message buffer. 0b01..Selects 16 bytes per message buffer. 0b10..Selects 32 bytes per message buffer. 0b11..Selects 64 bytes per message buffer.

◆ CAN_FDCTRL_MBDSR1 [2/2]

#define CAN_FDCTRL_MBDSR1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)

MBDSR1 - Message Buffer Data Size for Region 1 0b00..Selects 8 bytes per message buffer. 0b01..Selects 16 bytes per message buffer. 0b10..Selects 32 bytes per message buffer. 0b11..Selects 64 bytes per message buffer.

◆ CAN_FDCTRL_TDCEN [1/2]

#define CAN_FDCTRL_TDCEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)

TDCEN - Transceiver Delay Compensation Enable 0b0..TDC is disabled 0b1..TDC is enabled

◆ CAN_FDCTRL_TDCEN [2/2]

#define CAN_FDCTRL_TDCEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)

TDCEN - Transceiver Delay Compensation Enable 0b0..TDC is disabled 0b1..TDC is enabled

◆ CAN_FDCTRL_TDCFAIL [1/2]

#define CAN_FDCTRL_TDCFAIL ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)

TDCFAIL - Transceiver Delay Compensation Fail 0b0..Measured loop delay is in range. 0b1..Measured loop delay is out of range.

◆ CAN_FDCTRL_TDCFAIL [2/2]

#define CAN_FDCTRL_TDCFAIL ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)

TDCFAIL - Transceiver Delay Compensation Fail 0b0..Measured loop delay is in range. 0b1..Measured loop delay is out of range.

◆ CAN_FDCTRL_TDCOFF [1/2]

#define CAN_FDCTRL_TDCOFF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)

TDCOFF - Transceiver Delay Compensation Offset

◆ CAN_FDCTRL_TDCOFF [2/2]

#define CAN_FDCTRL_TDCOFF ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)

TDCOFF - Transceiver Delay Compensation Offset

◆ CAN_FDCTRL_TDCVAL [1/2]

#define CAN_FDCTRL_TDCVAL ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)

TDCVAL - Transceiver Delay Compensation Value

◆ CAN_FDCTRL_TDCVAL [2/2]

#define CAN_FDCTRL_TDCVAL ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)

TDCVAL - Transceiver Delay Compensation Value

◆ CAN_ID_EXT [1/5]

#define CAN_ID_EXT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

EXT - Contains extended (LOW word) identifier of message buffer.

◆ CAN_ID_EXT [2/5]

#define CAN_ID_EXT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

EXT - Contains extended (LOW word) identifier of message buffer.

◆ CAN_ID_EXT [3/5]

#define CAN_ID_EXT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

EXT - Contains extended (LOW word) identifier of message buffer.

◆ CAN_ID_EXT [4/5]

#define CAN_ID_EXT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

EXT - Contains extended (LOW word) identifier of message buffer.

◆ CAN_ID_EXT [5/5]

#define CAN_ID_EXT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

EXT - Contains extended (LOW word) identifier of message buffer.

◆ CAN_ID_PRIO [1/5]

#define CAN_ID_PRIO ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)

PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

◆ CAN_ID_PRIO [2/5]

#define CAN_ID_PRIO ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)

PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

◆ CAN_ID_PRIO [3/5]

#define CAN_ID_PRIO ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)

PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

◆ CAN_ID_PRIO [4/5]

#define CAN_ID_PRIO ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)

PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

◆ CAN_ID_PRIO [5/5]

#define CAN_ID_PRIO ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)

PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

◆ CAN_ID_STD [1/5]

#define CAN_ID_STD ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

STD - Contains standard/extended (HIGH word) identifier of message buffer.

◆ CAN_ID_STD [2/5]

#define CAN_ID_STD ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

STD - Contains standard/extended (HIGH word) identifier of message buffer.

◆ CAN_ID_STD [3/5]

#define CAN_ID_STD ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

STD - Contains standard/extended (HIGH word) identifier of message buffer.

◆ CAN_ID_STD [4/5]

#define CAN_ID_STD ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

STD - Contains standard/extended (HIGH word) identifier of message buffer.

◆ CAN_ID_STD [5/5]

#define CAN_ID_STD ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

STD - Contains standard/extended (HIGH word) identifier of message buffer.

◆ CAN_IFLAG1_BUF0I [1/2]

#define CAN_IFLAG1_BUF0I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)

BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

◆ CAN_IFLAG1_BUF0I [2/2]

#define CAN_IFLAG1_BUF0I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)

BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

◆ CAN_IFLAG1_BUF31TO8I [1/3]

#define CAN_IFLAG1_BUF31TO8I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

BUF31TO8I 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception 0b000000000000000000000000..No such occurrence

◆ CAN_IFLAG1_BUF31TO8I [2/3]

#define CAN_IFLAG1_BUF31TO8I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

BUF31TO8I - Buffer MBi Interrupt

◆ CAN_IFLAG1_BUF31TO8I [3/3]

#define CAN_IFLAG1_BUF31TO8I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

BUF31TO8I - Buffer MBi Interrupt

◆ CAN_IFLAG1_BUF4TO0I

#define CAN_IFLAG1_BUF4TO0I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)

BUF4TO0I 0b00001..Corresponding MB completed transmission/reception 0b00000..No such occurrence

◆ CAN_IFLAG1_BUF4TO1I [1/2]

#define CAN_IFLAG1_BUF4TO1I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)

BUF4TO1I - Buffer MBi Interrupt Or Reserved

◆ CAN_IFLAG1_BUF4TO1I [2/2]

#define CAN_IFLAG1_BUF4TO1I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)

BUF4TO1I - Buffer MBi Interrupt Or Reserved

◆ CAN_IFLAG1_BUF5I [1/3]

#define CAN_IFLAG1_BUF5I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

BUF5I 0b1..MB5 completed transmission/reception or frames available in the FIFO 0b0..No such occurrence

◆ CAN_IFLAG1_BUF5I [2/3]

#define CAN_IFLAG1_BUF5I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.

◆ CAN_IFLAG1_BUF5I [3/3]

#define CAN_IFLAG1_BUF5I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.

◆ CAN_IFLAG1_BUF6I [1/3]

#define CAN_IFLAG1_BUF6I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

BUF6I 0b1..MB6 completed transmission/reception or FIFO almost full 0b0..No such occurrence

◆ CAN_IFLAG1_BUF6I [2/3]

#define CAN_IFLAG1_BUF6I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF6I [3/3]

#define CAN_IFLAG1_BUF6I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF7I [1/3]

#define CAN_IFLAG1_BUF7I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

BUF7I 0b1..MB7 completed transmission/reception or FIFO overflow 0b0..No such occurrence

◆ CAN_IFLAG1_BUF7I [2/3]

#define CAN_IFLAG1_BUF7I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF7I [3/3]

#define CAN_IFLAG1_BUF7I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1

◆ CAN_IFLAG2_BUF63TO32I [1/2]

#define CAN_IFLAG2_BUF63TO32I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)

BUF63TO32I - Buffer MBi Interrupt

◆ CAN_IFLAG2_BUF63TO32I [2/2]

#define CAN_IFLAG2_BUF63TO32I ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)

BUF63TO32I - Buffer MBi Interrupt

◆ CAN_IFLAG2_BUFHI

#define CAN_IFLAG2_BUFHI ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)

BUFHI 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception 0b00000000000000000000000000000000..No such occurrence

◆ CAN_IMASK1_BUF31TO0M [1/2]

#define CAN_IMASK1_BUF31TO0M ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)

BUF31TO0M - Buffer MBi Mask

◆ CAN_IMASK1_BUF31TO0M [2/2]

#define CAN_IMASK1_BUF31TO0M ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)

BUF31TO0M - Buffer MBi Mask

◆ CAN_IMASK1_BUFLM

#define CAN_IMASK1_BUFLM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)

BUFLM 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled

◆ CAN_IMASK2_BUF63TO32M [1/2]

#define CAN_IMASK2_BUF63TO32M ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)

BUF63TO32M - Buffer MBi Mask

◆ CAN_IMASK2_BUF63TO32M [2/2]

#define CAN_IMASK2_BUF63TO32M ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)

BUF63TO32M - Buffer MBi Mask

◆ CAN_IMASK2_BUFHM

#define CAN_IMASK2_BUFHM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)

BUFHM 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled

◆ CAN_MCR_AEN [1/3]

#define CAN_MCR_AEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

AEN 0b1..Abort enabled 0b0..Abort disabled

◆ CAN_MCR_AEN [2/3]

#define CAN_MCR_AEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

AEN - Abort Enable 0b0..Abort disabled. 0b1..Abort enabled.

◆ CAN_MCR_AEN [3/3]

#define CAN_MCR_AEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

AEN - Abort Enable 0b0..Abort disabled. 0b1..Abort enabled.

◆ CAN_MCR_DMA [1/2]

#define CAN_MCR_DMA ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)

DMA - DMA Enable 0b0..DMA feature for RX FIFO disabled. 0b1..DMA feature for RX FIFO enabled.

◆ CAN_MCR_DMA [2/2]

#define CAN_MCR_DMA ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)

DMA - DMA Enable 0b0..DMA feature for RX FIFO disabled. 0b1..DMA feature for RX FIFO enabled.

◆ CAN_MCR_DOZE [1/2]

#define CAN_MCR_DOZE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)

DOZE - Doze Mode Enable 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested. 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.

◆ CAN_MCR_DOZE [2/2]

#define CAN_MCR_DOZE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)

DOZE - Doze Mode Enable 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested. 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.

◆ CAN_MCR_FDEN [1/2]

#define CAN_MCR_FDEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)

FDEN - CAN FD operation enable 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.

◆ CAN_MCR_FDEN [2/2]

#define CAN_MCR_FDEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)

FDEN - CAN FD operation enable 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.

◆ CAN_MCR_FRZ [1/3]

#define CAN_MCR_FRZ ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

FRZ 0b1..Enabled to enter Freeze Mode 0b0..Not enabled to enter Freeze Mode

◆ CAN_MCR_FRZ [2/3]

#define CAN_MCR_FRZ ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

FRZ - Freeze Enable 0b0..Not enabled to enter Freeze mode. 0b1..Enabled to enter Freeze mode.

◆ CAN_MCR_FRZ [3/3]

#define CAN_MCR_FRZ ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

FRZ - Freeze Enable 0b0..Not enabled to enter Freeze mode. 0b1..Enabled to enter Freeze mode.

◆ CAN_MCR_FRZACK [1/3]

#define CAN_MCR_FRZACK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

FRZACK 0b1..FLEXCAN in Freeze Mode, prescaler stopped 0b0..FLEXCAN not in Freeze Mode, prescaler running

◆ CAN_MCR_FRZACK [2/3]

#define CAN_MCR_FRZACK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

FRZACK - Freeze Mode Acknowledge 0b0..FlexCAN not in Freeze mode, prescaler running. 0b1..FlexCAN in Freeze mode, prescaler stopped.

◆ CAN_MCR_FRZACK [3/3]

#define CAN_MCR_FRZACK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

FRZACK - Freeze Mode Acknowledge 0b0..FlexCAN not in Freeze mode, prescaler running. 0b1..FlexCAN in Freeze mode, prescaler stopped.

◆ CAN_MCR_HALT [1/3]

#define CAN_MCR_HALT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

HALT 0b1..Enters Freeze Mode if the FRZ bit is asserted. 0b0..No Freeze Mode request.

◆ CAN_MCR_HALT [2/3]

#define CAN_MCR_HALT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

HALT - Halt FlexCAN 0b0..No Freeze mode request. 0b1..Enters Freeze mode if the FRZ bit is asserted.

◆ CAN_MCR_HALT [3/3]

#define CAN_MCR_HALT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

HALT - Halt FlexCAN 0b0..No Freeze mode request. 0b1..Enters Freeze mode if the FRZ bit is asserted.

◆ CAN_MCR_IDAM [1/3]

#define CAN_MCR_IDAM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

IDAM 0b00..Format A One full ID (standard or extended) per ID filter Table element. 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. 0b11..Format D All frames rejected.

◆ CAN_MCR_IDAM [2/3]

#define CAN_MCR_IDAM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

IDAM - ID Acceptance Mode 0b00..Format A: One full ID (standard and extended) per ID filter table element. 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. 0b11..Format D: All frames rejected.

◆ CAN_MCR_IDAM [3/3]

#define CAN_MCR_IDAM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

IDAM - ID Acceptance Mode 0b00..Format A: One full ID (standard and extended) per ID filter table element. 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. 0b11..Format D: All frames rejected.

◆ CAN_MCR_IRMQ [1/3]

#define CAN_MCR_IRMQ ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

IRMQ 0b1..Individual Rx masking and queue feature are enabled. 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY.

◆ CAN_MCR_IRMQ [2/3]

#define CAN_MCR_IRMQ ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

IRMQ - Individual Rx Masking And Queue Enable 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. 0b1..Individual Rx masking and queue feature are enabled.

◆ CAN_MCR_IRMQ [3/3]

#define CAN_MCR_IRMQ ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

IRMQ - Individual Rx Masking And Queue Enable 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. 0b1..Individual Rx masking and queue feature are enabled.

◆ CAN_MCR_LPMACK [1/3]

#define CAN_MCR_LPMACK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

LPMACK 0b1..FLEXCAN is either in Disable Mode, or Stop mode 0b0..FLEXCAN not in any of the low power modes

◆ CAN_MCR_LPMACK [2/3]

#define CAN_MCR_LPMACK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

LPMACK - Low-Power Mode Acknowledge 0b0..FlexCAN is not in a low-power mode. 0b1..FlexCAN is in a low-power mode.

◆ CAN_MCR_LPMACK [3/3]

#define CAN_MCR_LPMACK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

LPMACK - Low-Power Mode Acknowledge 0b0..FlexCAN is not in a low-power mode. 0b1..FlexCAN is in a low-power mode.

◆ CAN_MCR_LPRIOEN [1/3]

#define CAN_MCR_LPRIOEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

LPRIOEN 0b1..Local Priority enabled 0b0..Local Priority disabled

◆ CAN_MCR_LPRIOEN [2/3]

#define CAN_MCR_LPRIOEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

LPRIOEN - Local Priority Enable 0b0..Local Priority disabled. 0b1..Local Priority enabled.

◆ CAN_MCR_LPRIOEN [3/3]

#define CAN_MCR_LPRIOEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

LPRIOEN - Local Priority Enable 0b0..Local Priority disabled. 0b1..Local Priority enabled.

◆ CAN_MCR_MAXMB [1/2]

#define CAN_MCR_MAXMB ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)

MAXMB - Number Of The Last Message Buffer

◆ CAN_MCR_MAXMB [2/2]

#define CAN_MCR_MAXMB ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)

MAXMB - Number Of The Last Message Buffer

◆ CAN_MCR_MDIS [1/3]

#define CAN_MCR_MDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

MDIS 0b1..Disable the FLEXCAN module 0b0..Enable the FLEXCAN module

◆ CAN_MCR_MDIS [2/3]

#define CAN_MCR_MDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enable the FlexCAN module. 0b1..Disable the FlexCAN module.

◆ CAN_MCR_MDIS [3/3]

#define CAN_MCR_MDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enable the FlexCAN module. 0b1..Disable the FlexCAN module.

◆ CAN_MCR_NOTRDY [1/3]

#define CAN_MCR_NOTRDY ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

NOTRDY 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode

◆ CAN_MCR_NOTRDY [2/3]

#define CAN_MCR_NOTRDY ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

NOTRDY - FlexCAN Not Ready 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode. 0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.

◆ CAN_MCR_NOTRDY [3/3]

#define CAN_MCR_NOTRDY ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

NOTRDY - FlexCAN Not Ready 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode. 0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.

◆ CAN_MCR_RFEN [1/3]

#define CAN_MCR_RFEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

RFEN 0b1..FIFO enabled 0b0..FIFO not enabled

◆ CAN_MCR_RFEN [2/3]

#define CAN_MCR_RFEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

RFEN - Rx FIFO Enable 0b0..Rx FIFO not enabled. 0b1..Rx FIFO enabled.

◆ CAN_MCR_RFEN [3/3]

#define CAN_MCR_RFEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

RFEN - Rx FIFO Enable 0b0..Rx FIFO not enabled. 0b1..Rx FIFO enabled.

◆ CAN_MCR_SLFWAK [1/3]

#define CAN_MCR_SLFWAK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

SLFWAK 0b1..FLEXCAN Self Wake Up feature is enabled 0b0..FLEXCAN Self Wake Up feature is disabled

◆ CAN_MCR_SLFWAK [2/3]

#define CAN_MCR_SLFWAK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

SLFWAK - Self Wake Up 0b0..FlexCAN Self Wake Up feature is disabled. 0b1..FlexCAN Self Wake Up feature is enabled.

◆ CAN_MCR_SLFWAK [3/3]

#define CAN_MCR_SLFWAK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

SLFWAK - Self Wake Up 0b0..FlexCAN Self Wake Up feature is disabled. 0b1..FlexCAN Self Wake Up feature is enabled.

◆ CAN_MCR_SOFTRST [1/3]

#define CAN_MCR_SOFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

SOFTRST 0b1..Reset the registers 0b0..No reset request

◆ CAN_MCR_SOFTRST [2/3]

#define CAN_MCR_SOFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

SOFTRST - Soft Reset 0b0..No reset request. 0b1..Resets the registers affected by soft reset.

◆ CAN_MCR_SOFTRST [3/3]

#define CAN_MCR_SOFTRST ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

SOFTRST - Soft Reset 0b0..No reset request. 0b1..Resets the registers affected by soft reset.

◆ CAN_MCR_SRXDIS [1/3]

#define CAN_MCR_SRXDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

SRXDIS 0b1..Self reception disabled 0b0..Self reception enabled

◆ CAN_MCR_SRXDIS [2/3]

#define CAN_MCR_SRXDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

SRXDIS - Self Reception Disable 0b0..Self-reception enabled. 0b1..Self-reception disabled.

◆ CAN_MCR_SRXDIS [3/3]

#define CAN_MCR_SRXDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

SRXDIS - Self Reception Disable 0b0..Self-reception enabled. 0b1..Self-reception disabled.

◆ CAN_MCR_SUPV [1/3]

#define CAN_MCR_SUPV ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

SUPV 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses

◆ CAN_MCR_SUPV [2/3]

#define CAN_MCR_SUPV ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

SUPV - Supervisor Mode 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location.

◆ CAN_MCR_SUPV [3/3]

#define CAN_MCR_SUPV ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

SUPV - Supervisor Mode 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location.

◆ CAN_MCR_WAKMSK [1/3]

#define CAN_MCR_WAKMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

WAKMSK 0b1..Wake Up Interrupt is enabled 0b0..Wake Up Interrupt is disabled

◆ CAN_MCR_WAKMSK [2/3]

#define CAN_MCR_WAKMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

WAKMSK - Wake Up Interrupt Mask 0b0..Wake Up interrupt is disabled. 0b1..Wake Up interrupt is enabled.

◆ CAN_MCR_WAKMSK [3/3]

#define CAN_MCR_WAKMSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

WAKMSK - Wake Up Interrupt Mask 0b0..Wake Up interrupt is disabled. 0b1..Wake Up interrupt is enabled.

◆ CAN_MCR_WAKSRC [1/3]

#define CAN_MCR_WAKSRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

WAKSRC 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus.

◆ CAN_MCR_WAKSRC [2/3]

#define CAN_MCR_WAKSRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

WAKSRC - Wake Up Source 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.

◆ CAN_MCR_WAKSRC [3/3]

#define CAN_MCR_WAKSRC ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

WAKSRC - Wake Up Source 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.

◆ CAN_MCR_WRNEN [1/3]

#define CAN_MCR_WRNEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

WRNEN 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.

◆ CAN_MCR_WRNEN [2/3]

#define CAN_MCR_WRNEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

WRNEN - Warning Interrupt Enable 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.

◆ CAN_MCR_WRNEN [3/3]

#define CAN_MCR_WRNEN ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

WRNEN - Warning Interrupt Enable 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.

◆ CAN_MECR_CEI_MSK [1/2]

#define CAN_MECR_CEI_MSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)

CEI_MSK - Correctable Errors Interrupt Mask 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CAN_MECR_CEI_MSK [2/2]

#define CAN_MECR_CEI_MSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)

CEI_MSK - Correctable Errors Interrupt Mask 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CAN_MECR_ECCDIS [1/2]

#define CAN_MECR_ECCDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)

ECCDIS - Error Correction Disable 0b0..Enable memory error correction. 0b1..Disable memory error correction.

◆ CAN_MECR_ECCDIS [2/2]

#define CAN_MECR_ECCDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)

ECCDIS - Error Correction Disable 0b0..Enable memory error correction. 0b1..Disable memory error correction.

◆ CAN_MECR_ECRWRDIS [1/2]

#define CAN_MECR_ECRWRDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)

ECRWRDIS - Error Configuration Register Write Disable 0b0..Write is enabled. 0b1..Write is disabled.

◆ CAN_MECR_ECRWRDIS [2/2]

#define CAN_MECR_ECRWRDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)

ECRWRDIS - Error Configuration Register Write Disable 0b0..Write is enabled. 0b1..Write is disabled.

◆ CAN_MECR_EXTERRIE [1/2]

#define CAN_MECR_EXTERRIE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)

EXTERRIE - Extended Error Injection Enable 0b0..Error injection is applied only to the 32-bit word. 0b1..Error injection is applied to the 64-bit word.

◆ CAN_MECR_EXTERRIE [2/2]

#define CAN_MECR_EXTERRIE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)

EXTERRIE - Extended Error Injection Enable 0b0..Error injection is applied only to the 32-bit word. 0b1..Error injection is applied to the 64-bit word.

◆ CAN_MECR_FAERRIE [1/2]

#define CAN_MECR_FAERRIE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)

FAERRIE - FlexCAN Access Error Injection Enable 0b0..Injection is disabled. 0b1..Injection is enabled.

◆ CAN_MECR_FAERRIE [2/2]

#define CAN_MECR_FAERRIE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)

FAERRIE - FlexCAN Access Error Injection Enable 0b0..Injection is disabled. 0b1..Injection is enabled.

◆ CAN_MECR_FANCEI_MSK [1/2]

#define CAN_MECR_FANCEI_MSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)

FANCEI_MSK - FlexCAN Access With Non-Correctable Errors Interrupt Mask 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CAN_MECR_FANCEI_MSK [2/2]

#define CAN_MECR_FANCEI_MSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)

FANCEI_MSK - FlexCAN Access With Non-Correctable Errors Interrupt Mask 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CAN_MECR_HAERRIE [1/2]

#define CAN_MECR_HAERRIE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)

HAERRIE - Host Access Error Injection Enable 0b0..Injection is disabled. 0b1..Injection is enabled.

◆ CAN_MECR_HAERRIE [2/2]

#define CAN_MECR_HAERRIE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)

HAERRIE - Host Access Error Injection Enable 0b0..Injection is disabled. 0b1..Injection is enabled.

◆ CAN_MECR_HANCEI_MSK [1/2]

#define CAN_MECR_HANCEI_MSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)

HANCEI_MSK - Host Access With Non-Correctable Errors Interrupt Mask 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CAN_MECR_HANCEI_MSK [2/2]

#define CAN_MECR_HANCEI_MSK ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)

HANCEI_MSK - Host Access With Non-Correctable Errors Interrupt Mask 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

◆ CAN_MECR_NCEFAFRZ [1/2]

#define CAN_MECR_NCEFAFRZ ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)

NCEFAFRZ - Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode 0b0..Keep normal operation. 0b1..Put FlexCAN in Freeze mode (see section "Freeze mode").

◆ CAN_MECR_NCEFAFRZ [2/2]

#define CAN_MECR_NCEFAFRZ ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)

NCEFAFRZ - Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode 0b0..Keep normal operation. 0b1..Put FlexCAN in Freeze mode (see section "Freeze mode").

◆ CAN_MECR_RERRDIS [1/2]

#define CAN_MECR_RERRDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)

RERRDIS - Error Report Disable 0b0..Enable updates of the error report registers. 0b1..Disable updates of the error report registers.

◆ CAN_MECR_RERRDIS [2/2]

#define CAN_MECR_RERRDIS ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)

RERRDIS - Error Report Disable 0b0..Enable updates of the error report registers. 0b1..Disable updates of the error report registers.

◆ CAN_RERRAR_ERRADDR [1/2]

#define CAN_RERRAR_ERRADDR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)

ERRADDR - Address Where Error Detected

◆ CAN_RERRAR_ERRADDR [2/2]

#define CAN_RERRAR_ERRADDR ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)

ERRADDR - Address Where Error Detected

◆ CAN_RERRAR_NCE [1/2]

#define CAN_RERRAR_NCE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)

NCE - Non-Correctable Error 0b0..Reporting a correctable error 0b1..Reporting a non-correctable error

◆ CAN_RERRAR_NCE [2/2]

#define CAN_RERRAR_NCE ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)

NCE - Non-Correctable Error 0b0..Reporting a correctable error 0b1..Reporting a non-correctable error

◆ CAN_RERRAR_SAID [1/2]

#define CAN_RERRAR_SAID ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)

SAID - SAID

◆ CAN_RERRAR_SAID [2/2]

#define CAN_RERRAR_SAID ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)

SAID - SAID

◆ CAN_RERRDR_RDATA [1/2]

#define CAN_RERRDR_RDATA ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)

RDATA - Raw data word read from memory with error

◆ CAN_RERRDR_RDATA [2/2]

#define CAN_RERRDR_RDATA ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)

RDATA - Raw data word read from memory with error

◆ CAN_RERRSYNR_BE0 [1/2]

#define CAN_RERRSYNR_BE0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)

BE0 - Byte Enabled For Byte 0 (least significant) 0b0..The byte was not read. 0b1..The byte was read.

◆ CAN_RERRSYNR_BE0 [2/2]

#define CAN_RERRSYNR_BE0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)

BE0 - Byte Enabled For Byte 0 (least significant) 0b0..The byte was not read. 0b1..The byte was read.

◆ CAN_RERRSYNR_BE1 [1/2]

#define CAN_RERRSYNR_BE1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)

BE1 - Byte Enabled For Byte 1 0b0..The byte was not read. 0b1..The byte was read.

◆ CAN_RERRSYNR_BE1 [2/2]

#define CAN_RERRSYNR_BE1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)

BE1 - Byte Enabled For Byte 1 0b0..The byte was not read. 0b1..The byte was read.

◆ CAN_RERRSYNR_BE2 [1/2]

#define CAN_RERRSYNR_BE2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)

BE2 - Byte Enabled For Byte 2 0b0..The byte was not read. 0b1..The byte was read.

◆ CAN_RERRSYNR_BE2 [2/2]

#define CAN_RERRSYNR_BE2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)

BE2 - Byte Enabled For Byte 2 0b0..The byte was not read. 0b1..The byte was read.

◆ CAN_RERRSYNR_BE3 [1/2]

#define CAN_RERRSYNR_BE3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)

BE3 - Byte Enabled For Byte 3 (most significant) 0b0..The byte was not read. 0b1..The byte was read.

◆ CAN_RERRSYNR_BE3 [2/2]

#define CAN_RERRSYNR_BE3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)

BE3 - Byte Enabled For Byte 3 (most significant) 0b0..The byte was not read. 0b1..The byte was read.

◆ CAN_RERRSYNR_SYND0 [1/2]

#define CAN_RERRSYNR_SYND0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)

SYND0 - Error Syndrome For Byte 0 (least significant)

◆ CAN_RERRSYNR_SYND0 [2/2]

#define CAN_RERRSYNR_SYND0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)

SYND0 - Error Syndrome For Byte 0 (least significant)

◆ CAN_RERRSYNR_SYND1 [1/2]

#define CAN_RERRSYNR_SYND1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)

SYND1 - Error Syndrome for Byte 1

◆ CAN_RERRSYNR_SYND1 [2/2]

#define CAN_RERRSYNR_SYND1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)

SYND1 - Error Syndrome for Byte 1

◆ CAN_RERRSYNR_SYND2 [1/2]

#define CAN_RERRSYNR_SYND2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)

SYND2 - Error Syndrome For Byte 2

◆ CAN_RERRSYNR_SYND2 [2/2]

#define CAN_RERRSYNR_SYND2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)

SYND2 - Error Syndrome For Byte 2

◆ CAN_RERRSYNR_SYND3 [1/2]

#define CAN_RERRSYNR_SYND3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)

SYND3 - Error Syndrome For Byte 3 (most significant)

◆ CAN_RERRSYNR_SYND3 [2/2]

#define CAN_RERRSYNR_SYND3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)

SYND3 - Error Syndrome For Byte 3 (most significant)

◆ CAN_RX14MASK_RX14M [1/3]

#define CAN_RX14MASK_RX14M ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX14M 0b00000000000000000000000000000001..The corresponding bit in the filter is checked 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"

◆ CAN_RX14MASK_RX14M [2/3]

#define CAN_RX14MASK_RX14M ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX14M - Rx Buffer 14 Mask Bits

◆ CAN_RX14MASK_RX14M [3/3]

#define CAN_RX14MASK_RX14M ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX14M - Rx Buffer 14 Mask Bits

◆ CAN_RX15MASK_RX15M [1/3]

#define CAN_RX15MASK_RX15M ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

RX15M 0b00000000000000000000000000000001..The corresponding bit in the filter is checked 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"

◆ CAN_RX15MASK_RX15M [2/3]

#define CAN_RX15MASK_RX15M ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

RX15M - Rx Buffer 15 Mask Bits

◆ CAN_RX15MASK_RX15M [3/3]

#define CAN_RX15MASK_RX15M ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

RX15M - Rx Buffer 15 Mask Bits

◆ CAN_RXFGMASK_FGM [1/3]

#define CAN_RXFGMASK_FGM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

FGM 0b00000000000000000000000000000001..The corresponding bit in the filter is checked 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care"

◆ CAN_RXFGMASK_FGM [2/3]

#define CAN_RXFGMASK_FGM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

FGM - Rx FIFO Global Mask Bits

◆ CAN_RXFGMASK_FGM [3/3]

#define CAN_RXFGMASK_FGM ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

FGM - Rx FIFO Global Mask Bits

◆ CAN_RXFIR_IDHIT [1/2]

#define CAN_RXFIR_IDHIT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)

IDHIT - Identifier Acceptance Filter Hit Indicator

◆ CAN_RXFIR_IDHIT [2/2]

#define CAN_RXFIR_IDHIT ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)

IDHIT - Identifier Acceptance Filter Hit Indicator

◆ CAN_RXIMR_MI [1/3]

#define CAN_RXIMR_MI ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

MI 0b00000000000000000000000000000001..The corresponding bit in the filter is checked 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"

◆ CAN_RXIMR_MI [2/3]

#define CAN_RXIMR_MI ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

MI - Individual Mask Bits

◆ CAN_RXIMR_MI [3/3]

#define CAN_RXIMR_MI ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

MI - Individual Mask Bits

◆ CAN_RXMGMASK_MG [1/3]

#define CAN_RXMGMASK_MG ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

MG 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"

◆ CAN_RXMGMASK_MG [2/3]

#define CAN_RXMGMASK_MG ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

MG - Rx Mailboxes Global Mask Bits

◆ CAN_RXMGMASK_MG [3/3]

#define CAN_RXMGMASK_MG ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

MG - Rx Mailboxes Global Mask Bits

◆ CAN_TIMER_TIMER [1/2]

#define CAN_TIMER_TIMER ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)

TIMER - Timer Value

◆ CAN_TIMER_TIMER [2/2]

#define CAN_TIMER_TIMER ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)

TIMER - Timer Value

◆ CAN_WORD0_DATA_BYTE_0 [1/3]

#define CAN_WORD0_DATA_BYTE_0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)

DATA_BYTE_0 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD0_DATA_BYTE_0 [2/3]

#define CAN_WORD0_DATA_BYTE_0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)

DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD0_DATA_BYTE_0 [3/3]

#define CAN_WORD0_DATA_BYTE_0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)

DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD0_DATA_BYTE_1 [1/3]

#define CAN_WORD0_DATA_BYTE_1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)

DATA_BYTE_1 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD0_DATA_BYTE_1 [2/3]

#define CAN_WORD0_DATA_BYTE_1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)

DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD0_DATA_BYTE_1 [3/3]

#define CAN_WORD0_DATA_BYTE_1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)

DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD0_DATA_BYTE_2 [1/3]

#define CAN_WORD0_DATA_BYTE_2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)

DATA_BYTE_2 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD0_DATA_BYTE_2 [2/3]

#define CAN_WORD0_DATA_BYTE_2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)

DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD0_DATA_BYTE_2 [3/3]

#define CAN_WORD0_DATA_BYTE_2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)

DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD0_DATA_BYTE_3 [1/3]

#define CAN_WORD0_DATA_BYTE_3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)

DATA_BYTE_3 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD0_DATA_BYTE_3 [2/3]

#define CAN_WORD0_DATA_BYTE_3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)

DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD0_DATA_BYTE_3 [3/3]

#define CAN_WORD0_DATA_BYTE_3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)

DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_4 [1/3]

#define CAN_WORD1_DATA_BYTE_4 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)

DATA_BYTE_4 - Data byte 4 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_4 [2/3]

#define CAN_WORD1_DATA_BYTE_4 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)

DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_4 [3/3]

#define CAN_WORD1_DATA_BYTE_4 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)

DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_5 [1/3]

#define CAN_WORD1_DATA_BYTE_5 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)

DATA_BYTE_5 - Data byte 5 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_5 [2/3]

#define CAN_WORD1_DATA_BYTE_5 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)

DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_5 [3/3]

#define CAN_WORD1_DATA_BYTE_5 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)

DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_6 [1/3]

#define CAN_WORD1_DATA_BYTE_6 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)

DATA_BYTE_6 - Data byte 6 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_6 [2/3]

#define CAN_WORD1_DATA_BYTE_6 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)

DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_6 [3/3]

#define CAN_WORD1_DATA_BYTE_6 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)

DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_7 [1/3]

#define CAN_WORD1_DATA_BYTE_7 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)

DATA_BYTE_7 - Data byte 7 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_7 [2/3]

#define CAN_WORD1_DATA_BYTE_7 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)

DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD1_DATA_BYTE_7 [3/3]

#define CAN_WORD1_DATA_BYTE_7 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)

DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_0 [1/4]

#define CAN_WORD_DATA_BYTE_0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)

DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_0 [2/4]

#define CAN_WORD_DATA_BYTE_0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)

DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_0 [3/4]

#define CAN_WORD_DATA_BYTE_0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)

DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_0 [4/4]

#define CAN_WORD_DATA_BYTE_0 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)

DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_1 [1/4]

#define CAN_WORD_DATA_BYTE_1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)

DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_1 [2/4]

#define CAN_WORD_DATA_BYTE_1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)

DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_1 [3/4]

#define CAN_WORD_DATA_BYTE_1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)

DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_1 [4/4]

#define CAN_WORD_DATA_BYTE_1 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)

DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_10 [1/4]

#define CAN_WORD_DATA_BYTE_10 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)

DATA_BYTE_10 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_10 [2/4]

#define CAN_WORD_DATA_BYTE_10 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)

DATA_BYTE_10 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_10 [3/4]

#define CAN_WORD_DATA_BYTE_10 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)

DATA_BYTE_10 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_10 [4/4]

#define CAN_WORD_DATA_BYTE_10 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)

DATA_BYTE_10 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_11 [1/4]

#define CAN_WORD_DATA_BYTE_11 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)

DATA_BYTE_11 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_11 [2/4]

#define CAN_WORD_DATA_BYTE_11 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)

DATA_BYTE_11 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_11 [3/4]

#define CAN_WORD_DATA_BYTE_11 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)

DATA_BYTE_11 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_11 [4/4]

#define CAN_WORD_DATA_BYTE_11 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)

DATA_BYTE_11 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_12 [1/4]

#define CAN_WORD_DATA_BYTE_12 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)

DATA_BYTE_12 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_12 [2/4]

#define CAN_WORD_DATA_BYTE_12 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)

DATA_BYTE_12 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_12 [3/4]

#define CAN_WORD_DATA_BYTE_12 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)

DATA_BYTE_12 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_12 [4/4]

#define CAN_WORD_DATA_BYTE_12 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)

DATA_BYTE_12 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_13 [1/4]

#define CAN_WORD_DATA_BYTE_13 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)

DATA_BYTE_13 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_13 [2/4]

#define CAN_WORD_DATA_BYTE_13 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)

DATA_BYTE_13 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_13 [3/4]

#define CAN_WORD_DATA_BYTE_13 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)

DATA_BYTE_13 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_13 [4/4]

#define CAN_WORD_DATA_BYTE_13 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)

DATA_BYTE_13 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_14 [1/4]

#define CAN_WORD_DATA_BYTE_14 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)

DATA_BYTE_14 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_14 [2/4]

#define CAN_WORD_DATA_BYTE_14 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)

DATA_BYTE_14 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_14 [3/4]

#define CAN_WORD_DATA_BYTE_14 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)

DATA_BYTE_14 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_14 [4/4]

#define CAN_WORD_DATA_BYTE_14 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)

DATA_BYTE_14 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_15 [1/4]

#define CAN_WORD_DATA_BYTE_15 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)

DATA_BYTE_15 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_15 [2/4]

#define CAN_WORD_DATA_BYTE_15 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)

DATA_BYTE_15 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_15 [3/4]

#define CAN_WORD_DATA_BYTE_15 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)

DATA_BYTE_15 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_15 [4/4]

#define CAN_WORD_DATA_BYTE_15 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)

DATA_BYTE_15 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_16 [1/4]

#define CAN_WORD_DATA_BYTE_16 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)

DATA_BYTE_16 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_16 [2/4]

#define CAN_WORD_DATA_BYTE_16 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)

DATA_BYTE_16 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_16 [3/4]

#define CAN_WORD_DATA_BYTE_16 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)

DATA_BYTE_16 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_16 [4/4]

#define CAN_WORD_DATA_BYTE_16 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)

DATA_BYTE_16 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_17 [1/4]

#define CAN_WORD_DATA_BYTE_17 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)

DATA_BYTE_17 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_17 [2/4]

#define CAN_WORD_DATA_BYTE_17 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)

DATA_BYTE_17 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_17 [3/4]

#define CAN_WORD_DATA_BYTE_17 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)

DATA_BYTE_17 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_17 [4/4]

#define CAN_WORD_DATA_BYTE_17 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)

DATA_BYTE_17 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_18 [1/4]

#define CAN_WORD_DATA_BYTE_18 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)

DATA_BYTE_18 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_18 [2/4]

#define CAN_WORD_DATA_BYTE_18 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)

DATA_BYTE_18 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_18 [3/4]

#define CAN_WORD_DATA_BYTE_18 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)

DATA_BYTE_18 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_18 [4/4]

#define CAN_WORD_DATA_BYTE_18 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)

DATA_BYTE_18 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_19 [1/4]

#define CAN_WORD_DATA_BYTE_19 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)

DATA_BYTE_19 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_19 [2/4]

#define CAN_WORD_DATA_BYTE_19 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)

DATA_BYTE_19 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_19 [3/4]

#define CAN_WORD_DATA_BYTE_19 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)

DATA_BYTE_19 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_19 [4/4]

#define CAN_WORD_DATA_BYTE_19 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)

DATA_BYTE_19 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_2 [1/4]

#define CAN_WORD_DATA_BYTE_2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)

DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_2 [2/4]

#define CAN_WORD_DATA_BYTE_2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)

DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_2 [3/4]

#define CAN_WORD_DATA_BYTE_2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)

DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_2 [4/4]

#define CAN_WORD_DATA_BYTE_2 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)

DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_20 [1/4]

#define CAN_WORD_DATA_BYTE_20 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)

DATA_BYTE_20 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_20 [2/4]

#define CAN_WORD_DATA_BYTE_20 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)

DATA_BYTE_20 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_20 [3/4]

#define CAN_WORD_DATA_BYTE_20 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)

DATA_BYTE_20 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_20 [4/4]

#define CAN_WORD_DATA_BYTE_20 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)

DATA_BYTE_20 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_21 [1/4]

#define CAN_WORD_DATA_BYTE_21 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)

DATA_BYTE_21 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_21 [2/4]

#define CAN_WORD_DATA_BYTE_21 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)

DATA_BYTE_21 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_21 [3/4]

#define CAN_WORD_DATA_BYTE_21 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)

DATA_BYTE_21 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_21 [4/4]

#define CAN_WORD_DATA_BYTE_21 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)

DATA_BYTE_21 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_22 [1/4]

#define CAN_WORD_DATA_BYTE_22 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)

DATA_BYTE_22 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_22 [2/4]

#define CAN_WORD_DATA_BYTE_22 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)

DATA_BYTE_22 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_22 [3/4]

#define CAN_WORD_DATA_BYTE_22 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)

DATA_BYTE_22 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_22 [4/4]

#define CAN_WORD_DATA_BYTE_22 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)

DATA_BYTE_22 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_23 [1/4]

#define CAN_WORD_DATA_BYTE_23 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)

DATA_BYTE_23 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_23 [2/4]

#define CAN_WORD_DATA_BYTE_23 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)

DATA_BYTE_23 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_23 [3/4]

#define CAN_WORD_DATA_BYTE_23 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)

DATA_BYTE_23 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_23 [4/4]

#define CAN_WORD_DATA_BYTE_23 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)

DATA_BYTE_23 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_24 [1/4]

#define CAN_WORD_DATA_BYTE_24 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)

DATA_BYTE_24 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_24 [2/4]

#define CAN_WORD_DATA_BYTE_24 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)

DATA_BYTE_24 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_24 [3/4]

#define CAN_WORD_DATA_BYTE_24 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)

DATA_BYTE_24 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_24 [4/4]

#define CAN_WORD_DATA_BYTE_24 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)

DATA_BYTE_24 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_25 [1/4]

#define CAN_WORD_DATA_BYTE_25 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)

DATA_BYTE_25 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_25 [2/4]

#define CAN_WORD_DATA_BYTE_25 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)

DATA_BYTE_25 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_25 [3/4]

#define CAN_WORD_DATA_BYTE_25 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)

DATA_BYTE_25 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_25 [4/4]

#define CAN_WORD_DATA_BYTE_25 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)

DATA_BYTE_25 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_26 [1/4]

#define CAN_WORD_DATA_BYTE_26 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)

DATA_BYTE_26 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_26 [2/4]

#define CAN_WORD_DATA_BYTE_26 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)

DATA_BYTE_26 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_26 [3/4]

#define CAN_WORD_DATA_BYTE_26 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)

DATA_BYTE_26 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_26 [4/4]

#define CAN_WORD_DATA_BYTE_26 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)

DATA_BYTE_26 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_27 [1/4]

#define CAN_WORD_DATA_BYTE_27 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)

DATA_BYTE_27 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_27 [2/4]

#define CAN_WORD_DATA_BYTE_27 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)

DATA_BYTE_27 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_27 [3/4]

#define CAN_WORD_DATA_BYTE_27 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)

DATA_BYTE_27 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_27 [4/4]

#define CAN_WORD_DATA_BYTE_27 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)

DATA_BYTE_27 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_28 [1/4]

#define CAN_WORD_DATA_BYTE_28 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)

DATA_BYTE_28 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_28 [2/4]

#define CAN_WORD_DATA_BYTE_28 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)

DATA_BYTE_28 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_28 [3/4]

#define CAN_WORD_DATA_BYTE_28 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)

DATA_BYTE_28 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_28 [4/4]

#define CAN_WORD_DATA_BYTE_28 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)

DATA_BYTE_28 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_29 [1/4]

#define CAN_WORD_DATA_BYTE_29 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)

DATA_BYTE_29 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_29 [2/4]

#define CAN_WORD_DATA_BYTE_29 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)

DATA_BYTE_29 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_29 [3/4]

#define CAN_WORD_DATA_BYTE_29 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)

DATA_BYTE_29 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_29 [4/4]

#define CAN_WORD_DATA_BYTE_29 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)

DATA_BYTE_29 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_3 [1/4]

#define CAN_WORD_DATA_BYTE_3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)

DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_3 [2/4]

#define CAN_WORD_DATA_BYTE_3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)

DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_3 [3/4]

#define CAN_WORD_DATA_BYTE_3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)

DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_3 [4/4]

#define CAN_WORD_DATA_BYTE_3 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)

DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_30 [1/4]

#define CAN_WORD_DATA_BYTE_30 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)

DATA_BYTE_30 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_30 [2/4]

#define CAN_WORD_DATA_BYTE_30 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)

DATA_BYTE_30 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_30 [3/4]

#define CAN_WORD_DATA_BYTE_30 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)

DATA_BYTE_30 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_30 [4/4]

#define CAN_WORD_DATA_BYTE_30 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)

DATA_BYTE_30 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_31 [1/4]

#define CAN_WORD_DATA_BYTE_31 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)

DATA_BYTE_31 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_31 [2/4]

#define CAN_WORD_DATA_BYTE_31 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)

DATA_BYTE_31 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_31 [3/4]

#define CAN_WORD_DATA_BYTE_31 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)

DATA_BYTE_31 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_31 [4/4]

#define CAN_WORD_DATA_BYTE_31 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)

DATA_BYTE_31 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_32 [1/4]

#define CAN_WORD_DATA_BYTE_32 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)

DATA_BYTE_32 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_32 [2/4]

#define CAN_WORD_DATA_BYTE_32 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)

DATA_BYTE_32 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_32 [3/4]

#define CAN_WORD_DATA_BYTE_32 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)

DATA_BYTE_32 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_32 [4/4]

#define CAN_WORD_DATA_BYTE_32 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)

DATA_BYTE_32 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_33 [1/4]

#define CAN_WORD_DATA_BYTE_33 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)

DATA_BYTE_33 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_33 [2/4]

#define CAN_WORD_DATA_BYTE_33 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)

DATA_BYTE_33 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_33 [3/4]

#define CAN_WORD_DATA_BYTE_33 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)

DATA_BYTE_33 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_33 [4/4]

#define CAN_WORD_DATA_BYTE_33 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)

DATA_BYTE_33 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_34 [1/4]

#define CAN_WORD_DATA_BYTE_34 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)

DATA_BYTE_34 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_34 [2/4]

#define CAN_WORD_DATA_BYTE_34 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)

DATA_BYTE_34 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_34 [3/4]

#define CAN_WORD_DATA_BYTE_34 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)

DATA_BYTE_34 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_34 [4/4]

#define CAN_WORD_DATA_BYTE_34 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)

DATA_BYTE_34 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_35 [1/4]

#define CAN_WORD_DATA_BYTE_35 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)

DATA_BYTE_35 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_35 [2/4]

#define CAN_WORD_DATA_BYTE_35 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)

DATA_BYTE_35 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_35 [3/4]

#define CAN_WORD_DATA_BYTE_35 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)

DATA_BYTE_35 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_35 [4/4]

#define CAN_WORD_DATA_BYTE_35 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)

DATA_BYTE_35 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_36 [1/4]

#define CAN_WORD_DATA_BYTE_36 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)

DATA_BYTE_36 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_36 [2/4]

#define CAN_WORD_DATA_BYTE_36 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)

DATA_BYTE_36 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_36 [3/4]

#define CAN_WORD_DATA_BYTE_36 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)

DATA_BYTE_36 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_36 [4/4]

#define CAN_WORD_DATA_BYTE_36 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)

DATA_BYTE_36 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_37 [1/4]

#define CAN_WORD_DATA_BYTE_37 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)

DATA_BYTE_37 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_37 [2/4]

#define CAN_WORD_DATA_BYTE_37 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)

DATA_BYTE_37 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_37 [3/4]

#define CAN_WORD_DATA_BYTE_37 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)

DATA_BYTE_37 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_37 [4/4]

#define CAN_WORD_DATA_BYTE_37 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)

DATA_BYTE_37 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_38 [1/4]

#define CAN_WORD_DATA_BYTE_38 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)

DATA_BYTE_38 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_38 [2/4]

#define CAN_WORD_DATA_BYTE_38 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)

DATA_BYTE_38 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_38 [3/4]

#define CAN_WORD_DATA_BYTE_38 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)

DATA_BYTE_38 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_38 [4/4]

#define CAN_WORD_DATA_BYTE_38 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)

DATA_BYTE_38 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_39 [1/4]

#define CAN_WORD_DATA_BYTE_39 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)

DATA_BYTE_39 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_39 [2/4]

#define CAN_WORD_DATA_BYTE_39 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)

DATA_BYTE_39 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_39 [3/4]

#define CAN_WORD_DATA_BYTE_39 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)

DATA_BYTE_39 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_39 [4/4]

#define CAN_WORD_DATA_BYTE_39 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)

DATA_BYTE_39 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_4 [1/4]

#define CAN_WORD_DATA_BYTE_4 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)

DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_4 [2/4]

#define CAN_WORD_DATA_BYTE_4 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)

DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_4 [3/4]

#define CAN_WORD_DATA_BYTE_4 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)

DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_4 [4/4]

#define CAN_WORD_DATA_BYTE_4 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)

DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_40 [1/4]

#define CAN_WORD_DATA_BYTE_40 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)

DATA_BYTE_40 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_40 [2/4]

#define CAN_WORD_DATA_BYTE_40 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)

DATA_BYTE_40 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_40 [3/4]

#define CAN_WORD_DATA_BYTE_40 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)

DATA_BYTE_40 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_40 [4/4]

#define CAN_WORD_DATA_BYTE_40 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)

DATA_BYTE_40 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_41 [1/4]

#define CAN_WORD_DATA_BYTE_41 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)

DATA_BYTE_41 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_41 [2/4]

#define CAN_WORD_DATA_BYTE_41 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)

DATA_BYTE_41 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_41 [3/4]

#define CAN_WORD_DATA_BYTE_41 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)

DATA_BYTE_41 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_41 [4/4]

#define CAN_WORD_DATA_BYTE_41 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)

DATA_BYTE_41 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_42 [1/4]

#define CAN_WORD_DATA_BYTE_42 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)

DATA_BYTE_42 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_42 [2/4]

#define CAN_WORD_DATA_BYTE_42 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)

DATA_BYTE_42 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_42 [3/4]

#define CAN_WORD_DATA_BYTE_42 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)

DATA_BYTE_42 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_42 [4/4]

#define CAN_WORD_DATA_BYTE_42 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)

DATA_BYTE_42 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_43 [1/4]

#define CAN_WORD_DATA_BYTE_43 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)

DATA_BYTE_43 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_43 [2/4]

#define CAN_WORD_DATA_BYTE_43 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)

DATA_BYTE_43 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_43 [3/4]

#define CAN_WORD_DATA_BYTE_43 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)

DATA_BYTE_43 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_43 [4/4]

#define CAN_WORD_DATA_BYTE_43 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)

DATA_BYTE_43 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_44 [1/4]

#define CAN_WORD_DATA_BYTE_44 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)

DATA_BYTE_44 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_44 [2/4]

#define CAN_WORD_DATA_BYTE_44 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)

DATA_BYTE_44 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_44 [3/4]

#define CAN_WORD_DATA_BYTE_44 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)

DATA_BYTE_44 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_44 [4/4]

#define CAN_WORD_DATA_BYTE_44 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)

DATA_BYTE_44 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_45 [1/4]

#define CAN_WORD_DATA_BYTE_45 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)

DATA_BYTE_45 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_45 [2/4]

#define CAN_WORD_DATA_BYTE_45 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)

DATA_BYTE_45 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_45 [3/4]

#define CAN_WORD_DATA_BYTE_45 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)

DATA_BYTE_45 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_45 [4/4]

#define CAN_WORD_DATA_BYTE_45 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)

DATA_BYTE_45 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_46 [1/4]

#define CAN_WORD_DATA_BYTE_46 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)

DATA_BYTE_46 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_46 [2/4]

#define CAN_WORD_DATA_BYTE_46 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)

DATA_BYTE_46 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_46 [3/4]

#define CAN_WORD_DATA_BYTE_46 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)

DATA_BYTE_46 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_46 [4/4]

#define CAN_WORD_DATA_BYTE_46 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)

DATA_BYTE_46 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_47 [1/4]

#define CAN_WORD_DATA_BYTE_47 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)

DATA_BYTE_47 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_47 [2/4]

#define CAN_WORD_DATA_BYTE_47 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)

DATA_BYTE_47 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_47 [3/4]

#define CAN_WORD_DATA_BYTE_47 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)

DATA_BYTE_47 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_47 [4/4]

#define CAN_WORD_DATA_BYTE_47 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)

DATA_BYTE_47 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_48 [1/4]

#define CAN_WORD_DATA_BYTE_48 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)

DATA_BYTE_48 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_48 [2/4]

#define CAN_WORD_DATA_BYTE_48 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)

DATA_BYTE_48 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_48 [3/4]

#define CAN_WORD_DATA_BYTE_48 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)

DATA_BYTE_48 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_48 [4/4]

#define CAN_WORD_DATA_BYTE_48 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)

DATA_BYTE_48 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_49 [1/4]

#define CAN_WORD_DATA_BYTE_49 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)

DATA_BYTE_49 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_49 [2/4]

#define CAN_WORD_DATA_BYTE_49 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)

DATA_BYTE_49 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_49 [3/4]

#define CAN_WORD_DATA_BYTE_49 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)

DATA_BYTE_49 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_49 [4/4]

#define CAN_WORD_DATA_BYTE_49 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)

DATA_BYTE_49 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_5 [1/4]

#define CAN_WORD_DATA_BYTE_5 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)

DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_5 [2/4]

#define CAN_WORD_DATA_BYTE_5 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)

DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_5 [3/4]

#define CAN_WORD_DATA_BYTE_5 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)

DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_5 [4/4]

#define CAN_WORD_DATA_BYTE_5 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)

DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_50 [1/4]

#define CAN_WORD_DATA_BYTE_50 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)

DATA_BYTE_50 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_50 [2/4]

#define CAN_WORD_DATA_BYTE_50 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)

DATA_BYTE_50 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_50 [3/4]

#define CAN_WORD_DATA_BYTE_50 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)

DATA_BYTE_50 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_50 [4/4]

#define CAN_WORD_DATA_BYTE_50 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)

DATA_BYTE_50 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_51 [1/4]

#define CAN_WORD_DATA_BYTE_51 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)

DATA_BYTE_51 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_51 [2/4]

#define CAN_WORD_DATA_BYTE_51 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)

DATA_BYTE_51 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_51 [3/4]

#define CAN_WORD_DATA_BYTE_51 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)

DATA_BYTE_51 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_51 [4/4]

#define CAN_WORD_DATA_BYTE_51 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)

DATA_BYTE_51 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_52 [1/4]

#define CAN_WORD_DATA_BYTE_52 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)

DATA_BYTE_52 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_52 [2/4]

#define CAN_WORD_DATA_BYTE_52 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)

DATA_BYTE_52 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_52 [3/4]

#define CAN_WORD_DATA_BYTE_52 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)

DATA_BYTE_52 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_52 [4/4]

#define CAN_WORD_DATA_BYTE_52 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)

DATA_BYTE_52 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_53 [1/4]

#define CAN_WORD_DATA_BYTE_53 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)

DATA_BYTE_53 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_53 [2/4]

#define CAN_WORD_DATA_BYTE_53 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)

DATA_BYTE_53 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_53 [3/4]

#define CAN_WORD_DATA_BYTE_53 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)

DATA_BYTE_53 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_53 [4/4]

#define CAN_WORD_DATA_BYTE_53 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)

DATA_BYTE_53 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_54 [1/4]

#define CAN_WORD_DATA_BYTE_54 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)

DATA_BYTE_54 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_54 [2/4]

#define CAN_WORD_DATA_BYTE_54 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)

DATA_BYTE_54 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_54 [3/4]

#define CAN_WORD_DATA_BYTE_54 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)

DATA_BYTE_54 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_54 [4/4]

#define CAN_WORD_DATA_BYTE_54 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)

DATA_BYTE_54 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_55 [1/4]

#define CAN_WORD_DATA_BYTE_55 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)

DATA_BYTE_55 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_55 [2/4]

#define CAN_WORD_DATA_BYTE_55 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)

DATA_BYTE_55 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_55 [3/4]

#define CAN_WORD_DATA_BYTE_55 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)

DATA_BYTE_55 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_55 [4/4]

#define CAN_WORD_DATA_BYTE_55 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)

DATA_BYTE_55 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_56 [1/4]

#define CAN_WORD_DATA_BYTE_56 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)

DATA_BYTE_56 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_56 [2/4]

#define CAN_WORD_DATA_BYTE_56 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)

DATA_BYTE_56 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_56 [3/4]

#define CAN_WORD_DATA_BYTE_56 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)

DATA_BYTE_56 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_56 [4/4]

#define CAN_WORD_DATA_BYTE_56 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)

DATA_BYTE_56 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_57 [1/4]

#define CAN_WORD_DATA_BYTE_57 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)

DATA_BYTE_57 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_57 [2/4]

#define CAN_WORD_DATA_BYTE_57 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)

DATA_BYTE_57 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_57 [3/4]

#define CAN_WORD_DATA_BYTE_57 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)

DATA_BYTE_57 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_57 [4/4]

#define CAN_WORD_DATA_BYTE_57 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)

DATA_BYTE_57 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_58 [1/4]

#define CAN_WORD_DATA_BYTE_58 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)

DATA_BYTE_58 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_58 [2/4]

#define CAN_WORD_DATA_BYTE_58 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)

DATA_BYTE_58 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_58 [3/4]

#define CAN_WORD_DATA_BYTE_58 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)

DATA_BYTE_58 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_58 [4/4]

#define CAN_WORD_DATA_BYTE_58 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)

DATA_BYTE_58 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_59 [1/4]

#define CAN_WORD_DATA_BYTE_59 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)

DATA_BYTE_59 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_59 [2/4]

#define CAN_WORD_DATA_BYTE_59 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)

DATA_BYTE_59 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_59 [3/4]

#define CAN_WORD_DATA_BYTE_59 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)

DATA_BYTE_59 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_59 [4/4]

#define CAN_WORD_DATA_BYTE_59 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)

DATA_BYTE_59 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_6 [1/4]

#define CAN_WORD_DATA_BYTE_6 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)

DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_6 [2/4]

#define CAN_WORD_DATA_BYTE_6 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)

DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_6 [3/4]

#define CAN_WORD_DATA_BYTE_6 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)

DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_6 [4/4]

#define CAN_WORD_DATA_BYTE_6 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)

DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_60 [1/4]

#define CAN_WORD_DATA_BYTE_60 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)

DATA_BYTE_60 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_60 [2/4]

#define CAN_WORD_DATA_BYTE_60 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)

DATA_BYTE_60 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_60 [3/4]

#define CAN_WORD_DATA_BYTE_60 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)

DATA_BYTE_60 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_60 [4/4]

#define CAN_WORD_DATA_BYTE_60 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)

DATA_BYTE_60 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_61 [1/4]

#define CAN_WORD_DATA_BYTE_61 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)

DATA_BYTE_61 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_61 [2/4]

#define CAN_WORD_DATA_BYTE_61 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)

DATA_BYTE_61 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_61 [3/4]

#define CAN_WORD_DATA_BYTE_61 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)

DATA_BYTE_61 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_61 [4/4]

#define CAN_WORD_DATA_BYTE_61 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)

DATA_BYTE_61 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_62 [1/4]

#define CAN_WORD_DATA_BYTE_62 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)

DATA_BYTE_62 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_62 [2/4]

#define CAN_WORD_DATA_BYTE_62 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)

DATA_BYTE_62 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_62 [3/4]

#define CAN_WORD_DATA_BYTE_62 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)

DATA_BYTE_62 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_62 [4/4]

#define CAN_WORD_DATA_BYTE_62 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)

DATA_BYTE_62 - Data byte 1 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_63 [1/4]

#define CAN_WORD_DATA_BYTE_63 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)

DATA_BYTE_63 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_63 [2/4]

#define CAN_WORD_DATA_BYTE_63 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)

DATA_BYTE_63 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_63 [3/4]

#define CAN_WORD_DATA_BYTE_63 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)

DATA_BYTE_63 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_63 [4/4]

#define CAN_WORD_DATA_BYTE_63 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)

DATA_BYTE_63 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_7 [1/4]

#define CAN_WORD_DATA_BYTE_7 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)

DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_7 [2/4]

#define CAN_WORD_DATA_BYTE_7 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)

DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_7 [3/4]

#define CAN_WORD_DATA_BYTE_7 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)

DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_7 [4/4]

#define CAN_WORD_DATA_BYTE_7 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)

DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_8 [1/4]

#define CAN_WORD_DATA_BYTE_8 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)

DATA_BYTE_8 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_8 [2/4]

#define CAN_WORD_DATA_BYTE_8 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)

DATA_BYTE_8 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_8 [3/4]

#define CAN_WORD_DATA_BYTE_8 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)

DATA_BYTE_8 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_8 [4/4]

#define CAN_WORD_DATA_BYTE_8 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)

DATA_BYTE_8 - Data byte 3 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_9 [1/4]

#define CAN_WORD_DATA_BYTE_9 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)

DATA_BYTE_9 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_9 [2/4]

#define CAN_WORD_DATA_BYTE_9 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)

DATA_BYTE_9 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_9 [3/4]

#define CAN_WORD_DATA_BYTE_9 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)

DATA_BYTE_9 - Data byte 2 of Rx/Tx frame.

◆ CAN_WORD_DATA_BYTE_9 [4/4]

#define CAN_WORD_DATA_BYTE_9 ( x ) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)

DATA_BYTE_9 - Data byte 2 of Rx/Tx frame.

◆ ENC_CTRL2_DIR [1/3]

#define ENC_CTRL2_DIR ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

DIR - Count Direction Flag 0b0..Last count was in the down direction 0b1..Last count was in the up direction

◆ ENC_CTRL2_DIR [2/3]

#define ENC_CTRL2_DIR ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

DIR - Count Direction Flag 0b0..Last count was in the down direction 0b1..Last count was in the up direction

◆ ENC_CTRL2_DIR [3/3]

#define ENC_CTRL2_DIR ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

DIR - Count Direction Flag 0b0..Last count was in the down direction 0b1..Last count was in the up direction

◆ ENC_CTRL2_MOD [1/3]

#define ENC_CTRL2_MOD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

MOD - Enable Modulo Counting 0b0..Disable modulo counting 0b1..Enable modulo counting

◆ ENC_CTRL2_MOD [2/3]

#define ENC_CTRL2_MOD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

MOD - Enable Modulo Counting 0b0..Disable modulo counting 0b1..Enable modulo counting

◆ ENC_CTRL2_MOD [3/3]

#define ENC_CTRL2_MOD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

MOD - Enable Modulo Counting 0b0..Disable modulo counting 0b1..Enable modulo counting

◆ ENC_CTRL2_OUTCTL [1/3]

#define ENC_CTRL2_OUTCTL ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

OUTCTL - Output Control 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read

◆ ENC_CTRL2_OUTCTL [2/3]

#define ENC_CTRL2_OUTCTL ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

OUTCTL - Output Control 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read

◆ ENC_CTRL2_OUTCTL [3/3]

#define ENC_CTRL2_OUTCTL ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

OUTCTL - Output Control 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read

◆ ENC_CTRL2_REVMOD [1/3]

#define ENC_CTRL2_REVMOD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

REVMOD - Revolution Counter Modulus Enable 0b0..Use INDEX pulse to increment/decrement revolution counter (REV) 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)

◆ ENC_CTRL2_REVMOD [2/3]

#define ENC_CTRL2_REVMOD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

REVMOD - Revolution Counter Modulus Enable 0b0..Use INDEX pulse to increment/decrement revolution counter (REV) 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)

◆ ENC_CTRL2_REVMOD [3/3]

#define ENC_CTRL2_REVMOD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

REVMOD - Revolution Counter Modulus Enable 0b0..Use INDEX pulse to increment/decrement revolution counter (REV) 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)

◆ ENC_CTRL2_ROIE [1/3]

#define ENC_CTRL2_ROIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

ROIE - Roll-over Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ ENC_CTRL2_ROIE [2/3]

#define ENC_CTRL2_ROIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

ROIE - Roll-over Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ ENC_CTRL2_ROIE [3/3]

#define ENC_CTRL2_ROIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

ROIE - Roll-over Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ ENC_CTRL2_ROIRQ [1/3]

#define ENC_CTRL2_ROIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

ROIRQ - Roll-over Interrupt Request 0b0..No roll-over has occurred 0b1..Roll-over has occurred

◆ ENC_CTRL2_ROIRQ [2/3]

#define ENC_CTRL2_ROIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

ROIRQ - Roll-over Interrupt Request 0b0..No roll-over has occurred 0b1..Roll-over has occurred

◆ ENC_CTRL2_ROIRQ [3/3]

#define ENC_CTRL2_ROIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

ROIRQ - Roll-over Interrupt Request 0b0..No roll-over has occurred 0b1..Roll-over has occurred

◆ ENC_CTRL2_RUIE [1/3]

#define ENC_CTRL2_RUIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

RUIE - Roll-under Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ ENC_CTRL2_RUIE [2/3]

#define ENC_CTRL2_RUIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

RUIE - Roll-under Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ ENC_CTRL2_RUIE [3/3]

#define ENC_CTRL2_RUIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

RUIE - Roll-under Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ ENC_CTRL2_RUIRQ [1/3]

#define ENC_CTRL2_RUIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

RUIRQ - Roll-under Interrupt Request 0b0..No roll-under has occurred 0b1..Roll-under has occurred

◆ ENC_CTRL2_RUIRQ [2/3]

#define ENC_CTRL2_RUIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

RUIRQ - Roll-under Interrupt Request 0b0..No roll-under has occurred 0b1..Roll-under has occurred

◆ ENC_CTRL2_RUIRQ [3/3]

#define ENC_CTRL2_RUIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

RUIRQ - Roll-under Interrupt Request 0b0..No roll-under has occurred 0b1..Roll-under has occurred

◆ ENC_CTRL2_SABIE [1/2]

#define ENC_CTRL2_SABIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)

SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ ENC_CTRL2_SABIE [2/2]

#define ENC_CTRL2_SABIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)

SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable 0b0..Disabled 0b1..Enabled

◆ ENC_CTRL2_SABIRQ [1/2]

#define ENC_CTRL2_SABIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)

SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request 0b0..No simultaneous change of PHASEA and PHASEB has occurred 0b1..A simultaneous change of PHASEA and PHASEB has occurred

◆ ENC_CTRL2_SABIRQ [2/2]

#define ENC_CTRL2_SABIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)

SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request 0b0..No simultaneous change of PHASEA and PHASEB has occurred 0b1..A simultaneous change of PHASEA and PHASEB has occurred

◆ ENC_CTRL2_UPDHLD [1/3]

#define ENC_CTRL2_UPDHLD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

UPDHLD - Update Hold Registers 0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal 0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal

◆ ENC_CTRL2_UPDHLD [2/3]

#define ENC_CTRL2_UPDHLD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

UPDHLD - Update Hold Registers 0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal 0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal

◆ ENC_CTRL2_UPDHLD [3/3]

#define ENC_CTRL2_UPDHLD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

UPDHLD - Update Hold Registers 0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal 0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal

◆ ENC_CTRL2_UPDPOS [1/3]

#define ENC_CTRL2_UPDPOS ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

UPDPOS - Update Position Registers 0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER 0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER

◆ ENC_CTRL2_UPDPOS [2/3]

#define ENC_CTRL2_UPDPOS ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

UPDPOS - Update Position Registers 0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER 0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER

◆ ENC_CTRL2_UPDPOS [3/3]

#define ENC_CTRL2_UPDPOS ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

UPDPOS - Update Position Registers 0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER 0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER

◆ PWM_CTRL2_CLK_SEL [1/3]

#define PWM_CTRL2_CLK_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)

CLK_SEL - Clock Source Select 0b00..The IPBus clock is used as the clock for the local prescaler and counter. 0b01..EXT_CLK is used as the clock for the local prescaler and counter. 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. 0b11..reserved

◆ PWM_CTRL2_CLK_SEL [2/3]

#define PWM_CTRL2_CLK_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)

CLK_SEL - Clock Source Select 0b00..The IPBus clock is used as the clock for the local prescaler and counter. 0b01..EXT_CLK is used as the clock for the local prescaler and counter. 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. 0b11..reserved

◆ PWM_CTRL2_CLK_SEL [3/3]

#define PWM_CTRL2_CLK_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)

CLK_SEL - Clock Source Select 0b00..The IPBus clock is used as the clock for the local prescaler and counter. 0b01..EXT_CLK is used as the clock for the local prescaler and counter. 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. 0b11..reserved

◆ PWM_CTRL2_DBGEN [1/3]

#define PWM_CTRL2_DBGEN ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)

DBGEN - Debug Enable

◆ PWM_CTRL2_DBGEN [2/3]

#define PWM_CTRL2_DBGEN ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)

DBGEN - Debug Enable

◆ PWM_CTRL2_DBGEN [3/3]

#define PWM_CTRL2_DBGEN ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)

DBGEN - Debug Enable

◆ PWM_CTRL2_FORCE [1/3]

#define PWM_CTRL2_FORCE ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)

FORCE - Force Initialization

◆ PWM_CTRL2_FORCE [2/3]

#define PWM_CTRL2_FORCE ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)

FORCE - Force Initialization

◆ PWM_CTRL2_FORCE [3/3]

#define PWM_CTRL2_FORCE ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)

FORCE - Force Initialization

◆ PWM_CTRL2_FORCE_SEL [1/3]

#define PWM_CTRL2_FORCE_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)

FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b100..The local sync signal from this submodule is used to force updates. 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.

◆ PWM_CTRL2_FORCE_SEL [2/3]

#define PWM_CTRL2_FORCE_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)

FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b100..The local sync signal from this submodule is used to force updates. 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.

◆ PWM_CTRL2_FORCE_SEL [3/3]

#define PWM_CTRL2_FORCE_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)

FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b100..The local sync signal from this submodule is used to force updates. 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.

◆ PWM_CTRL2_FRCEN [1/3]

#define PWM_CTRL2_FRCEN ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)

FRCEN - FRCEN 0b0..Initialization from a FORCE_OUT is disabled. 0b1..Initialization from a FORCE_OUT is enabled.

◆ PWM_CTRL2_FRCEN [2/3]

#define PWM_CTRL2_FRCEN ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)

FRCEN - FRCEN 0b0..Initialization from a FORCE_OUT is disabled. 0b1..Initialization from a FORCE_OUT is enabled.

◆ PWM_CTRL2_FRCEN [3/3]

#define PWM_CTRL2_FRCEN ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)

FRCEN - FRCEN 0b0..Initialization from a FORCE_OUT is disabled. 0b1..Initialization from a FORCE_OUT is enabled.

◆ PWM_CTRL2_INDEP [1/3]

#define PWM_CTRL2_INDEP ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)

INDEP - Independent or Complementary Pair Operation 0b0..PWM_A and PWM_B form a complementary PWM pair. 0b1..PWM_A and PWM_B outputs are independent PWMs.

◆ PWM_CTRL2_INDEP [2/3]

#define PWM_CTRL2_INDEP ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)

INDEP - Independent or Complementary Pair Operation 0b0..PWM_A and PWM_B form a complementary PWM pair. 0b1..PWM_A and PWM_B outputs are independent PWMs.

◆ PWM_CTRL2_INDEP [3/3]

#define PWM_CTRL2_INDEP ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)

INDEP - Independent or Complementary Pair Operation 0b0..PWM_A and PWM_B form a complementary PWM pair. 0b1..PWM_A and PWM_B outputs are independent PWMs.

◆ PWM_CTRL2_INIT_SEL [1/3]

#define PWM_CTRL2_INIT_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)

INIT_SEL - Initialization Control Select 0b00..Local sync (PWM_X) causes initialization. 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 0b11..EXT_SYNC causes initialization.

◆ PWM_CTRL2_INIT_SEL [2/3]

#define PWM_CTRL2_INIT_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)

INIT_SEL - Initialization Control Select 0b00..Local sync (PWM_X) causes initialization. 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 0b11..EXT_SYNC causes initialization.

◆ PWM_CTRL2_INIT_SEL [3/3]

#define PWM_CTRL2_INIT_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)

INIT_SEL - Initialization Control Select 0b00..Local sync (PWM_X) causes initialization. 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 0b11..EXT_SYNC causes initialization.

◆ PWM_CTRL2_PWM23_INIT [1/3]

#define PWM_CTRL2_PWM23_INIT ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)

PWM23_INIT - PWM23 Initial Value

◆ PWM_CTRL2_PWM23_INIT [2/3]

#define PWM_CTRL2_PWM23_INIT ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)

PWM23_INIT - PWM23 Initial Value

◆ PWM_CTRL2_PWM23_INIT [3/3]

#define PWM_CTRL2_PWM23_INIT ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)

PWM23_INIT - PWM23 Initial Value

◆ PWM_CTRL2_PWM45_INIT [1/3]

#define PWM_CTRL2_PWM45_INIT ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)

PWM45_INIT - PWM45 Initial Value

◆ PWM_CTRL2_PWM45_INIT [2/3]

#define PWM_CTRL2_PWM45_INIT ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)

PWM45_INIT - PWM45 Initial Value

◆ PWM_CTRL2_PWM45_INIT [3/3]

#define PWM_CTRL2_PWM45_INIT ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)

PWM45_INIT - PWM45 Initial Value

◆ PWM_CTRL2_PWMX_INIT [1/3]

#define PWM_CTRL2_PWMX_INIT ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)

PWMX_INIT - PWM_X Initial Value

◆ PWM_CTRL2_PWMX_INIT [2/3]

#define PWM_CTRL2_PWMX_INIT ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)

PWMX_INIT - PWM_X Initial Value

◆ PWM_CTRL2_PWMX_INIT [3/3]

#define PWM_CTRL2_PWMX_INIT ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)

PWMX_INIT - PWM_X Initial Value

◆ PWM_CTRL2_RELOAD_SEL [1/3]

#define PWM_CTRL2_RELOAD_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)

RELOAD_SEL - Reload Source Select 0b0..The local RELOAD signal is used to reload registers. 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.

◆ PWM_CTRL2_RELOAD_SEL [2/3]

#define PWM_CTRL2_RELOAD_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)

RELOAD_SEL - Reload Source Select 0b0..The local RELOAD signal is used to reload registers. 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.

◆ PWM_CTRL2_RELOAD_SEL [3/3]

#define PWM_CTRL2_RELOAD_SEL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)

RELOAD_SEL - Reload Source Select 0b0..The local RELOAD signal is used to reload registers. 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.

◆ PWM_CTRL2_WAITEN [1/3]

#define PWM_CTRL2_WAITEN ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)

WAITEN - WAIT Enable

◆ PWM_CTRL2_WAITEN [2/3]

#define PWM_CTRL2_WAITEN ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)

WAITEN - WAIT Enable

◆ PWM_CTRL2_WAITEN [3/3]

#define PWM_CTRL2_WAITEN ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)

WAITEN - WAIT Enable

Macros

MCR - Module Configuration Register

CTRL1 - Control 1 Register

TIMER - Free Running Timer Register

RXMGMASK - Rx Mailboxes Global Mask Register

RX14MASK - Rx Buffer 14 Mask Register

RX15MASK - Rx Buffer 15 Mask Register

ECR - Error Counter Register

ESR1 - Error and Status 1 Register

IMASK2 - Interrupt Masks 2 Register

IMASK1 - Interrupt Masks 1 Register

IFLAG2 - Interrupt Flags 2 Register

IFLAG1 - Interrupt Flags 1 Register

CTRL2 - Control 2 Register

ESR2 - Error and Status 2 Register

CRCR - CRC Register

RXFGMASK - Rx FIFO Global Mask Register

RXFIR - Rx FIFO Information Register

DBG1 - Debug 1 register

DBG2 - Debug 2 register

CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register

ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register

WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register

WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register

RXIMR - Rx Individual Mask Registers

GFWR - Glitch Filter Width Registers

MCR - Module Configuration register

CTRL1 - Control 1 register

TIMER - Free Running Timer

RXMGMASK - Rx Mailboxes Global Mask register

RX14MASK - Rx 14 Mask register

RX15MASK - Rx 15 Mask register

ECR - Error Counter

ESR1 - Error and Status 1 register

IMASK2 - Interrupt Masks 2 register

IMASK1 - Interrupt Masks 1 register

IFLAG2 - Interrupt Flags 2 register

IFLAG1 - Interrupt Flags 1 register

CTRL2 - Control 2 register

ESR2 - Error and Status 2 register

CRCR - CRC register

RXFGMASK - Rx FIFO Global Mask register

RXFIR - Rx FIFO Information register

CBT - CAN Bit Timing register

CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register

ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register

WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register

WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register

WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register

RXIMR - Rx Individual Mask registers

MECR - Memory Error Control register

ERRIAR - Error Injection Address register

ERRIDPR - Error Injection Data Pattern register

ERRIPPR - Error Injection Parity Pattern register

RERRAR - Error Report Address register

RERRDR - Error Report Data register

RERRSYNR - Error Report Syndrome register

ERRSR - Error Status register

FDCTRL - CAN FD Control register

FDCBT - CAN FD Bit Timing register

FDCRC - CAN FD CRC register

MCR - Module Configuration register

CTRL1 - Control 1 register

TIMER - Free Running Timer

RXMGMASK - Rx Mailboxes Global Mask register

RX14MASK - Rx 14 Mask register

RX15MASK - Rx 15 Mask register

ECR - Error Counter

ESR1 - Error and Status 1 register

IMASK2 - Interrupt Masks 2 register

IMASK1 - Interrupt Masks 1 register

IFLAG2 - Interrupt Flags 2 register

IFLAG1 - Interrupt Flags 1 register

CTRL2 - Control 2 register

ESR2 - Error and Status 2 register

CRCR - CRC register

RXFGMASK - Rx FIFO Global Mask register

RXFIR - Rx FIFO Information register

CBT - CAN Bit Timing register

CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register