RTEMS 6.1-rc4
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Modules | Typedefs | Enumerations | Enumerator | Variables
Iomuxc_pads
Mapping Information

Modules

 Device Peripheral Access Layer
 
 Edma_request
 
 Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
 
 SDK Compatibility
 

Typedefs

typedef enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t
 Enumeration for the IOMUXC SW_MUX_CTL_PAD.
 
typedef enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t
 Enumeration for the IOMUXC SW_PAD_CTL_PAD.
 
typedef enum _iomuxc_select_input iomuxc_select_input_t
 Enumeration for the IOMUXC select input.
 
typedef enum _xbar_input_signal xbar_input_signal_t
 
typedef enum _xbar_output_signal xbar_output_signal_t
 
typedef enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t
 Enumeration for the IOMUXC SW_MUX_CTL_PAD.
 
typedef enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t
 Enumeration for the IOMUXC SW_PAD_CTL_PAD.
 
typedef enum _iomuxc_select_input iomuxc_select_input_t
 Enumeration for the IOMUXC select input.
 
typedef enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t
 Enumeration for the IOMUXC SW_MUX_CTL_PAD.
 
typedef enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t
 Enumeration for the IOMUXC SW_PAD_CTL_PAD.
 
typedef enum _iomuxc_select_input iomuxc_select_input_t
 Enumeration for the IOMUXC select input.
 

Enumerations

enum  _iomuxc_sw_mux_ctl_pad {
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 = 118U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 = 119U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 = 122U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 = 123U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 = 126U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 = 127U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 = 130U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 = 131U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 = 134U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 = 135U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 = 138U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 = 139U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 = 142U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 = 143U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 = 144U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 = 118U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 = 119U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 = 122U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 = 123U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 = 126U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 = 127U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 = 130U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 = 131U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 = 134U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 = 135U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 = 138U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 = 139U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 = 142U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 = 143U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 = 144U
}
 Enumeration for the IOMUXC SW_MUX_CTL_PAD. More...
 
enum  _iomuxc_sw_pad_ctl_pad {
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 = 118U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 = 119U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 = 122U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 = 123U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 = 126U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 = 127U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 = 130U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 = 131U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 = 134U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 = 135U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 = 138U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 = 139U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 = 142U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 = 143U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 = 144U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 = 118U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 = 119U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 = 122U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 = 123U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 = 126U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 = 127U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 = 130U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 = 131U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 = 134U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 = 135U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 = 138U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 = 139U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 = 142U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 = 143U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 = 144U
}
 Enumeration for the IOMUXC SW_PAD_CTL_PAD. More...
 
enum  _iomuxc_select_input {
  kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U , kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U , kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U , kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U ,
  kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U , kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U , kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U , kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U ,
  kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U , kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U , kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U , kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U ,
  kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U , kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U , kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U , kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U ,
  kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U , kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U , kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U , kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U ,
  kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U , kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U , kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U , kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U ,
  kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U , kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U , kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U , kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U ,
  kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U , kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U , kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U , kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U ,
  kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U , kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U , kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U , kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U ,
  kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U , kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U , kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U , kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U ,
  kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U , kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U , kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U , kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U ,
  kIOMUXC_FLEXSPI_A_DQS_SELECT_INPUT = 44U , kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT = 45U , kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT = 46U , kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT = 47U ,
  kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT = 48U , kIOMUXC_FLEXSPI_B_DATA0_SELECT_INPUT = 49U , kIOMUXC_FLEXSPI_B_DATA1_SELECT_INPUT = 50U , kIOMUXC_FLEXSPI_B_DATA2_SELECT_INPUT = 51U ,
  kIOMUXC_FLEXSPI_B_DATA3_SELECT_INPUT = 52U , kIOMUXC_FLEXSPI_A_SCK_SELECT_INPUT = 53U , kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U , kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U ,
  kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U , kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U , kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U , kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U ,
  kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U , kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U , kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U , kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U ,
  kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U , kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U , kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U , kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U ,
  kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U , kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U , kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U , kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U ,
  kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U , kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U , kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U , kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U ,
  kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U , kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U , kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U , kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U ,
  kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U , kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U , kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U , kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U ,
  kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U , kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U , kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U , kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U ,
  kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U , kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U , kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U , kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U ,
  kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U , kIOMUXC_NMI_SELECT_INPUT = 93U , kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U , kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U ,
  kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U , kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U , kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U , kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U ,
  kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U , kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U , kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U , kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U ,
  kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U , kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U , kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U , kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U ,
  kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U , kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U , kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U , kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U ,
  kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U , kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U , kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U , kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U ,
  kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U , kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U , kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U , kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U ,
  kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U , kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U , kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U , kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U ,
  kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U , kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U , kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U , kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U ,
  kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U , kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U , kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U , kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U ,
  kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U , kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U , kIOMUXC_XBAR_INOUT02_SELECT_INPUT = 134U , kIOMUXC_XBAR_INOUT03_SELECT_INPUT = 135U ,
  kIOMUXC_XBAR_INOUT04_SELECT_INPUT = 136U , kIOMUXC_XBAR_INOUT05_SELECT_INPUT = 137U , kIOMUXC_XBAR_INOUT06_SELECT_INPUT = 138U , kIOMUXC_XBAR_INOUT07_SELECT_INPUT = 139U ,
  kIOMUXC_XBAR_INOUT08_SELECT_INPUT = 140U , kIOMUXC_XBAR_INOUT09_SELECT_INPUT = 141U , kIOMUXC_XBAR_INOUT17_SELECT_INPUT = 142U , kIOMUXC_XBAR_INOUT18_SELECT_INPUT = 143U ,
  kIOMUXC_XBAR_INOUT20_SELECT_INPUT = 144U , kIOMUXC_XBAR_INOUT22_SELECT_INPUT = 145U , kIOMUXC_XBAR_INOUT23_SELECT_INPUT = 146U , kIOMUXC_XBAR_INOUT24_SELECT_INPUT = 147U ,
  kIOMUXC_XBAR_INOUT14_SELECT_INPUT = 148U , kIOMUXC_XBAR_INOUT15_SELECT_INPUT = 149U , kIOMUXC_XBAR_INOUT16_SELECT_INPUT = 150U , kIOMUXC_XBAR_INOUT25_SELECT_INPUT = 151U ,
  kIOMUXC_XBAR_INOUT19_SELECT_INPUT = 152U , kIOMUXC_XBAR_INOUT21_SELECT_INPUT = 153U , kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0U , kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 1U ,
  kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 4U , kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 5U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 = 6U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 = 7U ,
  kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT = 8U , kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT = 9U , kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT = 10U , kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT = 11U ,
  kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT = 12U , kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT = 13U , kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT = 14U , kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT = 15U ,
  kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT = 16U , kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT = 17U , kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT = 18U , kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT = 19U ,
  kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT = 20U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 26U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 27U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 28U ,
  kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 29U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 30U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 31U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 = 32U ,
  kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 = 33U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 = 34U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 = 35U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 = 36U ,
  kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 = 37U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 = 38U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 = 39U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 = 40U ,
  kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 = 41U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 = 42U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 = 43U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 = 44U ,
  kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 = 45U , kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT = 46U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 = 47U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 = 48U ,
  kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 = 49U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 = 50U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 = 51U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 = 52U ,
  kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 = 53U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 = 54U , kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT = 55U , kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT = 56U ,
  kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 = 57U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 = 58U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 = 59U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 = 60U ,
  kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT = 61U , kIOMUXC_GPT3_CAPIN1_SELECT_INPUT = 62U , kIOMUXC_GPT3_CAPIN2_SELECT_INPUT = 63U , kIOMUXC_GPT3_CLKIN_SELECT_INPUT = 64U ,
  kIOMUXC_KPP_COL_SELECT_INPUT_6 = 65U , kIOMUXC_KPP_COL_SELECT_INPUT_7 = 66U , kIOMUXC_KPP_ROW_SELECT_INPUT_6 = 67U , kIOMUXC_KPP_ROW_SELECT_INPUT_7 = 68U ,
  kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT = 69U , kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT = 70U , kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT = 71U , kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT = 72U ,
  kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT = 73U , kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT = 74U , kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT = 75U , kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT = 76U ,
  kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 = 77U , kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT = 78U , kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT = 79U , kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT = 80U ,
  kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 = 81U , kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 = 82U , kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT = 83U , kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT = 84U ,
  kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT = 85U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 = 86U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 = 87U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 = 88U ,
  kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 = 89U , kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT = 90U , kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT = 91U , kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT = 92U ,
  kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 = 93U , kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT = 94U , kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT = 95U , kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT = 96U ,
  kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT = 97U , kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT = 98U , kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT = 99U , kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT = 100U ,
  kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT = 101U , kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT = 102U , kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT = 103U , kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT = 104U ,
  kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 105U , kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 106U , kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 107U , kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 108U ,
  kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 109U , kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 110U , kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 111U , kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 112U ,
  kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 113U , kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 114U , kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 115U , kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 116U ,
  kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 117U , kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT = 118U , kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 = 119U , kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT = 120U ,
  kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT = 121U , kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT = 122U , kIOMUXC_EMVSIM1_SIO_SELECT_INPUT = 129U , kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT = 130U ,
  kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT = 131U , kIOMUXC_EMVSIM2_SIO_SELECT_INPUT = 132U , kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT = 133U , kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT = 134U ,
  kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 135U , kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 136U , kIOMUXC_USB_OTG_OC_SELECT_INPUT = 137U , kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 138U ,
  kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 139U , kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 140U , kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 141U , kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 142U ,
  kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 143U , kIOMUXC_XBAR1_IN_SELECT_INPUT_20 = 144U , kIOMUXC_XBAR1_IN_SELECT_INPUT_21 = 145U , kIOMUXC_XBAR1_IN_SELECT_INPUT_22 = 146U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_23 = 147U , kIOMUXC_XBAR1_IN_SELECT_INPUT_24 = 148U , kIOMUXC_XBAR1_IN_SELECT_INPUT_25 = 149U , kIOMUXC_XBAR1_IN_SELECT_INPUT_26 = 150U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_27 = 151U , kIOMUXC_XBAR1_IN_SELECT_INPUT_28 = 152U , kIOMUXC_XBAR1_IN_SELECT_INPUT_29 = 153U , kIOMUXC_XBAR1_IN_SELECT_INPUT_30 = 154U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_31 = 155U , kIOMUXC_XBAR1_IN_SELECT_INPUT_32 = 156U , kIOMUXC_XBAR1_IN_SELECT_INPUT_33 = 157U , kIOMUXC_XBAR1_IN_SELECT_INPUT_34 = 158U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_35 = 159U , kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0U , kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 1U , kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 4U ,
  kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 5U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 = 6U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 = 7U , kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT = 8U ,
  kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT = 9U , kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT = 10U , kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT = 11U , kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT = 12U ,
  kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT = 13U , kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT = 14U , kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT = 15U , kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT = 16U ,
  kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT = 17U , kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT = 18U , kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT = 19U , kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT = 20U ,
  kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 26U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 27U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 28U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 29U ,
  kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 30U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 31U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 = 32U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 = 33U ,
  kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 = 34U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 = 35U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 = 36U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 = 37U ,
  kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 = 38U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 = 39U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 = 40U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 = 41U ,
  kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 = 42U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 = 43U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 = 44U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 = 45U ,
  kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT = 46U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 = 47U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 = 48U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 = 49U ,
  kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 = 50U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 = 51U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 = 52U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 = 53U ,
  kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 = 54U , kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT = 55U , kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT = 56U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 = 57U ,
  kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 = 58U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 = 59U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 = 60U , kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT = 61U ,
  kIOMUXC_GPT3_CAPIN1_SELECT_INPUT = 62U , kIOMUXC_GPT3_CAPIN2_SELECT_INPUT = 63U , kIOMUXC_GPT3_CLKIN_SELECT_INPUT = 64U , kIOMUXC_KPP_COL_SELECT_INPUT_6 = 65U ,
  kIOMUXC_KPP_COL_SELECT_INPUT_7 = 66U , kIOMUXC_KPP_ROW_SELECT_INPUT_6 = 67U , kIOMUXC_KPP_ROW_SELECT_INPUT_7 = 68U , kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT = 69U ,
  kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT = 70U , kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT = 71U , kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT = 72U , kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT = 73U ,
  kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT = 74U , kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT = 75U , kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT = 76U , kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 = 77U ,
  kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT = 78U , kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT = 79U , kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT = 80U , kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 = 81U ,
  kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 = 82U , kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT = 83U , kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT = 84U , kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT = 85U ,
  kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 = 86U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 = 87U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 = 88U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 = 89U ,
  kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT = 90U , kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT = 91U , kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT = 92U , kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 = 93U ,
  kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT = 94U , kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT = 95U , kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT = 96U , kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT = 97U ,
  kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT = 98U , kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT = 99U , kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT = 100U , kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT = 101U ,
  kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT = 102U , kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT = 103U , kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT = 104U , kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 105U ,
  kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 106U , kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 107U , kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 108U , kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 109U ,
  kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 110U , kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 111U , kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 112U , kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 113U ,
  kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 114U , kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 115U , kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 116U , kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 117U ,
  kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT = 118U , kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 = 119U , kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT = 120U , kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT = 121U ,
  kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT = 122U , kIOMUXC_EMVSIM1_SIO_SELECT_INPUT = 129U , kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT = 130U , kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT = 131U ,
  kIOMUXC_EMVSIM2_SIO_SELECT_INPUT = 132U , kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT = 133U , kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT = 134U , kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 135U ,
  kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 136U , kIOMUXC_USB_OTG_OC_SELECT_INPUT = 137U , kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 138U , kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 139U ,
  kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 140U , kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 141U , kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 142U , kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 143U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_20 = 144U , kIOMUXC_XBAR1_IN_SELECT_INPUT_21 = 145U , kIOMUXC_XBAR1_IN_SELECT_INPUT_22 = 146U , kIOMUXC_XBAR1_IN_SELECT_INPUT_23 = 147U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_24 = 148U , kIOMUXC_XBAR1_IN_SELECT_INPUT_25 = 149U , kIOMUXC_XBAR1_IN_SELECT_INPUT_26 = 150U , kIOMUXC_XBAR1_IN_SELECT_INPUT_27 = 151U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_28 = 152U , kIOMUXC_XBAR1_IN_SELECT_INPUT_29 = 153U , kIOMUXC_XBAR1_IN_SELECT_INPUT_30 = 154U , kIOMUXC_XBAR1_IN_SELECT_INPUT_31 = 155U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_32 = 156U , kIOMUXC_XBAR1_IN_SELECT_INPUT_33 = 157U , kIOMUXC_XBAR1_IN_SELECT_INPUT_34 = 158U , kIOMUXC_XBAR1_IN_SELECT_INPUT_35 = 159U
}
 Enumeration for the IOMUXC select input. More...
 
enum  _xbar_input_signal {
  kXBARA1_InputLogicLow = 0|0x100U , kXBARA1_InputLogicHigh = 1|0x100U , kXBARA1_InputIomuxXbarIn02 = 2|0x100U , kXBARA1_InputIomuxXbarIn03 = 3|0x100U ,
  kXBARA1_InputIomuxXbarInout04 = 4|0x100U , kXBARA1_InputIomuxXbarInout05 = 5|0x100U , kXBARA1_InputIomuxXbarInout06 = 6|0x100U , kXBARA1_InputIomuxXbarInout07 = 7|0x100U ,
  kXBARA1_InputIomuxXbarInout08 = 8|0x100U , kXBARA1_InputIomuxXbarInout09 = 9|0x100U , kXBARA1_InputIomuxXbarInout10 = 10|0x100U , kXBARA1_InputIomuxXbarInout11 = 11|0x100U ,
  kXBARA1_InputIomuxXbarInout12 = 12|0x100U , kXBARA1_InputIomuxXbarInout13 = 13|0x100U , kXBARA1_InputIomuxXbarInout14 = 14|0x100U , kXBARA1_InputIomuxXbarInout15 = 15|0x100U ,
  kXBARA1_InputIomuxXbarInout16 = 16|0x100U , kXBARA1_InputIomuxXbarInout17 = 17|0x100U , kXBARA1_InputIomuxXbarInout18 = 18|0x100U , kXBARA1_InputIomuxXbarInout19 = 19|0x100U ,
  kXBARA1_InputIomuxXbarIn20 = 20|0x100U , kXBARA1_InputIomuxXbarIn21 = 21|0x100U , kXBARA1_InputIomuxXbarIn22 = 22|0x100U , kXBARA1_InputIomuxXbarIn23 = 23|0x100U ,
  kXBARA1_InputIomuxXbarIn24 = 24|0x100U , kXBARA1_InputIomuxXbarIn25 = 25|0x100U , kXBARA1_InputAcmp1Out = 26|0x100U , kXBARA1_InputAcmp2Out = 27|0x100U ,
  kXBARA1_InputAcmp3Out = 28|0x100U , kXBARA1_InputAcmp4Out = 29|0x100U , kXBARA1_InputRESERVED30 = 30|0x100U , kXBARA1_InputRESERVED31 = 31|0x100U ,
  kXBARA1_InputQtimer3Tmr0Output = 32|0x100U , kXBARA1_InputQtimer3Tmr1Output = 33|0x100U , kXBARA1_InputQtimer3Tmr2Output = 34|0x100U , kXBARA1_InputQtimer3Tmr3Output = 35|0x100U ,
  kXBARA1_InputQtimer4Tmr0Output = 36|0x100U , kXBARA1_InputQtimer4Tmr1Output = 37|0x100U , kXBARA1_InputQtimer4Tmr2Output = 38|0x100U , kXBARA1_InputQtimer4Tmr3Output = 39|0x100U ,
  kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U , kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U , kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U , kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U ,
  kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U , kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U , kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U , kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U ,
  kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U , kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U , kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U , kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U ,
  kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U , kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U , kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U , kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U ,
  kXBARA1_InputPitTrigger0 = 56|0x100U , kXBARA1_InputPitTrigger1 = 57|0x100U , kXBARA1_InputPitTrigger2 = 58|0x100U , kXBARA1_InputPitTrigger3 = 59|0x100U ,
  kXBARA1_InputEnc1PosMatch = 60|0x100U , kXBARA1_InputEnc2PosMatch = 61|0x100U , kXBARA1_InputEnc3PosMatch = 62|0x100U , kXBARA1_InputEnc4PosMatch = 63|0x100U ,
  kXBARA1_InputDmaDone0 = 64|0x100U , kXBARA1_InputDmaDone1 = 65|0x100U , kXBARA1_InputDmaDone2 = 66|0x100U , kXBARA1_InputDmaDone3 = 67|0x100U ,
  kXBARA1_InputDmaDone4 = 68|0x100U , kXBARA1_InputDmaDone5 = 69|0x100U , kXBARA1_InputDmaDone6 = 70|0x100U , kXBARA1_InputDmaDone7 = 71|0x100U ,
  kXBARA1_InputAoi1Out0 = 72|0x100U , kXBARA1_InputAoi1Out1 = 73|0x100U , kXBARA1_InputAoi1Out2 = 74|0x100U , kXBARA1_InputAoi1Out3 = 75|0x100U ,
  kXBARA1_InputAoi2Out0 = 76|0x100U , kXBARA1_InputAoi2Out1 = 77|0x100U , kXBARA1_InputAoi2Out2 = 78|0x100U , kXBARA1_InputAoi2Out3 = 79|0x100U ,
  kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U , kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U , kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U , kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U ,
  kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U , kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U , kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U , kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U ,
  kXBARB2_InputLogicLow = 0|0x200U , kXBARB2_InputLogicHigh = 1|0x200U , kXBARB2_InputRESERVED2 = 2|0x200U , kXBARB2_InputRESERVED3 = 3|0x200U ,
  kXBARB2_InputRESERVED4 = 4|0x200U , kXBARB2_InputRESERVED5 = 5|0x200U , kXBARB2_InputAcmp1Out = 6|0x200U , kXBARB2_InputAcmp2Out = 7|0x200U ,
  kXBARB2_InputAcmp3Out = 8|0x200U , kXBARB2_InputAcmp4Out = 9|0x200U , kXBARB2_InputRESERVED10 = 10|0x200U , kXBARB2_InputRESERVED11 = 11|0x200U ,
  kXBARB2_InputQtimer3Tmr0Output = 12|0x200U , kXBARB2_InputQtimer3Tmr1Output = 13|0x200U , kXBARB2_InputQtimer3Tmr2Output = 14|0x200U , kXBARB2_InputQtimer3Tmr3Output = 15|0x200U ,
  kXBARB2_InputQtimer4Tmr0Output = 16|0x200U , kXBARB2_InputQtimer4Tmr1Output = 17|0x200U , kXBARB2_InputQtimer4Tmr2Output = 18|0x200U , kXBARB2_InputQtimer4Tmr3Output = 19|0x200U ,
  kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U , kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U , kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U , kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U ,
  kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U , kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U , kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U , kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U ,
  kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U , kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U , kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U , kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U ,
  kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U , kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U , kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U , kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U ,
  kXBARB2_InputPitTrigger0 = 36|0x200U , kXBARB2_InputPitTrigger1 = 37|0x200U , kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U , kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U ,
  kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U , kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U , kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U , kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U ,
  kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U , kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U , kXBARB2_InputEnc1PosMatch = 46|0x200U , kXBARB2_InputEnc2PosMatch = 47|0x200U ,
  kXBARB2_InputEnc3PosMatch = 48|0x200U , kXBARB2_InputEnc4PosMatch = 49|0x200U , kXBARB2_InputDmaDone0 = 50|0x200U , kXBARB2_InputDmaDone1 = 51|0x200U ,
  kXBARB2_InputDmaDone2 = 52|0x200U , kXBARB2_InputDmaDone3 = 53|0x200U , kXBARB2_InputDmaDone4 = 54|0x200U , kXBARB2_InputDmaDone5 = 55|0x200U ,
  kXBARB2_InputDmaDone6 = 56|0x200U , kXBARB2_InputDmaDone7 = 57|0x200U , kXBARB3_InputLogicLow = 0|0x300U , kXBARB3_InputLogicHigh = 1|0x300U ,
  kXBARB3_InputRESERVED2 = 2|0x300U , kXBARB3_InputRESERVED3 = 3|0x300U , kXBARB3_InputRESERVED4 = 4|0x300U , kXBARB3_InputRESERVED5 = 5|0x300U ,
  kXBARB3_InputAcmp1Out = 6|0x300U , kXBARB3_InputAcmp2Out = 7|0x300U , kXBARB3_InputAcmp3Out = 8|0x300U , kXBARB3_InputAcmp4Out = 9|0x300U ,
  kXBARB3_InputRESERVED10 = 10|0x300U , kXBARB3_InputRESERVED11 = 11|0x300U , kXBARB3_InputQtimer3Tmr0Output = 12|0x300U , kXBARB3_InputQtimer3Tmr1Output = 13|0x300U ,
  kXBARB3_InputQtimer3Tmr2Output = 14|0x300U , kXBARB3_InputQtimer3Tmr3Output = 15|0x300U , kXBARB3_InputQtimer4Tmr0Output = 16|0x300U , kXBARB3_InputQtimer4Tmr1Output = 17|0x300U ,
  kXBARB3_InputQtimer4Tmr2Output = 18|0x300U , kXBARB3_InputQtimer4Tmr3Output = 19|0x300U , kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U , kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U ,
  kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U , kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U , kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U , kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U ,
  kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U , kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U , kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U , kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U ,
  kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U , kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U , kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U , kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U ,
  kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U , kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U , kXBARB3_InputPitTrigger0 = 36|0x300U , kXBARB3_InputPitTrigger1 = 37|0x300U ,
  kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U , kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U , kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U , kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U ,
  kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U , kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U , kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U , kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U ,
  kXBARB3_InputEnc1PosMatch = 46|0x300U , kXBARB3_InputEnc2PosMatch = 47|0x300U , kXBARB3_InputEnc3PosMatch = 48|0x300U , kXBARB3_InputEnc4PosMatch = 49|0x300U ,
  kXBARB3_InputDmaDone0 = 50|0x300U , kXBARB3_InputDmaDone1 = 51|0x300U , kXBARB3_InputDmaDone2 = 52|0x300U , kXBARB3_InputDmaDone3 = 53|0x300U ,
  kXBARB3_InputDmaDone4 = 54|0x300U , kXBARB3_InputDmaDone5 = 55|0x300U , kXBARB3_InputDmaDone6 = 56|0x300U , kXBARB3_InputDmaDone7 = 57|0x300U ,
  kXBARA1_InputLogicLow = 0|0x100U , kXBARA1_InputLogicHigh = 1|0x100U , kXBARA1_InputRESERVED2 = 2|0x100U , kXBARA1_InputRESERVED3 = 3|0x100U ,
  kXBARA1_InputIomuxXbarInout04 = 4|0x100U , kXBARA1_InputIomuxXbarInout05 = 5|0x100U , kXBARA1_InputIomuxXbarInout06 = 6|0x100U , kXBARA1_InputIomuxXbarInout07 = 7|0x100U ,
  kXBARA1_InputIomuxXbarInout08 = 8|0x100U , kXBARA1_InputIomuxXbarInout09 = 9|0x100U , kXBARA1_InputIomuxXbarInout10 = 10|0x100U , kXBARA1_InputIomuxXbarInout11 = 11|0x100U ,
  kXBARA1_InputIomuxXbarInout12 = 12|0x100U , kXBARA1_InputIomuxXbarInout13 = 13|0x100U , kXBARA1_InputIomuxXbarInout14 = 14|0x100U , kXBARA1_InputIomuxXbarInout15 = 15|0x100U ,
  kXBARA1_InputIomuxXbarInout16 = 16|0x100U , kXBARA1_InputIomuxXbarInout17 = 17|0x100U , kXBARA1_InputIomuxXbarInout18 = 18|0x100U , kXBARA1_InputIomuxXbarInout19 = 19|0x100U ,
  kXBARA1_InputIomuxXbarInout20 = 20|0x100U , kXBARA1_InputIomuxXbarInout21 = 21|0x100U , kXBARA1_InputIomuxXbarInout22 = 22|0x100U , kXBARA1_InputIomuxXbarInout23 = 23|0x100U ,
  kXBARA1_InputIomuxXbarInout24 = 24|0x100U , kXBARA1_InputIomuxXbarInout25 = 25|0x100U , kXBARA1_InputIomuxXbarInout26 = 26|0x100U , kXBARA1_InputIomuxXbarInout27 = 27|0x100U ,
  kXBARA1_InputIomuxXbarInout28 = 28|0x100U , kXBARA1_InputIomuxXbarInout29 = 29|0x100U , kXBARA1_InputIomuxXbarInout30 = 30|0x100U , kXBARA1_InputIomuxXbarInout31 = 31|0x100U ,
  kXBARA1_InputIomuxXbarInout32 = 32|0x100U , kXBARA1_InputIomuxXbarInout33 = 33|0x100U , kXBARA1_InputIomuxXbarInout34 = 34|0x100U , kXBARA1_InputIomuxXbarInout35 = 35|0x100U ,
  kXBARA1_InputIomuxXbarInout36 = 36|0x100U , kXBARA1_InputIomuxXbarInout37 = 37|0x100U , kXBARA1_InputIomuxXbarInout38 = 38|0x100U , kXBARA1_InputIomuxXbarInout39 = 39|0x100U ,
  kXBARA1_InputIomuxXbarInout40 = 40|0x100U , kXBARA1_InputRESERVED41 = 41|0x100U , kXBARA1_InputAcmp1Out = 42|0x100U , kXBARA1_InputAcmp2Out = 43|0x100U ,
  kXBARA1_InputAcmp3Out = 44|0x100U , kXBARA1_InputAcmp4Out = 45|0x100U , kXBARA1_InputRESERVED46 = 46|0x100U , kXBARA1_InputRESERVED47 = 47|0x100U ,
  kXBARA1_InputRESERVED48 = 48|0x100U , kXBARA1_InputRESERVED49 = 49|0x100U , kXBARA1_InputQtimer1Timer0 = 50|0x100U , kXBARA1_InputQtimer1Timer1 = 51|0x100U ,
  kXBARA1_InputQtimer1Timer2 = 52|0x100U , kXBARA1_InputQtimer1Timer3 = 53|0x100U , kXBARA1_InputQtimer2Timer0 = 54|0x100U , kXBARA1_InputQtimer2Timer1 = 55|0x100U ,
  kXBARA1_InputQtimer2Timer2 = 56|0x100U , kXBARA1_InputQtimer2Timer3 = 57|0x100U , kXBARA1_InputQtimer3Timer0 = 58|0x100U , kXBARA1_InputQtimer3Timer1 = 59|0x100U ,
  kXBARA1_InputQtimer3Timer2 = 60|0x100U , kXBARA1_InputQtimer3Timer3 = 61|0x100U , kXBARA1_InputQtimer4Timer0 = 62|0x100U , kXBARA1_InputQtimer4Timer1 = 63|0x100U ,
  kXBARA1_InputQtimer4Timer2 = 64|0x100U , kXBARA1_InputQtimer4Timer3 = 65|0x100U , kXBARA1_InputRESERVED66 = 66|0x100U , kXBARA1_InputRESERVED67 = 67|0x100U ,
  kXBARA1_InputRESERVED68 = 68|0x100U , kXBARA1_InputRESERVED69 = 69|0x100U , kXBARA1_InputRESERVED70 = 70|0x100U , kXBARA1_InputRESERVED71 = 71|0x100U ,
  kXBARA1_InputRESERVED72 = 72|0x100U , kXBARA1_InputRESERVED73 = 73|0x100U , kXBARA1_InputFlexpwm1Pwm0OutTrig0 = 74|0x100U , kXBARA1_InputFlexpwm1Pwm0OutTrig1 = 75|0x100U ,
  kXBARA1_InputFlexpwm1Pwm1OutTrig0 = 76|0x100U , kXBARA1_InputFlexpwm1Pwm1OutTrig1 = 77|0x100U , kXBARA1_InputFlexpwm1Pwm2OutTrig0 = 78|0x100U , kXBARA1_InputFlexpwm1Pwm2OutTrig1 = 79|0x100U ,
  kXBARA1_InputFlexpwm1Pwm3OutTrig0 = 80|0x100U , kXBARA1_InputFlexpwm1Pwm3OutTrig1 = 81|0x100U , kXBARA1_InputFlexpwm2Pwm0OutTrig01 = 82|0x100U , kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 83|0x100U ,
  kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 84|0x100U , kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 85|0x100U , kXBARA1_InputFlexpwm3Pwm0OutTrig01 = 86|0x100U , kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 87|0x100U ,
  kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 88|0x100U , kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 89|0x100U , kXBARA1_InputFlexpwm4Pwm0OutTrig01 = 90|0x100U , kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 91|0x100U ,
  kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 92|0x100U , kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 93|0x100U , kXBARA1_InputRESERVED94 = 94|0x100U , kXBARA1_InputRESERVED95 = 95|0x100U ,
  kXBARA1_InputRESERVED96 = 96|0x100U , kXBARA1_InputRESERVED97 = 97|0x100U , kXBARA1_InputRESERVED98 = 98|0x100U , kXBARA1_InputRESERVED99 = 99|0x100U ,
  kXBARA1_InputRESERVED100 = 100|0x100U , kXBARA1_InputRESERVED101 = 101|0x100U , kXBARA1_InputPit1Trigger0 = 102|0x100U , kXBARA1_InputPit1Trigger1 = 103|0x100U ,
  kXBARA1_InputPit1Trigger2 = 104|0x100U , kXBARA1_InputPit1Trigger3 = 105|0x100U , kXBARA1_InputDec1PosMatch = 106|0x100U , kXBARA1_InputDec2PosMatch = 107|0x100U ,
  kXBARA1_InputDec3PosMatch = 108|0x100U , kXBARA1_InputDec4PosMatch = 109|0x100U , kXBARA1_InputRESERVED110 = 110|0x100U , kXBARA1_InputRESERVED111 = 111|0x100U ,
  kXBARA1_InputDmaDone0 = 112|0x100U , kXBARA1_InputDmaDone1 = 113|0x100U , kXBARA1_InputDmaDone2 = 114|0x100U , kXBARA1_InputDmaDone3 = 115|0x100U ,
  kXBARA1_InputDmaDone4 = 116|0x100U , kXBARA1_InputDmaDone5 = 117|0x100U , kXBARA1_InputDmaDone6 = 118|0x100U , kXBARA1_InputDmaDone7 = 119|0x100U ,
  kXBARA1_InputDmaLpsrDone0 = 120|0x100U , kXBARA1_InputDmaLpsrDone1 = 121|0x100U , kXBARA1_InputDmaLpsrDone2 = 122|0x100U , kXBARA1_InputDmaLpsrDone3 = 123|0x100U ,
  kXBARA1_InputDmaLpsrDone4 = 124|0x100U , kXBARA1_InputDmaLpsrDone5 = 125|0x100U , kXBARA1_InputDmaLpsrDone6 = 126|0x100U , kXBARA1_InputDmaLpsrDone7 = 127|0x100U ,
  kXBARA1_InputAoi1Out0 = 128|0x100U , kXBARA1_InputAoi1Out1 = 129|0x100U , kXBARA1_InputAoi1Out2 = 130|0x100U , kXBARA1_InputAoi1Out3 = 131|0x100U ,
  kXBARA1_InputAoi2Out0 = 132|0x100U , kXBARA1_InputAoi2Out1 = 133|0x100U , kXBARA1_InputAoi2Out2 = 134|0x100U , kXBARA1_InputAoi2Out3 = 135|0x100U ,
  kXBARA1_InputAdcEtc0Coco0 = 136|0x100U , kXBARA1_InputAdcEtc0Coco1 = 137|0x100U , kXBARA1_InputAdcEtc0Coco2 = 138|0x100U , kXBARA1_InputAdcEtc0Coco3 = 139|0x100U ,
  kXBARA1_InputAdcEtc1Coco0 = 140|0x100U , kXBARA1_InputAdcEtc1Coco1 = 141|0x100U , kXBARA1_InputAdcEtc1Coco2 = 142|0x100U , kXBARA1_InputAdcEtc1Coco3 = 143|0x100U ,
  kXBARB2_InputLogicLow = 0|0x200U , kXBARB2_InputLogicHigh = 1|0x200U , kXBARB2_InputAcmp1Out = 2|0x200U , kXBARB2_InputAcmp2Out = 3|0x200U ,
  kXBARB2_InputAcmp3Out = 4|0x200U , kXBARB2_InputAcmp4Out = 5|0x200U , kXBARB2_InputRESERVED6 = 6|0x200U , kXBARB2_InputRESERVED7 = 7|0x200U ,
  kXBARB2_InputRESERVED8 = 8|0x200U , kXBARB2_InputRESERVED9 = 9|0x200U , kXBARB2_InputQtimer1Timer0 = 10|0x200U , kXBARB2_InputQtimer1Timer1 = 11|0x200U ,
  kXBARB2_InputQtimer1Timer2 = 12|0x200U , kXBARB2_InputQtimer1Timer3 = 13|0x200U , kXBARB2_InputQtimer2Timer0 = 14|0x200U , kXBARB2_InputQtimer2Timer1 = 15|0x200U ,
  kXBARB2_InputQtimer2Timer2 = 16|0x200U , kXBARB2_InputQtimer2Timer3 = 17|0x200U , kXBARB2_InputQtimer3Timer0 = 18|0x200U , kXBARB2_InputQtimer3Timer1 = 19|0x200U ,
  kXBARB2_InputQtimer3Timer2 = 20|0x200U , kXBARB2_InputQtimer3Timer3 = 21|0x200U , kXBARB2_InputQtimer4Timer0 = 22|0x200U , kXBARB2_InputQtimer4Timer1 = 23|0x200U ,
  kXBARB2_InputQtimer4Timer2 = 24|0x200U , kXBARB2_InputQtimer4Timer3 = 25|0x200U , kXBARB2_InputRESERVED26 = 26|0x200U , kXBARB2_InputRESERVED27 = 27|0x200U ,
  kXBARB2_InputRESERVED28 = 28|0x200U , kXBARB2_InputRESERVED29 = 29|0x200U , kXBARB2_InputRESERVED30 = 30|0x200U , kXBARB2_InputRESERVED31 = 31|0x200U ,
  kXBARB2_InputRESERVED32 = 32|0x200U , kXBARB2_InputRESERVED33 = 33|0x200U , kXBARB2_InputFlexpwm1Pwm0OutTrig01 = 34|0x200U , kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 35|0x200U ,
  kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 36|0x200U , kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 37|0x200U , kXBARB2_InputFlexpwm2Pwm0OutTrig01 = 38|0x200U , kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 39|0x200U ,
  kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 40|0x200U , kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 41|0x200U , kXBARB2_InputFlexpwm3Pwm0OutTrig01 = 42|0x200U , kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 43|0x200U ,
  kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 44|0x200U , kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 45|0x200U , kXBARB2_InputFlexpwm4Pwm0OutTrig01 = 46|0x200U , kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 47|0x200U ,
  kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 48|0x200U , kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 49|0x200U , kXBARB2_InputRESERVED50 = 50|0x200U , kXBARB2_InputRESERVED51 = 51|0x200U ,
  kXBARB2_InputRESERVED52 = 52|0x200U , kXBARB2_InputRESERVED53 = 53|0x200U , kXBARB2_InputRESERVED54 = 54|0x200U , kXBARB2_InputRESERVED55 = 55|0x200U ,
  kXBARB2_InputRESERVED56 = 56|0x200U , kXBARB2_InputRESERVED57 = 57|0x200U , kXBARB2_InputPit1Trigger0 = 58|0x200U , kXBARB2_InputPit1Trigger1 = 59|0x200U ,
  kXBARB2_InputAdcEtc0Coco0 = 60|0x200U , kXBARB2_InputAdcEtc0Coco1 = 61|0x200U , kXBARB2_InputAdcEtc0Coco2 = 62|0x200U , kXBARB2_InputAdcEtc0Coco3 = 63|0x200U ,
  kXBARB2_InputAdcEtc1Coco0 = 64|0x200U , kXBARB2_InputAdcEtc1Coco1 = 65|0x200U , kXBARB2_InputAdcEtc1Coco2 = 66|0x200U , kXBARB2_InputAdcEtc1Coco3 = 67|0x200U ,
  kXBARB2_InputRESERVED68 = 68|0x200U , kXBARB2_InputRESERVED69 = 69|0x200U , kXBARB2_InputRESERVED70 = 70|0x200U , kXBARB2_InputRESERVED71 = 71|0x200U ,
  kXBARB2_InputRESERVED72 = 72|0x200U , kXBARB2_InputRESERVED73 = 73|0x200U , kXBARB2_InputRESERVED74 = 74|0x200U , kXBARB2_InputRESERVED75 = 75|0x200U ,
  kXBARB2_InputDec1PosMatch = 76|0x200U , kXBARB2_InputDec2PosMatch = 77|0x200U , kXBARB2_InputDec3PosMatch = 78|0x200U , kXBARB2_InputDec4PosMatch = 79|0x200U ,
  kXBARB2_InputRESERVED80 = 80|0x200U , kXBARB2_InputRESERVED81 = 81|0x200U , kXBARB2_InputDmaDone0 = 82|0x200U , kXBARB2_InputDmaDone1 = 83|0x200U ,
  kXBARB2_InputDmaDone2 = 84|0x200U , kXBARB2_InputDmaDone3 = 85|0x200U , kXBARB2_InputDmaDone4 = 86|0x200U , kXBARB2_InputDmaDone5 = 87|0x200U ,
  kXBARB2_InputDmaDone6 = 88|0x200U , kXBARB2_InputDmaDone7 = 89|0x200U , kXBARB2_InputDmaLpsrDone0 = 90|0x200U , kXBARB2_InputDmaLpsrDone1 = 91|0x200U ,
  kXBARB2_InputDmaLpsrDone2 = 92|0x200U , kXBARB2_InputDmaLpsrDone3 = 93|0x200U , kXBARB2_InputDmaLpsrDone4 = 94|0x200U , kXBARB2_InputDmaLpsrDone5 = 95|0x200U ,
  kXBARB2_InputDmaLpsrDone6 = 96|0x200U , kXBARB2_InputDmaLpsrDone7 = 97|0x200U , kXBARB3_InputLogicLow = 0|0x300U , kXBARB3_InputLogicHigh = 1|0x300U ,
  kXBARB3_InputAcmp1Out = 2|0x300U , kXBARB3_InputAcmp2Out = 3|0x300U , kXBARB3_InputAcmp3Out = 4|0x300U , kXBARB3_InputAcmp4Out = 5|0x300U ,
  kXBARB3_InputRESERVED6 = 6|0x300U , kXBARB3_InputRESERVED7 = 7|0x300U , kXBARB3_InputRESERVED8 = 8|0x300U , kXBARB3_InputRESERVED9 = 9|0x300U ,
  kXBARB3_InputQtimer1Timer0 = 10|0x300U , kXBARB3_InputQtimer1Timer1 = 11|0x300U , kXBARB3_InputQtimer1Timer2 = 12|0x300U , kXBARB3_InputQtimer1Timer3 = 13|0x300U ,
  kXBARB3_InputQtimer2Timer0 = 14|0x300U , kXBARB3_InputQtimer2Timer1 = 15|0x300U , kXBARB3_InputQtimer2Timer2 = 16|0x300U , kXBARB3_InputQtimer2Timer3 = 17|0x300U ,
  kXBARB3_InputQtimer3Timer0 = 18|0x300U , kXBARB3_InputQtimer3Timer1 = 19|0x300U , kXBARB3_InputQtimer3Timer2 = 20|0x300U , kXBARB3_InputQtimer3Timer3 = 21|0x300U ,
  kXBARB3_InputQtimer4Timer0 = 22|0x300U , kXBARB3_InputQtimer4Timer1 = 23|0x300U , kXBARB3_InputQtimer4Timer2 = 24|0x300U , kXBARB3_InputQtimer4Timer3 = 25|0x300U ,
  kXBARB3_InputRESERVED26 = 26|0x300U , kXBARB3_InputRESERVED27 = 27|0x300U , kXBARB3_InputRESERVED28 = 28|0x300U , kXBARB3_InputRESERVED29 = 29|0x300U ,
  kXBARB3_InputRESERVED30 = 30|0x300U , kXBARB3_InputRESERVED31 = 31|0x300U , kXBARB3_InputRESERVED32 = 32|0x300U , kXBARB3_InputRESERVED33 = 33|0x300U ,
  kXBARB3_InputFlexpwm1Pwm0OutTrig01 = 34|0x300U , kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 35|0x300U , kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 36|0x300U , kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 37|0x300U ,
  kXBARB3_InputFlexpwm2Pwm0OutTrig01 = 38|0x300U , kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 39|0x300U , kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 40|0x300U , kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 41|0x300U ,
  kXBARB3_InputFlexpwm3Pwm0OutTrig01 = 42|0x300U , kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 43|0x300U , kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 44|0x300U , kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 45|0x300U ,
  kXBARB3_InputFlexpwm4Pwm0OutTrig01 = 46|0x300U , kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 47|0x300U , kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 48|0x300U , kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 49|0x300U ,
  kXBARB3_InputRESERVED50 = 50|0x300U , kXBARB3_InputRESERVED51 = 51|0x300U , kXBARB3_InputRESERVED52 = 52|0x300U , kXBARB3_InputRESERVED53 = 53|0x300U ,
  kXBARB3_InputRESERVED54 = 54|0x300U , kXBARB3_InputRESERVED55 = 55|0x300U , kXBARB3_InputRESERVED56 = 56|0x300U , kXBARB3_InputRESERVED57 = 57|0x300U ,
  kXBARB3_InputPit1Trigger0 = 58|0x300U , kXBARB3_InputPit1Trigger1 = 59|0x300U , kXBARB3_InputAdcEtc0Coco0 = 60|0x300U , kXBARB3_InputAdcEtc0Coco1 = 61|0x300U ,
  kXBARB3_InputAdcEtc0Coco2 = 62|0x300U , kXBARB3_InputAdcEtc0Coco3 = 63|0x300U , kXBARB3_InputAdcEtc1Coco0 = 64|0x300U , kXBARB3_InputAdcEtc1Coco1 = 65|0x300U ,
  kXBARB3_InputAdcEtc1Coco2 = 66|0x300U , kXBARB3_InputAdcEtc1Coco3 = 67|0x300U , kXBARB3_InputRESERVED68 = 68|0x300U , kXBARB3_InputRESERVED69 = 69|0x300U ,
  kXBARB3_InputRESERVED70 = 70|0x300U , kXBARB3_InputRESERVED71 = 71|0x300U , kXBARB3_InputRESERVED72 = 72|0x300U , kXBARB3_InputRESERVED73 = 73|0x300U ,
  kXBARB3_InputRESERVED74 = 74|0x300U , kXBARB3_InputRESERVED75 = 75|0x300U , kXBARB3_InputDec1PosMatch = 76|0x300U , kXBARB3_InputDec2PosMatch = 77|0x300U ,
  kXBARB3_InputDec3PosMatch = 78|0x300U , kXBARB3_InputDec4PosMatch = 79|0x300U , kXBARB3_InputRESERVED80 = 80|0x300U , kXBARB3_InputRESERVED81 = 81|0x300U ,
  kXBARB3_InputDmaDone0 = 82|0x300U , kXBARB3_InputDmaDone1 = 83|0x300U , kXBARB3_InputDmaDone2 = 84|0x300U , kXBARB3_InputDmaDone3 = 85|0x300U ,
  kXBARB3_InputDmaDone4 = 86|0x300U , kXBARB3_InputDmaDone5 = 87|0x300U , kXBARB3_InputDmaDone6 = 88|0x300U , kXBARB3_InputDmaDone7 = 89|0x300U ,
  kXBARB3_InputDmaLpsrDone0 = 90|0x300U , kXBARB3_InputDmaLpsrDone1 = 91|0x300U , kXBARB3_InputDmaLpsrDone2 = 92|0x300U , kXBARB3_InputDmaLpsrDone3 = 93|0x300U ,
  kXBARB3_InputDmaLpsrDone4 = 94|0x300U , kXBARB3_InputDmaLpsrDone5 = 95|0x300U , kXBARB3_InputDmaLpsrDone6 = 96|0x300U , kXBARB3_InputDmaLpsrDone7 = 97|0x300U ,
  kXBARA1_InputLogicLow = 0|0x100U , kXBARA1_InputLogicHigh = 1|0x100U , kXBARA1_InputRESERVED2 = 2|0x100U , kXBARA1_InputRESERVED3 = 3|0x100U ,
  kXBARA1_InputIomuxXbarInout04 = 4|0x100U , kXBARA1_InputIomuxXbarInout05 = 5|0x100U , kXBARA1_InputIomuxXbarInout06 = 6|0x100U , kXBARA1_InputIomuxXbarInout07 = 7|0x100U ,
  kXBARA1_InputIomuxXbarInout08 = 8|0x100U , kXBARA1_InputIomuxXbarInout09 = 9|0x100U , kXBARA1_InputIomuxXbarInout10 = 10|0x100U , kXBARA1_InputIomuxXbarInout11 = 11|0x100U ,
  kXBARA1_InputIomuxXbarInout12 = 12|0x100U , kXBARA1_InputIomuxXbarInout13 = 13|0x100U , kXBARA1_InputIomuxXbarInout14 = 14|0x100U , kXBARA1_InputIomuxXbarInout15 = 15|0x100U ,
  kXBARA1_InputIomuxXbarInout16 = 16|0x100U , kXBARA1_InputIomuxXbarInout17 = 17|0x100U , kXBARA1_InputIomuxXbarInout18 = 18|0x100U , kXBARA1_InputIomuxXbarInout19 = 19|0x100U ,
  kXBARA1_InputIomuxXbarInout20 = 20|0x100U , kXBARA1_InputIomuxXbarInout21 = 21|0x100U , kXBARA1_InputIomuxXbarInout22 = 22|0x100U , kXBARA1_InputIomuxXbarInout23 = 23|0x100U ,
  kXBARA1_InputIomuxXbarInout24 = 24|0x100U , kXBARA1_InputIomuxXbarInout25 = 25|0x100U , kXBARA1_InputIomuxXbarInout26 = 26|0x100U , kXBARA1_InputIomuxXbarInout27 = 27|0x100U ,
  kXBARA1_InputIomuxXbarInout28 = 28|0x100U , kXBARA1_InputIomuxXbarInout29 = 29|0x100U , kXBARA1_InputIomuxXbarInout30 = 30|0x100U , kXBARA1_InputIomuxXbarInout31 = 31|0x100U ,
  kXBARA1_InputIomuxXbarInout32 = 32|0x100U , kXBARA1_InputIomuxXbarInout33 = 33|0x100U , kXBARA1_InputIomuxXbarInout34 = 34|0x100U , kXBARA1_InputIomuxXbarInout35 = 35|0x100U ,
  kXBARA1_InputIomuxXbarInout36 = 36|0x100U , kXBARA1_InputIomuxXbarInout37 = 37|0x100U , kXBARA1_InputIomuxXbarInout38 = 38|0x100U , kXBARA1_InputIomuxXbarInout39 = 39|0x100U ,
  kXBARA1_InputIomuxXbarInout40 = 40|0x100U , kXBARA1_InputRESERVED41 = 41|0x100U , kXBARA1_InputAcmp1Out = 42|0x100U , kXBARA1_InputAcmp2Out = 43|0x100U ,
  kXBARA1_InputAcmp3Out = 44|0x100U , kXBARA1_InputAcmp4Out = 45|0x100U , kXBARA1_InputRESERVED46 = 46|0x100U , kXBARA1_InputRESERVED47 = 47|0x100U ,
  kXBARA1_InputRESERVED48 = 48|0x100U , kXBARA1_InputRESERVED49 = 49|0x100U , kXBARA1_InputQtimer1Timer0 = 50|0x100U , kXBARA1_InputQtimer1Timer1 = 51|0x100U ,
  kXBARA1_InputQtimer1Timer2 = 52|0x100U , kXBARA1_InputQtimer1Timer3 = 53|0x100U , kXBARA1_InputQtimer2Timer0 = 54|0x100U , kXBARA1_InputQtimer2Timer1 = 55|0x100U ,
  kXBARA1_InputQtimer2Timer2 = 56|0x100U , kXBARA1_InputQtimer2Timer3 = 57|0x100U , kXBARA1_InputQtimer3Timer0 = 58|0x100U , kXBARA1_InputQtimer3Timer1 = 59|0x100U ,
  kXBARA1_InputQtimer3Timer2 = 60|0x100U , kXBARA1_InputQtimer3Timer3 = 61|0x100U , kXBARA1_InputQtimer4Timer0 = 62|0x100U , kXBARA1_InputQtimer4Timer1 = 63|0x100U ,
  kXBARA1_InputQtimer4Timer2 = 64|0x100U , kXBARA1_InputQtimer4Timer3 = 65|0x100U , kXBARA1_InputRESERVED66 = 66|0x100U , kXBARA1_InputRESERVED67 = 67|0x100U ,
  kXBARA1_InputRESERVED68 = 68|0x100U , kXBARA1_InputRESERVED69 = 69|0x100U , kXBARA1_InputRESERVED70 = 70|0x100U , kXBARA1_InputRESERVED71 = 71|0x100U ,
  kXBARA1_InputRESERVED72 = 72|0x100U , kXBARA1_InputRESERVED73 = 73|0x100U , kXBARA1_InputFlexpwm1Pwm0OutTrig0 = 74|0x100U , kXBARA1_InputFlexpwm1Pwm0OutTrig1 = 75|0x100U ,
  kXBARA1_InputFlexpwm1Pwm1OutTrig0 = 76|0x100U , kXBARA1_InputFlexpwm1Pwm1OutTrig1 = 77|0x100U , kXBARA1_InputFlexpwm1Pwm2OutTrig0 = 78|0x100U , kXBARA1_InputFlexpwm1Pwm2OutTrig1 = 79|0x100U ,
  kXBARA1_InputFlexpwm1Pwm3OutTrig0 = 80|0x100U , kXBARA1_InputFlexpwm1Pwm3OutTrig1 = 81|0x100U , kXBARA1_InputFlexpwm2Pwm0OutTrig01 = 82|0x100U , kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 83|0x100U ,
  kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 84|0x100U , kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 85|0x100U , kXBARA1_InputFlexpwm3Pwm0OutTrig01 = 86|0x100U , kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 87|0x100U ,
  kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 88|0x100U , kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 89|0x100U , kXBARA1_InputFlexpwm4Pwm0OutTrig01 = 90|0x100U , kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 91|0x100U ,
  kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 92|0x100U , kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 93|0x100U , kXBARA1_InputRESERVED94 = 94|0x100U , kXBARA1_InputRESERVED95 = 95|0x100U ,
  kXBARA1_InputRESERVED96 = 96|0x100U , kXBARA1_InputRESERVED97 = 97|0x100U , kXBARA1_InputRESERVED98 = 98|0x100U , kXBARA1_InputRESERVED99 = 99|0x100U ,
  kXBARA1_InputRESERVED100 = 100|0x100U , kXBARA1_InputRESERVED101 = 101|0x100U , kXBARA1_InputPit1Trigger0 = 102|0x100U , kXBARA1_InputPit1Trigger1 = 103|0x100U ,
  kXBARA1_InputPit1Trigger2 = 104|0x100U , kXBARA1_InputPit1Trigger3 = 105|0x100U , kXBARA1_InputDec1PosMatch = 106|0x100U , kXBARA1_InputDec2PosMatch = 107|0x100U ,
  kXBARA1_InputDec3PosMatch = 108|0x100U , kXBARA1_InputDec4PosMatch = 109|0x100U , kXBARA1_InputRESERVED110 = 110|0x100U , kXBARA1_InputRESERVED111 = 111|0x100U ,
  kXBARA1_InputDmaDone0 = 112|0x100U , kXBARA1_InputDmaDone1 = 113|0x100U , kXBARA1_InputDmaDone2 = 114|0x100U , kXBARA1_InputDmaDone3 = 115|0x100U ,
  kXBARA1_InputDmaDone4 = 116|0x100U , kXBARA1_InputDmaDone5 = 117|0x100U , kXBARA1_InputDmaDone6 = 118|0x100U , kXBARA1_InputDmaDone7 = 119|0x100U ,
  kXBARA1_InputDmaLpsrDone0 = 120|0x100U , kXBARA1_InputDmaLpsrDone1 = 121|0x100U , kXBARA1_InputDmaLpsrDone2 = 122|0x100U , kXBARA1_InputDmaLpsrDone3 = 123|0x100U ,
  kXBARA1_InputDmaLpsrDone4 = 124|0x100U , kXBARA1_InputDmaLpsrDone5 = 125|0x100U , kXBARA1_InputDmaLpsrDone6 = 126|0x100U , kXBARA1_InputDmaLpsrDone7 = 127|0x100U ,
  kXBARA1_InputAoi1Out0 = 128|0x100U , kXBARA1_InputAoi1Out1 = 129|0x100U , kXBARA1_InputAoi1Out2 = 130|0x100U , kXBARA1_InputAoi1Out3 = 131|0x100U ,
  kXBARA1_InputAoi2Out0 = 132|0x100U , kXBARA1_InputAoi2Out1 = 133|0x100U , kXBARA1_InputAoi2Out2 = 134|0x100U , kXBARA1_InputAoi2Out3 = 135|0x100U ,
  kXBARA1_InputAdcEtc0Coco0 = 136|0x100U , kXBARA1_InputAdcEtc0Coco1 = 137|0x100U , kXBARA1_InputAdcEtc0Coco2 = 138|0x100U , kXBARA1_InputAdcEtc0Coco3 = 139|0x100U ,
  kXBARA1_InputAdcEtc1Coco0 = 140|0x100U , kXBARA1_InputAdcEtc1Coco1 = 141|0x100U , kXBARA1_InputAdcEtc1Coco2 = 142|0x100U , kXBARA1_InputAdcEtc1Coco3 = 143|0x100U ,
  kXBARB2_InputLogicLow = 0|0x200U , kXBARB2_InputLogicHigh = 1|0x200U , kXBARB2_InputAcmp1Out = 2|0x200U , kXBARB2_InputAcmp2Out = 3|0x200U ,
  kXBARB2_InputAcmp3Out = 4|0x200U , kXBARB2_InputAcmp4Out = 5|0x200U , kXBARB2_InputRESERVED6 = 6|0x200U , kXBARB2_InputRESERVED7 = 7|0x200U ,
  kXBARB2_InputRESERVED8 = 8|0x200U , kXBARB2_InputRESERVED9 = 9|0x200U , kXBARB2_InputQtimer1Timer0 = 10|0x200U , kXBARB2_InputQtimer1Timer1 = 11|0x200U ,
  kXBARB2_InputQtimer1Timer2 = 12|0x200U , kXBARB2_InputQtimer1Timer3 = 13|0x200U , kXBARB2_InputQtimer2Timer0 = 14|0x200U , kXBARB2_InputQtimer2Timer1 = 15|0x200U ,
  kXBARB2_InputQtimer2Timer2 = 16|0x200U , kXBARB2_InputQtimer2Timer3 = 17|0x200U , kXBARB2_InputQtimer3Timer0 = 18|0x200U , kXBARB2_InputQtimer3Timer1 = 19|0x200U ,
  kXBARB2_InputQtimer3Timer2 = 20|0x200U , kXBARB2_InputQtimer3Timer3 = 21|0x200U , kXBARB2_InputQtimer4Timer0 = 22|0x200U , kXBARB2_InputQtimer4Timer1 = 23|0x200U ,
  kXBARB2_InputQtimer4Timer2 = 24|0x200U , kXBARB2_InputQtimer4Timer3 = 25|0x200U , kXBARB2_InputRESERVED26 = 26|0x200U , kXBARB2_InputRESERVED27 = 27|0x200U ,
  kXBARB2_InputRESERVED28 = 28|0x200U , kXBARB2_InputRESERVED29 = 29|0x200U , kXBARB2_InputRESERVED30 = 30|0x200U , kXBARB2_InputRESERVED31 = 31|0x200U ,
  kXBARB2_InputRESERVED32 = 32|0x200U , kXBARB2_InputRESERVED33 = 33|0x200U , kXBARB2_InputFlexpwm1Pwm0OutTrig01 = 34|0x200U , kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 35|0x200U ,
  kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 36|0x200U , kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 37|0x200U , kXBARB2_InputFlexpwm2Pwm0OutTrig01 = 38|0x200U , kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 39|0x200U ,
  kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 40|0x200U , kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 41|0x200U , kXBARB2_InputFlexpwm3Pwm0OutTrig01 = 42|0x200U , kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 43|0x200U ,
  kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 44|0x200U , kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 45|0x200U , kXBARB2_InputFlexpwm4Pwm0OutTrig01 = 46|0x200U , kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 47|0x200U ,
  kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 48|0x200U , kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 49|0x200U , kXBARB2_InputRESERVED50 = 50|0x200U , kXBARB2_InputRESERVED51 = 51|0x200U ,
  kXBARB2_InputRESERVED52 = 52|0x200U , kXBARB2_InputRESERVED53 = 53|0x200U , kXBARB2_InputRESERVED54 = 54|0x200U , kXBARB2_InputRESERVED55 = 55|0x200U ,
  kXBARB2_InputRESERVED56 = 56|0x200U , kXBARB2_InputRESERVED57 = 57|0x200U , kXBARB2_InputPit1Trigger0 = 58|0x200U , kXBARB2_InputPit1Trigger1 = 59|0x200U ,
  kXBARB2_InputAdcEtc0Coco0 = 60|0x200U , kXBARB2_InputAdcEtc0Coco1 = 61|0x200U , kXBARB2_InputAdcEtc0Coco2 = 62|0x200U , kXBARB2_InputAdcEtc0Coco3 = 63|0x200U ,
  kXBARB2_InputAdcEtc1Coco0 = 64|0x200U , kXBARB2_InputAdcEtc1Coco1 = 65|0x200U , kXBARB2_InputAdcEtc1Coco2 = 66|0x200U , kXBARB2_InputAdcEtc1Coco3 = 67|0x200U ,
  kXBARB2_InputRESERVED68 = 68|0x200U , kXBARB2_InputRESERVED69 = 69|0x200U , kXBARB2_InputRESERVED70 = 70|0x200U , kXBARB2_InputRESERVED71 = 71|0x200U ,
  kXBARB2_InputRESERVED72 = 72|0x200U , kXBARB2_InputRESERVED73 = 73|0x200U , kXBARB2_InputRESERVED74 = 74|0x200U , kXBARB2_InputRESERVED75 = 75|0x200U ,
  kXBARB2_InputDec1PosMatch = 76|0x200U , kXBARB2_InputDec2PosMatch = 77|0x200U , kXBARB2_InputDec3PosMatch = 78|0x200U , kXBARB2_InputDec4PosMatch = 79|0x200U ,
  kXBARB2_InputRESERVED80 = 80|0x200U , kXBARB2_InputRESERVED81 = 81|0x200U , kXBARB2_InputDmaDone0 = 82|0x200U , kXBARB2_InputDmaDone1 = 83|0x200U ,
  kXBARB2_InputDmaDone2 = 84|0x200U , kXBARB2_InputDmaDone3 = 85|0x200U , kXBARB2_InputDmaDone4 = 86|0x200U , kXBARB2_InputDmaDone5 = 87|0x200U ,
  kXBARB2_InputDmaDone6 = 88|0x200U , kXBARB2_InputDmaDone7 = 89|0x200U , kXBARB2_InputDmaLpsrDone0 = 90|0x200U , kXBARB2_InputDmaLpsrDone1 = 91|0x200U ,
  kXBARB2_InputDmaLpsrDone2 = 92|0x200U , kXBARB2_InputDmaLpsrDone3 = 93|0x200U , kXBARB2_InputDmaLpsrDone4 = 94|0x200U , kXBARB2_InputDmaLpsrDone5 = 95|0x200U ,
  kXBARB2_InputDmaLpsrDone6 = 96|0x200U , kXBARB2_InputDmaLpsrDone7 = 97|0x200U , kXBARB3_InputLogicLow = 0|0x300U , kXBARB3_InputLogicHigh = 1|0x300U ,
  kXBARB3_InputAcmp1Out = 2|0x300U , kXBARB3_InputAcmp2Out = 3|0x300U , kXBARB3_InputAcmp3Out = 4|0x300U , kXBARB3_InputAcmp4Out = 5|0x300U ,
  kXBARB3_InputRESERVED6 = 6|0x300U , kXBARB3_InputRESERVED7 = 7|0x300U , kXBARB3_InputRESERVED8 = 8|0x300U , kXBARB3_InputRESERVED9 = 9|0x300U ,
  kXBARB3_InputQtimer1Timer0 = 10|0x300U , kXBARB3_InputQtimer1Timer1 = 11|0x300U , kXBARB3_InputQtimer1Timer2 = 12|0x300U , kXBARB3_InputQtimer1Timer3 = 13|0x300U ,
  kXBARB3_InputQtimer2Timer0 = 14|0x300U , kXBARB3_InputQtimer2Timer1 = 15|0x300U , kXBARB3_InputQtimer2Timer2 = 16|0x300U , kXBARB3_InputQtimer2Timer3 = 17|0x300U ,
  kXBARB3_InputQtimer3Timer0 = 18|0x300U , kXBARB3_InputQtimer3Timer1 = 19|0x300U , kXBARB3_InputQtimer3Timer2 = 20|0x300U , kXBARB3_InputQtimer3Timer3 = 21|0x300U ,
  kXBARB3_InputQtimer4Timer0 = 22|0x300U , kXBARB3_InputQtimer4Timer1 = 23|0x300U , kXBARB3_InputQtimer4Timer2 = 24|0x300U , kXBARB3_InputQtimer4Timer3 = 25|0x300U ,
  kXBARB3_InputRESERVED26 = 26|0x300U , kXBARB3_InputRESERVED27 = 27|0x300U , kXBARB3_InputRESERVED28 = 28|0x300U , kXBARB3_InputRESERVED29 = 29|0x300U ,
  kXBARB3_InputRESERVED30 = 30|0x300U , kXBARB3_InputRESERVED31 = 31|0x300U , kXBARB3_InputRESERVED32 = 32|0x300U , kXBARB3_InputRESERVED33 = 33|0x300U ,
  kXBARB3_InputFlexpwm1Pwm0OutTrig01 = 34|0x300U , kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 35|0x300U , kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 36|0x300U , kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 37|0x300U ,
  kXBARB3_InputFlexpwm2Pwm0OutTrig01 = 38|0x300U , kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 39|0x300U , kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 40|0x300U , kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 41|0x300U ,
  kXBARB3_InputFlexpwm3Pwm0OutTrig01 = 42|0x300U , kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 43|0x300U , kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 44|0x300U , kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 45|0x300U ,
  kXBARB3_InputFlexpwm4Pwm0OutTrig01 = 46|0x300U , kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 47|0x300U , kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 48|0x300U , kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 49|0x300U ,
  kXBARB3_InputRESERVED50 = 50|0x300U , kXBARB3_InputRESERVED51 = 51|0x300U , kXBARB3_InputRESERVED52 = 52|0x300U , kXBARB3_InputRESERVED53 = 53|0x300U ,
  kXBARB3_InputRESERVED54 = 54|0x300U , kXBARB3_InputRESERVED55 = 55|0x300U , kXBARB3_InputRESERVED56 = 56|0x300U , kXBARB3_InputRESERVED57 = 57|0x300U ,
  kXBARB3_InputPit1Trigger0 = 58|0x300U , kXBARB3_InputPit1Trigger1 = 59|0x300U , kXBARB3_InputAdcEtc0Coco0 = 60|0x300U , kXBARB3_InputAdcEtc0Coco1 = 61|0x300U ,
  kXBARB3_InputAdcEtc0Coco2 = 62|0x300U , kXBARB3_InputAdcEtc0Coco3 = 63|0x300U , kXBARB3_InputAdcEtc1Coco0 = 64|0x300U , kXBARB3_InputAdcEtc1Coco1 = 65|0x300U ,
  kXBARB3_InputAdcEtc1Coco2 = 66|0x300U , kXBARB3_InputAdcEtc1Coco3 = 67|0x300U , kXBARB3_InputRESERVED68 = 68|0x300U , kXBARB3_InputRESERVED69 = 69|0x300U ,
  kXBARB3_InputRESERVED70 = 70|0x300U , kXBARB3_InputRESERVED71 = 71|0x300U , kXBARB3_InputRESERVED72 = 72|0x300U , kXBARB3_InputRESERVED73 = 73|0x300U ,
  kXBARB3_InputRESERVED74 = 74|0x300U , kXBARB3_InputRESERVED75 = 75|0x300U , kXBARB3_InputDec1PosMatch = 76|0x300U , kXBARB3_InputDec2PosMatch = 77|0x300U ,
  kXBARB3_InputDec3PosMatch = 78|0x300U , kXBARB3_InputDec4PosMatch = 79|0x300U , kXBARB3_InputRESERVED80 = 80|0x300U , kXBARB3_InputRESERVED81 = 81|0x300U ,
  kXBARB3_InputDmaDone0 = 82|0x300U , kXBARB3_InputDmaDone1 = 83|0x300U , kXBARB3_InputDmaDone2 = 84|0x300U , kXBARB3_InputDmaDone3 = 85|0x300U ,
  kXBARB3_InputDmaDone4 = 86|0x300U , kXBARB3_InputDmaDone5 = 87|0x300U , kXBARB3_InputDmaDone6 = 88|0x300U , kXBARB3_InputDmaDone7 = 89|0x300U ,
  kXBARB3_InputDmaLpsrDone0 = 90|0x300U , kXBARB3_InputDmaLpsrDone1 = 91|0x300U , kXBARB3_InputDmaLpsrDone2 = 92|0x300U , kXBARB3_InputDmaLpsrDone3 = 93|0x300U ,
  kXBARB3_InputDmaLpsrDone4 = 94|0x300U , kXBARB3_InputDmaLpsrDone5 = 95|0x300U , kXBARB3_InputDmaLpsrDone6 = 96|0x300U , kXBARB3_InputDmaLpsrDone7 = 97|0x300U
}
 
enum  _xbar_output_signal {
  kXBARA1_OutputDmaChMuxReq30 = 0|0x100U , kXBARA1_OutputDmaChMuxReq31 = 1|0x100U , kXBARA1_OutputDmaChMuxReq94 = 2|0x100U , kXBARA1_OutputDmaChMuxReq95 = 3|0x100U ,
  kXBARA1_OutputIomuxXbarInout04 = 4|0x100U , kXBARA1_OutputIomuxXbarInout05 = 5|0x100U , kXBARA1_OutputIomuxXbarInout06 = 6|0x100U , kXBARA1_OutputIomuxXbarInout07 = 7|0x100U ,
  kXBARA1_OutputIomuxXbarInout08 = 8|0x100U , kXBARA1_OutputIomuxXbarInout09 = 9|0x100U , kXBARA1_OutputIomuxXbarInout10 = 10|0x100U , kXBARA1_OutputIomuxXbarInout11 = 11|0x100U ,
  kXBARA1_OutputIomuxXbarInout12 = 12|0x100U , kXBARA1_OutputIomuxXbarInout13 = 13|0x100U , kXBARA1_OutputIomuxXbarInout14 = 14|0x100U , kXBARA1_OutputIomuxXbarInout15 = 15|0x100U ,
  kXBARA1_OutputIomuxXbarInout16 = 16|0x100U , kXBARA1_OutputIomuxXbarInout17 = 17|0x100U , kXBARA1_OutputIomuxXbarInout18 = 18|0x100U , kXBARA1_OutputIomuxXbarInout19 = 19|0x100U ,
  kXBARA1_OutputAcmp1Sample = 20|0x100U , kXBARA1_OutputAcmp2Sample = 21|0x100U , kXBARA1_OutputAcmp3Sample = 22|0x100U , kXBARA1_OutputAcmp4Sample = 23|0x100U ,
  kXBARA1_OutputRESERVED24 = 24|0x100U , kXBARA1_OutputRESERVED25 = 25|0x100U , kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U , kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U ,
  kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U , kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U , kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U , kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U ,
  kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U , kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U , kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U , kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U ,
  kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U , kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U , kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U , kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U ,
  kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U , kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U , kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U , kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U ,
  kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U , kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U , kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U , kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U ,
  kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U , kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U , kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U , kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U ,
  kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U , kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U , kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U , kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U ,
  kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U , kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U , kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U , kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U ,
  kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U , kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U , kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U , kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U ,
  kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U , kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U , kXBARA1_OutputEnc1PhaseAInput = 66|0x100U , kXBARA1_OutputEnc1PhaseBInput = 67|0x100U ,
  kXBARA1_OutputEnc1Index = 68|0x100U , kXBARA1_OutputEnc1Home = 69|0x100U , kXBARA1_OutputEnc1Trigger = 70|0x100U , kXBARA1_OutputEnc2PhaseAInput = 71|0x100U ,
  kXBARA1_OutputEnc2PhaseBInput = 72|0x100U , kXBARA1_OutputEnc2Index = 73|0x100U , kXBARA1_OutputEnc2Home = 74|0x100U , kXBARA1_OutputEnc2Trigger = 75|0x100U ,
  kXBARA1_OutputEnc3PhaseAInput = 76|0x100U , kXBARA1_OutputEnc3PhaseBInput = 77|0x100U , kXBARA1_OutputEnc3Index = 78|0x100U , kXBARA1_OutputEnc3Home = 79|0x100U ,
  kXBARA1_OutputEnc3Trigger = 80|0x100U , kXBARA1_OutputEnc4PhaseAInput = 81|0x100U , kXBARA1_OutputEnc4PhaseBInput = 82|0x100U , kXBARA1_OutputEnc4Index = 83|0x100U ,
  kXBARA1_OutputEnc4Home = 84|0x100U , kXBARA1_OutputEnc4Trigger = 85|0x100U , kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U , kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U ,
  kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U , kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U , kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U , kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U ,
  kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U , kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U , kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U , kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U ,
  kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U , kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U , kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U , kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U ,
  kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U , kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U , kXBARA1_OutputEwmEwmIn = 102|0x100U , kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U ,
  kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U , kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U , kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U , kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U ,
  kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U , kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U , kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U , kXBARA1_OutputLpi2c1TrgInput = 111|0x100U ,
  kXBARA1_OutputLpi2c2TrgInput = 112|0x100U , kXBARA1_OutputLpi2c3TrgInput = 113|0x100U , kXBARA1_OutputLpi2c4TrgInput = 114|0x100U , kXBARA1_OutputLpspi1TrgInput = 115|0x100U ,
  kXBARA1_OutputLpspi2TrgInput = 116|0x100U , kXBARA1_OutputLpspi3TrgInput = 117|0x100U , kXBARA1_OutputLpspi4TrgInput = 118|0x100U , kXBARA1_OutputLpuart1TrgInput = 119|0x100U ,
  kXBARA1_OutputLpuart2TrgInput = 120|0x100U , kXBARA1_OutputLpuart3TrgInput = 121|0x100U , kXBARA1_OutputLpuart4TrgInput = 122|0x100U , kXBARA1_OutputLpuart5TrgInput = 123|0x100U ,
  kXBARA1_OutputLpuart6TrgInput = 124|0x100U , kXBARA1_OutputLpuart7TrgInput = 125|0x100U , kXBARA1_OutputLpuart8TrgInput = 126|0x100U , kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U ,
  kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U , kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U , kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U , kXBARB2_OutputAoi1In00 = 0|0x200U ,
  kXBARB2_OutputAoi1In01 = 1|0x200U , kXBARB2_OutputAoi1In02 = 2|0x200U , kXBARB2_OutputAoi1In03 = 3|0x200U , kXBARB2_OutputAoi1In04 = 4|0x200U ,
  kXBARB2_OutputAoi1In05 = 5|0x200U , kXBARB2_OutputAoi1In06 = 6|0x200U , kXBARB2_OutputAoi1In07 = 7|0x200U , kXBARB2_OutputAoi1In08 = 8|0x200U ,
  kXBARB2_OutputAoi1In09 = 9|0x200U , kXBARB2_OutputAoi1In10 = 10|0x200U , kXBARB2_OutputAoi1In11 = 11|0x200U , kXBARB2_OutputAoi1In12 = 12|0x200U ,
  kXBARB2_OutputAoi1In13 = 13|0x200U , kXBARB2_OutputAoi1In14 = 14|0x200U , kXBARB2_OutputAoi1In15 = 15|0x200U , kXBARB3_OutputAoi2In00 = 0|0x300U ,
  kXBARB3_OutputAoi2In01 = 1|0x300U , kXBARB3_OutputAoi2In02 = 2|0x300U , kXBARB3_OutputAoi2In03 = 3|0x300U , kXBARB3_OutputAoi2In04 = 4|0x300U ,
  kXBARB3_OutputAoi2In05 = 5|0x300U , kXBARB3_OutputAoi2In06 = 6|0x300U , kXBARB3_OutputAoi2In07 = 7|0x300U , kXBARB3_OutputAoi2In08 = 8|0x300U ,
  kXBARB3_OutputAoi2In09 = 9|0x300U , kXBARB3_OutputAoi2In10 = 10|0x300U , kXBARB3_OutputAoi2In11 = 11|0x300U , kXBARB3_OutputAoi2In12 = 12|0x300U ,
  kXBARB3_OutputAoi2In13 = 13|0x300U , kXBARB3_OutputAoi2In14 = 14|0x300U , kXBARB3_OutputAoi2In15 = 15|0x300U , kXBARA1_OutputDmaChMuxReq81 = 0|0x100U ,
  kXBARA1_OutputDmaChMuxReq82 = 1|0x100U , kXBARA1_OutputDmaChMuxReq83 = 2|0x100U , kXBARA1_OutputDmaChMuxReq84 = 3|0x100U , kXBARA1_OutputIomuxXbarInout04 = 4|0x100U ,
  kXBARA1_OutputIomuxXbarInout05 = 5|0x100U , kXBARA1_OutputIomuxXbarInout06 = 6|0x100U , kXBARA1_OutputIomuxXbarInout07 = 7|0x100U , kXBARA1_OutputIomuxXbarInout08 = 8|0x100U ,
  kXBARA1_OutputIomuxXbarInout09 = 9|0x100U , kXBARA1_OutputIomuxXbarInout10 = 10|0x100U , kXBARA1_OutputIomuxXbarInout11 = 11|0x100U , kXBARA1_OutputIomuxXbarInout12 = 12|0x100U ,
  kXBARA1_OutputIomuxXbarInout13 = 13|0x100U , kXBARA1_OutputIomuxXbarInout14 = 14|0x100U , kXBARA1_OutputIomuxXbarInout15 = 15|0x100U , kXBARA1_OutputIomuxXbarInout16 = 16|0x100U ,
  kXBARA1_OutputIomuxXbarInout17 = 17|0x100U , kXBARA1_OutputIomuxXbarInout18 = 18|0x100U , kXBARA1_OutputIomuxXbarInout19 = 19|0x100U , kXBARA1_OutputIomuxXbarInout20 = 20|0x100U ,
  kXBARA1_OutputIomuxXbarInout21 = 21|0x100U , kXBARA1_OutputIomuxXbarInout22 = 22|0x100U , kXBARA1_OutputIomuxXbarInout23 = 23|0x100U , kXBARA1_OutputIomuxXbarInout24 = 24|0x100U ,
  kXBARA1_OutputIomuxXbarInout25 = 25|0x100U , kXBARA1_OutputIomuxXbarInout26 = 26|0x100U , kXBARA1_OutputIomuxXbarInout27 = 27|0x100U , kXBARA1_OutputIomuxXbarInout28 = 28|0x100U ,
  kXBARA1_OutputIomuxXbarInout29 = 29|0x100U , kXBARA1_OutputIomuxXbarInout30 = 30|0x100U , kXBARA1_OutputIomuxXbarInout31 = 31|0x100U , kXBARA1_OutputIomuxXbarInout32 = 32|0x100U ,
  kXBARA1_OutputIomuxXbarInout33 = 33|0x100U , kXBARA1_OutputIomuxXbarInout34 = 34|0x100U , kXBARA1_OutputIomuxXbarInout35 = 35|0x100U , kXBARA1_OutputIomuxXbarInout36 = 36|0x100U ,
  kXBARA1_OutputIomuxXbarInout37 = 37|0x100U , kXBARA1_OutputIomuxXbarInout38 = 38|0x100U , kXBARA1_OutputIomuxXbarInout39 = 39|0x100U , kXBARA1_OutputIomuxXbarInout40 = 40|0x100U ,
  kXBARA1_OutputAcmp1Sample = 41|0x100U , kXBARA1_OutputAcmp2Sample = 42|0x100U , kXBARA1_OutputAcmp3Sample = 43|0x100U , kXBARA1_OutputAcmp4Sample = 44|0x100U ,
  kXBARA1_OutputRESERVED45 = 45|0x100U , kXBARA1_OutputRESERVED46 = 46|0x100U , kXBARA1_OutputRESERVED47 = 47|0x100U , kXBARA1_OutputRESERVED48 = 48|0x100U ,
  kXBARA1_OutputFlexpwm1Pwm0Exta = 49|0x100U , kXBARA1_OutputFlexpwm1Pwm1Exta = 50|0x100U , kXBARA1_OutputFlexpwm1Pwm2Exta = 51|0x100U , kXBARA1_OutputFlexpwm1Pwm3Exta = 52|0x100U ,
  kXBARA1_OutputFlexpwm1Pwm0ExtSync = 53|0x100U , kXBARA1_OutputFlexpwm1Pwm1ExtSync = 54|0x100U , kXBARA1_OutputFlexpwm1Pwm2ExtSync = 55|0x100U , kXBARA1_OutputFlexpwm1Pwm3ExtSync = 56|0x100U ,
  kXBARA1_OutputFlexpwm1ExtClk = 57|0x100U , kXBARA1_OutputFlexpwm1Fault0 = 58|0x100U , kXBARA1_OutputFlexpwm1Fault1 = 59|0x100U , kXBARA1_OutputFlexpwm1234Fault2 = 60|0x100U ,
  kXBARA1_OutputFlexpwm1234Fault3 = 61|0x100U , kXBARA1_OutputFlexpwm1ExtForce = 62|0x100U , kXBARA1_OutputFlexpwm2Pwm0Exta = 63|0x100U , kXBARA1_OutputFlexpwm2Pwm1Exta = 64|0x100U ,
  kXBARA1_OutputFlexpwm2Pwm2Exta = 65|0x100U , kXBARA1_OutputFlexpwm2Pwm3Exta = 66|0x100U , kXBARA1_OutputFlexpwm2Pwm0ExtSync = 67|0x100U , kXBARA1_OutputFlexpwm2Pwm1ExtSync = 68|0x100U ,
  kXBARA1_OutputFlexpwm2Pwm2ExtSync = 69|0x100U , kXBARA1_OutputFlexpwm2Pwm3ExtSync = 70|0x100U , kXBARA1_OutputFlexpwm2ExtClk = 71|0x100U , kXBARA1_OutputFlexpwm2Fault0 = 72|0x100U ,
  kXBARA1_OutputFlexpwm2Fault1 = 73|0x100U , kXBARA1_OutputFlexpwm2ExtForce = 74|0x100U , kXBARA1_OutputFlexpwm34Pwm0Exta = 75|0x100U , kXBARA1_OutputFlexpwm34Pwm1Exta = 76|0x100U ,
  kXBARA1_OutputFlexpwm34Pwm2Exta = 77|0x100U , kXBARA1_OutputFlexpwm34Pwm3Exta = 78|0x100U , kXBARA1_OutputFlexpwm34ExtClk = 79|0x100U , kXBARA1_OutputFlexpwm3Pwm0ExtSync = 80|0x100U ,
  kXBARA1_OutputFlexpwm3Pwm1ExtSync = 81|0x100U , kXBARA1_OutputFlexpwm3Pwm2ExtSync = 82|0x100U , kXBARA1_OutputFlexpwm3Pwm3ExtSync = 83|0x100U , kXBARA1_OutputFlexpwm3Fault0 = 84|0x100U ,
  kXBARA1_OutputFlexpwm3Fault1 = 85|0x100U , kXBARA1_OutputFlexpwm3ExtForce = 86|0x100U , kXBARA1_OutputFlexpwm4Pwm0ExtSync = 87|0x100U , kXBARA1_OutputFlexpwm4Pwm1ExtSync = 88|0x100U ,
  kXBARA1_OutputFlexpwm4Pwm2ExtSync = 89|0x100U , kXBARA1_OutputFlexpwm4Pwm3ExtSync = 90|0x100U , kXBARA1_OutputFlexpwm4Fault0 = 91|0x100U , kXBARA1_OutputFlexpwm4Fault1 = 92|0x100U ,
  kXBARA1_OutputFlexpwm4ExtForce = 93|0x100U , kXBARA1_OutputRESERVED94 = 94|0x100U , kXBARA1_OutputRESERVED95 = 95|0x100U , kXBARA1_OutputRESERVED96 = 96|0x100U ,
  kXBARA1_OutputRESERVED97 = 97|0x100U , kXBARA1_OutputRESERVED98 = 98|0x100U , kXBARA1_OutputRESERVED99 = 99|0x100U , kXBARA1_OutputRESERVED100 = 100|0x100U ,
  kXBARA1_OutputRESERVED101 = 101|0x100U , kXBARA1_OutputRESERVED102 = 102|0x100U , kXBARA1_OutputRESERVED103 = 103|0x100U , kXBARA1_OutputRESERVED104 = 104|0x100U ,
  kXBARA1_OutputRESERVED105 = 105|0x100U , kXBARA1_OutputRESERVED106 = 106|0x100U , kXBARA1_OutputRESERVED107 = 107|0x100U , kXBARA1_OutputDec1Phasea = 108|0x100U ,
  kXBARA1_OutputDec1Phaseb = 109|0x100U , kXBARA1_OutputDec1Index = 110|0x100U , kXBARA1_OutputDec1Home = 111|0x100U , kXBARA1_OutputDec1Trigger = 112|0x100U ,
  kXBARA1_OutputDec2Phasea = 113|0x100U , kXBARA1_OutputDec2Phaseb = 114|0x100U , kXBARA1_OutputDec2Index = 115|0x100U , kXBARA1_OutputDec2Home = 116|0x100U ,
  kXBARA1_OutputDec2Trigger = 117|0x100U , kXBARA1_OutputDec3Phasea = 118|0x100U , kXBARA1_OutputDec3Phaseb = 119|0x100U , kXBARA1_OutputDec3Index = 120|0x100U ,
  kXBARA1_OutputDec3Home = 121|0x100U , kXBARA1_OutputDec3Trigger = 122|0x100U , kXBARA1_OutputDec4Phasea = 123|0x100U , kXBARA1_OutputDec4Phaseb = 124|0x100U ,
  kXBARA1_OutputDec4Index = 125|0x100U , kXBARA1_OutputDec4Home = 126|0x100U , kXBARA1_OutputDec4Trigger = 127|0x100U , kXBARA1_OutputRESERVED128 = 128|0x100U ,
  kXBARA1_OutputRESERVED129 = 129|0x100U , kXBARA1_OutputRESERVED130 = 130|0x100U , kXBARA1_OutputRESERVED131 = 131|0x100U , kXBARA1_OutputCan1 = 132|0x100U ,
  kXBARA1_OutputCan2 = 133|0x100U , kXBARA1_OutputRESERVED134 = 134|0x100U , kXBARA1_OutputRESERVED135 = 135|0x100U , kXBARA1_OutputRESERVED136 = 136|0x100U ,
  kXBARA1_OutputRESERVED137 = 137|0x100U , kXBARA1_OutputQtimer1Timer0 = 138|0x100U , kXBARA1_OutputQtimer1Timer1 = 139|0x100U , kXBARA1_OutputQtimer1Timer2 = 140|0x100U ,
  kXBARA1_OutputQtimer1Timer3 = 141|0x100U , kXBARA1_OutputQtimer2Timer0 = 142|0x100U , kXBARA1_OutputQtimer2Timer1 = 143|0x100U , kXBARA1_OutputQtimer2Timer2 = 144|0x100U ,
  kXBARA1_OutputQtimer2Timer3 = 145|0x100U , kXBARA1_OutputQtimer3Timer0 = 146|0x100U , kXBARA1_OutputQtimer3Timer1 = 147|0x100U , kXBARA1_OutputQtimer3Timer2 = 148|0x100U ,
  kXBARA1_OutputQtimer3Timer3 = 149|0x100U , kXBARA1_OutputQtimer4Timer0 = 150|0x100U , kXBARA1_OutputQtimer4Timer1 = 151|0x100U , kXBARA1_OutputQtimer4Timer2 = 152|0x100U ,
  kXBARA1_OutputQtimer4Timer3 = 153|0x100U , kXBARA1_OutputEwmEwmIn = 154|0x100U , kXBARA1_OutputAdcEtc0Coco0 = 155|0x100U , kXBARA1_OutputAdcEtc0Coco1 = 156|0x100U ,
  kXBARA1_OutputAdcEtc0Coco2 = 157|0x100U , kXBARA1_OutputAdcEtc0Coco3 = 158|0x100U , kXBARA1_OutputAdcEtc1Coco0 = 159|0x100U , kXBARA1_OutputAdcEtc1Coco1 = 160|0x100U ,
  kXBARA1_OutputAdcEtc1Coco2 = 161|0x100U , kXBARA1_OutputAdcEtc1Coco3 = 162|0x100U , kXBARA1_OutputRESERVED163 = 163|0x100U , kXBARA1_OutputRESERVED164 = 164|0x100U ,
  kXBARA1_OutputRESERVED165 = 165|0x100U , kXBARA1_OutputRESERVED166 = 166|0x100U , kXBARA1_OutputRESERVED167 = 167|0x100U , kXBARA1_OutputRESERVED168 = 168|0x100U ,
  kXBARA1_OutputRESERVED169 = 169|0x100U , kXBARA1_OutputRESERVED170 = 170|0x100U , kXBARA1_OutputFlexio1TrigIn0 = 171|0x100U , kXBARA1_OutputFlexio1TrigIn1 = 172|0x100U ,
  kXBARA1_OutputFlexio2TrigIn0 = 173|0x100U , kXBARA1_OutputFlexio2TrigIn1 = 174|0x100U , kXBARB2_OutputAoi1In00 = 0|0x200U , kXBARB2_OutputAoi1In01 = 1|0x200U ,
  kXBARB2_OutputAoi1In02 = 2|0x200U , kXBARB2_OutputAoi1In03 = 3|0x200U , kXBARB2_OutputAoi1In04 = 4|0x200U , kXBARB2_OutputAoi1In05 = 5|0x200U ,
  kXBARB2_OutputAoi1In06 = 6|0x200U , kXBARB2_OutputAoi1In07 = 7|0x200U , kXBARB2_OutputAoi1In08 = 8|0x200U , kXBARB2_OutputAoi1In09 = 9|0x200U ,
  kXBARB2_OutputAoi1In10 = 10|0x200U , kXBARB2_OutputAoi1In11 = 11|0x200U , kXBARB2_OutputAoi1In12 = 12|0x200U , kXBARB2_OutputAoi1In13 = 13|0x200U ,
  kXBARB2_OutputAoi1In14 = 14|0x200U , kXBARB2_OutputAoi1In15 = 15|0x200U , kXBARB3_OutputAoi2In00 = 0|0x300U , kXBARB3_OutputAoi2In01 = 1|0x300U ,
  kXBARB3_OutputAoi2In02 = 2|0x300U , kXBARB3_OutputAoi2In03 = 3|0x300U , kXBARB3_OutputAoi2In04 = 4|0x300U , kXBARB3_OutputAoi2In05 = 5|0x300U ,
  kXBARB3_OutputAoi2In06 = 6|0x300U , kXBARB3_OutputAoi2In07 = 7|0x300U , kXBARB3_OutputAoi2In08 = 8|0x300U , kXBARB3_OutputAoi2In09 = 9|0x300U ,
  kXBARB3_OutputAoi2In10 = 10|0x300U , kXBARB3_OutputAoi2In11 = 11|0x300U , kXBARB3_OutputAoi2In12 = 12|0x300U , kXBARB3_OutputAoi2In13 = 13|0x300U ,
  kXBARB3_OutputAoi2In14 = 14|0x300U , kXBARB3_OutputAoi2In15 = 15|0x300U , kXBARA1_OutputDmaChMuxReq81 = 0|0x100U , kXBARA1_OutputDmaChMuxReq82 = 1|0x100U ,
  kXBARA1_OutputDmaChMuxReq83 = 2|0x100U , kXBARA1_OutputDmaChMuxReq84 = 3|0x100U , kXBARA1_OutputIomuxXbarInout04 = 4|0x100U , kXBARA1_OutputIomuxXbarInout05 = 5|0x100U ,
  kXBARA1_OutputIomuxXbarInout06 = 6|0x100U , kXBARA1_OutputIomuxXbarInout07 = 7|0x100U , kXBARA1_OutputIomuxXbarInout08 = 8|0x100U , kXBARA1_OutputIomuxXbarInout09 = 9|0x100U ,
  kXBARA1_OutputIomuxXbarInout10 = 10|0x100U , kXBARA1_OutputIomuxXbarInout11 = 11|0x100U , kXBARA1_OutputIomuxXbarInout12 = 12|0x100U , kXBARA1_OutputIomuxXbarInout13 = 13|0x100U ,
  kXBARA1_OutputIomuxXbarInout14 = 14|0x100U , kXBARA1_OutputIomuxXbarInout15 = 15|0x100U , kXBARA1_OutputIomuxXbarInout16 = 16|0x100U , kXBARA1_OutputIomuxXbarInout17 = 17|0x100U ,
  kXBARA1_OutputIomuxXbarInout18 = 18|0x100U , kXBARA1_OutputIomuxXbarInout19 = 19|0x100U , kXBARA1_OutputIomuxXbarInout20 = 20|0x100U , kXBARA1_OutputIomuxXbarInout21 = 21|0x100U ,
  kXBARA1_OutputIomuxXbarInout22 = 22|0x100U , kXBARA1_OutputIomuxXbarInout23 = 23|0x100U , kXBARA1_OutputIomuxXbarInout24 = 24|0x100U , kXBARA1_OutputIomuxXbarInout25 = 25|0x100U ,
  kXBARA1_OutputIomuxXbarInout26 = 26|0x100U , kXBARA1_OutputIomuxXbarInout27 = 27|0x100U , kXBARA1_OutputIomuxXbarInout28 = 28|0x100U , kXBARA1_OutputIomuxXbarInout29 = 29|0x100U ,
  kXBARA1_OutputIomuxXbarInout30 = 30|0x100U , kXBARA1_OutputIomuxXbarInout31 = 31|0x100U , kXBARA1_OutputIomuxXbarInout32 = 32|0x100U , kXBARA1_OutputIomuxXbarInout33 = 33|0x100U ,
  kXBARA1_OutputIomuxXbarInout34 = 34|0x100U , kXBARA1_OutputIomuxXbarInout35 = 35|0x100U , kXBARA1_OutputIomuxXbarInout36 = 36|0x100U , kXBARA1_OutputIomuxXbarInout37 = 37|0x100U ,
  kXBARA1_OutputIomuxXbarInout38 = 38|0x100U , kXBARA1_OutputIomuxXbarInout39 = 39|0x100U , kXBARA1_OutputIomuxXbarInout40 = 40|0x100U , kXBARA1_OutputAcmp1Sample = 41|0x100U ,
  kXBARA1_OutputAcmp2Sample = 42|0x100U , kXBARA1_OutputAcmp3Sample = 43|0x100U , kXBARA1_OutputAcmp4Sample = 44|0x100U , kXBARA1_OutputRESERVED45 = 45|0x100U ,
  kXBARA1_OutputRESERVED46 = 46|0x100U , kXBARA1_OutputRESERVED47 = 47|0x100U , kXBARA1_OutputRESERVED48 = 48|0x100U , kXBARA1_OutputFlexpwm1Pwm0Exta = 49|0x100U ,
  kXBARA1_OutputFlexpwm1Pwm1Exta = 50|0x100U , kXBARA1_OutputFlexpwm1Pwm2Exta = 51|0x100U , kXBARA1_OutputFlexpwm1Pwm3Exta = 52|0x100U , kXBARA1_OutputFlexpwm1Pwm0ExtSync = 53|0x100U ,
  kXBARA1_OutputFlexpwm1Pwm1ExtSync = 54|0x100U , kXBARA1_OutputFlexpwm1Pwm2ExtSync = 55|0x100U , kXBARA1_OutputFlexpwm1Pwm3ExtSync = 56|0x100U , kXBARA1_OutputFlexpwm1ExtClk = 57|0x100U ,
  kXBARA1_OutputFlexpwm1Fault0 = 58|0x100U , kXBARA1_OutputFlexpwm1Fault1 = 59|0x100U , kXBARA1_OutputFlexpwm1234Fault2 = 60|0x100U , kXBARA1_OutputFlexpwm1234Fault3 = 61|0x100U ,
  kXBARA1_OutputFlexpwm1ExtForce = 62|0x100U , kXBARA1_OutputFlexpwm2Pwm0Exta = 63|0x100U , kXBARA1_OutputFlexpwm2Pwm1Exta = 64|0x100U , kXBARA1_OutputFlexpwm2Pwm2Exta = 65|0x100U ,
  kXBARA1_OutputFlexpwm2Pwm3Exta = 66|0x100U , kXBARA1_OutputFlexpwm2Pwm0ExtSync = 67|0x100U , kXBARA1_OutputFlexpwm2Pwm1ExtSync = 68|0x100U , kXBARA1_OutputFlexpwm2Pwm2ExtSync = 69|0x100U ,
  kXBARA1_OutputFlexpwm2Pwm3ExtSync = 70|0x100U , kXBARA1_OutputFlexpwm2ExtClk = 71|0x100U , kXBARA1_OutputFlexpwm2Fault0 = 72|0x100U , kXBARA1_OutputFlexpwm2Fault1 = 73|0x100U ,
  kXBARA1_OutputFlexpwm2ExtForce = 74|0x100U , kXBARA1_OutputFlexpwm34Pwm0Exta = 75|0x100U , kXBARA1_OutputFlexpwm34Pwm1Exta = 76|0x100U , kXBARA1_OutputFlexpwm34Pwm2Exta = 77|0x100U ,
  kXBARA1_OutputFlexpwm34Pwm3Exta = 78|0x100U , kXBARA1_OutputFlexpwm34ExtClk = 79|0x100U , kXBARA1_OutputFlexpwm3Pwm0ExtSync = 80|0x100U , kXBARA1_OutputFlexpwm3Pwm1ExtSync = 81|0x100U ,
  kXBARA1_OutputFlexpwm3Pwm2ExtSync = 82|0x100U , kXBARA1_OutputFlexpwm3Pwm3ExtSync = 83|0x100U , kXBARA1_OutputFlexpwm3Fault0 = 84|0x100U , kXBARA1_OutputFlexpwm3Fault1 = 85|0x100U ,
  kXBARA1_OutputFlexpwm3ExtForce = 86|0x100U , kXBARA1_OutputFlexpwm4Pwm0ExtSync = 87|0x100U , kXBARA1_OutputFlexpwm4Pwm1ExtSync = 88|0x100U , kXBARA1_OutputFlexpwm4Pwm2ExtSync = 89|0x100U ,
  kXBARA1_OutputFlexpwm4Pwm3ExtSync = 90|0x100U , kXBARA1_OutputFlexpwm4Fault0 = 91|0x100U , kXBARA1_OutputFlexpwm4Fault1 = 92|0x100U , kXBARA1_OutputFlexpwm4ExtForce = 93|0x100U ,
  kXBARA1_OutputRESERVED94 = 94|0x100U , kXBARA1_OutputRESERVED95 = 95|0x100U , kXBARA1_OutputRESERVED96 = 96|0x100U , kXBARA1_OutputRESERVED97 = 97|0x100U ,
  kXBARA1_OutputRESERVED98 = 98|0x100U , kXBARA1_OutputRESERVED99 = 99|0x100U , kXBARA1_OutputRESERVED100 = 100|0x100U , kXBARA1_OutputRESERVED101 = 101|0x100U ,
  kXBARA1_OutputRESERVED102 = 102|0x100U , kXBARA1_OutputRESERVED103 = 103|0x100U , kXBARA1_OutputRESERVED104 = 104|0x100U , kXBARA1_OutputRESERVED105 = 105|0x100U ,
  kXBARA1_OutputRESERVED106 = 106|0x100U , kXBARA1_OutputRESERVED107 = 107|0x100U , kXBARA1_OutputDec1Phasea = 108|0x100U , kXBARA1_OutputDec1Phaseb = 109|0x100U ,
  kXBARA1_OutputDec1Index = 110|0x100U , kXBARA1_OutputDec1Home = 111|0x100U , kXBARA1_OutputDec1Trigger = 112|0x100U , kXBARA1_OutputDec2Phasea = 113|0x100U ,
  kXBARA1_OutputDec2Phaseb = 114|0x100U , kXBARA1_OutputDec2Index = 115|0x100U , kXBARA1_OutputDec2Home = 116|0x100U , kXBARA1_OutputDec2Trigger = 117|0x100U ,
  kXBARA1_OutputDec3Phasea = 118|0x100U , kXBARA1_OutputDec3Phaseb = 119|0x100U , kXBARA1_OutputDec3Index = 120|0x100U , kXBARA1_OutputDec3Home = 121|0x100U ,
  kXBARA1_OutputDec3Trigger = 122|0x100U , kXBARA1_OutputDec4Phasea = 123|0x100U , kXBARA1_OutputDec4Phaseb = 124|0x100U , kXBARA1_OutputDec4Index = 125|0x100U ,
  kXBARA1_OutputDec4Home = 126|0x100U , kXBARA1_OutputDec4Trigger = 127|0x100U , kXBARA1_OutputRESERVED128 = 128|0x100U , kXBARA1_OutputRESERVED129 = 129|0x100U ,
  kXBARA1_OutputRESERVED130 = 130|0x100U , kXBARA1_OutputRESERVED131 = 131|0x100U , kXBARA1_OutputCan1 = 132|0x100U , kXBARA1_OutputCan2 = 133|0x100U ,
  kXBARA1_OutputRESERVED134 = 134|0x100U , kXBARA1_OutputRESERVED135 = 135|0x100U , kXBARA1_OutputRESERVED136 = 136|0x100U , kXBARA1_OutputRESERVED137 = 137|0x100U ,
  kXBARA1_OutputQtimer1Timer0 = 138|0x100U , kXBARA1_OutputQtimer1Timer1 = 139|0x100U , kXBARA1_OutputQtimer1Timer2 = 140|0x100U , kXBARA1_OutputQtimer1Timer3 = 141|0x100U ,
  kXBARA1_OutputQtimer2Timer0 = 142|0x100U , kXBARA1_OutputQtimer2Timer1 = 143|0x100U , kXBARA1_OutputQtimer2Timer2 = 144|0x100U , kXBARA1_OutputQtimer2Timer3 = 145|0x100U ,
  kXBARA1_OutputQtimer3Timer0 = 146|0x100U , kXBARA1_OutputQtimer3Timer1 = 147|0x100U , kXBARA1_OutputQtimer3Timer2 = 148|0x100U , kXBARA1_OutputQtimer3Timer3 = 149|0x100U ,
  kXBARA1_OutputQtimer4Timer0 = 150|0x100U , kXBARA1_OutputQtimer4Timer1 = 151|0x100U , kXBARA1_OutputQtimer4Timer2 = 152|0x100U , kXBARA1_OutputQtimer4Timer3 = 153|0x100U ,
  kXBARA1_OutputEwmEwmIn = 154|0x100U , kXBARA1_OutputAdcEtc0Coco0 = 155|0x100U , kXBARA1_OutputAdcEtc0Coco1 = 156|0x100U , kXBARA1_OutputAdcEtc0Coco2 = 157|0x100U ,
  kXBARA1_OutputAdcEtc0Coco3 = 158|0x100U , kXBARA1_OutputAdcEtc1Coco0 = 159|0x100U , kXBARA1_OutputAdcEtc1Coco1 = 160|0x100U , kXBARA1_OutputAdcEtc1Coco2 = 161|0x100U ,
  kXBARA1_OutputAdcEtc1Coco3 = 162|0x100U , kXBARA1_OutputRESERVED163 = 163|0x100U , kXBARA1_OutputRESERVED164 = 164|0x100U , kXBARA1_OutputRESERVED165 = 165|0x100U ,
  kXBARA1_OutputRESERVED166 = 166|0x100U , kXBARA1_OutputRESERVED167 = 167|0x100U , kXBARA1_OutputRESERVED168 = 168|0x100U , kXBARA1_OutputRESERVED169 = 169|0x100U ,
  kXBARA1_OutputRESERVED170 = 170|0x100U , kXBARA1_OutputFlexio1TrigIn0 = 171|0x100U , kXBARA1_OutputFlexio1TrigIn1 = 172|0x100U , kXBARA1_OutputFlexio2TrigIn0 = 173|0x100U ,
  kXBARA1_OutputFlexio2TrigIn1 = 174|0x100U , kXBARB2_OutputAoi1In00 = 0|0x200U , kXBARB2_OutputAoi1In01 = 1|0x200U , kXBARB2_OutputAoi1In02 = 2|0x200U ,
  kXBARB2_OutputAoi1In03 = 3|0x200U , kXBARB2_OutputAoi1In04 = 4|0x200U , kXBARB2_OutputAoi1In05 = 5|0x200U , kXBARB2_OutputAoi1In06 = 6|0x200U ,
  kXBARB2_OutputAoi1In07 = 7|0x200U , kXBARB2_OutputAoi1In08 = 8|0x200U , kXBARB2_OutputAoi1In09 = 9|0x200U , kXBARB2_OutputAoi1In10 = 10|0x200U ,
  kXBARB2_OutputAoi1In11 = 11|0x200U , kXBARB2_OutputAoi1In12 = 12|0x200U , kXBARB2_OutputAoi1In13 = 13|0x200U , kXBARB2_OutputAoi1In14 = 14|0x200U ,
  kXBARB2_OutputAoi1In15 = 15|0x200U , kXBARB3_OutputAoi2In00 = 0|0x300U , kXBARB3_OutputAoi2In01 = 1|0x300U , kXBARB3_OutputAoi2In02 = 2|0x300U ,
  kXBARB3_OutputAoi2In03 = 3|0x300U , kXBARB3_OutputAoi2In04 = 4|0x300U , kXBARB3_OutputAoi2In05 = 5|0x300U , kXBARB3_OutputAoi2In06 = 6|0x300U ,
  kXBARB3_OutputAoi2In07 = 7|0x300U , kXBARB3_OutputAoi2In08 = 8|0x300U , kXBARB3_OutputAoi2In09 = 9|0x300U , kXBARB3_OutputAoi2In10 = 10|0x300U ,
  kXBARB3_OutputAoi2In11 = 11|0x300U , kXBARB3_OutputAoi2In12 = 12|0x300U , kXBARB3_OutputAoi2In13 = 13|0x300U , kXBARB3_OutputAoi2In14 = 14|0x300U ,
  kXBARB3_OutputAoi2In15 = 15|0x300U
}
 
enum  _iomuxc_sw_mux_ctl_pad {
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 = 118U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 = 119U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 = 122U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 = 123U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 = 126U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 = 127U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 = 130U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 = 131U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 = 134U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 = 135U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 = 138U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 = 139U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 = 142U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 = 143U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 = 144U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 = 118U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 = 119U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 = 122U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 = 123U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 = 126U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 = 127U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 = 130U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 = 131U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 = 134U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 = 135U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 = 138U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 = 139U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 = 142U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 = 143U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 = 144U
}
 Enumeration for the IOMUXC SW_MUX_CTL_PAD. More...
 
enum  _iomuxc_sw_pad_ctl_pad {
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 = 118U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 = 119U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 = 122U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 = 123U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 = 126U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 = 127U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 = 130U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 = 131U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 = 134U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 = 135U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 = 138U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 = 139U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 = 142U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 = 143U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 = 144U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 = 118U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 = 119U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 = 122U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 = 123U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 = 126U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 = 127U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 = 130U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 = 131U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 = 134U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 = 135U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 = 138U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 = 139U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 = 142U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 = 143U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 = 144U
}
 Enumeration for the IOMUXC SW_PAD_CTL_PAD. More...
 
enum  _iomuxc_select_input {
  kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U , kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U , kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U , kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U ,
  kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U , kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U , kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U , kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U ,
  kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U , kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U , kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U , kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U ,
  kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U , kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U , kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U , kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U ,
  kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U , kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U , kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U , kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U ,
  kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U , kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U , kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U , kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U ,
  kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U , kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U , kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U , kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U ,
  kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U , kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U , kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U , kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U ,
  kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U , kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U , kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U , kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U ,
  kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U , kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U , kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U , kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U ,
  kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U , kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U , kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U , kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U ,
  kIOMUXC_FLEXSPI_A_DQS_SELECT_INPUT = 44U , kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT = 45U , kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT = 46U , kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT = 47U ,
  kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT = 48U , kIOMUXC_FLEXSPI_B_DATA0_SELECT_INPUT = 49U , kIOMUXC_FLEXSPI_B_DATA1_SELECT_INPUT = 50U , kIOMUXC_FLEXSPI_B_DATA2_SELECT_INPUT = 51U ,
  kIOMUXC_FLEXSPI_B_DATA3_SELECT_INPUT = 52U , kIOMUXC_FLEXSPI_A_SCK_SELECT_INPUT = 53U , kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U , kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U ,
  kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U , kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U , kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U , kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U ,
  kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U , kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U , kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U , kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U ,
  kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U , kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U , kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U , kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U ,
  kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U , kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U , kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U , kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U ,
  kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U , kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U , kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U , kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U ,
  kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U , kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U , kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U , kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U ,
  kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U , kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U , kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U , kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U ,
  kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U , kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U , kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U , kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U ,
  kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U , kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U , kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U , kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U ,
  kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U , kIOMUXC_NMI_SELECT_INPUT = 93U , kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U , kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U ,
  kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U , kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U , kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U , kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U ,
  kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U , kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U , kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U , kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U ,
  kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U , kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U , kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U , kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U ,
  kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U , kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U , kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U , kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U ,
  kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U , kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U , kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U , kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U ,
  kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U , kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U , kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U , kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U ,
  kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U , kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U , kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U , kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U ,
  kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U , kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U , kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U , kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U ,
  kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U , kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U , kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U , kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U ,
  kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U , kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U , kIOMUXC_XBAR_INOUT02_SELECT_INPUT = 134U , kIOMUXC_XBAR_INOUT03_SELECT_INPUT = 135U ,
  kIOMUXC_XBAR_INOUT04_SELECT_INPUT = 136U , kIOMUXC_XBAR_INOUT05_SELECT_INPUT = 137U , kIOMUXC_XBAR_INOUT06_SELECT_INPUT = 138U , kIOMUXC_XBAR_INOUT07_SELECT_INPUT = 139U ,
  kIOMUXC_XBAR_INOUT08_SELECT_INPUT = 140U , kIOMUXC_XBAR_INOUT09_SELECT_INPUT = 141U , kIOMUXC_XBAR_INOUT17_SELECT_INPUT = 142U , kIOMUXC_XBAR_INOUT18_SELECT_INPUT = 143U ,
  kIOMUXC_XBAR_INOUT20_SELECT_INPUT = 144U , kIOMUXC_XBAR_INOUT22_SELECT_INPUT = 145U , kIOMUXC_XBAR_INOUT23_SELECT_INPUT = 146U , kIOMUXC_XBAR_INOUT24_SELECT_INPUT = 147U ,
  kIOMUXC_XBAR_INOUT14_SELECT_INPUT = 148U , kIOMUXC_XBAR_INOUT15_SELECT_INPUT = 149U , kIOMUXC_XBAR_INOUT16_SELECT_INPUT = 150U , kIOMUXC_XBAR_INOUT25_SELECT_INPUT = 151U ,
  kIOMUXC_XBAR_INOUT19_SELECT_INPUT = 152U , kIOMUXC_XBAR_INOUT21_SELECT_INPUT = 153U , kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0U , kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 1U ,
  kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 4U , kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 5U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 = 6U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 = 7U ,
  kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT = 8U , kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT = 9U , kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT = 10U , kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT = 11U ,
  kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT = 12U , kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT = 13U , kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT = 14U , kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT = 15U ,
  kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT = 16U , kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT = 17U , kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT = 18U , kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT = 19U ,
  kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT = 20U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 26U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 27U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 28U ,
  kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 29U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 30U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 31U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 = 32U ,
  kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 = 33U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 = 34U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 = 35U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 = 36U ,
  kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 = 37U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 = 38U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 = 39U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 = 40U ,
  kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 = 41U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 = 42U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 = 43U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 = 44U ,
  kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 = 45U , kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT = 46U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 = 47U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 = 48U ,
  kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 = 49U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 = 50U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 = 51U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 = 52U ,
  kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 = 53U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 = 54U , kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT = 55U , kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT = 56U ,
  kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 = 57U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 = 58U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 = 59U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 = 60U ,
  kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT = 61U , kIOMUXC_GPT3_CAPIN1_SELECT_INPUT = 62U , kIOMUXC_GPT3_CAPIN2_SELECT_INPUT = 63U , kIOMUXC_GPT3_CLKIN_SELECT_INPUT = 64U ,
  kIOMUXC_KPP_COL_SELECT_INPUT_6 = 65U , kIOMUXC_KPP_COL_SELECT_INPUT_7 = 66U , kIOMUXC_KPP_ROW_SELECT_INPUT_6 = 67U , kIOMUXC_KPP_ROW_SELECT_INPUT_7 = 68U ,
  kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT = 69U , kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT = 70U , kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT = 71U , kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT = 72U ,
  kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT = 73U , kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT = 74U , kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT = 75U , kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT = 76U ,
  kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 = 77U , kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT = 78U , kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT = 79U , kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT = 80U ,
  kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 = 81U , kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 = 82U , kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT = 83U , kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT = 84U ,
  kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT = 85U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 = 86U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 = 87U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 = 88U ,
  kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 = 89U , kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT = 90U , kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT = 91U , kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT = 92U ,
  kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 = 93U , kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT = 94U , kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT = 95U , kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT = 96U ,
  kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT = 97U , kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT = 98U , kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT = 99U , kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT = 100U ,
  kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT = 101U , kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT = 102U , kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT = 103U , kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT = 104U ,
  kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 105U , kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 106U , kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 107U , kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 108U ,
  kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 109U , kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 110U , kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 111U , kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 112U ,
  kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 113U , kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 114U , kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 115U , kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 116U ,
  kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 117U , kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT = 118U , kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 = 119U , kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT = 120U ,
  kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT = 121U , kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT = 122U , kIOMUXC_EMVSIM1_SIO_SELECT_INPUT = 129U , kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT = 130U ,
  kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT = 131U , kIOMUXC_EMVSIM2_SIO_SELECT_INPUT = 132U , kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT = 133U , kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT = 134U ,
  kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 135U , kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 136U , kIOMUXC_USB_OTG_OC_SELECT_INPUT = 137U , kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 138U ,
  kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 139U , kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 140U , kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 141U , kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 142U ,
  kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 143U , kIOMUXC_XBAR1_IN_SELECT_INPUT_20 = 144U , kIOMUXC_XBAR1_IN_SELECT_INPUT_21 = 145U , kIOMUXC_XBAR1_IN_SELECT_INPUT_22 = 146U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_23 = 147U , kIOMUXC_XBAR1_IN_SELECT_INPUT_24 = 148U , kIOMUXC_XBAR1_IN_SELECT_INPUT_25 = 149U , kIOMUXC_XBAR1_IN_SELECT_INPUT_26 = 150U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_27 = 151U , kIOMUXC_XBAR1_IN_SELECT_INPUT_28 = 152U , kIOMUXC_XBAR1_IN_SELECT_INPUT_29 = 153U , kIOMUXC_XBAR1_IN_SELECT_INPUT_30 = 154U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_31 = 155U , kIOMUXC_XBAR1_IN_SELECT_INPUT_32 = 156U , kIOMUXC_XBAR1_IN_SELECT_INPUT_33 = 157U , kIOMUXC_XBAR1_IN_SELECT_INPUT_34 = 158U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_35 = 159U , kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0U , kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 1U , kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 4U ,
  kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 5U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 = 6U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 = 7U , kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT = 8U ,
  kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT = 9U , kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT = 10U , kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT = 11U , kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT = 12U ,
  kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT = 13U , kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT = 14U , kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT = 15U , kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT = 16U ,
  kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT = 17U , kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT = 18U , kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT = 19U , kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT = 20U ,
  kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 26U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 27U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 28U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 29U ,
  kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 30U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 31U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 = 32U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 = 33U ,
  kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 = 34U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 = 35U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 = 36U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 = 37U ,
  kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 = 38U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 = 39U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 = 40U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 = 41U ,
  kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 = 42U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 = 43U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 = 44U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 = 45U ,
  kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT = 46U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 = 47U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 = 48U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 = 49U ,
  kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 = 50U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 = 51U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 = 52U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 = 53U ,
  kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 = 54U , kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT = 55U , kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT = 56U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 = 57U ,
  kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 = 58U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 = 59U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 = 60U , kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT = 61U ,
  kIOMUXC_GPT3_CAPIN1_SELECT_INPUT = 62U , kIOMUXC_GPT3_CAPIN2_SELECT_INPUT = 63U , kIOMUXC_GPT3_CLKIN_SELECT_INPUT = 64U , kIOMUXC_KPP_COL_SELECT_INPUT_6 = 65U ,
  kIOMUXC_KPP_COL_SELECT_INPUT_7 = 66U , kIOMUXC_KPP_ROW_SELECT_INPUT_6 = 67U , kIOMUXC_KPP_ROW_SELECT_INPUT_7 = 68U , kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT = 69U ,
  kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT = 70U , kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT = 71U , kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT = 72U , kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT = 73U ,
  kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT = 74U , kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT = 75U , kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT = 76U , kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 = 77U ,
  kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT = 78U , kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT = 79U , kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT = 80U , kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 = 81U ,
  kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 = 82U , kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT = 83U , kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT = 84U , kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT = 85U ,
  kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 = 86U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 = 87U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 = 88U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 = 89U ,
  kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT = 90U , kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT = 91U , kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT = 92U , kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 = 93U ,
  kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT = 94U , kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT = 95U , kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT = 96U , kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT = 97U ,
  kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT = 98U , kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT = 99U , kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT = 100U , kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT = 101U ,
  kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT = 102U , kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT = 103U , kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT = 104U , kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 105U ,
  kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 106U , kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 107U , kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 108U , kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 109U ,
  kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 110U , kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 111U , kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 112U , kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 113U ,
  kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 114U , kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 115U , kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 116U , kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 117U ,
  kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT = 118U , kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 = 119U , kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT = 120U , kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT = 121U ,
  kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT = 122U , kIOMUXC_EMVSIM1_SIO_SELECT_INPUT = 129U , kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT = 130U , kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT = 131U ,
  kIOMUXC_EMVSIM2_SIO_SELECT_INPUT = 132U , kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT = 133U , kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT = 134U , kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 135U ,
  kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 136U , kIOMUXC_USB_OTG_OC_SELECT_INPUT = 137U , kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 138U , kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 139U ,
  kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 140U , kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 141U , kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 142U , kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 143U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_20 = 144U , kIOMUXC_XBAR1_IN_SELECT_INPUT_21 = 145U , kIOMUXC_XBAR1_IN_SELECT_INPUT_22 = 146U , kIOMUXC_XBAR1_IN_SELECT_INPUT_23 = 147U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_24 = 148U , kIOMUXC_XBAR1_IN_SELECT_INPUT_25 = 149U , kIOMUXC_XBAR1_IN_SELECT_INPUT_26 = 150U , kIOMUXC_XBAR1_IN_SELECT_INPUT_27 = 151U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_28 = 152U , kIOMUXC_XBAR1_IN_SELECT_INPUT_29 = 153U , kIOMUXC_XBAR1_IN_SELECT_INPUT_30 = 154U , kIOMUXC_XBAR1_IN_SELECT_INPUT_31 = 155U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_32 = 156U , kIOMUXC_XBAR1_IN_SELECT_INPUT_33 = 157U , kIOMUXC_XBAR1_IN_SELECT_INPUT_34 = 158U , kIOMUXC_XBAR1_IN_SELECT_INPUT_35 = 159U
}
 Enumeration for the IOMUXC select input. More...
 
enum  _iomuxc_sw_mux_ctl_pad {
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 = 118U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 = 119U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 = 122U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 = 123U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 = 126U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 = 127U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 = 130U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 = 131U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 = 134U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 = 135U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 = 138U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 = 139U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 = 142U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 = 143U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 = 144U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 = 118U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 = 119U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 = 122U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 = 123U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 = 126U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 = 127U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 = 130U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 = 131U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 = 134U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 = 135U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 = 138U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 = 139U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 = 142U ,
  kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 = 143U , kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 = 144U
}
 Enumeration for the IOMUXC SW_MUX_CTL_PAD. More...
 
enum  _iomuxc_sw_pad_ctl_pad {
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 = 118U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 = 119U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 = 122U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 = 123U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 = 126U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 = 127U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 = 130U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 = 131U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 = 134U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 = 135U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 = 138U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 = 139U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 = 142U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 = 143U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 = 144U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 = 117U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 = 118U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 = 119U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 = 120U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 = 121U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 = 122U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 = 123U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 = 124U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 = 125U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 = 126U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 = 127U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 = 128U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 = 129U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 = 130U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 = 131U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 = 132U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 = 133U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 = 134U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 = 135U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 = 136U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 = 137U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 = 138U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 = 139U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 = 140U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 = 141U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 = 142U ,
  kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 = 143U , kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 = 144U
}
 Enumeration for the IOMUXC SW_PAD_CTL_PAD. More...
 
enum  _iomuxc_select_input {
  kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U , kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U , kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U , kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U ,
  kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U , kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U , kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U , kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U ,
  kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U , kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U , kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U , kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U ,
  kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U , kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U , kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U , kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U ,
  kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U , kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U , kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U , kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U ,
  kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U , kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U , kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U , kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U ,
  kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U , kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U , kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U , kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U ,
  kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U , kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U , kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U , kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U ,
  kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U , kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U , kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U , kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U ,
  kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U , kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U , kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U , kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U ,
  kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U , kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U , kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U , kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U ,
  kIOMUXC_FLEXSPI_A_DQS_SELECT_INPUT = 44U , kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT = 45U , kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT = 46U , kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT = 47U ,
  kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT = 48U , kIOMUXC_FLEXSPI_B_DATA0_SELECT_INPUT = 49U , kIOMUXC_FLEXSPI_B_DATA1_SELECT_INPUT = 50U , kIOMUXC_FLEXSPI_B_DATA2_SELECT_INPUT = 51U ,
  kIOMUXC_FLEXSPI_B_DATA3_SELECT_INPUT = 52U , kIOMUXC_FLEXSPI_A_SCK_SELECT_INPUT = 53U , kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U , kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U ,
  kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U , kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U , kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U , kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U ,
  kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U , kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U , kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U , kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U ,
  kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U , kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U , kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U , kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U ,
  kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U , kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U , kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U , kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U ,
  kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U , kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U , kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U , kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U ,
  kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U , kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U , kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U , kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U ,
  kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U , kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U , kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U , kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U ,
  kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U , kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U , kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U , kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U ,
  kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U , kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U , kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U , kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U ,
  kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U , kIOMUXC_NMI_SELECT_INPUT = 93U , kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U , kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U ,
  kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U , kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U , kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U , kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U ,
  kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U , kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U , kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U , kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U ,
  kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U , kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U , kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U , kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U ,
  kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U , kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U , kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U , kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U ,
  kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U , kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U , kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U , kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U ,
  kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U , kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U , kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U , kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U ,
  kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U , kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U , kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U , kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U ,
  kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U , kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U , kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U , kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U ,
  kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U , kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U , kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U , kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U ,
  kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U , kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U , kIOMUXC_XBAR_INOUT02_SELECT_INPUT = 134U , kIOMUXC_XBAR_INOUT03_SELECT_INPUT = 135U ,
  kIOMUXC_XBAR_INOUT04_SELECT_INPUT = 136U , kIOMUXC_XBAR_INOUT05_SELECT_INPUT = 137U , kIOMUXC_XBAR_INOUT06_SELECT_INPUT = 138U , kIOMUXC_XBAR_INOUT07_SELECT_INPUT = 139U ,
  kIOMUXC_XBAR_INOUT08_SELECT_INPUT = 140U , kIOMUXC_XBAR_INOUT09_SELECT_INPUT = 141U , kIOMUXC_XBAR_INOUT17_SELECT_INPUT = 142U , kIOMUXC_XBAR_INOUT18_SELECT_INPUT = 143U ,
  kIOMUXC_XBAR_INOUT20_SELECT_INPUT = 144U , kIOMUXC_XBAR_INOUT22_SELECT_INPUT = 145U , kIOMUXC_XBAR_INOUT23_SELECT_INPUT = 146U , kIOMUXC_XBAR_INOUT24_SELECT_INPUT = 147U ,
  kIOMUXC_XBAR_INOUT14_SELECT_INPUT = 148U , kIOMUXC_XBAR_INOUT15_SELECT_INPUT = 149U , kIOMUXC_XBAR_INOUT16_SELECT_INPUT = 150U , kIOMUXC_XBAR_INOUT25_SELECT_INPUT = 151U ,
  kIOMUXC_XBAR_INOUT19_SELECT_INPUT = 152U , kIOMUXC_XBAR_INOUT21_SELECT_INPUT = 153U , kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0U , kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 1U ,
  kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 4U , kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 5U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 = 6U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 = 7U ,
  kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT = 8U , kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT = 9U , kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT = 10U , kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT = 11U ,
  kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT = 12U , kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT = 13U , kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT = 14U , kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT = 15U ,
  kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT = 16U , kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT = 17U , kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT = 18U , kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT = 19U ,
  kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT = 20U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 26U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 27U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 28U ,
  kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 29U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 30U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 31U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 = 32U ,
  kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 = 33U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 = 34U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 = 35U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 = 36U ,
  kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 = 37U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 = 38U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 = 39U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 = 40U ,
  kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 = 41U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 = 42U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 = 43U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 = 44U ,
  kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 = 45U , kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT = 46U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 = 47U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 = 48U ,
  kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 = 49U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 = 50U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 = 51U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 = 52U ,
  kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 = 53U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 = 54U , kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT = 55U , kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT = 56U ,
  kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 = 57U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 = 58U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 = 59U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 = 60U ,
  kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT = 61U , kIOMUXC_GPT3_CAPIN1_SELECT_INPUT = 62U , kIOMUXC_GPT3_CAPIN2_SELECT_INPUT = 63U , kIOMUXC_GPT3_CLKIN_SELECT_INPUT = 64U ,
  kIOMUXC_KPP_COL_SELECT_INPUT_6 = 65U , kIOMUXC_KPP_COL_SELECT_INPUT_7 = 66U , kIOMUXC_KPP_ROW_SELECT_INPUT_6 = 67U , kIOMUXC_KPP_ROW_SELECT_INPUT_7 = 68U ,
  kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT = 69U , kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT = 70U , kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT = 71U , kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT = 72U ,
  kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT = 73U , kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT = 74U , kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT = 75U , kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT = 76U ,
  kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 = 77U , kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT = 78U , kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT = 79U , kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT = 80U ,
  kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 = 81U , kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 = 82U , kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT = 83U , kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT = 84U ,
  kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT = 85U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 = 86U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 = 87U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 = 88U ,
  kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 = 89U , kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT = 90U , kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT = 91U , kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT = 92U ,
  kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 = 93U , kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT = 94U , kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT = 95U , kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT = 96U ,
  kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT = 97U , kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT = 98U , kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT = 99U , kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT = 100U ,
  kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT = 101U , kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT = 102U , kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT = 103U , kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT = 104U ,
  kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 105U , kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 106U , kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 107U , kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 108U ,
  kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 109U , kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 110U , kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 111U , kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 112U ,
  kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 113U , kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 114U , kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 115U , kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 116U ,
  kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 117U , kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT = 118U , kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 = 119U , kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT = 120U ,
  kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT = 121U , kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT = 122U , kIOMUXC_EMVSIM1_SIO_SELECT_INPUT = 129U , kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT = 130U ,
  kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT = 131U , kIOMUXC_EMVSIM2_SIO_SELECT_INPUT = 132U , kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT = 133U , kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT = 134U ,
  kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 135U , kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 136U , kIOMUXC_USB_OTG_OC_SELECT_INPUT = 137U , kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 138U ,
  kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 139U , kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 140U , kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 141U , kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 142U ,
  kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 143U , kIOMUXC_XBAR1_IN_SELECT_INPUT_20 = 144U , kIOMUXC_XBAR1_IN_SELECT_INPUT_21 = 145U , kIOMUXC_XBAR1_IN_SELECT_INPUT_22 = 146U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_23 = 147U , kIOMUXC_XBAR1_IN_SELECT_INPUT_24 = 148U , kIOMUXC_XBAR1_IN_SELECT_INPUT_25 = 149U , kIOMUXC_XBAR1_IN_SELECT_INPUT_26 = 150U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_27 = 151U , kIOMUXC_XBAR1_IN_SELECT_INPUT_28 = 152U , kIOMUXC_XBAR1_IN_SELECT_INPUT_29 = 153U , kIOMUXC_XBAR1_IN_SELECT_INPUT_30 = 154U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_31 = 155U , kIOMUXC_XBAR1_IN_SELECT_INPUT_32 = 156U , kIOMUXC_XBAR1_IN_SELECT_INPUT_33 = 157U , kIOMUXC_XBAR1_IN_SELECT_INPUT_34 = 158U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_35 = 159U , kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0U , kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 1U , kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 4U ,
  kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 5U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 = 6U , kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 = 7U , kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT = 8U ,
  kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT = 9U , kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT = 10U , kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT = 11U , kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT = 12U ,
  kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT = 13U , kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT = 14U , kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT = 15U , kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT = 16U ,
  kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT = 17U , kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT = 18U , kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT = 19U , kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT = 20U ,
  kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 26U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 27U , kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 28U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 29U ,
  kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 30U , kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 31U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 = 32U , kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 = 33U ,
  kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 = 34U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 = 35U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 = 36U , kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 = 37U ,
  kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 = 38U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 = 39U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 = 40U , kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 = 41U ,
  kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 = 42U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 = 43U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 = 44U , kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 = 45U ,
  kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT = 46U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 = 47U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 = 48U , kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 = 49U ,
  kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 = 50U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 = 51U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 = 52U , kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 = 53U ,
  kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 = 54U , kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT = 55U , kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT = 56U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 = 57U ,
  kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 = 58U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 = 59U , kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 = 60U , kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT = 61U ,
  kIOMUXC_GPT3_CAPIN1_SELECT_INPUT = 62U , kIOMUXC_GPT3_CAPIN2_SELECT_INPUT = 63U , kIOMUXC_GPT3_CLKIN_SELECT_INPUT = 64U , kIOMUXC_KPP_COL_SELECT_INPUT_6 = 65U ,
  kIOMUXC_KPP_COL_SELECT_INPUT_7 = 66U , kIOMUXC_KPP_ROW_SELECT_INPUT_6 = 67U , kIOMUXC_KPP_ROW_SELECT_INPUT_7 = 68U , kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT = 69U ,
  kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT = 70U , kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT = 71U , kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT = 72U , kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT = 73U ,
  kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT = 74U , kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT = 75U , kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT = 76U , kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 = 77U ,
  kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT = 78U , kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT = 79U , kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT = 80U , kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 = 81U ,
  kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 = 82U , kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT = 83U , kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT = 84U , kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT = 85U ,
  kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 = 86U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 = 87U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 = 88U , kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 = 89U ,
  kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT = 90U , kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT = 91U , kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT = 92U , kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 = 93U ,
  kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT = 94U , kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT = 95U , kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT = 96U , kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT = 97U ,
  kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT = 98U , kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT = 99U , kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT = 100U , kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT = 101U ,
  kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT = 102U , kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT = 103U , kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT = 104U , kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 105U ,
  kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 106U , kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 107U , kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 108U , kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 109U ,
  kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 110U , kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 111U , kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 112U , kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 113U ,
  kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 114U , kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 115U , kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 116U , kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 117U ,
  kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT = 118U , kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 = 119U , kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT = 120U , kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT = 121U ,
  kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT = 122U , kIOMUXC_EMVSIM1_SIO_SELECT_INPUT = 129U , kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT = 130U , kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT = 131U ,
  kIOMUXC_EMVSIM2_SIO_SELECT_INPUT = 132U , kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT = 133U , kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT = 134U , kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 135U ,
  kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 136U , kIOMUXC_USB_OTG_OC_SELECT_INPUT = 137U , kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 138U , kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 139U ,
  kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 140U , kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 141U , kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 142U , kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 143U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_20 = 144U , kIOMUXC_XBAR1_IN_SELECT_INPUT_21 = 145U , kIOMUXC_XBAR1_IN_SELECT_INPUT_22 = 146U , kIOMUXC_XBAR1_IN_SELECT_INPUT_23 = 147U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_24 = 148U , kIOMUXC_XBAR1_IN_SELECT_INPUT_25 = 149U , kIOMUXC_XBAR1_IN_SELECT_INPUT_26 = 150U , kIOMUXC_XBAR1_IN_SELECT_INPUT_27 = 151U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_28 = 152U , kIOMUXC_XBAR1_IN_SELECT_INPUT_29 = 153U , kIOMUXC_XBAR1_IN_SELECT_INPUT_30 = 154U , kIOMUXC_XBAR1_IN_SELECT_INPUT_31 = 155U ,
  kIOMUXC_XBAR1_IN_SELECT_INPUT_32 = 156U , kIOMUXC_XBAR1_IN_SELECT_INPUT_33 = 157U , kIOMUXC_XBAR1_IN_SELECT_INPUT_34 = 158U , kIOMUXC_XBAR1_IN_SELECT_INPUT_35 = 159U
}
 Enumeration for the IOMUXC select input. More...
 

Variables

__IO uint32_t ADC_Type::HC [8]
 
__I uint32_t ADC_Type::HS
 
__I uint32_t ADC_Type::R [8]
 
__IO uint32_t ADC_Type::CFG
 
__IO uint32_t ADC_Type::GC
 
__IO uint32_t ADC_Type::GS
 
__IO uint32_t ADC_Type::CV
 
__IO uint32_t ADC_Type::OFS
 
__IO uint32_t ADC_Type::CAL
 
__IO uint32_t ADC_ETC_Type::CTRL
 
__IO uint32_t ADC_ETC_Type::DONE0_1_IRQ
 
__IO uint32_t ADC_ETC_Type::DONE2_3_ERR_IRQ
 
__IO uint32_t ADC_ETC_Type::DMA_CTRL
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CTRL
 
__IO uint32_t   ADC_ETC_Type::TRIGn_COUNTER
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_1_0
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_3_2
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_5_4
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_7_6
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_1_0
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_3_2
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_5_4
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_7_6
 
struct {
   __IO uint32_t   ADC_ETC_Type::TRIGn_CTRL
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_COUNTER
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_1_0
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_3_2
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_5_4
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_7_6
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_1_0
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_3_2
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_5_4
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_7_6
 
} ADC_ETC_Type::TRIG [8]
 
__IO uint32_t AIPSTZ_Type::MPR
 
uint8_t AIPSTZ_Type::RESERVED_0 [60]
 
__IO uint32_t AIPSTZ_Type::OPACR
 
__IO uint32_t AIPSTZ_Type::OPACR1
 
__IO uint32_t AIPSTZ_Type::OPACR2
 
__IO uint32_t AIPSTZ_Type::OPACR3
 
__IO uint32_t AIPSTZ_Type::OPACR4
 
__IO uint16_t   AOI_Type::BFCRT01
 
__IO uint16_t   AOI_Type::BFCRT23
 
struct {
   __IO uint16_t   AOI_Type::BFCRT01
 
   __IO uint16_t   AOI_Type::BFCRT23
 
} AOI_Type::BFCRT [4]
 
__IO uint32_t BEE_Type::CTRL
 
__IO uint32_t BEE_Type::ADDR_OFFSET0
 
__IO uint32_t BEE_Type::ADDR_OFFSET1
 
__IO uint32_t BEE_Type::AES_KEY0_W0
 
__IO uint32_t BEE_Type::AES_KEY0_W1
 
__IO uint32_t BEE_Type::AES_KEY0_W2
 
__IO uint32_t BEE_Type::AES_KEY0_W3
 
__IO uint32_t BEE_Type::STATUS
 
__O uint32_t BEE_Type::CTR_NONCE0_W0
 
__O uint32_t BEE_Type::CTR_NONCE0_W1
 
__O uint32_t BEE_Type::CTR_NONCE0_W2
 
__O uint32_t BEE_Type::CTR_NONCE0_W3
 
__O uint32_t BEE_Type::CTR_NONCE1_W0
 
__O uint32_t BEE_Type::CTR_NONCE1_W1
 
__O uint32_t BEE_Type::CTR_NONCE1_W2
 
__O uint32_t BEE_Type::CTR_NONCE1_W3
 
__IO uint32_t BEE_Type::REGION1_TOP
 
__IO uint32_t BEE_Type::REGION1_BOT
 
__IO uint32_t CAN_Type::MCR
 
__IO uint32_t CAN_Type::CTRL1
 
__IO uint32_t CAN_Type::TIMER
 
uint8_t CAN_Type::RESERVED_0 [4]
 
__IO uint32_t CAN_Type::RXMGMASK
 
__IO uint32_t CAN_Type::RX14MASK
 
__IO uint32_t CAN_Type::RX15MASK
 
__IO uint32_t CAN_Type::ECR
 
__IO uint32_t CAN_Type::ESR1
 
__IO uint32_t CAN_Type::IMASK2
 
__IO uint32_t CAN_Type::IMASK1
 
__IO uint32_t CAN_Type::IFLAG2
 
__IO uint32_t CAN_Type::IFLAG1
 
__IO uint32_t CAN_Type::CTRL2
 
__I uint32_t CAN_Type::ESR2
 
uint8_t CAN_Type::RESERVED_1 [8]
 
__I uint32_t CAN_Type::CRCR
 
__IO uint32_t CAN_Type::RXFGMASK
 
__I uint32_t CAN_Type::RXFIR
 
uint8_t CAN_Type::RESERVED_2 [8]
 
__I uint32_t CAN_Type::DBG1
 
__I uint32_t CAN_Type::DBG2
 
uint8_t CAN_Type::RESERVED_3 [32]
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD0
 
__IO uint32_t   CAN_Type::WORD1
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD0
 
   __IO uint32_t   CAN_Type::WORD1
 
} CAN_Type::MB [64]
 
uint8_t CAN_Type::RESERVED_4 [1024]
 
__IO uint32_t CAN_Type::RXIMR [64]
 
uint8_t CAN_Type::RESERVED_5 [96]
 
__IO uint32_t CAN_Type::GFWR
 
__IO uint32_t CCM_Type::CCR
 
uint8_t CCM_Type::RESERVED_0 [4]
 
__I uint32_t CCM_Type::CSR
 
__IO uint32_t CCM_Type::CCSR
 
__IO uint32_t CCM_Type::CACRR
 
__IO uint32_t CCM_Type::CBCDR
 
__IO uint32_t CCM_Type::CBCMR
 
__IO uint32_t CCM_Type::CSCMR1
 
__IO uint32_t CCM_Type::CSCMR2
 
__IO uint32_t CCM_Type::CSCDR1
 
__IO uint32_t CCM_Type::CS1CDR
 
__IO uint32_t CCM_Type::CS2CDR
 
__IO uint32_t CCM_Type::CDCDR
 
uint8_t CCM_Type::RESERVED_1 [4]
 
__IO uint32_t CCM_Type::CSCDR2
 
__IO uint32_t CCM_Type::CSCDR3
 
uint8_t CCM_Type::RESERVED_2 [8]
 
__I uint32_t CCM_Type::CDHIPR
 
uint8_t CCM_Type::RESERVED_3 [8]
 
__IO uint32_t CCM_Type::CLPCR
 
__IO uint32_t CCM_Type::CISR
 
__IO uint32_t CCM_Type::CIMR
 
__IO uint32_t CCM_Type::CCOSR
 
__IO uint32_t CCM_Type::CGPR
 
__IO uint32_t CCM_Type::CCGR0
 
__IO uint32_t CCM_Type::CCGR1
 
__IO uint32_t CCM_Type::CCGR2
 
__IO uint32_t CCM_Type::CCGR3
 
__IO uint32_t CCM_Type::CCGR4
 
__IO uint32_t CCM_Type::CCGR5
 
__IO uint32_t CCM_Type::CCGR6
 
uint8_t CCM_Type::RESERVED_4 [4]
 
__IO uint32_t CCM_Type::CMEOR
 
__IO uint32_t CCM_ANALOG_Type::PLL_ARM
 
__IO uint32_t CCM_ANALOG_Type::PLL_ARM_SET
 
__IO uint32_t CCM_ANALOG_Type::PLL_ARM_CLR
 
__IO uint32_t CCM_ANALOG_Type::PLL_ARM_TOG
 
__IO uint32_t CCM_ANALOG_Type::PLL_USB1
 
__IO uint32_t CCM_ANALOG_Type::PLL_USB1_SET
 
__IO uint32_t CCM_ANALOG_Type::PLL_USB1_CLR
 
__IO uint32_t CCM_ANALOG_Type::PLL_USB1_TOG
 
__IO uint32_t CCM_ANALOG_Type::PLL_USB2
 
__IO uint32_t CCM_ANALOG_Type::PLL_USB2_SET
 
__IO uint32_t CCM_ANALOG_Type::PLL_USB2_CLR
 
__IO uint32_t CCM_ANALOG_Type::PLL_USB2_TOG
 
__IO uint32_t CCM_ANALOG_Type::PLL_SYS
 
__IO uint32_t CCM_ANALOG_Type::PLL_SYS_SET
 
__IO uint32_t CCM_ANALOG_Type::PLL_SYS_CLR
 
__IO uint32_t CCM_ANALOG_Type::PLL_SYS_TOG
 
__IO uint32_t CCM_ANALOG_Type::PLL_SYS_SS
 
uint8_t CCM_ANALOG_Type::RESERVED_0 [12]
 
__IO uint32_t CCM_ANALOG_Type::PLL_SYS_NUM
 
uint8_t CCM_ANALOG_Type::RESERVED_1 [12]
 
__IO uint32_t CCM_ANALOG_Type::PLL_SYS_DENOM
 
uint8_t CCM_ANALOG_Type::RESERVED_2 [12]
 
__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO
 
__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_SET
 
__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_CLR
 
__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_TOG
 
__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_NUM
 
uint8_t CCM_ANALOG_Type::RESERVED_3 [12]
 
__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_DENOM
 
uint8_t CCM_ANALOG_Type::RESERVED_4 [12]
 
__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO
 
__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_SET
 
__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_CLR
 
__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_TOG
 
__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_NUM
 
uint8_t CCM_ANALOG_Type::RESERVED_5 [12]
 
__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_DENOM
 
uint8_t CCM_ANALOG_Type::RESERVED_6 [28]
 
__IO uint32_t CCM_ANALOG_Type::PLL_ENET
 
__IO uint32_t CCM_ANALOG_Type::PLL_ENET_SET
 
__IO uint32_t CCM_ANALOG_Type::PLL_ENET_CLR
 
__IO uint32_t CCM_ANALOG_Type::PLL_ENET_TOG
 
__IO uint32_t CCM_ANALOG_Type::PFD_480
 
__IO uint32_t CCM_ANALOG_Type::PFD_480_SET
 
__IO uint32_t CCM_ANALOG_Type::PFD_480_CLR
 
__IO uint32_t CCM_ANALOG_Type::PFD_480_TOG
 
__IO uint32_t CCM_ANALOG_Type::PFD_528
 
__IO uint32_t CCM_ANALOG_Type::PFD_528_SET
 
__IO uint32_t CCM_ANALOG_Type::PFD_528_CLR
 
__IO uint32_t CCM_ANALOG_Type::PFD_528_TOG
 
uint8_t CCM_ANALOG_Type::RESERVED_7 [64]
 
__IO uint32_t CCM_ANALOG_Type::MISC0
 
__IO uint32_t CCM_ANALOG_Type::MISC0_SET
 
__IO uint32_t CCM_ANALOG_Type::MISC0_CLR
 
__IO uint32_t CCM_ANALOG_Type::MISC0_TOG
 
__IO uint32_t CCM_ANALOG_Type::MISC1
 
__IO uint32_t CCM_ANALOG_Type::MISC1_SET
 
__IO uint32_t CCM_ANALOG_Type::MISC1_CLR
 
__IO uint32_t CCM_ANALOG_Type::MISC1_TOG
 
__IO uint32_t CCM_ANALOG_Type::MISC2
 
__IO uint32_t CCM_ANALOG_Type::MISC2_SET
 
__IO uint32_t CCM_ANALOG_Type::MISC2_CLR
 
__IO uint32_t CCM_ANALOG_Type::MISC2_TOG
 
uint8_t CM7_MCM_Type::RESERVED_0 [16]
 
__IO uint32_t CM7_MCM_Type::ISCR
 
__IO uint8_t CMP_Type::CR0
 
__IO uint8_t CMP_Type::CR1
 
__IO uint8_t CMP_Type::FPR
 
__IO uint8_t CMP_Type::SCR
 
__IO uint8_t CMP_Type::DACCR
 
__IO uint8_t CMP_Type::MUXCR
 
__IO uint32_t CSI_Type::CR1
 
__IO uint32_t CSI_Type::CR2
 
__IO uint32_t CSI_Type::CR3
 
__I uint32_t CSI_Type::STATFIFO
 
__I uint32_t CSI_Type::RFIFO
 
__IO uint32_t CSI_Type::RXCNT
 
__IO uint32_t CSI_Type::SR
 
uint8_t CSI_Type::RESERVED_0 [4]
 
__IO uint32_t CSI_Type::DMASA_STATFIFO
 
__IO uint32_t CSI_Type::DMATS_STATFIFO
 
__IO uint32_t CSI_Type::DMASA_FB1
 
__IO uint32_t CSI_Type::DMASA_FB2
 
__IO uint32_t CSI_Type::FBUF_PARA
 
__IO uint32_t CSI_Type::IMAG_PARA
 
uint8_t CSI_Type::RESERVED_1 [16]
 
__IO uint32_t CSI_Type::CR18
 
__IO uint32_t CSI_Type::CR19
 
__IO uint32_t CSU_Type::CSL [32]
 
uint8_t CSU_Type::RESERVED_0 [384]
 
__IO uint32_t CSU_Type::HP0
 
uint8_t CSU_Type::RESERVED_1 [20]
 
__IO uint32_t CSU_Type::SA
 
uint8_t CSU_Type::RESERVED_2 [316]
 
__IO uint32_t CSU_Type::HPCONTROL0
 
__IO uint32_t DCDC_Type::REG0
 
__IO uint32_t DCDC_Type::REG1
 
__IO uint32_t DCDC_Type::REG2
 
__IO uint32_t DCDC_Type::REG3
 
__IO uint32_t DCP_Type::CTRL
 
__IO uint32_t DCP_Type::CTRL_SET
 
__IO uint32_t DCP_Type::CTRL_CLR
 
__IO uint32_t DCP_Type::CTRL_TOG
 
__IO uint32_t DCP_Type::STAT
 
__IO uint32_t DCP_Type::STAT_SET
 
__IO uint32_t DCP_Type::STAT_CLR
 
__IO uint32_t DCP_Type::STAT_TOG
 
__IO uint32_t DCP_Type::CHANNELCTRL
 
__IO uint32_t DCP_Type::CHANNELCTRL_SET
 
__IO uint32_t DCP_Type::CHANNELCTRL_CLR
 
__IO uint32_t DCP_Type::CHANNELCTRL_TOG
 
__IO uint32_t DCP_Type::CAPABILITY0
 
uint8_t DCP_Type::RESERVED_0 [12]
 
__I uint32_t DCP_Type::CAPABILITY1
 
uint8_t DCP_Type::RESERVED_1 [12]
 
__IO uint32_t DCP_Type::CONTEXT
 
uint8_t DCP_Type::RESERVED_2 [12]
 
__IO uint32_t DCP_Type::KEY
 
uint8_t DCP_Type::RESERVED_3 [12]
 
__IO uint32_t DCP_Type::KEYDATA
 
uint8_t DCP_Type::RESERVED_4 [12]
 
__I uint32_t DCP_Type::PACKET0
 
uint8_t DCP_Type::RESERVED_5 [12]
 
__I uint32_t DCP_Type::PACKET1
 
uint8_t DCP_Type::RESERVED_6 [12]
 
__I uint32_t DCP_Type::PACKET2
 
uint8_t DCP_Type::RESERVED_7 [12]
 
__I uint32_t DCP_Type::PACKET3
 
uint8_t DCP_Type::RESERVED_8 [12]
 
__I uint32_t DCP_Type::PACKET4
 
uint8_t DCP_Type::RESERVED_9 [12]
 
__I uint32_t DCP_Type::PACKET5
 
uint8_t DCP_Type::RESERVED_10 [12]
 
__I uint32_t DCP_Type::PACKET6
 
uint8_t DCP_Type::RESERVED_11 [28]
 
__IO uint32_t DCP_Type::CH0CMDPTR
 
uint8_t DCP_Type::RESERVED_12 [12]
 
__IO uint32_t DCP_Type::CH0SEMA
 
uint8_t DCP_Type::RESERVED_13 [12]
 
__IO uint32_t DCP_Type::CH0STAT
 
__IO uint32_t DCP_Type::CH0STAT_SET
 
__IO uint32_t DCP_Type::CH0STAT_CLR
 
__IO uint32_t DCP_Type::CH0STAT_TOG
 
__IO uint32_t DCP_Type::CH0OPTS
 
__IO uint32_t DCP_Type::CH0OPTS_SET
 
__IO uint32_t DCP_Type::CH0OPTS_CLR
 
__IO uint32_t DCP_Type::CH0OPTS_TOG
 
__IO uint32_t DCP_Type::CH1CMDPTR
 
uint8_t DCP_Type::RESERVED_14 [12]
 
__IO uint32_t DCP_Type::CH1SEMA
 
uint8_t DCP_Type::RESERVED_15 [12]
 
__IO uint32_t DCP_Type::CH1STAT
 
__IO uint32_t DCP_Type::CH1STAT_SET
 
__IO uint32_t DCP_Type::CH1STAT_CLR
 
__IO uint32_t DCP_Type::CH1STAT_TOG
 
__IO uint32_t DCP_Type::CH1OPTS
 
__IO uint32_t DCP_Type::CH1OPTS_SET
 
__IO uint32_t DCP_Type::CH1OPTS_CLR
 
__IO uint32_t DCP_Type::CH1OPTS_TOG
 
__IO uint32_t DCP_Type::CH2CMDPTR
 
uint8_t DCP_Type::RESERVED_16 [12]
 
__IO uint32_t DCP_Type::CH2SEMA
 
uint8_t DCP_Type::RESERVED_17 [12]
 
__IO uint32_t DCP_Type::CH2STAT
 
__IO uint32_t DCP_Type::CH2STAT_SET
 
__IO uint32_t DCP_Type::CH2STAT_CLR
 
__IO uint32_t DCP_Type::CH2STAT_TOG
 
__IO uint32_t DCP_Type::CH2OPTS
 
__IO uint32_t DCP_Type::CH2OPTS_SET
 
__IO uint32_t DCP_Type::CH2OPTS_CLR
 
__IO uint32_t DCP_Type::CH2OPTS_TOG
 
__IO uint32_t DCP_Type::CH3CMDPTR
 
uint8_t DCP_Type::RESERVED_18 [12]
 
__IO uint32_t DCP_Type::CH3SEMA
 
uint8_t DCP_Type::RESERVED_19 [12]
 
__IO uint32_t DCP_Type::CH3STAT
 
__IO uint32_t DCP_Type::CH3STAT_SET
 
__IO uint32_t DCP_Type::CH3STAT_CLR
 
__IO uint32_t DCP_Type::CH3STAT_TOG
 
__IO uint32_t DCP_Type::CH3OPTS
 
__IO uint32_t DCP_Type::CH3OPTS_SET
 
__IO uint32_t DCP_Type::CH3OPTS_CLR
 
__IO uint32_t DCP_Type::CH3OPTS_TOG
 
uint8_t DCP_Type::RESERVED_20 [512]
 
__IO uint32_t DCP_Type::DBGSELECT
 
uint8_t DCP_Type::RESERVED_21 [12]
 
__I uint32_t DCP_Type::DBGDATA
 
uint8_t DCP_Type::RESERVED_22 [12]
 
__IO uint32_t DCP_Type::PAGETABLE
 
uint8_t DCP_Type::RESERVED_23 [12]
 
__I uint32_t DCP_Type::VERSION
 
__IO uint32_t DMA_Type::CR
 
__I uint32_t DMA_Type::ES
 
uint8_t DMA_Type::RESERVED_0 [4]
 
__IO uint32_t DMA_Type::ERQ
 
uint8_t DMA_Type::RESERVED_1 [4]
 
__IO uint32_t DMA_Type::EEI
 
__O uint8_t DMA_Type::CEEI
 
__O uint8_t DMA_Type::SEEI
 
__O uint8_t DMA_Type::CERQ
 
__O uint8_t DMA_Type::SERQ
 
__O uint8_t DMA_Type::CDNE
 
__O uint8_t DMA_Type::SSRT
 
__O uint8_t DMA_Type::CERR
 
__O uint8_t DMA_Type::CINT
 
uint8_t DMA_Type::RESERVED_2 [4]
 
__IO uint32_t DMA_Type::INT
 
uint8_t DMA_Type::RESERVED_3 [4]
 
__IO uint32_t DMA_Type::ERR
 
uint8_t DMA_Type::RESERVED_4 [4]
 
__I uint32_t DMA_Type::HRS
 
uint8_t DMA_Type::RESERVED_5 [12]
 
__IO uint32_t DMA_Type::EARS
 
uint8_t DMA_Type::RESERVED_6 [184]
 
__IO uint8_t DMA_Type::DCHPRI3
 
__IO uint8_t DMA_Type::DCHPRI2
 
__IO uint8_t DMA_Type::DCHPRI1
 
__IO uint8_t DMA_Type::DCHPRI0
 
__IO uint8_t DMA_Type::DCHPRI7
 
__IO uint8_t DMA_Type::DCHPRI6
 
__IO uint8_t DMA_Type::DCHPRI5
 
__IO uint8_t DMA_Type::DCHPRI4
 
__IO uint8_t DMA_Type::DCHPRI11
 
__IO uint8_t DMA_Type::DCHPRI10
 
__IO uint8_t DMA_Type::DCHPRI9
 
__IO uint8_t DMA_Type::DCHPRI8
 
__IO uint8_t DMA_Type::DCHPRI15
 
__IO uint8_t DMA_Type::DCHPRI14
 
__IO uint8_t DMA_Type::DCHPRI13
 
__IO uint8_t DMA_Type::DCHPRI12
 
__IO uint8_t DMA_Type::DCHPRI19
 
__IO uint8_t DMA_Type::DCHPRI18
 
__IO uint8_t DMA_Type::DCHPRI17
 
__IO uint8_t DMA_Type::DCHPRI16
 
__IO uint8_t DMA_Type::DCHPRI23
 
__IO uint8_t DMA_Type::DCHPRI22
 
__IO uint8_t DMA_Type::DCHPRI21
 
__IO uint8_t DMA_Type::DCHPRI20
 
__IO uint8_t DMA_Type::DCHPRI27
 
__IO uint8_t DMA_Type::DCHPRI26
 
__IO uint8_t DMA_Type::DCHPRI25
 
__IO uint8_t DMA_Type::DCHPRI24
 
__IO uint8_t DMA_Type::DCHPRI31
 
__IO uint8_t DMA_Type::DCHPRI30
 
__IO uint8_t DMA_Type::DCHPRI29
 
__IO uint8_t DMA_Type::DCHPRI28
 
uint8_t DMA_Type::RESERVED_7 [3808]
 
__IO uint32_t   DMA_Type::SADDR
 
__IO uint16_t   DMA_Type::SOFF
 
__IO uint16_t   DMA_Type::ATTR
 
__IO uint32_t   DMA_Type::NBYTES_MLNO
 
__IO uint32_t   DMA_Type::NBYTES_MLOFFNO
 
__IO uint32_t   DMA_Type::NBYTES_MLOFFYES
 
union {
   __IO uint32_t   DMA_Type::NBYTES_MLNO
 
   __IO uint32_t   DMA_Type::NBYTES_MLOFFNO
 
   __IO uint32_t   DMA_Type::NBYTES_MLOFFYES
 
} 
 
__IO int32_t   DMA_Type::SLAST
 
__IO uint32_t   DMA_Type::DADDR
 
__IO uint16_t   DMA_Type::DOFF
 
__IO uint16_t   DMA_Type::CITER_ELINKNO
 
__IO uint16_t   DMA_Type::CITER_ELINKYES
 
union {
   __IO uint16_t   DMA_Type::CITER_ELINKNO
 
   __IO uint16_t   DMA_Type::CITER_ELINKYES
 
} 
 
__IO int32_t   DMA_Type::DLAST_SGA
 
__IO uint16_t   DMA_Type::CSR
 
__IO uint16_t   DMA_Type::BITER_ELINKNO
 
__IO uint16_t   DMA_Type::BITER_ELINKYES
 
union {
   __IO uint16_t   DMA_Type::BITER_ELINKNO
 
   __IO uint16_t   DMA_Type::BITER_ELINKYES
 
} 
 
struct {
   __IO uint32_t   DMA_Type::SADDR
 
   __IO uint16_t   DMA_Type::SOFF
 
   __IO uint16_t   DMA_Type::ATTR
 
   union {
      __IO uint32_t   DMA_Type::NBYTES_MLNO
 
      __IO uint32_t   DMA_Type::NBYTES_MLOFFNO
 
      __IO uint32_t   DMA_Type::NBYTES_MLOFFYES
 
   } 
 
   __IO int32_t   DMA_Type::SLAST
 
   __IO uint32_t   DMA_Type::DADDR
 
   __IO uint16_t   DMA_Type::DOFF
 
   union {
      __IO uint16_t   DMA_Type::CITER_ELINKNO
 
      __IO uint16_t   DMA_Type::CITER_ELINKYES
 
   } 
 
   __IO int32_t   DMA_Type::DLAST_SGA
 
   __IO uint16_t   DMA_Type::CSR
 
   union {
      __IO uint16_t   DMA_Type::BITER_ELINKNO
 
      __IO uint16_t   DMA_Type::BITER_ELINKYES
 
   } 
 
} DMA_Type::TCD [32]
 
__IO uint32_t DMAMUX_Type::CHCFG [32]
 
__IO uint16_t ENC_Type::CTRL
 
__IO uint16_t ENC_Type::FILT
 
__IO uint16_t ENC_Type::WTR
 
__IO uint16_t ENC_Type::POSD
 
__I uint16_t ENC_Type::POSDH
 
__IO uint16_t ENC_Type::REV
 
__I uint16_t ENC_Type::REVH
 
__IO uint16_t ENC_Type::UPOS
 
__IO uint16_t ENC_Type::LPOS
 
__I uint16_t ENC_Type::UPOSH
 
__I uint16_t ENC_Type::LPOSH
 
__IO uint16_t ENC_Type::UINIT
 
__IO uint16_t ENC_Type::LINIT
 
__I uint16_t ENC_Type::IMR
 
__IO uint16_t ENC_Type::TST
 
__IO uint16_t ENC_Type::CTRL2
 
__IO uint16_t ENC_Type::UMOD
 
__IO uint16_t ENC_Type::LMOD
 
__IO uint16_t ENC_Type::UCOMP
 
__IO uint16_t ENC_Type::LCOMP
 
uint8_t ENET_Type::RESERVED_0 [4]
 
__IO uint32_t ENET_Type::EIR
 
__IO uint32_t ENET_Type::EIMR
 
uint8_t ENET_Type::RESERVED_1 [4]
 
__IO uint32_t ENET_Type::RDAR
 
__IO uint32_t ENET_Type::TDAR
 
uint8_t ENET_Type::RESERVED_2 [12]
 
__IO uint32_t ENET_Type::ECR
 
uint8_t ENET_Type::RESERVED_3 [24]
 
__IO uint32_t ENET_Type::MMFR
 
__IO uint32_t ENET_Type::MSCR
 
uint8_t ENET_Type::RESERVED_4 [28]
 
__IO uint32_t ENET_Type::MIBC
 
uint8_t ENET_Type::RESERVED_5 [28]
 
__IO uint32_t ENET_Type::RCR
 
uint8_t ENET_Type::RESERVED_6 [60]
 
__IO uint32_t ENET_Type::TCR
 
uint8_t ENET_Type::RESERVED_7 [28]
 
__IO uint32_t ENET_Type::PALR
 
__IO uint32_t ENET_Type::PAUR
 
__IO uint32_t ENET_Type::OPD
 
__IO uint32_t ENET_Type::TXIC [1]
 
uint8_t ENET_Type::RESERVED_8 [12]
 
__IO uint32_t ENET_Type::RXIC [1]
 
uint8_t ENET_Type::RESERVED_9 [20]
 
__IO uint32_t ENET_Type::IAUR
 
__IO uint32_t ENET_Type::IALR
 
__IO uint32_t ENET_Type::GAUR
 
__IO uint32_t ENET_Type::GALR
 
uint8_t ENET_Type::RESERVED_10 [28]
 
__IO uint32_t ENET_Type::TFWR
 
uint8_t ENET_Type::RESERVED_11 [56]
 
__IO uint32_t ENET_Type::RDSR
 
__IO uint32_t ENET_Type::TDSR
 
__IO uint32_t ENET_Type::MRBR
 
uint8_t ENET_Type::RESERVED_12 [4]
 
__IO uint32_t ENET_Type::RSFL
 
__IO uint32_t ENET_Type::RSEM
 
__IO uint32_t ENET_Type::RAEM
 
__IO uint32_t ENET_Type::RAFL
 
__IO uint32_t ENET_Type::TSEM
 
__IO uint32_t ENET_Type::TAEM
 
__IO uint32_t ENET_Type::TAFL
 
__IO uint32_t ENET_Type::TIPG
 
__IO uint32_t ENET_Type::FTRL
 
uint8_t ENET_Type::RESERVED_13 [12]
 
__IO uint32_t ENET_Type::TACC
 
__IO uint32_t ENET_Type::RACC
 
uint8_t ENET_Type::RESERVED_14 [60]
 
__I uint32_t ENET_Type::RMON_T_PACKETS
 
__I uint32_t ENET_Type::RMON_T_BC_PKT
 
__I uint32_t ENET_Type::RMON_T_MC_PKT
 
__I uint32_t ENET_Type::RMON_T_CRC_ALIGN
 
__I uint32_t ENET_Type::RMON_T_UNDERSIZE
 
__I uint32_t ENET_Type::RMON_T_OVERSIZE
 
__I uint32_t ENET_Type::RMON_T_FRAG
 
__I uint32_t ENET_Type::RMON_T_JAB
 
__I uint32_t ENET_Type::RMON_T_COL
 
__I uint32_t ENET_Type::RMON_T_P64
 
__I uint32_t ENET_Type::RMON_T_P65TO127
 
__I uint32_t ENET_Type::RMON_T_P128TO255
 
__I uint32_t ENET_Type::RMON_T_P256TO511
 
__I uint32_t ENET_Type::RMON_T_P512TO1023
 
__I uint32_t ENET_Type::RMON_T_P1024TO2047
 
__I uint32_t ENET_Type::RMON_T_P_GTE2048
 
__I uint32_t ENET_Type::RMON_T_OCTETS
 
uint8_t ENET_Type::RESERVED_15 [4]
 
__I uint32_t ENET_Type::IEEE_T_FRAME_OK
 
__I uint32_t ENET_Type::IEEE_T_1COL
 
__I uint32_t ENET_Type::IEEE_T_MCOL
 
__I uint32_t ENET_Type::IEEE_T_DEF
 
__I uint32_t ENET_Type::IEEE_T_LCOL
 
__I uint32_t ENET_Type::IEEE_T_EXCOL
 
__I uint32_t ENET_Type::IEEE_T_MACERR
 
__I uint32_t ENET_Type::IEEE_T_CSERR
 
__I uint32_t ENET_Type::IEEE_T_SQE
 
__I uint32_t ENET_Type::IEEE_T_FDXFC
 
__I uint32_t ENET_Type::IEEE_T_OCTETS_OK
 
uint8_t ENET_Type::RESERVED_16 [12]
 
__I uint32_t ENET_Type::RMON_R_PACKETS
 
__I uint32_t ENET_Type::RMON_R_BC_PKT
 
__I uint32_t ENET_Type::RMON_R_MC_PKT
 
__I uint32_t ENET_Type::RMON_R_CRC_ALIGN
 
__I uint32_t ENET_Type::RMON_R_UNDERSIZE
 
__I uint32_t ENET_Type::RMON_R_OVERSIZE
 
__I uint32_t ENET_Type::RMON_R_FRAG
 
__I uint32_t ENET_Type::RMON_R_JAB
 
uint8_t ENET_Type::RESERVED_17 [4]
 
__I uint32_t ENET_Type::RMON_R_P64
 
__I uint32_t ENET_Type::RMON_R_P65TO127
 
__I uint32_t ENET_Type::RMON_R_P128TO255
 
__I uint32_t ENET_Type::RMON_R_P256TO511
 
__I uint32_t ENET_Type::RMON_R_P512TO1023
 
__I uint32_t ENET_Type::RMON_R_P1024TO2047
 
__I uint32_t ENET_Type::RMON_R_P_GTE2048
 
__I uint32_t ENET_Type::RMON_R_OCTETS
 
__I uint32_t ENET_Type::IEEE_R_DROP
 
__I uint32_t ENET_Type::IEEE_R_FRAME_OK
 
__I uint32_t ENET_Type::IEEE_R_CRC
 
__I uint32_t ENET_Type::IEEE_R_ALIGN
 
__I uint32_t ENET_Type::IEEE_R_MACERR
 
__I uint32_t ENET_Type::IEEE_R_FDXFC
 
__I uint32_t ENET_Type::IEEE_R_OCTETS_OK
 
uint8_t ENET_Type::RESERVED_18 [284]
 
__IO uint32_t ENET_Type::ATCR
 
__IO uint32_t ENET_Type::ATVR
 
__IO uint32_t ENET_Type::ATOFF
 
__IO uint32_t ENET_Type::ATPER
 
__IO uint32_t ENET_Type::ATCOR
 
__IO uint32_t ENET_Type::ATINC
 
__I uint32_t ENET_Type::ATSTMP
 
uint8_t ENET_Type::RESERVED_19 [488]
 
__IO uint32_t ENET_Type::TGSR
 
__IO uint32_t   ENET_Type::TCSR
 
__IO uint32_t   ENET_Type::TCCR
 
struct {
   __IO uint32_t   ENET_Type::TCSR
 
   __IO uint32_t   ENET_Type::TCCR
 
} ENET_Type::CHANNEL [4]
 
__IO uint8_t EWM_Type::CTRL
 
__O uint8_t EWM_Type::SERV
 
__IO uint8_t EWM_Type::CMPL
 
__IO uint8_t EWM_Type::CMPH
 
__IO uint8_t EWM_Type::CLKCTRL
 
__IO uint8_t EWM_Type::CLKPRESCALER
 
__I uint32_t FLEXIO_Type::VERID
 
__I uint32_t FLEXIO_Type::PARAM
 
__IO uint32_t FLEXIO_Type::CTRL
 
__I uint32_t FLEXIO_Type::PIN
 
__IO uint32_t FLEXIO_Type::SHIFTSTAT
 
__IO uint32_t FLEXIO_Type::SHIFTERR
 
__IO uint32_t FLEXIO_Type::TIMSTAT
 
uint8_t FLEXIO_Type::RESERVED_0 [4]
 
__IO uint32_t FLEXIO_Type::SHIFTSIEN
 
__IO uint32_t FLEXIO_Type::SHIFTEIEN
 
__IO uint32_t FLEXIO_Type::TIMIEN
 
uint8_t FLEXIO_Type::RESERVED_1 [4]
 
__IO uint32_t FLEXIO_Type::SHIFTSDEN
 
uint8_t FLEXIO_Type::RESERVED_2 [12]
 
__IO uint32_t FLEXIO_Type::SHIFTSTATE
 
uint8_t FLEXIO_Type::RESERVED_3 [60]
 
__IO uint32_t FLEXIO_Type::SHIFTCTL [4]
 
uint8_t FLEXIO_Type::RESERVED_4 [112]
 
__IO uint32_t FLEXIO_Type::SHIFTCFG [4]
 
uint8_t FLEXIO_Type::RESERVED_5 [240]
 
__IO uint32_t FLEXIO_Type::SHIFTBUF [4]
 
uint8_t FLEXIO_Type::RESERVED_6 [112]
 
__IO uint32_t FLEXIO_Type::SHIFTBUFBIS [4]
 
uint8_t FLEXIO_Type::RESERVED_7 [112]
 
__IO uint32_t FLEXIO_Type::SHIFTBUFBYS [4]
 
uint8_t FLEXIO_Type::RESERVED_8 [112]
 
__IO uint32_t FLEXIO_Type::SHIFTBUFBBS [4]
 
uint8_t FLEXIO_Type::RESERVED_9 [112]
 
__IO uint32_t FLEXIO_Type::TIMCTL [4]
 
uint8_t FLEXIO_Type::RESERVED_10 [112]
 
__IO uint32_t FLEXIO_Type::TIMCFG [4]
 
uint8_t FLEXIO_Type::RESERVED_11 [112]
 
__IO uint32_t FLEXIO_Type::TIMCMP [4]
 
uint8_t FLEXIO_Type::RESERVED_12 [368]
 
__IO uint32_t FLEXIO_Type::SHIFTBUFNBS [4]
 
uint8_t FLEXIO_Type::RESERVED_13 [112]
 
__IO uint32_t FLEXIO_Type::SHIFTBUFHWS [4]
 
uint8_t FLEXIO_Type::RESERVED_14 [112]
 
__IO uint32_t FLEXIO_Type::SHIFTBUFNIS [4]
 
__IO uint32_t FLEXRAM_Type::TCM_CTRL
 
uint8_t FLEXRAM_Type::RESERVED_0 [12]
 
__IO uint32_t FLEXRAM_Type::INT_STATUS
 
__IO uint32_t FLEXRAM_Type::INT_STAT_EN
 
__IO uint32_t FLEXRAM_Type::INT_SIG_EN
 
__IO uint32_t FLEXSPI_Type::MCR0
 
__IO uint32_t FLEXSPI_Type::MCR1
 
__IO uint32_t FLEXSPI_Type::MCR2
 
__IO uint32_t FLEXSPI_Type::AHBCR
 
__IO uint32_t FLEXSPI_Type::INTEN
 
__IO uint32_t FLEXSPI_Type::INTR
 
__IO uint32_t FLEXSPI_Type::LUTKEY
 
__IO uint32_t FLEXSPI_Type::LUTCR
 
__IO uint32_t FLEXSPI_Type::AHBRXBUFCR0 [4]
 
uint8_t FLEXSPI_Type::RESERVED_0 [48]
 
__IO uint32_t FLEXSPI_Type::FLSHCR0 [4]
 
__IO uint32_t FLEXSPI_Type::FLSHCR1 [4]
 
__IO uint32_t FLEXSPI_Type::FLSHCR2 [4]
 
uint8_t FLEXSPI_Type::RESERVED_1 [4]
 
__IO uint32_t FLEXSPI_Type::FLSHCR4
 
uint8_t FLEXSPI_Type::RESERVED_2 [8]
 
__IO uint32_t FLEXSPI_Type::IPCR0
 
__IO uint32_t FLEXSPI_Type::IPCR1
 
uint8_t FLEXSPI_Type::RESERVED_3 [8]
 
__IO uint32_t FLEXSPI_Type::IPCMD
 
uint8_t FLEXSPI_Type::RESERVED_4 [4]
 
__IO uint32_t FLEXSPI_Type::IPRXFCR
 
__IO uint32_t FLEXSPI_Type::IPTXFCR
 
__IO uint32_t FLEXSPI_Type::DLLCR [2]
 
uint8_t FLEXSPI_Type::RESERVED_5 [24]
 
__I uint32_t FLEXSPI_Type::STS0
 
__I uint32_t FLEXSPI_Type::STS1
 
__I uint32_t FLEXSPI_Type::STS2
 
__I uint32_t FLEXSPI_Type::AHBSPNDSTS
 
__I uint32_t FLEXSPI_Type::IPRXFSTS
 
__I uint32_t FLEXSPI_Type::IPTXFSTS
 
uint8_t FLEXSPI_Type::RESERVED_6 [8]
 
__I uint32_t FLEXSPI_Type::RFDR [32]
 
__O uint32_t FLEXSPI_Type::TFDR [32]
 
__IO uint32_t FLEXSPI_Type::LUT [64]
 
__IO uint32_t GPC_Type::CNTR
 
uint8_t GPC_Type::RESERVED_0 [4]
 
__IO uint32_t GPC_Type::IMR [4]
 
__I uint32_t GPC_Type::ISR [4]
 
uint8_t GPC_Type::RESERVED_1 [12]
 
__IO uint32_t GPC_Type::IMR5
 
__I uint32_t GPC_Type::ISR5
 
__IO uint32_t GPIO_Type::DR
 
__IO uint32_t GPIO_Type::GDIR
 
__I uint32_t GPIO_Type::PSR
 
__IO uint32_t GPIO_Type::ICR1
 
__IO uint32_t GPIO_Type::ICR2
 
__IO uint32_t GPIO_Type::IMR
 
__IO uint32_t GPIO_Type::ISR
 
__IO uint32_t GPIO_Type::EDGE_SEL
 
uint8_t GPIO_Type::RESERVED_0 [100]
 
__O uint32_t GPIO_Type::DR_SET
 
__O uint32_t GPIO_Type::DR_CLEAR
 
__O uint32_t GPIO_Type::DR_TOGGLE
 
__IO uint32_t GPT_Type::CR
 
__IO uint32_t GPT_Type::PR
 
__IO uint32_t GPT_Type::SR
 
__IO uint32_t GPT_Type::IR
 
__IO uint32_t GPT_Type::OCR [3]
 
__I uint32_t GPT_Type::ICR [2]
 
__I uint32_t GPT_Type::CNT
 
__I uint32_t I2S_Type::VERID
 
__I uint32_t I2S_Type::PARAM
 
__IO uint32_t I2S_Type::TCSR
 
__IO uint32_t I2S_Type::TCR1
 
__IO uint32_t I2S_Type::TCR2
 
__IO uint32_t I2S_Type::TCR3
 
__IO uint32_t I2S_Type::TCR4
 
__IO uint32_t I2S_Type::TCR5
 
__O uint32_t I2S_Type::TDR [4]
 
uint8_t I2S_Type::RESERVED_0 [16]
 
__I uint32_t I2S_Type::TFR [4]
 
uint8_t I2S_Type::RESERVED_1 [16]
 
__IO uint32_t I2S_Type::TMR
 
uint8_t I2S_Type::RESERVED_2 [36]
 
__IO uint32_t I2S_Type::RCSR
 
__IO uint32_t I2S_Type::RCR1
 
__IO uint32_t I2S_Type::RCR2
 
__IO uint32_t I2S_Type::RCR3
 
__IO uint32_t I2S_Type::RCR4
 
__IO uint32_t I2S_Type::RCR5
 
__I uint32_t I2S_Type::RDR [4]
 
uint8_t I2S_Type::RESERVED_3 [16]
 
__I uint32_t I2S_Type::RFR [4]
 
uint8_t I2S_Type::RESERVED_4 [16]
 
__IO uint32_t I2S_Type::RMR
 
uint8_t IOMUXC_Type::RESERVED_0 [20]
 
__IO uint32_t IOMUXC_Type::SW_MUX_CTL_PAD [124]
 
__IO uint32_t IOMUXC_Type::SW_PAD_CTL_PAD [124]
 
__IO uint32_t IOMUXC_Type::SELECT_INPUT [154]
 
uint32_t IOMUXC_GPR_Type::GPR0
 
__IO uint32_t IOMUXC_GPR_Type::GPR1
 
__IO uint32_t IOMUXC_GPR_Type::GPR2
 
__IO uint32_t IOMUXC_GPR_Type::GPR3
 
__IO uint32_t IOMUXC_GPR_Type::GPR4
 
__IO uint32_t IOMUXC_GPR_Type::GPR5
 
__IO uint32_t IOMUXC_GPR_Type::GPR6
 
__IO uint32_t IOMUXC_GPR_Type::GPR7
 
__IO uint32_t IOMUXC_GPR_Type::GPR8
 
uint32_t IOMUXC_GPR_Type::GPR9
 
__IO uint32_t IOMUXC_GPR_Type::GPR10
 
__IO uint32_t IOMUXC_GPR_Type::GPR11
 
__IO uint32_t IOMUXC_GPR_Type::GPR12
 
__IO uint32_t IOMUXC_GPR_Type::GPR13
 
__IO uint32_t IOMUXC_GPR_Type::GPR14
 
uint32_t IOMUXC_GPR_Type::GPR15
 
__IO uint32_t IOMUXC_GPR_Type::GPR16
 
__IO uint32_t IOMUXC_GPR_Type::GPR17
 
__IO uint32_t IOMUXC_GPR_Type::GPR18
 
__IO uint32_t IOMUXC_GPR_Type::GPR19
 
__IO uint32_t IOMUXC_GPR_Type::GPR20
 
__IO uint32_t IOMUXC_GPR_Type::GPR21
 
__IO uint32_t IOMUXC_GPR_Type::GPR22
 
__IO uint32_t IOMUXC_GPR_Type::GPR23
 
__IO uint32_t IOMUXC_GPR_Type::GPR24
 
__IO uint32_t IOMUXC_GPR_Type::GPR25
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_WAKEUP
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_ON_REQ
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_STBY_REQ
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_TEST_MODE
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_POR_B
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_ONOFF
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_WAKEUP
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_ON_REQ
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_STBY_REQ
 
uint32_t IOMUXC_SNVS_GPR_Type::GPR0
 
uint32_t IOMUXC_SNVS_GPR_Type::GPR1
 
uint32_t IOMUXC_SNVS_GPR_Type::GPR2
 
__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR3
 
__IO uint16_t KPP_Type::KPCR
 
__IO uint16_t KPP_Type::KPSR
 
__IO uint16_t KPP_Type::KDDR
 
__IO uint16_t KPP_Type::KPDR
 
__IO uint32_t LCDIF_Type::CTRL
 
__IO uint32_t LCDIF_Type::CTRL_SET
 
__IO uint32_t LCDIF_Type::CTRL_CLR
 
__IO uint32_t LCDIF_Type::CTRL_TOG
 
__IO uint32_t LCDIF_Type::CTRL1
 
__IO uint32_t LCDIF_Type::CTRL1_SET
 
__IO uint32_t LCDIF_Type::CTRL1_CLR
 
__IO uint32_t LCDIF_Type::CTRL1_TOG
 
__IO uint32_t LCDIF_Type::CTRL2
 
__IO uint32_t LCDIF_Type::CTRL2_SET
 
__IO uint32_t LCDIF_Type::CTRL2_CLR
 
__IO uint32_t LCDIF_Type::CTRL2_TOG
 
__IO uint32_t LCDIF_Type::TRANSFER_COUNT
 
uint8_t LCDIF_Type::RESERVED_0 [12]
 
__IO uint32_t LCDIF_Type::CUR_BUF
 
uint8_t LCDIF_Type::RESERVED_1 [12]
 
__IO uint32_t LCDIF_Type::NEXT_BUF
 
uint8_t LCDIF_Type::RESERVED_2 [28]
 
__IO uint32_t LCDIF_Type::VDCTRL0
 
__IO uint32_t LCDIF_Type::VDCTRL0_SET
 
__IO uint32_t LCDIF_Type::VDCTRL0_CLR
 
__IO uint32_t LCDIF_Type::VDCTRL0_TOG
 
__IO uint32_t LCDIF_Type::VDCTRL1
 
uint8_t LCDIF_Type::RESERVED_3 [12]
 
__IO uint32_t LCDIF_Type::VDCTRL2
 
uint8_t LCDIF_Type::RESERVED_4 [12]
 
__IO uint32_t LCDIF_Type::VDCTRL3
 
uint8_t LCDIF_Type::RESERVED_5 [12]
 
__IO uint32_t LCDIF_Type::VDCTRL4
 
uint8_t LCDIF_Type::RESERVED_6 [220]
 
__IO uint32_t LCDIF_Type::BM_ERROR_STAT
 
uint8_t LCDIF_Type::RESERVED_7 [12]
 
__IO uint32_t LCDIF_Type::CRC_STAT
 
uint8_t LCDIF_Type::RESERVED_8 [12]
 
__I uint32_t LCDIF_Type::STAT
 
uint8_t LCDIF_Type::RESERVED_9 [236]
 
__IO uint32_t LCDIF_Type::RGB_ADJUST
 
__IO uint32_t LCDIF_Type::RGB_ADJUST_SET
 
__IO uint32_t LCDIF_Type::RGB_ADJUST_CLR
 
__IO uint32_t LCDIF_Type::RGB_ADJUST_TOG
 
uint8_t LCDIF_Type::RESERVED_10 [208]
 
__IO uint32_t LCDIF_Type::PIGEONCTRL0
 
__IO uint32_t LCDIF_Type::PIGEONCTRL0_SET
 
__IO uint32_t LCDIF_Type::PIGEONCTRL0_CLR
 
__IO uint32_t LCDIF_Type::PIGEONCTRL0_TOG
 
__IO uint32_t LCDIF_Type::PIGEONCTRL1
 
__IO uint32_t LCDIF_Type::PIGEONCTRL1_SET
 
__IO uint32_t LCDIF_Type::PIGEONCTRL1_CLR
 
__IO uint32_t LCDIF_Type::PIGEONCTRL1_TOG
 
__IO uint32_t LCDIF_Type::PIGEONCTRL2
 
__IO uint32_t LCDIF_Type::PIGEONCTRL2_SET
 
__IO uint32_t LCDIF_Type::PIGEONCTRL2_CLR
 
__IO uint32_t LCDIF_Type::PIGEONCTRL2_TOG
 
uint8_t LCDIF_Type::RESERVED_11 [1104]
 
__IO uint32_t   LCDIF_Type::PIGEON_0
 
uint8_t   LCDIF_Type::RESERVED_0 [12]
 
__IO uint32_t   LCDIF_Type::PIGEON_1
 
uint8_t   LCDIF_Type::RESERVED_1 [12]
 
__IO uint32_t   LCDIF_Type::PIGEON_2
 
uint8_t   LCDIF_Type::RESERVED_2 [28]
 
struct {
   __IO uint32_t   LCDIF_Type::PIGEON_0
 
   uint8_t   RESERVED_0 [12]
 
   __IO uint32_t   LCDIF_Type::PIGEON_1
 
   uint8_t   RESERVED_1 [12]
 
   __IO uint32_t   LCDIF_Type::PIGEON_2
 
   uint8_t   RESERVED_2 [28]
 
} LCDIF_Type::PIGEON [12]
 
__IO uint32_t LCDIF_Type::LUT_CTRL
 
uint8_t LCDIF_Type::RESERVED_12 [12]
 
__IO uint32_t LCDIF_Type::LUT0_ADDR
 
uint8_t LCDIF_Type::RESERVED_13 [12]
 
__IO uint32_t LCDIF_Type::LUT0_DATA
 
uint8_t LCDIF_Type::RESERVED_14 [12]
 
__IO uint32_t LCDIF_Type::LUT1_ADDR
 
uint8_t LCDIF_Type::RESERVED_15 [12]
 
__IO uint32_t LCDIF_Type::LUT1_DATA
 
__I uint32_t LPI2C_Type::VERID
 
__I uint32_t LPI2C_Type::PARAM
 
uint8_t LPI2C_Type::RESERVED_0 [8]
 
__IO uint32_t LPI2C_Type::MCR
 
__IO uint32_t LPI2C_Type::MSR
 
__IO uint32_t LPI2C_Type::MIER
 
__IO uint32_t LPI2C_Type::MDER
 
__IO uint32_t LPI2C_Type::MCFGR0
 
__IO uint32_t LPI2C_Type::MCFGR1
 
__IO uint32_t LPI2C_Type::MCFGR2
 
__IO uint32_t LPI2C_Type::MCFGR3
 
uint8_t LPI2C_Type::RESERVED_1 [16]
 
__IO uint32_t LPI2C_Type::MDMR
 
uint8_t LPI2C_Type::RESERVED_2 [4]
 
__IO uint32_t LPI2C_Type::MCCR0
 
uint8_t LPI2C_Type::RESERVED_3 [4]
 
__IO uint32_t LPI2C_Type::MCCR1
 
uint8_t LPI2C_Type::RESERVED_4 [4]
 
__IO uint32_t LPI2C_Type::MFCR
 
__I uint32_t LPI2C_Type::MFSR
 
__O uint32_t LPI2C_Type::MTDR
 
uint8_t LPI2C_Type::RESERVED_5 [12]
 
__I uint32_t LPI2C_Type::MRDR
 
uint8_t LPI2C_Type::RESERVED_6 [156]
 
__IO uint32_t LPI2C_Type::SCR
 
__IO uint32_t LPI2C_Type::SSR
 
__IO uint32_t LPI2C_Type::SIER
 
__IO uint32_t LPI2C_Type::SDER
 
uint8_t LPI2C_Type::RESERVED_7 [4]
 
__IO uint32_t LPI2C_Type::SCFGR1
 
__IO uint32_t LPI2C_Type::SCFGR2
 
uint8_t LPI2C_Type::RESERVED_8 [20]
 
__IO uint32_t LPI2C_Type::SAMR
 
uint8_t LPI2C_Type::RESERVED_9 [12]
 
__I uint32_t LPI2C_Type::SASR
 
__IO uint32_t LPI2C_Type::STAR
 
uint8_t LPI2C_Type::RESERVED_10 [8]
 
__O uint32_t LPI2C_Type::STDR
 
uint8_t LPI2C_Type::RESERVED_11 [12]
 
__I uint32_t LPI2C_Type::SRDR
 
__I uint32_t LPSPI_Type::VERID
 
__I uint32_t LPSPI_Type::PARAM
 
uint8_t LPSPI_Type::RESERVED_0 [8]
 
__IO uint32_t LPSPI_Type::CR
 
__IO uint32_t LPSPI_Type::SR
 
__IO uint32_t LPSPI_Type::IER
 
__IO uint32_t LPSPI_Type::DER
 
__IO uint32_t LPSPI_Type::CFGR0
 
__IO uint32_t LPSPI_Type::CFGR1
 
uint8_t LPSPI_Type::RESERVED_1 [8]
 
__IO uint32_t LPSPI_Type::DMR0
 
__IO uint32_t LPSPI_Type::DMR1
 
uint8_t LPSPI_Type::RESERVED_2 [8]
 
__IO uint32_t LPSPI_Type::CCR
 
uint8_t LPSPI_Type::RESERVED_3 [20]
 
__IO uint32_t LPSPI_Type::FCR
 
__I uint32_t LPSPI_Type::FSR
 
__IO uint32_t LPSPI_Type::TCR
 
__O uint32_t LPSPI_Type::TDR
 
uint8_t LPSPI_Type::RESERVED_4 [8]
 
__I uint32_t LPSPI_Type::RSR
 
__I uint32_t LPSPI_Type::RDR
 
__I uint32_t LPUART_Type::VERID
 
__I uint32_t LPUART_Type::PARAM
 
__IO uint32_t LPUART_Type::GLOBAL
 
__IO uint32_t LPUART_Type::PINCFG
 
__IO uint32_t LPUART_Type::BAUD
 
__IO uint32_t LPUART_Type::STAT
 
__IO uint32_t LPUART_Type::CTRL
 
__IO uint32_t LPUART_Type::DATA
 
__IO uint32_t LPUART_Type::MATCH
 
__IO uint32_t LPUART_Type::MODIR
 
__IO uint32_t LPUART_Type::FIFO
 
__IO uint32_t LPUART_Type::WATER
 
__IO uint32_t OCOTP_Type::CTRL
 
__IO uint32_t OCOTP_Type::CTRL_SET
 
__IO uint32_t OCOTP_Type::CTRL_CLR
 
__IO uint32_t OCOTP_Type::CTRL_TOG
 
__IO uint32_t OCOTP_Type::TIMING
 
uint8_t OCOTP_Type::RESERVED_0 [12]
 
__IO uint32_t OCOTP_Type::DATA
 
uint8_t OCOTP_Type::RESERVED_1 [12]
 
__IO uint32_t OCOTP_Type::READ_CTRL
 
uint8_t OCOTP_Type::RESERVED_2 [12]
 
__IO uint32_t OCOTP_Type::READ_FUSE_DATA
 
uint8_t OCOTP_Type::RESERVED_3 [12]
 
__IO uint32_t OCOTP_Type::SW_STICKY
 
uint8_t OCOTP_Type::RESERVED_4 [12]
 
__IO uint32_t OCOTP_Type::SCS
 
__IO uint32_t OCOTP_Type::SCS_SET
 
__IO uint32_t OCOTP_Type::SCS_CLR
 
__IO uint32_t OCOTP_Type::SCS_TOG
 
uint8_t OCOTP_Type::RESERVED_5 [32]
 
__I uint32_t OCOTP_Type::VERSION
 
uint8_t OCOTP_Type::RESERVED_6 [108]
 
__IO uint32_t OCOTP_Type::TIMING2
 
uint8_t OCOTP_Type::RESERVED_7 [764]
 
__IO uint32_t OCOTP_Type::LOCK
 
uint8_t OCOTP_Type::RESERVED_8 [12]
 
__IO uint32_t OCOTP_Type::CFG0
 
uint8_t OCOTP_Type::RESERVED_9 [12]
 
__IO uint32_t OCOTP_Type::CFG1
 
uint8_t OCOTP_Type::RESERVED_10 [12]
 
__IO uint32_t OCOTP_Type::CFG2
 
uint8_t OCOTP_Type::RESERVED_11 [12]
 
__IO uint32_t OCOTP_Type::CFG3
 
uint8_t OCOTP_Type::RESERVED_12 [12]
 
__IO uint32_t OCOTP_Type::CFG4
 
uint8_t OCOTP_Type::RESERVED_13 [12]
 
__IO uint32_t OCOTP_Type::CFG5
 
uint8_t OCOTP_Type::RESERVED_14 [12]
 
__IO uint32_t OCOTP_Type::CFG6
 
uint8_t OCOTP_Type::RESERVED_15 [12]
 
__IO uint32_t OCOTP_Type::MEM0
 
uint8_t OCOTP_Type::RESERVED_16 [12]
 
__IO uint32_t OCOTP_Type::MEM1
 
uint8_t OCOTP_Type::RESERVED_17 [12]
 
__IO uint32_t OCOTP_Type::MEM2
 
uint8_t OCOTP_Type::RESERVED_18 [12]
 
__IO uint32_t OCOTP_Type::MEM3
 
uint8_t OCOTP_Type::RESERVED_19 [12]
 
__IO uint32_t OCOTP_Type::MEM4
 
uint8_t OCOTP_Type::RESERVED_20 [12]
 
__IO uint32_t OCOTP_Type::ANA0
 
uint8_t OCOTP_Type::RESERVED_21 [12]
 
__IO uint32_t OCOTP_Type::ANA1
 
uint8_t OCOTP_Type::RESERVED_22 [12]
 
__IO uint32_t OCOTP_Type::ANA2
 
uint8_t OCOTP_Type::RESERVED_23 [140]
 
__IO uint32_t OCOTP_Type::SRK0
 
uint8_t OCOTP_Type::RESERVED_24 [12]
 
__IO uint32_t OCOTP_Type::SRK1
 
uint8_t OCOTP_Type::RESERVED_25 [12]
 
__IO uint32_t OCOTP_Type::SRK2
 
uint8_t OCOTP_Type::RESERVED_26 [12]
 
__IO uint32_t OCOTP_Type::SRK3
 
uint8_t OCOTP_Type::RESERVED_27 [12]
 
__IO uint32_t OCOTP_Type::SRK4
 
uint8_t OCOTP_Type::RESERVED_28 [12]
 
__IO uint32_t OCOTP_Type::SRK5
 
uint8_t OCOTP_Type::RESERVED_29 [12]
 
__IO uint32_t OCOTP_Type::SRK6
 
uint8_t OCOTP_Type::RESERVED_30 [12]
 
__IO uint32_t OCOTP_Type::SRK7
 
uint8_t OCOTP_Type::RESERVED_31 [12]
 
__IO uint32_t OCOTP_Type::SJC_RESP0
 
uint8_t OCOTP_Type::RESERVED_32 [12]
 
__IO uint32_t OCOTP_Type::SJC_RESP1
 
uint8_t OCOTP_Type::RESERVED_33 [12]
 
__IO uint32_t OCOTP_Type::MAC0
 
uint8_t OCOTP_Type::RESERVED_34 [12]
 
__IO uint32_t OCOTP_Type::MAC1
 
uint8_t OCOTP_Type::RESERVED_35 [12]
 
__IO uint32_t OCOTP_Type::GP3
 
uint8_t OCOTP_Type::RESERVED_36 [28]
 
__IO uint32_t OCOTP_Type::GP1
 
uint8_t OCOTP_Type::RESERVED_37 [12]
 
__IO uint32_t OCOTP_Type::GP2
 
uint8_t OCOTP_Type::RESERVED_38 [12]
 
__IO uint32_t OCOTP_Type::SW_GP1
 
uint8_t OCOTP_Type::RESERVED_39 [12]
 
__IO uint32_t OCOTP_Type::SW_GP20
 
uint8_t OCOTP_Type::RESERVED_40 [12]
 
__IO uint32_t OCOTP_Type::SW_GP21
 
uint8_t OCOTP_Type::RESERVED_41 [12]
 
__IO uint32_t OCOTP_Type::SW_GP22
 
uint8_t OCOTP_Type::RESERVED_42 [12]
 
__IO uint32_t OCOTP_Type::SW_GP23
 
uint8_t OCOTP_Type::RESERVED_43 [12]
 
__IO uint32_t OCOTP_Type::MISC_CONF0
 
uint8_t OCOTP_Type::RESERVED_44 [12]
 
__IO uint32_t OCOTP_Type::MISC_CONF1
 
uint8_t OCOTP_Type::RESERVED_45 [12]
 
__IO uint32_t OCOTP_Type::SRK_REVOKE
 
uint8_t PGC_Type::RESERVED_0 [544]
 
__IO uint32_t PGC_Type::MEGA_CTRL
 
__IO uint32_t PGC_Type::MEGA_PUPSCR
 
__IO uint32_t PGC_Type::MEGA_PDNSCR
 
__IO uint32_t PGC_Type::MEGA_SR
 
uint8_t PGC_Type::RESERVED_1 [112]
 
__IO uint32_t PGC_Type::CPU_CTRL
 
__IO uint32_t PGC_Type::CPU_PUPSCR
 
__IO uint32_t PGC_Type::CPU_PDNSCR
 
__IO uint32_t PGC_Type::CPU_SR
 
__IO uint32_t PIT_Type::MCR
 
uint8_t PIT_Type::RESERVED_0 [220]
 
__I uint32_t PIT_Type::LTMR64H
 
__I uint32_t PIT_Type::LTMR64L
 
uint8_t PIT_Type::RESERVED_1 [24]
 
__IO uint32_t   PIT_Type::LDVAL
 
__I uint32_t   PIT_Type::CVAL
 
__IO uint32_t   PIT_Type::TCTRL
 
__IO uint32_t   PIT_Type::TFLG
 
struct {
   __IO uint32_t   PIT_Type::LDVAL
 
   __I uint32_t   PIT_Type::CVAL
 
   __IO uint32_t   PIT_Type::TCTRL
 
   __IO uint32_t   PIT_Type::TFLG
 
} PIT_Type::CHANNEL [4]
 
uint8_t PMU_Type::RESERVED_0 [272]
 
__IO uint32_t PMU_Type::REG_1P1
 
__IO uint32_t PMU_Type::REG_1P1_SET
 
__IO uint32_t PMU_Type::REG_1P1_CLR
 
__IO uint32_t PMU_Type::REG_1P1_TOG
 
__IO uint32_t PMU_Type::REG_3P0
 
__IO uint32_t PMU_Type::REG_3P0_SET
 
__IO uint32_t PMU_Type::REG_3P0_CLR
 
__IO uint32_t PMU_Type::REG_3P0_TOG
 
__IO uint32_t PMU_Type::REG_2P5
 
__IO uint32_t PMU_Type::REG_2P5_SET
 
__IO uint32_t PMU_Type::REG_2P5_CLR
 
__IO uint32_t PMU_Type::REG_2P5_TOG
 
__IO uint32_t PMU_Type::REG_CORE
 
__IO uint32_t PMU_Type::REG_CORE_SET
 
__IO uint32_t PMU_Type::REG_CORE_CLR
 
__IO uint32_t PMU_Type::REG_CORE_TOG
 
__IO uint32_t PMU_Type::MISC0
 
__IO uint32_t PMU_Type::MISC0_SET
 
__IO uint32_t PMU_Type::MISC0_CLR
 
__IO uint32_t PMU_Type::MISC0_TOG
 
__IO uint32_t PMU_Type::MISC1
 
__IO uint32_t PMU_Type::MISC1_SET
 
__IO uint32_t PMU_Type::MISC1_CLR
 
__IO uint32_t PMU_Type::MISC1_TOG
 
__IO uint32_t PMU_Type::MISC2
 
__IO uint32_t PMU_Type::MISC2_SET
 
__IO uint32_t PMU_Type::MISC2_CLR
 
__IO uint32_t PMU_Type::MISC2_TOG
 
__I uint16_t   PWM_Type::CNT
 
__IO uint16_t   PWM_Type::INIT
 
__IO uint16_t   PWM_Type::CTRL2
 
__IO uint16_t   PWM_Type::CTRL
 
uint8_t   PWM_Type::RESERVED_0 [2]
 
__IO uint16_t   PWM_Type::VAL0
 
__IO uint16_t   PWM_Type::FRACVAL1
 
__IO uint16_t   PWM_Type::VAL1
 
__IO uint16_t   PWM_Type::FRACVAL2
 
__IO uint16_t   PWM_Type::VAL2
 
__IO uint16_t   PWM_Type::FRACVAL3
 
__IO uint16_t   PWM_Type::VAL3
 
__IO uint16_t   PWM_Type::FRACVAL4
 
__IO uint16_t   PWM_Type::VAL4
 
__IO uint16_t   PWM_Type::FRACVAL5
 
__IO uint16_t   PWM_Type::VAL5
 
__IO uint16_t   PWM_Type::FRCTRL
 
__IO uint16_t   PWM_Type::OCTRL
 
__IO uint16_t   PWM_Type::STS
 
__IO uint16_t   PWM_Type::INTEN
 
__IO uint16_t   PWM_Type::DMAEN
 
__IO uint16_t   PWM_Type::TCTRL
 
__IO uint16_t   PWM_Type::DISMAP [2]
 
__IO uint16_t   PWM_Type::DTCNT0
 
__IO uint16_t   PWM_Type::DTCNT1
 
__IO uint16_t   PWM_Type::CAPTCTRLA
 
__IO uint16_t   PWM_Type::CAPTCOMPA
 
__IO uint16_t   PWM_Type::CAPTCTRLB
 
__IO uint16_t   PWM_Type::CAPTCOMPB
 
__IO uint16_t   PWM_Type::CAPTCTRLX
 
__IO uint16_t   PWM_Type::CAPTCOMPX
 
__I uint16_t   PWM_Type::CVAL0
 
__I uint16_t   PWM_Type::CVAL0CYC
 
__I uint16_t   PWM_Type::CVAL1
 
__I uint16_t   PWM_Type::CVAL1CYC
 
__I uint16_t   PWM_Type::CVAL2
 
__I uint16_t   PWM_Type::CVAL2CYC
 
__I uint16_t   PWM_Type::CVAL3
 
__I uint16_t   PWM_Type::CVAL3CYC
 
__I uint16_t   PWM_Type::CVAL4
 
__I uint16_t   PWM_Type::CVAL4CYC
 
__I uint16_t   PWM_Type::CVAL5
 
__I uint16_t   PWM_Type::CVAL5CYC
 
uint8_t   PWM_Type::RESERVED_1 [8]
 
struct {
   __I uint16_t   PWM_Type::CNT
 
   __IO uint16_t   PWM_Type::INIT
 
   __IO uint16_t   PWM_Type::CTRL2
 
   __IO uint16_t   PWM_Type::CTRL
 
   uint8_t   RESERVED_0 [2]
 
   __IO uint16_t   PWM_Type::VAL0
 
   __IO uint16_t   PWM_Type::FRACVAL1
 
   __IO uint16_t   PWM_Type::VAL1
 
   __IO uint16_t   PWM_Type::FRACVAL2
 
   __IO uint16_t   PWM_Type::VAL2
 
   __IO uint16_t   PWM_Type::FRACVAL3
 
   __IO uint16_t   PWM_Type::VAL3
 
   __IO uint16_t   PWM_Type::FRACVAL4
 
   __IO uint16_t   PWM_Type::VAL4
 
   __IO uint16_t   PWM_Type::FRACVAL5
 
   __IO uint16_t   PWM_Type::VAL5
 
   __IO uint16_t   PWM_Type::FRCTRL
 
   __IO uint16_t   PWM_Type::OCTRL
 
   __IO uint16_t   PWM_Type::STS
 
   __IO uint16_t   PWM_Type::INTEN
 
   __IO uint16_t   PWM_Type::DMAEN
 
   __IO uint16_t   PWM_Type::TCTRL
 
   __IO uint16_t   PWM_Type::DISMAP [2]
 
   __IO uint16_t   PWM_Type::DTCNT0
 
   __IO uint16_t   PWM_Type::DTCNT1
 
   __IO uint16_t   PWM_Type::CAPTCTRLA
 
   __IO uint16_t   PWM_Type::CAPTCOMPA
 
   __IO uint16_t   PWM_Type::CAPTCTRLB
 
   __IO uint16_t   PWM_Type::CAPTCOMPB
 
   __IO uint16_t   PWM_Type::CAPTCTRLX
 
   __IO uint16_t   PWM_Type::CAPTCOMPX
 
   __I uint16_t   PWM_Type::CVAL0
 
   __I uint16_t   PWM_Type::CVAL0CYC
 
   __I uint16_t   PWM_Type::CVAL1
 
   __I uint16_t   PWM_Type::CVAL1CYC
 
   __I uint16_t   PWM_Type::CVAL2
 
   __I uint16_t   PWM_Type::CVAL2CYC
 
   __I uint16_t   PWM_Type::CVAL3
 
   __I uint16_t   PWM_Type::CVAL3CYC
 
   __I uint16_t   PWM_Type::CVAL4
 
   __I uint16_t   PWM_Type::CVAL4CYC
 
   __I uint16_t   PWM_Type::CVAL5
 
   __I uint16_t   PWM_Type::CVAL5CYC
 
   uint8_t   RESERVED_1 [8]
 
} PWM_Type::SM [4]
 
__IO uint16_t PWM_Type::OUTEN
 
__IO uint16_t PWM_Type::MASK
 
__IO uint16_t PWM_Type::SWCOUT
 
__IO uint16_t PWM_Type::DTSRCSEL
 
__IO uint16_t PWM_Type::MCTRL
 
__IO uint16_t PWM_Type::MCTRL2
 
__IO uint16_t PWM_Type::FCTRL
 
__IO uint16_t PWM_Type::FSTS
 
__IO uint16_t PWM_Type::FFILT
 
__IO uint16_t PWM_Type::FTST
 
__IO uint16_t PWM_Type::FCTRL2
 
__IO uint32_t PXP_Type::CTRL
 
__IO uint32_t PXP_Type::CTRL_SET
 
__IO uint32_t PXP_Type::CTRL_CLR
 
__IO uint32_t PXP_Type::CTRL_TOG
 
__IO uint32_t PXP_Type::STAT
 
__IO uint32_t PXP_Type::STAT_SET
 
__IO uint32_t PXP_Type::STAT_CLR
 
__IO uint32_t PXP_Type::STAT_TOG
 
__IO uint32_t PXP_Type::OUT_CTRL
 
__IO uint32_t PXP_Type::OUT_CTRL_SET
 
__IO uint32_t PXP_Type::OUT_CTRL_CLR
 
__IO uint32_t PXP_Type::OUT_CTRL_TOG
 
__IO uint32_t PXP_Type::OUT_BUF
 
uint8_t PXP_Type::RESERVED_0 [12]
 
__IO uint32_t PXP_Type::OUT_BUF2
 
uint8_t PXP_Type::RESERVED_1 [12]
 
__IO uint32_t PXP_Type::OUT_PITCH
 
uint8_t PXP_Type::RESERVED_2 [12]
 
__IO uint32_t PXP_Type::OUT_LRC
 
uint8_t PXP_Type::RESERVED_3 [12]
 
__IO uint32_t PXP_Type::OUT_PS_ULC
 
uint8_t PXP_Type::RESERVED_4 [12]
 
__IO uint32_t PXP_Type::OUT_PS_LRC
 
uint8_t PXP_Type::RESERVED_5 [12]
 
__IO uint32_t PXP_Type::OUT_AS_ULC
 
uint8_t PXP_Type::RESERVED_6 [12]
 
__IO uint32_t PXP_Type::OUT_AS_LRC
 
uint8_t PXP_Type::RESERVED_7 [12]
 
__IO uint32_t PXP_Type::PS_CTRL
 
__IO uint32_t PXP_Type::PS_CTRL_SET
 
__IO uint32_t PXP_Type::PS_CTRL_CLR
 
__IO uint32_t PXP_Type::PS_CTRL_TOG
 
__IO uint32_t PXP_Type::PS_BUF
 
uint8_t PXP_Type::RESERVED_8 [12]
 
__IO uint32_t PXP_Type::PS_UBUF
 
uint8_t PXP_Type::RESERVED_9 [12]
 
__IO uint32_t PXP_Type::PS_VBUF
 
uint8_t PXP_Type::RESERVED_10 [12]
 
__IO uint32_t PXP_Type::PS_PITCH
 
uint8_t PXP_Type::RESERVED_11 [12]
 
__IO uint32_t PXP_Type::PS_BACKGROUND
 
uint8_t PXP_Type::RESERVED_12 [12]
 
__IO uint32_t PXP_Type::PS_SCALE
 
uint8_t PXP_Type::RESERVED_13 [12]
 
__IO uint32_t PXP_Type::PS_OFFSET
 
uint8_t PXP_Type::RESERVED_14 [12]
 
__IO uint32_t PXP_Type::PS_CLRKEYLOW
 
uint8_t PXP_Type::RESERVED_15 [12]
 
__IO uint32_t PXP_Type::PS_CLRKEYHIGH
 
uint8_t PXP_Type::RESERVED_16 [12]
 
__IO uint32_t PXP_Type::AS_CTRL
 
uint8_t PXP_Type::RESERVED_17 [12]
 
__IO uint32_t PXP_Type::AS_BUF
 
uint8_t PXP_Type::RESERVED_18 [12]
 
__IO uint32_t PXP_Type::AS_PITCH
 
uint8_t PXP_Type::RESERVED_19 [12]
 
__IO uint32_t PXP_Type::AS_CLRKEYLOW
 
uint8_t PXP_Type::RESERVED_20 [12]
 
__IO uint32_t PXP_Type::AS_CLRKEYHIGH
 
uint8_t PXP_Type::RESERVED_21 [12]
 
__IO uint32_t PXP_Type::CSC1_COEF0
 
uint8_t PXP_Type::RESERVED_22 [12]
 
__IO uint32_t PXP_Type::CSC1_COEF1
 
uint8_t PXP_Type::RESERVED_23 [12]
 
__IO uint32_t PXP_Type::CSC1_COEF2
 
uint8_t PXP_Type::RESERVED_24 [348]
 
__IO uint32_t PXP_Type::POWER
 
uint8_t PXP_Type::RESERVED_25 [220]
 
__IO uint32_t PXP_Type::NEXT
 
uint8_t PXP_Type::RESERVED_26 [60]
 
__IO uint32_t PXP_Type::PORTER_DUFF_CTRL
 
uint8_t ROMC_Type::RESERVED_0 [212]
 
__IO uint32_t ROMC_Type::ROMPATCHD [8]
 
__IO uint32_t ROMC_Type::ROMPATCHCNTL
 
uint32_t ROMC_Type::ROMPATCHENH
 
__IO uint32_t ROMC_Type::ROMPATCHENL
 
__IO uint32_t ROMC_Type::ROMPATCHA [16]
 
uint8_t ROMC_Type::RESERVED_1 [200]
 
__IO uint32_t ROMC_Type::ROMPATCHSR
 
__IO uint32_t RTWDOG_Type::CS
 
__IO uint32_t RTWDOG_Type::CNT
 
__IO uint32_t RTWDOG_Type::TOVAL
 
__IO uint32_t RTWDOG_Type::WIN
 
__IO uint32_t SEMC_Type::MCR
 
__IO uint32_t SEMC_Type::IOCR
 
__IO uint32_t SEMC_Type::BMCR0
 
__IO uint32_t SEMC_Type::BMCR1
 
__IO uint32_t SEMC_Type::BR [9]
 
uint8_t SEMC_Type::RESERVED_0 [4]
 
__IO uint32_t SEMC_Type::INTEN
 
__IO uint32_t SEMC_Type::INTR
 
__IO uint32_t SEMC_Type::SDRAMCR0
 
__IO uint32_t SEMC_Type::SDRAMCR1
 
__IO uint32_t SEMC_Type::SDRAMCR2
 
__IO uint32_t SEMC_Type::SDRAMCR3
 
__IO uint32_t SEMC_Type::NANDCR0
 
__IO uint32_t SEMC_Type::NANDCR1
 
__IO uint32_t SEMC_Type::NANDCR2
 
__IO uint32_t SEMC_Type::NANDCR3
 
__IO uint32_t SEMC_Type::NORCR0
 
__IO uint32_t SEMC_Type::NORCR1
 
__IO uint32_t SEMC_Type::NORCR2
 
uint32_t SEMC_Type::NORCR3
 
__IO uint32_t SEMC_Type::SRAMCR0
 
__IO uint32_t SEMC_Type::SRAMCR1
 
__IO uint32_t SEMC_Type::SRAMCR2
 
uint32_t SEMC_Type::SRAMCR3
 
__IO uint32_t SEMC_Type::DBICR0
 
__IO uint32_t SEMC_Type::DBICR1
 
uint8_t SEMC_Type::RESERVED_1 [8]
 
__IO uint32_t SEMC_Type::IPCR0
 
__IO uint32_t SEMC_Type::IPCR1
 
__IO uint32_t SEMC_Type::IPCR2
 
__IO uint32_t SEMC_Type::IPCMD
 
__IO uint32_t SEMC_Type::IPTXDAT
 
uint8_t SEMC_Type::RESERVED_2 [12]
 
__I uint32_t SEMC_Type::IPRXDAT
 
uint8_t SEMC_Type::RESERVED_3 [12]
 
__I uint32_t SEMC_Type::STS0
 
uint32_t SEMC_Type::STS1
 
__I uint32_t SEMC_Type::STS2
 
uint32_t SEMC_Type::STS3
 
uint32_t SEMC_Type::STS4
 
uint32_t SEMC_Type::STS5
 
uint32_t SEMC_Type::STS6
 
uint32_t SEMC_Type::STS7
 
uint32_t SEMC_Type::STS8
 
uint32_t SEMC_Type::STS9
 
uint32_t SEMC_Type::STS10
 
uint32_t SEMC_Type::STS11
 
__I uint32_t SEMC_Type::STS12
 
uint32_t SEMC_Type::STS13
 
uint32_t SEMC_Type::STS14
 
uint32_t SEMC_Type::STS15
 
__IO uint32_t SNVS_Type::HPLR
 
__IO uint32_t SNVS_Type::HPCOMR
 
__IO uint32_t SNVS_Type::HPCR
 
__IO uint32_t SNVS_Type::HPSICR
 
__IO uint32_t SNVS_Type::HPSVCR
 
__IO uint32_t SNVS_Type::HPSR
 
__IO uint32_t SNVS_Type::HPSVSR
 
__IO uint32_t SNVS_Type::HPHACIVR
 
__I uint32_t SNVS_Type::HPHACR
 
__IO uint32_t SNVS_Type::HPRTCMR
 
__IO uint32_t SNVS_Type::HPRTCLR
 
__IO uint32_t SNVS_Type::HPTAMR
 
__IO uint32_t SNVS_Type::HPTALR
 
__IO uint32_t SNVS_Type::LPLR
 
__IO uint32_t SNVS_Type::LPCR
 
__IO uint32_t SNVS_Type::LPMKCR
 
__IO uint32_t SNVS_Type::LPSVCR
 
uint8_t SNVS_Type::RESERVED_0 [4]
 
__IO uint32_t SNVS_Type::LPSECR
 
__IO uint32_t SNVS_Type::LPSR
 
__IO uint32_t SNVS_Type::LPSRTCMR
 
__IO uint32_t SNVS_Type::LPSRTCLR
 
__IO uint32_t SNVS_Type::LPTAR
 
__IO uint32_t SNVS_Type::LPSMCMR
 
__IO uint32_t SNVS_Type::LPSMCLR
 
__IO uint32_t SNVS_Type::LPLVDR
 
__IO uint32_t SNVS_Type::LPGPR0_LEGACY_ALIAS
 
__IO uint32_t SNVS_Type::LPZMKR [8]
 
uint8_t SNVS_Type::RESERVED_1 [4]
 
__IO uint32_t SNVS_Type::LPGPR_ALIAS [4]
 
uint8_t SNVS_Type::RESERVED_2 [96]
 
__IO uint32_t SNVS_Type::LPGPR [8]
 
uint8_t SNVS_Type::RESERVED_3 [2776]
 
__I uint32_t SNVS_Type::HPVIDR1
 
__I uint32_t SNVS_Type::HPVIDR2
 
__IO uint32_t SPDIF_Type::SCR
 
__IO uint32_t SPDIF_Type::SRCD
 
__IO uint32_t SPDIF_Type::SRPC
 
__IO uint32_t SPDIF_Type::SIE
 
__O uint32_t   SPDIF_Type::SIC
 
__I uint32_t   SPDIF_Type::SIS
 
union {
   __O uint32_t   SPDIF_Type::SIC
 
   __I uint32_t   SPDIF_Type::SIS
 
}; 
 
__I uint32_t SPDIF_Type::SRL
 
__I uint32_t SPDIF_Type::SRR
 
__I uint32_t SPDIF_Type::SRCSH
 
__I uint32_t SPDIF_Type::SRCSL
 
__I uint32_t SPDIF_Type::SRU
 
__I uint32_t SPDIF_Type::SRQ
 
__O uint32_t SPDIF_Type::STL
 
__O uint32_t SPDIF_Type::STR
 
__IO uint32_t SPDIF_Type::STCSCH
 
__IO uint32_t SPDIF_Type::STCSCL
 
uint8_t SPDIF_Type::RESERVED_0 [8]
 
__I uint32_t SPDIF_Type::SRFM
 
uint8_t SPDIF_Type::RESERVED_1 [8]
 
__IO uint32_t SPDIF_Type::STC
 
__IO uint32_t SRC_Type::SCR
 
__I uint32_t SRC_Type::SBMR1
 
__IO uint32_t SRC_Type::SRSR
 
uint8_t SRC_Type::RESERVED_0 [16]
 
__I uint32_t SRC_Type::SBMR2
 
__IO uint32_t SRC_Type::GPR [10]
 
uint8_t TEMPMON_Type::RESERVED_0 [384]
 
__IO uint32_t TEMPMON_Type::TEMPSENSE0
 
__IO uint32_t TEMPMON_Type::TEMPSENSE0_SET
 
__IO uint32_t TEMPMON_Type::TEMPSENSE0_CLR
 
__IO uint32_t TEMPMON_Type::TEMPSENSE0_TOG
 
__IO uint32_t TEMPMON_Type::TEMPSENSE1
 
__IO uint32_t TEMPMON_Type::TEMPSENSE1_SET
 
__IO uint32_t TEMPMON_Type::TEMPSENSE1_CLR
 
__IO uint32_t TEMPMON_Type::TEMPSENSE1_TOG
 
uint8_t TEMPMON_Type::RESERVED_1 [240]
 
__IO uint32_t TEMPMON_Type::TEMPSENSE2
 
__IO uint32_t TEMPMON_Type::TEMPSENSE2_SET
 
__IO uint32_t TEMPMON_Type::TEMPSENSE2_CLR
 
__IO uint32_t TEMPMON_Type::TEMPSENSE2_TOG
 
__IO uint16_t   TMR_Type::COMP1
 
__IO uint16_t   TMR_Type::COMP2
 
__IO uint16_t   TMR_Type::CAPT
 
__IO uint16_t   TMR_Type::LOAD
 
__IO uint16_t   TMR_Type::HOLD
 
__IO uint16_t   TMR_Type::CNTR
 
__IO uint16_t   TMR_Type::CTRL
 
__IO uint16_t   TMR_Type::SCTRL
 
__IO uint16_t   TMR_Type::CMPLD1
 
__IO uint16_t   TMR_Type::CMPLD2
 
__IO uint16_t   TMR_Type::CSCTRL
 
__IO uint16_t   TMR_Type::FILT
 
__IO uint16_t   TMR_Type::DMA
 
uint8_t   TMR_Type::RESERVED_0 [4]
 
__IO uint16_t   TMR_Type::ENBL
 
struct {
   __IO uint16_t   TMR_Type::COMP1
 
   __IO uint16_t   TMR_Type::COMP2
 
   __IO uint16_t   TMR_Type::CAPT
 
   __IO uint16_t   TMR_Type::LOAD
 
   __IO uint16_t   TMR_Type::HOLD
 
   __IO uint16_t   TMR_Type::CNTR
 
   __IO uint16_t   TMR_Type::CTRL
 
   __IO uint16_t   TMR_Type::SCTRL
 
   __IO uint16_t   TMR_Type::CMPLD1
 
   __IO uint16_t   TMR_Type::CMPLD2
 
   __IO uint16_t   TMR_Type::CSCTRL
 
   __IO uint16_t   TMR_Type::FILT
 
   __IO uint16_t   TMR_Type::DMA
 
   uint8_t   RESERVED_0 [4]
 
   __IO uint16_t   TMR_Type::ENBL
 
} TMR_Type::CHANNEL [4]
 
__IO uint32_t TRNG_Type::MCTL
 
__IO uint32_t TRNG_Type::SCMISC
 
__IO uint32_t TRNG_Type::PKRRNG
 
__IO uint32_t   TRNG_Type::PKRMAX
 
__I uint32_t   TRNG_Type::PKRSQ
 
union {
   __IO uint32_t   TRNG_Type::PKRMAX
 
   __I uint32_t   TRNG_Type::PKRSQ
 
}; 
 
__IO uint32_t TRNG_Type::SDCTL
 
__IO uint32_t   TRNG_Type::SBLIM
 
__I uint32_t   TRNG_Type::TOTSAM
 
union {
   __IO uint32_t   TRNG_Type::SBLIM
 
   __I uint32_t   TRNG_Type::TOTSAM
 
}; 
 
__IO uint32_t TRNG_Type::FRQMIN
 
__I uint32_t   TRNG_Type::FRQCNT
 
__IO uint32_t   TRNG_Type::FRQMAX
 
union {
   __I uint32_t   TRNG_Type::FRQCNT
 
   __IO uint32_t   TRNG_Type::FRQMAX
 
}; 
 
__I uint32_t   TRNG_Type::SCMC
 
__IO uint32_t   TRNG_Type::SCML
 
union {
   __I uint32_t   TRNG_Type::SCMC
 
   __IO uint32_t   TRNG_Type::SCML
 
}; 
 
__I uint32_t   TRNG_Type::SCR1C
 
__IO uint32_t   TRNG_Type::SCR1L
 
union {
   __I uint32_t   TRNG_Type::SCR1C
 
   __IO uint32_t   TRNG_Type::SCR1L
 
}; 
 
__I uint32_t   TRNG_Type::SCR2C
 
__IO uint32_t   TRNG_Type::SCR2L
 
union {
   __I uint32_t   TRNG_Type::SCR2C
 
   __IO uint32_t   TRNG_Type::SCR2L
 
}; 
 
__I uint32_t   TRNG_Type::SCR3C
 
__IO uint32_t   TRNG_Type::SCR3L
 
union {
   __I uint32_t   TRNG_Type::SCR3C
 
   __IO uint32_t   TRNG_Type::SCR3L
 
}; 
 
__I uint32_t   TRNG_Type::SCR4C
 
__IO uint32_t   TRNG_Type::SCR4L
 
union {
   __I uint32_t   TRNG_Type::SCR4C
 
   __IO uint32_t   TRNG_Type::SCR4L
 
}; 
 
__I uint32_t   TRNG_Type::SCR5C
 
__IO uint32_t   TRNG_Type::SCR5L
 
union {
   __I uint32_t   TRNG_Type::SCR5C
 
   __IO uint32_t   TRNG_Type::SCR5L
 
}; 
 
__I uint32_t   TRNG_Type::SCR6PC
 
__IO uint32_t   TRNG_Type::SCR6PL
 
union {
   __I uint32_t   TRNG_Type::SCR6PC
 
   __IO uint32_t   TRNG_Type::SCR6PL
 
}; 
 
__I uint32_t TRNG_Type::STATUS
 
__I uint32_t TRNG_Type::ENT [16]
 
__I uint32_t TRNG_Type::PKRCNT10
 
__I uint32_t TRNG_Type::PKRCNT32
 
__I uint32_t TRNG_Type::PKRCNT54
 
__I uint32_t TRNG_Type::PKRCNT76
 
__I uint32_t TRNG_Type::PKRCNT98
 
__I uint32_t TRNG_Type::PKRCNTBA
 
__I uint32_t TRNG_Type::PKRCNTDC
 
__I uint32_t TRNG_Type::PKRCNTFE
 
__IO uint32_t TRNG_Type::SEC_CFG
 
__IO uint32_t TRNG_Type::INT_CTRL
 
__IO uint32_t TRNG_Type::INT_MASK
 
__I uint32_t TRNG_Type::INT_STATUS
 
uint8_t TRNG_Type::RESERVED_0 [64]
 
__I uint32_t TRNG_Type::VID1
 
__I uint32_t TRNG_Type::VID2
 
__IO uint32_t TSC_Type::BASIC_SETTING
 
uint8_t TSC_Type::RESERVED_0 [12]
 
__IO uint32_t TSC_Type::PRE_CHARGE_TIME
 
uint8_t TSC_Type::RESERVED_1 [12]
 
__IO uint32_t TSC_Type::FLOW_CONTROL
 
uint8_t TSC_Type::RESERVED_2 [12]
 
__I uint32_t TSC_Type::MEASEURE_VALUE
 
uint8_t TSC_Type::RESERVED_3 [12]
 
__IO uint32_t TSC_Type::INT_EN
 
uint8_t TSC_Type::RESERVED_4 [12]
 
__IO uint32_t TSC_Type::INT_SIG_EN
 
uint8_t TSC_Type::RESERVED_5 [12]
 
__IO uint32_t TSC_Type::INT_STATUS
 
uint8_t TSC_Type::RESERVED_6 [12]
 
__IO uint32_t TSC_Type::DEBUG_MODE
 
uint8_t TSC_Type::RESERVED_7 [12]
 
__IO uint32_t TSC_Type::DEBUG_MODE2
 
__I uint32_t USB_Type::ID
 
__I uint32_t USB_Type::HWGENERAL
 
__I uint32_t USB_Type::HWHOST
 
__I uint32_t USB_Type::HWDEVICE
 
__I uint32_t USB_Type::HWTXBUF
 
__I uint32_t USB_Type::HWRXBUF
 
uint8_t USB_Type::RESERVED_0 [104]
 
__IO uint32_t USB_Type::GPTIMER0LD
 
__IO uint32_t USB_Type::GPTIMER0CTRL
 
__IO uint32_t USB_Type::GPTIMER1LD
 
__IO uint32_t USB_Type::GPTIMER1CTRL
 
__IO uint32_t USB_Type::SBUSCFG
 
uint8_t USB_Type::RESERVED_1 [108]
 
__I uint8_t USB_Type::CAPLENGTH
 
uint8_t USB_Type::RESERVED_2 [1]
 
__I uint16_t USB_Type::HCIVERSION
 
__I uint32_t USB_Type::HCSPARAMS
 
__I uint32_t USB_Type::HCCPARAMS
 
uint8_t USB_Type::RESERVED_3 [20]
 
__I uint16_t USB_Type::DCIVERSION
 
uint8_t USB_Type::RESERVED_4 [2]
 
__I uint32_t USB_Type::DCCPARAMS
 
uint8_t USB_Type::RESERVED_5 [24]
 
__IO uint32_t USB_Type::USBCMD
 
__IO uint32_t USB_Type::USBSTS
 
__IO uint32_t USB_Type::USBINTR
 
__IO uint32_t USB_Type::FRINDEX
 
uint8_t USB_Type::RESERVED_6 [4]
 
__IO uint32_t   USB_Type::DEVICEADDR
 
__IO uint32_t   USB_Type::PERIODICLISTBASE
 
union {
   __IO uint32_t   USB_Type::DEVICEADDR
 
   __IO uint32_t   USB_Type::PERIODICLISTBASE
 
}; 
 
__IO uint32_t   USB_Type::ASYNCLISTADDR
 
__IO uint32_t   USB_Type::ENDPTLISTADDR
 
union {
   __IO uint32_t   USB_Type::ASYNCLISTADDR
 
   __IO uint32_t   USB_Type::ENDPTLISTADDR
 
}; 
 
uint8_t USB_Type::RESERVED_7 [4]
 
__IO uint32_t USB_Type::BURSTSIZE
 
__IO uint32_t USB_Type::TXFILLTUNING
 
uint8_t USB_Type::RESERVED_8 [16]
 
__IO uint32_t USB_Type::ENDPTNAK
 
__IO uint32_t USB_Type::ENDPTNAKEN
 
__I uint32_t USB_Type::CONFIGFLAG
 
__IO uint32_t USB_Type::PORTSC1
 
uint8_t USB_Type::RESERVED_9 [28]
 
__IO uint32_t USB_Type::OTGSC
 
__IO uint32_t USB_Type::USBMODE
 
__IO uint32_t USB_Type::ENDPTSETUPSTAT
 
__IO uint32_t USB_Type::ENDPTPRIME
 
__IO uint32_t USB_Type::ENDPTFLUSH
 
__I uint32_t USB_Type::ENDPTSTAT
 
__IO uint32_t USB_Type::ENDPTCOMPLETE
 
__IO uint32_t USB_Type::ENDPTCTRL0
 
__IO uint32_t USB_Type::ENDPTCTRL [7]
 
uint8_t USBNC_Type::RESERVED_0 [2048]
 
__IO uint32_t USBNC_Type::USB_OTGn_CTRL
 
uint8_t USBNC_Type::RESERVED_1 [20]
 
__IO uint32_t USBNC_Type::USB_OTGn_PHY_CTRL_0
 
__IO uint32_t USBPHY_Type::PWD
 
__IO uint32_t USBPHY_Type::PWD_SET
 
__IO uint32_t USBPHY_Type::PWD_CLR
 
__IO uint32_t USBPHY_Type::PWD_TOG
 
__IO uint32_t USBPHY_Type::TX
 
__IO uint32_t USBPHY_Type::TX_SET
 
__IO uint32_t USBPHY_Type::TX_CLR
 
__IO uint32_t USBPHY_Type::TX_TOG
 
__IO uint32_t USBPHY_Type::RX
 
__IO uint32_t USBPHY_Type::RX_SET
 
__IO uint32_t USBPHY_Type::RX_CLR
 
__IO uint32_t USBPHY_Type::RX_TOG
 
__IO uint32_t USBPHY_Type::CTRL
 
__IO uint32_t USBPHY_Type::CTRL_SET
 
__IO uint32_t USBPHY_Type::CTRL_CLR
 
__IO uint32_t USBPHY_Type::CTRL_TOG
 
__IO uint32_t USBPHY_Type::STATUS
 
uint8_t USBPHY_Type::RESERVED_0 [12]
 
__IO uint32_t USBPHY_Type::DEBUGr
 
__IO uint32_t USBPHY_Type::DEBUG_SET
 
__IO uint32_t USBPHY_Type::DEBUG_CLR
 
__IO uint32_t USBPHY_Type::DEBUG_TOG
 
__I uint32_t USBPHY_Type::DEBUG0_STATUS
 
uint8_t USBPHY_Type::RESERVED_1 [12]
 
__IO uint32_t USBPHY_Type::DEBUG1
 
__IO uint32_t USBPHY_Type::DEBUG1_SET
 
__IO uint32_t USBPHY_Type::DEBUG1_CLR
 
__IO uint32_t USBPHY_Type::DEBUG1_TOG
 
__I uint32_t USBPHY_Type::VERSION
 
uint8_t USB_ANALOG_Type::RESERVED_0 [416]
 
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT
 
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_SET
 
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_CLR
 
__IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_TOG
 
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT
 
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_SET
 
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_CLR
 
__IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_TOG
 
__I uint32_t   USB_ANALOG_Type::VBUS_DETECT_STAT
 
uint8_t   USB_ANALOG_Type::RESERVED_0 [12]
 
__I uint32_t   USB_ANALOG_Type::CHRG_DETECT_STAT
 
uint8_t   USB_ANALOG_Type::RESERVED_1 [12]
 
__IO uint32_t   USB_ANALOG_Type::LOOPBACK
 
__IO uint32_t   USB_ANALOG_Type::LOOPBACK_SET
 
__IO uint32_t   USB_ANALOG_Type::LOOPBACK_CLR
 
__IO uint32_t   USB_ANALOG_Type::LOOPBACK_TOG
 
__IO uint32_t   USB_ANALOG_Type::MISC
 
__IO uint32_t   USB_ANALOG_Type::MISC_SET
 
__IO uint32_t   USB_ANALOG_Type::MISC_CLR
 
__IO uint32_t   USB_ANALOG_Type::MISC_TOG
 
struct {
   __IO uint32_t   USB_ANALOG_Type::VBUS_DETECT
 
   __IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_SET
 
   __IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_CLR
 
   __IO uint32_t   USB_ANALOG_Type::VBUS_DETECT_TOG
 
   __IO uint32_t   USB_ANALOG_Type::CHRG_DETECT
 
   __IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_SET
 
   __IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_CLR
 
   __IO uint32_t   USB_ANALOG_Type::CHRG_DETECT_TOG
 
   __I uint32_t   USB_ANALOG_Type::VBUS_DETECT_STAT
 
   uint8_t   RESERVED_0 [12]
 
   __I uint32_t   USB_ANALOG_Type::CHRG_DETECT_STAT
 
   uint8_t   RESERVED_1 [12]
 
   __IO uint32_t   USB_ANALOG_Type::LOOPBACK
 
   __IO uint32_t   USB_ANALOG_Type::LOOPBACK_SET
 
   __IO uint32_t   USB_ANALOG_Type::LOOPBACK_CLR
 
   __IO uint32_t   USB_ANALOG_Type::LOOPBACK_TOG
 
   __IO uint32_t   USB_ANALOG_Type::MISC
 
   __IO uint32_t   USB_ANALOG_Type::MISC_SET
 
   __IO uint32_t   USB_ANALOG_Type::MISC_CLR
 
   __IO uint32_t   USB_ANALOG_Type::MISC_TOG
 
} USB_ANALOG_Type::INSTANCE [2]
 
__I uint32_t USB_ANALOG_Type::DIGPROG
 
__IO uint32_t USDHC_Type::DS_ADDR
 
__IO uint32_t USDHC_Type::BLK_ATT
 
__IO uint32_t USDHC_Type::CMD_ARG
 
__IO uint32_t USDHC_Type::CMD_XFR_TYP
 
__I uint32_t USDHC_Type::CMD_RSP0
 
__I uint32_t USDHC_Type::CMD_RSP1
 
__I uint32_t USDHC_Type::CMD_RSP2
 
__I uint32_t USDHC_Type::CMD_RSP3
 
__IO uint32_t USDHC_Type::DATA_BUFF_ACC_PORT
 
__I uint32_t USDHC_Type::PRES_STATE
 
__IO uint32_t USDHC_Type::PROT_CTRL
 
__IO uint32_t USDHC_Type::SYS_CTRL
 
__IO uint32_t USDHC_Type::INT_STATUS
 
__IO uint32_t USDHC_Type::INT_STATUS_EN
 
__IO uint32_t USDHC_Type::INT_SIGNAL_EN
 
__IO uint32_t USDHC_Type::AUTOCMD12_ERR_STATUS
 
__IO uint32_t USDHC_Type::HOST_CTRL_CAP
 
__IO uint32_t USDHC_Type::WTMK_LVL
 
__IO uint32_t USDHC_Type::MIX_CTRL
 
uint8_t USDHC_Type::RESERVED_0 [4]
 
__O uint32_t USDHC_Type::FORCE_EVENT
 
__I uint32_t USDHC_Type::ADMA_ERR_STATUS
 
__IO uint32_t USDHC_Type::ADMA_SYS_ADDR
 
uint8_t USDHC_Type::RESERVED_1 [4]
 
__IO uint32_t USDHC_Type::DLL_CTRL
 
__I uint32_t USDHC_Type::DLL_STATUS
 
__IO uint32_t USDHC_Type::CLK_TUNE_CTRL_STATUS
 
uint8_t USDHC_Type::RESERVED_2 [84]
 
__IO uint32_t USDHC_Type::VEND_SPEC
 
__IO uint32_t USDHC_Type::MMC_BOOT
 
__IO uint32_t USDHC_Type::VEND_SPEC2
 
__IO uint32_t USDHC_Type::TUNING_CTRL
 
__IO uint16_t WDOG_Type::WCR
 
__IO uint16_t WDOG_Type::WSR
 
__I uint16_t WDOG_Type::WRSR
 
__IO uint16_t WDOG_Type::WICR
 
__IO uint16_t WDOG_Type::WMCR
 
__IO uint16_t XBARA_Type::SEL0
 
__IO uint16_t XBARA_Type::SEL1
 
__IO uint16_t XBARA_Type::SEL2
 
__IO uint16_t XBARA_Type::SEL3
 
__IO uint16_t XBARA_Type::SEL4
 
__IO uint16_t XBARA_Type::SEL5
 
__IO uint16_t XBARA_Type::SEL6
 
__IO uint16_t XBARA_Type::SEL7
 
__IO uint16_t XBARA_Type::SEL8
 
__IO uint16_t XBARA_Type::SEL9
 
__IO uint16_t XBARA_Type::SEL10
 
__IO uint16_t XBARA_Type::SEL11
 
__IO uint16_t XBARA_Type::SEL12
 
__IO uint16_t XBARA_Type::SEL13
 
__IO uint16_t XBARA_Type::SEL14
 
__IO uint16_t XBARA_Type::SEL15
 
__IO uint16_t XBARA_Type::SEL16
 
__IO uint16_t XBARA_Type::SEL17
 
__IO uint16_t XBARA_Type::SEL18
 
__IO uint16_t XBARA_Type::SEL19
 
__IO uint16_t XBARA_Type::SEL20
 
__IO uint16_t XBARA_Type::SEL21
 
__IO uint16_t XBARA_Type::SEL22
 
__IO uint16_t XBARA_Type::SEL23
 
__IO uint16_t XBARA_Type::SEL24
 
__IO uint16_t XBARA_Type::SEL25
 
__IO uint16_t XBARA_Type::SEL26
 
__IO uint16_t XBARA_Type::SEL27
 
__IO uint16_t XBARA_Type::SEL28
 
__IO uint16_t XBARA_Type::SEL29
 
__IO uint16_t XBARA_Type::SEL30
 
__IO uint16_t XBARA_Type::SEL31
 
__IO uint16_t XBARA_Type::SEL32
 
__IO uint16_t XBARA_Type::SEL33
 
__IO uint16_t XBARA_Type::SEL34
 
__IO uint16_t XBARA_Type::SEL35
 
__IO uint16_t XBARA_Type::SEL36
 
__IO uint16_t XBARA_Type::SEL37
 
__IO uint16_t XBARA_Type::SEL38
 
__IO uint16_t XBARA_Type::SEL39
 
__IO uint16_t XBARA_Type::SEL40
 
__IO uint16_t XBARA_Type::SEL41
 
__IO uint16_t XBARA_Type::SEL42
 
__IO uint16_t XBARA_Type::SEL43
 
__IO uint16_t XBARA_Type::SEL44
 
__IO uint16_t XBARA_Type::SEL45
 
__IO uint16_t XBARA_Type::SEL46
 
__IO uint16_t XBARA_Type::SEL47
 
__IO uint16_t XBARA_Type::SEL48
 
__IO uint16_t XBARA_Type::SEL49
 
__IO uint16_t XBARA_Type::SEL50
 
__IO uint16_t XBARA_Type::SEL51
 
__IO uint16_t XBARA_Type::SEL52
 
__IO uint16_t XBARA_Type::SEL53
 
__IO uint16_t XBARA_Type::SEL54
 
__IO uint16_t XBARA_Type::SEL55
 
__IO uint16_t XBARA_Type::SEL56
 
__IO uint16_t XBARA_Type::SEL57
 
__IO uint16_t XBARA_Type::SEL58
 
__IO uint16_t XBARA_Type::SEL59
 
__IO uint16_t XBARA_Type::SEL60
 
__IO uint16_t XBARA_Type::SEL61
 
__IO uint16_t XBARA_Type::SEL62
 
__IO uint16_t XBARA_Type::SEL63
 
__IO uint16_t XBARA_Type::SEL64
 
__IO uint16_t XBARA_Type::SEL65
 
__IO uint16_t XBARA_Type::CTRL0
 
__IO uint16_t XBARA_Type::CTRL1
 
__IO uint16_t XBARB_Type::SEL0
 
__IO uint16_t XBARB_Type::SEL1
 
__IO uint16_t XBARB_Type::SEL2
 
__IO uint16_t XBARB_Type::SEL3
 
__IO uint16_t XBARB_Type::SEL4
 
__IO uint16_t XBARB_Type::SEL5
 
__IO uint16_t XBARB_Type::SEL6
 
__IO uint16_t XBARB_Type::SEL7
 
uint8_t XTALOSC24M_Type::RESERVED_0 [336]
 
__IO uint32_t XTALOSC24M_Type::MISC0
 
__IO uint32_t XTALOSC24M_Type::MISC0_SET
 
__IO uint32_t XTALOSC24M_Type::MISC0_CLR
 
__IO uint32_t XTALOSC24M_Type::MISC0_TOG
 
uint8_t XTALOSC24M_Type::RESERVED_1 [272]
 
__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL
 
__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_SET
 
__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_CLR
 
__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_TOG
 
uint8_t XTALOSC24M_Type::RESERVED_2 [32]
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_SET
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_CLR
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_TOG
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_SET
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_CLR
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_TOG
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_SET
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_CLR
 
__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_TOG
 
__I uint32_t ADC_Type::VERID
 
__I uint32_t ADC_Type::PARAM
 
uint8_t ADC_Type::RESERVED_0 [8]
 
__IO uint32_t ADC_Type::CTRL
 
__IO uint32_t ADC_Type::STAT
 
__IO uint32_t ADC_Type::IE
 
__IO uint32_t ADC_Type::DE
 
__IO uint32_t ADC_Type::PAUSE
 
uint8_t ADC_Type::RESERVED_1 [8]
 
__IO uint32_t ADC_Type::FCTRL
 
__O uint32_t ADC_Type::SWTRIG
 
uint8_t ADC_Type::RESERVED_2 [136]
 
__IO uint32_t ADC_Type::TCTRL [8]
 
uint8_t ADC_Type::RESERVED_3 [32]
 
__IO uint32_t   ADC_Type::CMDL
 
__IO uint32_t   ADC_Type::CMDH
 
struct {
   __IO uint32_t   ADC_Type::CMDL
 
   __IO uint32_t   ADC_Type::CMDH
 
} ADC_Type::CMD [15]
 
uint8_t ADC_Type::RESERVED_4 [136]
 
uint8_t ADC_Type::RESERVED_5 [240]
 
__I uint32_t ADC_Type::RESFIFO
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CTRL
 
__IO uint32_t   ADC_ETC_Type::TRIGn_COUNTER
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_1_0
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_3_2
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_5_4
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_7_6
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_1_0
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_3_2
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_5_4
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_7_6
 
struct {
   __IO uint32_t   ADC_ETC_Type::TRIGn_CTRL
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_COUNTER
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_1_0
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_3_2
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_5_4
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_7_6
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_1_0
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_3_2
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_5_4
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_7_6
 
} ADC_ETC_Type::TRIG [8]
 
uint8_t ANADIG_LDO_SNVS_Type::RESERVED_0 [1296]
 
__IO uint32_t ANADIG_LDO_SNVS_Type::PMU_LDO_LPSR_ANA
 
uint8_t ANADIG_LDO_SNVS_Type::RESERVED_1 [12]
 
__IO uint32_t ANADIG_LDO_SNVS_Type::PMU_LDO_LPSR_DIG_2
 
uint8_t ANADIG_LDO_SNVS_Type::RESERVED_2 [12]
 
__IO uint32_t ANADIG_LDO_SNVS_Type::PMU_LDO_LPSR_DIG
 
uint8_t ANADIG_LDO_SNVS_DIG_Type::RESERVED_0 [1344]
 
__IO uint32_t ANADIG_LDO_SNVS_DIG_Type::PMU_LDO_SNVS_DIG
 
uint8_t ANADIG_MISC_Type::RESERVED_0 [2048]
 
__I uint32_t ANADIG_MISC_Type::MISC_DIFPROG
 
uint8_t ANADIG_MISC_Type::RESERVED_1 [28]
 
__IO uint32_t ANADIG_MISC_Type::VDDSOC_AI_CTRL
 
uint8_t ANADIG_MISC_Type::RESERVED_2 [12]
 
__IO uint32_t ANADIG_MISC_Type::VDDSOC_AI_WDATA
 
uint8_t ANADIG_MISC_Type::RESERVED_3 [12]
 
__I uint32_t ANADIG_MISC_Type::VDDSOC_AI_RDATA
 
uint8_t ANADIG_MISC_Type::RESERVED_4 [12]
 
__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_CTRL_1G
 
uint8_t ANADIG_MISC_Type::RESERVED_5 [12]
 
__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_WDATA_1G
 
uint8_t ANADIG_MISC_Type::RESERVED_6 [12]
 
__I uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_RDATA_1G
 
uint8_t ANADIG_MISC_Type::RESERVED_7 [12]
 
__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_CTRL_AUDIO
 
uint8_t ANADIG_MISC_Type::RESERVED_8 [12]
 
__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_WDATA_AUDIO
 
uint8_t ANADIG_MISC_Type::RESERVED_9 [12]
 
__I uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_RDATA_AUDIO
 
uint8_t ANADIG_MISC_Type::RESERVED_10 [12]
 
__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_CTRL_VIDEO
 
uint8_t ANADIG_MISC_Type::RESERVED_11 [12]
 
__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_WDATA_VIDEO
 
uint8_t ANADIG_MISC_Type::RESERVED_12 [12]
 
__I uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_RDATA_VIDEO
 
uint8_t ANADIG_MISC_Type::RESERVED_13 [12]
 
__IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI_CTRL
 
uint8_t ANADIG_MISC_Type::RESERVED_14 [12]
 
__IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI_WDATA
 
uint8_t ANADIG_MISC_Type::RESERVED_15 [12]
 
__I uint32_t ANADIG_MISC_Type::VDDLPSR_AI_RDATA_REFTOP
 
uint8_t ANADIG_MISC_Type::RESERVED_16 [12]
 
__I uint32_t ANADIG_MISC_Type::VDDLPSR_AI_RDATA_TMPSNS
 
uint8_t ANADIG_MISC_Type::RESERVED_17 [12]
 
__IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI400M_CTRL
 
uint8_t ANADIG_MISC_Type::RESERVED_18 [12]
 
__IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI400M_WDATA
 
uint8_t ANADIG_MISC_Type::RESERVED_19 [12]
 
__I uint32_t ANADIG_MISC_Type::VDDLPSR_AI400M_RDATA
 
uint8_t ANADIG_OSC_Type::RESERVED_0 [16]
 
__IO uint32_t ANADIG_OSC_Type::OSC_48M_CTRL
 
uint8_t ANADIG_OSC_Type::RESERVED_1 [12]
 
__IO uint32_t ANADIG_OSC_Type::OSC_24M_CTRL
 
uint8_t ANADIG_OSC_Type::RESERVED_2 [28]
 
__I uint32_t ANADIG_OSC_Type::OSC_400M_CTRL0
 
uint8_t ANADIG_OSC_Type::RESERVED_3 [12]
 
__IO uint32_t ANADIG_OSC_Type::OSC_400M_CTRL1
 
uint8_t ANADIG_OSC_Type::RESERVED_4 [12]
 
__IO uint32_t ANADIG_OSC_Type::OSC_400M_CTRL2
 
uint8_t ANADIG_OSC_Type::RESERVED_5 [92]
 
__IO uint32_t ANADIG_OSC_Type::OSC_16M_CTRL
 
uint8_t ANADIG_PLL_Type::RESERVED_0 [512]
 
__IO uint32_t ANADIG_PLL_Type::ARM_PLL_CTRL
 
uint8_t ANADIG_PLL_Type::RESERVED_1 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL3_CTRL
 
uint8_t ANADIG_PLL_Type::RESERVED_2 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL3_UPDATE
 
uint8_t ANADIG_PLL_Type::RESERVED_3 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL3_PFD
 
uint8_t ANADIG_PLL_Type::RESERVED_4 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL2_CTRL
 
uint8_t ANADIG_PLL_Type::RESERVED_5 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL2_UPDATE
 
uint8_t ANADIG_PLL_Type::RESERVED_6 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL2_SS
 
uint8_t ANADIG_PLL_Type::RESERVED_7 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL2_PFD
 
uint8_t ANADIG_PLL_Type::RESERVED_8 [44]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL2_MFD
 
uint8_t ANADIG_PLL_Type::RESERVED_9 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL1_SS
 
uint8_t ANADIG_PLL_Type::RESERVED_10 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL1_CTRL
 
uint8_t ANADIG_PLL_Type::RESERVED_11 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL1_DENOMINATOR
 
uint8_t ANADIG_PLL_Type::RESERVED_12 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL1_NUMERATOR
 
uint8_t ANADIG_PLL_Type::RESERVED_13 [12]
 
__IO uint32_t ANADIG_PLL_Type::SYS_PLL1_DIV_SELECT
 
uint8_t ANADIG_PLL_Type::RESERVED_14 [12]
 
__IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_CTRL
 
uint8_t ANADIG_PLL_Type::RESERVED_15 [12]
 
__IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_SS
 
uint8_t ANADIG_PLL_Type::RESERVED_16 [12]
 
__IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_DENOMINATOR
 
uint8_t ANADIG_PLL_Type::RESERVED_17 [12]
 
__IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_NUMERATOR
 
uint8_t ANADIG_PLL_Type::RESERVED_18 [12]
 
__IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_DIV_SELECT
 
uint8_t ANADIG_PLL_Type::RESERVED_19 [12]
 
__IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_CTRL
 
uint8_t ANADIG_PLL_Type::RESERVED_20 [12]
 
__IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_SS
 
uint8_t ANADIG_PLL_Type::RESERVED_21 [12]
 
__IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_DENOMINATOR
 
uint8_t ANADIG_PLL_Type::RESERVED_22 [12]
 
__IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_NUMERATOR
 
uint8_t ANADIG_PLL_Type::RESERVED_23 [12]
 
__IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_DIV_SELECT
 
uint8_t ANADIG_PMU_Type::RESERVED_0 [1280]
 
__IO uint32_t ANADIG_PMU_Type::PMU_LDO_PLL
 
uint8_t ANADIG_PMU_Type::RESERVED_1 [76]
 
__IO uint32_t ANADIG_PMU_Type::PMU_BIAS_CTRL
 
uint8_t ANADIG_PMU_Type::RESERVED_2 [12]
 
__IO uint32_t ANADIG_PMU_Type::PMU_BIAS_CTRL2
 
uint8_t ANADIG_PMU_Type::RESERVED_3 [12]
 
__IO uint32_t ANADIG_PMU_Type::PMU_REF_CTRL
 
uint8_t ANADIG_PMU_Type::RESERVED_4 [12]
 
__IO uint32_t ANADIG_PMU_Type::PMU_POWER_DETECT_CTRL
 
uint8_t ANADIG_PMU_Type::RESERVED_5 [124]
 
__IO uint32_t ANADIG_PMU_Type::LDO_PLL_ENABLE_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_6 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_ENABLE_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_7 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_LP_MODE_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_8 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_TRACKING_EN_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_9 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_BYPASS_EN_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_10 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_STBY_EN_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_11 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_ENABLE_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_12 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP0
 
uint8_t ANADIG_PMU_Type::RESERVED_13 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP1
 
uint8_t ANADIG_PMU_Type::RESERVED_14 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP2
 
uint8_t ANADIG_PMU_Type::RESERVED_15 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP3
 
uint8_t ANADIG_PMU_Type::RESERVED_16 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_LP_MODE_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_17 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRACKING_EN_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_18 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_BYPASS_EN_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_19 [12]
 
__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_STBY_EN_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_20 [12]
 
__IO uint32_t ANADIG_PMU_Type::BANDGAP_ENABLE_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_21 [28]
 
__IO uint32_t ANADIG_PMU_Type::RBB_SOC_ENABLE_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_22 [12]
 
__IO uint32_t ANADIG_PMU_Type::RBB_LPSR_ENABLE_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_23 [12]
 
__IO uint32_t ANADIG_PMU_Type::BANDGAP_STBY_EN_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_24 [12]
 
__IO uint32_t ANADIG_PMU_Type::PLL_LDO_STBY_EN_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_25 [28]
 
__IO uint32_t ANADIG_PMU_Type::RBB_SOC_STBY_EN_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_26 [12]
 
__IO uint32_t ANADIG_PMU_Type::RBB_LPSR_STBY_EN_SP
 
uint8_t ANADIG_PMU_Type::RESERVED_27 [28]
 
__IO uint32_t ANADIG_PMU_Type::RBB_LPSR_CONFIGURE
 
uint8_t ANADIG_PMU_Type::RESERVED_28 [12]
 
__IO uint32_t ANADIG_PMU_Type::RBB_SOC_CONFIGURE
 
uint8_t ANADIG_PMU_Type::RESERVED_29 [12]
 
__I uint32_t ANADIG_PMU_Type::REFTOP_OTP_TRIM_VALUE
 
uint8_t ANADIG_PMU_Type::RESERVED_30 [28]
 
__I uint32_t ANADIG_PMU_Type::LPSR_1P8_LDO_OTP_TRIM_VALUE
 
uint8_t ANADIG_TEMPSENSOR_Type::RESERVED_0 [1024]
 
__IO uint32_t ANADIG_TEMPSENSOR_Type::TEMPSENSOR
 
uint8_t ANADIG_TEMPSENSOR_Type::RESERVED_1 [44]
 
__I uint32_t ANADIG_TEMPSENSOR_Type::TEMPSNS_OTP_TRIM_VALUE
 
__IO uint16_t   AOI_Type::BFCRT01
 
__IO uint16_t   AOI_Type::BFCRT23
 
struct {
   __IO uint16_t   AOI_Type::BFCRT01
 
   __IO uint16_t   AOI_Type::BFCRT23
 
} AOI_Type::BFCRT [4]
 
__IO uint32_t ASRC_Type::ASRCTR
 
__IO uint32_t ASRC_Type::ASRIER
 
uint8_t ASRC_Type::RESERVED_0 [4]
 
__IO uint32_t ASRC_Type::ASRCNCR
 
__IO uint32_t ASRC_Type::ASRCFG
 
__IO uint32_t ASRC_Type::ASRCSR
 
__IO uint32_t ASRC_Type::ASRCDR1
 
__IO uint32_t ASRC_Type::ASRCDR2
 
__I uint32_t ASRC_Type::ASRSTR
 
uint8_t ASRC_Type::RESERVED_1 [28]
 
__IO uint32_t ASRC_Type::ASRPM [5]
 
__IO uint32_t ASRC_Type::ASRTFR1
 
uint8_t ASRC_Type::RESERVED_2 [4]
 
__IO uint32_t ASRC_Type::ASRCCR
 
__O uint32_t ASRC_Type::ASRDIA
 
__I uint32_t ASRC_Type::ASRDOA
 
__O uint32_t ASRC_Type::ASRDIB
 
__I uint32_t ASRC_Type::ASRDOB
 
__O uint32_t ASRC_Type::ASRDIC
 
__I uint32_t ASRC_Type::ASRDOC
 
uint8_t ASRC_Type::RESERVED_3 [8]
 
__IO uint32_t ASRC_Type::ASRIDRHA
 
__IO uint32_t ASRC_Type::ASRIDRLA
 
__IO uint32_t ASRC_Type::ASRIDRHB
 
__IO uint32_t ASRC_Type::ASRIDRLB
 
__IO uint32_t ASRC_Type::ASRIDRHC
 
__IO uint32_t ASRC_Type::ASRIDRLC
 
__IO uint32_t ASRC_Type::ASR76K
 
__IO uint32_t ASRC_Type::ASR56K
 
__IO uint32_t ASRC_Type::ASRMCRA
 
__I uint32_t ASRC_Type::ASRFSTA
 
__IO uint32_t ASRC_Type::ASRMCRB
 
__I uint32_t ASRC_Type::ASRFSTB
 
__IO uint32_t ASRC_Type::ASRMCRC
 
__I uint32_t ASRC_Type::ASRFSTC
 
uint8_t ASRC_Type::RESERVED_4 [8]
 
__IO uint32_t ASRC_Type::ASRMCR1 [3]
 
__IO uint32_t   AUDIO_PLL_Type::RW
 
__IO uint32_t   AUDIO_PLL_Type::SET
 
__IO uint32_t   AUDIO_PLL_Type::CLR
 
__IO uint32_t   AUDIO_PLL_Type::TOG
 
struct {
   __IO uint32_t   AUDIO_PLL_Type::RW
 
   __IO uint32_t   AUDIO_PLL_Type::SET
 
   __IO uint32_t   AUDIO_PLL_Type::CLR
 
   __IO uint32_t   AUDIO_PLL_Type::TOG
 
} AUDIO_PLL_Type::CTRL0
 
__IO uint32_t   AUDIO_PLL_Type::RW
 
__IO uint32_t   AUDIO_PLL_Type::SET
 
__IO uint32_t   AUDIO_PLL_Type::CLR
 
__IO uint32_t   AUDIO_PLL_Type::TOG
 
struct {
   __IO uint32_t   AUDIO_PLL_Type::RW
 
   __IO uint32_t   AUDIO_PLL_Type::SET
 
   __IO uint32_t   AUDIO_PLL_Type::CLR
 
   __IO uint32_t   AUDIO_PLL_Type::TOG
 
} AUDIO_PLL_Type::SPREAD_SPECTRUM
 
__IO uint32_t   AUDIO_PLL_Type::RW
 
__IO uint32_t   AUDIO_PLL_Type::SET
 
__IO uint32_t   AUDIO_PLL_Type::CLR
 
__IO uint32_t   AUDIO_PLL_Type::TOG
 
struct {
   __IO uint32_t   AUDIO_PLL_Type::RW
 
   __IO uint32_t   AUDIO_PLL_Type::SET
 
   __IO uint32_t   AUDIO_PLL_Type::CLR
 
   __IO uint32_t   AUDIO_PLL_Type::TOG
 
} AUDIO_PLL_Type::NUMERATOR
 
__IO uint32_t   AUDIO_PLL_Type::RW
 
__IO uint32_t   AUDIO_PLL_Type::SET
 
__IO uint32_t   AUDIO_PLL_Type::CLR
 
__IO uint32_t   AUDIO_PLL_Type::TOG
 
struct {
   __IO uint32_t   AUDIO_PLL_Type::RW
 
   __IO uint32_t   AUDIO_PLL_Type::SET
 
   __IO uint32_t   AUDIO_PLL_Type::CLR
 
   __IO uint32_t   AUDIO_PLL_Type::TOG
 
} AUDIO_PLL_Type::DENOMINATOR
 
uint8_t CAAM_Type::RESERVED_0 [4]
 
__IO uint32_t CAAM_Type::MCFGR
 
__IO uint32_t CAAM_Type::PAGE0_SDID
 
__IO uint32_t CAAM_Type::SCFGR
 
__IO uint32_t   CAAM_Type::JRDID_MS
 
__IO uint32_t   CAAM_Type::JRDID_LS
 
struct {
   __IO uint32_t   CAAM_Type::JRDID_MS
 
   __IO uint32_t   CAAM_Type::JRDID_LS
 
} CAAM_Type::JRADID [4]
 
uint8_t CAAM_Type::RESERVED_1 [40]
 
__IO uint32_t CAAM_Type::DEBUGCTL
 
__IO uint32_t CAAM_Type::JRSTARTR
 
__IO uint32_t CAAM_Type::RTIC_OWN
 
__IO uint32_t   CAAM_Type::RTIC_DID
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
struct {
   __IO uint32_t   CAAM_Type::RTIC_DID
 
   uint8_t   RESERVED_0 [4]
 
} CAAM_Type::RTICADID [4]
 
uint8_t CAAM_Type::RESERVED_2 [16]
 
__IO uint32_t CAAM_Type::DECORSR
 
uint8_t CAAM_Type::RESERVED_3 [4]
 
__IO uint32_t CAAM_Type::DECORR
 
__IO uint32_t   CAAM_Type::DECODID_MS
 
__IO uint32_t   CAAM_Type::DECODID_LS
 
struct {
   __IO uint32_t   CAAM_Type::DECODID_MS
 
   __IO uint32_t   CAAM_Type::DECODID_LS
 
} CAAM_Type::DECONDID [1]
 
uint8_t CAAM_Type::RESERVED_4 [120]
 
__IO uint32_t CAAM_Type::DAR
 
__O uint32_t CAAM_Type::DRR
 
uint8_t CAAM_Type::RESERVED_5 [92]
 
__IO uint32_t   CAAM_Type::JRSMVBAR
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
struct {
   __IO uint32_t   CAAM_Type::JRSMVBAR
 
   uint8_t   RESERVED_0 [4]
 
} CAAM_Type::JRNSMVBAR [4]
 
uint8_t CAAM_Type::RESERVED_6 [124]
 
__IO uint32_t CAAM_Type::PBSL
 
uint8_t CAAM_Type::RESERVED_7 [28]
 
__I uint32_t   CAAM_Type::DMA_AIDL_MAP_MS
 
__I uint32_t   CAAM_Type::DMA_AIDL_MAP_LS
 
__I uint32_t   CAAM_Type::DMA_AIDM_MAP_MS
 
__I uint32_t   CAAM_Type::DMA_AIDM_MAP_LS
 
struct {
   __I uint32_t   CAAM_Type::DMA_AIDL_MAP_MS
 
   __I uint32_t   CAAM_Type::DMA_AIDL_MAP_LS
 
   __I uint32_t   CAAM_Type::DMA_AIDM_MAP_MS
 
   __I uint32_t   CAAM_Type::DMA_AIDM_MAP_LS
 
} CAAM_Type::AID_CNTS [1]
 
__I uint32_t CAAM_Type::DMA0_AID_ENB
 
uint8_t CAAM_Type::RESERVED_8 [12]
 
__IO uint64_t CAAM_Type::DMA0_ARD_TC
 
uint8_t CAAM_Type::RESERVED_9 [4]
 
__IO uint32_t CAAM_Type::DMA0_ARD_LAT
 
__IO uint64_t CAAM_Type::DMA0_AWR_TC
 
uint8_t CAAM_Type::RESERVED_10 [4]
 
__IO uint32_t CAAM_Type::DMA0_AWR_LAT
 
uint8_t CAAM_Type::RESERVED_11 [128]
 
__IO uint8_t CAAM_Type::MPPKR [64]
 
uint8_t CAAM_Type::RESERVED_12 [64]
 
__IO uint8_t CAAM_Type::MPMR [32]
 
uint8_t CAAM_Type::RESERVED_13 [32]
 
__I uint8_t CAAM_Type::MPTESTR [32]
 
uint8_t CAAM_Type::RESERVED_14 [24]
 
__I uint32_t CAAM_Type::MPECC
 
uint8_t CAAM_Type::RESERVED_15 [4]
 
__IO uint32_t CAAM_Type::JDKEKR [8]
 
__IO uint32_t CAAM_Type::TDKEKR [8]
 
__IO uint32_t CAAM_Type::TDSKR [8]
 
uint8_t CAAM_Type::RESERVED_16 [128]
 
__IO uint64_t CAAM_Type::SKNR
 
uint8_t CAAM_Type::RESERVED_17 [36]
 
__I uint32_t CAAM_Type::DMA_STA
 
__I uint32_t CAAM_Type::DMA_X_AID_7_4_MAP
 
__I uint32_t CAAM_Type::DMA_X_AID_3_0_MAP
 
__I uint32_t CAAM_Type::DMA_X_AID_15_12_MAP
 
__I uint32_t CAAM_Type::DMA_X_AID_11_8_MAP
 
uint8_t CAAM_Type::RESERVED_18 [4]
 
__I uint32_t CAAM_Type::DMA_X_AID_15_0_EN
 
uint8_t CAAM_Type::RESERVED_19 [8]
 
__IO uint32_t CAAM_Type::DMA_X_ARTC_CTL
 
__IO uint32_t CAAM_Type::DMA_X_ARTC_LC
 
__IO uint32_t CAAM_Type::DMA_X_ARTC_SC
 
__IO uint32_t CAAM_Type::DMA_X_ARTC_LAT
 
__IO uint32_t CAAM_Type::DMA_X_AWTC_CTL
 
__IO uint32_t CAAM_Type::DMA_X_AWTC_LC
 
__IO uint32_t CAAM_Type::DMA_X_AWTC_SC
 
__IO uint32_t CAAM_Type::DMA_X_AWTC_LAT
 
uint8_t CAAM_Type::RESERVED_20 [176]
 
__IO uint32_t CAAM_Type::RTMCTL
 
__IO uint32_t CAAM_Type::RTSCMISC
 
__IO uint32_t CAAM_Type::RTPKRRNG
 
__IO uint32_t   CAAM_Type::RTPKRMAX
 
__I uint32_t   CAAM_Type::RTPKRSQ
 
union {
   __IO uint32_t   CAAM_Type::RTPKRMAX
 
   __I uint32_t   CAAM_Type::RTPKRSQ
 
}; 
 
__IO uint32_t CAAM_Type::RTSDCTL
 
__IO uint32_t   CAAM_Type::RTSBLIM
 
__I uint32_t   CAAM_Type::RTTOTSAM
 
union {
   __IO uint32_t   CAAM_Type::RTSBLIM
 
   __I uint32_t   CAAM_Type::RTTOTSAM
 
}; 
 
__IO uint32_t CAAM_Type::RTFRQMIN
 
__I uint32_t   CAAM_Type::RTFRQCNT
 
__I uint32_t   CAAM_Type::RTSCMC
 
__I uint32_t   CAAM_Type::RTSCR1C
 
__I uint32_t   CAAM_Type::RTSCR2C
 
__I uint32_t   CAAM_Type::RTSCR3C
 
__I uint32_t   CAAM_Type::RTSCR4C
 
__I uint32_t   CAAM_Type::RTSCR5C
 
__I uint32_t   CAAM_Type::RTSCR6PC
 
struct {
   __I uint32_t   CAAM_Type::RTFRQCNT
 
   __I uint32_t   CAAM_Type::RTSCMC
 
   __I uint32_t   CAAM_Type::RTSCR1C
 
   __I uint32_t   CAAM_Type::RTSCR2C
 
   __I uint32_t   CAAM_Type::RTSCR3C
 
   __I uint32_t   CAAM_Type::RTSCR4C
 
   __I uint32_t   CAAM_Type::RTSCR5C
 
   __I uint32_t   CAAM_Type::RTSCR6PC
 
}   CAAM_Type::COUNT
 
__IO uint32_t   CAAM_Type::RTFRQMAX
 
__IO uint32_t   CAAM_Type::RTSCML
 
__IO uint32_t   CAAM_Type::RTSCR1L
 
__IO uint32_t   CAAM_Type::RTSCR2L
 
__IO uint32_t   CAAM_Type::RTSCR3L
 
__IO uint32_t   CAAM_Type::RTSCR4L
 
__IO uint32_t   CAAM_Type::RTSCR5L
 
__IO uint32_t   CAAM_Type::RTSCR6PL
 
struct {
   __IO uint32_t   CAAM_Type::RTFRQMAX
 
   __IO uint32_t   CAAM_Type::RTSCML
 
   __IO uint32_t   CAAM_Type::RTSCR1L
 
   __IO uint32_t   CAAM_Type::RTSCR2L
 
   __IO uint32_t   CAAM_Type::RTSCR3L
 
   __IO uint32_t   CAAM_Type::RTSCR4L
 
   __IO uint32_t   CAAM_Type::RTSCR5L
 
   __IO uint32_t   CAAM_Type::RTSCR6PL
 
}   CAAM_Type::LIMIT
 
union {
   struct {
      __I uint32_t   CAAM_Type::RTFRQCNT
 
      __I uint32_t   CAAM_Type::RTSCMC
 
      __I uint32_t   CAAM_Type::RTSCR1C
 
      __I uint32_t   CAAM_Type::RTSCR2C
 
      __I uint32_t   CAAM_Type::RTSCR3C
 
      __I uint32_t   CAAM_Type::RTSCR4C
 
      __I uint32_t   CAAM_Type::RTSCR5C
 
      __I uint32_t   CAAM_Type::RTSCR6PC
 
   }   COUNT
 
   struct {
      __IO uint32_t   CAAM_Type::RTFRQMAX
 
      __IO uint32_t   CAAM_Type::RTSCML
 
      __IO uint32_t   CAAM_Type::RTSCR1L
 
      __IO uint32_t   CAAM_Type::RTSCR2L
 
      __IO uint32_t   CAAM_Type::RTSCR3L
 
      __IO uint32_t   CAAM_Type::RTSCR4L
 
      __IO uint32_t   CAAM_Type::RTSCR5L
 
      __IO uint32_t   CAAM_Type::RTSCR6PL
 
   }   LIMIT
 
}; 
 
__I uint32_t CAAM_Type::RTSTATUS
 
__I uint32_t CAAM_Type::RTENT [16]
 
__I uint32_t CAAM_Type::RTPKRCNT10
 
__I uint32_t CAAM_Type::RTPKRCNT32
 
__I uint32_t CAAM_Type::RTPKRCNT54
 
__I uint32_t CAAM_Type::RTPKRCNT76
 
__I uint32_t CAAM_Type::RTPKRCNT98
 
__I uint32_t CAAM_Type::RTPKRCNTBA
 
__I uint32_t CAAM_Type::RTPKRCNTDC
 
__I uint32_t CAAM_Type::RTPKRCNTFE
 
uint8_t CAAM_Type::RESERVED_21 [32]
 
__I uint32_t CAAM_Type::RDSTA
 
uint8_t CAAM_Type::RESERVED_22 [12]
 
__I uint32_t CAAM_Type::RDINT0
 
__I uint32_t CAAM_Type::RDINT1
 
uint8_t CAAM_Type::RESERVED_23 [8]
 
__IO uint32_t CAAM_Type::RDHCNTL
 
__I uint32_t CAAM_Type::RDHDIG
 
__O uint32_t CAAM_Type::RDHBUF
 
uint8_t CAAM_Type::RESERVED_24 [788]
 
__I uint32_t   CAAM_Type::PX_SDID_PG0
 
__IO uint32_t   CAAM_Type::PX_SMAPR_PG0
 
__IO uint32_t   CAAM_Type::PX_SMAG2_PG0
 
__IO uint32_t   CAAM_Type::PX_SMAG1_PG0
 
struct {
   __I uint32_t   CAAM_Type::PX_SDID_PG0
 
   __IO uint32_t   CAAM_Type::PX_SMAPR_PG0
 
   __IO uint32_t   CAAM_Type::PX_SMAG2_PG0
 
   __IO uint32_t   CAAM_Type::PX_SMAG1_PG0
 
} CAAM_Type::PX_PG0 [16]
 
__IO uint32_t CAAM_Type::REIS
 
__IO uint32_t CAAM_Type::REIE
 
__I uint32_t CAAM_Type::REIF
 
__IO uint32_t CAAM_Type::REIH
 
uint8_t CAAM_Type::RESERVED_25 [192]
 
__IO uint32_t CAAM_Type::SMWPJRR [4]
 
uint8_t CAAM_Type::RESERVED_26 [4]
 
__O uint32_t CAAM_Type::SMCR_PG0
 
uint8_t CAAM_Type::RESERVED_27 [4]
 
__I uint32_t CAAM_Type::SMCSR_PG0
 
uint8_t CAAM_Type::RESERVED_28 [8]
 
__I uint32_t CAAM_Type::CAAMVID_MS_TRAD
 
__I uint32_t CAAM_Type::CAAMVID_LS_TRAD
 
__I uint64_t   CAAM_Type::HT_JD_ADDR
 
__I uint64_t   CAAM_Type::HT_SD_ADDR
 
__I uint32_t   CAAM_Type::HT_JQ_CTRL_MS
 
__I uint32_t   CAAM_Type::HT_JQ_CTRL_LS
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
__I uint32_t   CAAM_Type::HT_STATUS
 
struct {
   __I uint64_t   CAAM_Type::HT_JD_ADDR
 
   __I uint64_t   CAAM_Type::HT_SD_ADDR
 
   __I uint32_t   CAAM_Type::HT_JQ_CTRL_MS
 
   __I uint32_t   CAAM_Type::HT_JQ_CTRL_LS
 
   uint8_t   RESERVED_0 [4]
 
   __I uint32_t   CAAM_Type::HT_STATUS
 
} CAAM_Type::HTA [1]
 
uint8_t CAAM_Type::RESERVED_29 [4]
 
__IO uint32_t CAAM_Type::JQ_DEBUG_SEL
 
uint8_t CAAM_Type::RESERVED_30 [404]
 
__I uint32_t CAAM_Type::JRJIDU_LS
 
__I uint32_t CAAM_Type::JRJDJIFBC
 
__I uint32_t CAAM_Type::JRJDJIF
 
uint8_t CAAM_Type::RESERVED_31 [28]
 
__I uint32_t CAAM_Type::JRJDS1
 
uint8_t CAAM_Type::RESERVED_32 [24]
 
__I uint64_t CAAM_Type::JRJDDA [1]
 
uint8_t CAAM_Type::RESERVED_33 [408]
 
__I uint32_t CAAM_Type::CRNR_MS
 
__I uint32_t CAAM_Type::CRNR_LS
 
__I uint32_t CAAM_Type::CTPR_MS
 
__I uint32_t CAAM_Type::CTPR_LS
 
uint8_t CAAM_Type::RESERVED_34 [4]
 
__I uint32_t CAAM_Type::SMSTA
 
uint8_t CAAM_Type::RESERVED_35 [4]
 
__I uint32_t CAAM_Type::SMPO
 
__I uint64_t CAAM_Type::FAR
 
__I uint32_t CAAM_Type::FADID
 
__I uint32_t CAAM_Type::FADR
 
uint8_t CAAM_Type::RESERVED_36 [4]
 
__I uint32_t CAAM_Type::CSTA
 
__I uint32_t CAAM_Type::SMVID_MS
 
__I uint32_t CAAM_Type::SMVID_LS
 
__I uint32_t CAAM_Type::RVID
 
__I uint32_t CAAM_Type::CCBVID
 
__I uint32_t CAAM_Type::CHAVID_MS
 
__I uint32_t CAAM_Type::CHAVID_LS
 
__I uint32_t CAAM_Type::CHANUM_MS
 
__I uint32_t CAAM_Type::CHANUM_LS
 
__I uint32_t CAAM_Type::CAAMVID_MS
 
__I uint32_t CAAM_Type::CAAMVID_LS
 
uint8_t CAAM_Type::RESERVED_37 [61440]
 
__IO uint64_t   CAAM_Type::IRBAR_JR
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
__IO uint32_t   CAAM_Type::IRSR_JR
 
uint8_t   CAAM_Type::RESERVED_1 [4]
 
__IO uint32_t   CAAM_Type::IRSAR_JR
 
uint8_t   CAAM_Type::RESERVED_2 [4]
 
__IO uint32_t   CAAM_Type::IRJAR_JR
 
__IO uint64_t   CAAM_Type::ORBAR_JR
 
uint8_t   CAAM_Type::RESERVED_3 [4]
 
__IO uint32_t   CAAM_Type::ORSR_JR
 
uint8_t   CAAM_Type::RESERVED_4 [4]
 
__IO uint32_t   CAAM_Type::ORJRR_JR
 
uint8_t   CAAM_Type::RESERVED_5 [4]
 
__IO uint32_t   CAAM_Type::ORSFR_JR
 
uint8_t   CAAM_Type::RESERVED_6 [4]
 
__I uint32_t   CAAM_Type::JRSTAR_JR
 
uint8_t   CAAM_Type::RESERVED_7 [4]
 
__IO uint32_t   CAAM_Type::JRINTR_JR
 
__IO uint32_t   CAAM_Type::JRCFGR_JR_MS
 
__IO uint32_t   CAAM_Type::JRCFGR_JR_LS
 
uint8_t   CAAM_Type::RESERVED_8 [4]
 
__IO uint32_t   CAAM_Type::IRRIR_JR
 
uint8_t   CAAM_Type::RESERVED_9 [4]
 
__IO uint32_t   CAAM_Type::ORWIR_JR
 
uint8_t   CAAM_Type::RESERVED_10 [4]
 
__O uint32_t   CAAM_Type::JRCR_JR
 
uint8_t   CAAM_Type::RESERVED_11 [1684]
 
__I uint32_t   CAAM_Type::JRAAV
 
uint8_t   CAAM_Type::RESERVED_12 [248]
 
__I uint64_t   CAAM_Type::JRAAA [4]
 
uint8_t   CAAM_Type::RESERVED_13 [480]
 
__I uint32_t   CAAM_Type::PX_SDID_JR
 
__IO uint32_t   CAAM_Type::PX_SMAPR_JR
 
__IO uint32_t   CAAM_Type::PX_SMAG2_JR
 
__IO uint32_t   CAAM_Type::PX_SMAG1_JR
 
struct {
   __I uint32_t   CAAM_Type::PX_SDID_JR
 
   __IO uint32_t   CAAM_Type::PX_SMAPR_JR
 
   __IO uint32_t   CAAM_Type::PX_SMAG2_JR
 
   __IO uint32_t   CAAM_Type::PX_SMAG1_JR
 
}   CAAM_Type::PX_JR [16]
 
uint8_t   CAAM_Type::RESERVED_14 [228]
 
__O uint32_t   CAAM_Type::SMCR_JR
 
uint8_t   CAAM_Type::RESERVED_15 [4]
 
__I uint32_t   CAAM_Type::SMCSR_JR
 
uint8_t   CAAM_Type::RESERVED_16 [528]
 
__I uint32_t   CAAM_Type::REIR0JR
 
uint8_t   CAAM_Type::RESERVED_17 [4]
 
__I uint64_t   CAAM_Type::REIR2JR
 
__I uint32_t   CAAM_Type::REIR4JR
 
__I uint32_t   CAAM_Type::REIR5JR
 
uint8_t   CAAM_Type::RESERVED_18 [392]
 
__I uint32_t   CAAM_Type::CRNR_MS_JR
 
__I uint32_t   CAAM_Type::CRNR_LS_JR
 
__I uint32_t   CAAM_Type::CTPR_MS_JR
 
__I uint32_t   CAAM_Type::CTPR_LS_JR
 
uint8_t   CAAM_Type::RESERVED_19 [4]
 
__I uint32_t   CAAM_Type::SMSTA_JR
 
uint8_t   CAAM_Type::RESERVED_20 [4]
 
__I uint32_t   CAAM_Type::SMPO_JR
 
__I uint64_t   CAAM_Type::FAR_JR
 
__I uint32_t   CAAM_Type::FADID_JR
 
__I uint32_t   CAAM_Type::FADR_JR
 
uint8_t   CAAM_Type::RESERVED_21 [4]
 
__I uint32_t   CAAM_Type::CSTA_JR
 
__I uint32_t   CAAM_Type::SMVID_MS_JR
 
__I uint32_t   CAAM_Type::SMVID_LS_JR
 
__I uint32_t   CAAM_Type::RVID_JR
 
__I uint32_t   CAAM_Type::CCBVID_JR
 
__I uint32_t   CAAM_Type::CHAVID_MS_JR
 
__I uint32_t   CAAM_Type::CHAVID_LS_JR
 
__I uint32_t   CAAM_Type::CHANUM_MS_JR
 
__I uint32_t   CAAM_Type::CHANUM_LS_JR
 
__I uint32_t   CAAM_Type::CAAMVID_MS_JR
 
__I uint32_t   CAAM_Type::CAAMVID_LS_JR
 
uint8_t   CAAM_Type::RESERVED_22 [61440]
 
struct {
   __IO uint64_t   CAAM_Type::IRBAR_JR
 
   uint8_t   RESERVED_0 [4]
 
   __IO uint32_t   CAAM_Type::IRSR_JR
 
   uint8_t   RESERVED_1 [4]
 
   __IO uint32_t   CAAM_Type::IRSAR_JR
 
   uint8_t   RESERVED_2 [4]
 
   __IO uint32_t   CAAM_Type::IRJAR_JR
 
   __IO uint64_t   CAAM_Type::ORBAR_JR
 
   uint8_t   RESERVED_3 [4]
 
   __IO uint32_t   CAAM_Type::ORSR_JR
 
   uint8_t   RESERVED_4 [4]
 
   __IO uint32_t   CAAM_Type::ORJRR_JR
 
   uint8_t   RESERVED_5 [4]
 
   __IO uint32_t   CAAM_Type::ORSFR_JR
 
   uint8_t   RESERVED_6 [4]
 
   __I uint32_t   CAAM_Type::JRSTAR_JR
 
   uint8_t   RESERVED_7 [4]
 
   __IO uint32_t   CAAM_Type::JRINTR_JR
 
   __IO uint32_t   CAAM_Type::JRCFGR_JR_MS
 
   __IO uint32_t   CAAM_Type::JRCFGR_JR_LS
 
   uint8_t   RESERVED_8 [4]
 
   __IO uint32_t   CAAM_Type::IRRIR_JR
 
   uint8_t   RESERVED_9 [4]
 
   __IO uint32_t   CAAM_Type::ORWIR_JR
 
   uint8_t   RESERVED_10 [4]
 
   __O uint32_t   CAAM_Type::JRCR_JR
 
   uint8_t   RESERVED_11 [1684]
 
   __I uint32_t   CAAM_Type::JRAAV
 
   uint8_t   RESERVED_12 [248]
 
   __I uint64_t   CAAM_Type::JRAAA [4]
 
   uint8_t   RESERVED_13 [480]
 
   struct {
      __I uint32_t   CAAM_Type::PX_SDID_JR
 
      __IO uint32_t   CAAM_Type::PX_SMAPR_JR
 
      __IO uint32_t   CAAM_Type::PX_SMAG2_JR
 
      __IO uint32_t   CAAM_Type::PX_SMAG1_JR
 
   }   PX_JR [16]
 
   uint8_t   RESERVED_14 [228]
 
   __O uint32_t   CAAM_Type::SMCR_JR
 
   uint8_t   RESERVED_15 [4]
 
   __I uint32_t   CAAM_Type::SMCSR_JR
 
   uint8_t   RESERVED_16 [528]
 
   __I uint32_t   CAAM_Type::REIR0JR
 
   uint8_t   RESERVED_17 [4]
 
   __I uint64_t   CAAM_Type::REIR2JR
 
   __I uint32_t   CAAM_Type::REIR4JR
 
   __I uint32_t   CAAM_Type::REIR5JR
 
   uint8_t   RESERVED_18 [392]
 
   __I uint32_t   CAAM_Type::CRNR_MS_JR
 
   __I uint32_t   CAAM_Type::CRNR_LS_JR
 
   __I uint32_t   CAAM_Type::CTPR_MS_JR
 
   __I uint32_t   CAAM_Type::CTPR_LS_JR
 
   uint8_t   RESERVED_19 [4]
 
   __I uint32_t   CAAM_Type::SMSTA_JR
 
   uint8_t   RESERVED_20 [4]
 
   __I uint32_t   CAAM_Type::SMPO_JR
 
   __I uint64_t   CAAM_Type::FAR_JR
 
   __I uint32_t   CAAM_Type::FADID_JR
 
   __I uint32_t   CAAM_Type::FADR_JR
 
   uint8_t   RESERVED_21 [4]
 
   __I uint32_t   CAAM_Type::CSTA_JR
 
   __I uint32_t   CAAM_Type::SMVID_MS_JR
 
   __I uint32_t   CAAM_Type::SMVID_LS_JR
 
   __I uint32_t   CAAM_Type::RVID_JR
 
   __I uint32_t   CAAM_Type::CCBVID_JR
 
   __I uint32_t   CAAM_Type::CHAVID_MS_JR
 
   __I uint32_t   CAAM_Type::CHAVID_LS_JR
 
   __I uint32_t   CAAM_Type::CHANUM_MS_JR
 
   __I uint32_t   CAAM_Type::CHANUM_LS_JR
 
   __I uint32_t   CAAM_Type::CAAMVID_MS_JR
 
   __I uint32_t   CAAM_Type::CAAMVID_LS_JR
 
   uint8_t   RESERVED_22 [61440]
 
} CAAM_Type::JOBRING [4]
 
uint8_t CAAM_Type::RESERVED_38 [65540]
 
__I uint32_t CAAM_Type::RSTA
 
uint8_t CAAM_Type::RESERVED_39 [4]
 
__IO uint32_t CAAM_Type::RCMD
 
uint8_t CAAM_Type::RESERVED_40 [4]
 
__IO uint32_t CAAM_Type::RCTL
 
uint8_t CAAM_Type::RESERVED_41 [4]
 
__IO uint32_t CAAM_Type::RTHR
 
uint8_t CAAM_Type::RESERVED_42 [8]
 
__IO uint64_t CAAM_Type::RWDOG
 
uint8_t CAAM_Type::RESERVED_43 [4]
 
__IO uint32_t CAAM_Type::REND
 
uint8_t CAAM_Type::RESERVED_44 [200]
 
__IO uint64_t   CAAM_Type::RMA
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
__IO uint32_t   CAAM_Type::RML
 
struct {
   __IO uint64_t   CAAM_Type::RMA
 
   uint8_t   RESERVED_0 [4]
 
   __IO uint32_t   CAAM_Type::RML
 
} CAAM_Type::RM [4][2]
 
uint8_t CAAM_Type::RESERVED_45 [128]
 
__IO uint32_t CAAM_Type::RMD [4][2][32]
 
uint8_t CAAM_Type::RESERVED_46 [2048]
 
__I uint32_t CAAM_Type::REIR0RTIC
 
uint8_t CAAM_Type::RESERVED_47 [4]
 
__I uint64_t CAAM_Type::REIR2RTIC
 
__I uint32_t CAAM_Type::REIR4RTIC
 
__I uint32_t CAAM_Type::REIR5RTIC
 
uint8_t CAAM_Type::RESERVED_48 [392]
 
__I uint32_t CAAM_Type::CRNR_MS_RTIC
 
__I uint32_t CAAM_Type::CRNR_LS_RTIC
 
__I uint32_t CAAM_Type::CTPR_MS_RTIC
 
__I uint32_t CAAM_Type::CTPR_LS_RTIC
 
uint8_t CAAM_Type::RESERVED_49 [4]
 
__I uint32_t CAAM_Type::SMSTA_RTIC
 
uint8_t CAAM_Type::RESERVED_50 [8]
 
__I uint64_t CAAM_Type::FAR_RTIC
 
__I uint32_t CAAM_Type::FADID_RTIC
 
__I uint32_t CAAM_Type::FADR_RTIC
 
uint8_t CAAM_Type::RESERVED_51 [4]
 
__I uint32_t CAAM_Type::CSTA_RTIC
 
__I uint32_t CAAM_Type::SMVID_MS_RTIC
 
__I uint32_t CAAM_Type::SMVID_LS_RTIC
 
__I uint32_t CAAM_Type::RVID_RTIC
 
__I uint32_t CAAM_Type::CCBVID_RTIC
 
__I uint32_t CAAM_Type::CHAVID_MS_RTIC
 
__I uint32_t CAAM_Type::CHAVID_LS_RTIC
 
__I uint32_t CAAM_Type::CHANUM_MS_RTIC
 
__I uint32_t CAAM_Type::CHANUM_LS_RTIC
 
__I uint32_t CAAM_Type::CAAMVID_MS_RTIC
 
__I uint32_t CAAM_Type::CAAMVID_LS_RTIC
 
uint8_t CAAM_Type::RESERVED_52 [126976]
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
__IO uint32_t   CAAM_Type::CC1MR
 
__IO uint32_t   CAAM_Type::CC1MR_PK
 
__IO uint32_t   CAAM_Type::CC1MR_RNG
 
union {
   __IO uint32_t   CAAM_Type::CC1MR
 
   __IO uint32_t   CAAM_Type::CC1MR_PK
 
   __IO uint32_t   CAAM_Type::CC1MR_RNG
 
} 
 
uint8_t   CAAM_Type::RESERVED_1 [4]
 
__IO uint32_t   CAAM_Type::CC1KSR
 
__IO uint64_t   CAAM_Type::CC1DSR
 
uint8_t   CAAM_Type::RESERVED_2 [4]
 
__IO uint32_t   CAAM_Type::CC1ICVSR
 
uint8_t   CAAM_Type::RESERVED_3 [20]
 
__O uint32_t   CAAM_Type::CCCTRL
 
uint8_t   CAAM_Type::RESERVED_4 [4]
 
__IO uint32_t   CAAM_Type::CICTL
 
uint8_t   CAAM_Type::RESERVED_5 [4]
 
__O uint32_t   CAAM_Type::CCWR
 
__I uint32_t   CAAM_Type::CCSTA_MS
 
__I uint32_t   CAAM_Type::CCSTA_LS
 
uint8_t   CAAM_Type::RESERVED_6 [12]
 
__IO uint32_t   CAAM_Type::CC1AADSZR
 
uint8_t   CAAM_Type::RESERVED_7 [4]
 
__IO uint32_t   CAAM_Type::CC1IVSZR
 
uint8_t   CAAM_Type::RESERVED_8 [28]
 
__IO uint32_t   CAAM_Type::CPKASZR
 
uint8_t   CAAM_Type::RESERVED_9 [4]
 
__IO uint32_t   CAAM_Type::CPKBSZR
 
uint8_t   CAAM_Type::RESERVED_10 [4]
 
__IO uint32_t   CAAM_Type::CPKNSZR
 
uint8_t   CAAM_Type::RESERVED_11 [4]
 
__IO uint32_t   CAAM_Type::CPKESZR
 
uint8_t   CAAM_Type::RESERVED_12 [96]
 
__IO uint32_t   CAAM_Type::CC1CTXR [16]
 
uint8_t   CAAM_Type::RESERVED_13 [192]
 
__IO uint32_t   CAAM_Type::CC1KR [8]
 
uint8_t   CAAM_Type::RESERVED_14 [484]
 
__IO uint32_t   CAAM_Type::CC2MR
 
uint8_t   CAAM_Type::RESERVED_15 [4]
 
__IO uint32_t   CAAM_Type::CC2KSR
 
__IO uint64_t   CAAM_Type::CC2DSR
 
uint8_t   CAAM_Type::RESERVED_16 [4]
 
__IO uint32_t   CAAM_Type::CC2ICVSZR
 
uint8_t   CAAM_Type::RESERVED_17 [224]
 
__IO uint32_t   CAAM_Type::CC2CTXR [18]
 
uint8_t   CAAM_Type::RESERVED_18 [184]
 
__IO uint32_t   CAAM_Type::CC2KEYR [32]
 
uint8_t   CAAM_Type::RESERVED_19 [320]
 
__I uint32_t   CAAM_Type::CFIFOSTA
 
uint8_t   CAAM_Type::RESERVED_20 [12]
 
__O uint32_t   CAAM_Type::CNFIFO
 
__O uint32_t   CAAM_Type::CNFIFO_2
 
union {
   __O uint32_t   CAAM_Type::CNFIFO
 
   __O uint32_t   CAAM_Type::CNFIFO_2
 
} 
 
uint8_t   CAAM_Type::RESERVED_21 [12]
 
__O uint32_t   CAAM_Type::CIFIFO
 
uint8_t   CAAM_Type::RESERVED_22 [12]
 
__I uint64_t   CAAM_Type::COFIFO
 
uint8_t   CAAM_Type::RESERVED_23 [8]
 
__IO uint32_t   CAAM_Type::DJQCR_MS
 
__I uint32_t   CAAM_Type::DJQCR_LS
 
__I uint64_t   CAAM_Type::DDAR
 
__I uint32_t   CAAM_Type::DOPSTA_MS
 
__I uint32_t   CAAM_Type::DOPSTA_LS
 
uint8_t   CAAM_Type::RESERVED_24 [8]
 
__I uint32_t   CAAM_Type::DPDIDSR
 
__I uint32_t   CAAM_Type::DODIDSR
 
uint8_t   CAAM_Type::RESERVED_25 [24]
 
__IO uint32_t   CAAM_Type::DMTH_MS
 
__IO uint32_t   CAAM_Type::DMTH_LS
 
struct {
   __IO uint32_t   CAAM_Type::DMTH_MS
 
   __IO uint32_t   CAAM_Type::DMTH_LS
 
}   CAAM_Type::DDMTHB [4]
 
uint8_t   CAAM_Type::RESERVED_26 [32]
 
__IO uint32_t   CAAM_Type::DGTR_0
 
__IO uint32_t   CAAM_Type::DGTR_1
 
__IO uint32_t   CAAM_Type::DGTR_2
 
__IO uint32_t   CAAM_Type::DGTR_3
 
struct {
   __IO uint32_t   CAAM_Type::DGTR_0
 
   __IO uint32_t   CAAM_Type::DGTR_1
 
   __IO uint32_t   CAAM_Type::DGTR_2
 
   __IO uint32_t   CAAM_Type::DGTR_3
 
}   CAAM_Type::DDGTR [1]
 
uint8_t   CAAM_Type::RESERVED_27 [112]
 
__IO uint32_t   CAAM_Type::DSTR_0
 
__IO uint32_t   CAAM_Type::DSTR_1
 
__IO uint32_t   CAAM_Type::DSTR_2
 
__IO uint32_t   CAAM_Type::DSTR_3
 
struct {
   __IO uint32_t   CAAM_Type::DSTR_0
 
   __IO uint32_t   CAAM_Type::DSTR_1
 
   __IO uint32_t   CAAM_Type::DSTR_2
 
   __IO uint32_t   CAAM_Type::DSTR_3
 
}   CAAM_Type::DDSTR [1]
 
uint8_t   CAAM_Type::RESERVED_28 [240]
 
__IO uint32_t   CAAM_Type::DDESB [64]
 
uint8_t   CAAM_Type::RESERVED_29 [768]
 
__I uint32_t   CAAM_Type::DDJR
 
__I uint32_t   CAAM_Type::DDDR
 
__I uint64_t   CAAM_Type::DDJP
 
__I uint64_t   CAAM_Type::DSDP
 
__I uint32_t   CAAM_Type::DDDR_MS
 
__I uint32_t   CAAM_Type::DDDR_LS
 
__IO uint32_t   CAAM_Type::SOL
 
__IO uint32_t   CAAM_Type::VSOL
 
__IO uint32_t   CAAM_Type::SIL
 
__IO uint32_t   CAAM_Type::VSIL
 
__IO uint32_t   CAAM_Type::DPOVRD
 
__IO uint32_t   CAAM_Type::UVSOL
 
__IO uint32_t   CAAM_Type::UVSIL
 
struct {
   uint8_t   RESERVED_0 [4]
 
   union {
      __IO uint32_t   CAAM_Type::CC1MR
 
      __IO uint32_t   CAAM_Type::CC1MR_PK
 
      __IO uint32_t   CAAM_Type::CC1MR_RNG
 
   } 
 
   uint8_t   RESERVED_1 [4]
 
   __IO uint32_t   CAAM_Type::CC1KSR
 
   __IO uint64_t   CAAM_Type::CC1DSR
 
   uint8_t   RESERVED_2 [4]
 
   __IO uint32_t   CAAM_Type::CC1ICVSR
 
   uint8_t   RESERVED_3 [20]
 
   __O uint32_t   CAAM_Type::CCCTRL
 
   uint8_t   RESERVED_4 [4]
 
   __IO uint32_t   CAAM_Type::CICTL
 
   uint8_t   RESERVED_5 [4]
 
   __O uint32_t   CAAM_Type::CCWR
 
   __I uint32_t   CAAM_Type::CCSTA_MS
 
   __I uint32_t   CAAM_Type::CCSTA_LS
 
   uint8_t   RESERVED_6 [12]
 
   __IO uint32_t   CAAM_Type::CC1AADSZR
 
   uint8_t   RESERVED_7 [4]
 
   __IO uint32_t   CAAM_Type::CC1IVSZR
 
   uint8_t   RESERVED_8 [28]
 
   __IO uint32_t   CAAM_Type::CPKASZR
 
   uint8_t   RESERVED_9 [4]
 
   __IO uint32_t   CAAM_Type::CPKBSZR
 
   uint8_t   RESERVED_10 [4]
 
   __IO uint32_t   CAAM_Type::CPKNSZR
 
   uint8_t   RESERVED_11 [4]
 
   __IO uint32_t   CAAM_Type::CPKESZR
 
   uint8_t   RESERVED_12 [96]
 
   __IO uint32_t   CAAM_Type::CC1CTXR [16]
 
   uint8_t   RESERVED_13 [192]
 
   __IO uint32_t   CAAM_Type::CC1KR [8]
 
   uint8_t   RESERVED_14 [484]
 
   __IO uint32_t   CAAM_Type::CC2MR
 
   uint8_t   RESERVED_15 [4]
 
   __IO uint32_t   CAAM_Type::CC2KSR
 
   __IO uint64_t   CAAM_Type::CC2DSR
 
   uint8_t   RESERVED_16 [4]
 
   __IO uint32_t   CAAM_Type::CC2ICVSZR
 
   uint8_t   RESERVED_17 [224]
 
   __IO uint32_t   CAAM_Type::CC2CTXR [18]
 
   uint8_t   RESERVED_18 [184]
 
   __IO uint32_t   CAAM_Type::CC2KEYR [32]
 
   uint8_t   RESERVED_19 [320]
 
   __I uint32_t   CAAM_Type::CFIFOSTA
 
   uint8_t   RESERVED_20 [12]
 
   union {
      __O uint32_t   CAAM_Type::CNFIFO
 
      __O uint32_t   CAAM_Type::CNFIFO_2
 
   } 
 
   uint8_t   RESERVED_21 [12]
 
   __O uint32_t   CAAM_Type::CIFIFO
 
   uint8_t   RESERVED_22 [12]
 
   __I uint64_t   CAAM_Type::COFIFO
 
   uint8_t   RESERVED_23 [8]
 
   __IO uint32_t   CAAM_Type::DJQCR_MS
 
   __I uint32_t   CAAM_Type::DJQCR_LS
 
   __I uint64_t   CAAM_Type::DDAR
 
   __I uint32_t   CAAM_Type::DOPSTA_MS
 
   __I uint32_t   CAAM_Type::DOPSTA_LS
 
   uint8_t   RESERVED_24 [8]
 
   __I uint32_t   CAAM_Type::DPDIDSR
 
   __I uint32_t   CAAM_Type::DODIDSR
 
   uint8_t   RESERVED_25 [24]
 
   struct {
      __IO uint32_t   CAAM_Type::DMTH_MS
 
      __IO uint32_t   CAAM_Type::DMTH_LS
 
   }   DDMTHB [4]
 
   uint8_t   RESERVED_26 [32]
 
   struct {
      __IO uint32_t   CAAM_Type::DGTR_0
 
      __IO uint32_t   CAAM_Type::DGTR_1
 
      __IO uint32_t   CAAM_Type::DGTR_2
 
      __IO uint32_t   CAAM_Type::DGTR_3
 
   }   DDGTR [1]
 
   uint8_t   RESERVED_27 [112]
 
   struct {
      __IO uint32_t   CAAM_Type::DSTR_0
 
      __IO uint32_t   CAAM_Type::DSTR_1
 
      __IO uint32_t   CAAM_Type::DSTR_2
 
      __IO uint32_t   CAAM_Type::DSTR_3
 
   }   DDSTR [1]
 
   uint8_t   RESERVED_28 [240]
 
   __IO uint32_t   CAAM_Type::DDESB [64]
 
   uint8_t   RESERVED_29 [768]
 
   __I uint32_t   CAAM_Type::DDJR
 
   __I uint32_t   CAAM_Type::DDDR
 
   __I uint64_t   CAAM_Type::DDJP
 
   __I uint64_t   CAAM_Type::DSDP
 
   __I uint32_t   CAAM_Type::DDDR_MS
 
   __I uint32_t   CAAM_Type::DDDR_LS
 
   __IO uint32_t   CAAM_Type::SOL
 
   __IO uint32_t   CAAM_Type::VSOL
 
   __IO uint32_t   CAAM_Type::SIL
 
   __IO uint32_t   CAAM_Type::VSIL
 
   __IO uint32_t   CAAM_Type::DPOVRD
 
   __IO uint32_t   CAAM_Type::UVSOL
 
   __IO uint32_t   CAAM_Type::UVSIL
 
} CAAM_Type::DC [1]
 
uint8_t CAAM_Type::RESERVED_53 [356]
 
__I uint32_t CAAM_Type::CRNR_MS_DC01
 
__I uint32_t CAAM_Type::CRNR_LS_DC01
 
__I uint32_t CAAM_Type::CTPR_MS_DC01
 
__I uint32_t CAAM_Type::CTPR_LS_DC01
 
uint8_t CAAM_Type::RESERVED_54 [4]
 
__I uint32_t CAAM_Type::SMSTA_DC01
 
uint8_t CAAM_Type::RESERVED_55 [8]
 
__I uint64_t CAAM_Type::FAR_DC01
 
__I uint32_t CAAM_Type::FADID_DC01
 
__I uint32_t CAAM_Type::FADR_DC01
 
uint8_t CAAM_Type::RESERVED_56 [4]
 
__I uint32_t CAAM_Type::CSTA_DC01
 
__I uint32_t CAAM_Type::SMVID_MS_DC01
 
__I uint32_t CAAM_Type::SMVID_LS_DC01
 
__I uint32_t CAAM_Type::RVID_DC01
 
__I uint32_t CAAM_Type::CCBVID_DC01
 
__I uint32_t CAAM_Type::CHAVID_MS_DC01
 
__I uint32_t CAAM_Type::CHAVID_LS_DC01
 
__I uint32_t CAAM_Type::CHANUM_MS_DC01
 
__I uint32_t CAAM_Type::CHANUM_LS_DC01
 
__I uint32_t CAAM_Type::CAAMVID_MS_DC01
 
__I uint32_t CAAM_Type::CAAMVID_LS_DC01
 
__IO uint32_t CAN_Type::CBT
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [2]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [2]
 
}   CAN_Type::MB_8B [64]
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [4]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [4]
 
}   CAN_Type::MB_16B_L [21]
 
uint8_t   CAN_Type::RESERVED_0 [8]
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [4]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [4]
 
}   CAN_Type::MB_16B_H [21]
 
struct {
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [4]
 
   }   MB_16B_L [21]
 
   uint8_t   RESERVED_0 [8]
 
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [4]
 
   }   MB_16B_H [21]
 
}   CAN_Type::MB_16B
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [8]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [8]
 
}   CAN_Type::MB_32B_L [12]
 
uint8_t   CAN_Type::RESERVED_0 [32]
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [8]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [8]
 
}   CAN_Type::MB_32B_H [12]
 
struct {
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [8]
 
   }   MB_32B_L [12]
 
   uint8_t   RESERVED_0 [32]
 
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [8]
 
   }   MB_32B_H [12]
 
}   CAN_Type::MB_32B
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [16]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [16]
 
}   CAN_Type::MB_64B_L [7]
 
uint8_t   CAN_Type::RESERVED_0 [8]
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [16]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [16]
 
}   CAN_Type::MB_64B_H [7]
 
struct {
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [16]
 
   }   MB_64B_L [7]
 
   uint8_t   RESERVED_0 [8]
 
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [16]
 
   }   MB_64B_H [7]
 
}   CAN_Type::MB_64B
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD0
 
__IO uint32_t   CAN_Type::WORD1
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD0
 
   __IO uint32_t   CAN_Type::WORD1
 
}   CAN_Type::MB [64]
 
union {
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [2]
 
   }   MB_8B [64]
 
   struct {
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [4]
 
      }   MB_16B_L [21]
 
      uint8_t   RESERVED_0 [8]
 
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [4]
 
      }   MB_16B_H [21]
 
   }   MB_16B
 
   struct {
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [8]
 
      }   MB_32B_L [12]
 
      uint8_t   RESERVED_0 [32]
 
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [8]
 
      }   MB_32B_H [12]
 
   }   MB_32B
 
   struct {
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [16]
 
      }   MB_64B_L [7]
 
      uint8_t   RESERVED_0 [8]
 
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [16]
 
      }   MB_64B_H [7]
 
   }   MB_64B
 
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD0
 
      __IO uint32_t   CAN_Type::WORD1
 
   }   MB [64]
 
}; 
 
__IO uint32_t CAN_Type::MECR
 
__IO uint32_t CAN_Type::ERRIAR
 
__IO uint32_t CAN_Type::ERRIDPR
 
__IO uint32_t CAN_Type::ERRIPPR
 
__I uint32_t CAN_Type::RERRAR
 
__I uint32_t CAN_Type::RERRDR
 
__I uint32_t CAN_Type::RERRSYNR
 
__IO uint32_t CAN_Type::ERRSR
 
__IO uint32_t CAN_Type::FDCTRL
 
__IO uint32_t CAN_Type::FDCBT
 
__I uint32_t CAN_Type::FDCRC
 
uint8_t CAN_WRAPPER_Type::RESERVED_0 [2528]
 
__IO uint32_t CAN_WRAPPER_Type::GFWR
 
__IO uint32_t   CCM_Type::CONTROL
 
__IO uint32_t   CCM_Type::CONTROL_SET
 
__IO uint32_t   CCM_Type::CONTROL_CLR
 
__IO uint32_t   CCM_Type::CONTROL_TOG
 
uint8_t   CCM_Type::RESERVED_0 [16]
 
__I uint32_t   CCM_Type::STATUS0
 
__I uint32_t   CCM_Type::STATUS1
 
uint8_t   CCM_Type::RESERVED_1 [4]
 
__I uint32_t   CCM_Type::CONFIG
 
__IO uint32_t   CCM_Type::AUTHEN
 
__IO uint32_t   CCM_Type::AUTHEN_SET
 
__IO uint32_t   CCM_Type::AUTHEN_CLR
 
__IO uint32_t   CCM_Type::AUTHEN_TOG
 
__IO uint32_t   CCM_Type::SETPOINT [16]
 
struct {
   __IO uint32_t   CCM_Type::CONTROL
 
   __IO uint32_t   CCM_Type::CONTROL_SET
 
   __IO uint32_t   CCM_Type::CONTROL_CLR
 
   __IO uint32_t   CCM_Type::CONTROL_TOG
 
   uint8_t   RESERVED_0 [16]
 
   __I uint32_t   CCM_Type::STATUS0
 
   __I uint32_t   CCM_Type::STATUS1
 
   uint8_t   RESERVED_1 [4]
 
   __I uint32_t   CCM_Type::CONFIG
 
   __IO uint32_t   CCM_Type::AUTHEN
 
   __IO uint32_t   CCM_Type::AUTHEN_SET
 
   __IO uint32_t   CCM_Type::AUTHEN_CLR
 
   __IO uint32_t   CCM_Type::AUTHEN_TOG
 
   __IO uint32_t   CCM_Type::SETPOINT [16]
 
} CCM_Type::CLOCK_ROOT [79]
 
__IO uint32_t   CCM_Type::CONTROL
 
__IO uint32_t   CCM_Type::CONTROL_SET
 
__IO uint32_t   CCM_Type::CONTROL_CLR
 
__IO uint32_t   CCM_Type::CONTROL_TOG
 
uint8_t   CCM_Type::RESERVED_0 [16]
 
__IO uint32_t   CCM_Type::STATUS0
 
__I uint32_t   CCM_Type::STATUS1
 
uint8_t   CCM_Type::RESERVED_1 [4]
 
__I uint32_t   CCM_Type::CONFIG
 
__IO uint32_t   CCM_Type::AUTHEN
 
__IO uint32_t   CCM_Type::AUTHEN_SET
 
__IO uint32_t   CCM_Type::AUTHEN_CLR
 
__IO uint32_t   CCM_Type::AUTHEN_TOG
 
__IO uint32_t   CCM_Type::SETPOINT [16]
 
struct {
   __IO uint32_t   CCM_Type::CONTROL
 
   __IO uint32_t   CCM_Type::CONTROL_SET
 
   __IO uint32_t   CCM_Type::CONTROL_CLR
 
   __IO uint32_t   CCM_Type::CONTROL_TOG
 
   uint8_t   RESERVED_0 [16]
 
   __IO uint32_t   CCM_Type::STATUS0
 
   __I uint32_t   CCM_Type::STATUS1
 
   uint8_t   RESERVED_1 [4]
 
   __I uint32_t   CCM_Type::CONFIG
 
   __IO uint32_t   CCM_Type::AUTHEN
 
   __IO uint32_t   CCM_Type::AUTHEN_SET
 
   __IO uint32_t   CCM_Type::AUTHEN_CLR
 
   __IO uint32_t   CCM_Type::AUTHEN_TOG
 
   __IO uint32_t   CCM_Type::SETPOINT [16]
 
} CCM_Type::CLOCK_GROUP [2]
 
__IO uint32_t   CCM_Type::GPR_SHARED
 
__IO uint32_t   CCM_Type::SET
 
__IO uint32_t   CCM_Type::CLR
 
__IO uint32_t   CCM_Type::TOG
 
__IO uint32_t   CCM_Type::AUTHEN
 
__IO uint32_t   CCM_Type::AUTHEN_SET
 
__IO uint32_t   CCM_Type::AUTHEN_CLR
 
__IO uint32_t   CCM_Type::AUTHEN_TOG
 
struct {
   __IO uint32_t   CCM_Type::GPR_SHARED
 
   __IO uint32_t   CCM_Type::SET
 
   __IO uint32_t   CCM_Type::CLR
 
   __IO uint32_t   CCM_Type::TOG
 
   __IO uint32_t   CCM_Type::AUTHEN
 
   __IO uint32_t   CCM_Type::AUTHEN_SET
 
   __IO uint32_t   CCM_Type::AUTHEN_CLR
 
   __IO uint32_t   CCM_Type::AUTHEN_TOG
 
} CCM_Type::GPR_SHARED [8]
 
__IO uint32_t CCM_Type::GPR_PRIVATE1
 
__IO uint32_t CCM_Type::GPR_PRIVATE1_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE1_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE1_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN
 
__IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE2
 
__IO uint32_t CCM_Type::GPR_PRIVATE2_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE2_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE2_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN
 
__IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE3
 
__IO uint32_t CCM_Type::GPR_PRIVATE3_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE3_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE3_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN
 
__IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE4
 
__IO uint32_t CCM_Type::GPR_PRIVATE4_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE4_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE4_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN
 
__IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE5
 
__IO uint32_t CCM_Type::GPR_PRIVATE5_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE5_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE5_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN
 
__IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE6
 
__IO uint32_t CCM_Type::GPR_PRIVATE6_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE6_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE6_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN
 
__IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE7
 
__IO uint32_t CCM_Type::GPR_PRIVATE7_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE7_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE7_TOG
 
__IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN
 
__IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN_SET
 
__IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN_CLR
 
__IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN_TOG
 
__IO uint32_t   CCM_Type::DIRECT
 
__IO uint32_t   CCM_Type::DOMAINr
 
__IO uint32_t   CCM_Type::SETPOINT
 
uint8_t   CCM_Type::RESERVED_0 [4]
 
__I uint32_t   CCM_Type::STATUS0
 
__I uint32_t   CCM_Type::STATUS1
 
__I uint32_t   CCM_Type::CONFIG
 
__IO uint32_t   CCM_Type::AUTHEN
 
struct {
   __IO uint32_t   CCM_Type::DIRECT
 
   __IO uint32_t   CCM_Type::DOMAINr
 
   __IO uint32_t   CCM_Type::SETPOINT
 
   uint8_t   RESERVED_0 [4]
 
   __I uint32_t   CCM_Type::STATUS0
 
   __I uint32_t   CCM_Type::STATUS1
 
   __I uint32_t   CCM_Type::CONFIG
 
   __IO uint32_t   CCM_Type::AUTHEN
 
} CCM_Type::OSCPLL [29]
 
__IO uint32_t   CCM_Type::DIRECT
 
__IO uint32_t   CCM_Type::DOMAINr
 
__IO uint32_t   CCM_Type::SETPOINT
 
uint8_t   CCM_Type::RESERVED_0 [4]
 
__I uint32_t   CCM_Type::STATUS0
 
__I uint32_t   CCM_Type::STATUS1
 
__I uint32_t   CCM_Type::CONFIG
 
__IO uint32_t   CCM_Type::AUTHEN
 
struct {
   __IO uint32_t   CCM_Type::DIRECT
 
   __IO uint32_t   CCM_Type::DOMAINr
 
   __IO uint32_t   CCM_Type::SETPOINT
 
   uint8_t   RESERVED_0 [4]
 
   __I uint32_t   CCM_Type::STATUS0
 
   __I uint32_t   CCM_Type::STATUS1
 
   __I uint32_t   CCM_Type::CONFIG
 
   __IO uint32_t   CCM_Type::AUTHEN
 
} CCM_Type::LPCG [138]
 
__IO uint32_t   CCM_OBS_Type::CONTROL
 
__IO uint32_t   CCM_OBS_Type::CONTROL_SET
 
__IO uint32_t   CCM_OBS_Type::CONTROL_CLR
 
__IO uint32_t   CCM_OBS_Type::CONTROL_TOG
 
uint8_t   CCM_OBS_Type::RESERVED_0 [16]
 
__I uint32_t   CCM_OBS_Type::STATUS0
 
uint8_t   CCM_OBS_Type::RESERVED_1 [12]
 
__IO uint32_t   CCM_OBS_Type::AUTHEN
 
__IO uint32_t   CCM_OBS_Type::AUTHEN_SET
 
__IO uint32_t   CCM_OBS_Type::AUTHEN_CLR
 
__IO uint32_t   CCM_OBS_Type::AUTHEN_TOG
 
__I uint32_t   CCM_OBS_Type::FREQUENCY_CURRENT
 
__I uint32_t   CCM_OBS_Type::FREQUENCY_MIN
 
__I uint32_t   CCM_OBS_Type::FREQUENCY_MAX
 
uint8_t   CCM_OBS_Type::RESERVED_2 [52]
 
struct {
   __IO uint32_t   CCM_OBS_Type::CONTROL
 
   __IO uint32_t   CCM_OBS_Type::CONTROL_SET
 
   __IO uint32_t   CCM_OBS_Type::CONTROL_CLR
 
   __IO uint32_t   CCM_OBS_Type::CONTROL_TOG
 
   uint8_t   RESERVED_0 [16]
 
   __I uint32_t   CCM_OBS_Type::STATUS0
 
   uint8_t   RESERVED_1 [12]
 
   __IO uint32_t   CCM_OBS_Type::AUTHEN
 
   __IO uint32_t   CCM_OBS_Type::AUTHEN_SET
 
   __IO uint32_t   CCM_OBS_Type::AUTHEN_CLR
 
   __IO uint32_t   CCM_OBS_Type::AUTHEN_TOG
 
   __I uint32_t   CCM_OBS_Type::FREQUENCY_CURRENT
 
   __I uint32_t   CCM_OBS_Type::FREQUENCY_MIN
 
   __I uint32_t   CCM_OBS_Type::FREQUENCY_MAX
 
   uint8_t   RESERVED_2 [52]
 
} CCM_OBS_Type::OBSERVE [6]
 
__IO uint32_t CDOG_Type::CONTROL
 
__IO uint32_t CDOG_Type::RELOAD
 
__IO uint32_t CDOG_Type::INSTRUCTION_TIMER
 
__O uint32_t CDOG_Type::SECURE_COUNTER
 
__I uint32_t CDOG_Type::STATUS
 
__I uint32_t CDOG_Type::STATUS2
 
__IO uint32_t CDOG_Type::FLAGS
 
__IO uint32_t CDOG_Type::PERSISTENT
 
__O uint32_t CDOG_Type::START
 
__O uint32_t CDOG_Type::STOP
 
__O uint32_t CDOG_Type::RESTART
 
__O uint32_t CDOG_Type::ADD
 
__O uint32_t CDOG_Type::ADD1
 
__O uint32_t CDOG_Type::ADD16
 
__O uint32_t CDOG_Type::ADD256
 
__O uint32_t CDOG_Type::SUB
 
__O uint32_t CDOG_Type::SUB1
 
__O uint32_t CDOG_Type::SUB16
 
__O uint32_t CDOG_Type::SUB256
 
__I uint32_t CMP_Type::VERID
 
__I uint32_t CMP_Type::PARAM
 
__IO uint32_t CMP_Type::C0
 
__IO uint32_t CMP_Type::C1
 
__IO uint32_t CMP_Type::C2
 
__IO uint32_t CMP_Type::C3
 
__IO uint32_t CSI_Type::CR20
 
__IO uint32_t CSI_Type::CR [256]
 
__I uint32_t DAC_Type::VERID
 
__I uint32_t DAC_Type::PARAM
 
__O uint32_t DAC_Type::DATA
 
__IO uint32_t DAC_Type::CR
 
__I uint32_t DAC_Type::PTR
 
__IO uint32_t DAC_Type::CR2
 
__IO uint32_t DCDC_Type::CTRL0
 
__IO uint32_t DCDC_Type::CTRL1
 
__IO uint32_t DCDC_Type::REG4
 
__IO uint32_t DCDC_Type::REG5
 
__IO uint32_t DCDC_Type::REG6
 
__IO uint32_t DCDC_Type::REG7
 
__IO uint32_t DCDC_Type::REG7P
 
__IO uint32_t DCDC_Type::REG8
 
__IO uint32_t DCDC_Type::REG9
 
__IO uint32_t DCDC_Type::REG10
 
__IO uint32_t DCDC_Type::REG11
 
__IO uint32_t DCDC_Type::REG12
 
__IO uint32_t DCDC_Type::REG13
 
__IO uint32_t DCDC_Type::REG14
 
__IO uint32_t DCDC_Type::REG15
 
__IO uint32_t DCDC_Type::REG16
 
__IO uint32_t DCDC_Type::REG17
 
__IO uint32_t DCDC_Type::REG18
 
__IO uint32_t DCDC_Type::REG19
 
__IO uint32_t DCDC_Type::REG20
 
__IO uint32_t DCDC_Type::REG21
 
__IO uint32_t DCDC_Type::REG22
 
__IO uint32_t DCDC_Type::REG23
 
__IO uint32_t DCDC_Type::REG24
 
__IO uint32_t DCIC_Type::DCICC
 
__IO uint32_t DCIC_Type::DCICIC
 
__IO uint32_t DCIC_Type::DCICS
 
uint8_t DCIC_Type::RESERVED_0 [4]
 
__IO uint32_t   DCIC_Type::DCICRC
 
__IO uint32_t   DCIC_Type::DCICRS
 
__IO uint32_t   DCIC_Type::DCICRRS
 
__I uint32_t   DCIC_Type::DCICRCS
 
struct {
   __IO uint32_t   DCIC_Type::DCICRC
 
   __IO uint32_t   DCIC_Type::DCICRS
 
   __IO uint32_t   DCIC_Type::DCICRRS
 
   __I uint32_t   DCIC_Type::DCICRCS
 
} DCIC_Type::REGION [16]
 
__IO uint32_t   DMA_Type::SADDR
 
__IO uint16_t   DMA_Type::SOFF
 
__IO uint16_t   DMA_Type::ATTR
 
__IO uint32_t   DMA_Type::NBYTES_MLNO
 
__IO uint32_t   DMA_Type::NBYTES_MLOFFNO
 
__IO uint32_t   DMA_Type::NBYTES_MLOFFYES
 
union {
   __IO uint32_t   DMA_Type::NBYTES_MLNO
 
   __IO uint32_t   DMA_Type::NBYTES_MLOFFNO
 
   __IO uint32_t   DMA_Type::NBYTES_MLOFFYES
 
} 
 
__IO int32_t   DMA_Type::SLAST
 
__IO uint32_t   DMA_Type::DADDR
 
__IO uint16_t   DMA_Type::DOFF
 
__IO uint16_t   DMA_Type::CITER_ELINKNO
 
__IO uint16_t   DMA_Type::CITER_ELINKYES
 
union {
   __IO uint16_t   DMA_Type::CITER_ELINKNO
 
   __IO uint16_t   DMA_Type::CITER_ELINKYES
 
} 
 
__IO int32_t   DMA_Type::DLAST_SGA
 
__IO uint16_t   DMA_Type::CSR
 
__IO uint16_t   DMA_Type::BITER_ELINKNO
 
__IO uint16_t   DMA_Type::BITER_ELINKYES
 
union {
   __IO uint16_t   DMA_Type::BITER_ELINKNO
 
   __IO uint16_t   DMA_Type::BITER_ELINKYES
 
} 
 
struct {
   __IO uint32_t   DMA_Type::SADDR
 
   __IO uint16_t   DMA_Type::SOFF
 
   __IO uint16_t   DMA_Type::ATTR
 
   union {
      __IO uint32_t   DMA_Type::NBYTES_MLNO
 
      __IO uint32_t   DMA_Type::NBYTES_MLOFFNO
 
      __IO uint32_t   DMA_Type::NBYTES_MLOFFYES
 
   } 
 
   __IO int32_t   DMA_Type::SLAST
 
   __IO uint32_t   DMA_Type::DADDR
 
   __IO uint16_t   DMA_Type::DOFF
 
   union {
      __IO uint16_t   DMA_Type::CITER_ELINKNO
 
      __IO uint16_t   DMA_Type::CITER_ELINKYES
 
   } 
 
   __IO int32_t   DMA_Type::DLAST_SGA
 
   __IO uint16_t   DMA_Type::CSR
 
   union {
      __IO uint16_t   DMA_Type::BITER_ELINKNO
 
      __IO uint16_t   DMA_Type::BITER_ELINKYES
 
   } 
 
} DMA_Type::TCD [32]
 
__IO uint32_t DSI_HOST_Type::CFG_NUM_LANES
 
__IO uint32_t DSI_HOST_Type::CFG_NONCONTINUOUS_CLK
 
__IO uint32_t DSI_HOST_Type::CFG_T_PRE
 
__IO uint32_t DSI_HOST_Type::CFG_T_POST
 
__IO uint32_t DSI_HOST_Type::CFG_TX_GAP
 
__IO uint32_t DSI_HOST_Type::CFG_AUTOINSERT_EOTP
 
__IO uint32_t DSI_HOST_Type::CFG_EXTRA_CMDS_AFTER_EOTP
 
__IO uint32_t DSI_HOST_Type::CFG_HTX_TO_COUNT
 
__IO uint32_t DSI_HOST_Type::CFG_LRX_H_TO_COUNT
 
__IO uint32_t DSI_HOST_Type::CFG_BTA_H_TO_COUNT
 
__IO uint32_t DSI_HOST_Type::CFG_TWAKEUP
 
__I uint32_t DSI_HOST_Type::CFG_STATUS_OUT
 
__I uint32_t DSI_HOST_Type::RX_ERROR_STATUS
 
__IO uint32_t DSI_HOST_APB_PKT_IF_Type::TX_PAYLOAD
 
__IO uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_CONTROL
 
__IO uint32_t DSI_HOST_APB_PKT_IF_Type::SEND_PACKET
 
__I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_STATUS
 
__I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_FIFO_WR_LEVEL
 
__I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_FIFO_RD_LEVEL
 
__I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_RX_PAYLOAD
 
__I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_RX_PKT_HEADER
 
__I uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_STATUS
 
__I uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_STATUS2
 
__IO uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_MASK
 
__IO uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_MASK2
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::PIXEL_PAYLOAD_SIZE
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::PIXEL_FIFO_SEND_LEVEL
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::INTERFACE_COLOR_CODING
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::PIXEL_FORMAT
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::VSYNC_POLARITY
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::HSYNC_POLARITY
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::VIDEO_MODE
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::HFP
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::HBP
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::HSA
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::ENABLE_MULT_PKTS
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::VBP
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::VFP
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::BLLP_MODE
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::USE_NULL_PKT_BLLP
 
__IO uint32_t DSI_HOST_DPI_INTFC_Type::VACTIVE
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::PD_TX
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::M_PRG_HS_PREPARE
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::MC_PRG_HS_PREPARE
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::M_PRG_HS_ZERO
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::MC_PRG_HS_ZERO
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::M_PRG_HS_TRAIL
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::MC_PRG_HS_TRAIL
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::PD_PLL
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::TST
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::CN
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::CM
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::CO
 
__I uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::LOCK
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::LOCK_BYP
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::TX_RCAL
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::AUTO_PD_EN
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::RXLPRP
 
__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::RXCDRP
 
__I uint32_t EMVSIM_Type::VER_ID
 
__I uint32_t EMVSIM_Type::PARAM
 
__IO uint32_t EMVSIM_Type::CLKCFG
 
__IO uint32_t EMVSIM_Type::DIVISOR
 
__IO uint32_t EMVSIM_Type::CTRL
 
__IO uint32_t EMVSIM_Type::INT_MASK
 
__IO uint32_t EMVSIM_Type::RX_THD
 
__IO uint32_t EMVSIM_Type::TX_THD
 
__IO uint32_t EMVSIM_Type::RX_STATUS
 
__IO uint32_t EMVSIM_Type::TX_STATUS
 
__IO uint32_t EMVSIM_Type::PCSR
 
__I uint32_t EMVSIM_Type::RX_BUF
 
__O uint32_t EMVSIM_Type::TX_BUF
 
__IO uint32_t EMVSIM_Type::TX_GETU
 
__IO uint32_t EMVSIM_Type::CWT_VAL
 
__IO uint32_t EMVSIM_Type::BWT_VAL
 
__IO uint32_t EMVSIM_Type::BGT_VAL
 
__IO uint32_t EMVSIM_Type::GPCNT0_VAL
 
__IO uint32_t EMVSIM_Type::GPCNT1_VAL
 
__I uint16_t ENC_Type::LASTEDGE
 
__I uint16_t ENC_Type::LASTEDGEH
 
__I uint16_t ENC_Type::POSDPER
 
__I uint16_t ENC_Type::POSDPERBFR
 
__I uint16_t ENC_Type::POSDPERH
 
__IO uint16_t ENC_Type::CTRL3
 
__IO uint32_t ENET_Type::RDSR1
 
__IO uint32_t ENET_Type::TDSR1
 
__IO uint32_t ENET_Type::MRBR1
 
__IO uint32_t ENET_Type::RDSR2
 
__IO uint32_t ENET_Type::TDSR2
 
__IO uint32_t ENET_Type::MRBR2
 
__IO uint32_t ENET_Type::RCMR [2]
 
__IO uint32_t ENET_Type::DMACFG [2]
 
__IO uint32_t ENET_Type::RDAR1
 
__IO uint32_t ENET_Type::TDAR1
 
__IO uint32_t ENET_Type::RDAR2
 
__IO uint32_t ENET_Type::TDAR2
 
__IO uint32_t ENET_Type::QOS
 
uint32_t ENET_Type::IEEE_T_DROP
 
uint8_t ENET_Type::RESERVED_20 [488]
 
__IO uint32_t   ENET_Type::TCSR
 
__IO uint32_t   ENET_Type::TCCR
 
struct {
   __IO uint32_t   ENET_Type::TCSR
 
   __IO uint32_t   ENET_Type::TCCR
 
} ENET_Type::CHANNEL [4]
 
__IO uint32_t   ETHERNET_PLL_Type::RW
 
__IO uint32_t   ETHERNET_PLL_Type::SET
 
__IO uint32_t   ETHERNET_PLL_Type::CLR
 
__IO uint32_t   ETHERNET_PLL_Type::TOG
 
struct {
   __IO uint32_t   ETHERNET_PLL_Type::RW
 
   __IO uint32_t   ETHERNET_PLL_Type::SET
 
   __IO uint32_t   ETHERNET_PLL_Type::CLR
 
   __IO uint32_t   ETHERNET_PLL_Type::TOG
 
} ETHERNET_PLL_Type::CTRL0
 
__IO uint32_t   ETHERNET_PLL_Type::RW
 
__IO uint32_t   ETHERNET_PLL_Type::SET
 
__IO uint32_t   ETHERNET_PLL_Type::CLR
 
__IO uint32_t   ETHERNET_PLL_Type::TOG
 
struct {
   __IO uint32_t   ETHERNET_PLL_Type::RW
 
   __IO uint32_t   ETHERNET_PLL_Type::SET
 
   __IO uint32_t   ETHERNET_PLL_Type::CLR
 
   __IO uint32_t   ETHERNET_PLL_Type::TOG
 
} ETHERNET_PLL_Type::SPREAD_SPECTRUM
 
__IO uint32_t   ETHERNET_PLL_Type::RW
 
__IO uint32_t   ETHERNET_PLL_Type::SET
 
__IO uint32_t   ETHERNET_PLL_Type::CLR
 
__IO uint32_t   ETHERNET_PLL_Type::TOG
 
struct {
   __IO uint32_t   ETHERNET_PLL_Type::RW
 
   __IO uint32_t   ETHERNET_PLL_Type::SET
 
   __IO uint32_t   ETHERNET_PLL_Type::CLR
 
   __IO uint32_t   ETHERNET_PLL_Type::TOG
 
} ETHERNET_PLL_Type::NUMERATOR
 
__IO uint32_t   ETHERNET_PLL_Type::RW
 
__IO uint32_t   ETHERNET_PLL_Type::SET
 
__IO uint32_t   ETHERNET_PLL_Type::CLR
 
__IO uint32_t   ETHERNET_PLL_Type::TOG
 
struct {
   __IO uint32_t   ETHERNET_PLL_Type::RW
 
   __IO uint32_t   ETHERNET_PLL_Type::SET
 
   __IO uint32_t   ETHERNET_PLL_Type::CLR
 
   __IO uint32_t   ETHERNET_PLL_Type::TOG
 
} ETHERNET_PLL_Type::DENOMINATOR
 
__IO uint32_t FLEXIO_Type::TIMERSDEN
 
uint8_t FLEXIO_Type::RESERVED_15 [96]
 
uint8_t FLEXIO_Type::RESERVED_16 [96]
 
__IO uint32_t FLEXIO_Type::SHIFTBUFOES [8]
 
uint8_t FLEXIO_Type::RESERVED_17 [96]
 
__IO uint32_t FLEXIO_Type::SHIFTBUFEOS [8]
 
__IO uint32_t FLEXRAM_Type::OCRAM_MAGIC_ADDR
 
__IO uint32_t FLEXRAM_Type::DTCM_MAGIC_ADDR
 
__IO uint32_t FLEXRAM_Type::ITCM_MAGIC_ADDR
 
__I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_INFO
 
__I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_ADDR
 
__I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_DATA_LSB
 
__I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_DATA_MSB
 
__I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_INFO
 
__I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_ADDR
 
__I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_DATA_LSB
 
__I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_DATA_MSB
 
__I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_INFO
 
__I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_ADDR
 
__I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_DATA_LSB
 
__I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_DATA_MSB
 
__I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_INFO
 
__I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_ADDR
 
__I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_DATA_LSB
 
__I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_DATA_MSB
 
__I uint32_t FLEXRAM_Type::D0TCM_ECC_SINGLE_ERROR_INFO
 
__I uint32_t FLEXRAM_Type::D0TCM_ECC_SINGLE_ERROR_ADDR
 
__I uint32_t FLEXRAM_Type::D0TCM_ECC_SINGLE_ERROR_DATA
 
__I uint32_t FLEXRAM_Type::D0TCM_ECC_MULTI_ERROR_INFO
 
__I uint32_t FLEXRAM_Type::D0TCM_ECC_MULTI_ERROR_ADDR
 
__I uint32_t FLEXRAM_Type::D0TCM_ECC_MULTI_ERROR_DATA
 
__I uint32_t FLEXRAM_Type::D1TCM_ECC_SINGLE_ERROR_INFO
 
__I uint32_t FLEXRAM_Type::D1TCM_ECC_SINGLE_ERROR_ADDR
 
__I uint32_t FLEXRAM_Type::D1TCM_ECC_SINGLE_ERROR_DATA
 
__I uint32_t FLEXRAM_Type::D1TCM_ECC_MULTI_ERROR_INFO
 
__I uint32_t FLEXRAM_Type::D1TCM_ECC_MULTI_ERROR_ADDR
 
__I uint32_t FLEXRAM_Type::D1TCM_ECC_MULTI_ERROR_DATA
 
__IO uint32_t FLEXRAM_Type::FLEXRAM_CTRL
 
__I uint32_t FLEXRAM_Type::OCRAM_PIPELINE_STATUS
 
__I uint32_t FLEXSPI_Type::MISCCR4
 
__I uint32_t FLEXSPI_Type::MISCCR5
 
__I uint32_t FLEXSPI_Type::MISCCR6
 
__I uint32_t FLEXSPI_Type::MISCCR7
 
uint8_t FLEXSPI_Type::RESERVED_7 [256]
 
__IO uint32_t FLEXSPI_Type::HMSTRCR [8]
 
__IO uint32_t FLEXSPI_Type::HADDRSTART
 
__IO uint32_t FLEXSPI_Type::HADDREND
 
__IO uint32_t FLEXSPI_Type::HADDROFFSET
 
uint8_t FLEXSPI_Type::RESERVED_8 [4]
 
__IO uint32_t FLEXSPI_Type::IPSNSZSTART0
 
__IO uint32_t FLEXSPI_Type::IPSNSZEND0
 
__IO uint32_t FLEXSPI_Type::IPSNSZSTART1
 
__IO uint32_t FLEXSPI_Type::IPSNSZEND1
 
__IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART0
 
__IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND0
 
__IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART1
 
__IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND1
 
__IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART2
 
__IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND2
 
__IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART3
 
__IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND3
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_0 [4]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_AUTHEN_CTRL
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_INT_CTRL
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_MISC
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_MODE_CTRL
 
__I uint32_t GPC_CPU_MODE_CTRL_Type::CM_MODE_STAT
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_1 [232]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_IRQ_WAKEUP_MASK [8]
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_2 [32]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_NON_IRQ_WAKEUP_MASK
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_3 [12]
 
__I uint32_t GPC_CPU_MODE_CTRL_Type::CM_IRQ_WAKEUP_STAT [8]
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_4 [32]
 
__I uint32_t GPC_CPU_MODE_CTRL_Type::CM_NON_IRQ_WAKEUP_STAT
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_5 [108]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_SSAR_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_6 [4]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_LPCG_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_7 [4]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_PLL_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_8 [4]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_ISO_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_9 [4]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_RESET_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_10 [4]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_POWER_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_11 [100]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_POWER_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_12 [4]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_RESET_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_13 [4]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_ISO_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_14 [4]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_PLL_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_15 [4]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_LPCG_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_16 [4]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_SSAR_CTRL
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_17 [68]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SP_CTRL
 
__I uint32_t GPC_CPU_MODE_CTRL_Type::CM_SP_STAT
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_18 [8]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_RUN_MODE_MAPPING
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAIT_MODE_MAPPING
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_STOP_MODE_MAPPING
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SUSPEND_MODE_MAPPING
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SP_MAPPING [16]
 
uint8_t GPC_CPU_MODE_CTRL_Type::RESERVED_19 [32]
 
__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_STBY_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_0 [4]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_AUTHEN_CTRL
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_INT_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_1 [4]
 
__I uint32_t GPC_SET_POINT_CTRL_Type::SP_CPU_REQ
 
__I uint32_t GPC_SET_POINT_CTRL_Type::SP_SYS_STAT
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_2 [4]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ROSC_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_3 [32]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PRIORITY_0_7
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PRIORITY_8_15
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_4 [184]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_SSAR_SAVE_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_5 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LPCG_OFF_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_6 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_GROUP_DOWN_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_7 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ROOT_DOWN_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_8 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PLL_OFF_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_9 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ISO_ON_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_10 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_RESET_EARLY_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_11 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_POWER_OFF_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_12 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BIAS_OFF_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_13 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BG_PLDO_OFF_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_14 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LDO_PRE_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_15 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_DCDC_DOWN_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_16 [76]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_DCDC_UP_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_17 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LDO_POST_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_18 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BG_PLDO_ON_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_19 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BIAS_ON_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_20 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_POWER_ON_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_21 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_RESET_LATE_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_22 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ISO_OFF_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_23 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PLL_ON_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_24 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ROOT_UP_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_25 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_GROUP_UP_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_26 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LPCG_ON_CTRL
 
uint8_t GPC_SET_POINT_CTRL_Type::RESERVED_27 [12]
 
__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_SSAR_RESTORE_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_0 [4]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_AUTHEN_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_1 [4]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_MISC
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_2 [224]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_LPCG_IN_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_3 [12]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_PLL_IN_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_4 [12]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_BIAS_IN_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_5 [12]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_PLDO_IN_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_6 [4]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_BANDGAP_IN_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_7 [4]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_LDO_IN_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_8 [12]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_DCDC_IN_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_9 [12]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_PMIC_IN_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_10 [172]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_PMIC_OUT_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_11 [12]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_DCDC_OUT_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_12 [12]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_LDO_OUT_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_13 [12]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_BANDGAP_OUT_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_14 [4]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_PLDO_OUT_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_15 [4]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_BIAS_OUT_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_16 [12]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_PLL_OUT_CTRL
 
uint8_t GPC_STBY_CTRL_Type::RESERVED_17 [12]
 
__IO uint32_t GPC_STBY_CTRL_Type::STBY_LPCG_OUT_CTRL
 
__IO uint32_t IEE_Type::GCFG
 
__I uint32_t IEE_Type::STA
 
__IO uint32_t IEE_Type::TSTMD
 
__O uint32_t IEE_Type::DPAMS
 
uint8_t IEE_Type::RESERVED_0 [16]
 
__IO uint32_t IEE_Type::PC_S_LT
 
__IO uint32_t IEE_Type::PC_M_LT
 
uint8_t IEE_Type::RESERVED_1 [24]
 
__IO uint32_t IEE_Type::PC_BLK_ENC
 
__IO uint32_t IEE_Type::PC_BLK_DEC
 
uint8_t IEE_Type::RESERVED_2 [8]
 
__IO uint32_t IEE_Type::PC_SR_TRANS
 
__IO uint32_t IEE_Type::PC_SW_TRANS
 
__IO uint32_t IEE_Type::PC_MR_TRANS
 
__IO uint32_t IEE_Type::PC_MW_TRANS
 
uint8_t IEE_Type::RESERVED_3 [4]
 
__IO uint32_t IEE_Type::PC_M_MBR
 
uint8_t IEE_Type::RESERVED_4 [8]
 
__IO uint32_t IEE_Type::PC_SR_TBC_U
 
__IO uint32_t IEE_Type::PC_SR_TBC_L
 
__IO uint32_t IEE_Type::PC_SW_TBC_U
 
__IO uint32_t IEE_Type::PC_SW_TBC_L
 
__IO uint32_t IEE_Type::PC_MR_TBC_U
 
__IO uint32_t IEE_Type::PC_MR_TBC_L
 
__IO uint32_t IEE_Type::PC_MW_TBC_U
 
__IO uint32_t IEE_Type::PC_MW_TBC_L
 
__IO uint32_t IEE_Type::PC_SR_TLGTT
 
__IO uint32_t IEE_Type::PC_SW_TLGTT
 
__IO uint32_t IEE_Type::PC_MR_TLGTT
 
__IO uint32_t IEE_Type::PC_MW_TLGTT
 
__IO uint32_t IEE_Type::PC_SR_TLAT_U
 
__IO uint32_t IEE_Type::PC_SR_TLAT_L
 
__IO uint32_t IEE_Type::PC_SW_TLAT_U
 
__IO uint32_t IEE_Type::PC_SW_TLAT_L
 
__IO uint32_t IEE_Type::PC_MR_TLAT_U
 
__IO uint32_t IEE_Type::PC_MR_TLAT_L
 
__IO uint32_t IEE_Type::PC_MW_TLAT_U
 
__IO uint32_t IEE_Type::PC_MW_TLAT_L
 
__IO uint32_t IEE_Type::PC_SR_TNRT_U
 
__IO uint32_t IEE_Type::PC_SR_TNRT_L
 
__IO uint32_t IEE_Type::PC_SW_TNRT_U
 
__IO uint32_t IEE_Type::PC_SW_TNRT_L
 
uint8_t IEE_Type::RESERVED_5 [32]
 
__I uint32_t IEE_Type::VIDR1
 
uint8_t IEE_Type::RESERVED_6 [4]
 
__I uint32_t IEE_Type::AESVID
 
uint8_t IEE_Type::RESERVED_7 [4]
 
__IO uint32_t   IEE_Type::REGATTR
 
uint8_t   IEE_Type::RESERVED_0 [4]
 
__IO uint32_t   IEE_Type::REGPO
 
uint8_t   IEE_Type::RESERVED_1 [52]
 
__O uint32_t   IEE_Type::REGKEY1 [8]
 
uint8_t   IEE_Type::RESERVED_2 [32]
 
__O uint32_t   IEE_Type::REGKEY2 [8]
 
uint8_t   IEE_Type::RESERVED_3 [96]
 
struct {
   __IO uint32_t   IEE_Type::REGATTR
 
   uint8_t   RESERVED_0 [4]
 
   __IO uint32_t   IEE_Type::REGPO
 
   uint8_t   RESERVED_1 [52]
 
   __O uint32_t   IEE_Type::REGKEY1 [8]
 
   uint8_t   RESERVED_2 [32]
 
   __O uint32_t   IEE_Type::REGKEY2 [8]
 
   uint8_t   RESERVED_3 [96]
 
} IEE_Type::REGX [8]
 
uint8_t IEE_Type::RESERVED_8 [1536]
 
__IO uint32_t IEE_Type::AES_TST_DB [32]
 
__IO uint32_t IEE_APC_Type::REGION0_TOP_ADDR
 
__IO uint32_t IEE_APC_Type::REGION0_BOT_ADDR
 
__IO uint32_t IEE_APC_Type::REGION0_RDC_D0
 
__IO uint32_t IEE_APC_Type::REGION0_RDC_D1
 
__IO uint32_t IEE_APC_Type::REGION1_TOP_ADDR
 
__IO uint32_t IEE_APC_Type::REGION1_BOT_ADDR
 
__IO uint32_t IEE_APC_Type::REGION1_RDC_D0
 
__IO uint32_t IEE_APC_Type::REGION1_RDC_D1
 
__IO uint32_t IEE_APC_Type::REGION2_TOP_ADDR
 
__IO uint32_t IEE_APC_Type::REGION2_BOT_ADDR
 
__IO uint32_t IEE_APC_Type::REGION2_RDC_D0
 
__IO uint32_t IEE_APC_Type::REGION2_RDC_D1
 
__IO uint32_t IEE_APC_Type::REGION3_TOP_ADDR
 
__IO uint32_t IEE_APC_Type::REGION3_BOT_ADDR
 
__IO uint32_t IEE_APC_Type::REGION3_RDC_D0
 
__IO uint32_t IEE_APC_Type::REGION3_RDC_D1
 
__IO uint32_t IEE_APC_Type::REGION4_TOP_ADDR
 
__IO uint32_t IEE_APC_Type::REGION4_BOT_ADDR
 
__IO uint32_t IEE_APC_Type::REGION4_RDC_D0
 
__IO uint32_t IEE_APC_Type::REGION4_RDC_D1
 
__IO uint32_t IEE_APC_Type::REGION5_TOP_ADDR
 
__IO uint32_t IEE_APC_Type::REGION5_BOT_ADDR
 
__IO uint32_t IEE_APC_Type::REGION5_RDC_D0
 
__IO uint32_t IEE_APC_Type::REGION5_RDC_D1
 
__IO uint32_t IEE_APC_Type::REGION6_TOP_ADDR
 
__IO uint32_t IEE_APC_Type::REGION6_BOT_ADDR
 
__IO uint32_t IEE_APC_Type::REGION6_RDC_D0
 
__IO uint32_t IEE_APC_Type::REGION6_RDC_D1
 
__IO uint32_t IEE_APC_Type::REGION7_TOP_ADDR
 
__IO uint32_t IEE_APC_Type::REGION7_BOT_ADDR
 
__IO uint32_t IEE_APC_Type::REGION7_RDC_D0
 
__IO uint32_t IEE_APC_Type::REGION7_RDC_D1
 
__IO uint32_t IOMUXC_GPR_Type::GPR0
 
uint8_t IOMUXC_GPR_Type::RESERVED_0 [4]
 
__IO uint32_t IOMUXC_GPR_Type::GPR9
 
__IO uint32_t IOMUXC_GPR_Type::GPR15
 
uint8_t IOMUXC_GPR_Type::RESERVED_1 [4]
 
__IO uint32_t IOMUXC_GPR_Type::GPR26
 
__IO uint32_t IOMUXC_GPR_Type::GPR27
 
__IO uint32_t IOMUXC_GPR_Type::GPR28
 
__IO uint32_t IOMUXC_GPR_Type::GPR29
 
__IO uint32_t IOMUXC_GPR_Type::GPR30
 
__IO uint32_t IOMUXC_GPR_Type::GPR31
 
__IO uint32_t IOMUXC_GPR_Type::GPR32
 
__IO uint32_t IOMUXC_GPR_Type::GPR33
 
__IO uint32_t IOMUXC_GPR_Type::GPR34
 
__IO uint32_t IOMUXC_GPR_Type::GPR35
 
__IO uint32_t IOMUXC_GPR_Type::GPR36
 
__IO uint32_t IOMUXC_GPR_Type::GPR37
 
__IO uint32_t IOMUXC_GPR_Type::GPR38
 
__IO uint32_t IOMUXC_GPR_Type::GPR39
 
__IO uint32_t IOMUXC_GPR_Type::GPR40
 
__IO uint32_t IOMUXC_GPR_Type::GPR41
 
__IO uint32_t IOMUXC_GPR_Type::GPR42
 
__IO uint32_t IOMUXC_GPR_Type::GPR43
 
__IO uint32_t IOMUXC_GPR_Type::GPR44
 
__IO uint32_t IOMUXC_GPR_Type::GPR45
 
__IO uint32_t IOMUXC_GPR_Type::GPR46
 
__IO uint32_t IOMUXC_GPR_Type::GPR47
 
__IO uint32_t IOMUXC_GPR_Type::GPR48
 
__IO uint32_t IOMUXC_GPR_Type::GPR49
 
__IO uint32_t IOMUXC_GPR_Type::GPR50
 
__IO uint32_t IOMUXC_GPR_Type::GPR51
 
__IO uint32_t IOMUXC_GPR_Type::GPR52
 
__IO uint32_t IOMUXC_GPR_Type::GPR53
 
__IO uint32_t IOMUXC_GPR_Type::GPR54
 
__IO uint32_t IOMUXC_GPR_Type::GPR55
 
uint8_t IOMUXC_GPR_Type::RESERVED_2 [12]
 
__IO uint32_t IOMUXC_GPR_Type::GPR59
 
uint8_t IOMUXC_GPR_Type::RESERVED_3 [8]
 
__IO uint32_t IOMUXC_GPR_Type::GPR62
 
__I uint32_t IOMUXC_GPR_Type::GPR63
 
__IO uint32_t IOMUXC_GPR_Type::GPR64
 
__IO uint32_t IOMUXC_GPR_Type::GPR65
 
__IO uint32_t IOMUXC_GPR_Type::GPR66
 
__IO uint32_t IOMUXC_GPR_Type::GPR67
 
__IO uint32_t IOMUXC_GPR_Type::GPR68
 
__IO uint32_t IOMUXC_GPR_Type::GPR69
 
__IO uint32_t IOMUXC_GPR_Type::GPR70
 
__IO uint32_t IOMUXC_GPR_Type::GPR71
 
__IO uint32_t IOMUXC_GPR_Type::GPR72
 
__IO uint32_t IOMUXC_GPR_Type::GPR73
 
__IO uint32_t IOMUXC_GPR_Type::GPR74
 
__I uint32_t IOMUXC_GPR_Type::GPR75
 
__I uint32_t IOMUXC_GPR_Type::GPR76
 
__IO uint32_t IOMUXC_LPSR_Type::SW_MUX_CTL_PAD [16]
 
__IO uint32_t IOMUXC_LPSR_Type::SW_PAD_CTL_PAD [16]
 
__IO uint32_t IOMUXC_LPSR_Type::SELECT_INPUT [24]
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR0
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR1
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR2
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR3
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR4
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR5
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR6
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR7
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR8
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR9
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR10
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR11
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR12
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR13
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR14
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR15
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR16
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR17
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR18
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR19
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR20
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR21
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR22
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR23
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR24
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR25
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR26
 
uint8_t IOMUXC_LPSR_GPR_Type::RESERVED_0 [24]
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR33
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR34
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR35
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR36
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR37
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR38
 
__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR39
 
__I uint32_t IOMUXC_LPSR_GPR_Type::GPR40
 
__I uint32_t IOMUXC_LPSR_GPR_Type::GPR41
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_WAKEUP_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_TEST_MODE_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_POR_B_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_ONOFF_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_WAKEUP_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG
 
__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG
 
__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR [32]
 
__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR32
 
__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR33
 
__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR34
 
__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR35
 
__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR36
 
__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR37
 
__IO uint32_t   IPS_DOMAIN_Type::SLOT_CTRL
 
uint8_t   IPS_DOMAIN_Type::RESERVED_0 [12]
 
struct {
   __IO uint32_t   IPS_DOMAIN_Type::SLOT_CTRL
 
   uint8_t   RESERVED_0 [12]
 
} IPS_DOMAIN_Type::SLOT_CTRL [38]
 
__IO uint32_t KEY_MANAGER_Type::MASTER_KEY_CTRL
 
uint8_t KEY_MANAGER_Type::RESERVED_0 [12]
 
__IO uint32_t KEY_MANAGER_Type::OTFAD1_KEY_CTRL
 
uint8_t KEY_MANAGER_Type::RESERVED_1 [4]
 
__IO uint32_t KEY_MANAGER_Type::OTFAD2_KEY_CTRL
 
uint8_t KEY_MANAGER_Type::RESERVED_2 [4]
 
__IO uint32_t KEY_MANAGER_Type::IEE_KEY_CTRL
 
uint8_t KEY_MANAGER_Type::RESERVED_3 [12]
 
__IO uint32_t KEY_MANAGER_Type::PUF_KEY_CTRL
 
uint8_t KEY_MANAGER_Type::RESERVED_4 [972]
 
__IO uint32_t KEY_MANAGER_Type::SLOT0_CTRL
 
__IO uint32_t KEY_MANAGER_Type::SLOT1_CTRL
 
__IO uint32_t KEY_MANAGER_Type::SLOT2_CTRL
 
__IO uint32_t KEY_MANAGER_Type::SLOT3_CTRL
 
__IO uint32_t KEY_MANAGER_Type::SLOT4_CTRL
 
__IO uint32_t LCDIF_Type::THRES
 
__IO uint32_t   LCDIF_Type::PIGEON_0
 
uint8_t   LCDIF_Type::RESERVED_0 [12]
 
__IO uint32_t   LCDIF_Type::PIGEON_1
 
uint8_t   LCDIF_Type::RESERVED_1 [12]
 
__IO uint32_t   LCDIF_Type::PIGEON_2
 
uint8_t   LCDIF_Type::RESERVED_2 [28]
 
struct {
   __IO uint32_t   LCDIF_Type::PIGEON_0
 
   uint8_t   RESERVED_0 [12]
 
   __IO uint32_t   LCDIF_Type::PIGEON_1
 
   uint8_t   RESERVED_1 [12]
 
   __IO uint32_t   LCDIF_Type::PIGEON_2
 
   uint8_t   RESERVED_2 [28]
 
} LCDIF_Type::PIGEON [12]
 
__IO uint32_t LCDIFV2_Type::CTRL
 
__IO uint32_t LCDIFV2_Type::CTRL_SET
 
__IO uint32_t LCDIFV2_Type::CTRL_CLR
 
__IO uint32_t LCDIFV2_Type::CTRL_TOG
 
__IO uint32_t LCDIFV2_Type::DISP_PARA
 
__IO uint32_t LCDIFV2_Type::DISP_SIZE
 
__IO uint32_t LCDIFV2_Type::HSYN_PARA
 
__IO uint32_t LCDIFV2_Type::VSYN_PARA
 
__IO uint32_t   LCDIFV2_Type::INT_STATUS
 
__IO uint32_t   LCDIFV2_Type::INT_ENABLE
 
uint8_t   LCDIFV2_Type::RESERVED_0 [8]
 
struct {
   __IO uint32_t   LCDIFV2_Type::INT_STATUS
 
   __IO uint32_t   LCDIFV2_Type::INT_ENABLE
 
   uint8_t   RESERVED_0 [8]
 
} LCDIFV2_Type::INT [2]
 
__IO uint32_t LCDIFV2_Type::PDI_PARA
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL1
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL2
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL3
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL4
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL5
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL6
 
__IO uint32_t   LCDIFV2_Type::CSC_COEF0
 
__IO uint32_t   LCDIFV2_Type::CSC_COEF1
 
__IO uint32_t   LCDIFV2_Type::CSC_COEF2
 
uint8_t   LCDIFV2_Type::RESERVED_0 [28]
 
struct {
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL1
 
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL2
 
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL3
 
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL4
 
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL5
 
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL6
 
   __IO uint32_t   LCDIFV2_Type::CSC_COEF0
 
   __IO uint32_t   LCDIFV2_Type::CSC_COEF1
 
   __IO uint32_t   LCDIFV2_Type::CSC_COEF2
 
   uint8_t   RESERVED_0 [28]
 
} LCDIFV2_Type::LAYER [8]
 
__IO uint32_t LCDIFV2_Type::CLUT_LOAD
 
__IO uint32_t LMEM_Type::PCCCR
 
__IO uint32_t LMEM_Type::PCCLCR
 
__IO uint32_t LMEM_Type::PCCSAR
 
__IO uint32_t LMEM_Type::PCCCVR
 
uint8_t LMEM_Type::RESERVED_0 [2032]
 
__IO uint32_t LMEM_Type::PSCCR
 
__IO uint32_t LMEM_Type::PSCLCR
 
__IO uint32_t LMEM_Type::PSCSAR
 
__IO uint32_t LMEM_Type::PSCCVR
 
__I uint16_t MCM_Type::PLREV
 
__I uint16_t MCM_Type::PCT
 
__I uint32_t MCM_Type::MEMCFG
 
__I uint16_t MCM_Type::PLASC
 
__I uint16_t MCM_Type::PLAMC
 
__IO uint32_t MCM_Type::CR
 
__IO uint32_t MCM_Type::ISCR
 
uint8_t MCM_Type::RESERVED_0 [12]
 
__I uint32_t MCM_Type::FADR
 
__I uint32_t MCM_Type::FATR
 
__I uint32_t MCM_Type::FDR
 
uint8_t MCM_Type::RESERVED_1 [980]
 
__IO uint32_t MCM_Type::LMDR [4]
 
uint8_t MCM_Type::RESERVED_2 [112]
 
__IO uint32_t MCM_Type::LMPECR
 
uint8_t MCM_Type::RESERVED_3 [4]
 
__IO uint32_t MCM_Type::LMPEIR
 
uint8_t MCM_Type::RESERVED_4 [4]
 
__I uint32_t MCM_Type::LMFAR
 
__IO uint32_t MCM_Type::LMFATR
 
uint8_t MCM_Type::RESERVED_5 [8]
 
__I uint32_t MCM_Type::LMFDHR
 
__I uint32_t MCM_Type::LMFDLR
 
__IO uint32_t MECC_Type::ERR_STATUS
 
__IO uint32_t MECC_Type::ERR_STAT_EN
 
__IO uint32_t MECC_Type::ERR_SIG_EN
 
__IO uint32_t MECC_Type::ERR_DATA_INJ_LOW0
 
__IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH0
 
__IO uint32_t MECC_Type::ERR_ECC_INJ0
 
__IO uint32_t MECC_Type::ERR_DATA_INJ_LOW1
 
__IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH1
 
__IO uint32_t MECC_Type::ERR_ECC_INJ1
 
__IO uint32_t MECC_Type::ERR_DATA_INJ_LOW2
 
__IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH2
 
__IO uint32_t MECC_Type::ERR_ECC_INJ2
 
__IO uint32_t MECC_Type::ERR_DATA_INJ_LOW3
 
__IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH3
 
__IO uint32_t MECC_Type::ERR_ECC_INJ3
 
__I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC0
 
__I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW0
 
__I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH0
 
__I uint32_t MECC_Type::SINGLE_ERR_POS_LOW0
 
__I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH0
 
__I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC1
 
__I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW1
 
__I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH1
 
__I uint32_t MECC_Type::SINGLE_ERR_POS_LOW1
 
__I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH1
 
__I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC2
 
__I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW2
 
__I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH2
 
__I uint32_t MECC_Type::SINGLE_ERR_POS_LOW2
 
__I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH2
 
__I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC3
 
__I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW3
 
__I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH3
 
__I uint32_t MECC_Type::SINGLE_ERR_POS_LOW3
 
__I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH3
 
__I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC0
 
__I uint32_t MECC_Type::MULTI_ERR_DATA_LOW0
 
__I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH0
 
__I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC1
 
__I uint32_t MECC_Type::MULTI_ERR_DATA_LOW1
 
__I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH1
 
__I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC2
 
__I uint32_t MECC_Type::MULTI_ERR_DATA_LOW2
 
__I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH2
 
__I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC3
 
__I uint32_t MECC_Type::MULTI_ERR_DATA_LOW3
 
__I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH3
 
uint8_t MECC_Type::RESERVED_0 [68]
 
__IO uint32_t MECC_Type::PIPE_ECC_EN
 
__I uint32_t MECC_Type::PENDING_STAT
 
uint8_t MIPI_CSI2RX_Type::RESERVED_0 [256]
 
__IO uint32_t MIPI_CSI2RX_Type::CFG_NUM_LANES
 
__IO uint32_t MIPI_CSI2RX_Type::CFG_DISABLE_DATA_LANES
 
__I uint32_t MIPI_CSI2RX_Type::BIT_ERR
 
__I uint32_t MIPI_CSI2RX_Type::IRQ_STATUS
 
__IO uint32_t MIPI_CSI2RX_Type::IRQ_MASK
 
__I uint32_t MIPI_CSI2RX_Type::ULPS_STATUS
 
__I uint32_t MIPI_CSI2RX_Type::PPI_ERRSOT_HS
 
__I uint32_t MIPI_CSI2RX_Type::PPI_ERRSOTSYNC_HS
 
__I uint32_t MIPI_CSI2RX_Type::PPI_ERRESC
 
__I uint32_t MIPI_CSI2RX_Type::PPI_ERRSYNCESC
 
__I uint32_t MIPI_CSI2RX_Type::PPI_ERRCONTROL
 
__IO uint32_t MIPI_CSI2RX_Type::CFG_DISABLE_PAYLOAD_0
 
__IO uint32_t MIPI_CSI2RX_Type::CFG_DISABLE_PAYLOAD_1
 
uint8_t MIPI_CSI2RX_Type::RESERVED_1 [76]
 
__IO uint32_t MIPI_CSI2RX_Type::CFG_IGNORE_VC
 
__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_VC
 
__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_P_FIFO_SEND_LEVEL
 
__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_VSYNC
 
__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_HSYNC_FP
 
__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_HSYNC
 
__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_HSYNC_BP
 
__IO uint32_t MMCAU_Type::CASR
 
__IO uint32_t MMCAU_Type::CAA
 
__IO uint32_t MMCAU_Type::CA [9]
 
__IO uint32_t MU_Type::TR [4]
 
__I uint32_t MU_Type::RR [4]
 
__IO uint32_t MU_Type::SR
 
__IO uint32_t MU_Type::CR
 
__IO uint32_t OCOTP_Type::PDN
 
__IO uint32_t OCOTP_Type::OUT_STATUS
 
__IO uint32_t OCOTP_Type::OUT_STATUS_SET
 
__IO uint32_t OCOTP_Type::OUT_STATUS_CLR
 
__IO uint32_t OCOTP_Type::OUT_STATUS_TOG
 
__IO uint32_t   OCOTP_Type::READ_FUSE_DATA
 
uint8_t   OCOTP_Type::RESERVED_0 [12]
 
struct {
   __IO uint32_t   OCOTP_Type::READ_FUSE_DATA
 
   uint8_t   RESERVED_0 [12]
 
} OCOTP_Type::READ_FUSE_DATAS [4]
 
__IO uint32_t OCOTP_Type::SW_LOCK
 
__IO uint32_t OCOTP_Type::BIT_LOCK
 
__I uint32_t OCOTP_Type::LOCKED0
 
__I uint32_t OCOTP_Type::LOCKED1
 
__I uint32_t OCOTP_Type::LOCKED2
 
__I uint32_t OCOTP_Type::LOCKED3
 
__I uint32_t OCOTP_Type::LOCKED4
 
__I uint32_t   OCOTP_Type::FUSE
 
uint8_t   OCOTP_Type::RESERVED_0 [12]
 
struct {
   __I uint32_t   OCOTP_Type::FUSE
 
   uint8_t   RESERVED_0 [12]
 
} OCOTP_Type::FUSEN [144]
 
__IO uint32_t   OSC_RC_400M_Type::RW
 
__IO uint32_t   OSC_RC_400M_Type::SET
 
__IO uint32_t   OSC_RC_400M_Type::CLR
 
__IO uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __IO uint32_t   OSC_RC_400M_Type::RW
 
   __IO uint32_t   OSC_RC_400M_Type::SET
 
   __IO uint32_t   OSC_RC_400M_Type::CLR
 
   __IO uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::CTRL0
 
__IO uint32_t   OSC_RC_400M_Type::RW
 
__IO uint32_t   OSC_RC_400M_Type::SET
 
__IO uint32_t   OSC_RC_400M_Type::CLR
 
__IO uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __IO uint32_t   OSC_RC_400M_Type::RW
 
   __IO uint32_t   OSC_RC_400M_Type::SET
 
   __IO uint32_t   OSC_RC_400M_Type::CLR
 
   __IO uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::CTRL1
 
__IO uint32_t   OSC_RC_400M_Type::RW
 
__IO uint32_t   OSC_RC_400M_Type::SET
 
__IO uint32_t   OSC_RC_400M_Type::CLR
 
__IO uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __IO uint32_t   OSC_RC_400M_Type::RW
 
   __IO uint32_t   OSC_RC_400M_Type::SET
 
   __IO uint32_t   OSC_RC_400M_Type::CLR
 
   __IO uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::CTRL2
 
__IO uint32_t   OSC_RC_400M_Type::RW
 
__IO uint32_t   OSC_RC_400M_Type::SET
 
__IO uint32_t   OSC_RC_400M_Type::CLR
 
__IO uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __IO uint32_t   OSC_RC_400M_Type::RW
 
   __IO uint32_t   OSC_RC_400M_Type::SET
 
   __IO uint32_t   OSC_RC_400M_Type::CLR
 
   __IO uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::CTRL3
 
uint8_t OSC_RC_400M_Type::RESERVED_0 [16]
 
__I uint32_t   OSC_RC_400M_Type::RW
 
__I uint32_t   OSC_RC_400M_Type::SET
 
__I uint32_t   OSC_RC_400M_Type::CLR
 
__I uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __I uint32_t   OSC_RC_400M_Type::RW
 
   __I uint32_t   OSC_RC_400M_Type::SET
 
   __I uint32_t   OSC_RC_400M_Type::CLR
 
   __I uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::STAT0
 
__I uint32_t   OSC_RC_400M_Type::RW
 
__I uint32_t   OSC_RC_400M_Type::SET
 
__I uint32_t   OSC_RC_400M_Type::CLR
 
__I uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __I uint32_t   OSC_RC_400M_Type::RW
 
   __I uint32_t   OSC_RC_400M_Type::SET
 
   __I uint32_t   OSC_RC_400M_Type::CLR
 
   __I uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::STAT1
 
__I uint32_t   OSC_RC_400M_Type::RW
 
__I uint32_t   OSC_RC_400M_Type::SET
 
__I uint32_t   OSC_RC_400M_Type::CLR
 
__I uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __I uint32_t   OSC_RC_400M_Type::RW
 
   __I uint32_t   OSC_RC_400M_Type::SET
 
   __I uint32_t   OSC_RC_400M_Type::CLR
 
   __I uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::STAT2
 
uint8_t OTFAD_Type::RESERVED_0 [3072]
 
__IO uint32_t OTFAD_Type::CR
 
__IO uint32_t OTFAD_Type::SR
 
uint8_t OTFAD_Type::RESERVED_1 [248]
 
__IO uint32_t   OTFAD_Type::KEY [4]
 
__IO uint32_t   OTFAD_Type::CTR [2]
 
__IO uint32_t   OTFAD_Type::RGD_W0
 
__IO uint32_t   OTFAD_Type::RGD_W1
 
uint8_t   OTFAD_Type::RESERVED_0 [32]
 
struct {
   __IO uint32_t   OTFAD_Type::KEY [4]
 
   __IO uint32_t   OTFAD_Type::CTR [2]
 
   __IO uint32_t   OTFAD_Type::RGD_W0
 
   __IO uint32_t   OTFAD_Type::RGD_W1
 
   uint8_t   RESERVED_0 [32]
 
} OTFAD_Type::CTX [4]
 
__IO uint32_t PDM_Type::CTRL_1
 
__IO uint32_t PDM_Type::CTRL_2
 
__IO uint32_t PDM_Type::STAT
 
uint8_t PDM_Type::RESERVED_0 [4]
 
__IO uint32_t PDM_Type::FIFO_CTRL
 
__IO uint32_t PDM_Type::FIFO_STAT
 
uint8_t PDM_Type::RESERVED_1 [12]
 
__I uint32_t PDM_Type::DATACH [8]
 
uint8_t PDM_Type::RESERVED_2 [32]
 
__IO uint32_t PDM_Type::DC_CTRL
 
uint8_t PDM_Type::RESERVED_3 [12]
 
__IO uint32_t PDM_Type::RANGE_CTRL
 
uint8_t PDM_Type::RESERVED_4 [4]
 
__IO uint32_t PDM_Type::RANGE_STAT
 
uint8_t PDM_Type::RESERVED_5 [16]
 
__IO uint32_t PDM_Type::VAD0_CTRL_1
 
__IO uint32_t PDM_Type::VAD0_CTRL_2
 
__IO uint32_t PDM_Type::VAD0_STAT
 
__IO uint32_t PDM_Type::VAD0_SCONFIG
 
__IO uint32_t PDM_Type::VAD0_NCONFIG
 
__I uint32_t PDM_Type::VAD0_NDATA
 
__IO uint32_t PDM_Type::VAD0_ZCD
 
uint8_t PGMC_BPC_Type::RESERVED_0 [4]
 
__IO uint32_t PGMC_BPC_Type::BPC_AUTHEN_CTRL
 
uint8_t PGMC_BPC_Type::RESERVED_1 [8]
 
__IO uint32_t PGMC_BPC_Type::BPC_MODE
 
__IO uint32_t PGMC_BPC_Type::BPC_POWER_CTRL
 
uint8_t PGMC_BPC_Type::RESERVED_2 [20]
 
__IO uint32_t PGMC_BPC_Type::BPC_FLAG
 
uint8_t PGMC_BPC_Type::RESERVED_3 [16]
 
__IO uint32_t PGMC_BPC_Type::BPC_SSAR_SAVE_CTRL
 
__IO uint32_t PGMC_BPC_Type::BPC_SSAR_RESTORE_CTRL
 
uint8_t PGMC_CPC_Type::RESERVED_0 [4]
 
__IO uint32_t PGMC_CPC_Type::CPC_AUTHEN_CTRL
 
uint8_t PGMC_CPC_Type::RESERVED_1 [8]
 
__IO uint32_t PGMC_CPC_Type::CPC_CORE_MODE
 
__IO uint32_t PGMC_CPC_Type::CPC_CORE_POWER_CTRL
 
uint8_t PGMC_CPC_Type::RESERVED_2 [20]
 
__IO uint32_t PGMC_CPC_Type::CPC_FLAG
 
uint8_t PGMC_CPC_Type::RESERVED_3 [16]
 
__IO uint32_t PGMC_CPC_Type::CPC_CACHE_MODE
 
__IO uint32_t PGMC_CPC_Type::CPC_CACHE_CM_CTRL
 
__IO uint32_t PGMC_CPC_Type::CPC_CACHE_SP_CTRL_0
 
__IO uint32_t PGMC_CPC_Type::CPC_CACHE_SP_CTRL_1
 
uint8_t PGMC_CPC_Type::RESERVED_4 [112]
 
__IO uint32_t PGMC_CPC_Type::CPC_LMEM_MODE
 
__IO uint32_t PGMC_CPC_Type::CPC_LMEM_CM_CTRL
 
__IO uint32_t PGMC_CPC_Type::CPC_LMEM_SP_CTRL_0
 
__IO uint32_t PGMC_CPC_Type::CPC_LMEM_SP_CTRL_1
 
uint8_t PGMC_MIF_Type::RESERVED_0 [4]
 
__IO uint32_t PGMC_MIF_Type::MIF_AUTHEN_CTRL
 
uint8_t PGMC_MIF_Type::RESERVED_1 [8]
 
__IO uint32_t PGMC_MIF_Type::MIF_MLPL_SLEEP
 
uint8_t PGMC_MIF_Type::RESERVED_2 [12]
 
__IO uint32_t PGMC_MIF_Type::MIF_MLPL_IG
 
uint8_t PGMC_MIF_Type::RESERVED_3 [12]
 
__IO uint32_t PGMC_MIF_Type::MIF_MLPL_LS
 
uint8_t PGMC_MIF_Type::RESERVED_4 [12]
 
__IO uint32_t PGMC_MIF_Type::MIF_MLPL_HS
 
uint8_t PGMC_MIF_Type::RESERVED_5 [12]
 
__IO uint32_t PGMC_MIF_Type::MIF_MLPL_STDBY
 
uint8_t PGMC_MIF_Type::RESERVED_6 [12]
 
__IO uint32_t PGMC_MIF_Type::MIF_MLPL_ARR_PDN
 
uint8_t PGMC_MIF_Type::RESERVED_7 [12]
 
__IO uint32_t PGMC_MIF_Type::MIF_MLPL_PER_PDN
 
uint8_t PGMC_MIF_Type::RESERVED_8 [12]
 
__IO uint32_t PGMC_MIF_Type::MIF_MLPL_INITN
 
uint8_t PGMC_MIF_Type::RESERVED_9 [44]
 
__IO uint32_t PGMC_MIF_Type::MIF_MLPL_ISO
 
uint8_t PGMC_PPC_Type::RESERVED_0 [4]
 
__IO uint32_t PGMC_PPC_Type::PPC_AUTHEN_CTRL
 
uint8_t PGMC_PPC_Type::RESERVED_1 [8]
 
__IO uint32_t PGMC_PPC_Type::PPC_MODE
 
__IO uint32_t PGMC_PPC_Type::PPC_STBY_CM_CTRL
 
__IO uint32_t PGMC_PPC_Type::PPC_STBY_SP_CTRL
 
__IO uint32_t   PHY_LDO_Type::RW
 
__IO uint32_t   PHY_LDO_Type::SET
 
__IO uint32_t   PHY_LDO_Type::CLR
 
__IO uint32_t   PHY_LDO_Type::TOG
 
struct {
   __IO uint32_t   PHY_LDO_Type::RW
 
   __IO uint32_t   PHY_LDO_Type::SET
 
   __IO uint32_t   PHY_LDO_Type::CLR
 
   __IO uint32_t   PHY_LDO_Type::TOG
 
} PHY_LDO_Type::CTRL0
 
uint8_t PHY_LDO_Type::RESERVED_0 [64]
 
__I uint32_t   PHY_LDO_Type::RW
 
__I uint32_t   PHY_LDO_Type::SET
 
__I uint32_t   PHY_LDO_Type::CLR
 
__I uint32_t   PHY_LDO_Type::TOG
 
struct {
   __I uint32_t   PHY_LDO_Type::RW
 
   __I uint32_t   PHY_LDO_Type::SET
 
   __I uint32_t   PHY_LDO_Type::CLR
 
   __I uint32_t   PHY_LDO_Type::TOG
 
} PHY_LDO_Type::STAT0
 
__IO uint32_t   PIT_Type::LDVAL
 
__I uint32_t   PIT_Type::CVAL
 
__IO uint32_t   PIT_Type::TCTRL
 
__IO uint32_t   PIT_Type::TFLG
 
struct {
   __IO uint32_t   PIT_Type::LDVAL
 
   __I uint32_t   PIT_Type::CVAL
 
   __IO uint32_t   PIT_Type::TCTRL
 
   __IO uint32_t   PIT_Type::TFLG
 
} PIT_Type::CHANNEL [4]
 
__IO uint32_t PUF_Type::CTRL
 
__IO uint32_t PUF_Type::KEYINDEX
 
__IO uint32_t PUF_Type::KEYSIZE
 
uint8_t PUF_Type::RESERVED_0 [20]
 
__I uint32_t PUF_Type::STAT
 
uint8_t PUF_Type::RESERVED_1 [4]
 
__I uint32_t PUF_Type::ALLOW
 
uint8_t PUF_Type::RESERVED_2 [20]
 
__O uint32_t PUF_Type::KEYINPUT
 
__O uint32_t PUF_Type::CODEINPUT
 
__I uint32_t PUF_Type::CODEOUTPUT
 
uint8_t PUF_Type::RESERVED_3 [20]
 
__I uint32_t PUF_Type::KEYOUTINDEX
 
__I uint32_t PUF_Type::KEYOUTPUT
 
uint8_t PUF_Type::RESERVED_4 [116]
 
__IO uint32_t PUF_Type::IFSTAT
 
uint8_t PUF_Type::RESERVED_5 [28]
 
__I uint32_t PUF_Type::VERSION
 
__IO uint32_t PUF_Type::INTEN
 
__IO uint32_t PUF_Type::INTSTAT
 
__IO uint32_t PUF_Type::PWRCTRL
 
__IO uint32_t PUF_Type::CFG
 
uint8_t PUF_Type::RESERVED_6 [240]
 
__IO uint32_t PUF_Type::KEYLOCK
 
__IO uint32_t PUF_Type::KEYENABLE
 
__IO uint32_t PUF_Type::KEYRESET
 
__IO uint32_t PUF_Type::IDXBLK
 
__IO uint32_t PUF_Type::IDXBLK_DP
 
__IO uint32_t PUF_Type::KEYMASK [2]
 
uint8_t PUF_Type::RESERVED_7 [56]
 
__I uint32_t PUF_Type::IDXBLK_STATUS
 
__I uint32_t PUF_Type::IDXBLK_SHIFT
 
__I uint16_t   PWM_Type::CNT
 
__IO uint16_t   PWM_Type::INIT
 
__IO uint16_t   PWM_Type::CTRL2
 
__IO uint16_t   PWM_Type::CTRL
 
uint8_t   PWM_Type::RESERVED_0 [2]
 
__IO uint16_t   PWM_Type::VAL0
 
__IO uint16_t   PWM_Type::FRACVAL1
 
__IO uint16_t   PWM_Type::VAL1
 
__IO uint16_t   PWM_Type::FRACVAL2
 
__IO uint16_t   PWM_Type::VAL2
 
__IO uint16_t   PWM_Type::FRACVAL3
 
__IO uint16_t   PWM_Type::VAL3
 
__IO uint16_t   PWM_Type::FRACVAL4
 
__IO uint16_t   PWM_Type::VAL4
 
__IO uint16_t   PWM_Type::FRACVAL5
 
__IO uint16_t   PWM_Type::VAL5
 
__IO uint16_t   PWM_Type::FRCTRL
 
__IO uint16_t   PWM_Type::OCTRL
 
__IO uint16_t   PWM_Type::STS
 
__IO uint16_t   PWM_Type::INTEN
 
__IO uint16_t   PWM_Type::DMAEN
 
__IO uint16_t   PWM_Type::TCTRL
 
__IO uint16_t   PWM_Type::DISMAP [1]
 
uint8_t   PWM_Type::RESERVED_1 [2]
 
__IO uint16_t   PWM_Type::DTCNT0
 
__IO uint16_t   PWM_Type::DTCNT1
 
__IO uint16_t   PWM_Type::CAPTCTRLA
 
__IO uint16_t   PWM_Type::CAPTCOMPA
 
__IO uint16_t   PWM_Type::CAPTCTRLB
 
__IO uint16_t   PWM_Type::CAPTCOMPB
 
__IO uint16_t   PWM_Type::CAPTCTRLX
 
__IO uint16_t   PWM_Type::CAPTCOMPX
 
__I uint16_t   PWM_Type::CVAL0
 
__I uint16_t   PWM_Type::CVAL0CYC
 
__I uint16_t   PWM_Type::CVAL1
 
__I uint16_t   PWM_Type::CVAL1CYC
 
__I uint16_t   PWM_Type::CVAL2
 
__I uint16_t   PWM_Type::CVAL2CYC
 
__I uint16_t   PWM_Type::CVAL3
 
__I uint16_t   PWM_Type::CVAL3CYC
 
__I uint16_t   PWM_Type::CVAL4
 
__I uint16_t   PWM_Type::CVAL4CYC
 
__I uint16_t   PWM_Type::CVAL5
 
__I uint16_t   PWM_Type::CVAL5CYC
 
uint8_t   PWM_Type::RESERVED_2 [8]
 
struct {
   __I uint16_t   PWM_Type::CNT
 
   __IO uint16_t   PWM_Type::INIT
 
   __IO uint16_t   PWM_Type::CTRL2
 
   __IO uint16_t   PWM_Type::CTRL
 
   uint8_t   RESERVED_0 [2]
 
   __IO uint16_t   PWM_Type::VAL0
 
   __IO uint16_t   PWM_Type::FRACVAL1
 
   __IO uint16_t   PWM_Type::VAL1
 
   __IO uint16_t   PWM_Type::FRACVAL2
 
   __IO uint16_t   PWM_Type::VAL2
 
   __IO uint16_t   PWM_Type::FRACVAL3
 
   __IO uint16_t   PWM_Type::VAL3
 
   __IO uint16_t   PWM_Type::FRACVAL4
 
   __IO uint16_t   PWM_Type::VAL4
 
   __IO uint16_t   PWM_Type::FRACVAL5
 
   __IO uint16_t   PWM_Type::VAL5
 
   __IO uint16_t   PWM_Type::FRCTRL
 
   __IO uint16_t   PWM_Type::OCTRL
 
   __IO uint16_t   PWM_Type::STS
 
   __IO uint16_t   PWM_Type::INTEN
 
   __IO uint16_t   PWM_Type::DMAEN
 
   __IO uint16_t   PWM_Type::TCTRL
 
   __IO uint16_t   PWM_Type::DISMAP [1]
 
   uint8_t   RESERVED_1 [2]
 
   __IO uint16_t   PWM_Type::DTCNT0
 
   __IO uint16_t   PWM_Type::DTCNT1
 
   __IO uint16_t   PWM_Type::CAPTCTRLA
 
   __IO uint16_t   PWM_Type::CAPTCOMPA
 
   __IO uint16_t   PWM_Type::CAPTCTRLB
 
   __IO uint16_t   PWM_Type::CAPTCOMPB
 
   __IO uint16_t   PWM_Type::CAPTCTRLX
 
   __IO uint16_t   PWM_Type::CAPTCOMPX
 
   __I uint16_t   PWM_Type::CVAL0
 
   __I uint16_t   PWM_Type::CVAL0CYC
 
   __I uint16_t   PWM_Type::CVAL1
 
   __I uint16_t   PWM_Type::CVAL1CYC
 
   __I uint16_t   PWM_Type::CVAL2
 
   __I uint16_t   PWM_Type::CVAL2CYC
 
   __I uint16_t   PWM_Type::CVAL3
 
   __I uint16_t   PWM_Type::CVAL3CYC
 
   __I uint16_t   PWM_Type::CVAL4
 
   __I uint16_t   PWM_Type::CVAL4CYC
 
   __I uint16_t   PWM_Type::CVAL5
 
   __I uint16_t   PWM_Type::CVAL5CYC
 
   uint8_t   RESERVED_2 [8]
 
} PWM_Type::SM [4]
 
__I uint32_t RDC_Type::VIR
 
uint8_t RDC_Type::RESERVED_0 [32]
 
__IO uint32_t RDC_Type::STAT
 
__IO uint32_t RDC_Type::INTCTRL
 
__IO uint32_t RDC_Type::INTSTAT
 
uint8_t RDC_Type::RESERVED_1 [464]
 
__IO uint32_t RDC_Type::MDA [12]
 
uint8_t RDC_Type::RESERVED_2 [464]
 
__IO uint32_t RDC_Type::PDAP [128]
 
uint8_t RDC_Type::RESERVED_3 [512]
 
__IO uint32_t   RDC_Type::MRSA
 
__IO uint32_t   RDC_Type::MREA
 
__IO uint32_t   RDC_Type::MRC
 
__IO uint32_t   RDC_Type::MRVS
 
struct {
   __IO uint32_t   RDC_Type::MRSA
 
   __IO uint32_t   RDC_Type::MREA
 
   __IO uint32_t   RDC_Type::MRC
 
   __IO uint32_t   RDC_Type::MRVS
 
} RDC_Type::MR [59]
 
__IO uint8_t RDC_SEMAPHORE_Type::GATE [64]
 
uint8_t RDC_SEMAPHORE_Type::RESERVED_0 [2]
 
__IO uint16_t   RDC_SEMAPHORE_Type::RSTGT_R
 
__IO uint16_t   RDC_SEMAPHORE_Type::RSTGT_W
 
union {
   __IO uint16_t   RDC_SEMAPHORE_Type::RSTGT_R
 
   __IO uint16_t   RDC_SEMAPHORE_Type::RSTGT_W
 
}; 
 
__IO uint8_t SEMA4_Type::GATE [16]
 
uint8_t SEMA4_Type::RESERVED_0 [48]
 
__IO uint16_t   SEMA4_Type::CPINE
 
uint8_t   SEMA4_Type::RESERVED_0 [6]
 
struct {
   __IO uint16_t   SEMA4_Type::CPINE
 
   uint8_t   RESERVED_0 [6]
 
} SEMA4_Type::CPINE [2]
 
uint8_t SEMA4_Type::RESERVED_1 [48]
 
__I uint16_t   SEMA4_Type::CPNTF
 
uint8_t   SEMA4_Type::RESERVED_0 [6]
 
struct {
   __I uint16_t   SEMA4_Type::CPNTF
 
   uint8_t   RESERVED_0 [6]
 
} SEMA4_Type::CPNTF [2]
 
uint8_t SEMA4_Type::RESERVED_2 [112]
 
__IO uint16_t SEMA4_Type::RSTGT
 
uint8_t SEMA4_Type::RESERVED_3 [2]
 
__IO uint16_t SEMA4_Type::RSTNTF
 
__IO uint32_t SEMC_Type::DLLCR
 
__IO uint32_t SEMC_Type::NORCR3
 
__IO uint32_t SEMC_Type::DBICR2
 
__I uint32_t SEMC_Type::STS13
 
__IO uint32_t SEMC_Type::BR9
 
__IO uint32_t SEMC_Type::BR10
 
__IO uint32_t SEMC_Type::BR11
 
__IO uint32_t SEMC_Type::SRAMCR4
 
__IO uint32_t SEMC_Type::SRAMCR5
 
__IO uint32_t SEMC_Type::SRAMCR6
 
uint8_t SEMC_Type::RESERVED_4 [36]
 
__IO uint32_t SEMC_Type::DCCR
 
__IO uint32_t SNVS_Type::LPTGFCR
 
__IO uint32_t SNVS_Type::LPTDCR
 
__IO uint32_t SNVS_Type::LPTDC2R
 
__IO uint32_t SNVS_Type::LPTDSR
 
__IO uint32_t SNVS_Type::LPTGF1CR
 
__IO uint32_t SNVS_Type::LPTGF2CR
 
__O uint32_t SNVS_Type::LPATCR [5]
 
__IO uint32_t SNVS_Type::LPATCTLR
 
__IO uint32_t SNVS_Type::LPATCLKR
 
__IO uint32_t SNVS_Type::LPATRC1R
 
__IO uint32_t SNVS_Type::LPATRC2R
 
uint8_t SNVS_Type::RESERVED_4 [2792]
 
__O uint32_t   SPDIF_Type::SIC
 
__I uint32_t   SPDIF_Type::SIS
 
union {
   __O uint32_t   SPDIF_Type::SIC
 
   __I uint32_t   SPDIF_Type::SIS
 
}; 
 
uint8_t SRAM_Type::RESERVED_0 [12288]
 
__IO uint32_t SRAM_Type::CTRL
 
__IO uint32_t SRC_Type::SRMR
 
__IO uint32_t SRC_Type::AUTHEN_MEGA
 
__IO uint32_t SRC_Type::CTRL_MEGA
 
__IO uint32_t SRC_Type::SETPOINT_MEGA
 
__IO uint32_t SRC_Type::DOMAIN_MEGA
 
__IO uint32_t SRC_Type::STAT_MEGA
 
uint8_t SRC_Type::RESERVED_1 [12]
 
__IO uint32_t SRC_Type::AUTHEN_DISPLAY
 
__IO uint32_t SRC_Type::CTRL_DISPLAY
 
__IO uint32_t SRC_Type::SETPOINT_DISPLAY
 
__IO uint32_t SRC_Type::DOMAIN_DISPLAY
 
__IO uint32_t SRC_Type::STAT_DISPLAY
 
uint8_t SRC_Type::RESERVED_2 [12]
 
__IO uint32_t SRC_Type::AUTHEN_WAKEUP
 
__IO uint32_t SRC_Type::CTRL_WAKEUP
 
__IO uint32_t SRC_Type::SETPOINT_WAKEUP
 
__IO uint32_t SRC_Type::DOMAIN_WAKEUP
 
__IO uint32_t SRC_Type::STAT_WAKEUP
 
uint8_t SRC_Type::RESERVED_3 [44]
 
__IO uint32_t SRC_Type::AUTHEN_M4CORE
 
__IO uint32_t SRC_Type::CTRL_M4CORE
 
__IO uint32_t SRC_Type::SETPOINT_M4CORE
 
__IO uint32_t SRC_Type::DOMAIN_M4CORE
 
__IO uint32_t SRC_Type::STAT_M4CORE
 
uint8_t SRC_Type::RESERVED_4 [12]
 
__IO uint32_t SRC_Type::AUTHEN_M7CORE
 
__IO uint32_t SRC_Type::CTRL_M7CORE
 
__IO uint32_t SRC_Type::SETPOINT_M7CORE
 
__IO uint32_t SRC_Type::DOMAIN_M7CORE
 
__IO uint32_t SRC_Type::STAT_M7CORE
 
uint8_t SRC_Type::RESERVED_5 [12]
 
__IO uint32_t SRC_Type::AUTHEN_M4DEBUG
 
__IO uint32_t SRC_Type::CTRL_M4DEBUG
 
__IO uint32_t SRC_Type::SETPOINT_M4DEBUG
 
__IO uint32_t SRC_Type::DOMAIN_M4DEBUG
 
__IO uint32_t SRC_Type::STAT_M4DEBUG
 
uint8_t SRC_Type::RESERVED_6 [12]
 
__IO uint32_t SRC_Type::AUTHEN_M7DEBUG
 
__IO uint32_t SRC_Type::CTRL_M7DEBUG
 
__IO uint32_t SRC_Type::SETPOINT_M7DEBUG
 
__IO uint32_t SRC_Type::DOMAIN_M7DEBUG
 
__IO uint32_t SRC_Type::STAT_M7DEBUG
 
uint8_t SRC_Type::RESERVED_7 [12]
 
__IO uint32_t SRC_Type::AUTHEN_USBPHY1
 
__IO uint32_t SRC_Type::CTRL_USBPHY1
 
__IO uint32_t SRC_Type::SETPOINT_USBPHY1
 
__IO uint32_t SRC_Type::DOMAIN_USBPHY1
 
__IO uint32_t SRC_Type::STAT_USBPHY1
 
uint8_t SRC_Type::RESERVED_8 [12]
 
__IO uint32_t SRC_Type::AUTHEN_USBPHY2
 
__IO uint32_t SRC_Type::CTRL_USBPHY2
 
__IO uint32_t SRC_Type::SETPOINT_USBPHY2
 
__IO uint32_t SRC_Type::DOMAIN_USBPHY2
 
__IO uint32_t SRC_Type::STAT_USBPHY2
 
__IO uint32_t   SSARC_HP_Type::SRAM0
 
__IO uint32_t   SSARC_HP_Type::SRAM1
 
__IO uint32_t   SSARC_HP_Type::SRAM2
 
uint8_t   SSARC_HP_Type::RESERVED_0 [4]
 
struct {
   __IO uint32_t   SSARC_HP_Type::SRAM0
 
   __IO uint32_t   SSARC_HP_Type::SRAM1
 
   __IO uint32_t   SSARC_HP_Type::SRAM2
 
   uint8_t   RESERVED_0 [4]
 
} SSARC_HP_Type::DESC [1024]
 
__IO uint32_t   SSARC_LP_Type::DESC_CTRL0
 
__IO uint32_t   SSARC_LP_Type::DESC_CTRL1
 
__IO uint32_t   SSARC_LP_Type::DESC_ADDR_UP
 
__IO uint32_t   SSARC_LP_Type::DESC_ADDR_DOWN
 
uint8_t   SSARC_LP_Type::RESERVED_0 [16]
 
struct {
   __IO uint32_t   SSARC_LP_Type::DESC_CTRL0
 
   __IO uint32_t   SSARC_LP_Type::DESC_CTRL1
 
   __IO uint32_t   SSARC_LP_Type::DESC_ADDR_UP
 
   __IO uint32_t   SSARC_LP_Type::DESC_ADDR_DOWN
 
   uint8_t   RESERVED_0 [16]
 
} SSARC_LP_Type::GROUPS [16]
 
__IO uint32_t SSARC_LP_Type::CTRL
 
__IO uint32_t SSARC_LP_Type::INT_STATUS
 
__IO uint32_t SSARC_LP_Type::HP_TIMEOUT
 
uint8_t SSARC_LP_Type::RESERVED_1 [12]
 
__I uint32_t SSARC_LP_Type::HW_GROUP_PENDING
 
__I uint32_t SSARC_LP_Type::SW_GROUP_PENDING
 
__IO uint32_t TMPSNS_Type::CTRL0
 
__IO uint32_t TMPSNS_Type::CTRL0_SET
 
__IO uint32_t TMPSNS_Type::CTRL0_CLR
 
__IO uint32_t TMPSNS_Type::CTRL0_TOG
 
__IO uint32_t TMPSNS_Type::CTRL1
 
__IO uint32_t TMPSNS_Type::CTRL1_SET
 
__IO uint32_t TMPSNS_Type::CTRL1_CLR
 
__IO uint32_t TMPSNS_Type::CTRL1_TOG
 
__IO uint32_t TMPSNS_Type::RANGE0
 
__IO uint32_t TMPSNS_Type::RANGE0_SET
 
__IO uint32_t TMPSNS_Type::RANGE0_CLR
 
__IO uint32_t TMPSNS_Type::RANGE0_TOG
 
__IO uint32_t TMPSNS_Type::RANGE1
 
__IO uint32_t TMPSNS_Type::RANGE1_SET
 
__IO uint32_t TMPSNS_Type::RANGE1_CLR
 
__IO uint32_t TMPSNS_Type::RANGE1_TOG
 
uint8_t TMPSNS_Type::RESERVED_0 [16]
 
__IO uint32_t TMPSNS_Type::STATUS0
 
__IO uint16_t   TMR_Type::COMP1
 
__IO uint16_t   TMR_Type::COMP2
 
__IO uint16_t   TMR_Type::CAPT
 
__IO uint16_t   TMR_Type::LOAD
 
__IO uint16_t   TMR_Type::HOLD
 
__IO uint16_t   TMR_Type::CNTR
 
__IO uint16_t   TMR_Type::CTRL
 
__IO uint16_t   TMR_Type::SCTRL
 
__IO uint16_t   TMR_Type::CMPLD1
 
__IO uint16_t   TMR_Type::CMPLD2
 
__IO uint16_t   TMR_Type::CSCTRL
 
__IO uint16_t   TMR_Type::FILT
 
__IO uint16_t   TMR_Type::DMA
 
uint8_t   TMR_Type::RESERVED_0 [4]
 
__IO uint16_t   TMR_Type::ENBL
 
struct {
   __IO uint16_t   TMR_Type::COMP1
 
   __IO uint16_t   TMR_Type::COMP2
 
   __IO uint16_t   TMR_Type::CAPT
 
   __IO uint16_t   TMR_Type::LOAD
 
   __IO uint16_t   TMR_Type::HOLD
 
   __IO uint16_t   TMR_Type::CNTR
 
   __IO uint16_t   TMR_Type::CTRL
 
   __IO uint16_t   TMR_Type::SCTRL
 
   __IO uint16_t   TMR_Type::CMPLD1
 
   __IO uint16_t   TMR_Type::CMPLD2
 
   __IO uint16_t   TMR_Type::CSCTRL
 
   __IO uint16_t   TMR_Type::FILT
 
   __IO uint16_t   TMR_Type::DMA
 
   uint8_t   RESERVED_0 [4]
 
   __IO uint16_t   TMR_Type::ENBL
 
} TMR_Type::CHANNEL [4]
 
__IO uint32_t   USB_Type::DEVICEADDR
 
__IO uint32_t   USB_Type::PERIODICLISTBASE
 
union {
   __IO uint32_t   USB_Type::DEVICEADDR
 
   __IO uint32_t   USB_Type::PERIODICLISTBASE
 
}; 
 
__IO uint32_t   USB_Type::ASYNCLISTADDR
 
__IO uint32_t   USB_Type::ENDPTLISTADDR
 
union {
   __IO uint32_t   USB_Type::ASYNCLISTADDR
 
   __IO uint32_t   USB_Type::ENDPTLISTADDR
 
}; 
 
__IO uint32_t USBHSDCD_Type::CONTROL
 
__IO uint32_t USBHSDCD_Type::CLOCK
 
__I uint32_t USBHSDCD_Type::STATUS
 
__IO uint32_t USBHSDCD_Type::SIGNAL_OVERRIDE
 
__IO uint32_t USBHSDCD_Type::TIMER0
 
__IO uint32_t USBHSDCD_Type::TIMER1
 
__IO uint32_t   USBHSDCD_Type::TIMER2_BC11
 
__IO uint32_t   USBHSDCD_Type::TIMER2_BC12
 
union {
   __IO uint32_t   USBHSDCD_Type::TIMER2_BC11
 
   __IO uint32_t   USBHSDCD_Type::TIMER2_BC12
 
}; 
 
__IO uint32_t USBNC_Type::CTRL1
 
__IO uint32_t USBNC_Type::CTRL2
 
__IO uint32_t USBNC_Type::HSIC_CTRL
 
uint8_t USBPHY_Type::RESERVED_2 [28]
 
__IO uint32_t USBPHY_Type::PLL_SIC
 
__IO uint32_t USBPHY_Type::PLL_SIC_SET
 
__IO uint32_t USBPHY_Type::PLL_SIC_CLR
 
__IO uint32_t USBPHY_Type::PLL_SIC_TOG
 
uint8_t USBPHY_Type::RESERVED_3 [16]
 
__IO uint32_t USBPHY_Type::USB1_VBUS_DETECT
 
__IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_SET
 
__IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_CLR
 
__IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_TOG
 
__I uint32_t USBPHY_Type::USB1_VBUS_DET_STAT
 
uint8_t USBPHY_Type::RESERVED_4 [12]
 
__IO uint32_t USBPHY_Type::USB1_CHRG_DETECT
 
__IO uint32_t USBPHY_Type::USB1_CHRG_DETECT_SET
 
__IO uint32_t USBPHY_Type::USB1_CHRG_DETECT_CLR
 
__IO uint32_t USBPHY_Type::USB1_CHRG_DETECT_TOG
 
__I uint32_t USBPHY_Type::USB1_CHRG_DET_STAT
 
uint8_t USBPHY_Type::RESERVED_5 [12]
 
__IO uint32_t USBPHY_Type::ANACTRL
 
__IO uint32_t USBPHY_Type::ANACTRL_SET
 
__IO uint32_t USBPHY_Type::ANACTRL_CLR
 
__IO uint32_t USBPHY_Type::ANACTRL_TOG
 
__IO uint32_t USBPHY_Type::USB1_LOOPBACK
 
__IO uint32_t USBPHY_Type::USB1_LOOPBACK_SET
 
__IO uint32_t USBPHY_Type::USB1_LOOPBACK_CLR
 
__IO uint32_t USBPHY_Type::USB1_LOOPBACK_TOG
 
__IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT
 
__IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_SET
 
__IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_CLR
 
__IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_TOG
 
__IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN
 
__IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_SET
 
__IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_CLR
 
__IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_TOG
 
__IO uint32_t USDHC_Type::STROBE_DLL_CTRL
 
__I uint32_t USDHC_Type::STROBE_DLL_STATUS
 
uint8_t USDHC_Type::RESERVED_3 [72]
 
__IO uint32_t   VIDEO_MUX_Type::RW
 
__IO uint32_t   VIDEO_MUX_Type::SET
 
__IO uint32_t   VIDEO_MUX_Type::CLR
 
__IO uint32_t   VIDEO_MUX_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_MUX_Type::RW
 
   __IO uint32_t   VIDEO_MUX_Type::SET
 
   __IO uint32_t   VIDEO_MUX_Type::CLR
 
   __IO uint32_t   VIDEO_MUX_Type::TOG
 
} VIDEO_MUX_Type::VID_MUX_CTRL
 
uint8_t VIDEO_MUX_Type::RESERVED_0 [16]
 
__IO uint32_t   VIDEO_MUX_Type::RW
 
__IO uint32_t   VIDEO_MUX_Type::SET
 
__IO uint32_t   VIDEO_MUX_Type::CLR
 
__IO uint32_t   VIDEO_MUX_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_MUX_Type::RW
 
   __IO uint32_t   VIDEO_MUX_Type::SET
 
   __IO uint32_t   VIDEO_MUX_Type::CLR
 
   __IO uint32_t   VIDEO_MUX_Type::TOG
 
} VIDEO_MUX_Type::PLM_CTRL
 
__IO uint32_t   VIDEO_MUX_Type::RW
 
__IO uint32_t   VIDEO_MUX_Type::SET
 
__IO uint32_t   VIDEO_MUX_Type::CLR
 
__IO uint32_t   VIDEO_MUX_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_MUX_Type::RW
 
   __IO uint32_t   VIDEO_MUX_Type::SET
 
   __IO uint32_t   VIDEO_MUX_Type::CLR
 
   __IO uint32_t   VIDEO_MUX_Type::TOG
 
} VIDEO_MUX_Type::YUV420_CTRL
 
uint8_t VIDEO_MUX_Type::RESERVED_1 [16]
 
__IO uint32_t   VIDEO_MUX_Type::RW
 
__IO uint32_t   VIDEO_MUX_Type::SET
 
__IO uint32_t   VIDEO_MUX_Type::CLR
 
__IO uint32_t   VIDEO_MUX_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_MUX_Type::RW
 
   __IO uint32_t   VIDEO_MUX_Type::SET
 
   __IO uint32_t   VIDEO_MUX_Type::CLR
 
   __IO uint32_t   VIDEO_MUX_Type::TOG
 
} VIDEO_MUX_Type::CFG_DT_DISABLE
 
uint8_t VIDEO_MUX_Type::RESERVED_2 [16]
 
__IO uint32_t   VIDEO_MUX_Type::RW
 
__IO uint32_t   VIDEO_MUX_Type::SET
 
__IO uint32_t   VIDEO_MUX_Type::CLR
 
__IO uint32_t   VIDEO_MUX_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_MUX_Type::RW
 
   __IO uint32_t   VIDEO_MUX_Type::SET
 
   __IO uint32_t   VIDEO_MUX_Type::CLR
 
   __IO uint32_t   VIDEO_MUX_Type::TOG
 
} VIDEO_MUX_Type::MIPI_DSI_CTRL
 
__IO uint32_t   VIDEO_PLL_Type::RW
 
__IO uint32_t   VIDEO_PLL_Type::SET
 
__IO uint32_t   VIDEO_PLL_Type::CLR
 
__IO uint32_t   VIDEO_PLL_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_PLL_Type::RW
 
   __IO uint32_t   VIDEO_PLL_Type::SET
 
   __IO uint32_t   VIDEO_PLL_Type::CLR
 
   __IO uint32_t   VIDEO_PLL_Type::TOG
 
} VIDEO_PLL_Type::CTRL0
 
__IO uint32_t   VIDEO_PLL_Type::RW
 
__IO uint32_t   VIDEO_PLL_Type::SET
 
__IO uint32_t   VIDEO_PLL_Type::CLR
 
__IO uint32_t   VIDEO_PLL_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_PLL_Type::RW
 
   __IO uint32_t   VIDEO_PLL_Type::SET
 
   __IO uint32_t   VIDEO_PLL_Type::CLR
 
   __IO uint32_t   VIDEO_PLL_Type::TOG
 
} VIDEO_PLL_Type::SPREAD_SPECTRUM
 
__IO uint32_t   VIDEO_PLL_Type::RW
 
__IO uint32_t   VIDEO_PLL_Type::SET
 
__IO uint32_t   VIDEO_PLL_Type::CLR
 
__IO uint32_t   VIDEO_PLL_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_PLL_Type::RW
 
   __IO uint32_t   VIDEO_PLL_Type::SET
 
   __IO uint32_t   VIDEO_PLL_Type::CLR
 
   __IO uint32_t   VIDEO_PLL_Type::TOG
 
} VIDEO_PLL_Type::NUMERATOR
 
__IO uint32_t   VIDEO_PLL_Type::RW
 
__IO uint32_t   VIDEO_PLL_Type::SET
 
__IO uint32_t   VIDEO_PLL_Type::CLR
 
__IO uint32_t   VIDEO_PLL_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_PLL_Type::RW
 
   __IO uint32_t   VIDEO_PLL_Type::SET
 
   __IO uint32_t   VIDEO_PLL_Type::CLR
 
   __IO uint32_t   VIDEO_PLL_Type::TOG
 
} VIDEO_PLL_Type::DENOMINATOR
 
__IO uint32_t   VMBANDGAP_Type::RW
 
__IO uint32_t   VMBANDGAP_Type::SET
 
__IO uint32_t   VMBANDGAP_Type::CLR
 
__IO uint32_t   VMBANDGAP_Type::TOG
 
struct {
   __IO uint32_t   VMBANDGAP_Type::RW
 
   __IO uint32_t   VMBANDGAP_Type::SET
 
   __IO uint32_t   VMBANDGAP_Type::CLR
 
   __IO uint32_t   VMBANDGAP_Type::TOG
 
} VMBANDGAP_Type::CTRL0
 
uint8_t VMBANDGAP_Type::RESERVED_0 [64]
 
__I uint32_t   VMBANDGAP_Type::RW
 
__I uint32_t   VMBANDGAP_Type::SET
 
__I uint32_t   VMBANDGAP_Type::CLR
 
__I uint32_t   VMBANDGAP_Type::TOG
 
struct {
   __I uint32_t   VMBANDGAP_Type::RW
 
   __I uint32_t   VMBANDGAP_Type::SET
 
   __I uint32_t   VMBANDGAP_Type::CLR
 
   __I uint32_t   VMBANDGAP_Type::TOG
 
} VMBANDGAP_Type::STAT0
 
__IO uint16_t XBARA_Type::SEL66
 
__IO uint16_t XBARA_Type::SEL67
 
__IO uint16_t XBARA_Type::SEL68
 
__IO uint16_t XBARA_Type::SEL69
 
__IO uint16_t XBARA_Type::SEL70
 
__IO uint16_t XBARA_Type::SEL71
 
__IO uint16_t XBARA_Type::SEL72
 
__IO uint16_t XBARA_Type::SEL73
 
__IO uint16_t XBARA_Type::SEL74
 
__IO uint16_t XBARA_Type::SEL75
 
__IO uint16_t XBARA_Type::SEL76
 
__IO uint16_t XBARA_Type::SEL77
 
__IO uint16_t XBARA_Type::SEL78
 
__IO uint16_t XBARA_Type::SEL79
 
__IO uint16_t XBARA_Type::SEL80
 
__IO uint16_t XBARA_Type::SEL81
 
__IO uint16_t XBARA_Type::SEL82
 
__IO uint16_t XBARA_Type::SEL83
 
__IO uint16_t XBARA_Type::SEL84
 
__IO uint16_t XBARA_Type::SEL85
 
__IO uint16_t XBARA_Type::SEL86
 
__IO uint16_t XBARA_Type::SEL87
 
__IO uint32_t XECC_Type::ECC_CTRL
 
__IO uint32_t XECC_Type::ERR_STATUS
 
__IO uint32_t XECC_Type::ERR_STAT_EN
 
__IO uint32_t XECC_Type::ERR_SIG_EN
 
__IO uint32_t XECC_Type::ERR_DATA_INJ
 
__IO uint32_t XECC_Type::ERR_ECC_INJ
 
__I uint32_t XECC_Type::SINGLE_ERR_ADDR
 
__I uint32_t XECC_Type::SINGLE_ERR_DATA
 
__I uint32_t XECC_Type::SINGLE_ERR_ECC
 
__I uint32_t XECC_Type::SINGLE_ERR_POS
 
__I uint32_t XECC_Type::SINGLE_ERR_BIT_FIELD
 
__I uint32_t XECC_Type::MULTI_ERR_ADDR
 
__I uint32_t XECC_Type::MULTI_ERR_DATA
 
__I uint32_t XECC_Type::MULTI_ERR_ECC
 
__I uint32_t XECC_Type::MULTI_ERR_BIT_FIELD
 
__IO uint32_t XECC_Type::ECC_BASE_ADDR0
 
__IO uint32_t XECC_Type::ECC_END_ADDR0
 
__IO uint32_t XECC_Type::ECC_BASE_ADDR1
 
__IO uint32_t XECC_Type::ECC_END_ADDR1
 
__IO uint32_t XECC_Type::ECC_BASE_ADDR2
 
__IO uint32_t XECC_Type::ECC_END_ADDR2
 
__IO uint32_t XECC_Type::ECC_BASE_ADDR3
 
__IO uint32_t XECC_Type::ECC_END_ADDR3
 
__IO uint32_t XRDC2_Type::MCR
 
__I uint32_t XRDC2_Type::SR
 
uint8_t XRDC2_Type::RESERVED_0 [4088]
 
__IO uint32_t   XRDC2_Type::MSC_MSAC_W0
 
__IO uint32_t   XRDC2_Type::MSC_MSAC_W1
 
struct {
   __IO uint32_t   XRDC2_Type::MSC_MSAC_W0
 
   __IO uint32_t   XRDC2_Type::MSC_MSAC_W1
 
} XRDC2_Type::MSCI_MSAC_WK [128]
 
uint8_t XRDC2_Type::RESERVED_1 [3072]
 
__IO uint32_t   XRDC2_Type::MDAC_MDA_W0
 
__IO uint32_t   XRDC2_Type::MDAC_MDA_W1
 
struct {
   __IO uint32_t   XRDC2_Type::MDAC_MDA_W0
 
   __IO uint32_t   XRDC2_Type::MDAC_MDA_W1
 
} XRDC2_Type::MDACI_MDAJ [32][32]
 
__IO uint32_t   XRDC2_Type::PAC_PDAC_W0
 
__IO uint32_t   XRDC2_Type::PAC_PDAC_W1
 
struct {
   __IO uint32_t   XRDC2_Type::PAC_PDAC_W0
 
   __IO uint32_t   XRDC2_Type::PAC_PDAC_W1
 
} XRDC2_Type::PACI_PDACJ [8][256]
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W0
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W1
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W2
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W3
 
uint8_t   XRDC2_Type::RESERVED_0 [4]
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W5
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W6
 
uint8_t   XRDC2_Type::RESERVED_1 [4]
 
struct {
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W0
 
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W1
 
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W2
 
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W3
 
   uint8_t   RESERVED_0 [4]
 
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W5
 
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W6
 
   uint8_t   RESERVED_1 [4]
 
} XRDC2_Type::MRCI_MRGDJ [32][32]
 
__IO uint32_t   ADC_Type::CMDL
 
__IO uint32_t   ADC_Type::CMDH
 
struct {
   __IO uint32_t   ADC_Type::CMDL
 
   __IO uint32_t   ADC_Type::CMDH
 
} ADC_Type::CMD [15]
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CTRL
 
__IO uint32_t   ADC_ETC_Type::TRIGn_COUNTER
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_1_0
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_3_2
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_5_4
 
__IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_7_6
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_1_0
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_3_2
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_5_4
 
__I uint32_t   ADC_ETC_Type::TRIGn_RESULT_7_6
 
struct {
   __IO uint32_t   ADC_ETC_Type::TRIGn_CTRL
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_COUNTER
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_1_0
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_3_2
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_5_4
 
   __IO uint32_t   ADC_ETC_Type::TRIGn_CHAIN_7_6
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_1_0
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_3_2
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_5_4
 
   __I uint32_t   ADC_ETC_Type::TRIGn_RESULT_7_6
 
} ADC_ETC_Type::TRIG [8]
 
__IO uint16_t   AOI_Type::BFCRT01
 
__IO uint16_t   AOI_Type::BFCRT23
 
struct {
   __IO uint16_t   AOI_Type::BFCRT01
 
   __IO uint16_t   AOI_Type::BFCRT23
 
} AOI_Type::BFCRT [4]
 
__IO uint32_t   AUDIO_PLL_Type::RW
 
__IO uint32_t   AUDIO_PLL_Type::SET
 
__IO uint32_t   AUDIO_PLL_Type::CLR
 
__IO uint32_t   AUDIO_PLL_Type::TOG
 
struct {
   __IO uint32_t   AUDIO_PLL_Type::RW
 
   __IO uint32_t   AUDIO_PLL_Type::SET
 
   __IO uint32_t   AUDIO_PLL_Type::CLR
 
   __IO uint32_t   AUDIO_PLL_Type::TOG
 
} AUDIO_PLL_Type::CTRL0
 
__IO uint32_t   AUDIO_PLL_Type::RW
 
__IO uint32_t   AUDIO_PLL_Type::SET
 
__IO uint32_t   AUDIO_PLL_Type::CLR
 
__IO uint32_t   AUDIO_PLL_Type::TOG
 
struct {
   __IO uint32_t   AUDIO_PLL_Type::RW
 
   __IO uint32_t   AUDIO_PLL_Type::SET
 
   __IO uint32_t   AUDIO_PLL_Type::CLR
 
   __IO uint32_t   AUDIO_PLL_Type::TOG
 
} AUDIO_PLL_Type::SPREAD_SPECTRUM
 
__IO uint32_t   AUDIO_PLL_Type::RW
 
__IO uint32_t   AUDIO_PLL_Type::SET
 
__IO uint32_t   AUDIO_PLL_Type::CLR
 
__IO uint32_t   AUDIO_PLL_Type::TOG
 
struct {
   __IO uint32_t   AUDIO_PLL_Type::RW
 
   __IO uint32_t   AUDIO_PLL_Type::SET
 
   __IO uint32_t   AUDIO_PLL_Type::CLR
 
   __IO uint32_t   AUDIO_PLL_Type::TOG
 
} AUDIO_PLL_Type::NUMERATOR
 
__IO uint32_t   AUDIO_PLL_Type::RW
 
__IO uint32_t   AUDIO_PLL_Type::SET
 
__IO uint32_t   AUDIO_PLL_Type::CLR
 
__IO uint32_t   AUDIO_PLL_Type::TOG
 
struct {
   __IO uint32_t   AUDIO_PLL_Type::RW
 
   __IO uint32_t   AUDIO_PLL_Type::SET
 
   __IO uint32_t   AUDIO_PLL_Type::CLR
 
   __IO uint32_t   AUDIO_PLL_Type::TOG
 
} AUDIO_PLL_Type::DENOMINATOR
 
__IO uint32_t   CAAM_Type::JRDID_MS
 
__IO uint32_t   CAAM_Type::JRDID_LS
 
struct {
   __IO uint32_t   CAAM_Type::JRDID_MS
 
   __IO uint32_t   CAAM_Type::JRDID_LS
 
} CAAM_Type::JRADID [4]
 
__IO uint32_t   CAAM_Type::RTIC_DID
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
struct {
   __IO uint32_t   CAAM_Type::RTIC_DID
 
   uint8_t   RESERVED_0 [4]
 
} CAAM_Type::RTICADID [4]
 
__IO uint32_t   CAAM_Type::DECODID_MS
 
__IO uint32_t   CAAM_Type::DECODID_LS
 
struct {
   __IO uint32_t   CAAM_Type::DECODID_MS
 
   __IO uint32_t   CAAM_Type::DECODID_LS
 
} CAAM_Type::DECONDID [1]
 
__IO uint32_t   CAAM_Type::JRSMVBAR
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
struct {
   __IO uint32_t   CAAM_Type::JRSMVBAR
 
   uint8_t   RESERVED_0 [4]
 
} CAAM_Type::JRNSMVBAR [4]
 
__I uint32_t   CAAM_Type::DMA_AIDL_MAP_MS
 
__I uint32_t   CAAM_Type::DMA_AIDL_MAP_LS
 
__I uint32_t   CAAM_Type::DMA_AIDM_MAP_MS
 
__I uint32_t   CAAM_Type::DMA_AIDM_MAP_LS
 
struct {
   __I uint32_t   CAAM_Type::DMA_AIDL_MAP_MS
 
   __I uint32_t   CAAM_Type::DMA_AIDL_MAP_LS
 
   __I uint32_t   CAAM_Type::DMA_AIDM_MAP_MS
 
   __I uint32_t   CAAM_Type::DMA_AIDM_MAP_LS
 
} CAAM_Type::AID_CNTS [1]
 
__IO uint32_t   CAAM_Type::RTPKRMAX
 
__I uint32_t   CAAM_Type::RTPKRSQ
 
union {
   __IO uint32_t   CAAM_Type::RTPKRMAX
 
   __I uint32_t   CAAM_Type::RTPKRSQ
 
}; 
 
__IO uint32_t   CAAM_Type::RTSBLIM
 
__I uint32_t   CAAM_Type::RTTOTSAM
 
union {
   __IO uint32_t   CAAM_Type::RTSBLIM
 
   __I uint32_t   CAAM_Type::RTTOTSAM
 
}; 
 
__I uint32_t   CAAM_Type::RTFRQCNT
 
__I uint32_t   CAAM_Type::RTSCMC
 
__I uint32_t   CAAM_Type::RTSCR1C
 
__I uint32_t   CAAM_Type::RTSCR2C
 
__I uint32_t   CAAM_Type::RTSCR3C
 
__I uint32_t   CAAM_Type::RTSCR4C
 
__I uint32_t   CAAM_Type::RTSCR5C
 
__I uint32_t   CAAM_Type::RTSCR6PC
 
struct {
   __I uint32_t   CAAM_Type::RTFRQCNT
 
   __I uint32_t   CAAM_Type::RTSCMC
 
   __I uint32_t   CAAM_Type::RTSCR1C
 
   __I uint32_t   CAAM_Type::RTSCR2C
 
   __I uint32_t   CAAM_Type::RTSCR3C
 
   __I uint32_t   CAAM_Type::RTSCR4C
 
   __I uint32_t   CAAM_Type::RTSCR5C
 
   __I uint32_t   CAAM_Type::RTSCR6PC
 
}   CAAM_Type::COUNT
 
__IO uint32_t   CAAM_Type::RTFRQMAX
 
__IO uint32_t   CAAM_Type::RTSCML
 
__IO uint32_t   CAAM_Type::RTSCR1L
 
__IO uint32_t   CAAM_Type::RTSCR2L
 
__IO uint32_t   CAAM_Type::RTSCR3L
 
__IO uint32_t   CAAM_Type::RTSCR4L
 
__IO uint32_t   CAAM_Type::RTSCR5L
 
__IO uint32_t   CAAM_Type::RTSCR6PL
 
struct {
   __IO uint32_t   CAAM_Type::RTFRQMAX
 
   __IO uint32_t   CAAM_Type::RTSCML
 
   __IO uint32_t   CAAM_Type::RTSCR1L
 
   __IO uint32_t   CAAM_Type::RTSCR2L
 
   __IO uint32_t   CAAM_Type::RTSCR3L
 
   __IO uint32_t   CAAM_Type::RTSCR4L
 
   __IO uint32_t   CAAM_Type::RTSCR5L
 
   __IO uint32_t   CAAM_Type::RTSCR6PL
 
}   CAAM_Type::LIMIT
 
union {
   struct {
      __I uint32_t   CAAM_Type::RTFRQCNT
 
      __I uint32_t   CAAM_Type::RTSCMC
 
      __I uint32_t   CAAM_Type::RTSCR1C
 
      __I uint32_t   CAAM_Type::RTSCR2C
 
      __I uint32_t   CAAM_Type::RTSCR3C
 
      __I uint32_t   CAAM_Type::RTSCR4C
 
      __I uint32_t   CAAM_Type::RTSCR5C
 
      __I uint32_t   CAAM_Type::RTSCR6PC
 
   }   COUNT
 
   struct {
      __IO uint32_t   CAAM_Type::RTFRQMAX
 
      __IO uint32_t   CAAM_Type::RTSCML
 
      __IO uint32_t   CAAM_Type::RTSCR1L
 
      __IO uint32_t   CAAM_Type::RTSCR2L
 
      __IO uint32_t   CAAM_Type::RTSCR3L
 
      __IO uint32_t   CAAM_Type::RTSCR4L
 
      __IO uint32_t   CAAM_Type::RTSCR5L
 
      __IO uint32_t   CAAM_Type::RTSCR6PL
 
   }   LIMIT
 
}; 
 
__I uint32_t   CAAM_Type::PX_SDID_PG0
 
__IO uint32_t   CAAM_Type::PX_SMAPR_PG0
 
__IO uint32_t   CAAM_Type::PX_SMAG2_PG0
 
__IO uint32_t   CAAM_Type::PX_SMAG1_PG0
 
struct {
   __I uint32_t   CAAM_Type::PX_SDID_PG0
 
   __IO uint32_t   CAAM_Type::PX_SMAPR_PG0
 
   __IO uint32_t   CAAM_Type::PX_SMAG2_PG0
 
   __IO uint32_t   CAAM_Type::PX_SMAG1_PG0
 
} CAAM_Type::PX_PG0 [16]
 
__I uint64_t   CAAM_Type::HT_JD_ADDR
 
__I uint64_t   CAAM_Type::HT_SD_ADDR
 
__I uint32_t   CAAM_Type::HT_JQ_CTRL_MS
 
__I uint32_t   CAAM_Type::HT_JQ_CTRL_LS
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
__I uint32_t   CAAM_Type::HT_STATUS
 
struct {
   __I uint64_t   CAAM_Type::HT_JD_ADDR
 
   __I uint64_t   CAAM_Type::HT_SD_ADDR
 
   __I uint32_t   CAAM_Type::HT_JQ_CTRL_MS
 
   __I uint32_t   CAAM_Type::HT_JQ_CTRL_LS
 
   uint8_t   RESERVED_0 [4]
 
   __I uint32_t   CAAM_Type::HT_STATUS
 
} CAAM_Type::HTA [1]
 
__IO uint64_t   CAAM_Type::IRBAR_JR
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
__IO uint32_t   CAAM_Type::IRSR_JR
 
uint8_t   CAAM_Type::RESERVED_1 [4]
 
__IO uint32_t   CAAM_Type::IRSAR_JR
 
uint8_t   CAAM_Type::RESERVED_2 [4]
 
__IO uint32_t   CAAM_Type::IRJAR_JR
 
__IO uint64_t   CAAM_Type::ORBAR_JR
 
uint8_t   CAAM_Type::RESERVED_3 [4]
 
__IO uint32_t   CAAM_Type::ORSR_JR
 
uint8_t   CAAM_Type::RESERVED_4 [4]
 
__IO uint32_t   CAAM_Type::ORJRR_JR
 
uint8_t   CAAM_Type::RESERVED_5 [4]
 
__IO uint32_t   CAAM_Type::ORSFR_JR
 
uint8_t   CAAM_Type::RESERVED_6 [4]
 
__I uint32_t   CAAM_Type::JRSTAR_JR
 
uint8_t   CAAM_Type::RESERVED_7 [4]
 
__IO uint32_t   CAAM_Type::JRINTR_JR
 
__IO uint32_t   CAAM_Type::JRCFGR_JR_MS
 
__IO uint32_t   CAAM_Type::JRCFGR_JR_LS
 
uint8_t   CAAM_Type::RESERVED_8 [4]
 
__IO uint32_t   CAAM_Type::IRRIR_JR
 
uint8_t   CAAM_Type::RESERVED_9 [4]
 
__IO uint32_t   CAAM_Type::ORWIR_JR
 
uint8_t   CAAM_Type::RESERVED_10 [4]
 
__O uint32_t   CAAM_Type::JRCR_JR
 
uint8_t   CAAM_Type::RESERVED_11 [1684]
 
__I uint32_t   CAAM_Type::JRAAV
 
uint8_t   CAAM_Type::RESERVED_12 [248]
 
__I uint64_t   CAAM_Type::JRAAA [4]
 
uint8_t   CAAM_Type::RESERVED_13 [480]
 
__I uint32_t   CAAM_Type::PX_SDID_JR
 
__IO uint32_t   CAAM_Type::PX_SMAPR_JR
 
__IO uint32_t   CAAM_Type::PX_SMAG2_JR
 
__IO uint32_t   CAAM_Type::PX_SMAG1_JR
 
struct {
   __I uint32_t   CAAM_Type::PX_SDID_JR
 
   __IO uint32_t   CAAM_Type::PX_SMAPR_JR
 
   __IO uint32_t   CAAM_Type::PX_SMAG2_JR
 
   __IO uint32_t   CAAM_Type::PX_SMAG1_JR
 
}   CAAM_Type::PX_JR [16]
 
uint8_t   CAAM_Type::RESERVED_14 [228]
 
__O uint32_t   CAAM_Type::SMCR_JR
 
uint8_t   CAAM_Type::RESERVED_15 [4]
 
__I uint32_t   CAAM_Type::SMCSR_JR
 
uint8_t   CAAM_Type::RESERVED_16 [528]
 
__I uint32_t   CAAM_Type::REIR0JR
 
uint8_t   CAAM_Type::RESERVED_17 [4]
 
__I uint64_t   CAAM_Type::REIR2JR
 
__I uint32_t   CAAM_Type::REIR4JR
 
__I uint32_t   CAAM_Type::REIR5JR
 
uint8_t   CAAM_Type::RESERVED_18 [392]
 
__I uint32_t   CAAM_Type::CRNR_MS_JR
 
__I uint32_t   CAAM_Type::CRNR_LS_JR
 
__I uint32_t   CAAM_Type::CTPR_MS_JR
 
__I uint32_t   CAAM_Type::CTPR_LS_JR
 
uint8_t   CAAM_Type::RESERVED_19 [4]
 
__I uint32_t   CAAM_Type::SMSTA_JR
 
uint8_t   CAAM_Type::RESERVED_20 [4]
 
__I uint32_t   CAAM_Type::SMPO_JR
 
__I uint64_t   CAAM_Type::FAR_JR
 
__I uint32_t   CAAM_Type::FADID_JR
 
__I uint32_t   CAAM_Type::FADR_JR
 
uint8_t   CAAM_Type::RESERVED_21 [4]
 
__I uint32_t   CAAM_Type::CSTA_JR
 
__I uint32_t   CAAM_Type::SMVID_MS_JR
 
__I uint32_t   CAAM_Type::SMVID_LS_JR
 
__I uint32_t   CAAM_Type::RVID_JR
 
__I uint32_t   CAAM_Type::CCBVID_JR
 
__I uint32_t   CAAM_Type::CHAVID_MS_JR
 
__I uint32_t   CAAM_Type::CHAVID_LS_JR
 
__I uint32_t   CAAM_Type::CHANUM_MS_JR
 
__I uint32_t   CAAM_Type::CHANUM_LS_JR
 
__I uint32_t   CAAM_Type::CAAMVID_MS_JR
 
__I uint32_t   CAAM_Type::CAAMVID_LS_JR
 
uint8_t   CAAM_Type::RESERVED_22 [61440]
 
struct {
   __IO uint64_t   CAAM_Type::IRBAR_JR
 
   uint8_t   RESERVED_0 [4]
 
   __IO uint32_t   CAAM_Type::IRSR_JR
 
   uint8_t   RESERVED_1 [4]
 
   __IO uint32_t   CAAM_Type::IRSAR_JR
 
   uint8_t   RESERVED_2 [4]
 
   __IO uint32_t   CAAM_Type::IRJAR_JR
 
   __IO uint64_t   CAAM_Type::ORBAR_JR
 
   uint8_t   RESERVED_3 [4]
 
   __IO uint32_t   CAAM_Type::ORSR_JR
 
   uint8_t   RESERVED_4 [4]
 
   __IO uint32_t   CAAM_Type::ORJRR_JR
 
   uint8_t   RESERVED_5 [4]
 
   __IO uint32_t   CAAM_Type::ORSFR_JR
 
   uint8_t   RESERVED_6 [4]
 
   __I uint32_t   CAAM_Type::JRSTAR_JR
 
   uint8_t   RESERVED_7 [4]
 
   __IO uint32_t   CAAM_Type::JRINTR_JR
 
   __IO uint32_t   CAAM_Type::JRCFGR_JR_MS
 
   __IO uint32_t   CAAM_Type::JRCFGR_JR_LS
 
   uint8_t   RESERVED_8 [4]
 
   __IO uint32_t   CAAM_Type::IRRIR_JR
 
   uint8_t   RESERVED_9 [4]
 
   __IO uint32_t   CAAM_Type::ORWIR_JR
 
   uint8_t   RESERVED_10 [4]
 
   __O uint32_t   CAAM_Type::JRCR_JR
 
   uint8_t   RESERVED_11 [1684]
 
   __I uint32_t   CAAM_Type::JRAAV
 
   uint8_t   RESERVED_12 [248]
 
   __I uint64_t   CAAM_Type::JRAAA [4]
 
   uint8_t   RESERVED_13 [480]
 
   struct {
      __I uint32_t   CAAM_Type::PX_SDID_JR
 
      __IO uint32_t   CAAM_Type::PX_SMAPR_JR
 
      __IO uint32_t   CAAM_Type::PX_SMAG2_JR
 
      __IO uint32_t   CAAM_Type::PX_SMAG1_JR
 
   }   PX_JR [16]
 
   uint8_t   RESERVED_14 [228]
 
   __O uint32_t   CAAM_Type::SMCR_JR
 
   uint8_t   RESERVED_15 [4]
 
   __I uint32_t   CAAM_Type::SMCSR_JR
 
   uint8_t   RESERVED_16 [528]
 
   __I uint32_t   CAAM_Type::REIR0JR
 
   uint8_t   RESERVED_17 [4]
 
   __I uint64_t   CAAM_Type::REIR2JR
 
   __I uint32_t   CAAM_Type::REIR4JR
 
   __I uint32_t   CAAM_Type::REIR5JR
 
   uint8_t   RESERVED_18 [392]
 
   __I uint32_t   CAAM_Type::CRNR_MS_JR
 
   __I uint32_t   CAAM_Type::CRNR_LS_JR
 
   __I uint32_t   CAAM_Type::CTPR_MS_JR
 
   __I uint32_t   CAAM_Type::CTPR_LS_JR
 
   uint8_t   RESERVED_19 [4]
 
   __I uint32_t   CAAM_Type::SMSTA_JR
 
   uint8_t   RESERVED_20 [4]
 
   __I uint32_t   CAAM_Type::SMPO_JR
 
   __I uint64_t   CAAM_Type::FAR_JR
 
   __I uint32_t   CAAM_Type::FADID_JR
 
   __I uint32_t   CAAM_Type::FADR_JR
 
   uint8_t   RESERVED_21 [4]
 
   __I uint32_t   CAAM_Type::CSTA_JR
 
   __I uint32_t   CAAM_Type::SMVID_MS_JR
 
   __I uint32_t   CAAM_Type::SMVID_LS_JR
 
   __I uint32_t   CAAM_Type::RVID_JR
 
   __I uint32_t   CAAM_Type::CCBVID_JR
 
   __I uint32_t   CAAM_Type::CHAVID_MS_JR
 
   __I uint32_t   CAAM_Type::CHAVID_LS_JR
 
   __I uint32_t   CAAM_Type::CHANUM_MS_JR
 
   __I uint32_t   CAAM_Type::CHANUM_LS_JR
 
   __I uint32_t   CAAM_Type::CAAMVID_MS_JR
 
   __I uint32_t   CAAM_Type::CAAMVID_LS_JR
 
   uint8_t   RESERVED_22 [61440]
 
} CAAM_Type::JOBRING [4]
 
__IO uint64_t   CAAM_Type::RMA
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
__IO uint32_t   CAAM_Type::RML
 
struct {
   __IO uint64_t   CAAM_Type::RMA
 
   uint8_t   RESERVED_0 [4]
 
   __IO uint32_t   CAAM_Type::RML
 
} CAAM_Type::RM [4][2]
 
uint8_t   CAAM_Type::RESERVED_0 [4]
 
__IO uint32_t   CAAM_Type::CC1MR
 
__IO uint32_t   CAAM_Type::CC1MR_PK
 
__IO uint32_t   CAAM_Type::CC1MR_RNG
 
union {
   __IO uint32_t   CAAM_Type::CC1MR
 
   __IO uint32_t   CAAM_Type::CC1MR_PK
 
   __IO uint32_t   CAAM_Type::CC1MR_RNG
 
} 
 
uint8_t   CAAM_Type::RESERVED_1 [4]
 
__IO uint32_t   CAAM_Type::CC1KSR
 
__IO uint64_t   CAAM_Type::CC1DSR
 
uint8_t   CAAM_Type::RESERVED_2 [4]
 
__IO uint32_t   CAAM_Type::CC1ICVSR
 
uint8_t   CAAM_Type::RESERVED_3 [20]
 
__O uint32_t   CAAM_Type::CCCTRL
 
uint8_t   CAAM_Type::RESERVED_4 [4]
 
__IO uint32_t   CAAM_Type::CICTL
 
uint8_t   CAAM_Type::RESERVED_5 [4]
 
__O uint32_t   CAAM_Type::CCWR
 
__I uint32_t   CAAM_Type::CCSTA_MS
 
__I uint32_t   CAAM_Type::CCSTA_LS
 
uint8_t   CAAM_Type::RESERVED_6 [12]
 
__IO uint32_t   CAAM_Type::CC1AADSZR
 
uint8_t   CAAM_Type::RESERVED_7 [4]
 
__IO uint32_t   CAAM_Type::CC1IVSZR
 
uint8_t   CAAM_Type::RESERVED_8 [28]
 
__IO uint32_t   CAAM_Type::CPKASZR
 
uint8_t   CAAM_Type::RESERVED_9 [4]
 
__IO uint32_t   CAAM_Type::CPKBSZR
 
uint8_t   CAAM_Type::RESERVED_10 [4]
 
__IO uint32_t   CAAM_Type::CPKNSZR
 
uint8_t   CAAM_Type::RESERVED_11 [4]
 
__IO uint32_t   CAAM_Type::CPKESZR
 
uint8_t   CAAM_Type::RESERVED_12 [96]
 
__IO uint32_t   CAAM_Type::CC1CTXR [16]
 
uint8_t   CAAM_Type::RESERVED_13 [192]
 
__IO uint32_t   CAAM_Type::CC1KR [8]
 
uint8_t   CAAM_Type::RESERVED_14 [484]
 
__IO uint32_t   CAAM_Type::CC2MR
 
uint8_t   CAAM_Type::RESERVED_15 [4]
 
__IO uint32_t   CAAM_Type::CC2KSR
 
__IO uint64_t   CAAM_Type::CC2DSR
 
uint8_t   CAAM_Type::RESERVED_16 [4]
 
__IO uint32_t   CAAM_Type::CC2ICVSZR
 
uint8_t   CAAM_Type::RESERVED_17 [224]
 
__IO uint32_t   CAAM_Type::CC2CTXR [18]
 
uint8_t   CAAM_Type::RESERVED_18 [184]
 
__IO uint32_t   CAAM_Type::CC2KEYR [32]
 
uint8_t   CAAM_Type::RESERVED_19 [320]
 
__I uint32_t   CAAM_Type::CFIFOSTA
 
uint8_t   CAAM_Type::RESERVED_20 [12]
 
__O uint32_t   CAAM_Type::CNFIFO
 
__O uint32_t   CAAM_Type::CNFIFO_2
 
union {
   __O uint32_t   CAAM_Type::CNFIFO
 
   __O uint32_t   CAAM_Type::CNFIFO_2
 
} 
 
uint8_t   CAAM_Type::RESERVED_21 [12]
 
__O uint32_t   CAAM_Type::CIFIFO
 
uint8_t   CAAM_Type::RESERVED_22 [12]
 
__I uint64_t   CAAM_Type::COFIFO
 
uint8_t   CAAM_Type::RESERVED_23 [8]
 
__IO uint32_t   CAAM_Type::DJQCR_MS
 
__I uint32_t   CAAM_Type::DJQCR_LS
 
__I uint64_t   CAAM_Type::DDAR
 
__I uint32_t   CAAM_Type::DOPSTA_MS
 
__I uint32_t   CAAM_Type::DOPSTA_LS
 
uint8_t   CAAM_Type::RESERVED_24 [8]
 
__I uint32_t   CAAM_Type::DPDIDSR
 
__I uint32_t   CAAM_Type::DODIDSR
 
uint8_t   CAAM_Type::RESERVED_25 [24]
 
__IO uint32_t   CAAM_Type::DMTH_MS
 
__IO uint32_t   CAAM_Type::DMTH_LS
 
struct {
   __IO uint32_t   CAAM_Type::DMTH_MS
 
   __IO uint32_t   CAAM_Type::DMTH_LS
 
}   CAAM_Type::DDMTHB [4]
 
uint8_t   CAAM_Type::RESERVED_26 [32]
 
__IO uint32_t   CAAM_Type::DGTR_0
 
__IO uint32_t   CAAM_Type::DGTR_1
 
__IO uint32_t   CAAM_Type::DGTR_2
 
__IO uint32_t   CAAM_Type::DGTR_3
 
struct {
   __IO uint32_t   CAAM_Type::DGTR_0
 
   __IO uint32_t   CAAM_Type::DGTR_1
 
   __IO uint32_t   CAAM_Type::DGTR_2
 
   __IO uint32_t   CAAM_Type::DGTR_3
 
}   CAAM_Type::DDGTR [1]
 
uint8_t   CAAM_Type::RESERVED_27 [112]
 
__IO uint32_t   CAAM_Type::DSTR_0
 
__IO uint32_t   CAAM_Type::DSTR_1
 
__IO uint32_t   CAAM_Type::DSTR_2
 
__IO uint32_t   CAAM_Type::DSTR_3
 
struct {
   __IO uint32_t   CAAM_Type::DSTR_0
 
   __IO uint32_t   CAAM_Type::DSTR_1
 
   __IO uint32_t   CAAM_Type::DSTR_2
 
   __IO uint32_t   CAAM_Type::DSTR_3
 
}   CAAM_Type::DDSTR [1]
 
uint8_t   CAAM_Type::RESERVED_28 [240]
 
__IO uint32_t   CAAM_Type::DDESB [64]
 
uint8_t   CAAM_Type::RESERVED_29 [768]
 
__I uint32_t   CAAM_Type::DDJR
 
__I uint32_t   CAAM_Type::DDDR
 
__I uint64_t   CAAM_Type::DDJP
 
__I uint64_t   CAAM_Type::DSDP
 
__I uint32_t   CAAM_Type::DDDR_MS
 
__I uint32_t   CAAM_Type::DDDR_LS
 
__IO uint32_t   CAAM_Type::SOL
 
__IO uint32_t   CAAM_Type::VSOL
 
__IO uint32_t   CAAM_Type::SIL
 
__IO uint32_t   CAAM_Type::VSIL
 
__IO uint32_t   CAAM_Type::DPOVRD
 
__IO uint32_t   CAAM_Type::UVSOL
 
__IO uint32_t   CAAM_Type::UVSIL
 
struct {
   uint8_t   RESERVED_0 [4]
 
   union {
      __IO uint32_t   CAAM_Type::CC1MR
 
      __IO uint32_t   CAAM_Type::CC1MR_PK
 
      __IO uint32_t   CAAM_Type::CC1MR_RNG
 
   } 
 
   uint8_t   RESERVED_1 [4]
 
   __IO uint32_t   CAAM_Type::CC1KSR
 
   __IO uint64_t   CAAM_Type::CC1DSR
 
   uint8_t   RESERVED_2 [4]
 
   __IO uint32_t   CAAM_Type::CC1ICVSR
 
   uint8_t   RESERVED_3 [20]
 
   __O uint32_t   CAAM_Type::CCCTRL
 
   uint8_t   RESERVED_4 [4]
 
   __IO uint32_t   CAAM_Type::CICTL
 
   uint8_t   RESERVED_5 [4]
 
   __O uint32_t   CAAM_Type::CCWR
 
   __I uint32_t   CAAM_Type::CCSTA_MS
 
   __I uint32_t   CAAM_Type::CCSTA_LS
 
   uint8_t   RESERVED_6 [12]
 
   __IO uint32_t   CAAM_Type::CC1AADSZR
 
   uint8_t   RESERVED_7 [4]
 
   __IO uint32_t   CAAM_Type::CC1IVSZR
 
   uint8_t   RESERVED_8 [28]
 
   __IO uint32_t   CAAM_Type::CPKASZR
 
   uint8_t   RESERVED_9 [4]
 
   __IO uint32_t   CAAM_Type::CPKBSZR
 
   uint8_t   RESERVED_10 [4]
 
   __IO uint32_t   CAAM_Type::CPKNSZR
 
   uint8_t   RESERVED_11 [4]
 
   __IO uint32_t   CAAM_Type::CPKESZR
 
   uint8_t   RESERVED_12 [96]
 
   __IO uint32_t   CAAM_Type::CC1CTXR [16]
 
   uint8_t   RESERVED_13 [192]
 
   __IO uint32_t   CAAM_Type::CC1KR [8]
 
   uint8_t   RESERVED_14 [484]
 
   __IO uint32_t   CAAM_Type::CC2MR
 
   uint8_t   RESERVED_15 [4]
 
   __IO uint32_t   CAAM_Type::CC2KSR
 
   __IO uint64_t   CAAM_Type::CC2DSR
 
   uint8_t   RESERVED_16 [4]
 
   __IO uint32_t   CAAM_Type::CC2ICVSZR
 
   uint8_t   RESERVED_17 [224]
 
   __IO uint32_t   CAAM_Type::CC2CTXR [18]
 
   uint8_t   RESERVED_18 [184]
 
   __IO uint32_t   CAAM_Type::CC2KEYR [32]
 
   uint8_t   RESERVED_19 [320]
 
   __I uint32_t   CAAM_Type::CFIFOSTA
 
   uint8_t   RESERVED_20 [12]
 
   union {
      __O uint32_t   CAAM_Type::CNFIFO
 
      __O uint32_t   CAAM_Type::CNFIFO_2
 
   } 
 
   uint8_t   RESERVED_21 [12]
 
   __O uint32_t   CAAM_Type::CIFIFO
 
   uint8_t   RESERVED_22 [12]
 
   __I uint64_t   CAAM_Type::COFIFO
 
   uint8_t   RESERVED_23 [8]
 
   __IO uint32_t   CAAM_Type::DJQCR_MS
 
   __I uint32_t   CAAM_Type::DJQCR_LS
 
   __I uint64_t   CAAM_Type::DDAR
 
   __I uint32_t   CAAM_Type::DOPSTA_MS
 
   __I uint32_t   CAAM_Type::DOPSTA_LS
 
   uint8_t   RESERVED_24 [8]
 
   __I uint32_t   CAAM_Type::DPDIDSR
 
   __I uint32_t   CAAM_Type::DODIDSR
 
   uint8_t   RESERVED_25 [24]
 
   struct {
      __IO uint32_t   CAAM_Type::DMTH_MS
 
      __IO uint32_t   CAAM_Type::DMTH_LS
 
   }   DDMTHB [4]
 
   uint8_t   RESERVED_26 [32]
 
   struct {
      __IO uint32_t   CAAM_Type::DGTR_0
 
      __IO uint32_t   CAAM_Type::DGTR_1
 
      __IO uint32_t   CAAM_Type::DGTR_2
 
      __IO uint32_t   CAAM_Type::DGTR_3
 
   }   DDGTR [1]
 
   uint8_t   RESERVED_27 [112]
 
   struct {
      __IO uint32_t   CAAM_Type::DSTR_0
 
      __IO uint32_t   CAAM_Type::DSTR_1
 
      __IO uint32_t   CAAM_Type::DSTR_2
 
      __IO uint32_t   CAAM_Type::DSTR_3
 
   }   DDSTR [1]
 
   uint8_t   RESERVED_28 [240]
 
   __IO uint32_t   CAAM_Type::DDESB [64]
 
   uint8_t   RESERVED_29 [768]
 
   __I uint32_t   CAAM_Type::DDJR
 
   __I uint32_t   CAAM_Type::DDDR
 
   __I uint64_t   CAAM_Type::DDJP
 
   __I uint64_t   CAAM_Type::DSDP
 
   __I uint32_t   CAAM_Type::DDDR_MS
 
   __I uint32_t   CAAM_Type::DDDR_LS
 
   __IO uint32_t   CAAM_Type::SOL
 
   __IO uint32_t   CAAM_Type::VSOL
 
   __IO uint32_t   CAAM_Type::SIL
 
   __IO uint32_t   CAAM_Type::VSIL
 
   __IO uint32_t   CAAM_Type::DPOVRD
 
   __IO uint32_t   CAAM_Type::UVSOL
 
   __IO uint32_t   CAAM_Type::UVSIL
 
} CAAM_Type::DC [1]
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [2]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [2]
 
}   CAN_Type::MB_8B [64]
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [4]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [4]
 
}   CAN_Type::MB_16B_L [21]
 
uint8_t   CAN_Type::RESERVED_0 [8]
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [4]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [4]
 
}   CAN_Type::MB_16B_H [21]
 
struct {
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [4]
 
   }   MB_16B_L [21]
 
   uint8_t   RESERVED_0 [8]
 
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [4]
 
   }   MB_16B_H [21]
 
}   CAN_Type::MB_16B
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [8]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [8]
 
}   CAN_Type::MB_32B_L [12]
 
uint8_t   CAN_Type::RESERVED_0 [32]
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [8]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [8]
 
}   CAN_Type::MB_32B_H [12]
 
struct {
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [8]
 
   }   MB_32B_L [12]
 
   uint8_t   RESERVED_0 [32]
 
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [8]
 
   }   MB_32B_H [12]
 
}   CAN_Type::MB_32B
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [16]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [16]
 
}   CAN_Type::MB_64B_L [7]
 
uint8_t   CAN_Type::RESERVED_0 [8]
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD [16]
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD [16]
 
}   CAN_Type::MB_64B_H [7]
 
struct {
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [16]
 
   }   MB_64B_L [7]
 
   uint8_t   RESERVED_0 [8]
 
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [16]
 
   }   MB_64B_H [7]
 
}   CAN_Type::MB_64B
 
__IO uint32_t   CAN_Type::CS
 
__IO uint32_t   CAN_Type::ID
 
__IO uint32_t   CAN_Type::WORD0
 
__IO uint32_t   CAN_Type::WORD1
 
struct {
   __IO uint32_t   CAN_Type::CS
 
   __IO uint32_t   CAN_Type::ID
 
   __IO uint32_t   CAN_Type::WORD0
 
   __IO uint32_t   CAN_Type::WORD1
 
}   CAN_Type::MB [64]
 
union {
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD [2]
 
   }   MB_8B [64]
 
   struct {
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [4]
 
      }   MB_16B_L [21]
 
      uint8_t   RESERVED_0 [8]
 
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [4]
 
      }   MB_16B_H [21]
 
   }   MB_16B
 
   struct {
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [8]
 
      }   MB_32B_L [12]
 
      uint8_t   RESERVED_0 [32]
 
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [8]
 
      }   MB_32B_H [12]
 
   }   MB_32B
 
   struct {
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [16]
 
      }   MB_64B_L [7]
 
      uint8_t   RESERVED_0 [8]
 
      struct {
         __IO uint32_t   CAN_Type::CS
 
         __IO uint32_t   CAN_Type::ID
 
         __IO uint32_t   CAN_Type::WORD [16]
 
      }   MB_64B_H [7]
 
   }   MB_64B
 
   struct {
      __IO uint32_t   CAN_Type::CS
 
      __IO uint32_t   CAN_Type::ID
 
      __IO uint32_t   CAN_Type::WORD0
 
      __IO uint32_t   CAN_Type::WORD1
 
   }   MB [64]
 
}; 
 
__IO uint32_t   CCM_Type::CONTROL
 
__IO uint32_t   CCM_Type::CONTROL_SET
 
__IO uint32_t   CCM_Type::CONTROL_CLR
 
__IO uint32_t   CCM_Type::CONTROL_TOG
 
uint8_t   CCM_Type::RESERVED_0 [16]
 
__I uint32_t   CCM_Type::STATUS0
 
__I uint32_t   CCM_Type::STATUS1
 
uint8_t   CCM_Type::RESERVED_1 [4]
 
__I uint32_t   CCM_Type::CONFIG
 
__IO uint32_t   CCM_Type::AUTHEN
 
__IO uint32_t   CCM_Type::AUTHEN_SET
 
__IO uint32_t   CCM_Type::AUTHEN_CLR
 
__IO uint32_t   CCM_Type::AUTHEN_TOG
 
__IO uint32_t   CCM_Type::SETPOINT [16]
 
struct {
   __IO uint32_t   CCM_Type::CONTROL
 
   __IO uint32_t   CCM_Type::CONTROL_SET
 
   __IO uint32_t   CCM_Type::CONTROL_CLR
 
   __IO uint32_t   CCM_Type::CONTROL_TOG
 
   uint8_t   RESERVED_0 [16]
 
   __I uint32_t   CCM_Type::STATUS0
 
   __I uint32_t   CCM_Type::STATUS1
 
   uint8_t   RESERVED_1 [4]
 
   __I uint32_t   CCM_Type::CONFIG
 
   __IO uint32_t   CCM_Type::AUTHEN
 
   __IO uint32_t   CCM_Type::AUTHEN_SET
 
   __IO uint32_t   CCM_Type::AUTHEN_CLR
 
   __IO uint32_t   CCM_Type::AUTHEN_TOG
 
   __IO uint32_t   CCM_Type::SETPOINT [16]
 
} CCM_Type::CLOCK_ROOT [79]
 
__IO uint32_t   CCM_Type::CONTROL
 
__IO uint32_t   CCM_Type::CONTROL_SET
 
__IO uint32_t   CCM_Type::CONTROL_CLR
 
__IO uint32_t   CCM_Type::CONTROL_TOG
 
uint8_t   CCM_Type::RESERVED_0 [16]
 
__IO uint32_t   CCM_Type::STATUS0
 
__I uint32_t   CCM_Type::STATUS1
 
uint8_t   CCM_Type::RESERVED_1 [4]
 
__I uint32_t   CCM_Type::CONFIG
 
__IO uint32_t   CCM_Type::AUTHEN
 
__IO uint32_t   CCM_Type::AUTHEN_SET
 
__IO uint32_t   CCM_Type::AUTHEN_CLR
 
__IO uint32_t   CCM_Type::AUTHEN_TOG
 
__IO uint32_t   CCM_Type::SETPOINT [16]
 
struct {
   __IO uint32_t   CCM_Type::CONTROL
 
   __IO uint32_t   CCM_Type::CONTROL_SET
 
   __IO uint32_t   CCM_Type::CONTROL_CLR
 
   __IO uint32_t   CCM_Type::CONTROL_TOG
 
   uint8_t   RESERVED_0 [16]
 
   __IO uint32_t   CCM_Type::STATUS0
 
   __I uint32_t   CCM_Type::STATUS1
 
   uint8_t   RESERVED_1 [4]
 
   __I uint32_t   CCM_Type::CONFIG
 
   __IO uint32_t   CCM_Type::AUTHEN
 
   __IO uint32_t   CCM_Type::AUTHEN_SET
 
   __IO uint32_t   CCM_Type::AUTHEN_CLR
 
   __IO uint32_t   CCM_Type::AUTHEN_TOG
 
   __IO uint32_t   CCM_Type::SETPOINT [16]
 
} CCM_Type::CLOCK_GROUP [2]
 
__IO uint32_t   CCM_Type::GPR_SHARED
 
__IO uint32_t   CCM_Type::SET
 
__IO uint32_t   CCM_Type::CLR
 
__IO uint32_t   CCM_Type::TOG
 
__IO uint32_t   CCM_Type::AUTHEN
 
__IO uint32_t   CCM_Type::AUTHEN_SET
 
__IO uint32_t   CCM_Type::AUTHEN_CLR
 
__IO uint32_t   CCM_Type::AUTHEN_TOG
 
struct {
   __IO uint32_t   CCM_Type::GPR_SHARED
 
   __IO uint32_t   CCM_Type::SET
 
   __IO uint32_t   CCM_Type::CLR
 
   __IO uint32_t   CCM_Type::TOG
 
   __IO uint32_t   CCM_Type::AUTHEN
 
   __IO uint32_t   CCM_Type::AUTHEN_SET
 
   __IO uint32_t   CCM_Type::AUTHEN_CLR
 
   __IO uint32_t   CCM_Type::AUTHEN_TOG
 
} CCM_Type::GPR_SHARED [8]
 
__IO uint32_t   CCM_Type::DIRECT
 
__IO uint32_t   CCM_Type::DOMAINr
 
__IO uint32_t   CCM_Type::SETPOINT
 
uint8_t   CCM_Type::RESERVED_0 [4]
 
__I uint32_t   CCM_Type::STATUS0
 
__I uint32_t   CCM_Type::STATUS1
 
__I uint32_t   CCM_Type::CONFIG
 
__IO uint32_t   CCM_Type::AUTHEN
 
struct {
   __IO uint32_t   CCM_Type::DIRECT
 
   __IO uint32_t   CCM_Type::DOMAINr
 
   __IO uint32_t   CCM_Type::SETPOINT
 
   uint8_t   RESERVED_0 [4]
 
   __I uint32_t   CCM_Type::STATUS0
 
   __I uint32_t   CCM_Type::STATUS1
 
   __I uint32_t   CCM_Type::CONFIG
 
   __IO uint32_t   CCM_Type::AUTHEN
 
} CCM_Type::OSCPLL [29]
 
__IO uint32_t   CCM_Type::DIRECT
 
__IO uint32_t   CCM_Type::DOMAINr
 
__IO uint32_t   CCM_Type::SETPOINT
 
uint8_t   CCM_Type::RESERVED_0 [4]
 
__I uint32_t   CCM_Type::STATUS0
 
__I uint32_t   CCM_Type::STATUS1
 
__I uint32_t   CCM_Type::CONFIG
 
__IO uint32_t   CCM_Type::AUTHEN
 
struct {
   __IO uint32_t   CCM_Type::DIRECT
 
   __IO uint32_t   CCM_Type::DOMAINr
 
   __IO uint32_t   CCM_Type::SETPOINT
 
   uint8_t   RESERVED_0 [4]
 
   __I uint32_t   CCM_Type::STATUS0
 
   __I uint32_t   CCM_Type::STATUS1
 
   __I uint32_t   CCM_Type::CONFIG
 
   __IO uint32_t   CCM_Type::AUTHEN
 
} CCM_Type::LPCG [138]
 
__IO uint32_t   CCM_OBS_Type::CONTROL
 
__IO uint32_t   CCM_OBS_Type::CONTROL_SET
 
__IO uint32_t   CCM_OBS_Type::CONTROL_CLR
 
__IO uint32_t   CCM_OBS_Type::CONTROL_TOG
 
uint8_t   CCM_OBS_Type::RESERVED_0 [16]
 
__I uint32_t   CCM_OBS_Type::STATUS0
 
uint8_t   CCM_OBS_Type::RESERVED_1 [12]
 
__IO uint32_t   CCM_OBS_Type::AUTHEN
 
__IO uint32_t   CCM_OBS_Type::AUTHEN_SET
 
__IO uint32_t   CCM_OBS_Type::AUTHEN_CLR
 
__IO uint32_t   CCM_OBS_Type::AUTHEN_TOG
 
__I uint32_t   CCM_OBS_Type::FREQUENCY_CURRENT
 
__I uint32_t   CCM_OBS_Type::FREQUENCY_MIN
 
__I uint32_t   CCM_OBS_Type::FREQUENCY_MAX
 
uint8_t   CCM_OBS_Type::RESERVED_2 [52]
 
struct {
   __IO uint32_t   CCM_OBS_Type::CONTROL
 
   __IO uint32_t   CCM_OBS_Type::CONTROL_SET
 
   __IO uint32_t   CCM_OBS_Type::CONTROL_CLR
 
   __IO uint32_t   CCM_OBS_Type::CONTROL_TOG
 
   uint8_t   RESERVED_0 [16]
 
   __I uint32_t   CCM_OBS_Type::STATUS0
 
   uint8_t   RESERVED_1 [12]
 
   __IO uint32_t   CCM_OBS_Type::AUTHEN
 
   __IO uint32_t   CCM_OBS_Type::AUTHEN_SET
 
   __IO uint32_t   CCM_OBS_Type::AUTHEN_CLR
 
   __IO uint32_t   CCM_OBS_Type::AUTHEN_TOG
 
   __I uint32_t   CCM_OBS_Type::FREQUENCY_CURRENT
 
   __I uint32_t   CCM_OBS_Type::FREQUENCY_MIN
 
   __I uint32_t   CCM_OBS_Type::FREQUENCY_MAX
 
   uint8_t   RESERVED_2 [52]
 
} CCM_OBS_Type::OBSERVE [6]
 
__IO uint32_t   DCIC_Type::DCICRC
 
__IO uint32_t   DCIC_Type::DCICRS
 
__IO uint32_t   DCIC_Type::DCICRRS
 
__I uint32_t   DCIC_Type::DCICRCS
 
struct {
   __IO uint32_t   DCIC_Type::DCICRC
 
   __IO uint32_t   DCIC_Type::DCICRS
 
   __IO uint32_t   DCIC_Type::DCICRRS
 
   __I uint32_t   DCIC_Type::DCICRCS
 
} DCIC_Type::REGION [16]
 
__IO uint32_t   DMA_Type::SADDR
 
__IO uint16_t   DMA_Type::SOFF
 
__IO uint16_t   DMA_Type::ATTR
 
__IO uint32_t   DMA_Type::NBYTES_MLNO
 
__IO uint32_t   DMA_Type::NBYTES_MLOFFNO
 
__IO uint32_t   DMA_Type::NBYTES_MLOFFYES
 
union {
   __IO uint32_t   DMA_Type::NBYTES_MLNO
 
   __IO uint32_t   DMA_Type::NBYTES_MLOFFNO
 
   __IO uint32_t   DMA_Type::NBYTES_MLOFFYES
 
} 
 
__IO int32_t   DMA_Type::SLAST
 
__IO uint32_t   DMA_Type::DADDR
 
__IO uint16_t   DMA_Type::DOFF
 
__IO uint16_t   DMA_Type::CITER_ELINKNO
 
__IO uint16_t   DMA_Type::CITER_ELINKYES
 
union {
   __IO uint16_t   DMA_Type::CITER_ELINKNO
 
   __IO uint16_t   DMA_Type::CITER_ELINKYES
 
} 
 
__IO int32_t   DMA_Type::DLAST_SGA
 
__IO uint16_t   DMA_Type::CSR
 
__IO uint16_t   DMA_Type::BITER_ELINKNO
 
__IO uint16_t   DMA_Type::BITER_ELINKYES
 
union {
   __IO uint16_t   DMA_Type::BITER_ELINKNO
 
   __IO uint16_t   DMA_Type::BITER_ELINKYES
 
} 
 
struct {
   __IO uint32_t   DMA_Type::SADDR
 
   __IO uint16_t   DMA_Type::SOFF
 
   __IO uint16_t   DMA_Type::ATTR
 
   union {
      __IO uint32_t   DMA_Type::NBYTES_MLNO
 
      __IO uint32_t   DMA_Type::NBYTES_MLOFFNO
 
      __IO uint32_t   DMA_Type::NBYTES_MLOFFYES
 
   } 
 
   __IO int32_t   DMA_Type::SLAST
 
   __IO uint32_t   DMA_Type::DADDR
 
   __IO uint16_t   DMA_Type::DOFF
 
   union {
      __IO uint16_t   DMA_Type::CITER_ELINKNO
 
      __IO uint16_t   DMA_Type::CITER_ELINKYES
 
   } 
 
   __IO int32_t   DMA_Type::DLAST_SGA
 
   __IO uint16_t   DMA_Type::CSR
 
   union {
      __IO uint16_t   DMA_Type::BITER_ELINKNO
 
      __IO uint16_t   DMA_Type::BITER_ELINKYES
 
   } 
 
} DMA_Type::TCD [32]
 
__IO uint32_t   ENET_Type::TCSR
 
__IO uint32_t   ENET_Type::TCCR
 
struct {
   __IO uint32_t   ENET_Type::TCSR
 
   __IO uint32_t   ENET_Type::TCCR
 
} ENET_Type::CHANNEL [4]
 
__IO uint32_t   ETHERNET_PLL_Type::RW
 
__IO uint32_t   ETHERNET_PLL_Type::SET
 
__IO uint32_t   ETHERNET_PLL_Type::CLR
 
__IO uint32_t   ETHERNET_PLL_Type::TOG
 
struct {
   __IO uint32_t   ETHERNET_PLL_Type::RW
 
   __IO uint32_t   ETHERNET_PLL_Type::SET
 
   __IO uint32_t   ETHERNET_PLL_Type::CLR
 
   __IO uint32_t   ETHERNET_PLL_Type::TOG
 
} ETHERNET_PLL_Type::CTRL0
 
__IO uint32_t   ETHERNET_PLL_Type::RW
 
__IO uint32_t   ETHERNET_PLL_Type::SET
 
__IO uint32_t   ETHERNET_PLL_Type::CLR
 
__IO uint32_t   ETHERNET_PLL_Type::TOG
 
struct {
   __IO uint32_t   ETHERNET_PLL_Type::RW
 
   __IO uint32_t   ETHERNET_PLL_Type::SET
 
   __IO uint32_t   ETHERNET_PLL_Type::CLR
 
   __IO uint32_t   ETHERNET_PLL_Type::TOG
 
} ETHERNET_PLL_Type::SPREAD_SPECTRUM
 
__IO uint32_t   ETHERNET_PLL_Type::RW
 
__IO uint32_t   ETHERNET_PLL_Type::SET
 
__IO uint32_t   ETHERNET_PLL_Type::CLR
 
__IO uint32_t   ETHERNET_PLL_Type::TOG
 
struct {
   __IO uint32_t   ETHERNET_PLL_Type::RW
 
   __IO uint32_t   ETHERNET_PLL_Type::SET
 
   __IO uint32_t   ETHERNET_PLL_Type::CLR
 
   __IO uint32_t   ETHERNET_PLL_Type::TOG
 
} ETHERNET_PLL_Type::NUMERATOR
 
__IO uint32_t   ETHERNET_PLL_Type::RW
 
__IO uint32_t   ETHERNET_PLL_Type::SET
 
__IO uint32_t   ETHERNET_PLL_Type::CLR
 
__IO uint32_t   ETHERNET_PLL_Type::TOG
 
struct {
   __IO uint32_t   ETHERNET_PLL_Type::RW
 
   __IO uint32_t   ETHERNET_PLL_Type::SET
 
   __IO uint32_t   ETHERNET_PLL_Type::CLR
 
   __IO uint32_t   ETHERNET_PLL_Type::TOG
 
} ETHERNET_PLL_Type::DENOMINATOR
 
__IO uint32_t   IEE_Type::REGATTR
 
uint8_t   IEE_Type::RESERVED_0 [4]
 
__IO uint32_t   IEE_Type::REGPO
 
uint8_t   IEE_Type::RESERVED_1 [52]
 
__O uint32_t   IEE_Type::REGKEY1 [8]
 
uint8_t   IEE_Type::RESERVED_2 [32]
 
__O uint32_t   IEE_Type::REGKEY2 [8]
 
uint8_t   IEE_Type::RESERVED_3 [96]
 
struct {
   __IO uint32_t   IEE_Type::REGATTR
 
   uint8_t   RESERVED_0 [4]
 
   __IO uint32_t   IEE_Type::REGPO
 
   uint8_t   RESERVED_1 [52]
 
   __O uint32_t   IEE_Type::REGKEY1 [8]
 
   uint8_t   RESERVED_2 [32]
 
   __O uint32_t   IEE_Type::REGKEY2 [8]
 
   uint8_t   RESERVED_3 [96]
 
} IEE_Type::REGX [8]
 
__IO uint32_t   IPS_DOMAIN_Type::SLOT_CTRL
 
uint8_t   IPS_DOMAIN_Type::RESERVED_0 [12]
 
struct {
   __IO uint32_t   IPS_DOMAIN_Type::SLOT_CTRL
 
   uint8_t   RESERVED_0 [12]
 
} IPS_DOMAIN_Type::SLOT_CTRL [38]
 
__IO uint32_t   LCDIF_Type::PIGEON_0
 
uint8_t   LCDIF_Type::RESERVED_0 [12]
 
__IO uint32_t   LCDIF_Type::PIGEON_1
 
uint8_t   LCDIF_Type::RESERVED_1 [12]
 
__IO uint32_t   LCDIF_Type::PIGEON_2
 
uint8_t   LCDIF_Type::RESERVED_2 [28]
 
struct {
   __IO uint32_t   LCDIF_Type::PIGEON_0
 
   uint8_t   RESERVED_0 [12]
 
   __IO uint32_t   LCDIF_Type::PIGEON_1
 
   uint8_t   RESERVED_1 [12]
 
   __IO uint32_t   LCDIF_Type::PIGEON_2
 
   uint8_t   RESERVED_2 [28]
 
} LCDIF_Type::PIGEON [12]
 
__IO uint32_t   LCDIFV2_Type::INT_STATUS
 
__IO uint32_t   LCDIFV2_Type::INT_ENABLE
 
uint8_t   LCDIFV2_Type::RESERVED_0 [8]
 
struct {
   __IO uint32_t   LCDIFV2_Type::INT_STATUS
 
   __IO uint32_t   LCDIFV2_Type::INT_ENABLE
 
   uint8_t   RESERVED_0 [8]
 
} LCDIFV2_Type::INT [2]
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL1
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL2
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL3
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL4
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL5
 
__IO uint32_t   LCDIFV2_Type::CTRLDESCL6
 
__IO uint32_t   LCDIFV2_Type::CSC_COEF0
 
__IO uint32_t   LCDIFV2_Type::CSC_COEF1
 
__IO uint32_t   LCDIFV2_Type::CSC_COEF2
 
uint8_t   LCDIFV2_Type::RESERVED_0 [28]
 
struct {
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL1
 
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL2
 
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL3
 
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL4
 
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL5
 
   __IO uint32_t   LCDIFV2_Type::CTRLDESCL6
 
   __IO uint32_t   LCDIFV2_Type::CSC_COEF0
 
   __IO uint32_t   LCDIFV2_Type::CSC_COEF1
 
   __IO uint32_t   LCDIFV2_Type::CSC_COEF2
 
   uint8_t   RESERVED_0 [28]
 
} LCDIFV2_Type::LAYER [8]
 
__IO uint32_t   OCOTP_Type::READ_FUSE_DATA
 
uint8_t   OCOTP_Type::RESERVED_0 [12]
 
struct {
   __IO uint32_t   OCOTP_Type::READ_FUSE_DATA
 
   uint8_t   RESERVED_0 [12]
 
} OCOTP_Type::READ_FUSE_DATAS [4]
 
__I uint32_t   OCOTP_Type::FUSE
 
uint8_t   OCOTP_Type::RESERVED_0 [12]
 
struct {
   __I uint32_t   OCOTP_Type::FUSE
 
   uint8_t   RESERVED_0 [12]
 
} OCOTP_Type::FUSEN [144]
 
__IO uint32_t   OSC_RC_400M_Type::RW
 
__IO uint32_t   OSC_RC_400M_Type::SET
 
__IO uint32_t   OSC_RC_400M_Type::CLR
 
__IO uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __IO uint32_t   OSC_RC_400M_Type::RW
 
   __IO uint32_t   OSC_RC_400M_Type::SET
 
   __IO uint32_t   OSC_RC_400M_Type::CLR
 
   __IO uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::CTRL0
 
__IO uint32_t   OSC_RC_400M_Type::RW
 
__IO uint32_t   OSC_RC_400M_Type::SET
 
__IO uint32_t   OSC_RC_400M_Type::CLR
 
__IO uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __IO uint32_t   OSC_RC_400M_Type::RW
 
   __IO uint32_t   OSC_RC_400M_Type::SET
 
   __IO uint32_t   OSC_RC_400M_Type::CLR
 
   __IO uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::CTRL1
 
__IO uint32_t   OSC_RC_400M_Type::RW
 
__IO uint32_t   OSC_RC_400M_Type::SET
 
__IO uint32_t   OSC_RC_400M_Type::CLR
 
__IO uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __IO uint32_t   OSC_RC_400M_Type::RW
 
   __IO uint32_t   OSC_RC_400M_Type::SET
 
   __IO uint32_t   OSC_RC_400M_Type::CLR
 
   __IO uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::CTRL2
 
__IO uint32_t   OSC_RC_400M_Type::RW
 
__IO uint32_t   OSC_RC_400M_Type::SET
 
__IO uint32_t   OSC_RC_400M_Type::CLR
 
__IO uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __IO uint32_t   OSC_RC_400M_Type::RW
 
   __IO uint32_t   OSC_RC_400M_Type::SET
 
   __IO uint32_t   OSC_RC_400M_Type::CLR
 
   __IO uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::CTRL3
 
__I uint32_t   OSC_RC_400M_Type::RW
 
__I uint32_t   OSC_RC_400M_Type::SET
 
__I uint32_t   OSC_RC_400M_Type::CLR
 
__I uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __I uint32_t   OSC_RC_400M_Type::RW
 
   __I uint32_t   OSC_RC_400M_Type::SET
 
   __I uint32_t   OSC_RC_400M_Type::CLR
 
   __I uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::STAT0
 
__I uint32_t   OSC_RC_400M_Type::RW
 
__I uint32_t   OSC_RC_400M_Type::SET
 
__I uint32_t   OSC_RC_400M_Type::CLR
 
__I uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __I uint32_t   OSC_RC_400M_Type::RW
 
   __I uint32_t   OSC_RC_400M_Type::SET
 
   __I uint32_t   OSC_RC_400M_Type::CLR
 
   __I uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::STAT1
 
__I uint32_t   OSC_RC_400M_Type::RW
 
__I uint32_t   OSC_RC_400M_Type::SET
 
__I uint32_t   OSC_RC_400M_Type::CLR
 
__I uint32_t   OSC_RC_400M_Type::TOG
 
struct {
   __I uint32_t   OSC_RC_400M_Type::RW
 
   __I uint32_t   OSC_RC_400M_Type::SET
 
   __I uint32_t   OSC_RC_400M_Type::CLR
 
   __I uint32_t   OSC_RC_400M_Type::TOG
 
} OSC_RC_400M_Type::STAT2
 
__IO uint32_t   OTFAD_Type::KEY [4]
 
__IO uint32_t   OTFAD_Type::CTR [2]
 
__IO uint32_t   OTFAD_Type::RGD_W0
 
__IO uint32_t   OTFAD_Type::RGD_W1
 
uint8_t   OTFAD_Type::RESERVED_0 [32]
 
struct {
   __IO uint32_t   OTFAD_Type::KEY [4]
 
   __IO uint32_t   OTFAD_Type::CTR [2]
 
   __IO uint32_t   OTFAD_Type::RGD_W0
 
   __IO uint32_t   OTFAD_Type::RGD_W1
 
   uint8_t   RESERVED_0 [32]
 
} OTFAD_Type::CTX [4]
 
__IO uint32_t   PHY_LDO_Type::RW
 
__IO uint32_t   PHY_LDO_Type::SET
 
__IO uint32_t   PHY_LDO_Type::CLR
 
__IO uint32_t   PHY_LDO_Type::TOG
 
struct {
   __IO uint32_t   PHY_LDO_Type::RW
 
   __IO uint32_t   PHY_LDO_Type::SET
 
   __IO uint32_t   PHY_LDO_Type::CLR
 
   __IO uint32_t   PHY_LDO_Type::TOG
 
} PHY_LDO_Type::CTRL0
 
__I uint32_t   PHY_LDO_Type::RW
 
__I uint32_t   PHY_LDO_Type::SET
 
__I uint32_t   PHY_LDO_Type::CLR
 
__I uint32_t   PHY_LDO_Type::TOG
 
struct {
   __I uint32_t   PHY_LDO_Type::RW
 
   __I uint32_t   PHY_LDO_Type::SET
 
   __I uint32_t   PHY_LDO_Type::CLR
 
   __I uint32_t   PHY_LDO_Type::TOG
 
} PHY_LDO_Type::STAT0
 
__IO uint32_t   PIT_Type::LDVAL
 
__I uint32_t   PIT_Type::CVAL
 
__IO uint32_t   PIT_Type::TCTRL
 
__IO uint32_t   PIT_Type::TFLG
 
struct {
   __IO uint32_t   PIT_Type::LDVAL
 
   __I uint32_t   PIT_Type::CVAL
 
   __IO uint32_t   PIT_Type::TCTRL
 
   __IO uint32_t   PIT_Type::TFLG
 
} PIT_Type::CHANNEL [4]
 
__I uint16_t   PWM_Type::CNT
 
__IO uint16_t   PWM_Type::INIT
 
__IO uint16_t   PWM_Type::CTRL2
 
__IO uint16_t   PWM_Type::CTRL
 
uint8_t   PWM_Type::RESERVED_0 [2]
 
__IO uint16_t   PWM_Type::VAL0
 
__IO uint16_t   PWM_Type::FRACVAL1
 
__IO uint16_t   PWM_Type::VAL1
 
__IO uint16_t   PWM_Type::FRACVAL2
 
__IO uint16_t   PWM_Type::VAL2
 
__IO uint16_t   PWM_Type::FRACVAL3
 
__IO uint16_t   PWM_Type::VAL3
 
__IO uint16_t   PWM_Type::FRACVAL4
 
__IO uint16_t   PWM_Type::VAL4
 
__IO uint16_t   PWM_Type::FRACVAL5
 
__IO uint16_t   PWM_Type::VAL5
 
__IO uint16_t   PWM_Type::FRCTRL
 
__IO uint16_t   PWM_Type::OCTRL
 
__IO uint16_t   PWM_Type::STS
 
__IO uint16_t   PWM_Type::INTEN
 
__IO uint16_t   PWM_Type::DMAEN
 
__IO uint16_t   PWM_Type::TCTRL
 
__IO uint16_t   PWM_Type::DISMAP [1]
 
uint8_t   PWM_Type::RESERVED_1 [2]
 
__IO uint16_t   PWM_Type::DTCNT0
 
__IO uint16_t   PWM_Type::DTCNT1
 
__IO uint16_t   PWM_Type::CAPTCTRLA
 
__IO uint16_t   PWM_Type::CAPTCOMPA
 
__IO uint16_t   PWM_Type::CAPTCTRLB
 
__IO uint16_t   PWM_Type::CAPTCOMPB
 
__IO uint16_t   PWM_Type::CAPTCTRLX
 
__IO uint16_t   PWM_Type::CAPTCOMPX
 
__I uint16_t   PWM_Type::CVAL0
 
__I uint16_t   PWM_Type::CVAL0CYC
 
__I uint16_t   PWM_Type::CVAL1
 
__I uint16_t   PWM_Type::CVAL1CYC
 
__I uint16_t   PWM_Type::CVAL2
 
__I uint16_t   PWM_Type::CVAL2CYC
 
__I uint16_t   PWM_Type::CVAL3
 
__I uint16_t   PWM_Type::CVAL3CYC
 
__I uint16_t   PWM_Type::CVAL4
 
__I uint16_t   PWM_Type::CVAL4CYC
 
__I uint16_t   PWM_Type::CVAL5
 
__I uint16_t   PWM_Type::CVAL5CYC
 
uint8_t   PWM_Type::RESERVED_2 [8]
 
struct {
   __I uint16_t   PWM_Type::CNT
 
   __IO uint16_t   PWM_Type::INIT
 
   __IO uint16_t   PWM_Type::CTRL2
 
   __IO uint16_t   PWM_Type::CTRL
 
   uint8_t   RESERVED_0 [2]
 
   __IO uint16_t   PWM_Type::VAL0
 
   __IO uint16_t   PWM_Type::FRACVAL1
 
   __IO uint16_t   PWM_Type::VAL1
 
   __IO uint16_t   PWM_Type::FRACVAL2
 
   __IO uint16_t   PWM_Type::VAL2
 
   __IO uint16_t   PWM_Type::FRACVAL3
 
   __IO uint16_t   PWM_Type::VAL3
 
   __IO uint16_t   PWM_Type::FRACVAL4
 
   __IO uint16_t   PWM_Type::VAL4
 
   __IO uint16_t   PWM_Type::FRACVAL5
 
   __IO uint16_t   PWM_Type::VAL5
 
   __IO uint16_t   PWM_Type::FRCTRL
 
   __IO uint16_t   PWM_Type::OCTRL
 
   __IO uint16_t   PWM_Type::STS
 
   __IO uint16_t   PWM_Type::INTEN
 
   __IO uint16_t   PWM_Type::DMAEN
 
   __IO uint16_t   PWM_Type::TCTRL
 
   __IO uint16_t   PWM_Type::DISMAP [1]
 
   uint8_t   RESERVED_1 [2]
 
   __IO uint16_t   PWM_Type::DTCNT0
 
   __IO uint16_t   PWM_Type::DTCNT1
 
   __IO uint16_t   PWM_Type::CAPTCTRLA
 
   __IO uint16_t   PWM_Type::CAPTCOMPA
 
   __IO uint16_t   PWM_Type::CAPTCTRLB
 
   __IO uint16_t   PWM_Type::CAPTCOMPB
 
   __IO uint16_t   PWM_Type::CAPTCTRLX
 
   __IO uint16_t   PWM_Type::CAPTCOMPX
 
   __I uint16_t   PWM_Type::CVAL0
 
   __I uint16_t   PWM_Type::CVAL0CYC
 
   __I uint16_t   PWM_Type::CVAL1
 
   __I uint16_t   PWM_Type::CVAL1CYC
 
   __I uint16_t   PWM_Type::CVAL2
 
   __I uint16_t   PWM_Type::CVAL2CYC
 
   __I uint16_t   PWM_Type::CVAL3
 
   __I uint16_t   PWM_Type::CVAL3CYC
 
   __I uint16_t   PWM_Type::CVAL4
 
   __I uint16_t   PWM_Type::CVAL4CYC
 
   __I uint16_t   PWM_Type::CVAL5
 
   __I uint16_t   PWM_Type::CVAL5CYC
 
   uint8_t   RESERVED_2 [8]
 
} PWM_Type::SM [4]
 
__IO uint32_t   RDC_Type::MRSA
 
__IO uint32_t   RDC_Type::MREA
 
__IO uint32_t   RDC_Type::MRC
 
__IO uint32_t   RDC_Type::MRVS
 
struct {
   __IO uint32_t   RDC_Type::MRSA
 
   __IO uint32_t   RDC_Type::MREA
 
   __IO uint32_t   RDC_Type::MRC
 
   __IO uint32_t   RDC_Type::MRVS
 
} RDC_Type::MR [59]
 
__IO uint16_t   RDC_SEMAPHORE_Type::RSTGT_R
 
__IO uint16_t   RDC_SEMAPHORE_Type::RSTGT_W
 
union {
   __IO uint16_t   RDC_SEMAPHORE_Type::RSTGT_R
 
   __IO uint16_t   RDC_SEMAPHORE_Type::RSTGT_W
 
}; 
 
__IO uint16_t   SEMA4_Type::CPINE
 
uint8_t   SEMA4_Type::RESERVED_0 [6]
 
struct {
   __IO uint16_t   SEMA4_Type::CPINE
 
   uint8_t   RESERVED_0 [6]
 
} SEMA4_Type::CPINE [2]
 
__I uint16_t   SEMA4_Type::CPNTF
 
uint8_t   SEMA4_Type::RESERVED_0 [6]
 
struct {
   __I uint16_t   SEMA4_Type::CPNTF
 
   uint8_t   RESERVED_0 [6]
 
} SEMA4_Type::CPNTF [2]
 
__O uint32_t   SPDIF_Type::SIC
 
__I uint32_t   SPDIF_Type::SIS
 
union {
   __O uint32_t   SPDIF_Type::SIC
 
   __I uint32_t   SPDIF_Type::SIS
 
}; 
 
__IO uint32_t   SSARC_HP_Type::SRAM0
 
__IO uint32_t   SSARC_HP_Type::SRAM1
 
__IO uint32_t   SSARC_HP_Type::SRAM2
 
uint8_t   SSARC_HP_Type::RESERVED_0 [4]
 
struct {
   __IO uint32_t   SSARC_HP_Type::SRAM0
 
   __IO uint32_t   SSARC_HP_Type::SRAM1
 
   __IO uint32_t   SSARC_HP_Type::SRAM2
 
   uint8_t   RESERVED_0 [4]
 
} SSARC_HP_Type::DESC [1024]
 
__IO uint32_t   SSARC_LP_Type::DESC_CTRL0
 
__IO uint32_t   SSARC_LP_Type::DESC_CTRL1
 
__IO uint32_t   SSARC_LP_Type::DESC_ADDR_UP
 
__IO uint32_t   SSARC_LP_Type::DESC_ADDR_DOWN
 
uint8_t   SSARC_LP_Type::RESERVED_0 [16]
 
struct {
   __IO uint32_t   SSARC_LP_Type::DESC_CTRL0
 
   __IO uint32_t   SSARC_LP_Type::DESC_CTRL1
 
   __IO uint32_t   SSARC_LP_Type::DESC_ADDR_UP
 
   __IO uint32_t   SSARC_LP_Type::DESC_ADDR_DOWN
 
   uint8_t   RESERVED_0 [16]
 
} SSARC_LP_Type::GROUPS [16]
 
__IO uint16_t   TMR_Type::COMP1
 
__IO uint16_t   TMR_Type::COMP2
 
__IO uint16_t   TMR_Type::CAPT
 
__IO uint16_t   TMR_Type::LOAD
 
__IO uint16_t   TMR_Type::HOLD
 
__IO uint16_t   TMR_Type::CNTR
 
__IO uint16_t   TMR_Type::CTRL
 
__IO uint16_t   TMR_Type::SCTRL
 
__IO uint16_t   TMR_Type::CMPLD1
 
__IO uint16_t   TMR_Type::CMPLD2
 
__IO uint16_t   TMR_Type::CSCTRL
 
__IO uint16_t   TMR_Type::FILT
 
__IO uint16_t   TMR_Type::DMA
 
uint8_t   TMR_Type::RESERVED_0 [4]
 
__IO uint16_t   TMR_Type::ENBL
 
struct {
   __IO uint16_t   TMR_Type::COMP1
 
   __IO uint16_t   TMR_Type::COMP2
 
   __IO uint16_t   TMR_Type::CAPT
 
   __IO uint16_t   TMR_Type::LOAD
 
   __IO uint16_t   TMR_Type::HOLD
 
   __IO uint16_t   TMR_Type::CNTR
 
   __IO uint16_t   TMR_Type::CTRL
 
   __IO uint16_t   TMR_Type::SCTRL
 
   __IO uint16_t   TMR_Type::CMPLD1
 
   __IO uint16_t   TMR_Type::CMPLD2
 
   __IO uint16_t   TMR_Type::CSCTRL
 
   __IO uint16_t   TMR_Type::FILT
 
   __IO uint16_t   TMR_Type::DMA
 
   uint8_t   RESERVED_0 [4]
 
   __IO uint16_t   TMR_Type::ENBL
 
} TMR_Type::CHANNEL [4]
 
__IO uint32_t   USB_Type::DEVICEADDR
 
__IO uint32_t   USB_Type::PERIODICLISTBASE
 
union {
   __IO uint32_t   USB_Type::DEVICEADDR
 
   __IO uint32_t   USB_Type::PERIODICLISTBASE
 
}; 
 
__IO uint32_t   USB_Type::ASYNCLISTADDR
 
__IO uint32_t   USB_Type::ENDPTLISTADDR
 
union {
   __IO uint32_t   USB_Type::ASYNCLISTADDR
 
   __IO uint32_t   USB_Type::ENDPTLISTADDR
 
}; 
 
__IO uint32_t   USBHSDCD_Type::TIMER2_BC11
 
__IO uint32_t   USBHSDCD_Type::TIMER2_BC12
 
union {
   __IO uint32_t   USBHSDCD_Type::TIMER2_BC11
 
   __IO uint32_t   USBHSDCD_Type::TIMER2_BC12
 
}; 
 
__IO uint32_t   VIDEO_MUX_Type::RW
 
__IO uint32_t   VIDEO_MUX_Type::SET
 
__IO uint32_t   VIDEO_MUX_Type::CLR
 
__IO uint32_t   VIDEO_MUX_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_MUX_Type::RW
 
   __IO uint32_t   VIDEO_MUX_Type::SET
 
   __IO uint32_t   VIDEO_MUX_Type::CLR
 
   __IO uint32_t   VIDEO_MUX_Type::TOG
 
} VIDEO_MUX_Type::VID_MUX_CTRL
 
__IO uint32_t   VIDEO_MUX_Type::RW
 
__IO uint32_t   VIDEO_MUX_Type::SET
 
__IO uint32_t   VIDEO_MUX_Type::CLR
 
__IO uint32_t   VIDEO_MUX_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_MUX_Type::RW
 
   __IO uint32_t   VIDEO_MUX_Type::SET
 
   __IO uint32_t   VIDEO_MUX_Type::CLR
 
   __IO uint32_t   VIDEO_MUX_Type::TOG
 
} VIDEO_MUX_Type::PLM_CTRL
 
__IO uint32_t   VIDEO_MUX_Type::RW
 
__IO uint32_t   VIDEO_MUX_Type::SET
 
__IO uint32_t   VIDEO_MUX_Type::CLR
 
__IO uint32_t   VIDEO_MUX_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_MUX_Type::RW
 
   __IO uint32_t   VIDEO_MUX_Type::SET
 
   __IO uint32_t   VIDEO_MUX_Type::CLR
 
   __IO uint32_t   VIDEO_MUX_Type::TOG
 
} VIDEO_MUX_Type::YUV420_CTRL
 
__IO uint32_t   VIDEO_MUX_Type::RW
 
__IO uint32_t   VIDEO_MUX_Type::SET
 
__IO uint32_t   VIDEO_MUX_Type::CLR
 
__IO uint32_t   VIDEO_MUX_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_MUX_Type::RW
 
   __IO uint32_t   VIDEO_MUX_Type::SET
 
   __IO uint32_t   VIDEO_MUX_Type::CLR
 
   __IO uint32_t   VIDEO_MUX_Type::TOG
 
} VIDEO_MUX_Type::CFG_DT_DISABLE
 
__IO uint32_t   VIDEO_MUX_Type::RW
 
__IO uint32_t   VIDEO_MUX_Type::SET
 
__IO uint32_t   VIDEO_MUX_Type::CLR
 
__IO uint32_t   VIDEO_MUX_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_MUX_Type::RW
 
   __IO uint32_t   VIDEO_MUX_Type::SET
 
   __IO uint32_t   VIDEO_MUX_Type::CLR
 
   __IO uint32_t   VIDEO_MUX_Type::TOG
 
} VIDEO_MUX_Type::MIPI_DSI_CTRL
 
__IO uint32_t   VIDEO_PLL_Type::RW
 
__IO uint32_t   VIDEO_PLL_Type::SET
 
__IO uint32_t   VIDEO_PLL_Type::CLR
 
__IO uint32_t   VIDEO_PLL_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_PLL_Type::RW
 
   __IO uint32_t   VIDEO_PLL_Type::SET
 
   __IO uint32_t   VIDEO_PLL_Type::CLR
 
   __IO uint32_t   VIDEO_PLL_Type::TOG
 
} VIDEO_PLL_Type::CTRL0
 
__IO uint32_t   VIDEO_PLL_Type::RW
 
__IO uint32_t   VIDEO_PLL_Type::SET
 
__IO uint32_t   VIDEO_PLL_Type::CLR
 
__IO uint32_t   VIDEO_PLL_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_PLL_Type::RW
 
   __IO uint32_t   VIDEO_PLL_Type::SET
 
   __IO uint32_t   VIDEO_PLL_Type::CLR
 
   __IO uint32_t   VIDEO_PLL_Type::TOG
 
} VIDEO_PLL_Type::SPREAD_SPECTRUM
 
__IO uint32_t   VIDEO_PLL_Type::RW
 
__IO uint32_t   VIDEO_PLL_Type::SET
 
__IO uint32_t   VIDEO_PLL_Type::CLR
 
__IO uint32_t   VIDEO_PLL_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_PLL_Type::RW
 
   __IO uint32_t   VIDEO_PLL_Type::SET
 
   __IO uint32_t   VIDEO_PLL_Type::CLR
 
   __IO uint32_t   VIDEO_PLL_Type::TOG
 
} VIDEO_PLL_Type::NUMERATOR
 
__IO uint32_t   VIDEO_PLL_Type::RW
 
__IO uint32_t   VIDEO_PLL_Type::SET
 
__IO uint32_t   VIDEO_PLL_Type::CLR
 
__IO uint32_t   VIDEO_PLL_Type::TOG
 
struct {
   __IO uint32_t   VIDEO_PLL_Type::RW
 
   __IO uint32_t   VIDEO_PLL_Type::SET
 
   __IO uint32_t   VIDEO_PLL_Type::CLR
 
   __IO uint32_t   VIDEO_PLL_Type::TOG
 
} VIDEO_PLL_Type::DENOMINATOR
 
__IO uint32_t   VMBANDGAP_Type::RW
 
__IO uint32_t   VMBANDGAP_Type::SET
 
__IO uint32_t   VMBANDGAP_Type::CLR
 
__IO uint32_t   VMBANDGAP_Type::TOG
 
struct {
   __IO uint32_t   VMBANDGAP_Type::RW
 
   __IO uint32_t   VMBANDGAP_Type::SET
 
   __IO uint32_t   VMBANDGAP_Type::CLR
 
   __IO uint32_t   VMBANDGAP_Type::TOG
 
} VMBANDGAP_Type::CTRL0
 
__I uint32_t   VMBANDGAP_Type::RW
 
__I uint32_t   VMBANDGAP_Type::SET
 
__I uint32_t   VMBANDGAP_Type::CLR
 
__I uint32_t   VMBANDGAP_Type::TOG
 
struct {
   __I uint32_t   VMBANDGAP_Type::RW
 
   __I uint32_t   VMBANDGAP_Type::SET
 
   __I uint32_t   VMBANDGAP_Type::CLR
 
   __I uint32_t   VMBANDGAP_Type::TOG
 
} VMBANDGAP_Type::STAT0
 
__IO uint32_t   XRDC2_Type::MSC_MSAC_W0
 
__IO uint32_t   XRDC2_Type::MSC_MSAC_W1
 
struct {
   __IO uint32_t   XRDC2_Type::MSC_MSAC_W0
 
   __IO uint32_t   XRDC2_Type::MSC_MSAC_W1
 
} XRDC2_Type::MSCI_MSAC_WK [128]
 
__IO uint32_t   XRDC2_Type::MDAC_MDA_W0
 
__IO uint32_t   XRDC2_Type::MDAC_MDA_W1
 
struct {
   __IO uint32_t   XRDC2_Type::MDAC_MDA_W0
 
   __IO uint32_t   XRDC2_Type::MDAC_MDA_W1
 
} XRDC2_Type::MDACI_MDAJ [32][32]
 
__IO uint32_t   XRDC2_Type::PAC_PDAC_W0
 
__IO uint32_t   XRDC2_Type::PAC_PDAC_W1
 
struct {
   __IO uint32_t   XRDC2_Type::PAC_PDAC_W0
 
   __IO uint32_t   XRDC2_Type::PAC_PDAC_W1
 
} XRDC2_Type::PACI_PDACJ [8][256]
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W0
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W1
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W2
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W3
 
uint8_t   XRDC2_Type::RESERVED_0 [4]
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W5
 
__IO uint32_t   XRDC2_Type::MRC_MRGD_W6
 
uint8_t   XRDC2_Type::RESERVED_1 [4]
 
struct {
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W0
 
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W1
 
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W2
 
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W3
 
   uint8_t   RESERVED_0 [4]
 
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W5
 
   __IO uint32_t   XRDC2_Type::MRC_MRGD_W6
 
   uint8_t   RESERVED_1 [4]
 
} XRDC2_Type::MRCI_MRGDJ [32][32]
 

Detailed Description

Mapping Information

Typedef Documentation

◆ iomuxc_select_input_t [1/3]

typedef enum _iomuxc_select_input iomuxc_select_input_t

Enumeration for the IOMUXC select input.

Defines the enumeration for the IOMUXC select input collections.

◆ iomuxc_select_input_t [2/3]

typedef enum _iomuxc_select_input iomuxc_select_input_t

Enumeration for the IOMUXC select input.

Defines the enumeration for the IOMUXC select input collections.

◆ iomuxc_select_input_t [3/3]

typedef enum _iomuxc_select_input iomuxc_select_input_t

Enumeration for the IOMUXC select input.

Defines the enumeration for the IOMUXC select input collections.

◆ iomuxc_sw_mux_ctl_pad_t [1/3]

typedef enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t

Enumeration for the IOMUXC SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.

◆ iomuxc_sw_mux_ctl_pad_t [2/3]

typedef enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t

Enumeration for the IOMUXC SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.

◆ iomuxc_sw_mux_ctl_pad_t [3/3]

typedef enum _iomuxc_sw_mux_ctl_pad iomuxc_sw_mux_ctl_pad_t

Enumeration for the IOMUXC SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.

◆ iomuxc_sw_pad_ctl_pad_t [1/3]

typedef enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t

Enumeration for the IOMUXC SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.

◆ iomuxc_sw_pad_ctl_pad_t [2/3]

typedef enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t

Enumeration for the IOMUXC SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.

◆ iomuxc_sw_pad_ctl_pad_t [3/3]

typedef enum _iomuxc_sw_pad_ctl_pad iomuxc_sw_pad_ctl_pad_t

Enumeration for the IOMUXC SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.

Enumeration Type Documentation

◆ _iomuxc_select_input [1/3]

enum _iomuxc_select_input

Enumeration for the IOMUXC select input.

Defines the enumeration for the IOMUXC select input collections.

Enumerator
kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CCM_PMIC_READY_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA02_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA03_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA04_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA05_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA06_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA07_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA08_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA09_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_HSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_PIXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_VSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET0_RXDATA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET1_RXDATA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET0_TIMER_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN1_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DQS_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART2_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART3_CTS_B_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART3_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART3_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART4_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART4_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART5_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART5_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART6_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART6_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_NMI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_MCLK2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_MCLK2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SPDIF_IN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG2_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG1_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_CD_B_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_WP_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_CLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_CD_B_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_CMD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA4_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA5_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA6_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA7_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_WP_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT02_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT03_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT04_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT05_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT06_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT07_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT08_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT09_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT17_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT18_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT20_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT22_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT23_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT24_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT14_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT15_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT16_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT25_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT19_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT21_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN1_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CLKIN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG2_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_20 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_21 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_22 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_23 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_24 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_25 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_26 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_27 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_28 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_29 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_30 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_31 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_32 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_33 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_34 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_35 

IOMUXC select input index

kIOMUXC_FLEXCAN1_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CLKIN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG2_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_20 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_21 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_22 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_23 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_24 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_25 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_26 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_27 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_28 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_29 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_30 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_31 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_32 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_33 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_34 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_35 

IOMUXC select input index

◆ _iomuxc_select_input [2/3]

enum _iomuxc_select_input

Enumeration for the IOMUXC select input.

Defines the enumeration for the IOMUXC select input collections.

Enumerator
kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CCM_PMIC_READY_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA02_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA03_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA04_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA05_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA06_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA07_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA08_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA09_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_HSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_PIXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_VSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET0_RXDATA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET1_RXDATA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET0_TIMER_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN1_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DQS_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART2_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART3_CTS_B_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART3_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART3_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART4_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART4_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART5_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART5_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART6_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART6_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_NMI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_MCLK2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_MCLK2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SPDIF_IN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG2_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG1_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_CD_B_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_WP_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_CLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_CD_B_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_CMD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA4_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA5_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA6_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA7_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_WP_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT02_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT03_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT04_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT05_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT06_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT07_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT08_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT09_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT17_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT18_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT20_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT22_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT23_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT24_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT14_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT15_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT16_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT25_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT19_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT21_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN1_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CLKIN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG2_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_20 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_21 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_22 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_23 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_24 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_25 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_26 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_27 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_28 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_29 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_30 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_31 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_32 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_33 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_34 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_35 

IOMUXC select input index

kIOMUXC_FLEXCAN1_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CLKIN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG2_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_20 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_21 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_22 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_23 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_24 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_25 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_26 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_27 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_28 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_29 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_30 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_31 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_32 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_33 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_34 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_35 

IOMUXC select input index

◆ _iomuxc_select_input [3/3]

enum _iomuxc_select_input

Enumeration for the IOMUXC select input.

Defines the enumeration for the IOMUXC select input collections.

Enumerator
kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CCM_PMIC_READY_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA02_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA03_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA04_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA05_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA06_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA07_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA08_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_DATA09_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_HSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_PIXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_CSI_VSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET0_RXDATA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET1_RXDATA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET0_TIMER_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN1_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DQS_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_B_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI_A_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_PCS0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART2_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART3_CTS_B_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART3_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART3_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART4_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART4_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART5_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART5_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART6_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART6_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_TX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_NMI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_MCLK2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_MCLK2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SPDIF_IN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG2_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG1_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_CD_B_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_WP_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_CLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_CD_B_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_CMD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA4_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA5_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA6_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_DATA7_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_WP_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT02_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT03_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT04_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT05_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT06_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT07_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT08_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT09_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT17_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT18_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT20_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT22_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT23_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT24_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT14_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT15_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT16_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT25_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT19_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR_INOUT21_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN1_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CLKIN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG2_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_20 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_21 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_22 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_23 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_24 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_25 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_26 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_27 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_28 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_29 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_30 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_31 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_32 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_33 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_34 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_35 

IOMUXC select input index

kIOMUXC_FLEXCAN1_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXCAN2_RX_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CAPIN2_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_GPT3_CLKIN_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_COL_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_6 

IOMUXC select input index

kIOMUXC_KPP_ROW_SELECT_INPUT_7 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 

IOMUXC select input index

kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_SIO_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG2_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USB_OTG_OC_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_20 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_21 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_22 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_23 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_24 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_25 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_26 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_27 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_28 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_29 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_30 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_31 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_32 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_33 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_34 

IOMUXC select input index

kIOMUXC_XBAR1_IN_SELECT_INPUT_35 

IOMUXC select input index

◆ _iomuxc_sw_mux_ctl_pad [1/3]

enum _iomuxc_sw_mux_ctl_pad

Enumeration for the IOMUXC SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.

Enumerator
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_MUX_CTL_PAD index

◆ _iomuxc_sw_mux_ctl_pad [2/3]

enum _iomuxc_sw_mux_ctl_pad

Enumeration for the IOMUXC SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.

Enumerator
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_MUX_CTL_PAD index

◆ _iomuxc_sw_mux_ctl_pad [3/3]

enum _iomuxc_sw_mux_ctl_pad

Enumeration for the IOMUXC SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.

Enumerator
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_MUX_CTL_PAD index

kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_MUX_CTL_PAD index

◆ _iomuxc_sw_pad_ctl_pad [1/3]

enum _iomuxc_sw_pad_ctl_pad

Enumeration for the IOMUXC SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.

Enumerator
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_PAD_CTL_PAD index

◆ _iomuxc_sw_pad_ctl_pad [2/3]

enum _iomuxc_sw_pad_ctl_pad

Enumeration for the IOMUXC SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.

Enumerator
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_PAD_CTL_PAD index

◆ _iomuxc_sw_pad_ctl_pad [3/3]

enum _iomuxc_sw_pad_ctl_pad

Enumeration for the IOMUXC SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.

Enumerator
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 

IOMUXC SW_PAD_CTL_PAD index

kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 

IOMUXC SW_PAD_CTL_PAD index

◆ _xbar_input_signal

enum _xbar_input_signal
Enumerator
kXBARA1_InputLogicLow 

LOGIC_LOW output assigned to XBARA1_IN0 input.

kXBARA1_InputLogicHigh 

LOGIC_HIGH output assigned to XBARA1_IN1 input.

kXBARA1_InputIomuxXbarIn02 

IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input.

kXBARA1_InputIomuxXbarIn03 

IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input.

kXBARA1_InputIomuxXbarInout04 

IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input.

kXBARA1_InputIomuxXbarInout05 

IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input.

kXBARA1_InputIomuxXbarInout06 

IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input.

kXBARA1_InputIomuxXbarInout07 

IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input.

kXBARA1_InputIomuxXbarInout08 

IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input.

kXBARA1_InputIomuxXbarInout09 

IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input.

kXBARA1_InputIomuxXbarInout10 

IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input.

kXBARA1_InputIomuxXbarInout11 

IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input.

kXBARA1_InputIomuxXbarInout12 

IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input.

kXBARA1_InputIomuxXbarInout13 

IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input.

kXBARA1_InputIomuxXbarInout14 

IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input.

kXBARA1_InputIomuxXbarInout15 

IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input.

kXBARA1_InputIomuxXbarInout16 

IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input.

kXBARA1_InputIomuxXbarInout17 

IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input.

kXBARA1_InputIomuxXbarInout18 

IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input.

kXBARA1_InputIomuxXbarInout19 

IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input.

kXBARA1_InputIomuxXbarIn20 

IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input.

kXBARA1_InputIomuxXbarIn21 

IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input.

kXBARA1_InputIomuxXbarIn22 

IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input.

kXBARA1_InputIomuxXbarIn23 

IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input.

kXBARA1_InputIomuxXbarIn24 

IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input.

kXBARA1_InputIomuxXbarIn25 

IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input.

kXBARA1_InputAcmp1Out 

ACMP1_OUT output assigned to XBARA1_IN26 input.

kXBARA1_InputAcmp2Out 

ACMP2_OUT output assigned to XBARA1_IN27 input.

kXBARA1_InputAcmp3Out 

ACMP3_OUT output assigned to XBARA1_IN28 input.

kXBARA1_InputAcmp4Out 

ACMP4_OUT output assigned to XBARA1_IN29 input.

kXBARA1_InputRESERVED30 

XBARA1_IN30 input is reserved.

kXBARA1_InputRESERVED31 

XBARA1_IN31 input is reserved.

kXBARA1_InputQtimer3Tmr0Output 

QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input.

kXBARA1_InputQtimer3Tmr1Output 

QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input.

kXBARA1_InputQtimer3Tmr2Output 

QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input.

kXBARA1_InputQtimer3Tmr3Output 

QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input.

kXBARA1_InputQtimer4Tmr0Output 

QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input.

kXBARA1_InputQtimer4Tmr1Output 

QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input.

kXBARA1_InputQtimer4Tmr2Output 

QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input.

kXBARA1_InputQtimer4Tmr3Output 

QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input.

kXBARA1_InputFlexpwm1Pwm1OutTrig01 

FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input.

kXBARA1_InputFlexpwm1Pwm2OutTrig01 

FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input.

kXBARA1_InputFlexpwm1Pwm3OutTrig01 

FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input.

kXBARA1_InputFlexpwm1Pwm4OutTrig01 

FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input.

kXBARA1_InputFlexpwm2Pwm1OutTrig01 

FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input.

kXBARA1_InputFlexpwm2Pwm2OutTrig01 

FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input.

kXBARA1_InputFlexpwm2Pwm3OutTrig01 

FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input.

kXBARA1_InputFlexpwm2Pwm4OutTrig01 

FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input.

kXBARA1_InputFlexpwm3Pwm1OutTrig01 

FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input.

kXBARA1_InputFlexpwm3Pwm2OutTrig01 

FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input.

kXBARA1_InputFlexpwm3Pwm3OutTrig01 

FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input.

kXBARA1_InputFlexpwm3Pwm4OutTrig01 

FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input.

kXBARA1_InputFlexpwm4Pwm1OutTrig01 

FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input.

kXBARA1_InputFlexpwm4Pwm2OutTrig01 

FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input.

kXBARA1_InputFlexpwm4Pwm3OutTrig01 

FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input.

kXBARA1_InputFlexpwm4Pwm4OutTrig01 

FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input.

kXBARA1_InputPitTrigger0 

PIT_TRIGGER0 output assigned to XBARA1_IN56 input.

kXBARA1_InputPitTrigger1 

PIT_TRIGGER1 output assigned to XBARA1_IN57 input.

kXBARA1_InputPitTrigger2 

PIT_TRIGGER2 output assigned to XBARA1_IN58 input.

kXBARA1_InputPitTrigger3 

PIT_TRIGGER3 output assigned to XBARA1_IN59 input.

kXBARA1_InputEnc1PosMatch 

ENC1_POS_MATCH output assigned to XBARA1_IN60 input.

kXBARA1_InputEnc2PosMatch 

ENC2_POS_MATCH output assigned to XBARA1_IN61 input.

kXBARA1_InputEnc3PosMatch 

ENC3_POS_MATCH output assigned to XBARA1_IN62 input.

kXBARA1_InputEnc4PosMatch 

ENC4_POS_MATCH output assigned to XBARA1_IN63 input.

kXBARA1_InputDmaDone0 

DMA_DONE0 output assigned to XBARA1_IN64 input.

kXBARA1_InputDmaDone1 

DMA_DONE1 output assigned to XBARA1_IN65 input.

kXBARA1_InputDmaDone2 

DMA_DONE2 output assigned to XBARA1_IN66 input.

kXBARA1_InputDmaDone3 

DMA_DONE3 output assigned to XBARA1_IN67 input.

kXBARA1_InputDmaDone4 

DMA_DONE4 output assigned to XBARA1_IN68 input.

kXBARA1_InputDmaDone5 

DMA_DONE5 output assigned to XBARA1_IN69 input.

kXBARA1_InputDmaDone6 

DMA_DONE6 output assigned to XBARA1_IN70 input.

kXBARA1_InputDmaDone7 

DMA_DONE7 output assigned to XBARA1_IN71 input.

kXBARA1_InputAoi1Out0 

AOI1_OUT0 output assigned to XBARA1_IN72 input.

kXBARA1_InputAoi1Out1 

AOI1_OUT1 output assigned to XBARA1_IN73 input.

kXBARA1_InputAoi1Out2 

AOI1_OUT2 output assigned to XBARA1_IN74 input.

kXBARA1_InputAoi1Out3 

AOI1_OUT3 output assigned to XBARA1_IN75 input.

kXBARA1_InputAoi2Out0 

AOI2_OUT0 output assigned to XBARA1_IN76 input.

kXBARA1_InputAoi2Out1 

AOI2_OUT1 output assigned to XBARA1_IN77 input.

kXBARA1_InputAoi2Out2 

AOI2_OUT2 output assigned to XBARA1_IN78 input.

kXBARA1_InputAoi2Out3 

AOI2_OUT3 output assigned to XBARA1_IN79 input.

kXBARA1_InputAdcEtcXbar0Coco0 

ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input.

kXBARA1_InputAdcEtcXbar0Coco1 

ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input.

kXBARA1_InputAdcEtcXbar0Coco2 

ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input.

kXBARA1_InputAdcEtcXbar0Coco3 

ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input.

kXBARA1_InputAdcEtcXbar1Coco0 

ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input.

kXBARA1_InputAdcEtcXbar1Coco1 

ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input.

kXBARA1_InputAdcEtcXbar1Coco2 

ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input.

kXBARA1_InputAdcEtcXbar1Coco3 

ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input.

kXBARB2_InputLogicLow 

LOGIC_LOW output assigned to XBARB2_IN0 input.

kXBARB2_InputLogicHigh 

LOGIC_HIGH output assigned to XBARB2_IN1 input.

kXBARB2_InputRESERVED2 

XBARB2_IN2 input is reserved.

kXBARB2_InputRESERVED3 

XBARB2_IN3 input is reserved.

kXBARB2_InputRESERVED4 

XBARB2_IN4 input is reserved.

kXBARB2_InputRESERVED5 

XBARB2_IN5 input is reserved.

kXBARB2_InputAcmp1Out 

ACMP1_OUT output assigned to XBARB2_IN6 input.

kXBARB2_InputAcmp2Out 

ACMP2_OUT output assigned to XBARB2_IN7 input.

kXBARB2_InputAcmp3Out 

ACMP3_OUT output assigned to XBARB2_IN8 input.

kXBARB2_InputAcmp4Out 

ACMP4_OUT output assigned to XBARB2_IN9 input.

kXBARB2_InputRESERVED10 

XBARB2_IN10 input is reserved.

kXBARB2_InputRESERVED11 

XBARB2_IN11 input is reserved.

kXBARB2_InputQtimer3Tmr0Output 

QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input.

kXBARB2_InputQtimer3Tmr1Output 

QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input.

kXBARB2_InputQtimer3Tmr2Output 

QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input.

kXBARB2_InputQtimer3Tmr3Output 

QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input.

kXBARB2_InputQtimer4Tmr0Output 

QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input.

kXBARB2_InputQtimer4Tmr1Output 

QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input.

kXBARB2_InputQtimer4Tmr2Output 

QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input.

kXBARB2_InputQtimer4Tmr3Output 

QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input.

kXBARB2_InputFlexpwm1Pwm1OutTrig01 

FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input.

kXBARB2_InputFlexpwm1Pwm2OutTrig01 

FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input.

kXBARB2_InputFlexpwm1Pwm3OutTrig01 

FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input.

kXBARB2_InputFlexpwm1Pwm4OutTrig01 

FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input.

kXBARB2_InputFlexpwm2Pwm1OutTrig01 

FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input.

kXBARB2_InputFlexpwm2Pwm2OutTrig01 

FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input.

kXBARB2_InputFlexpwm2Pwm3OutTrig01 

FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input.

kXBARB2_InputFlexpwm2Pwm4OutTrig01 

FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input.

kXBARB2_InputFlexpwm3Pwm1OutTrig01 

FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input.

kXBARB2_InputFlexpwm3Pwm2OutTrig01 

FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input.

kXBARB2_InputFlexpwm3Pwm3OutTrig01 

FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input.

kXBARB2_InputFlexpwm3Pwm4OutTrig01 

FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input.

kXBARB2_InputFlexpwm4Pwm1OutTrig01 

FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input.

kXBARB2_InputFlexpwm4Pwm2OutTrig01 

FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input.

kXBARB2_InputFlexpwm4Pwm3OutTrig01 

FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input.

kXBARB2_InputFlexpwm4Pwm4OutTrig01 

FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input.

kXBARB2_InputPitTrigger0 

PIT_TRIGGER0 output assigned to XBARB2_IN36 input.

kXBARB2_InputPitTrigger1 

PIT_TRIGGER1 output assigned to XBARB2_IN37 input.

kXBARB2_InputAdcEtcXbar0Coco0 

ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input.

kXBARB2_InputAdcEtcXbar0Coco1 

ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input.

kXBARB2_InputAdcEtcXbar0Coco2 

ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input.

kXBARB2_InputAdcEtcXbar0Coco3 

ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input.

kXBARB2_InputAdcEtcXbar1Coco0 

ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input.

kXBARB2_InputAdcEtcXbar1Coco1 

ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input.

kXBARB2_InputAdcEtcXbar1Coco2 

ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input.

kXBARB2_InputAdcEtcXbar1Coco3 

ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input.

kXBARB2_InputEnc1PosMatch 

ENC1_POS_MATCH output assigned to XBARB2_IN46 input.

kXBARB2_InputEnc2PosMatch 

ENC2_POS_MATCH output assigned to XBARB2_IN47 input.

kXBARB2_InputEnc3PosMatch 

ENC3_POS_MATCH output assigned to XBARB2_IN48 input.

kXBARB2_InputEnc4PosMatch 

ENC4_POS_MATCH output assigned to XBARB2_IN49 input.

kXBARB2_InputDmaDone0 

DMA_DONE0 output assigned to XBARB2_IN50 input.

kXBARB2_InputDmaDone1 

DMA_DONE1 output assigned to XBARB2_IN51 input.

kXBARB2_InputDmaDone2 

DMA_DONE2 output assigned to XBARB2_IN52 input.

kXBARB2_InputDmaDone3 

DMA_DONE3 output assigned to XBARB2_IN53 input.

kXBARB2_InputDmaDone4 

DMA_DONE4 output assigned to XBARB2_IN54 input.

kXBARB2_InputDmaDone5 

DMA_DONE5 output assigned to XBARB2_IN55 input.

kXBARB2_InputDmaDone6 

DMA_DONE6 output assigned to XBARB2_IN56 input.

kXBARB2_InputDmaDone7 

DMA_DONE7 output assigned to XBARB2_IN57 input.

kXBARB3_InputLogicLow 

LOGIC_LOW output assigned to XBARB3_IN0 input.

kXBARB3_InputLogicHigh 

LOGIC_HIGH output assigned to XBARB3_IN1 input.

kXBARB3_InputRESERVED2 

XBARB3_IN2 input is reserved.

kXBARB3_InputRESERVED3 

XBARB3_IN3 input is reserved.

kXBARB3_InputRESERVED4 

XBARB3_IN4 input is reserved.

kXBARB3_InputRESERVED5 

XBARB3_IN5 input is reserved.

kXBARB3_InputAcmp1Out 

ACMP1_OUT output assigned to XBARB3_IN6 input.

kXBARB3_InputAcmp2Out 

ACMP2_OUT output assigned to XBARB3_IN7 input.

kXBARB3_InputAcmp3Out 

ACMP3_OUT output assigned to XBARB3_IN8 input.

kXBARB3_InputAcmp4Out 

ACMP4_OUT output assigned to XBARB3_IN9 input.

kXBARB3_InputRESERVED10 

XBARB3_IN10 input is reserved.

kXBARB3_InputRESERVED11 

XBARB3_IN11 input is reserved.

kXBARB3_InputQtimer3Tmr0Output 

QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input.

kXBARB3_InputQtimer3Tmr1Output 

QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input.

kXBARB3_InputQtimer3Tmr2Output 

QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input.

kXBARB3_InputQtimer3Tmr3Output 

QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input.

kXBARB3_InputQtimer4Tmr0Output 

QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input.

kXBARB3_InputQtimer4Tmr1Output 

QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input.

kXBARB3_InputQtimer4Tmr2Output 

QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input.

kXBARB3_InputQtimer4Tmr3Output 

QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input.

kXBARB3_InputFlexpwm1Pwm1OutTrig01 

FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input.

kXBARB3_InputFlexpwm1Pwm2OutTrig01 

FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input.

kXBARB3_InputFlexpwm1Pwm3OutTrig01 

FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input.

kXBARB3_InputFlexpwm1Pwm4OutTrig01 

FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input.

kXBARB3_InputFlexpwm2Pwm1OutTrig01 

FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input.

kXBARB3_InputFlexpwm2Pwm2OutTrig01 

FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input.

kXBARB3_InputFlexpwm2Pwm3OutTrig01 

FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input.

kXBARB3_InputFlexpwm2Pwm4OutTrig01 

FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input.

kXBARB3_InputFlexpwm3Pwm1OutTrig01 

FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input.

kXBARB3_InputFlexpwm3Pwm2OutTrig01 

FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input.

kXBARB3_InputFlexpwm3Pwm3OutTrig01 

FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input.

kXBARB3_InputFlexpwm3Pwm4OutTrig01 

FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input.

kXBARB3_InputFlexpwm4Pwm1OutTrig01 

FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input.

kXBARB3_InputFlexpwm4Pwm2OutTrig01 

FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input.

kXBARB3_InputFlexpwm4Pwm3OutTrig01 

FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input.

kXBARB3_InputFlexpwm4Pwm4OutTrig01 

FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input.

kXBARB3_InputPitTrigger0 

PIT_TRIGGER0 output assigned to XBARB3_IN36 input.

kXBARB3_InputPitTrigger1 

PIT_TRIGGER1 output assigned to XBARB3_IN37 input.

kXBARB3_InputAdcEtcXbar0Coco0 

ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input.

kXBARB3_InputAdcEtcXbar0Coco1 

ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input.

kXBARB3_InputAdcEtcXbar0Coco2 

ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input.

kXBARB3_InputAdcEtcXbar0Coco3 

ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input.

kXBARB3_InputAdcEtcXbar1Coco0 

ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input.

kXBARB3_InputAdcEtcXbar1Coco1 

ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input.

kXBARB3_InputAdcEtcXbar1Coco2 

ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input.

kXBARB3_InputAdcEtcXbar1Coco3 

ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input.

kXBARB3_InputEnc1PosMatch 

ENC1_POS_MATCH output assigned to XBARB3_IN46 input.

kXBARB3_InputEnc2PosMatch 

ENC2_POS_MATCH output assigned to XBARB3_IN47 input.

kXBARB3_InputEnc3PosMatch 

ENC3_POS_MATCH output assigned to XBARB3_IN48 input.

kXBARB3_InputEnc4PosMatch 

ENC4_POS_MATCH output assigned to XBARB3_IN49 input.

kXBARB3_InputDmaDone0 

DMA_DONE0 output assigned to XBARB3_IN50 input.

kXBARB3_InputDmaDone1 

DMA_DONE1 output assigned to XBARB3_IN51 input.

kXBARB3_InputDmaDone2 

DMA_DONE2 output assigned to XBARB3_IN52 input.

kXBARB3_InputDmaDone3 

DMA_DONE3 output assigned to XBARB3_IN53 input.

kXBARB3_InputDmaDone4 

DMA_DONE4 output assigned to XBARB3_IN54 input.

kXBARB3_InputDmaDone5 

DMA_DONE5 output assigned to XBARB3_IN55 input.

kXBARB3_InputDmaDone6 

DMA_DONE6 output assigned to XBARB3_IN56 input.

kXBARB3_InputDmaDone7 

DMA_DONE7 output assigned to XBARB3_IN57 input.

kXBARA1_InputLogicLow 

LOGIC_LOW output assigned to XBARA1_IN0 input.

kXBARA1_InputLogicHigh 

LOGIC_HIGH output assigned to XBARA1_IN1 input.

kXBARA1_InputRESERVED2 

XBARA1_IN2 input is reserved.

kXBARA1_InputRESERVED3 

XBARA1_IN3 input is reserved.

kXBARA1_InputIomuxXbarInout04 

IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input.

kXBARA1_InputIomuxXbarInout05 

IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input.

kXBARA1_InputIomuxXbarInout06 

IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input.

kXBARA1_InputIomuxXbarInout07 

IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input.

kXBARA1_InputIomuxXbarInout08 

IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input.

kXBARA1_InputIomuxXbarInout09 

IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input.

kXBARA1_InputIomuxXbarInout10 

IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input.

kXBARA1_InputIomuxXbarInout11 

IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input.

kXBARA1_InputIomuxXbarInout12 

IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input.

kXBARA1_InputIomuxXbarInout13 

IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input.

kXBARA1_InputIomuxXbarInout14 

IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input.

kXBARA1_InputIomuxXbarInout15 

IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input.

kXBARA1_InputIomuxXbarInout16 

IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input.

kXBARA1_InputIomuxXbarInout17 

IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input.

kXBARA1_InputIomuxXbarInout18 

IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input.

kXBARA1_InputIomuxXbarInout19 

IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input.

kXBARA1_InputIomuxXbarInout20 

IOMUX_XBAR_INOUT20 output assigned to XBARA1_IN20 input.

kXBARA1_InputIomuxXbarInout21 

IOMUX_XBAR_INOUT21 output assigned to XBARA1_IN21 input.

kXBARA1_InputIomuxXbarInout22 

IOMUX_XBAR_INOUT22 output assigned to XBARA1_IN22 input.

kXBARA1_InputIomuxXbarInout23 

IOMUX_XBAR_INOUT23 output assigned to XBARA1_IN23 input.

kXBARA1_InputIomuxXbarInout24 

IOMUX_XBAR_INOUT24 output assigned to XBARA1_IN24 input.

kXBARA1_InputIomuxXbarInout25 

IOMUX_XBAR_INOUT25 output assigned to XBARA1_IN25 input.

kXBARA1_InputIomuxXbarInout26 

IOMUX_XBAR_INOUT26 output assigned to XBARA1_IN26 input.

kXBARA1_InputIomuxXbarInout27 

IOMUX_XBAR_INOUT27 output assigned to XBARA1_IN27 input.

kXBARA1_InputIomuxXbarInout28 

IOMUX_XBAR_INOUT28 output assigned to XBARA1_IN28 input.

kXBARA1_InputIomuxXbarInout29 

IOMUX_XBAR_INOUT29 output assigned to XBARA1_IN29 input.

kXBARA1_InputIomuxXbarInout30 

IOMUX_XBAR_INOUT30 output assigned to XBARA1_IN30 input.

kXBARA1_InputIomuxXbarInout31 

IOMUX_XBAR_INOUT31 output assigned to XBARA1_IN31 input.

kXBARA1_InputIomuxXbarInout32 

IOMUX_XBAR_INOUT32 output assigned to XBARA1_IN32 input.

kXBARA1_InputIomuxXbarInout33 

IOMUX_XBAR_INOUT33 output assigned to XBARA1_IN33 input.

kXBARA1_InputIomuxXbarInout34 

IOMUX_XBAR_INOUT34 output assigned to XBARA1_IN34 input.

kXBARA1_InputIomuxXbarInout35 

IOMUX_XBAR_INOUT35 output assigned to XBARA1_IN35 input.

kXBARA1_InputIomuxXbarInout36 

IOMUX_XBAR_INOUT36 output assigned to XBARA1_IN36 input.

kXBARA1_InputIomuxXbarInout37 

IOMUX_XBAR_INOUT37 output assigned to XBARA1_IN37 input.

kXBARA1_InputIomuxXbarInout38 

IOMUX_XBAR_INOUT38 output assigned to XBARA1_IN38 input.

kXBARA1_InputIomuxXbarInout39 

IOMUX_XBAR_INOUT39 output assigned to XBARA1_IN39 input.

kXBARA1_InputIomuxXbarInout40 

IOMUX_XBAR_INOUT40 output assigned to XBARA1_IN40 input.

kXBARA1_InputRESERVED41 

XBARA1_IN41 input is reserved.

kXBARA1_InputAcmp1Out 

ACMP1_OUT output assigned to XBARA1_IN42 input.

kXBARA1_InputAcmp2Out 

ACMP2_OUT output assigned to XBARA1_IN43 input.

kXBARA1_InputAcmp3Out 

ACMP3_OUT output assigned to XBARA1_IN44 input.

kXBARA1_InputAcmp4Out 

ACMP4_OUT output assigned to XBARA1_IN45 input.

kXBARA1_InputRESERVED46 

XBARA1_IN46 input is reserved.

kXBARA1_InputRESERVED47 

XBARA1_IN47 input is reserved.

kXBARA1_InputRESERVED48 

XBARA1_IN48 input is reserved.

kXBARA1_InputRESERVED49 

XBARA1_IN49 input is reserved.

kXBARA1_InputQtimer1Timer0 

QTIMER1_TIMER0 output assigned to XBARA1_IN50 input.

kXBARA1_InputQtimer1Timer1 

QTIMER1_TIMER1 output assigned to XBARA1_IN51 input.

kXBARA1_InputQtimer1Timer2 

QTIMER1_TIMER2 output assigned to XBARA1_IN52 input.

kXBARA1_InputQtimer1Timer3 

QTIMER1_TIMER3 output assigned to XBARA1_IN53 input.

kXBARA1_InputQtimer2Timer0 

QTIMER2_TIMER0 output assigned to XBARA1_IN54 input.

kXBARA1_InputQtimer2Timer1 

QTIMER2_TIMER1 output assigned to XBARA1_IN55 input.

kXBARA1_InputQtimer2Timer2 

QTIMER2_TIMER2 output assigned to XBARA1_IN56 input.

kXBARA1_InputQtimer2Timer3 

QTIMER2_TIMER3 output assigned to XBARA1_IN57 input.

kXBARA1_InputQtimer3Timer0 

QTIMER3_TIMER0 output assigned to XBARA1_IN58 input.

kXBARA1_InputQtimer3Timer1 

QTIMER3_TIMER1 output assigned to XBARA1_IN59 input.

kXBARA1_InputQtimer3Timer2 

QTIMER3_TIMER2 output assigned to XBARA1_IN60 input.

kXBARA1_InputQtimer3Timer3 

QTIMER3_TIMER3 output assigned to XBARA1_IN61 input.

kXBARA1_InputQtimer4Timer0 

QTIMER4_TIMER0 output assigned to XBARA1_IN62 input.

kXBARA1_InputQtimer4Timer1 

QTIMER4_TIMER1 output assigned to XBARA1_IN63 input.

kXBARA1_InputQtimer4Timer2 

QTIMER4_TIMER2 output assigned to XBARA1_IN64 input.

kXBARA1_InputQtimer4Timer3 

QTIMER4_TIMER3 output assigned to XBARA1_IN65 input.

kXBARA1_InputRESERVED66 

XBARA1_IN66 input is reserved.

kXBARA1_InputRESERVED67 

XBARA1_IN67 input is reserved.

kXBARA1_InputRESERVED68 

XBARA1_IN68 input is reserved.

kXBARA1_InputRESERVED69 

XBARA1_IN69 input is reserved.

kXBARA1_InputRESERVED70 

XBARA1_IN70 input is reserved.

kXBARA1_InputRESERVED71 

XBARA1_IN71 input is reserved.

kXBARA1_InputRESERVED72 

XBARA1_IN72 input is reserved.

kXBARA1_InputRESERVED73 

XBARA1_IN73 input is reserved.

kXBARA1_InputFlexpwm1Pwm0OutTrig0 

FLEXPWM1_PWM0_OUT_TRIG0 output assigned to XBARA1_IN74 input.

kXBARA1_InputFlexpwm1Pwm0OutTrig1 

FLEXPWM1_PWM0_OUT_TRIG1 output assigned to XBARA1_IN75 input.

kXBARA1_InputFlexpwm1Pwm1OutTrig0 

FLEXPWM1_PWM1_OUT_TRIG0 output assigned to XBARA1_IN76 input.

kXBARA1_InputFlexpwm1Pwm1OutTrig1 

FLEXPWM1_PWM1_OUT_TRIG1 output assigned to XBARA1_IN77 input.

kXBARA1_InputFlexpwm1Pwm2OutTrig0 

FLEXPWM1_PWM2_OUT_TRIG0 output assigned to XBARA1_IN78 input.

kXBARA1_InputFlexpwm1Pwm2OutTrig1 

FLEXPWM1_PWM2_OUT_TRIG1 output assigned to XBARA1_IN79 input.

kXBARA1_InputFlexpwm1Pwm3OutTrig0 

FLEXPWM1_PWM3_OUT_TRIG0 output assigned to XBARA1_IN80 input.

kXBARA1_InputFlexpwm1Pwm3OutTrig1 

FLEXPWM1_PWM3_OUT_TRIG1 output assigned to XBARA1_IN81 input.

kXBARA1_InputFlexpwm2Pwm0OutTrig01 

FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN82 input.

kXBARA1_InputFlexpwm2Pwm1OutTrig01 

FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN83 input.

kXBARA1_InputFlexpwm2Pwm2OutTrig01 

FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN84 input.

kXBARA1_InputFlexpwm2Pwm3OutTrig01 

FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN85 input.

kXBARA1_InputFlexpwm3Pwm0OutTrig01 

FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN86 input.

kXBARA1_InputFlexpwm3Pwm1OutTrig01 

FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN87 input.

kXBARA1_InputFlexpwm3Pwm2OutTrig01 

FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN88 input.

kXBARA1_InputFlexpwm3Pwm3OutTrig01 

FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN89 input.

kXBARA1_InputFlexpwm4Pwm0OutTrig01 

FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN90 input.

kXBARA1_InputFlexpwm4Pwm1OutTrig01 

FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN91 input.

kXBARA1_InputFlexpwm4Pwm2OutTrig01 

FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN92 input.

kXBARA1_InputFlexpwm4Pwm3OutTrig01 

FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN93 input.

kXBARA1_InputRESERVED94 

XBARA1_IN94 input is reserved.

kXBARA1_InputRESERVED95 

XBARA1_IN95 input is reserved.

kXBARA1_InputRESERVED96 

XBARA1_IN96 input is reserved.

kXBARA1_InputRESERVED97 

XBARA1_IN97 input is reserved.

kXBARA1_InputRESERVED98 

XBARA1_IN98 input is reserved.

kXBARA1_InputRESERVED99 

XBARA1_IN99 input is reserved.

kXBARA1_InputRESERVED100 

XBARA1_IN100 input is reserved.

kXBARA1_InputRESERVED101 

XBARA1_IN101 input is reserved.

kXBARA1_InputPit1Trigger0 

PIT1_TRIGGER0 output assigned to XBARA1_IN102 input.

kXBARA1_InputPit1Trigger1 

PIT1_TRIGGER1 output assigned to XBARA1_IN103 input.

kXBARA1_InputPit1Trigger2 

PIT1_TRIGGER2 output assigned to XBARA1_IN104 input.

kXBARA1_InputPit1Trigger3 

PIT1_TRIGGER3 output assigned to XBARA1_IN105 input.

kXBARA1_InputDec1PosMatch 

DEC1_POS_MATCH output assigned to XBARA1_IN106 input.

kXBARA1_InputDec2PosMatch 

DEC2_POS_MATCH output assigned to XBARA1_IN107 input.

kXBARA1_InputDec3PosMatch 

DEC3_POS_MATCH output assigned to XBARA1_IN108 input.

kXBARA1_InputDec4PosMatch 

DEC4_POS_MATCH output assigned to XBARA1_IN109 input.

kXBARA1_InputRESERVED110 

XBARA1_IN110 input is reserved.

kXBARA1_InputRESERVED111 

XBARA1_IN111 input is reserved.

kXBARA1_InputDmaDone0 

DMA_DONE0 output assigned to XBARA1_IN112 input.

kXBARA1_InputDmaDone1 

DMA_DONE1 output assigned to XBARA1_IN113 input.

kXBARA1_InputDmaDone2 

DMA_DONE2 output assigned to XBARA1_IN114 input.

kXBARA1_InputDmaDone3 

DMA_DONE3 output assigned to XBARA1_IN115 input.

kXBARA1_InputDmaDone4 

DMA_DONE4 output assigned to XBARA1_IN116 input.

kXBARA1_InputDmaDone5 

DMA_DONE5 output assigned to XBARA1_IN117 input.

kXBARA1_InputDmaDone6 

DMA_DONE6 output assigned to XBARA1_IN118 input.

kXBARA1_InputDmaDone7 

DMA_DONE7 output assigned to XBARA1_IN119 input.

kXBARA1_InputDmaLpsrDone0 

DMA_LPSR_DONE0 output assigned to XBARA1_IN120 input.

kXBARA1_InputDmaLpsrDone1 

DMA_LPSR_DONE1 output assigned to XBARA1_IN121 input.

kXBARA1_InputDmaLpsrDone2 

DMA_LPSR_DONE2 output assigned to XBARA1_IN122 input.

kXBARA1_InputDmaLpsrDone3 

DMA_LPSR_DONE3 output assigned to XBARA1_IN123 input.

kXBARA1_InputDmaLpsrDone4 

DMA_LPSR_DONE4 output assigned to XBARA1_IN124 input.

kXBARA1_InputDmaLpsrDone5 

DMA_LPSR_DONE5 output assigned to XBARA1_IN125 input.

kXBARA1_InputDmaLpsrDone6 

DMA_LPSR_DONE6 output assigned to XBARA1_IN126 input.

kXBARA1_InputDmaLpsrDone7 

DMA_LPSR_DONE7 output assigned to XBARA1_IN127 input.

kXBARA1_InputAoi1Out0 

AOI1_OUT0 output assigned to XBARA1_IN128 input.

kXBARA1_InputAoi1Out1 

AOI1_OUT1 output assigned to XBARA1_IN129 input.

kXBARA1_InputAoi1Out2 

AOI1_OUT2 output assigned to XBARA1_IN130 input.

kXBARA1_InputAoi1Out3 

AOI1_OUT3 output assigned to XBARA1_IN131 input.

kXBARA1_InputAoi2Out0 

AOI2_OUT0 output assigned to XBARA1_IN132 input.

kXBARA1_InputAoi2Out1 

AOI2_OUT1 output assigned to XBARA1_IN133 input.

kXBARA1_InputAoi2Out2 

AOI2_OUT2 output assigned to XBARA1_IN134 input.

kXBARA1_InputAoi2Out3 

AOI2_OUT3 output assigned to XBARA1_IN135 input.

kXBARA1_InputAdcEtc0Coco0 

ADC_ETC0_COCO0 output assigned to XBARA1_IN136 input.

kXBARA1_InputAdcEtc0Coco1 

ADC_ETC0_COCO1 output assigned to XBARA1_IN137 input.

kXBARA1_InputAdcEtc0Coco2 

ADC_ETC0_COCO2 output assigned to XBARA1_IN138 input.

kXBARA1_InputAdcEtc0Coco3 

ADC_ETC0_COCO3 output assigned to XBARA1_IN139 input.

kXBARA1_InputAdcEtc1Coco0 

ADC_ETC1_COCO0 output assigned to XBARA1_IN140 input.

kXBARA1_InputAdcEtc1Coco1 

ADC_ETC1_COCO1 output assigned to XBARA1_IN141 input.

kXBARA1_InputAdcEtc1Coco2 

ADC_ETC1_COCO2 output assigned to XBARA1_IN142 input.

kXBARA1_InputAdcEtc1Coco3 

ADC_ETC1_COCO3 output assigned to XBARA1_IN143 input.

kXBARB2_InputLogicLow 

LOGIC_LOW output assigned to XBARB2_IN0 input.

kXBARB2_InputLogicHigh 

LOGIC_HIGH output assigned to XBARB2_IN1 input.

kXBARB2_InputAcmp1Out 

ACMP1_OUT output assigned to XBARB2_IN2 input.

kXBARB2_InputAcmp2Out 

ACMP2_OUT output assigned to XBARB2_IN3 input.

kXBARB2_InputAcmp3Out 

ACMP3_OUT output assigned to XBARB2_IN4 input.

kXBARB2_InputAcmp4Out 

ACMP4_OUT output assigned to XBARB2_IN5 input.

kXBARB2_InputRESERVED6 

XBARB2_IN6 input is reserved.

kXBARB2_InputRESERVED7 

XBARB2_IN7 input is reserved.

kXBARB2_InputRESERVED8 

XBARB2_IN8 input is reserved.

kXBARB2_InputRESERVED9 

XBARB2_IN9 input is reserved.

kXBARB2_InputQtimer1Timer0 

QTIMER1_TIMER0 output assigned to XBARB2_IN10 input.

kXBARB2_InputQtimer1Timer1 

QTIMER1_TIMER1 output assigned to XBARB2_IN11 input.

kXBARB2_InputQtimer1Timer2 

QTIMER1_TIMER2 output assigned to XBARB2_IN12 input.

kXBARB2_InputQtimer1Timer3 

QTIMER1_TIMER3 output assigned to XBARB2_IN13 input.

kXBARB2_InputQtimer2Timer0 

QTIMER2_TIMER0 output assigned to XBARB2_IN14 input.

kXBARB2_InputQtimer2Timer1 

QTIMER2_TIMER1 output assigned to XBARB2_IN15 input.

kXBARB2_InputQtimer2Timer2 

QTIMER2_TIMER2 output assigned to XBARB2_IN16 input.

kXBARB2_InputQtimer2Timer3 

QTIMER2_TIMER3 output assigned to XBARB2_IN17 input.

kXBARB2_InputQtimer3Timer0 

QTIMER3_TIMER0 output assigned to XBARB2_IN18 input.

kXBARB2_InputQtimer3Timer1 

QTIMER3_TIMER1 output assigned to XBARB2_IN19 input.

kXBARB2_InputQtimer3Timer2 

QTIMER3_TIMER2 output assigned to XBARB2_IN20 input.

kXBARB2_InputQtimer3Timer3 

QTIMER3_TIMER3 output assigned to XBARB2_IN21 input.

kXBARB2_InputQtimer4Timer0 

QTIMER4_TIMER0 output assigned to XBARB2_IN22 input.

kXBARB2_InputQtimer4Timer1 

QTIMER4_TIMER1 output assigned to XBARB2_IN23 input.

kXBARB2_InputQtimer4Timer2 

QTIMER4_TIMER2 output assigned to XBARB2_IN24 input.

kXBARB2_InputQtimer4Timer3 

QTIMER4_TIMER3 output assigned to XBARB2_IN25 input.

kXBARB2_InputRESERVED26 

XBARB2_IN26 input is reserved.

kXBARB2_InputRESERVED27 

XBARB2_IN27 input is reserved.

kXBARB2_InputRESERVED28 

XBARB2_IN28 input is reserved.

kXBARB2_InputRESERVED29 

XBARB2_IN29 input is reserved.

kXBARB2_InputRESERVED30 

XBARB2_IN30 input is reserved.

kXBARB2_InputRESERVED31 

XBARB2_IN31 input is reserved.

kXBARB2_InputRESERVED32 

XBARB2_IN32 input is reserved.

kXBARB2_InputRESERVED33 

XBARB2_IN33 input is reserved.

kXBARB2_InputFlexpwm1Pwm0OutTrig01 

FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN34 input.

kXBARB2_InputFlexpwm1Pwm1OutTrig01 

FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN35 input.

kXBARB2_InputFlexpwm1Pwm2OutTrig01 

FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN36 input.

kXBARB2_InputFlexpwm1Pwm3OutTrig01 

FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN37 input.

kXBARB2_InputFlexpwm2Pwm0OutTrig01 

FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN38 input.

kXBARB2_InputFlexpwm2Pwm1OutTrig01 

FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN39 input.

kXBARB2_InputFlexpwm2Pwm2OutTrig01 

FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN40 input.

kXBARB2_InputFlexpwm2Pwm3OutTrig01 

FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN41 input.

kXBARB2_InputFlexpwm3Pwm0OutTrig01 

FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN42 input.

kXBARB2_InputFlexpwm3Pwm1OutTrig01 

FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN43 input.

kXBARB2_InputFlexpwm3Pwm2OutTrig01 

FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN44 input.

kXBARB2_InputFlexpwm3Pwm3OutTrig01 

FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN45 input.

kXBARB2_InputFlexpwm4Pwm0OutTrig01 

FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN46 input.

kXBARB2_InputFlexpwm4Pwm1OutTrig01 

FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN47 input.

kXBARB2_InputFlexpwm4Pwm2OutTrig01 

FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN48 input.

kXBARB2_InputFlexpwm4Pwm3OutTrig01 

FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN49 input.

kXBARB2_InputRESERVED50 

XBARB2_IN50 input is reserved.

kXBARB2_InputRESERVED51 

XBARB2_IN51 input is reserved.

kXBARB2_InputRESERVED52 

XBARB2_IN52 input is reserved.

kXBARB2_InputRESERVED53 

XBARB2_IN53 input is reserved.

kXBARB2_InputRESERVED54 

XBARB2_IN54 input is reserved.

kXBARB2_InputRESERVED55 

XBARB2_IN55 input is reserved.

kXBARB2_InputRESERVED56 

XBARB2_IN56 input is reserved.

kXBARB2_InputRESERVED57 

XBARB2_IN57 input is reserved.

kXBARB2_InputPit1Trigger0 

PIT1_TRIGGER0 output assigned to XBARB2_IN58 input.

kXBARB2_InputPit1Trigger1 

PIT1_TRIGGER1 output assigned to XBARB2_IN59 input.

kXBARB2_InputAdcEtc0Coco0 

ADC_ETC0_COCO0 output assigned to XBARB2_IN60 input.

kXBARB2_InputAdcEtc0Coco1 

ADC_ETC0_COCO1 output assigned to XBARB2_IN61 input.

kXBARB2_InputAdcEtc0Coco2 

ADC_ETC0_COCO2 output assigned to XBARB2_IN62 input.

kXBARB2_InputAdcEtc0Coco3 

ADC_ETC0_COCO3 output assigned to XBARB2_IN63 input.

kXBARB2_InputAdcEtc1Coco0 

ADC_ETC1_COCO0 output assigned to XBARB2_IN64 input.

kXBARB2_InputAdcEtc1Coco1 

ADC_ETC1_COCO1 output assigned to XBARB2_IN65 input.

kXBARB2_InputAdcEtc1Coco2 

ADC_ETC1_COCO2 output assigned to XBARB2_IN66 input.

kXBARB2_InputAdcEtc1Coco3 

ADC_ETC1_COCO3 output assigned to XBARB2_IN67 input.

kXBARB2_InputRESERVED68 

XBARB2_IN68 input is reserved.

kXBARB2_InputRESERVED69 

XBARB2_IN69 input is reserved.

kXBARB2_InputRESERVED70 

XBARB2_IN70 input is reserved.

kXBARB2_InputRESERVED71 

XBARB2_IN71 input is reserved.

kXBARB2_InputRESERVED72 

XBARB2_IN72 input is reserved.

kXBARB2_InputRESERVED73 

XBARB2_IN73 input is reserved.

kXBARB2_InputRESERVED74 

XBARB2_IN74 input is reserved.

kXBARB2_InputRESERVED75 

XBARB2_IN75 input is reserved.

kXBARB2_InputDec1PosMatch 

DEC1_POS_MATCH output assigned to XBARB2_IN76 input.

kXBARB2_InputDec2PosMatch 

DEC2_POS_MATCH output assigned to XBARB2_IN77 input.

kXBARB2_InputDec3PosMatch 

DEC3_POS_MATCH output assigned to XBARB2_IN78 input.

kXBARB2_InputDec4PosMatch 

DEC4_POS_MATCH output assigned to XBARB2_IN79 input.

kXBARB2_InputRESERVED80 

XBARB2_IN80 input is reserved.

kXBARB2_InputRESERVED81 

XBARB2_IN81 input is reserved.

kXBARB2_InputDmaDone0 

DMA_DONE0 output assigned to XBARB2_IN82 input.

kXBARB2_InputDmaDone1 

DMA_DONE1 output assigned to XBARB2_IN83 input.

kXBARB2_InputDmaDone2 

DMA_DONE2 output assigned to XBARB2_IN84 input.

kXBARB2_InputDmaDone3 

DMA_DONE3 output assigned to XBARB2_IN85 input.

kXBARB2_InputDmaDone4 

DMA_DONE4 output assigned to XBARB2_IN86 input.

kXBARB2_InputDmaDone5 

DMA_DONE5 output assigned to XBARB2_IN87 input.

kXBARB2_InputDmaDone6 

DMA_DONE6 output assigned to XBARB2_IN88 input.

kXBARB2_InputDmaDone7 

DMA_DONE7 output assigned to XBARB2_IN89 input.

kXBARB2_InputDmaLpsrDone0 

DMA_LPSR_DONE0 output assigned to XBARB2_IN90 input.

kXBARB2_InputDmaLpsrDone1 

DMA_LPSR_DONE1 output assigned to XBARB2_IN91 input.

kXBARB2_InputDmaLpsrDone2 

DMA_LPSR_DONE2 output assigned to XBARB2_IN92 input.

kXBARB2_InputDmaLpsrDone3 

DMA_LPSR_DONE3 output assigned to XBARB2_IN93 input.

kXBARB2_InputDmaLpsrDone4 

DMA_LPSR_DONE4 output assigned to XBARB2_IN94 input.

kXBARB2_InputDmaLpsrDone5 

DMA_LPSR_DONE5 output assigned to XBARB2_IN95 input.

kXBARB2_InputDmaLpsrDone6 

DMA_LPSR_DONE6 output assigned to XBARB2_IN96 input.

kXBARB2_InputDmaLpsrDone7 

DMA_LPSR_DONE7 output assigned to XBARB2_IN97 input.

kXBARB3_InputLogicLow 

LOGIC_LOW output assigned to XBARB3_IN0 input.

kXBARB3_InputLogicHigh 

LOGIC_HIGH output assigned to XBARB3_IN1 input.

kXBARB3_InputAcmp1Out 

ACMP1_OUT output assigned to XBARB3_IN2 input.

kXBARB3_InputAcmp2Out 

ACMP2_OUT output assigned to XBARB3_IN3 input.

kXBARB3_InputAcmp3Out 

ACMP3_OUT output assigned to XBARB3_IN4 input.

kXBARB3_InputAcmp4Out 

ACMP4_OUT output assigned to XBARB3_IN5 input.

kXBARB3_InputRESERVED6 

XBARB3_IN6 input is reserved.

kXBARB3_InputRESERVED7 

XBARB3_IN7 input is reserved.

kXBARB3_InputRESERVED8 

XBARB3_IN8 input is reserved.

kXBARB3_InputRESERVED9 

XBARB3_IN9 input is reserved.

kXBARB3_InputQtimer1Timer0 

QTIMER1_TIMER0 output assigned to XBARB3_IN10 input.

kXBARB3_InputQtimer1Timer1 

QTIMER1_TIMER1 output assigned to XBARB3_IN11 input.

kXBARB3_InputQtimer1Timer2 

QTIMER1_TIMER2 output assigned to XBARB3_IN12 input.

kXBARB3_InputQtimer1Timer3 

QTIMER1_TIMER3 output assigned to XBARB3_IN13 input.

kXBARB3_InputQtimer2Timer0 

QTIMER2_TIMER0 output assigned to XBARB3_IN14 input.

kXBARB3_InputQtimer2Timer1 

QTIMER2_TIMER1 output assigned to XBARB3_IN15 input.

kXBARB3_InputQtimer2Timer2 

QTIMER2_TIMER2 output assigned to XBARB3_IN16 input.

kXBARB3_InputQtimer2Timer3 

QTIMER2_TIMER3 output assigned to XBARB3_IN17 input.

kXBARB3_InputQtimer3Timer0 

QTIMER3_TIMER0 output assigned to XBARB3_IN18 input.

kXBARB3_InputQtimer3Timer1 

QTIMER3_TIMER1 output assigned to XBARB3_IN19 input.

kXBARB3_InputQtimer3Timer2 

QTIMER3_TIMER2 output assigned to XBARB3_IN20 input.

kXBARB3_InputQtimer3Timer3 

QTIMER3_TIMER3 output assigned to XBARB3_IN21 input.

kXBARB3_InputQtimer4Timer0 

QTIMER4_TIMER0 output assigned to XBARB3_IN22 input.

kXBARB3_InputQtimer4Timer1 

QTIMER4_TIMER1 output assigned to XBARB3_IN23 input.

kXBARB3_InputQtimer4Timer2 

QTIMER4_TIMER2 output assigned to XBARB3_IN24 input.

kXBARB3_InputQtimer4Timer3 

QTIMER4_TIMER3 output assigned to XBARB3_IN25 input.

kXBARB3_InputRESERVED26 

XBARB3_IN26 input is reserved.

kXBARB3_InputRESERVED27 

XBARB3_IN27 input is reserved.

kXBARB3_InputRESERVED28 

XBARB3_IN28 input is reserved.

kXBARB3_InputRESERVED29 

XBARB3_IN29 input is reserved.

kXBARB3_InputRESERVED30 

XBARB3_IN30 input is reserved.

kXBARB3_InputRESERVED31 

XBARB3_IN31 input is reserved.

kXBARB3_InputRESERVED32 

XBARB3_IN32 input is reserved.

kXBARB3_InputRESERVED33 

XBARB3_IN33 input is reserved.

kXBARB3_InputFlexpwm1Pwm0OutTrig01 

FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN34 input.

kXBARB3_InputFlexpwm1Pwm1OutTrig01 

FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN35 input.

kXBARB3_InputFlexpwm1Pwm2OutTrig01 

FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN36 input.

kXBARB3_InputFlexpwm1Pwm3OutTrig01 

FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN37 input.

kXBARB3_InputFlexpwm2Pwm0OutTrig01 

FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN38 input.

kXBARB3_InputFlexpwm2Pwm1OutTrig01 

FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN39 input.

kXBARB3_InputFlexpwm2Pwm2OutTrig01 

FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN40 input.

kXBARB3_InputFlexpwm2Pwm3OutTrig01 

FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN41 input.

kXBARB3_InputFlexpwm3Pwm0OutTrig01 

FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN42 input.

kXBARB3_InputFlexpwm3Pwm1OutTrig01 

FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN43 input.

kXBARB3_InputFlexpwm3Pwm2OutTrig01 

FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN44 input.

kXBARB3_InputFlexpwm3Pwm3OutTrig01 

FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN45 input.

kXBARB3_InputFlexpwm4Pwm0OutTrig01 

FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN46 input.

kXBARB3_InputFlexpwm4Pwm1OutTrig01 

FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN47 input.

kXBARB3_InputFlexpwm4Pwm2OutTrig01 

FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN48 input.

kXBARB3_InputFlexpwm4Pwm3OutTrig01 

FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN49 input.

kXBARB3_InputRESERVED50 

XBARB3_IN50 input is reserved.

kXBARB3_InputRESERVED51 

XBARB3_IN51 input is reserved.

kXBARB3_InputRESERVED52 

XBARB3_IN52 input is reserved.

kXBARB3_InputRESERVED53 

XBARB3_IN53 input is reserved.

kXBARB3_InputRESERVED54 

XBARB3_IN54 input is reserved.

kXBARB3_InputRESERVED55 

XBARB3_IN55 input is reserved.

kXBARB3_InputRESERVED56 

XBARB3_IN56 input is reserved.

kXBARB3_InputRESERVED57 

XBARB3_IN57 input is reserved.

kXBARB3_InputPit1Trigger0 

PIT1_TRIGGER0 output assigned to XBARB3_IN58 input.

kXBARB3_InputPit1Trigger1 

PIT1_TRIGGER1 output assigned to XBARB3_IN59 input.

kXBARB3_InputAdcEtc0Coco0 

ADC_ETC0_COCO0 output assigned to XBARB3_IN60 input.

kXBARB3_InputAdcEtc0Coco1 

ADC_ETC0_COCO1 output assigned to XBARB3_IN61 input.

kXBARB3_InputAdcEtc0Coco2 

ADC_ETC0_COCO2 output assigned to XBARB3_IN62 input.

kXBARB3_InputAdcEtc0Coco3 

ADC_ETC0_COCO3 output assigned to XBARB3_IN63 input.

kXBARB3_InputAdcEtc1Coco0 

ADC_ETC1_COCO0 output assigned to XBARB3_IN64 input.

kXBARB3_InputAdcEtc1Coco1 

ADC_ETC1_COCO1 output assigned to XBARB3_IN65 input.

kXBARB3_InputAdcEtc1Coco2 

ADC_ETC1_COCO2 output assigned to XBARB3_IN66 input.

kXBARB3_InputAdcEtc1Coco3 

ADC_ETC1_COCO3 output assigned to XBARB3_IN67 input.

kXBARB3_InputRESERVED68 

XBARB3_IN68 input is reserved.

kXBARB3_InputRESERVED69 

XBARB3_IN69 input is reserved.

kXBARB3_InputRESERVED70 

XBARB3_IN70 input is reserved.

kXBARB3_InputRESERVED71 

XBARB3_IN71 input is reserved.

kXBARB3_InputRESERVED72 

XBARB3_IN72 input is reserved.

kXBARB3_InputRESERVED73 

XBARB3_IN73 input is reserved.

kXBARB3_InputRESERVED74 

XBARB3_IN74 input is reserved.

kXBARB3_InputRESERVED75 

XBARB3_IN75 input is reserved.

kXBARB3_InputDec1PosMatch 

DEC1_POS_MATCH output assigned to XBARB3_IN76 input.

kXBARB3_InputDec2PosMatch 

DEC2_POS_MATCH output assigned to XBARB3_IN77 input.

kXBARB3_InputDec3PosMatch 

DEC3_POS_MATCH output assigned to XBARB3_IN78 input.

kXBARB3_InputDec4PosMatch 

DEC4_POS_MATCH output assigned to XBARB3_IN79 input.

kXBARB3_InputRESERVED80 

XBARB3_IN80 input is reserved.

kXBARB3_InputRESERVED81 

XBARB3_IN81 input is reserved.

kXBARB3_InputDmaDone0 

DMA_DONE0 output assigned to XBARB3_IN82 input.

kXBARB3_InputDmaDone1 

DMA_DONE1 output assigned to XBARB3_IN83 input.

kXBARB3_InputDmaDone2 

DMA_DONE2 output assigned to XBARB3_IN84 input.

kXBARB3_InputDmaDone3 

DMA_DONE3 output assigned to XBARB3_IN85 input.

kXBARB3_InputDmaDone4 

DMA_DONE4 output assigned to XBARB3_IN86 input.

kXBARB3_InputDmaDone5 

DMA_DONE5 output assigned to XBARB3_IN87 input.

kXBARB3_InputDmaDone6 

DMA_DONE6 output assigned to XBARB3_IN88 input.

kXBARB3_InputDmaDone7 

DMA_DONE7 output assigned to XBARB3_IN89 input.

kXBARB3_InputDmaLpsrDone0 

DMA_LPSR_DONE0 output assigned to XBARB3_IN90 input.

kXBARB3_InputDmaLpsrDone1 

DMA_LPSR_DONE1 output assigned to XBARB3_IN91 input.

kXBARB3_InputDmaLpsrDone2 

DMA_LPSR_DONE2 output assigned to XBARB3_IN92 input.

kXBARB3_InputDmaLpsrDone3 

DMA_LPSR_DONE3 output assigned to XBARB3_IN93 input.

kXBARB3_InputDmaLpsrDone4 

DMA_LPSR_DONE4 output assigned to XBARB3_IN94 input.

kXBARB3_InputDmaLpsrDone5 

DMA_LPSR_DONE5 output assigned to XBARB3_IN95 input.

kXBARB3_InputDmaLpsrDone6 

DMA_LPSR_DONE6 output assigned to XBARB3_IN96 input.

kXBARB3_InputDmaLpsrDone7 

DMA_LPSR_DONE7 output assigned to XBARB3_IN97 input.

kXBARA1_InputLogicLow 

LOGIC_LOW output assigned to XBARA1_IN0 input.

kXBARA1_InputLogicHigh 

LOGIC_HIGH output assigned to XBARA1_IN1 input.

kXBARA1_InputRESERVED2 

XBARA1_IN2 input is reserved.

kXBARA1_InputRESERVED3 

XBARA1_IN3 input is reserved.

kXBARA1_InputIomuxXbarInout04 

IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input.

kXBARA1_InputIomuxXbarInout05 

IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input.

kXBARA1_InputIomuxXbarInout06 

IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input.

kXBARA1_InputIomuxXbarInout07 

IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input.

kXBARA1_InputIomuxXbarInout08 

IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input.

kXBARA1_InputIomuxXbarInout09 

IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input.

kXBARA1_InputIomuxXbarInout10 

IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input.

kXBARA1_InputIomuxXbarInout11 

IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input.

kXBARA1_InputIomuxXbarInout12 

IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input.

kXBARA1_InputIomuxXbarInout13 

IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input.

kXBARA1_InputIomuxXbarInout14 

IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input.

kXBARA1_InputIomuxXbarInout15 

IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input.

kXBARA1_InputIomuxXbarInout16 

IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input.

kXBARA1_InputIomuxXbarInout17 

IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input.

kXBARA1_InputIomuxXbarInout18 

IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input.

kXBARA1_InputIomuxXbarInout19 

IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input.

kXBARA1_InputIomuxXbarInout20 

IOMUX_XBAR_INOUT20 output assigned to XBARA1_IN20 input.

kXBARA1_InputIomuxXbarInout21 

IOMUX_XBAR_INOUT21 output assigned to XBARA1_IN21 input.

kXBARA1_InputIomuxXbarInout22 

IOMUX_XBAR_INOUT22 output assigned to XBARA1_IN22 input.

kXBARA1_InputIomuxXbarInout23 

IOMUX_XBAR_INOUT23 output assigned to XBARA1_IN23 input.

kXBARA1_InputIomuxXbarInout24 

IOMUX_XBAR_INOUT24 output assigned to XBARA1_IN24 input.

kXBARA1_InputIomuxXbarInout25 

IOMUX_XBAR_INOUT25 output assigned to XBARA1_IN25 input.

kXBARA1_InputIomuxXbarInout26 

IOMUX_XBAR_INOUT26 output assigned to XBARA1_IN26 input.

kXBARA1_InputIomuxXbarInout27 

IOMUX_XBAR_INOUT27 output assigned to XBARA1_IN27 input.

kXBARA1_InputIomuxXbarInout28 

IOMUX_XBAR_INOUT28 output assigned to XBARA1_IN28 input.

kXBARA1_InputIomuxXbarInout29 

IOMUX_XBAR_INOUT29 output assigned to XBARA1_IN29 input.

kXBARA1_InputIomuxXbarInout30 

IOMUX_XBAR_INOUT30 output assigned to XBARA1_IN30 input.

kXBARA1_InputIomuxXbarInout31 

IOMUX_XBAR_INOUT31 output assigned to XBARA1_IN31 input.

kXBARA1_InputIomuxXbarInout32 

IOMUX_XBAR_INOUT32 output assigned to XBARA1_IN32 input.

kXBARA1_InputIomuxXbarInout33 

IOMUX_XBAR_INOUT33 output assigned to XBARA1_IN33 input.

kXBARA1_InputIomuxXbarInout34 

IOMUX_XBAR_INOUT34 output assigned to XBARA1_IN34 input.

kXBARA1_InputIomuxXbarInout35 

IOMUX_XBAR_INOUT35 output assigned to XBARA1_IN35 input.

kXBARA1_InputIomuxXbarInout36 

IOMUX_XBAR_INOUT36 output assigned to XBARA1_IN36 input.

kXBARA1_InputIomuxXbarInout37 

IOMUX_XBAR_INOUT37 output assigned to XBARA1_IN37 input.

kXBARA1_InputIomuxXbarInout38 

IOMUX_XBAR_INOUT38 output assigned to XBARA1_IN38 input.

kXBARA1_InputIomuxXbarInout39 

IOMUX_XBAR_INOUT39 output assigned to XBARA1_IN39 input.

kXBARA1_InputIomuxXbarInout40 

IOMUX_XBAR_INOUT40 output assigned to XBARA1_IN40 input.

kXBARA1_InputRESERVED41 

XBARA1_IN41 input is reserved.

kXBARA1_InputAcmp1Out 

ACMP1_OUT output assigned to XBARA1_IN42 input.

kXBARA1_InputAcmp2Out 

ACMP2_OUT output assigned to XBARA1_IN43 input.

kXBARA1_InputAcmp3Out 

ACMP3_OUT output assigned to XBARA1_IN44 input.

kXBARA1_InputAcmp4Out 

ACMP4_OUT output assigned to XBARA1_IN45 input.

kXBARA1_InputRESERVED46 

XBARA1_IN46 input is reserved.

kXBARA1_InputRESERVED47 

XBARA1_IN47 input is reserved.

kXBARA1_InputRESERVED48 

XBARA1_IN48 input is reserved.

kXBARA1_InputRESERVED49 

XBARA1_IN49 input is reserved.

kXBARA1_InputQtimer1Timer0 

QTIMER1_TIMER0 output assigned to XBARA1_IN50 input.

kXBARA1_InputQtimer1Timer1 

QTIMER1_TIMER1 output assigned to XBARA1_IN51 input.

kXBARA1_InputQtimer1Timer2 

QTIMER1_TIMER2 output assigned to XBARA1_IN52 input.

kXBARA1_InputQtimer1Timer3 

QTIMER1_TIMER3 output assigned to XBARA1_IN53 input.

kXBARA1_InputQtimer2Timer0 

QTIMER2_TIMER0 output assigned to XBARA1_IN54 input.

kXBARA1_InputQtimer2Timer1 

QTIMER2_TIMER1 output assigned to XBARA1_IN55 input.

kXBARA1_InputQtimer2Timer2 

QTIMER2_TIMER2 output assigned to XBARA1_IN56 input.

kXBARA1_InputQtimer2Timer3 

QTIMER2_TIMER3 output assigned to XBARA1_IN57 input.

kXBARA1_InputQtimer3Timer0 

QTIMER3_TIMER0 output assigned to XBARA1_IN58 input.

kXBARA1_InputQtimer3Timer1 

QTIMER3_TIMER1 output assigned to XBARA1_IN59 input.

kXBARA1_InputQtimer3Timer2 

QTIMER3_TIMER2 output assigned to XBARA1_IN60 input.

kXBARA1_InputQtimer3Timer3 

QTIMER3_TIMER3 output assigned to XBARA1_IN61 input.

kXBARA1_InputQtimer4Timer0 

QTIMER4_TIMER0 output assigned to XBARA1_IN62 input.

kXBARA1_InputQtimer4Timer1 

QTIMER4_TIMER1 output assigned to XBARA1_IN63 input.

kXBARA1_InputQtimer4Timer2 

QTIMER4_TIMER2 output assigned to XBARA1_IN64 input.

kXBARA1_InputQtimer4Timer3 

QTIMER4_TIMER3 output assigned to XBARA1_IN65 input.

kXBARA1_InputRESERVED66 

XBARA1_IN66 input is reserved.

kXBARA1_InputRESERVED67 

XBARA1_IN67 input is reserved.

kXBARA1_InputRESERVED68 

XBARA1_IN68 input is reserved.

kXBARA1_InputRESERVED69 

XBARA1_IN69 input is reserved.

kXBARA1_InputRESERVED70 

XBARA1_IN70 input is reserved.

kXBARA1_InputRESERVED71 

XBARA1_IN71 input is reserved.

kXBARA1_InputRESERVED72 

XBARA1_IN72 input is reserved.

kXBARA1_InputRESERVED73 

XBARA1_IN73 input is reserved.

kXBARA1_InputFlexpwm1Pwm0OutTrig0 

FLEXPWM1_PWM0_OUT_TRIG0 output assigned to XBARA1_IN74 input.

kXBARA1_InputFlexpwm1Pwm0OutTrig1 

FLEXPWM1_PWM0_OUT_TRIG1 output assigned to XBARA1_IN75 input.

kXBARA1_InputFlexpwm1Pwm1OutTrig0 

FLEXPWM1_PWM1_OUT_TRIG0 output assigned to XBARA1_IN76 input.

kXBARA1_InputFlexpwm1Pwm1OutTrig1 

FLEXPWM1_PWM1_OUT_TRIG1 output assigned to XBARA1_IN77 input.

kXBARA1_InputFlexpwm1Pwm2OutTrig0 

FLEXPWM1_PWM2_OUT_TRIG0 output assigned to XBARA1_IN78 input.

kXBARA1_InputFlexpwm1Pwm2OutTrig1 

FLEXPWM1_PWM2_OUT_TRIG1 output assigned to XBARA1_IN79 input.

kXBARA1_InputFlexpwm1Pwm3OutTrig0 

FLEXPWM1_PWM3_OUT_TRIG0 output assigned to XBARA1_IN80 input.

kXBARA1_InputFlexpwm1Pwm3OutTrig1 

FLEXPWM1_PWM3_OUT_TRIG1 output assigned to XBARA1_IN81 input.

kXBARA1_InputFlexpwm2Pwm0OutTrig01 

FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN82 input.

kXBARA1_InputFlexpwm2Pwm1OutTrig01 

FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN83 input.

kXBARA1_InputFlexpwm2Pwm2OutTrig01 

FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN84 input.

kXBARA1_InputFlexpwm2Pwm3OutTrig01 

FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN85 input.

kXBARA1_InputFlexpwm3Pwm0OutTrig01 

FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN86 input.

kXBARA1_InputFlexpwm3Pwm1OutTrig01 

FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN87 input.

kXBARA1_InputFlexpwm3Pwm2OutTrig01 

FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN88 input.

kXBARA1_InputFlexpwm3Pwm3OutTrig01 

FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN89 input.

kXBARA1_InputFlexpwm4Pwm0OutTrig01 

FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN90 input.

kXBARA1_InputFlexpwm4Pwm1OutTrig01 

FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN91 input.

kXBARA1_InputFlexpwm4Pwm2OutTrig01 

FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN92 input.

kXBARA1_InputFlexpwm4Pwm3OutTrig01 

FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN93 input.

kXBARA1_InputRESERVED94 

XBARA1_IN94 input is reserved.

kXBARA1_InputRESERVED95 

XBARA1_IN95 input is reserved.

kXBARA1_InputRESERVED96 

XBARA1_IN96 input is reserved.

kXBARA1_InputRESERVED97 

XBARA1_IN97 input is reserved.

kXBARA1_InputRESERVED98 

XBARA1_IN98 input is reserved.

kXBARA1_InputRESERVED99 

XBARA1_IN99 input is reserved.

kXBARA1_InputRESERVED100 

XBARA1_IN100 input is reserved.

kXBARA1_InputRESERVED101 

XBARA1_IN101 input is reserved.

kXBARA1_InputPit1Trigger0 

PIT1_TRIGGER0 output assigned to XBARA1_IN102 input.

kXBARA1_InputPit1Trigger1 

PIT1_TRIGGER1 output assigned to XBARA1_IN103 input.

kXBARA1_InputPit1Trigger2 

PIT1_TRIGGER2 output assigned to XBARA1_IN104 input.

kXBARA1_InputPit1Trigger3 

PIT1_TRIGGER3 output assigned to XBARA1_IN105 input.

kXBARA1_InputDec1PosMatch 

DEC1_POS_MATCH output assigned to XBARA1_IN106 input.

kXBARA1_InputDec2PosMatch 

DEC2_POS_MATCH output assigned to XBARA1_IN107 input.

kXBARA1_InputDec3PosMatch 

DEC3_POS_MATCH output assigned to XBARA1_IN108 input.

kXBARA1_InputDec4PosMatch 

DEC4_POS_MATCH output assigned to XBARA1_IN109 input.

kXBARA1_InputRESERVED110 

XBARA1_IN110 input is reserved.

kXBARA1_InputRESERVED111 

XBARA1_IN111 input is reserved.

kXBARA1_InputDmaDone0 

DMA_DONE0 output assigned to XBARA1_IN112 input.

kXBARA1_InputDmaDone1 

DMA_DONE1 output assigned to XBARA1_IN113 input.

kXBARA1_InputDmaDone2 

DMA_DONE2 output assigned to XBARA1_IN114 input.

kXBARA1_InputDmaDone3 

DMA_DONE3 output assigned to XBARA1_IN115 input.

kXBARA1_InputDmaDone4 

DMA_DONE4 output assigned to XBARA1_IN116 input.

kXBARA1_InputDmaDone5 

DMA_DONE5 output assigned to XBARA1_IN117 input.

kXBARA1_InputDmaDone6 

DMA_DONE6 output assigned to XBARA1_IN118 input.

kXBARA1_InputDmaDone7 

DMA_DONE7 output assigned to XBARA1_IN119 input.

kXBARA1_InputDmaLpsrDone0 

DMA_LPSR_DONE0 output assigned to XBARA1_IN120 input.

kXBARA1_InputDmaLpsrDone1 

DMA_LPSR_DONE1 output assigned to XBARA1_IN121 input.

kXBARA1_InputDmaLpsrDone2 

DMA_LPSR_DONE2 output assigned to XBARA1_IN122 input.

kXBARA1_InputDmaLpsrDone3 

DMA_LPSR_DONE3 output assigned to XBARA1_IN123 input.

kXBARA1_InputDmaLpsrDone4 

DMA_LPSR_DONE4 output assigned to XBARA1_IN124 input.

kXBARA1_InputDmaLpsrDone5 

DMA_LPSR_DONE5 output assigned to XBARA1_IN125 input.

kXBARA1_InputDmaLpsrDone6 

DMA_LPSR_DONE6 output assigned to XBARA1_IN126 input.

kXBARA1_InputDmaLpsrDone7 

DMA_LPSR_DONE7 output assigned to XBARA1_IN127 input.

kXBARA1_InputAoi1Out0 

AOI1_OUT0 output assigned to XBARA1_IN128 input.

kXBARA1_InputAoi1Out1 

AOI1_OUT1 output assigned to XBARA1_IN129 input.

kXBARA1_InputAoi1Out2 

AOI1_OUT2 output assigned to XBARA1_IN130 input.

kXBARA1_InputAoi1Out3 

AOI1_OUT3 output assigned to XBARA1_IN131 input.

kXBARA1_InputAoi2Out0 

AOI2_OUT0 output assigned to XBARA1_IN132 input.

kXBARA1_InputAoi2Out1 

AOI2_OUT1 output assigned to XBARA1_IN133 input.

kXBARA1_InputAoi2Out2 

AOI2_OUT2 output assigned to XBARA1_IN134 input.

kXBARA1_InputAoi2Out3 

AOI2_OUT3 output assigned to XBARA1_IN135 input.

kXBARA1_InputAdcEtc0Coco0 

ADC_ETC0_COCO0 output assigned to XBARA1_IN136 input.

kXBARA1_InputAdcEtc0Coco1 

ADC_ETC0_COCO1 output assigned to XBARA1_IN137 input.

kXBARA1_InputAdcEtc0Coco2 

ADC_ETC0_COCO2 output assigned to XBARA1_IN138 input.

kXBARA1_InputAdcEtc0Coco3 

ADC_ETC0_COCO3 output assigned to XBARA1_IN139 input.

kXBARA1_InputAdcEtc1Coco0 

ADC_ETC1_COCO0 output assigned to XBARA1_IN140 input.

kXBARA1_InputAdcEtc1Coco1 

ADC_ETC1_COCO1 output assigned to XBARA1_IN141 input.

kXBARA1_InputAdcEtc1Coco2 

ADC_ETC1_COCO2 output assigned to XBARA1_IN142 input.

kXBARA1_InputAdcEtc1Coco3 

ADC_ETC1_COCO3 output assigned to XBARA1_IN143 input.

kXBARB2_InputLogicLow 

LOGIC_LOW output assigned to XBARB2_IN0 input.

kXBARB2_InputLogicHigh 

LOGIC_HIGH output assigned to XBARB2_IN1 input.

kXBARB2_InputAcmp1Out 

ACMP1_OUT output assigned to XBARB2_IN2 input.

kXBARB2_InputAcmp2Out 

ACMP2_OUT output assigned to XBARB2_IN3 input.

kXBARB2_InputAcmp3Out 

ACMP3_OUT output assigned to XBARB2_IN4 input.

kXBARB2_InputAcmp4Out 

ACMP4_OUT output assigned to XBARB2_IN5 input.

kXBARB2_InputRESERVED6 

XBARB2_IN6 input is reserved.

kXBARB2_InputRESERVED7 

XBARB2_IN7 input is reserved.

kXBARB2_InputRESERVED8 

XBARB2_IN8 input is reserved.

kXBARB2_InputRESERVED9 

XBARB2_IN9 input is reserved.

kXBARB2_InputQtimer1Timer0 

QTIMER1_TIMER0 output assigned to XBARB2_IN10 input.

kXBARB2_InputQtimer1Timer1 

QTIMER1_TIMER1 output assigned to XBARB2_IN11 input.

kXBARB2_InputQtimer1Timer2 

QTIMER1_TIMER2 output assigned to XBARB2_IN12 input.

kXBARB2_InputQtimer1Timer3 

QTIMER1_TIMER3 output assigned to XBARB2_IN13 input.

kXBARB2_InputQtimer2Timer0 

QTIMER2_TIMER0 output assigned to XBARB2_IN14 input.

kXBARB2_InputQtimer2Timer1 

QTIMER2_TIMER1 output assigned to XBARB2_IN15 input.

kXBARB2_InputQtimer2Timer2 

QTIMER2_TIMER2 output assigned to XBARB2_IN16 input.

kXBARB2_InputQtimer2Timer3 

QTIMER2_TIMER3 output assigned to XBARB2_IN17 input.

kXBARB2_InputQtimer3Timer0 

QTIMER3_TIMER0 output assigned to XBARB2_IN18 input.

kXBARB2_InputQtimer3Timer1 

QTIMER3_TIMER1 output assigned to XBARB2_IN19 input.

kXBARB2_InputQtimer3Timer2 

QTIMER3_TIMER2 output assigned to XBARB2_IN20 input.

kXBARB2_InputQtimer3Timer3 

QTIMER3_TIMER3 output assigned to XBARB2_IN21 input.

kXBARB2_InputQtimer4Timer0 

QTIMER4_TIMER0 output assigned to XBARB2_IN22 input.

kXBARB2_InputQtimer4Timer1 

QTIMER4_TIMER1 output assigned to XBARB2_IN23 input.

kXBARB2_InputQtimer4Timer2 

QTIMER4_TIMER2 output assigned to XBARB2_IN24 input.

kXBARB2_InputQtimer4Timer3 

QTIMER4_TIMER3 output assigned to XBARB2_IN25 input.

kXBARB2_InputRESERVED26 

XBARB2_IN26 input is reserved.

kXBARB2_InputRESERVED27 

XBARB2_IN27 input is reserved.

kXBARB2_InputRESERVED28 

XBARB2_IN28 input is reserved.

kXBARB2_InputRESERVED29 

XBARB2_IN29 input is reserved.

kXBARB2_InputRESERVED30 

XBARB2_IN30 input is reserved.

kXBARB2_InputRESERVED31 

XBARB2_IN31 input is reserved.

kXBARB2_InputRESERVED32 

XBARB2_IN32 input is reserved.

kXBARB2_InputRESERVED33 

XBARB2_IN33 input is reserved.

kXBARB2_InputFlexpwm1Pwm0OutTrig01 

FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN34 input.

kXBARB2_InputFlexpwm1Pwm1OutTrig01 

FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN35 input.

kXBARB2_InputFlexpwm1Pwm2OutTrig01 

FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN36 input.

kXBARB2_InputFlexpwm1Pwm3OutTrig01 

FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN37 input.

kXBARB2_InputFlexpwm2Pwm0OutTrig01 

FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN38 input.

kXBARB2_InputFlexpwm2Pwm1OutTrig01 

FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN39 input.

kXBARB2_InputFlexpwm2Pwm2OutTrig01 

FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN40 input.

kXBARB2_InputFlexpwm2Pwm3OutTrig01 

FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN41 input.

kXBARB2_InputFlexpwm3Pwm0OutTrig01 

FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN42 input.

kXBARB2_InputFlexpwm3Pwm1OutTrig01 

FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN43 input.

kXBARB2_InputFlexpwm3Pwm2OutTrig01 

FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN44 input.

kXBARB2_InputFlexpwm3Pwm3OutTrig01 

FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN45 input.

kXBARB2_InputFlexpwm4Pwm0OutTrig01 

FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN46 input.

kXBARB2_InputFlexpwm4Pwm1OutTrig01 

FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN47 input.

kXBARB2_InputFlexpwm4Pwm2OutTrig01 

FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN48 input.

kXBARB2_InputFlexpwm4Pwm3OutTrig01 

FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN49 input.

kXBARB2_InputRESERVED50 

XBARB2_IN50 input is reserved.

kXBARB2_InputRESERVED51 

XBARB2_IN51 input is reserved.

kXBARB2_InputRESERVED52 

XBARB2_IN52 input is reserved.

kXBARB2_InputRESERVED53 

XBARB2_IN53 input is reserved.

kXBARB2_InputRESERVED54 

XBARB2_IN54 input is reserved.

kXBARB2_InputRESERVED55 

XBARB2_IN55 input is reserved.

kXBARB2_InputRESERVED56 

XBARB2_IN56 input is reserved.

kXBARB2_InputRESERVED57 

XBARB2_IN57 input is reserved.

kXBARB2_InputPit1Trigger0 

PIT1_TRIGGER0 output assigned to XBARB2_IN58 input.

kXBARB2_InputPit1Trigger1 

PIT1_TRIGGER1 output assigned to XBARB2_IN59 input.

kXBARB2_InputAdcEtc0Coco0 

ADC_ETC0_COCO0 output assigned to XBARB2_IN60 input.

kXBARB2_InputAdcEtc0Coco1 

ADC_ETC0_COCO1 output assigned to XBARB2_IN61 input.

kXBARB2_InputAdcEtc0Coco2 

ADC_ETC0_COCO2 output assigned to XBARB2_IN62 input.

kXBARB2_InputAdcEtc0Coco3 

ADC_ETC0_COCO3 output assigned to XBARB2_IN63 input.

kXBARB2_InputAdcEtc1Coco0 

ADC_ETC1_COCO0 output assigned to XBARB2_IN64 input.

kXBARB2_InputAdcEtc1Coco1 

ADC_ETC1_COCO1 output assigned to XBARB2_IN65 input.

kXBARB2_InputAdcEtc1Coco2 

ADC_ETC1_COCO2 output assigned to XBARB2_IN66 input.

kXBARB2_InputAdcEtc1Coco3 

ADC_ETC1_COCO3 output assigned to XBARB2_IN67 input.

kXBARB2_InputRESERVED68 

XBARB2_IN68 input is reserved.

kXBARB2_InputRESERVED69 

XBARB2_IN69 input is reserved.

kXBARB2_InputRESERVED70 

XBARB2_IN70 input is reserved.

kXBARB2_InputRESERVED71 

XBARB2_IN71 input is reserved.

kXBARB2_InputRESERVED72 

XBARB2_IN72 input is reserved.

kXBARB2_InputRESERVED73 

XBARB2_IN73 input is reserved.

kXBARB2_InputRESERVED74 

XBARB2_IN74 input is reserved.

kXBARB2_InputRESERVED75 

XBARB2_IN75 input is reserved.

kXBARB2_InputDec1PosMatch 

DEC1_POS_MATCH output assigned to XBARB2_IN76 input.

kXBARB2_InputDec2PosMatch 

DEC2_POS_MATCH output assigned to XBARB2_IN77 input.

kXBARB2_InputDec3PosMatch 

DEC3_POS_MATCH output assigned to XBARB2_IN78 input.

kXBARB2_InputDec4PosMatch 

DEC4_POS_MATCH output assigned to XBARB2_IN79 input.

kXBARB2_InputRESERVED80 

XBARB2_IN80 input is reserved.

kXBARB2_InputRESERVED81 

XBARB2_IN81 input is reserved.

kXBARB2_InputDmaDone0 

DMA_DONE0 output assigned to XBARB2_IN82 input.

kXBARB2_InputDmaDone1 

DMA_DONE1 output assigned to XBARB2_IN83 input.

kXBARB2_InputDmaDone2 

DMA_DONE2 output assigned to XBARB2_IN84 input.

kXBARB2_InputDmaDone3 

DMA_DONE3 output assigned to XBARB2_IN85 input.

kXBARB2_InputDmaDone4 

DMA_DONE4 output assigned to XBARB2_IN86 input.

kXBARB2_InputDmaDone5 

DMA_DONE5 output assigned to XBARB2_IN87 input.

kXBARB2_InputDmaDone6 

DMA_DONE6 output assigned to XBARB2_IN88 input.

kXBARB2_InputDmaDone7 

DMA_DONE7 output assigned to XBARB2_IN89 input.

kXBARB2_InputDmaLpsrDone0 

DMA_LPSR_DONE0 output assigned to XBARB2_IN90 input.

kXBARB2_InputDmaLpsrDone1 

DMA_LPSR_DONE1 output assigned to XBARB2_IN91 input.

kXBARB2_InputDmaLpsrDone2 

DMA_LPSR_DONE2 output assigned to XBARB2_IN92 input.

kXBARB2_InputDmaLpsrDone3 

DMA_LPSR_DONE3 output assigned to XBARB2_IN93 input.

kXBARB2_InputDmaLpsrDone4 

DMA_LPSR_DONE4 output assigned to XBARB2_IN94 input.

kXBARB2_InputDmaLpsrDone5 

DMA_LPSR_DONE5 output assigned to XBARB2_IN95 input.

kXBARB2_InputDmaLpsrDone6 

DMA_LPSR_DONE6 output assigned to XBARB2_IN96 input.

kXBARB2_InputDmaLpsrDone7 

DMA_LPSR_DONE7 output assigned to XBARB2_IN97 input.

kXBARB3_InputLogicLow 

LOGIC_LOW output assigned to XBARB3_IN0 input.

kXBARB3_InputLogicHigh 

LOGIC_HIGH output assigned to XBARB3_IN1 input.

kXBARB3_InputAcmp1Out 

ACMP1_OUT output assigned to XBARB3_IN2 input.

kXBARB3_InputAcmp2Out 

ACMP2_OUT output assigned to XBARB3_IN3 input.

kXBARB3_InputAcmp3Out 

ACMP3_OUT output assigned to XBARB3_IN4 input.

kXBARB3_InputAcmp4Out 

ACMP4_OUT output assigned to XBARB3_IN5 input.

kXBARB3_InputRESERVED6 

XBARB3_IN6 input is reserved.

kXBARB3_InputRESERVED7 

XBARB3_IN7 input is reserved.

kXBARB3_InputRESERVED8 

XBARB3_IN8 input is reserved.

kXBARB3_InputRESERVED9 

XBARB3_IN9 input is reserved.

kXBARB3_InputQtimer1Timer0 

QTIMER1_TIMER0 output assigned to XBARB3_IN10 input.

kXBARB3_InputQtimer1Timer1 

QTIMER1_TIMER1 output assigned to XBARB3_IN11 input.

kXBARB3_InputQtimer1Timer2 

QTIMER1_TIMER2 output assigned to XBARB3_IN12 input.

kXBARB3_InputQtimer1Timer3 

QTIMER1_TIMER3 output assigned to XBARB3_IN13 input.

kXBARB3_InputQtimer2Timer0 

QTIMER2_TIMER0 output assigned to XBARB3_IN14 input.

kXBARB3_InputQtimer2Timer1 

QTIMER2_TIMER1 output assigned to XBARB3_IN15 input.

kXBARB3_InputQtimer2Timer2 

QTIMER2_TIMER2 output assigned to XBARB3_IN16 input.

kXBARB3_InputQtimer2Timer3 

QTIMER2_TIMER3 output assigned to XBARB3_IN17 input.

kXBARB3_InputQtimer3Timer0 

QTIMER3_TIMER0 output assigned to XBARB3_IN18 input.

kXBARB3_InputQtimer3Timer1 

QTIMER3_TIMER1 output assigned to XBARB3_IN19 input.

kXBARB3_InputQtimer3Timer2 

QTIMER3_TIMER2 output assigned to XBARB3_IN20 input.

kXBARB3_InputQtimer3Timer3 

QTIMER3_TIMER3 output assigned to XBARB3_IN21 input.

kXBARB3_InputQtimer4Timer0 

QTIMER4_TIMER0 output assigned to XBARB3_IN22 input.

kXBARB3_InputQtimer4Timer1 

QTIMER4_TIMER1 output assigned to XBARB3_IN23 input.

kXBARB3_InputQtimer4Timer2 

QTIMER4_TIMER2 output assigned to XBARB3_IN24 input.

kXBARB3_InputQtimer4Timer3 

QTIMER4_TIMER3 output assigned to XBARB3_IN25 input.

kXBARB3_InputRESERVED26 

XBARB3_IN26 input is reserved.

kXBARB3_InputRESERVED27 

XBARB3_IN27 input is reserved.

kXBARB3_InputRESERVED28 

XBARB3_IN28 input is reserved.

kXBARB3_InputRESERVED29 

XBARB3_IN29 input is reserved.

kXBARB3_InputRESERVED30 

XBARB3_IN30 input is reserved.

kXBARB3_InputRESERVED31 

XBARB3_IN31 input is reserved.

kXBARB3_InputRESERVED32 

XBARB3_IN32 input is reserved.

kXBARB3_InputRESERVED33 

XBARB3_IN33 input is reserved.

kXBARB3_InputFlexpwm1Pwm0OutTrig01 

FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN34 input.

kXBARB3_InputFlexpwm1Pwm1OutTrig01 

FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN35 input.

kXBARB3_InputFlexpwm1Pwm2OutTrig01 

FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN36 input.

kXBARB3_InputFlexpwm1Pwm3OutTrig01 

FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN37 input.

kXBARB3_InputFlexpwm2Pwm0OutTrig01 

FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN38 input.

kXBARB3_InputFlexpwm2Pwm1OutTrig01 

FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN39 input.

kXBARB3_InputFlexpwm2Pwm2OutTrig01 

FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN40 input.

kXBARB3_InputFlexpwm2Pwm3OutTrig01 

FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN41 input.

kXBARB3_InputFlexpwm3Pwm0OutTrig01 

FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN42 input.

kXBARB3_InputFlexpwm3Pwm1OutTrig01 

FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN43 input.

kXBARB3_InputFlexpwm3Pwm2OutTrig01 

FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN44 input.

kXBARB3_InputFlexpwm3Pwm3OutTrig01 

FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN45 input.

kXBARB3_InputFlexpwm4Pwm0OutTrig01 

FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN46 input.

kXBARB3_InputFlexpwm4Pwm1OutTrig01 

FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN47 input.

kXBARB3_InputFlexpwm4Pwm2OutTrig01 

FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN48 input.

kXBARB3_InputFlexpwm4Pwm3OutTrig01 

FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN49 input.

kXBARB3_InputRESERVED50 

XBARB3_IN50 input is reserved.

kXBARB3_InputRESERVED51 

XBARB3_IN51 input is reserved.

kXBARB3_InputRESERVED52 

XBARB3_IN52 input is reserved.

kXBARB3_InputRESERVED53 

XBARB3_IN53 input is reserved.

kXBARB3_InputRESERVED54 

XBARB3_IN54 input is reserved.

kXBARB3_InputRESERVED55 

XBARB3_IN55 input is reserved.

kXBARB3_InputRESERVED56 

XBARB3_IN56 input is reserved.

kXBARB3_InputRESERVED57 

XBARB3_IN57 input is reserved.

kXBARB3_InputPit1Trigger0 

PIT1_TRIGGER0 output assigned to XBARB3_IN58 input.

kXBARB3_InputPit1Trigger1 

PIT1_TRIGGER1 output assigned to XBARB3_IN59 input.

kXBARB3_InputAdcEtc0Coco0 

ADC_ETC0_COCO0 output assigned to XBARB3_IN60 input.

kXBARB3_InputAdcEtc0Coco1 

ADC_ETC0_COCO1 output assigned to XBARB3_IN61 input.

kXBARB3_InputAdcEtc0Coco2 

ADC_ETC0_COCO2 output assigned to XBARB3_IN62 input.

kXBARB3_InputAdcEtc0Coco3 

ADC_ETC0_COCO3 output assigned to XBARB3_IN63 input.

kXBARB3_InputAdcEtc1Coco0 

ADC_ETC1_COCO0 output assigned to XBARB3_IN64 input.

kXBARB3_InputAdcEtc1Coco1 

ADC_ETC1_COCO1 output assigned to XBARB3_IN65 input.

kXBARB3_InputAdcEtc1Coco2 

ADC_ETC1_COCO2 output assigned to XBARB3_IN66 input.

kXBARB3_InputAdcEtc1Coco3 

ADC_ETC1_COCO3 output assigned to XBARB3_IN67 input.

kXBARB3_InputRESERVED68 

XBARB3_IN68 input is reserved.

kXBARB3_InputRESERVED69 

XBARB3_IN69 input is reserved.

kXBARB3_InputRESERVED70 

XBARB3_IN70 input is reserved.

kXBARB3_InputRESERVED71 

XBARB3_IN71 input is reserved.

kXBARB3_InputRESERVED72 

XBARB3_IN72 input is reserved.

kXBARB3_InputRESERVED73 

XBARB3_IN73 input is reserved.

kXBARB3_InputRESERVED74 

XBARB3_IN74 input is reserved.

kXBARB3_InputRESERVED75 

XBARB3_IN75 input is reserved.

kXBARB3_InputDec1PosMatch 

DEC1_POS_MATCH output assigned to XBARB3_IN76 input.

kXBARB3_InputDec2PosMatch 

DEC2_POS_MATCH output assigned to XBARB3_IN77 input.

kXBARB3_InputDec3PosMatch 

DEC3_POS_MATCH output assigned to XBARB3_IN78 input.

kXBARB3_InputDec4PosMatch 

DEC4_POS_MATCH output assigned to XBARB3_IN79 input.

kXBARB3_InputRESERVED80 

XBARB3_IN80 input is reserved.

kXBARB3_InputRESERVED81 

XBARB3_IN81 input is reserved.

kXBARB3_InputDmaDone0 

DMA_DONE0 output assigned to XBARB3_IN82 input.

kXBARB3_InputDmaDone1 

DMA_DONE1 output assigned to XBARB3_IN83 input.

kXBARB3_InputDmaDone2 

DMA_DONE2 output assigned to XBARB3_IN84 input.

kXBARB3_InputDmaDone3 

DMA_DONE3 output assigned to XBARB3_IN85 input.

kXBARB3_InputDmaDone4 

DMA_DONE4 output assigned to XBARB3_IN86 input.

kXBARB3_InputDmaDone5 

DMA_DONE5 output assigned to XBARB3_IN87 input.

kXBARB3_InputDmaDone6 

DMA_DONE6 output assigned to XBARB3_IN88 input.

kXBARB3_InputDmaDone7 

DMA_DONE7 output assigned to XBARB3_IN89 input.

kXBARB3_InputDmaLpsrDone0 

DMA_LPSR_DONE0 output assigned to XBARB3_IN90 input.

kXBARB3_InputDmaLpsrDone1 

DMA_LPSR_DONE1 output assigned to XBARB3_IN91 input.

kXBARB3_InputDmaLpsrDone2 

DMA_LPSR_DONE2 output assigned to XBARB3_IN92 input.

kXBARB3_InputDmaLpsrDone3 

DMA_LPSR_DONE3 output assigned to XBARB3_IN93 input.

kXBARB3_InputDmaLpsrDone4 

DMA_LPSR_DONE4 output assigned to XBARB3_IN94 input.

kXBARB3_InputDmaLpsrDone5 

DMA_LPSR_DONE5 output assigned to XBARB3_IN95 input.

kXBARB3_InputDmaLpsrDone6 

DMA_LPSR_DONE6 output assigned to XBARB3_IN96 input.

kXBARB3_InputDmaLpsrDone7 

DMA_LPSR_DONE7 output assigned to XBARB3_IN97 input.

◆ _xbar_output_signal

enum _xbar_output_signal
Enumerator
kXBARA1_OutputDmaChMuxReq30 

XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30

kXBARA1_OutputDmaChMuxReq31 

XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31

kXBARA1_OutputDmaChMuxReq94 

XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94

kXBARA1_OutputDmaChMuxReq95 

XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95

kXBARA1_OutputIomuxXbarInout04 

XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04

kXBARA1_OutputIomuxXbarInout05 

XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05

kXBARA1_OutputIomuxXbarInout06 

XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06

kXBARA1_OutputIomuxXbarInout07 

XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07

kXBARA1_OutputIomuxXbarInout08 

XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08

kXBARA1_OutputIomuxXbarInout09 

XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09

kXBARA1_OutputIomuxXbarInout10 

XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10

kXBARA1_OutputIomuxXbarInout11 

XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11

kXBARA1_OutputIomuxXbarInout12 

XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12

kXBARA1_OutputIomuxXbarInout13 

XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13

kXBARA1_OutputIomuxXbarInout14 

XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14

kXBARA1_OutputIomuxXbarInout15 

XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15

kXBARA1_OutputIomuxXbarInout16 

XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16

kXBARA1_OutputIomuxXbarInout17 

XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17

kXBARA1_OutputIomuxXbarInout18 

XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18

kXBARA1_OutputIomuxXbarInout19 

XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19

kXBARA1_OutputAcmp1Sample 

XBARA1_OUT20 output assigned to ACMP1_SAMPLE

kXBARA1_OutputAcmp2Sample 

XBARA1_OUT21 output assigned to ACMP2_SAMPLE

kXBARA1_OutputAcmp3Sample 

XBARA1_OUT22 output assigned to ACMP3_SAMPLE

kXBARA1_OutputAcmp4Sample 

XBARA1_OUT23 output assigned to ACMP4_SAMPLE

kXBARA1_OutputRESERVED24 

XBARA1_OUT24 output is reserved.

kXBARA1_OutputRESERVED25 

XBARA1_OUT25 output is reserved.

kXBARA1_OutputFlexpwm1Exta0 

XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0

kXBARA1_OutputFlexpwm1Exta1 

XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1

kXBARA1_OutputFlexpwm1Exta2 

XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2

kXBARA1_OutputFlexpwm1Exta3 

XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3

kXBARA1_OutputFlexpwm1ExtSync0 

XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0

kXBARA1_OutputFlexpwm1ExtSync1 

XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1

kXBARA1_OutputFlexpwm1ExtSync2 

XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2

kXBARA1_OutputFlexpwm1ExtSync3 

XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3

kXBARA1_OutputFlexpwm1ExtClk 

XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK

kXBARA1_OutputFlexpwm1Fault0 

XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0

kXBARA1_OutputFlexpwm1Fault1 

XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1

kXBARA1_OutputFlexpwm1234Fault2 

XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2

kXBARA1_OutputFlexpwm1234Fault3 

XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3

kXBARA1_OutputFlexpwm1ExtForce 

XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE

kXBARA1_OutputFlexpwm234Exta0 

XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0

kXBARA1_OutputFlexpwm234Exta1 

XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1

kXBARA1_OutputFlexpwm234Exta2 

XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2

kXBARA1_OutputFlexpwm234Exta3 

XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3

kXBARA1_OutputFlexpwm2ExtSync0 

XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0

kXBARA1_OutputFlexpwm2ExtSync1 

XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1

kXBARA1_OutputFlexpwm2ExtSync2 

XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2

kXBARA1_OutputFlexpwm2ExtSync3 

XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3

kXBARA1_OutputFlexpwm234ExtClk 

XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK

kXBARA1_OutputFlexpwm2Fault0 

XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0

kXBARA1_OutputFlexpwm2Fault1 

XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1

kXBARA1_OutputFlexpwm2ExtForce 

XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE

kXBARA1_OutputFlexpwm3ExtSync0 

XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0

kXBARA1_OutputFlexpwm3ExtSync1 

XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1

kXBARA1_OutputFlexpwm3ExtSync2 

XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2

kXBARA1_OutputFlexpwm3ExtSync3 

XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3

kXBARA1_OutputFlexpwm3Fault0 

XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0

kXBARA1_OutputFlexpwm3Fault1 

XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1

kXBARA1_OutputFlexpwm3ExtForce 

XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE

kXBARA1_OutputFlexpwm4ExtSync0 

XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0

kXBARA1_OutputFlexpwm4ExtSync1 

XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1

kXBARA1_OutputFlexpwm4ExtSync2 

XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2

kXBARA1_OutputFlexpwm4ExtSync3 

XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3

kXBARA1_OutputFlexpwm4Fault0 

XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0

kXBARA1_OutputFlexpwm4Fault1 

XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1

kXBARA1_OutputFlexpwm4ExtForce 

XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE

kXBARA1_OutputEnc1PhaseAInput 

XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT

kXBARA1_OutputEnc1PhaseBInput 

XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT

kXBARA1_OutputEnc1Index 

XBARA1_OUT68 output assigned to ENC1_INDEX

kXBARA1_OutputEnc1Home 

XBARA1_OUT69 output assigned to ENC1_HOME

kXBARA1_OutputEnc1Trigger 

XBARA1_OUT70 output assigned to ENC1_TRIGGER

kXBARA1_OutputEnc2PhaseAInput 

XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT

kXBARA1_OutputEnc2PhaseBInput 

XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT

kXBARA1_OutputEnc2Index 

XBARA1_OUT73 output assigned to ENC2_INDEX

kXBARA1_OutputEnc2Home 

XBARA1_OUT74 output assigned to ENC2_HOME

kXBARA1_OutputEnc2Trigger 

XBARA1_OUT75 output assigned to ENC2_TRIGGER

kXBARA1_OutputEnc3PhaseAInput 

XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT

kXBARA1_OutputEnc3PhaseBInput 

XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT

kXBARA1_OutputEnc3Index 

XBARA1_OUT78 output assigned to ENC3_INDEX

kXBARA1_OutputEnc3Home 

XBARA1_OUT79 output assigned to ENC3_HOME

kXBARA1_OutputEnc3Trigger 

XBARA1_OUT80 output assigned to ENC3_TRIGGER

kXBARA1_OutputEnc4PhaseAInput 

XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT

kXBARA1_OutputEnc4PhaseBInput 

XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT

kXBARA1_OutputEnc4Index 

XBARA1_OUT83 output assigned to ENC4_INDEX

kXBARA1_OutputEnc4Home 

XBARA1_OUT84 output assigned to ENC4_HOME

kXBARA1_OutputEnc4Trigger 

XBARA1_OUT85 output assigned to ENC4_TRIGGER

kXBARA1_OutputQtimer1Tmr0Input 

XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT

kXBARA1_OutputQtimer1Tmr1Input 

XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT

kXBARA1_OutputQtimer1Tmr2Input 

XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT

kXBARA1_OutputQtimer1Tmr3Input 

XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT

kXBARA1_OutputQtimer2Tmr0Input 

XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT

kXBARA1_OutputQtimer2Tmr1Input 

XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT

kXBARA1_OutputQtimer2Tmr2Input 

XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT

kXBARA1_OutputQtimer2Tmr3Input 

XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT

kXBARA1_OutputQtimer3Tmr0Input 

XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT

kXBARA1_OutputQtimer3Tmr1Input 

XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT

kXBARA1_OutputQtimer3Tmr2Input 

XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT

kXBARA1_OutputQtimer3Tmr3Input 

XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT

kXBARA1_OutputQtimer4Tmr0Input 

XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT

kXBARA1_OutputQtimer4Tmr1Input 

XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT

kXBARA1_OutputQtimer4Tmr2Input 

XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT

kXBARA1_OutputQtimer4Tmr3Input 

XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT

kXBARA1_OutputEwmEwmIn 

XBARA1_OUT102 output assigned to EWM_EWM_IN

kXBARA1_OutputAdcEtcXbar0Trig0 

XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0

kXBARA1_OutputAdcEtcXbar0Trig1 

XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1

kXBARA1_OutputAdcEtcXbar0Trig2 

XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2

kXBARA1_OutputAdcEtcXbar0Trig3 

XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3

kXBARA1_OutputAdcEtcXbar1Trig0 

XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0

kXBARA1_OutputAdcEtcXbar1Trig1 

XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1

kXBARA1_OutputAdcEtcXbar1Trig2 

XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2

kXBARA1_OutputAdcEtcXbar1Trig3 

XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3

kXBARA1_OutputLpi2c1TrgInput 

XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT

kXBARA1_OutputLpi2c2TrgInput 

XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT

kXBARA1_OutputLpi2c3TrgInput 

XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT

kXBARA1_OutputLpi2c4TrgInput 

XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT

kXBARA1_OutputLpspi1TrgInput 

XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT

kXBARA1_OutputLpspi2TrgInput 

XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT

kXBARA1_OutputLpspi3TrgInput 

XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT

kXBARA1_OutputLpspi4TrgInput 

XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT

kXBARA1_OutputLpuart1TrgInput 

XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT

kXBARA1_OutputLpuart2TrgInput 

XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT

kXBARA1_OutputLpuart3TrgInput 

XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT

kXBARA1_OutputLpuart4TrgInput 

XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT

kXBARA1_OutputLpuart5TrgInput 

XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT

kXBARA1_OutputLpuart6TrgInput 

XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT

kXBARA1_OutputLpuart7TrgInput 

XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT

kXBARA1_OutputLpuart8TrgInput 

XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT

kXBARA1_OutputFlexio1TriggerIn0 

XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0

kXBARA1_OutputFlexio1TriggerIn1 

XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1

kXBARA1_OutputFlexio2TriggerIn0 

XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0

kXBARA1_OutputFlexio2TriggerIn1 

XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1

kXBARB2_OutputAoi1In00 

XBARB2_OUT0 output assigned to AOI1_IN00

kXBARB2_OutputAoi1In01 

XBARB2_OUT1 output assigned to AOI1_IN01

kXBARB2_OutputAoi1In02 

XBARB2_OUT2 output assigned to AOI1_IN02

kXBARB2_OutputAoi1In03 

XBARB2_OUT3 output assigned to AOI1_IN03

kXBARB2_OutputAoi1In04 

XBARB2_OUT4 output assigned to AOI1_IN04

kXBARB2_OutputAoi1In05 

XBARB2_OUT5 output assigned to AOI1_IN05

kXBARB2_OutputAoi1In06 

XBARB2_OUT6 output assigned to AOI1_IN06

kXBARB2_OutputAoi1In07 

XBARB2_OUT7 output assigned to AOI1_IN07

kXBARB2_OutputAoi1In08 

XBARB2_OUT8 output assigned to AOI1_IN08

kXBARB2_OutputAoi1In09 

XBARB2_OUT9 output assigned to AOI1_IN09

kXBARB2_OutputAoi1In10 

XBARB2_OUT10 output assigned to AOI1_IN10

kXBARB2_OutputAoi1In11 

XBARB2_OUT11 output assigned to AOI1_IN11

kXBARB2_OutputAoi1In12 

XBARB2_OUT12 output assigned to AOI1_IN12

kXBARB2_OutputAoi1In13 

XBARB2_OUT13 output assigned to AOI1_IN13

kXBARB2_OutputAoi1In14 

XBARB2_OUT14 output assigned to AOI1_IN14

kXBARB2_OutputAoi1In15 

XBARB2_OUT15 output assigned to AOI1_IN15

kXBARB3_OutputAoi2In00 

XBARB3_OUT0 output assigned to AOI2_IN00

kXBARB3_OutputAoi2In01 

XBARB3_OUT1 output assigned to AOI2_IN01

kXBARB3_OutputAoi2In02 

XBARB3_OUT2 output assigned to AOI2_IN02

kXBARB3_OutputAoi2In03 

XBARB3_OUT3 output assigned to AOI2_IN03

kXBARB3_OutputAoi2In04 

XBARB3_OUT4 output assigned to AOI2_IN04

kXBARB3_OutputAoi2In05 

XBARB3_OUT5 output assigned to AOI2_IN05

kXBARB3_OutputAoi2In06 

XBARB3_OUT6 output assigned to AOI2_IN06

kXBARB3_OutputAoi2In07 

XBARB3_OUT7 output assigned to AOI2_IN07

kXBARB3_OutputAoi2In08 

XBARB3_OUT8 output assigned to AOI2_IN08

kXBARB3_OutputAoi2In09 

XBARB3_OUT9 output assigned to AOI2_IN09

kXBARB3_OutputAoi2In10 

XBARB3_OUT10 output assigned to AOI2_IN10

kXBARB3_OutputAoi2In11 

XBARB3_OUT11 output assigned to AOI2_IN11

kXBARB3_OutputAoi2In12 

XBARB3_OUT12 output assigned to AOI2_IN12

kXBARB3_OutputAoi2In13 

XBARB3_OUT13 output assigned to AOI2_IN13

kXBARB3_OutputAoi2In14 

XBARB3_OUT14 output assigned to AOI2_IN14

kXBARB3_OutputAoi2In15 

XBARB3_OUT15 output assigned to AOI2_IN15

kXBARA1_OutputDmaChMuxReq81 

XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ81

kXBARA1_OutputDmaChMuxReq82 

XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ82

kXBARA1_OutputDmaChMuxReq83 

XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ83

kXBARA1_OutputDmaChMuxReq84 

XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ84

kXBARA1_OutputIomuxXbarInout04 

XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04

kXBARA1_OutputIomuxXbarInout05 

XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05

kXBARA1_OutputIomuxXbarInout06 

XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06

kXBARA1_OutputIomuxXbarInout07 

XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07

kXBARA1_OutputIomuxXbarInout08 

XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08

kXBARA1_OutputIomuxXbarInout09 

XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09

kXBARA1_OutputIomuxXbarInout10 

XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10

kXBARA1_OutputIomuxXbarInout11 

XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11

kXBARA1_OutputIomuxXbarInout12 

XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12

kXBARA1_OutputIomuxXbarInout13 

XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13

kXBARA1_OutputIomuxXbarInout14 

XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14

kXBARA1_OutputIomuxXbarInout15 

XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15

kXBARA1_OutputIomuxXbarInout16 

XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16

kXBARA1_OutputIomuxXbarInout17 

XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17

kXBARA1_OutputIomuxXbarInout18 

XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18

kXBARA1_OutputIomuxXbarInout19 

XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19

kXBARA1_OutputIomuxXbarInout20 

XBARA1_OUT20 output assigned to IOMUX_XBAR_INOUT20

kXBARA1_OutputIomuxXbarInout21 

XBARA1_OUT21 output assigned to IOMUX_XBAR_INOUT21

kXBARA1_OutputIomuxXbarInout22 

XBARA1_OUT22 output assigned to IOMUX_XBAR_INOUT22

kXBARA1_OutputIomuxXbarInout23 

XBARA1_OUT23 output assigned to IOMUX_XBAR_INOUT23

kXBARA1_OutputIomuxXbarInout24 

XBARA1_OUT24 output assigned to IOMUX_XBAR_INOUT24

kXBARA1_OutputIomuxXbarInout25 

XBARA1_OUT25 output assigned to IOMUX_XBAR_INOUT25

kXBARA1_OutputIomuxXbarInout26 

XBARA1_OUT26 output assigned to IOMUX_XBAR_INOUT26

kXBARA1_OutputIomuxXbarInout27 

XBARA1_OUT27 output assigned to IOMUX_XBAR_INOUT27

kXBARA1_OutputIomuxXbarInout28 

XBARA1_OUT28 output assigned to IOMUX_XBAR_INOUT28

kXBARA1_OutputIomuxXbarInout29 

XBARA1_OUT29 output assigned to IOMUX_XBAR_INOUT29

kXBARA1_OutputIomuxXbarInout30 

XBARA1_OUT30 output assigned to IOMUX_XBAR_INOUT30

kXBARA1_OutputIomuxXbarInout31 

XBARA1_OUT31 output assigned to IOMUX_XBAR_INOUT31

kXBARA1_OutputIomuxXbarInout32 

XBARA1_OUT32 output assigned to IOMUX_XBAR_INOUT32

kXBARA1_OutputIomuxXbarInout33 

XBARA1_OUT33 output assigned to IOMUX_XBAR_INOUT33

kXBARA1_OutputIomuxXbarInout34 

XBARA1_OUT34 output assigned to IOMUX_XBAR_INOUT34

kXBARA1_OutputIomuxXbarInout35 

XBARA1_OUT35 output assigned to IOMUX_XBAR_INOUT35

kXBARA1_OutputIomuxXbarInout36 

XBARA1_OUT36 output assigned to IOMUX_XBAR_INOUT36

kXBARA1_OutputIomuxXbarInout37 

XBARA1_OUT37 output assigned to IOMUX_XBAR_INOUT37

kXBARA1_OutputIomuxXbarInout38 

XBARA1_OUT38 output assigned to IOMUX_XBAR_INOUT38

kXBARA1_OutputIomuxXbarInout39 

XBARA1_OUT39 output assigned to IOMUX_XBAR_INOUT39

kXBARA1_OutputIomuxXbarInout40 

XBARA1_OUT40 output assigned to IOMUX_XBAR_INOUT40

kXBARA1_OutputAcmp1Sample 

XBARA1_OUT41 output assigned to ACMP1_SAMPLE

kXBARA1_OutputAcmp2Sample 

XBARA1_OUT42 output assigned to ACMP2_SAMPLE

kXBARA1_OutputAcmp3Sample 

XBARA1_OUT43 output assigned to ACMP3_SAMPLE

kXBARA1_OutputAcmp4Sample 

XBARA1_OUT44 output assigned to ACMP4_SAMPLE

kXBARA1_OutputRESERVED45 

XBARA1_OUT45 output is reserved.

kXBARA1_OutputRESERVED46 

XBARA1_OUT46 output is reserved.

kXBARA1_OutputRESERVED47 

XBARA1_OUT47 output is reserved.

kXBARA1_OutputRESERVED48 

XBARA1_OUT48 output is reserved.

kXBARA1_OutputFlexpwm1Pwm0Exta 

XBARA1_OUT49 output assigned to FLEXPWM1_PWM0_EXTA

kXBARA1_OutputFlexpwm1Pwm1Exta 

XBARA1_OUT50 output assigned to FLEXPWM1_PWM1_EXTA

kXBARA1_OutputFlexpwm1Pwm2Exta 

XBARA1_OUT51 output assigned to FLEXPWM1_PWM2_EXTA

kXBARA1_OutputFlexpwm1Pwm3Exta 

XBARA1_OUT52 output assigned to FLEXPWM1_PWM3_EXTA

kXBARA1_OutputFlexpwm1Pwm0ExtSync 

XBARA1_OUT53 output assigned to FLEXPWM1_PWM0_EXT_SYNC

kXBARA1_OutputFlexpwm1Pwm1ExtSync 

XBARA1_OUT54 output assigned to FLEXPWM1_PWM1_EXT_SYNC

kXBARA1_OutputFlexpwm1Pwm2ExtSync 

XBARA1_OUT55 output assigned to FLEXPWM1_PWM2_EXT_SYNC

kXBARA1_OutputFlexpwm1Pwm3ExtSync 

XBARA1_OUT56 output assigned to FLEXPWM1_PWM3_EXT_SYNC

kXBARA1_OutputFlexpwm1ExtClk 

XBARA1_OUT57 output assigned to FLEXPWM1_EXT_CLK

kXBARA1_OutputFlexpwm1Fault0 

XBARA1_OUT58 output assigned to FLEXPWM1_FAULT0

kXBARA1_OutputFlexpwm1Fault1 

XBARA1_OUT59 output assigned to FLEXPWM1_FAULT1

kXBARA1_OutputFlexpwm1234Fault2 

XBARA1_OUT60 output assigned to FLEXPWM1_2_3_4_FAULT2

kXBARA1_OutputFlexpwm1234Fault3 

XBARA1_OUT61 output assigned to FLEXPWM1_2_3_4_FAULT3

kXBARA1_OutputFlexpwm1ExtForce 

XBARA1_OUT62 output assigned to FLEXPWM1_EXT_FORCE

kXBARA1_OutputFlexpwm2Pwm0Exta 

XBARA1_OUT63 output assigned to FLEXPWM2_PWM0_EXTA

kXBARA1_OutputFlexpwm2Pwm1Exta 

XBARA1_OUT64 output assigned to FLEXPWM2_PWM1_EXTA

kXBARA1_OutputFlexpwm2Pwm2Exta 

XBARA1_OUT65 output assigned to FLEXPWM2_PWM2_EXTA

kXBARA1_OutputFlexpwm2Pwm3Exta 

XBARA1_OUT66 output assigned to FLEXPWM2_PWM3_EXTA

kXBARA1_OutputFlexpwm2Pwm0ExtSync 

XBARA1_OUT67 output assigned to FLEXPWM2_PWM0_EXT_SYNC

kXBARA1_OutputFlexpwm2Pwm1ExtSync 

XBARA1_OUT68 output assigned to FLEXPWM2_PWM1_EXT_SYNC

kXBARA1_OutputFlexpwm2Pwm2ExtSync 

XBARA1_OUT69 output assigned to FLEXPWM2_PWM2_EXT_SYNC

kXBARA1_OutputFlexpwm2Pwm3ExtSync 

XBARA1_OUT70 output assigned to FLEXPWM2_PWM3_EXT_SYNC

kXBARA1_OutputFlexpwm2ExtClk 

XBARA1_OUT71 output assigned to FLEXPWM2_EXT_CLK

kXBARA1_OutputFlexpwm2Fault0 

XBARA1_OUT72 output assigned to FLEXPWM2_FAULT0

kXBARA1_OutputFlexpwm2Fault1 

XBARA1_OUT73 output assigned to FLEXPWM2_FAULT1

kXBARA1_OutputFlexpwm2ExtForce 

XBARA1_OUT74 output assigned to FLEXPWM2_EXT_FORCE

kXBARA1_OutputFlexpwm34Pwm0Exta 

XBARA1_OUT75 output assigned to FLEXPWM3_4_PWM0_EXTA

kXBARA1_OutputFlexpwm34Pwm1Exta 

XBARA1_OUT76 output assigned to FLEXPWM3_4_PWM1_EXTA

kXBARA1_OutputFlexpwm34Pwm2Exta 

XBARA1_OUT77 output assigned to FLEXPWM3_4_PWM2_EXTA

kXBARA1_OutputFlexpwm34Pwm3Exta 

XBARA1_OUT78 output assigned to FLEXPWM3_4_PWM3_EXTA

kXBARA1_OutputFlexpwm34ExtClk 

XBARA1_OUT79 output assigned to FLEXPWM3_4_EXT_CLK

kXBARA1_OutputFlexpwm3Pwm0ExtSync 

XBARA1_OUT80 output assigned to FLEXPWM3_PWM0_EXT_SYNC

kXBARA1_OutputFlexpwm3Pwm1ExtSync 

XBARA1_OUT81 output assigned to FLEXPWM3_PWM1_EXT_SYNC

kXBARA1_OutputFlexpwm3Pwm2ExtSync 

XBARA1_OUT82 output assigned to FLEXPWM3_PWM2_EXT_SYNC

kXBARA1_OutputFlexpwm3Pwm3ExtSync 

XBARA1_OUT83 output assigned to FLEXPWM3_PWM3_EXT_SYNC

kXBARA1_OutputFlexpwm3Fault0 

XBARA1_OUT84 output assigned to FLEXPWM3_FAULT0

kXBARA1_OutputFlexpwm3Fault1 

XBARA1_OUT85 output assigned to FLEXPWM3_FAULT1

kXBARA1_OutputFlexpwm3ExtForce 

XBARA1_OUT86 output assigned to FLEXPWM3_EXT_FORCE

kXBARA1_OutputFlexpwm4Pwm0ExtSync 

XBARA1_OUT87 output assigned to FLEXPWM4_PWM0_EXT_SYNC

kXBARA1_OutputFlexpwm4Pwm1ExtSync 

XBARA1_OUT88 output assigned to FLEXPWM4_PWM1_EXT_SYNC

kXBARA1_OutputFlexpwm4Pwm2ExtSync 

XBARA1_OUT89 output assigned to FLEXPWM4_PWM2_EXT_SYNC

kXBARA1_OutputFlexpwm4Pwm3ExtSync 

XBARA1_OUT90 output assigned to FLEXPWM4_PWM3_EXT_SYNC

kXBARA1_OutputFlexpwm4Fault0 

XBARA1_OUT91 output assigned to FLEXPWM4_FAULT0

kXBARA1_OutputFlexpwm4Fault1 

XBARA1_OUT92 output assigned to FLEXPWM4_FAULT1

kXBARA1_OutputFlexpwm4ExtForce 

XBARA1_OUT93 output assigned to FLEXPWM4_EXT_FORCE

kXBARA1_OutputRESERVED94 

XBARA1_OUT94 output is reserved.

kXBARA1_OutputRESERVED95 

XBARA1_OUT95 output is reserved.

kXBARA1_OutputRESERVED96 

XBARA1_OUT96 output is reserved.

kXBARA1_OutputRESERVED97 

XBARA1_OUT97 output is reserved.

kXBARA1_OutputRESERVED98 

XBARA1_OUT98 output is reserved.

kXBARA1_OutputRESERVED99 

XBARA1_OUT99 output is reserved.

kXBARA1_OutputRESERVED100 

XBARA1_OUT100 output is reserved.

kXBARA1_OutputRESERVED101 

XBARA1_OUT101 output is reserved.

kXBARA1_OutputRESERVED102 

XBARA1_OUT102 output is reserved.

kXBARA1_OutputRESERVED103 

XBARA1_OUT103 output is reserved.

kXBARA1_OutputRESERVED104 

XBARA1_OUT104 output is reserved.

kXBARA1_OutputRESERVED105 

XBARA1_OUT105 output is reserved.

kXBARA1_OutputRESERVED106 

XBARA1_OUT106 output is reserved.

kXBARA1_OutputRESERVED107 

XBARA1_OUT107 output is reserved.

kXBARA1_OutputDec1Phasea 

XBARA1_OUT108 output assigned to DEC1_PHASEA

kXBARA1_OutputDec1Phaseb 

XBARA1_OUT109 output assigned to DEC1_PHASEB

kXBARA1_OutputDec1Index 

XBARA1_OUT110 output assigned to DEC1_INDEX

kXBARA1_OutputDec1Home 

XBARA1_OUT111 output assigned to DEC1_HOME

kXBARA1_OutputDec1Trigger 

XBARA1_OUT112 output assigned to DEC1_TRIGGER

kXBARA1_OutputDec2Phasea 

XBARA1_OUT113 output assigned to DEC2_PHASEA

kXBARA1_OutputDec2Phaseb 

XBARA1_OUT114 output assigned to DEC2_PHASEB

kXBARA1_OutputDec2Index 

XBARA1_OUT115 output assigned to DEC2_INDEX

kXBARA1_OutputDec2Home 

XBARA1_OUT116 output assigned to DEC2_HOME

kXBARA1_OutputDec2Trigger 

XBARA1_OUT117 output assigned to DEC2_TRIGGER

kXBARA1_OutputDec3Phasea 

XBARA1_OUT118 output assigned to DEC3_PHASEA

kXBARA1_OutputDec3Phaseb 

XBARA1_OUT119 output assigned to DEC3_PHASEB

kXBARA1_OutputDec3Index 

XBARA1_OUT120 output assigned to DEC3_INDEX

kXBARA1_OutputDec3Home 

XBARA1_OUT121 output assigned to DEC3_HOME

kXBARA1_OutputDec3Trigger 

XBARA1_OUT122 output assigned to DEC3_TRIGGER

kXBARA1_OutputDec4Phasea 

XBARA1_OUT123 output assigned to DEC4_PHASEA

kXBARA1_OutputDec4Phaseb 

XBARA1_OUT124 output assigned to DEC4_PHASEB

kXBARA1_OutputDec4Index 

XBARA1_OUT125 output assigned to DEC4_INDEX

kXBARA1_OutputDec4Home 

XBARA1_OUT126 output assigned to DEC4_HOME

kXBARA1_OutputDec4Trigger 

XBARA1_OUT127 output assigned to DEC4_TRIGGER

kXBARA1_OutputRESERVED128 

XBARA1_OUT128 output is reserved.

kXBARA1_OutputRESERVED129 

XBARA1_OUT129 output is reserved.

kXBARA1_OutputRESERVED130 

XBARA1_OUT130 output is reserved.

kXBARA1_OutputRESERVED131 

XBARA1_OUT131 output is reserved.

kXBARA1_OutputCan1 

XBARA1_OUT132 output assigned to CAN1

kXBARA1_OutputCan2 

XBARA1_OUT133 output assigned to CAN2

kXBARA1_OutputRESERVED134 

XBARA1_OUT134 output is reserved.

kXBARA1_OutputRESERVED135 

XBARA1_OUT135 output is reserved.

kXBARA1_OutputRESERVED136 

XBARA1_OUT136 output is reserved.

kXBARA1_OutputRESERVED137 

XBARA1_OUT137 output is reserved.

kXBARA1_OutputQtimer1Timer0 

XBARA1_OUT138 output assigned to QTIMER1_TIMER0

kXBARA1_OutputQtimer1Timer1 

XBARA1_OUT139 output assigned to QTIMER1_TIMER1

kXBARA1_OutputQtimer1Timer2 

XBARA1_OUT140 output assigned to QTIMER1_TIMER2

kXBARA1_OutputQtimer1Timer3 

XBARA1_OUT141 output assigned to QTIMER1_TIMER3

kXBARA1_OutputQtimer2Timer0 

XBARA1_OUT142 output assigned to QTIMER2_TIMER0

kXBARA1_OutputQtimer2Timer1 

XBARA1_OUT143 output assigned to QTIMER2_TIMER1

kXBARA1_OutputQtimer2Timer2 

XBARA1_OUT144 output assigned to QTIMER2_TIMER2

kXBARA1_OutputQtimer2Timer3 

XBARA1_OUT145 output assigned to QTIMER2_TIMER3

kXBARA1_OutputQtimer3Timer0 

XBARA1_OUT146 output assigned to QTIMER3_TIMER0

kXBARA1_OutputQtimer3Timer1 

XBARA1_OUT147 output assigned to QTIMER3_TIMER1

kXBARA1_OutputQtimer3Timer2 

XBARA1_OUT148 output assigned to QTIMER3_TIMER2

kXBARA1_OutputQtimer3Timer3 

XBARA1_OUT149 output assigned to QTIMER3_TIMER3

kXBARA1_OutputQtimer4Timer0 

XBARA1_OUT150 output assigned to QTIMER4_TIMER0

kXBARA1_OutputQtimer4Timer1 

XBARA1_OUT151 output assigned to QTIMER4_TIMER1

kXBARA1_OutputQtimer4Timer2 

XBARA1_OUT152 output assigned to QTIMER4_TIMER2

kXBARA1_OutputQtimer4Timer3 

XBARA1_OUT153 output assigned to QTIMER4_TIMER3

kXBARA1_OutputEwmEwmIn 

XBARA1_OUT154 output assigned to EWM_EWM_IN

kXBARA1_OutputAdcEtc0Coco0 

XBARA1_OUT155 output assigned to ADC_ETC0_COCO0

kXBARA1_OutputAdcEtc0Coco1 

XBARA1_OUT156 output assigned to ADC_ETC0_COCO1

kXBARA1_OutputAdcEtc0Coco2 

XBARA1_OUT157 output assigned to ADC_ETC0_COCO2

kXBARA1_OutputAdcEtc0Coco3 

XBARA1_OUT158 output assigned to ADC_ETC0_COCO3

kXBARA1_OutputAdcEtc1Coco0 

XBARA1_OUT159 output assigned to ADC_ETC1_COCO0

kXBARA1_OutputAdcEtc1Coco1 

XBARA1_OUT160 output assigned to ADC_ETC1_COCO1

kXBARA1_OutputAdcEtc1Coco2 

XBARA1_OUT161 output assigned to ADC_ETC1_COCO2

kXBARA1_OutputAdcEtc1Coco3 

XBARA1_OUT162 output assigned to ADC_ETC1_COCO3

kXBARA1_OutputRESERVED163 

XBARA1_OUT163 output is reserved.

kXBARA1_OutputRESERVED164 

XBARA1_OUT164 output is reserved.

kXBARA1_OutputRESERVED165 

XBARA1_OUT165 output is reserved.

kXBARA1_OutputRESERVED166 

XBARA1_OUT166 output is reserved.

kXBARA1_OutputRESERVED167 

XBARA1_OUT167 output is reserved.

kXBARA1_OutputRESERVED168 

XBARA1_OUT168 output is reserved.

kXBARA1_OutputRESERVED169 

XBARA1_OUT169 output is reserved.

kXBARA1_OutputRESERVED170 

XBARA1_OUT170 output is reserved.

kXBARA1_OutputFlexio1TrigIn0 

XBARA1_OUT171 output assigned to FLEXIO1_TRIG_IN0

kXBARA1_OutputFlexio1TrigIn1 

XBARA1_OUT172 output assigned to FLEXIO1_TRIG_IN1

kXBARA1_OutputFlexio2TrigIn0 

XBARA1_OUT173 output assigned to FLEXIO2_TRIG_IN0

kXBARA1_OutputFlexio2TrigIn1 

XBARA1_OUT174 output assigned to FLEXIO2_TRIG_IN1

kXBARB2_OutputAoi1In00 

XBARB2_OUT0 output assigned to AOI1_IN00

kXBARB2_OutputAoi1In01 

XBARB2_OUT1 output assigned to AOI1_IN01

kXBARB2_OutputAoi1In02 

XBARB2_OUT2 output assigned to AOI1_IN02

kXBARB2_OutputAoi1In03 

XBARB2_OUT3 output assigned to AOI1_IN03

kXBARB2_OutputAoi1In04 

XBARB2_OUT4 output assigned to AOI1_IN04

kXBARB2_OutputAoi1In05 

XBARB2_OUT5 output assigned to AOI1_IN05

kXBARB2_OutputAoi1In06 

XBARB2_OUT6 output assigned to AOI1_IN06

kXBARB2_OutputAoi1In07 

XBARB2_OUT7 output assigned to AOI1_IN07

kXBARB2_OutputAoi1In08 

XBARB2_OUT8 output assigned to AOI1_IN08

kXBARB2_OutputAoi1In09 

XBARB2_OUT9 output assigned to AOI1_IN09

kXBARB2_OutputAoi1In10 

XBARB2_OUT10 output assigned to AOI1_IN10

kXBARB2_OutputAoi1In11 

XBARB2_OUT11 output assigned to AOI1_IN11

kXBARB2_OutputAoi1In12 

XBARB2_OUT12 output assigned to AOI1_IN12

kXBARB2_OutputAoi1In13 

XBARB2_OUT13 output assigned to AOI1_IN13

kXBARB2_OutputAoi1In14 

XBARB2_OUT14 output assigned to AOI1_IN14

kXBARB2_OutputAoi1In15 

XBARB2_OUT15 output assigned to AOI1_IN15

kXBARB3_OutputAoi2In00 

XBARB3_OUT0 output assigned to AOI2_IN00

kXBARB3_OutputAoi2In01 

XBARB3_OUT1 output assigned to AOI2_IN01

kXBARB3_OutputAoi2In02 

XBARB3_OUT2 output assigned to AOI2_IN02

kXBARB3_OutputAoi2In03 

XBARB3_OUT3 output assigned to AOI2_IN03

kXBARB3_OutputAoi2In04 

XBARB3_OUT4 output assigned to AOI2_IN04

kXBARB3_OutputAoi2In05 

XBARB3_OUT5 output assigned to AOI2_IN05

kXBARB3_OutputAoi2In06 

XBARB3_OUT6 output assigned to AOI2_IN06

kXBARB3_OutputAoi2In07 

XBARB3_OUT7 output assigned to AOI2_IN07

kXBARB3_OutputAoi2In08 

XBARB3_OUT8 output assigned to AOI2_IN08

kXBARB3_OutputAoi2In09 

XBARB3_OUT9 output assigned to AOI2_IN09

kXBARB3_OutputAoi2In10 

XBARB3_OUT10 output assigned to AOI2_IN10

kXBARB3_OutputAoi2In11 

XBARB3_OUT11 output assigned to AOI2_IN11

kXBARB3_OutputAoi2In12 

XBARB3_OUT12 output assigned to AOI2_IN12

kXBARB3_OutputAoi2In13 

XBARB3_OUT13 output assigned to AOI2_IN13

kXBARB3_OutputAoi2In14 

XBARB3_OUT14 output assigned to AOI2_IN14

kXBARB3_OutputAoi2In15 

XBARB3_OUT15 output assigned to AOI2_IN15

kXBARA1_OutputDmaChMuxReq81 

XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ81

kXBARA1_OutputDmaChMuxReq82 

XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ82

kXBARA1_OutputDmaChMuxReq83 

XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ83

kXBARA1_OutputDmaChMuxReq84 

XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ84

kXBARA1_OutputIomuxXbarInout04 

XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04

kXBARA1_OutputIomuxXbarInout05 

XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05

kXBARA1_OutputIomuxXbarInout06 

XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06

kXBARA1_OutputIomuxXbarInout07 

XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07

kXBARA1_OutputIomuxXbarInout08 

XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08

kXBARA1_OutputIomuxXbarInout09 

XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09

kXBARA1_OutputIomuxXbarInout10 

XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10

kXBARA1_OutputIomuxXbarInout11 

XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11

kXBARA1_OutputIomuxXbarInout12 

XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12

kXBARA1_OutputIomuxXbarInout13 

XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13

kXBARA1_OutputIomuxXbarInout14 

XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14

kXBARA1_OutputIomuxXbarInout15 

XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15

kXBARA1_OutputIomuxXbarInout16 

XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16

kXBARA1_OutputIomuxXbarInout17 

XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17

kXBARA1_OutputIomuxXbarInout18 

XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18

kXBARA1_OutputIomuxXbarInout19 

XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19

kXBARA1_OutputIomuxXbarInout20 

XBARA1_OUT20 output assigned to IOMUX_XBAR_INOUT20

kXBARA1_OutputIomuxXbarInout21 

XBARA1_OUT21 output assigned to IOMUX_XBAR_INOUT21

kXBARA1_OutputIomuxXbarInout22 

XBARA1_OUT22 output assigned to IOMUX_XBAR_INOUT22

kXBARA1_OutputIomuxXbarInout23 

XBARA1_OUT23 output assigned to IOMUX_XBAR_INOUT23

kXBARA1_OutputIomuxXbarInout24 

XBARA1_OUT24 output assigned to IOMUX_XBAR_INOUT24

kXBARA1_OutputIomuxXbarInout25 

XBARA1_OUT25 output assigned to IOMUX_XBAR_INOUT25

kXBARA1_OutputIomuxXbarInout26 

XBARA1_OUT26 output assigned to IOMUX_XBAR_INOUT26

kXBARA1_OutputIomuxXbarInout27 

XBARA1_OUT27 output assigned to IOMUX_XBAR_INOUT27

kXBARA1_OutputIomuxXbarInout28 

XBARA1_OUT28 output assigned to IOMUX_XBAR_INOUT28

kXBARA1_OutputIomuxXbarInout29 

XBARA1_OUT29 output assigned to IOMUX_XBAR_INOUT29

kXBARA1_OutputIomuxXbarInout30 

XBARA1_OUT30 output assigned to IOMUX_XBAR_INOUT30

kXBARA1_OutputIomuxXbarInout31 

XBARA1_OUT31 output assigned to IOMUX_XBAR_INOUT31

kXBARA1_OutputIomuxXbarInout32 

XBARA1_OUT32 output assigned to IOMUX_XBAR_INOUT32

kXBARA1_OutputIomuxXbarInout33 

XBARA1_OUT33 output assigned to IOMUX_XBAR_INOUT33

kXBARA1_OutputIomuxXbarInout34 

XBARA1_OUT34 output assigned to IOMUX_XBAR_INOUT34

kXBARA1_OutputIomuxXbarInout35 

XBARA1_OUT35 output assigned to IOMUX_XBAR_INOUT35

kXBARA1_OutputIomuxXbarInout36 

XBARA1_OUT36 output assigned to IOMUX_XBAR_INOUT36

kXBARA1_OutputIomuxXbarInout37 

XBARA1_OUT37 output assigned to IOMUX_XBAR_INOUT37

kXBARA1_OutputIomuxXbarInout38 

XBARA1_OUT38 output assigned to IOMUX_XBAR_INOUT38

kXBARA1_OutputIomuxXbarInout39 

XBARA1_OUT39 output assigned to IOMUX_XBAR_INOUT39

kXBARA1_OutputIomuxXbarInout40 

XBARA1_OUT40 output assigned to IOMUX_XBAR_INOUT40

kXBARA1_OutputAcmp1Sample 

XBARA1_OUT41 output assigned to ACMP1_SAMPLE

kXBARA1_OutputAcmp2Sample 

XBARA1_OUT42 output assigned to ACMP2_SAMPLE

kXBARA1_OutputAcmp3Sample 

XBARA1_OUT43 output assigned to ACMP3_SAMPLE

kXBARA1_OutputAcmp4Sample 

XBARA1_OUT44 output assigned to ACMP4_SAMPLE

kXBARA1_OutputRESERVED45 

XBARA1_OUT45 output is reserved.

kXBARA1_OutputRESERVED46 

XBARA1_OUT46 output is reserved.

kXBARA1_OutputRESERVED47 

XBARA1_OUT47 output is reserved.

kXBARA1_OutputRESERVED48 

XBARA1_OUT48 output is reserved.

kXBARA1_OutputFlexpwm1Pwm0Exta 

XBARA1_OUT49 output assigned to FLEXPWM1_PWM0_EXTA

kXBARA1_OutputFlexpwm1Pwm1Exta 

XBARA1_OUT50 output assigned to FLEXPWM1_PWM1_EXTA

kXBARA1_OutputFlexpwm1Pwm2Exta 

XBARA1_OUT51 output assigned to FLEXPWM1_PWM2_EXTA

kXBARA1_OutputFlexpwm1Pwm3Exta 

XBARA1_OUT52 output assigned to FLEXPWM1_PWM3_EXTA

kXBARA1_OutputFlexpwm1Pwm0ExtSync 

XBARA1_OUT53 output assigned to FLEXPWM1_PWM0_EXT_SYNC

kXBARA1_OutputFlexpwm1Pwm1ExtSync 

XBARA1_OUT54 output assigned to FLEXPWM1_PWM1_EXT_SYNC

kXBARA1_OutputFlexpwm1Pwm2ExtSync 

XBARA1_OUT55 output assigned to FLEXPWM1_PWM2_EXT_SYNC

kXBARA1_OutputFlexpwm1Pwm3ExtSync 

XBARA1_OUT56 output assigned to FLEXPWM1_PWM3_EXT_SYNC

kXBARA1_OutputFlexpwm1ExtClk 

XBARA1_OUT57 output assigned to FLEXPWM1_EXT_CLK

kXBARA1_OutputFlexpwm1Fault0 

XBARA1_OUT58 output assigned to FLEXPWM1_FAULT0

kXBARA1_OutputFlexpwm1Fault1 

XBARA1_OUT59 output assigned to FLEXPWM1_FAULT1

kXBARA1_OutputFlexpwm1234Fault2 

XBARA1_OUT60 output assigned to FLEXPWM1_2_3_4_FAULT2

kXBARA1_OutputFlexpwm1234Fault3 

XBARA1_OUT61 output assigned to FLEXPWM1_2_3_4_FAULT3

kXBARA1_OutputFlexpwm1ExtForce 

XBARA1_OUT62 output assigned to FLEXPWM1_EXT_FORCE

kXBARA1_OutputFlexpwm2Pwm0Exta 

XBARA1_OUT63 output assigned to FLEXPWM2_PWM0_EXTA

kXBARA1_OutputFlexpwm2Pwm1Exta 

XBARA1_OUT64 output assigned to FLEXPWM2_PWM1_EXTA

kXBARA1_OutputFlexpwm2Pwm2Exta 

XBARA1_OUT65 output assigned to FLEXPWM2_PWM2_EXTA

kXBARA1_OutputFlexpwm2Pwm3Exta 

XBARA1_OUT66 output assigned to FLEXPWM2_PWM3_EXTA

kXBARA1_OutputFlexpwm2Pwm0ExtSync 

XBARA1_OUT67 output assigned to FLEXPWM2_PWM0_EXT_SYNC

kXBARA1_OutputFlexpwm2Pwm1ExtSync 

XBARA1_OUT68 output assigned to FLEXPWM2_PWM1_EXT_SYNC

kXBARA1_OutputFlexpwm2Pwm2ExtSync 

XBARA1_OUT69 output assigned to FLEXPWM2_PWM2_EXT_SYNC

kXBARA1_OutputFlexpwm2Pwm3ExtSync 

XBARA1_OUT70 output assigned to FLEXPWM2_PWM3_EXT_SYNC

kXBARA1_OutputFlexpwm2ExtClk 

XBARA1_OUT71 output assigned to FLEXPWM2_EXT_CLK

kXBARA1_OutputFlexpwm2Fault0 

XBARA1_OUT72 output assigned to FLEXPWM2_FAULT0

kXBARA1_OutputFlexpwm2Fault1 

XBARA1_OUT73 output assigned to FLEXPWM2_FAULT1

kXBARA1_OutputFlexpwm2ExtForce 

XBARA1_OUT74 output assigned to FLEXPWM2_EXT_FORCE

kXBARA1_OutputFlexpwm34Pwm0Exta 

XBARA1_OUT75 output assigned to FLEXPWM3_4_PWM0_EXTA

kXBARA1_OutputFlexpwm34Pwm1Exta 

XBARA1_OUT76 output assigned to FLEXPWM3_4_PWM1_EXTA

kXBARA1_OutputFlexpwm34Pwm2Exta 

XBARA1_OUT77 output assigned to FLEXPWM3_4_PWM2_EXTA

kXBARA1_OutputFlexpwm34Pwm3Exta 

XBARA1_OUT78 output assigned to FLEXPWM3_4_PWM3_EXTA

kXBARA1_OutputFlexpwm34ExtClk 

XBARA1_OUT79 output assigned to FLEXPWM3_4_EXT_CLK

kXBARA1_OutputFlexpwm3Pwm0ExtSync 

XBARA1_OUT80 output assigned to FLEXPWM3_PWM0_EXT_SYNC

kXBARA1_OutputFlexpwm3Pwm1ExtSync 

XBARA1_OUT81 output assigned to FLEXPWM3_PWM1_EXT_SYNC

kXBARA1_OutputFlexpwm3Pwm2ExtSync 

XBARA1_OUT82 output assigned to FLEXPWM3_PWM2_EXT_SYNC

kXBARA1_OutputFlexpwm3Pwm3ExtSync 

XBARA1_OUT83 output assigned to FLEXPWM3_PWM3_EXT_SYNC

kXBARA1_OutputFlexpwm3Fault0 

XBARA1_OUT84 output assigned to FLEXPWM3_FAULT0

kXBARA1_OutputFlexpwm3Fault1 

XBARA1_OUT85 output assigned to FLEXPWM3_FAULT1

kXBARA1_OutputFlexpwm3ExtForce 

XBARA1_OUT86 output assigned to FLEXPWM3_EXT_FORCE

kXBARA1_OutputFlexpwm4Pwm0ExtSync 

XBARA1_OUT87 output assigned to FLEXPWM4_PWM0_EXT_SYNC

kXBARA1_OutputFlexpwm4Pwm1ExtSync 

XBARA1_OUT88 output assigned to FLEXPWM4_PWM1_EXT_SYNC

kXBARA1_OutputFlexpwm4Pwm2ExtSync 

XBARA1_OUT89 output assigned to FLEXPWM4_PWM2_EXT_SYNC

kXBARA1_OutputFlexpwm4Pwm3ExtSync 

XBARA1_OUT90 output assigned to FLEXPWM4_PWM3_EXT_SYNC

kXBARA1_OutputFlexpwm4Fault0 

XBARA1_OUT91 output assigned to FLEXPWM4_FAULT0

kXBARA1_OutputFlexpwm4Fault1 

XBARA1_OUT92 output assigned to FLEXPWM4_FAULT1

kXBARA1_OutputFlexpwm4ExtForce 

XBARA1_OUT93 output assigned to FLEXPWM4_EXT_FORCE

kXBARA1_OutputRESERVED94 

XBARA1_OUT94 output is reserved.

kXBARA1_OutputRESERVED95 

XBARA1_OUT95 output is reserved.

kXBARA1_OutputRESERVED96 

XBARA1_OUT96 output is reserved.

kXBARA1_OutputRESERVED97 

XBARA1_OUT97 output is reserved.

kXBARA1_OutputRESERVED98 

XBARA1_OUT98 output is reserved.

kXBARA1_OutputRESERVED99 

XBARA1_OUT99 output is reserved.

kXBARA1_OutputRESERVED100 

XBARA1_OUT100 output is reserved.

kXBARA1_OutputRESERVED101 

XBARA1_OUT101 output is reserved.

kXBARA1_OutputRESERVED102 

XBARA1_OUT102 output is reserved.

kXBARA1_OutputRESERVED103 

XBARA1_OUT103 output is reserved.

kXBARA1_OutputRESERVED104 

XBARA1_OUT104 output is reserved.

kXBARA1_OutputRESERVED105 

XBARA1_OUT105 output is reserved.

kXBARA1_OutputRESERVED106 

XBARA1_OUT106 output is reserved.

kXBARA1_OutputRESERVED107 

XBARA1_OUT107 output is reserved.

kXBARA1_OutputDec1Phasea 

XBARA1_OUT108 output assigned to DEC1_PHASEA

kXBARA1_OutputDec1Phaseb 

XBARA1_OUT109 output assigned to DEC1_PHASEB

kXBARA1_OutputDec1Index 

XBARA1_OUT110 output assigned to DEC1_INDEX

kXBARA1_OutputDec1Home 

XBARA1_OUT111 output assigned to DEC1_HOME

kXBARA1_OutputDec1Trigger 

XBARA1_OUT112 output assigned to DEC1_TRIGGER

kXBARA1_OutputDec2Phasea 

XBARA1_OUT113 output assigned to DEC2_PHASEA

kXBARA1_OutputDec2Phaseb 

XBARA1_OUT114 output assigned to DEC2_PHASEB

kXBARA1_OutputDec2Index 

XBARA1_OUT115 output assigned to DEC2_INDEX

kXBARA1_OutputDec2Home 

XBARA1_OUT116 output assigned to DEC2_HOME

kXBARA1_OutputDec2Trigger 

XBARA1_OUT117 output assigned to DEC2_TRIGGER

kXBARA1_OutputDec3Phasea 

XBARA1_OUT118 output assigned to DEC3_PHASEA

kXBARA1_OutputDec3Phaseb 

XBARA1_OUT119 output assigned to DEC3_PHASEB

kXBARA1_OutputDec3Index 

XBARA1_OUT120 output assigned to DEC3_INDEX

kXBARA1_OutputDec3Home 

XBARA1_OUT121 output assigned to DEC3_HOME

kXBARA1_OutputDec3Trigger 

XBARA1_OUT122 output assigned to DEC3_TRIGGER

kXBARA1_OutputDec4Phasea 

XBARA1_OUT123 output assigned to DEC4_PHASEA

kXBARA1_OutputDec4Phaseb 

XBARA1_OUT124 output assigned to DEC4_PHASEB

kXBARA1_OutputDec4Index 

XBARA1_OUT125 output assigned to DEC4_INDEX

kXBARA1_OutputDec4Home 

XBARA1_OUT126 output assigned to DEC4_HOME

kXBARA1_OutputDec4Trigger 

XBARA1_OUT127 output assigned to DEC4_TRIGGER

kXBARA1_OutputRESERVED128 

XBARA1_OUT128 output is reserved.

kXBARA1_OutputRESERVED129 

XBARA1_OUT129 output is reserved.

kXBARA1_OutputRESERVED130 

XBARA1_OUT130 output is reserved.

kXBARA1_OutputRESERVED131 

XBARA1_OUT131 output is reserved.

kXBARA1_OutputCan1 

XBARA1_OUT132 output assigned to CAN1

kXBARA1_OutputCan2 

XBARA1_OUT133 output assigned to CAN2

kXBARA1_OutputRESERVED134 

XBARA1_OUT134 output is reserved.

kXBARA1_OutputRESERVED135 

XBARA1_OUT135 output is reserved.

kXBARA1_OutputRESERVED136 

XBARA1_OUT136 output is reserved.

kXBARA1_OutputRESERVED137 

XBARA1_OUT137 output is reserved.

kXBARA1_OutputQtimer1Timer0 

XBARA1_OUT138 output assigned to QTIMER1_TIMER0

kXBARA1_OutputQtimer1Timer1 

XBARA1_OUT139 output assigned to QTIMER1_TIMER1

kXBARA1_OutputQtimer1Timer2 

XBARA1_OUT140 output assigned to QTIMER1_TIMER2

kXBARA1_OutputQtimer1Timer3 

XBARA1_OUT141 output assigned to QTIMER1_TIMER3

kXBARA1_OutputQtimer2Timer0 

XBARA1_OUT142 output assigned to QTIMER2_TIMER0

kXBARA1_OutputQtimer2Timer1 

XBARA1_OUT143 output assigned to QTIMER2_TIMER1

kXBARA1_OutputQtimer2Timer2 

XBARA1_OUT144 output assigned to QTIMER2_TIMER2

kXBARA1_OutputQtimer2Timer3 

XBARA1_OUT145 output assigned to QTIMER2_TIMER3

kXBARA1_OutputQtimer3Timer0 

XBARA1_OUT146 output assigned to QTIMER3_TIMER0

kXBARA1_OutputQtimer3Timer1 

XBARA1_OUT147 output assigned to QTIMER3_TIMER1

kXBARA1_OutputQtimer3Timer2 

XBARA1_OUT148 output assigned to QTIMER3_TIMER2

kXBARA1_OutputQtimer3Timer3 

XBARA1_OUT149 output assigned to QTIMER3_TIMER3

kXBARA1_OutputQtimer4Timer0 

XBARA1_OUT150 output assigned to QTIMER4_TIMER0

kXBARA1_OutputQtimer4Timer1 

XBARA1_OUT151 output assigned to QTIMER4_TIMER1

kXBARA1_OutputQtimer4Timer2 

XBARA1_OUT152 output assigned to QTIMER4_TIMER2

kXBARA1_OutputQtimer4Timer3 

XBARA1_OUT153 output assigned to QTIMER4_TIMER3

kXBARA1_OutputEwmEwmIn 

XBARA1_OUT154 output assigned to EWM_EWM_IN

kXBARA1_OutputAdcEtc0Coco0 

XBARA1_OUT155 output assigned to ADC_ETC0_COCO0

kXBARA1_OutputAdcEtc0Coco1 

XBARA1_OUT156 output assigned to ADC_ETC0_COCO1

kXBARA1_OutputAdcEtc0Coco2 

XBARA1_OUT157 output assigned to ADC_ETC0_COCO2

kXBARA1_OutputAdcEtc0Coco3 

XBARA1_OUT158 output assigned to ADC_ETC0_COCO3

kXBARA1_OutputAdcEtc1Coco0 

XBARA1_OUT159 output assigned to ADC_ETC1_COCO0

kXBARA1_OutputAdcEtc1Coco1 

XBARA1_OUT160 output assigned to ADC_ETC1_COCO1

kXBARA1_OutputAdcEtc1Coco2 

XBARA1_OUT161 output assigned to ADC_ETC1_COCO2

kXBARA1_OutputAdcEtc1Coco3 

XBARA1_OUT162 output assigned to ADC_ETC1_COCO3

kXBARA1_OutputRESERVED163 

XBARA1_OUT163 output is reserved.

kXBARA1_OutputRESERVED164 

XBARA1_OUT164 output is reserved.

kXBARA1_OutputRESERVED165 

XBARA1_OUT165 output is reserved.

kXBARA1_OutputRESERVED166 

XBARA1_OUT166 output is reserved.

kXBARA1_OutputRESERVED167 

XBARA1_OUT167 output is reserved.

kXBARA1_OutputRESERVED168 

XBARA1_OUT168 output is reserved.

kXBARA1_OutputRESERVED169 

XBARA1_OUT169 output is reserved.

kXBARA1_OutputRESERVED170 

XBARA1_OUT170 output is reserved.

kXBARA1_OutputFlexio1TrigIn0 

XBARA1_OUT171 output assigned to FLEXIO1_TRIG_IN0

kXBARA1_OutputFlexio1TrigIn1 

XBARA1_OUT172 output assigned to FLEXIO1_TRIG_IN1

kXBARA1_OutputFlexio2TrigIn0 

XBARA1_OUT173 output assigned to FLEXIO2_TRIG_IN0

kXBARA1_OutputFlexio2TrigIn1 

XBARA1_OUT174 output assigned to FLEXIO2_TRIG_IN1

kXBARB2_OutputAoi1In00 

XBARB2_OUT0 output assigned to AOI1_IN00

kXBARB2_OutputAoi1In01 

XBARB2_OUT1 output assigned to AOI1_IN01

kXBARB2_OutputAoi1In02 

XBARB2_OUT2 output assigned to AOI1_IN02

kXBARB2_OutputAoi1In03 

XBARB2_OUT3 output assigned to AOI1_IN03

kXBARB2_OutputAoi1In04 

XBARB2_OUT4 output assigned to AOI1_IN04

kXBARB2_OutputAoi1In05 

XBARB2_OUT5 output assigned to AOI1_IN05

kXBARB2_OutputAoi1In06 

XBARB2_OUT6 output assigned to AOI1_IN06

kXBARB2_OutputAoi1In07 

XBARB2_OUT7 output assigned to AOI1_IN07

kXBARB2_OutputAoi1In08 

XBARB2_OUT8 output assigned to AOI1_IN08

kXBARB2_OutputAoi1In09 

XBARB2_OUT9 output assigned to AOI1_IN09

kXBARB2_OutputAoi1In10 

XBARB2_OUT10 output assigned to AOI1_IN10

kXBARB2_OutputAoi1In11 

XBARB2_OUT11 output assigned to AOI1_IN11

kXBARB2_OutputAoi1In12 

XBARB2_OUT12 output assigned to AOI1_IN12

kXBARB2_OutputAoi1In13 

XBARB2_OUT13 output assigned to AOI1_IN13

kXBARB2_OutputAoi1In14 

XBARB2_OUT14 output assigned to AOI1_IN14

kXBARB2_OutputAoi1In15 

XBARB2_OUT15 output assigned to AOI1_IN15

kXBARB3_OutputAoi2In00 

XBARB3_OUT0 output assigned to AOI2_IN00

kXBARB3_OutputAoi2In01 

XBARB3_OUT1 output assigned to AOI2_IN01

kXBARB3_OutputAoi2In02 

XBARB3_OUT2 output assigned to AOI2_IN02

kXBARB3_OutputAoi2In03 

XBARB3_OUT3 output assigned to AOI2_IN03

kXBARB3_OutputAoi2In04 

XBARB3_OUT4 output assigned to AOI2_IN04

kXBARB3_OutputAoi2In05 

XBARB3_OUT5 output assigned to AOI2_IN05

kXBARB3_OutputAoi2In06 

XBARB3_OUT6 output assigned to AOI2_IN06

kXBARB3_OutputAoi2In07 

XBARB3_OUT7 output assigned to AOI2_IN07

kXBARB3_OutputAoi2In08 

XBARB3_OUT8 output assigned to AOI2_IN08

kXBARB3_OutputAoi2In09 

XBARB3_OUT9 output assigned to AOI2_IN09

kXBARB3_OutputAoi2In10 

XBARB3_OUT10 output assigned to AOI2_IN10

kXBARB3_OutputAoi2In11 

XBARB3_OUT11 output assigned to AOI2_IN11

kXBARB3_OutputAoi2In12 

XBARB3_OUT12 output assigned to AOI2_IN12

kXBARB3_OutputAoi2In13 

XBARB3_OUT13 output assigned to AOI2_IN13

kXBARB3_OutputAoi2In14 

XBARB3_OUT14 output assigned to AOI2_IN14

kXBARB3_OutputAoi2In15 

XBARB3_OUT15 output assigned to AOI2_IN15

Variable Documentation

◆ ADD

__O uint32_t CDOG_Type::ADD

ADD Command, offset: 0x2C

◆ ADD1

__O uint32_t CDOG_Type::ADD1

ADD1 Command, offset: 0x30

◆ ADD16

__O uint32_t CDOG_Type::ADD16

ADD16 Command, offset: 0x34

◆ ADD256

__O uint32_t CDOG_Type::ADD256

ADD256 Command, offset: 0x38

◆ ADDR_OFFSET0

__IO uint32_t BEE_Type::ADDR_OFFSET0

Offset region 0 Register, offset: 0x4

◆ ADDR_OFFSET1

__IO uint32_t BEE_Type::ADDR_OFFSET1

Offset region 1 Register, offset: 0x8

◆ ADMA_ERR_STATUS

__I uint32_t USDHC_Type::ADMA_ERR_STATUS

ADMA Error Status, offset: 0x54

◆ ADMA_SYS_ADDR

__IO uint32_t USDHC_Type::ADMA_SYS_ADDR

ADMA System Address, offset: 0x58

◆ AES_KEY0_W0

__IO uint32_t BEE_Type::AES_KEY0_W0

AES Key 0 Register, offset: 0xC

◆ AES_KEY0_W1

__IO uint32_t BEE_Type::AES_KEY0_W1

AES Key 1 Register, offset: 0x10

◆ AES_KEY0_W2

__IO uint32_t BEE_Type::AES_KEY0_W2

AES Key 2 Register, offset: 0x14

◆ AES_KEY0_W3

__IO uint32_t BEE_Type::AES_KEY0_W3

AES Key 3 Register, offset: 0x18

◆ AES_TST_DB

__IO uint32_t IEE_Type::AES_TST_DB

IEE AES Test Mode Data Buffer, array offset: 0xF00, array step: 0x4

◆ AESVID

__I uint32_t IEE_Type::AESVID

IEE AES Version ID Register, offset: 0xF8

◆ AHBBUFREGIONEND0

__IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND0

RX BUF region End address of region 0, offset: 0x444

◆ AHBBUFREGIONEND1

__IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND1

RX BUF region End address of region 1, offset: 0x44C

◆ AHBBUFREGIONEND2

__IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND2

RX BUF region End address of region 2, offset: 0x454

◆ AHBBUFREGIONEND3

__IO uint32_t FLEXSPI_Type::AHBBUFREGIONEND3

RX BUF region End address of region 3, offset: 0x45C

◆ AHBBUFREGIONSTART0

__IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART0

RX BUF Start address of region 0, offset: 0x440

◆ AHBBUFREGIONSTART1

__IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART1

RX BUF Start address of region 1, offset: 0x448

◆ AHBBUFREGIONSTART2

__IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART2

RX BUF Start address of region 2, offset: 0x450

◆ AHBBUFREGIONSTART3

__IO uint32_t FLEXSPI_Type::AHBBUFREGIONSTART3

RX BUF Start address of region 3, offset: 0x458

◆ AHBCR

__IO uint32_t FLEXSPI_Type::AHBCR

AHB Bus Control Register, offset: 0xC

◆ AHBRXBUFCR0

__IO uint32_t FLEXSPI_Type::AHBRXBUFCR0

AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4

AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4

◆ AHBSPNDSTS

__I uint32_t FLEXSPI_Type::AHBSPNDSTS

AHB Suspend Status Register, offset: 0xEC

◆ ALLOW

__I uint32_t PUF_Type::ALLOW

PUF Allow Register, offset: 0x28

◆ ANA0

__IO uint32_t OCOTP_Type::ANA0

Value of OTP Bank 1 Word 5 (Analog Info.), offset: 0x4D0

◆ ANA1

__IO uint32_t OCOTP_Type::ANA1

Value of OTP Bank 1 Word 6 (Analog Info.), offset: 0x4E0

◆ ANA2

__IO uint32_t OCOTP_Type::ANA2

Value of OTP Bank 1 Word 7 (Analog Info.), offset: 0x4F0

◆ ANACTRL

__IO uint32_t USBPHY_Type::ANACTRL

USB PHY Analog Control Register, offset: 0x100

◆ ANACTRL_CLR

__IO uint32_t USBPHY_Type::ANACTRL_CLR

USB PHY Analog Control Register, offset: 0x108

◆ ANACTRL_SET

__IO uint32_t USBPHY_Type::ANACTRL_SET

USB PHY Analog Control Register, offset: 0x104

◆ ANACTRL_TOG

__IO uint32_t USBPHY_Type::ANACTRL_TOG

USB PHY Analog Control Register, offset: 0x10C

◆ ARM_PLL_CTRL

__IO uint32_t ANADIG_PLL_Type::ARM_PLL_CTRL

ARM_PLL_CTRL_REGISTER, offset: 0x200

◆ AS_BUF

__IO uint32_t PXP_Type::AS_BUF

Alpha Surface Buffer Pointer, offset: 0x160

◆ AS_CLRKEYHIGH

__IO uint32_t PXP_Type::AS_CLRKEYHIGH

Overlay Color Key High, offset: 0x190

◆ AS_CLRKEYLOW

__IO uint32_t PXP_Type::AS_CLRKEYLOW

Overlay Color Key Low, offset: 0x180

◆ AS_CTRL

__IO uint32_t PXP_Type::AS_CTRL

Alpha Surface Control, offset: 0x150

◆ AS_PITCH

__IO uint32_t PXP_Type::AS_PITCH

Alpha Surface Pitch, offset: 0x170

◆ ASR56K

__IO uint32_t ASRC_Type::ASR56K

ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C

◆ ASR76K

__IO uint32_t ASRC_Type::ASR76K

ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98

◆ ASRCCR

__IO uint32_t ASRC_Type::ASRCCR

ASRC Channel Counter Register, offset: 0x5C

◆ ASRCDR1

__IO uint32_t ASRC_Type::ASRCDR1

ASRC Clock Divider Register 1, offset: 0x18

◆ ASRCDR2

__IO uint32_t ASRC_Type::ASRCDR2

ASRC Clock Divider Register 2, offset: 0x1C

◆ ASRCFG

__IO uint32_t ASRC_Type::ASRCFG

ASRC Filter Configuration Status Register, offset: 0x10

◆ ASRCNCR

__IO uint32_t ASRC_Type::ASRCNCR

ASRC Channel Number Configuration Register, offset: 0xC

◆ ASRCSR

__IO uint32_t ASRC_Type::ASRCSR

ASRC Clock Source Register, offset: 0x14

◆ ASRCTR

__IO uint32_t ASRC_Type::ASRCTR

ASRC Control Register, offset: 0x0

◆ ASRDIA

__O uint32_t ASRC_Type::ASRDIA

ASRC Data Input Register for Pair x, offset: 0x60

◆ ASRDIB

__O uint32_t ASRC_Type::ASRDIB

ASRC Data Input Register for Pair x, offset: 0x68

◆ ASRDIC

__O uint32_t ASRC_Type::ASRDIC

ASRC Data Input Register for Pair x, offset: 0x70

◆ ASRDOA

__I uint32_t ASRC_Type::ASRDOA

ASRC Data Output Register for Pair x, offset: 0x64

◆ ASRDOB

__I uint32_t ASRC_Type::ASRDOB

ASRC Data Output Register for Pair x, offset: 0x6C

◆ ASRDOC

__I uint32_t ASRC_Type::ASRDOC

ASRC Data Output Register for Pair x, offset: 0x74

◆ ASRFSTA

__I uint32_t ASRC_Type::ASRFSTA

ASRC FIFO Status Register for Pair A, offset: 0xA4

◆ ASRFSTB

__I uint32_t ASRC_Type::ASRFSTB

ASRC FIFO Status Register for Pair B, offset: 0xAC

◆ ASRFSTC

__I uint32_t ASRC_Type::ASRFSTC

ASRC FIFO Status Register for Pair C, offset: 0xB4

◆ ASRIDRHA

__IO uint32_t ASRC_Type::ASRIDRHA

ASRC Ideal Ratio for Pair A-High Part, offset: 0x80

◆ ASRIDRHB

__IO uint32_t ASRC_Type::ASRIDRHB

ASRC Ideal Ratio for Pair B-High Part, offset: 0x88

◆ ASRIDRHC

__IO uint32_t ASRC_Type::ASRIDRHC

ASRC Ideal Ratio for Pair C-High Part, offset: 0x90

◆ ASRIDRLA

__IO uint32_t ASRC_Type::ASRIDRLA

ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84

◆ ASRIDRLB

__IO uint32_t ASRC_Type::ASRIDRLB

ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C

◆ ASRIDRLC

__IO uint32_t ASRC_Type::ASRIDRLC

ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94

◆ ASRIER

__IO uint32_t ASRC_Type::ASRIER

ASRC Interrupt Enable Register, offset: 0x4

◆ ASRMCR1

__IO uint32_t ASRC_Type::ASRMCR1

ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4

◆ ASRMCRA

__IO uint32_t ASRC_Type::ASRMCRA

ASRC Misc Control Register for Pair A, offset: 0xA0

◆ ASRMCRB

__IO uint32_t ASRC_Type::ASRMCRB

ASRC Misc Control Register for Pair B, offset: 0xA8

◆ ASRMCRC

__IO uint32_t ASRC_Type::ASRMCRC

ASRC Misc Control Register for Pair C, offset: 0xB0

◆ ASRPM

__IO uint32_t ASRC_Type::ASRPM

ASRC Parameter Register n, array offset: 0x40, array step: 0x4

◆ ASRSTR

__I uint32_t ASRC_Type::ASRSTR

ASRC Status Register, offset: 0x20

◆ ASRTFR1

__IO uint32_t ASRC_Type::ASRTFR1

ASRC Task Queue FIFO Register 1, offset: 0x54

◆ ASYNCLISTADDR [1/4]

__IO uint32_t USB_Type::ASYNCLISTADDR

Next Asynch. Address, offset: 0x158

◆  [2/4]

__IO uint32_t { ... } ::ASYNCLISTADDR

Next Asynch. Address, offset: 0x158

◆  [3/4]

__IO uint32_t { ... } ::ASYNCLISTADDR

Next Asynch. Address, offset: 0x158

◆  [4/4]

__IO uint32_t { ... } ::ASYNCLISTADDR

Next Asynch. Address, offset: 0x158

◆ ATCOR

__IO uint32_t ENET_Type::ATCOR

Timer Correction Register, offset: 0x410

◆ ATCR

__IO uint32_t ENET_Type::ATCR

Adjustable Timer Control Register, offset: 0x400

◆ ATINC

__IO uint32_t ENET_Type::ATINC

Time-Stamping Clock Period Register, offset: 0x414

◆ ATOFF

__IO uint32_t ENET_Type::ATOFF

Timer Offset Register, offset: 0x408

◆ ATPER

__IO uint32_t ENET_Type::ATPER

Timer Period Register, offset: 0x40C

◆ ATSTMP

__I uint32_t ENET_Type::ATSTMP

Timestamp of Last Transmitted Frame, offset: 0x418

◆ ATTR [1/4]

__IO uint16_t DMA_Type::ATTR

TCD Transfer Attributes, array offset: 0x1006, array step: 0x20

◆  [2/4]

__IO uint16_t { ... } ::ATTR

TCD Transfer Attributes, array offset: 0x1006, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::ATTR

TCD Transfer Attributes, array offset: 0x1006, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::ATTR

TCD Transfer Attributes, array offset: 0x1006, array step: 0x20

◆ ATVR

__IO uint32_t ENET_Type::ATVR

Timer Value Register, offset: 0x404

◆  [1/14]

__IO uint32_t { ... } ::AUTHEN

Clock root access control, array offset: 0x30, array step: 0x80

◆ AUTHEN [2/14]

__IO uint32_t CCM_Type::AUTHEN

Clock root access control, array offset: 0x30, array step: 0x80

Clock group access control, array offset: 0x4030, array step: 0x80

GPR access control, array offset: 0x4810, array step: 0x20

Clock source access control, array offset: 0x501C, array step: 0x20

LPCG access control, array offset: 0x601C, array step: 0x20

◆  [3/14]

__IO uint32_t { ... } ::AUTHEN

Clock group access control, array offset: 0x4030, array step: 0x80

◆  [4/14]

__IO uint32_t { ... } ::AUTHEN

GPR access control, array offset: 0x4810, array step: 0x20

◆  [5/14]

__IO uint32_t { ... } ::AUTHEN

Clock source access control, array offset: 0x501C, array step: 0x20

◆  [6/14]

__IO uint32_t { ... } ::AUTHEN

LPCG access control, array offset: 0x601C, array step: 0x20

◆  [7/14]

__IO uint32_t { ... } ::AUTHEN

Observe access control, array offset: 0x30, array step: 0x80

◆ AUTHEN [8/14]

__IO uint32_t CCM_OBS_Type::AUTHEN

Observe access control, array offset: 0x30, array step: 0x80

◆  [9/14]

__IO uint32_t { ... } ::AUTHEN

Clock root access control, array offset: 0x30, array step: 0x80

◆  [10/14]

__IO uint32_t { ... } ::AUTHEN

Clock group access control, array offset: 0x4030, array step: 0x80

◆  [11/14]

__IO uint32_t { ... } ::AUTHEN

GPR access control, array offset: 0x4810, array step: 0x20

◆  [12/14]

__IO uint32_t { ... } ::AUTHEN

Clock source access control, array offset: 0x501C, array step: 0x20

◆  [13/14]

__IO uint32_t { ... } ::AUTHEN

LPCG access control, array offset: 0x601C, array step: 0x20

◆  [14/14]

__IO uint32_t { ... } ::AUTHEN

Observe access control, array offset: 0x30, array step: 0x80

◆  [1/10]

__IO uint32_t { ... } ::AUTHEN_CLR

Clock root access control, array offset: 0x38, array step: 0x80

◆ AUTHEN_CLR [2/10]

__IO uint32_t CCM_Type::AUTHEN_CLR

Clock root access control, array offset: 0x38, array step: 0x80

Clock group access control, array offset: 0x4038, array step: 0x80

GPR access control, array offset: 0x4818, array step: 0x20

◆  [3/10]

__IO uint32_t { ... } ::AUTHEN_CLR

Clock group access control, array offset: 0x4038, array step: 0x80

◆  [4/10]

__IO uint32_t { ... } ::AUTHEN_CLR

GPR access control, array offset: 0x4818, array step: 0x20

◆  [5/10]

__IO uint32_t { ... } ::AUTHEN_CLR

Observe access control, array offset: 0x38, array step: 0x80

◆ AUTHEN_CLR [6/10]

__IO uint32_t CCM_OBS_Type::AUTHEN_CLR

Observe access control, array offset: 0x38, array step: 0x80

◆  [7/10]

__IO uint32_t { ... } ::AUTHEN_CLR

Clock root access control, array offset: 0x38, array step: 0x80

◆  [8/10]

__IO uint32_t { ... } ::AUTHEN_CLR

Clock group access control, array offset: 0x4038, array step: 0x80

◆  [9/10]

__IO uint32_t { ... } ::AUTHEN_CLR

GPR access control, array offset: 0x4818, array step: 0x20

◆  [10/10]

__IO uint32_t { ... } ::AUTHEN_CLR

Observe access control, array offset: 0x38, array step: 0x80

◆ AUTHEN_DISPLAY

__IO uint32_t SRC_Type::AUTHEN_DISPLAY

Slice Authentication Register, offset: 0x220

◆ AUTHEN_M4CORE

__IO uint32_t SRC_Type::AUTHEN_M4CORE

Slice Authentication Register, offset: 0x280

◆ AUTHEN_M4DEBUG

__IO uint32_t SRC_Type::AUTHEN_M4DEBUG

Slice Authentication Register, offset: 0x2C0

◆ AUTHEN_M7CORE

__IO uint32_t SRC_Type::AUTHEN_M7CORE

Slice Authentication Register, offset: 0x2A0

◆ AUTHEN_M7DEBUG

__IO uint32_t SRC_Type::AUTHEN_M7DEBUG

Slice Authentication Register, offset: 0x2E0

◆ AUTHEN_MEGA

__IO uint32_t SRC_Type::AUTHEN_MEGA

Slice Authentication Register, offset: 0x200

◆ AUTHEN_SET [1/10]

__IO uint32_t CCM_Type::AUTHEN_SET

Clock root access control, array offset: 0x34, array step: 0x80

Clock group access control, array offset: 0x4034, array step: 0x80

GPR access control, array offset: 0x4814, array step: 0x20

◆  [2/10]

__IO uint32_t { ... } ::AUTHEN_SET

Clock root access control, array offset: 0x34, array step: 0x80

◆  [3/10]

__IO uint32_t { ... } ::AUTHEN_SET

Clock group access control, array offset: 0x4034, array step: 0x80

◆  [4/10]

__IO uint32_t { ... } ::AUTHEN_SET

GPR access control, array offset: 0x4814, array step: 0x20

◆ AUTHEN_SET [5/10]

__IO uint32_t CCM_OBS_Type::AUTHEN_SET

Observe access control, array offset: 0x34, array step: 0x80

◆  [6/10]

__IO uint32_t { ... } ::AUTHEN_SET

Observe access control, array offset: 0x34, array step: 0x80

◆  [7/10]

__IO uint32_t { ... } ::AUTHEN_SET

Clock root access control, array offset: 0x34, array step: 0x80

◆  [8/10]

__IO uint32_t { ... } ::AUTHEN_SET

Clock group access control, array offset: 0x4034, array step: 0x80

◆  [9/10]

__IO uint32_t { ... } ::AUTHEN_SET

GPR access control, array offset: 0x4814, array step: 0x20

◆  [10/10]

__IO uint32_t { ... } ::AUTHEN_SET

Observe access control, array offset: 0x34, array step: 0x80

◆ AUTHEN_TOG [1/10]

__IO uint32_t CCM_Type::AUTHEN_TOG

Clock root access control, array offset: 0x3C, array step: 0x80

Clock group access control, array offset: 0x403C, array step: 0x80

GPR access control, array offset: 0x481C, array step: 0x20

◆  [2/10]

__IO uint32_t { ... } ::AUTHEN_TOG

Clock root access control, array offset: 0x3C, array step: 0x80

◆  [3/10]

__IO uint32_t { ... } ::AUTHEN_TOG

Clock group access control, array offset: 0x403C, array step: 0x80

◆  [4/10]

__IO uint32_t { ... } ::AUTHEN_TOG

GPR access control, array offset: 0x481C, array step: 0x20

◆ AUTHEN_TOG [5/10]

__IO uint32_t CCM_OBS_Type::AUTHEN_TOG

Observe access control, array offset: 0x3C, array step: 0x80

◆  [6/10]

__IO uint32_t { ... } ::AUTHEN_TOG

Observe access control, array offset: 0x3C, array step: 0x80

◆  [7/10]

__IO uint32_t { ... } ::AUTHEN_TOG

Clock root access control, array offset: 0x3C, array step: 0x80

◆  [8/10]

__IO uint32_t { ... } ::AUTHEN_TOG

Clock group access control, array offset: 0x403C, array step: 0x80

◆  [9/10]

__IO uint32_t { ... } ::AUTHEN_TOG

GPR access control, array offset: 0x481C, array step: 0x20

◆  [10/10]

__IO uint32_t { ... } ::AUTHEN_TOG

Observe access control, array offset: 0x3C, array step: 0x80

◆ AUTHEN_USBPHY1

__IO uint32_t SRC_Type::AUTHEN_USBPHY1

Slice Authentication Register, offset: 0x300

◆ AUTHEN_USBPHY2

__IO uint32_t SRC_Type::AUTHEN_USBPHY2

Slice Authentication Register, offset: 0x320

◆ AUTHEN_WAKEUP

__IO uint32_t SRC_Type::AUTHEN_WAKEUP

Slice Authentication Register, offset: 0x240

◆ AUTO_PD_EN

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::AUTO_PD_EN

AUTO_PD_EN, offset: 0x3C

◆ AUTOCMD12_ERR_STATUS

__IO uint32_t USDHC_Type::AUTOCMD12_ERR_STATUS

Auto CMD12 Error Status, offset: 0x3C

◆ BANDGAP_ENABLE_SP

__IO uint32_t ANADIG_PMU_Type::BANDGAP_ENABLE_SP

BANDGAP_ENABLE_SP_REGISTER, offset: 0x6F0

◆ BANDGAP_STBY_EN_SP

__IO uint32_t ANADIG_PMU_Type::BANDGAP_STBY_EN_SP

BANDGAP_STBY_EN_SP_REGISTER, offset: 0x730

◆ BASIC_SETTING

__IO uint32_t TSC_Type::BASIC_SETTING

Basic Setting, offset: 0x0

◆ BAUD

__IO uint32_t LPUART_Type::BAUD

LPUART Baud Rate Register, offset: 0x10

◆ BFCRT01 [1/4]

__IO uint16_t AOI_Type::BFCRT01

Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4

◆  [2/4]

__IO uint16_t { ... } ::BFCRT01

Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4

◆  [3/4]

__IO uint16_t { ... } ::BFCRT01

Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4

◆  [4/4]

__IO uint16_t { ... } ::BFCRT01

Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4

◆ BFCRT23 [1/4]

__IO uint16_t AOI_Type::BFCRT23

Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4

◆  [2/4]

__IO uint16_t { ... } ::BFCRT23

Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4

◆  [3/4]

__IO uint16_t { ... } ::BFCRT23

Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4

◆  [4/4]

__IO uint16_t { ... } ::BFCRT23

Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4

◆ BGT_VAL

__IO uint32_t EMVSIM_Type::BGT_VAL

Block Guard Time Value Register, offset: 0x40

◆ BIT_ERR

__I uint32_t MIPI_CSI2RX_Type::BIT_ERR

ECC and CRC Error Status Register, offset: 0x108

◆ BIT_LOCK

__IO uint32_t OCOTP_Type::BIT_LOCK

BIT_LOCK Register, offset: 0x150

◆  [1/4]

__IO uint16_t { ... } ::BITER_ELINKNO

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20

◆ BITER_ELINKNO [2/4]

__IO uint16_t DMA_Type::BITER_ELINKNO

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::BITER_ELINKNO

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::BITER_ELINKNO

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20

◆  [1/4]

__IO uint16_t { ... } ::BITER_ELINKYES

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20

◆ BITER_ELINKYES [2/4]

__IO uint16_t DMA_Type::BITER_ELINKYES

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::BITER_ELINKYES

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::BITER_ELINKYES

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20

◆ BLK_ATT

__IO uint32_t USDHC_Type::BLK_ATT

Block Attributes, offset: 0x4

◆ BLLP_MODE

__IO uint32_t DSI_HOST_DPI_INTFC_Type::BLLP_MODE

BLLP_MODE, offset: 0x34

◆ BM_ERROR_STAT

__IO uint32_t LCDIF_Type::BM_ERROR_STAT

Bus Master Error Status Register, offset: 0x190

◆ BMCR0

__IO uint32_t SEMC_Type::BMCR0

Bus (AXI) Master Control Register 0, offset: 0x8

◆ BMCR1

__IO uint32_t SEMC_Type::BMCR1

Bus (AXI) Master Control Register 1, offset: 0xC

◆ BPC_AUTHEN_CTRL

__IO uint32_t PGMC_BPC_Type::BPC_AUTHEN_CTRL

BPC Authentication Control, offset: 0x4

◆ BPC_FLAG

__IO uint32_t PGMC_BPC_Type::BPC_FLAG

BPC flag, offset: 0x2C

◆ BPC_MODE

__IO uint32_t PGMC_BPC_Type::BPC_MODE

BPC Mode, offset: 0x10

◆ BPC_POWER_CTRL

__IO uint32_t PGMC_BPC_Type::BPC_POWER_CTRL

BPC power control, offset: 0x14

◆ BPC_SSAR_RESTORE_CTRL

__IO uint32_t PGMC_BPC_Type::BPC_SSAR_RESTORE_CTRL

BPC SSAR restore control, offset: 0x44

◆ BPC_SSAR_SAVE_CTRL

__IO uint32_t PGMC_BPC_Type::BPC_SSAR_SAVE_CTRL

BPC SSAR save control, offset: 0x40

◆ BR

__IO uint32_t SEMC_Type::BR

Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4

Base Register 0..Base Register 8, array offset: 0x10, array step: 0x4

◆ BR10

__IO uint32_t SEMC_Type::BR10

Base Register 10, offset: 0x104

◆ BR11

__IO uint32_t SEMC_Type::BR11

Base Register 11, offset: 0x108

◆ BR9

__IO uint32_t SEMC_Type::BR9

Base Register 9, offset: 0x100

◆ BURSTSIZE

__IO uint32_t USB_Type::BURSTSIZE

Programmable Burst Size, offset: 0x160

◆ BWT_VAL

__IO uint32_t EMVSIM_Type::BWT_VAL

Block Wait Time Value Register, offset: 0x3C

◆ C0

__IO uint32_t CMP_Type::C0

CMP Control Register 0, offset: 0x8

◆ C1

__IO uint32_t CMP_Type::C1

CMP Control Register 1, offset: 0xC

◆ C2

__IO uint32_t CMP_Type::C2

CMP Control Register 2, offset: 0x10

◆ C3

__IO uint32_t CMP_Type::C3

CMP Control Register 3, offset: 0x14

◆ CA

__IO uint32_t MMCAU_Type::CA[9]

General Purpose Register, array offset: 0x8, array step: 0x4

◆ CAA

__IO uint32_t MMCAU_Type::CAA

Accumulator, offset: 0x4

◆ CAAMVID_LS

__I uint32_t CAAM_Type::CAAMVID_LS

CAAM Version ID Register, least-significant half, offset: 0xFFC

◆ CAAMVID_LS_DC01

__I uint32_t CAAM_Type::CAAMVID_LS_DC01

CAAM Version ID Register, least-significant half, offset: 0x80FFC

◆ CAAMVID_LS_JR [1/3]

__I uint32_t CAAM_Type::CAAMVID_LS_JR

CAAM Version ID Register, least-significant half, array offset: 0x10FFC, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::CAAMVID_LS_JR

CAAM Version ID Register, least-significant half, array offset: 0x10FFC, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CAAMVID_LS_JR

CAAM Version ID Register, least-significant half, array offset: 0x10FFC, array step: 0x10000

◆ CAAMVID_LS_RTIC

__I uint32_t CAAM_Type::CAAMVID_LS_RTIC

CAAM Version ID Register, least-significant half, offset: 0x60FFC

◆ CAAMVID_LS_TRAD

__I uint32_t CAAM_Type::CAAMVID_LS_TRAD

CAAM Version ID Register, least-significant half, offset: 0xBFC

◆ CAAMVID_MS

__I uint32_t CAAM_Type::CAAMVID_MS

CAAM Version ID Register, most-significant half, offset: 0xFF8

◆ CAAMVID_MS_DC01

__I uint32_t CAAM_Type::CAAMVID_MS_DC01

CAAM Version ID Register, most-significant half, offset: 0x80FF8

◆ CAAMVID_MS_JR [1/3]

__I uint32_t CAAM_Type::CAAMVID_MS_JR

CAAM Version ID Register, most-significant half, array offset: 0x10FF8, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::CAAMVID_MS_JR

CAAM Version ID Register, most-significant half, array offset: 0x10FF8, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CAAMVID_MS_JR

CAAM Version ID Register, most-significant half, array offset: 0x10FF8, array step: 0x10000

◆ CAAMVID_MS_RTIC

__I uint32_t CAAM_Type::CAAMVID_MS_RTIC

CAAM Version ID Register, most-significant half, offset: 0x60FF8

◆ CAAMVID_MS_TRAD

__I uint32_t CAAM_Type::CAAMVID_MS_TRAD

CAAM Version ID Register, most-significant half, offset: 0xBF8

◆ CACRR

__IO uint32_t CCM_Type::CACRR

CCM Arm Clock Root Register, offset: 0x10

◆ CAL

__IO uint32_t ADC_Type::CAL

Calibration value register, offset: 0x58

◆ CAPABILITY0

__IO uint32_t DCP_Type::CAPABILITY0

DCP capability 0 register, offset: 0x30

◆ CAPABILITY1

__I uint32_t DCP_Type::CAPABILITY1

DCP capability 1 register, offset: 0x40

◆ CAPLENGTH

__I uint8_t USB_Type::CAPLENGTH

Capability Registers Length, offset: 0x100

◆ CAPT [1/4]

__IO uint16_t TMR_Type::CAPT

Timer Channel Capture Register, array offset: 0x4, array step: 0x20

◆  [2/4]

__IO uint16_t { ... } ::CAPT

Timer Channel Capture Register, array offset: 0x4, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::CAPT

Timer Channel Capture Register, array offset: 0x4, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::CAPT

Timer Channel Capture Register, array offset: 0x4, array step: 0x20

◆  [1/4]

__IO uint16_t { ... } ::CAPTCOMPA

Capture Compare A Register, array offset: 0x36, array step: 0x60

◆ CAPTCOMPA [2/4]

__IO uint16_t PWM_Type::CAPTCOMPA

Capture Compare A Register, array offset: 0x36, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::CAPTCOMPA

Capture Compare A Register, array offset: 0x36, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::CAPTCOMPA

Capture Compare A Register, array offset: 0x36, array step: 0x60

◆  [1/4]

__IO uint16_t { ... } ::CAPTCOMPB

Capture Compare B Register, array offset: 0x3A, array step: 0x60

◆ CAPTCOMPB [2/4]

__IO uint16_t PWM_Type::CAPTCOMPB

Capture Compare B Register, array offset: 0x3A, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::CAPTCOMPB

Capture Compare B Register, array offset: 0x3A, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::CAPTCOMPB

Capture Compare B Register, array offset: 0x3A, array step: 0x60

◆ CAPTCOMPX [1/4]

__IO uint16_t PWM_Type::CAPTCOMPX

Capture Compare X Register, array offset: 0x3E, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::CAPTCOMPX

Capture Compare X Register, array offset: 0x3E, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::CAPTCOMPX

Capture Compare X Register, array offset: 0x3E, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::CAPTCOMPX

Capture Compare X Register, array offset: 0x3E, array step: 0x60

◆ CAPTCTRLA [1/4]

__IO uint16_t PWM_Type::CAPTCTRLA

Capture Control A Register, array offset: 0x34, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::CAPTCTRLA

Capture Control A Register, array offset: 0x34, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::CAPTCTRLA

Capture Control A Register, array offset: 0x34, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::CAPTCTRLA

Capture Control A Register, array offset: 0x34, array step: 0x60

◆  [1/4]

__IO uint16_t { ... } ::CAPTCTRLB

Capture Control B Register, array offset: 0x38, array step: 0x60

◆ CAPTCTRLB [2/4]

__IO uint16_t PWM_Type::CAPTCTRLB

Capture Control B Register, array offset: 0x38, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::CAPTCTRLB

Capture Control B Register, array offset: 0x38, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::CAPTCTRLB

Capture Control B Register, array offset: 0x38, array step: 0x60

◆ CAPTCTRLX [1/4]

__IO uint16_t PWM_Type::CAPTCTRLX

Capture Control X Register, array offset: 0x3C, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::CAPTCTRLX

Capture Control X Register, array offset: 0x3C, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::CAPTCTRLX

Capture Control X Register, array offset: 0x3C, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::CAPTCTRLX

Capture Control X Register, array offset: 0x3C, array step: 0x60

◆ CASR

__IO uint32_t MMCAU_Type::CASR

Status Register, offset: 0x0

◆ CBCDR

__IO uint32_t CCM_Type::CBCDR

CCM Bus Clock Divider Register, offset: 0x14

◆ CBCMR

__IO uint32_t CCM_Type::CBCMR

CCM Bus Clock Multiplexer Register, offset: 0x18

◆ CBT

__IO uint32_t CAN_Type::CBT

CAN Bit Timing register, offset: 0x50

◆ CC1AADSZR [1/3]

__IO uint32_t CAAM_Type::CC1AADSZR

CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C

◆  [2/3]

__IO uint32_t { ... } ::CC1AADSZR

CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CC1AADSZR

CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C

◆ CC1CTXR [1/3]

__IO uint32_t CAAM_Type::CC1CTXR[16]

CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4

◆  [2/3]

__IO uint32_t { ... } ::CC1CTXR[16]

CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4

◆  [3/3]

__IO uint32_t { ... } ::CC1CTXR[16]

CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4

◆  [1/3]

__IO uint64_t { ... } ::CC1DSR

CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C

◆ CC1DSR [2/3]

__IO uint64_t CAAM_Type::CC1DSR

CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C

◆  [3/3]

__IO uint64_t { ... } ::CC1DSR

CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C

◆  [1/3]

__IO uint32_t { ... } ::CC1ICVSR

CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C

◆ CC1ICVSR [2/3]

__IO uint32_t CAAM_Type::CC1ICVSR

CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CC1ICVSR

CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C

◆ CC1IVSZR [1/3]

__IO uint32_t CAAM_Type::CC1IVSZR

CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C

◆  [2/3]

__IO uint32_t { ... } ::CC1IVSZR

CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CC1IVSZR

CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C

◆  [1/3]

__IO uint32_t { ... } ::CC1KR[8]

CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4

◆ CC1KR [2/3]

__IO uint32_t CAAM_Type::CC1KR[8]

CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4

◆  [3/3]

__IO uint32_t { ... } ::CC1KR[8]

CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4

◆ CC1KSR [1/3]

__IO uint32_t CAAM_Type::CC1KSR

CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C

◆  [2/3]

__IO uint32_t { ... } ::CC1KSR

CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CC1KSR

CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C

◆  [1/3]

__IO uint32_t { ... } ::CC1MR

CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms, array offset: 0x80004, array step: 0xE3C

◆ CC1MR [2/3]

__IO uint32_t CAAM_Type::CC1MR

CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms, array offset: 0x80004, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CC1MR

CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms, array offset: 0x80004, array step: 0xE3C

◆  [1/3]

__IO uint32_t { ... } ::CC1MR_PK

CCB 0 Class 1 Mode Register Format for Public Key Algorithms, array offset: 0x80004, array step: 0xE3C

◆ CC1MR_PK [2/3]

__IO uint32_t CAAM_Type::CC1MR_PK

CCB 0 Class 1 Mode Register Format for Public Key Algorithms, array offset: 0x80004, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CC1MR_PK

CCB 0 Class 1 Mode Register Format for Public Key Algorithms, array offset: 0x80004, array step: 0xE3C

◆  [1/3]

__IO uint32_t { ... } ::CC1MR_RNG

CCB 0 Class 1 Mode Register Format for RNG4, array offset: 0x80004, array step: 0xE3C

◆ CC1MR_RNG [2/3]

__IO uint32_t CAAM_Type::CC1MR_RNG

CCB 0 Class 1 Mode Register Format for RNG4, array offset: 0x80004, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CC1MR_RNG

CCB 0 Class 1 Mode Register Format for RNG4, array offset: 0x80004, array step: 0xE3C

◆ CC2CTXR [1/3]

__IO uint32_t CAAM_Type::CC2CTXR[18]

CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4

◆  [2/3]

__IO uint32_t { ... } ::CC2CTXR[18]

CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4

◆  [3/3]

__IO uint32_t { ... } ::CC2CTXR[18]

CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4

◆ CC2DSR [1/3]

__IO uint64_t CAAM_Type::CC2DSR

CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C

◆  [2/3]

__IO uint64_t { ... } ::CC2DSR

CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C

◆  [3/3]

__IO uint64_t { ... } ::CC2DSR

CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C

◆ CC2ICVSZR [1/3]

__IO uint32_t CAAM_Type::CC2ICVSZR

CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C

◆  [2/3]

__IO uint32_t { ... } ::CC2ICVSZR

CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CC2ICVSZR

CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C

◆ CC2KEYR [1/3]

__IO uint32_t CAAM_Type::CC2KEYR[32]

CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4

◆  [2/3]

__IO uint32_t { ... } ::CC2KEYR[32]

CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4

◆  [3/3]

__IO uint32_t { ... } ::CC2KEYR[32]

CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4

◆  [1/3]

__IO uint32_t { ... } ::CC2KSR

CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C

◆ CC2KSR [2/3]

__IO uint32_t CAAM_Type::CC2KSR

CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CC2KSR

CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C

◆  [1/3]

__IO uint32_t { ... } ::CC2MR

CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C

◆ CC2MR [2/3]

__IO uint32_t CAAM_Type::CC2MR

CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CC2MR

CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C

◆ CCBVID

__I uint32_t CAAM_Type::CCBVID

CHA Cluster Block Version ID Register, offset: 0xFE4

◆ CCBVID_DC01

__I uint32_t CAAM_Type::CCBVID_DC01

CHA Cluster Block Version ID Register, offset: 0x80FE4

◆ CCBVID_JR [1/3]

__I uint32_t CAAM_Type::CCBVID_JR

CHA Cluster Block Version ID Register, array offset: 0x10FE4, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::CCBVID_JR

CHA Cluster Block Version ID Register, array offset: 0x10FE4, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CCBVID_JR

CHA Cluster Block Version ID Register, array offset: 0x10FE4, array step: 0x10000

◆ CCBVID_RTIC

__I uint32_t CAAM_Type::CCBVID_RTIC

CHA Cluster Block Version ID Register, offset: 0x60FE4

◆  [1/3]

__O uint32_t { ... } ::CCCTRL

CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C

◆ CCCTRL [2/3]

__O uint32_t CAAM_Type::CCCTRL

CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C

◆  [3/3]

__O uint32_t { ... } ::CCCTRL

CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C

◆ CCGR0

__IO uint32_t CCM_Type::CCGR0

CCM Clock Gating Register 0, offset: 0x68

◆ CCGR1

__IO uint32_t CCM_Type::CCGR1

CCM Clock Gating Register 1, offset: 0x6C

◆ CCGR2

__IO uint32_t CCM_Type::CCGR2

CCM Clock Gating Register 2, offset: 0x70

◆ CCGR3

__IO uint32_t CCM_Type::CCGR3

CCM Clock Gating Register 3, offset: 0x74

◆ CCGR4

__IO uint32_t CCM_Type::CCGR4

CCM Clock Gating Register 4, offset: 0x78

◆ CCGR5

__IO uint32_t CCM_Type::CCGR5

CCM Clock Gating Register 5, offset: 0x7C

◆ CCGR6

__IO uint32_t CCM_Type::CCGR6

CCM Clock Gating Register 6, offset: 0x80

◆ CCOSR

__IO uint32_t CCM_Type::CCOSR

CCM Clock Output Source Register, offset: 0x60

◆ CCR [1/2]

__IO uint32_t CCM_Type::CCR

CCM Control Register, offset: 0x0

◆ CCR [2/2]

__IO uint32_t LPSPI_Type::CCR

Clock Configuration Register, offset: 0x40

Clock Configuration, offset: 0x40

◆ CCSR

__IO uint32_t CCM_Type::CCSR

CCM Clock Switcher Register, offset: 0xC

◆  [1/3]

__I uint32_t { ... } ::CCSTA_LS

CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C

◆ CCSTA_LS [2/3]

__I uint32_t CAAM_Type::CCSTA_LS

CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::CCSTA_LS

CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C

◆  [1/3]

__I uint32_t { ... } ::CCSTA_MS

CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C

◆ CCSTA_MS [2/3]

__I uint32_t CAAM_Type::CCSTA_MS

CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::CCSTA_MS

CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C

◆  [1/3]

__O uint32_t { ... } ::CCWR

CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C

◆ CCWR [2/3]

__O uint32_t CAAM_Type::CCWR

CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C

◆  [3/3]

__O uint32_t { ... } ::CCWR

CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C

◆ CDCDR

__IO uint32_t CCM_Type::CDCDR

CCM D1 Clock Divider Register, offset: 0x30

◆ CDHIPR

__I uint32_t CCM_Type::CDHIPR

CCM Divider Handshake In-Process Register, offset: 0x48

◆ CDNE

__O uint8_t DMA_Type::CDNE

Clear DONE Status Bit, offset: 0x1C

◆ CEEI

__O uint8_t DMA_Type::CEEI

Clear Enable Error Interrupt, offset: 0x18

◆ CERQ

__O uint8_t DMA_Type::CERQ

Clear Enable Request, offset: 0x1A

◆ CERR

__O uint8_t DMA_Type::CERR

Clear Error, offset: 0x1E

◆ CFG [1/2]

__IO uint32_t ADC_Type::CFG

Configuration register, offset: 0x44

LPADC Configuration Register, offset: 0x20

◆ CFG [2/2]

__IO uint32_t PUF_Type::CFG

PUF Configuration Register, offset: 0x10C

◆ CFG0

__IO uint32_t OCOTP_Type::CFG0

Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410

◆ CFG1

__IO uint32_t OCOTP_Type::CFG1

Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420

◆ CFG2

__IO uint32_t OCOTP_Type::CFG2

Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430

◆ CFG3

__IO uint32_t OCOTP_Type::CFG3

Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440

◆ CFG4

__IO uint32_t OCOTP_Type::CFG4

Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450

◆ CFG5

__IO uint32_t OCOTP_Type::CFG5

Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460

◆ CFG6

__IO uint32_t OCOTP_Type::CFG6

Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470

◆ CFG_AUTOINSERT_EOTP

__IO uint32_t DSI_HOST_Type::CFG_AUTOINSERT_EOTP

CFG_AUTOINSERT_ETOP, offset: 0x14

◆ CFG_BTA_H_TO_COUNT

__IO uint32_t DSI_HOST_Type::CFG_BTA_H_TO_COUNT

CFG_BTA_H_TO_COUNT, offset: 0x24

◆ CFG_DISABLE_DATA_LANES

__IO uint32_t MIPI_CSI2RX_Type::CFG_DISABLE_DATA_LANES

Disable Data Lane Register, offset: 0x104

◆ CFG_DISABLE_PAYLOAD_0

__IO uint32_t MIPI_CSI2RX_Type::CFG_DISABLE_PAYLOAD_0

Disable Payload 0 Register, offset: 0x12C

◆ CFG_DISABLE_PAYLOAD_1

__IO uint32_t MIPI_CSI2RX_Type::CFG_DISABLE_PAYLOAD_1

Disable Payload 1 Register, offset: 0x130

◆ CFG_EXTRA_CMDS_AFTER_EOTP

__IO uint32_t DSI_HOST_Type::CFG_EXTRA_CMDS_AFTER_EOTP

CFG_EXTRA_CMDS_AFTER_ETOP, offset: 0x18

◆ CFG_HTX_TO_COUNT

__IO uint32_t DSI_HOST_Type::CFG_HTX_TO_COUNT

CFG_HTX_TO_COUNT, offset: 0x1C

◆ CFG_IGNORE_VC

__IO uint32_t MIPI_CSI2RX_Type::CFG_IGNORE_VC

Ignore Virtual Channel Register, offset: 0x180

◆ CFG_LRX_H_TO_COUNT

__IO uint32_t DSI_HOST_Type::CFG_LRX_H_TO_COUNT

CFG_LRX_H_TO_COUNT, offset: 0x20

◆ CFG_NONCONTINUOUS_CLK

__IO uint32_t DSI_HOST_Type::CFG_NONCONTINUOUS_CLK

CFG_NONCONTINUOUS_CLK, offset: 0x4

◆ CFG_NUM_LANES [1/2]

__IO uint32_t DSI_HOST_Type::CFG_NUM_LANES

CFG_NUM_LANES, offset: 0x0

◆ CFG_NUM_LANES [2/2]

__IO uint32_t MIPI_CSI2RX_Type::CFG_NUM_LANES

Lane Configuration Register, offset: 0x100

◆ CFG_STATUS_OUT

__I uint32_t DSI_HOST_Type::CFG_STATUS_OUT

CFG_STATUS_OUT, offset: 0x2C

◆ CFG_T_POST

__IO uint32_t DSI_HOST_Type::CFG_T_POST

CFG_T_POST, offset: 0xC

◆ CFG_T_PRE

__IO uint32_t DSI_HOST_Type::CFG_T_PRE

CFG_T_PRE, offset: 0x8

◆ CFG_TWAKEUP

__IO uint32_t DSI_HOST_Type::CFG_TWAKEUP

CFG_TWAKEUP, offset: 0x28

◆ CFG_TX_GAP

__IO uint32_t DSI_HOST_Type::CFG_TX_GAP

CFG_TX_GAP, offset: 0x10

◆ CFG_VID_HSYNC

__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_HSYNC

HSYNC Configuration Register, offset: 0x194

◆ CFG_VID_HSYNC_BP

__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_HSYNC_BP

End of HSYNC Delay Control Register, offset: 0x198

◆ CFG_VID_HSYNC_FP

__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_HSYNC_FP

Start of HSYNC Delay control Register, offset: 0x190

◆ CFG_VID_P_FIFO_SEND_LEVEL

__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_P_FIFO_SEND_LEVEL

FIFO Send Level Configuration Register, offset: 0x188

◆ CFG_VID_VC

__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_VC

Virtual Channel value Register, offset: 0x184

◆ CFG_VID_VSYNC

__IO uint32_t MIPI_CSI2RX_Type::CFG_VID_VSYNC

VSYNC Configuration Register, offset: 0x18C

◆ CFGR0

__IO uint32_t LPSPI_Type::CFGR0

Configuration Register 0, offset: 0x20

Configuration 0, offset: 0x20

◆ CFGR1

__IO uint32_t LPSPI_Type::CFGR1

Configuration Register 1, offset: 0x24

Configuration 1, offset: 0x24

◆ CFIFOSTA [1/3]

__I uint32_t CAAM_Type::CFIFOSTA

CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C

◆  [2/3]

__I uint32_t { ... } ::CFIFOSTA

CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::CFIFOSTA

CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C

◆ CGPR

__IO uint32_t CCM_Type::CGPR

CCM General Purpose Register, offset: 0x64

◆ CH0CMDPTR

__IO uint32_t DCP_Type::CH0CMDPTR

DCP channel 0 command pointer address register, offset: 0x100

◆ CH0OPTS

__IO uint32_t DCP_Type::CH0OPTS

DCP channel 0 options register, offset: 0x130

◆ CH0OPTS_CLR

__IO uint32_t DCP_Type::CH0OPTS_CLR

DCP channel 0 options register, offset: 0x138

◆ CH0OPTS_SET

__IO uint32_t DCP_Type::CH0OPTS_SET

DCP channel 0 options register, offset: 0x134

◆ CH0OPTS_TOG

__IO uint32_t DCP_Type::CH0OPTS_TOG

DCP channel 0 options register, offset: 0x13C

◆ CH0SEMA

__IO uint32_t DCP_Type::CH0SEMA

DCP channel 0 semaphore register, offset: 0x110

◆ CH0STAT

__IO uint32_t DCP_Type::CH0STAT

DCP channel 0 status register, offset: 0x120

◆ CH0STAT_CLR

__IO uint32_t DCP_Type::CH0STAT_CLR

DCP channel 0 status register, offset: 0x128

◆ CH0STAT_SET

__IO uint32_t DCP_Type::CH0STAT_SET

DCP channel 0 status register, offset: 0x124

◆ CH0STAT_TOG

__IO uint32_t DCP_Type::CH0STAT_TOG

DCP channel 0 status register, offset: 0x12C

◆ CH1CMDPTR

__IO uint32_t DCP_Type::CH1CMDPTR

DCP channel 1 command pointer address register, offset: 0x140

◆ CH1OPTS

__IO uint32_t DCP_Type::CH1OPTS

DCP channel 1 options register, offset: 0x170

◆ CH1OPTS_CLR

__IO uint32_t DCP_Type::CH1OPTS_CLR

DCP channel 1 options register, offset: 0x178

◆ CH1OPTS_SET

__IO uint32_t DCP_Type::CH1OPTS_SET

DCP channel 1 options register, offset: 0x174

◆ CH1OPTS_TOG

__IO uint32_t DCP_Type::CH1OPTS_TOG

DCP channel 1 options register, offset: 0x17C

◆ CH1SEMA

__IO uint32_t DCP_Type::CH1SEMA

DCP channel 1 semaphore register, offset: 0x150

◆ CH1STAT

__IO uint32_t DCP_Type::CH1STAT

DCP channel 1 status register, offset: 0x160

◆ CH1STAT_CLR

__IO uint32_t DCP_Type::CH1STAT_CLR

DCP channel 1 status register, offset: 0x168

◆ CH1STAT_SET

__IO uint32_t DCP_Type::CH1STAT_SET

DCP channel 1 status register, offset: 0x164

◆ CH1STAT_TOG

__IO uint32_t DCP_Type::CH1STAT_TOG

DCP channel 1 status register, offset: 0x16C

◆ CH2CMDPTR

__IO uint32_t DCP_Type::CH2CMDPTR

DCP channel 2 command pointer address register, offset: 0x180

◆ CH2OPTS

__IO uint32_t DCP_Type::CH2OPTS

DCP channel 2 options register, offset: 0x1B0

◆ CH2OPTS_CLR

__IO uint32_t DCP_Type::CH2OPTS_CLR

DCP channel 2 options register, offset: 0x1B8

◆ CH2OPTS_SET

__IO uint32_t DCP_Type::CH2OPTS_SET

DCP channel 2 options register, offset: 0x1B4

◆ CH2OPTS_TOG

__IO uint32_t DCP_Type::CH2OPTS_TOG

DCP channel 2 options register, offset: 0x1BC

◆ CH2SEMA

__IO uint32_t DCP_Type::CH2SEMA

DCP channel 2 semaphore register, offset: 0x190

◆ CH2STAT

__IO uint32_t DCP_Type::CH2STAT

DCP channel 2 status register, offset: 0x1A0

◆ CH2STAT_CLR

__IO uint32_t DCP_Type::CH2STAT_CLR

DCP channel 2 status register, offset: 0x1A8

◆ CH2STAT_SET

__IO uint32_t DCP_Type::CH2STAT_SET

DCP channel 2 status register, offset: 0x1A4

◆ CH2STAT_TOG

__IO uint32_t DCP_Type::CH2STAT_TOG

DCP channel 2 status register, offset: 0x1AC

◆ CH3CMDPTR

__IO uint32_t DCP_Type::CH3CMDPTR

DCP channel 3 command pointer address register, offset: 0x1C0

◆ CH3OPTS

__IO uint32_t DCP_Type::CH3OPTS

DCP channel 3 options register, offset: 0x1F0

◆ CH3OPTS_CLR

__IO uint32_t DCP_Type::CH3OPTS_CLR

DCP channel 3 options register, offset: 0x1F8

◆ CH3OPTS_SET

__IO uint32_t DCP_Type::CH3OPTS_SET

DCP channel 3 options register, offset: 0x1F4

◆ CH3OPTS_TOG

__IO uint32_t DCP_Type::CH3OPTS_TOG

DCP channel 3 options register, offset: 0x1FC

◆ CH3SEMA

__IO uint32_t DCP_Type::CH3SEMA

DCP channel 3 semaphore register, offset: 0x1D0

◆ CH3STAT

__IO uint32_t DCP_Type::CH3STAT

DCP channel 3 status register, offset: 0x1E0

◆ CH3STAT_CLR

__IO uint32_t DCP_Type::CH3STAT_CLR

DCP channel 3 status register, offset: 0x1E8

◆ CH3STAT_SET

__IO uint32_t DCP_Type::CH3STAT_SET

DCP channel 3 status register, offset: 0x1E4

◆ CH3STAT_TOG

__IO uint32_t DCP_Type::CH3STAT_TOG

DCP channel 3 status register, offset: 0x1EC

◆ CHANNELCTRL

__IO uint32_t DCP_Type::CHANNELCTRL

DCP channel control register, offset: 0x20

◆ CHANNELCTRL_CLR

__IO uint32_t DCP_Type::CHANNELCTRL_CLR

DCP channel control register, offset: 0x28

◆ CHANNELCTRL_SET

__IO uint32_t DCP_Type::CHANNELCTRL_SET

DCP channel control register, offset: 0x24

◆ CHANNELCTRL_TOG

__IO uint32_t DCP_Type::CHANNELCTRL_TOG

DCP channel control register, offset: 0x2C

◆ CHANUM_LS

__I uint32_t CAAM_Type::CHANUM_LS

CHA Number Register, least-significant half, offset: 0xFF4

◆ CHANUM_LS_DC01

__I uint32_t CAAM_Type::CHANUM_LS_DC01

CHA Number Register, least-significant half, offset: 0x80FF4

◆  [1/3]

__I uint32_t { ... } ::CHANUM_LS_JR

CHA Number Register, least-significant half, array offset: 0x10FF4, array step: 0x10000

◆ CHANUM_LS_JR [2/3]

__I uint32_t CAAM_Type::CHANUM_LS_JR

CHA Number Register, least-significant half, array offset: 0x10FF4, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CHANUM_LS_JR

CHA Number Register, least-significant half, array offset: 0x10FF4, array step: 0x10000

◆ CHANUM_LS_RTIC

__I uint32_t CAAM_Type::CHANUM_LS_RTIC

CHA Number Register, least-significant half, offset: 0x60FF4

◆ CHANUM_MS

__I uint32_t CAAM_Type::CHANUM_MS

CHA Number Register, most-significant half, offset: 0xFF0

◆ CHANUM_MS_DC01

__I uint32_t CAAM_Type::CHANUM_MS_DC01

CHA Number Register, most-significant half, offset: 0x80FF0

◆ CHANUM_MS_JR [1/3]

__I uint32_t CAAM_Type::CHANUM_MS_JR

CHA Number Register, most-significant half, array offset: 0x10FF0, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::CHANUM_MS_JR

CHA Number Register, most-significant half, array offset: 0x10FF0, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CHANUM_MS_JR

CHA Number Register, most-significant half, array offset: 0x10FF0, array step: 0x10000

◆ CHANUM_MS_RTIC

__I uint32_t CAAM_Type::CHANUM_MS_RTIC

CHA Number Register, most-significant half, offset: 0x60FF0

◆ CHAVID_LS

__I uint32_t CAAM_Type::CHAVID_LS

CHA Version ID Register, least-significant half, offset: 0xFEC

◆ CHAVID_LS_DC01

__I uint32_t CAAM_Type::CHAVID_LS_DC01

CHA Version ID Register, least-significant half, offset: 0x80FEC

◆ CHAVID_LS_JR [1/3]

__I uint32_t CAAM_Type::CHAVID_LS_JR

CHA Version ID Register, least-significant half, array offset: 0x10FEC, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::CHAVID_LS_JR

CHA Version ID Register, least-significant half, array offset: 0x10FEC, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CHAVID_LS_JR

CHA Version ID Register, least-significant half, array offset: 0x10FEC, array step: 0x10000

◆ CHAVID_LS_RTIC

__I uint32_t CAAM_Type::CHAVID_LS_RTIC

CHA Version ID Register, least-significant half, offset: 0x60FEC

◆ CHAVID_MS

__I uint32_t CAAM_Type::CHAVID_MS

CHA Version ID Register, most-significant half, offset: 0xFE8

◆ CHAVID_MS_DC01

__I uint32_t CAAM_Type::CHAVID_MS_DC01

CHA Version ID Register, most-significant half, offset: 0x80FE8

◆ CHAVID_MS_JR [1/3]

__I uint32_t CAAM_Type::CHAVID_MS_JR

CHA Version ID Register, most-significant half, array offset: 0x10FE8, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::CHAVID_MS_JR

CHA Version ID Register, most-significant half, array offset: 0x10FE8, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CHAVID_MS_JR

CHA Version ID Register, most-significant half, array offset: 0x10FE8, array step: 0x10000

◆ CHAVID_MS_RTIC

__I uint32_t CAAM_Type::CHAVID_MS_RTIC

CHA Version ID Register, most-significant half, offset: 0x60FE8

◆ CHCFG

__IO uint32_t DMAMUX_Type::CHCFG

Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4

◆  [1/2]

__IO uint32_t { ... } ::CHRG_DETECT

USB Charger Detect Register, array offset: 0x1B0, array step: 0x60

◆ CHRG_DETECT [2/2]

__IO uint32_t USB_ANALOG_Type::CHRG_DETECT

USB Charger Detect Register, array offset: 0x1B0, array step: 0x60

◆  [1/2]

__IO uint32_t { ... } ::CHRG_DETECT_CLR

USB Charger Detect Register, array offset: 0x1B8, array step: 0x60

◆ CHRG_DETECT_CLR [2/2]

__IO uint32_t USB_ANALOG_Type::CHRG_DETECT_CLR

USB Charger Detect Register, array offset: 0x1B8, array step: 0x60

◆  [1/2]

__IO uint32_t { ... } ::CHRG_DETECT_SET

USB Charger Detect Register, array offset: 0x1B4, array step: 0x60

◆ CHRG_DETECT_SET [2/2]

__IO uint32_t USB_ANALOG_Type::CHRG_DETECT_SET

USB Charger Detect Register, array offset: 0x1B4, array step: 0x60

◆  [1/2]

__I uint32_t { ... } ::CHRG_DETECT_STAT

USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60

◆ CHRG_DETECT_STAT [2/2]

__I uint32_t USB_ANALOG_Type::CHRG_DETECT_STAT

USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60

◆  [1/2]

__IO uint32_t { ... } ::CHRG_DETECT_TOG

USB Charger Detect Register, array offset: 0x1BC, array step: 0x60

◆ CHRG_DETECT_TOG [2/2]

__IO uint32_t USB_ANALOG_Type::CHRG_DETECT_TOG

USB Charger Detect Register, array offset: 0x1BC, array step: 0x60

◆  [1/3]

__IO uint32_t { ... } ::CICTL

CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C

◆ CICTL [2/3]

__IO uint32_t CAAM_Type::CICTL

CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CICTL

CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C

◆ CIFIFO [1/3]

__O uint32_t CAAM_Type::CIFIFO

CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C

◆  [2/3]

__O uint32_t { ... } ::CIFIFO

CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C

◆  [3/3]

__O uint32_t { ... } ::CIFIFO

CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C

◆ CIMR

__IO uint32_t CCM_Type::CIMR

CCM Interrupt Mask Register, offset: 0x5C

◆ CINT

__O uint8_t DMA_Type::CINT

Clear Interrupt Request, offset: 0x1F

◆ CISR

__IO uint32_t CCM_Type::CISR

CCM Interrupt Status Register, offset: 0x58

◆ CITER_ELINKNO [1/4]

__IO uint16_t DMA_Type::CITER_ELINKNO

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20

◆  [2/4]

__IO uint16_t { ... } ::CITER_ELINKNO

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::CITER_ELINKNO

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::CITER_ELINKNO

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20

◆  [1/4]

__IO uint16_t { ... } ::CITER_ELINKYES

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20

◆ CITER_ELINKYES [2/4]

__IO uint16_t DMA_Type::CITER_ELINKYES

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::CITER_ELINKYES

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::CITER_ELINKYES

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20

◆ CLK_TUNE_CTRL_STATUS

__IO uint32_t USDHC_Type::CLK_TUNE_CTRL_STATUS

CLK Tuning Control and Status, offset: 0x68

◆ CLKCFG

__IO uint32_t EMVSIM_Type::CLKCFG

Clock Configuration Register, offset: 0x8

◆ CLKCTRL

__IO uint8_t EWM_Type::CLKCTRL

Clock Control Register, offset: 0x4

◆ CLKPRESCALER

__IO uint8_t EWM_Type::CLKPRESCALER

Clock Prescaler Register, offset: 0x5

◆ CLOCK

__IO uint32_t USBHSDCD_Type::CLOCK

Clock register, offset: 0x4

◆ CLPCR

__IO uint32_t CCM_Type::CLPCR

CCM Low Power Control Register, offset: 0x54

◆ CLR [1/69]

__IO uint32_t AUDIO_PLL_Type::CLR

Fractional PLL Control Register, offset: 0x8

Fractional PLL Spread Spectrum Control Register, offset: 0x18

Fractional PLL Numerator Control Register, offset: 0x28

Fractional PLL Denominator Control Register, offset: 0x38

◆  [2/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Control Register, offset: 0x8

◆  [3/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Spread Spectrum Control Register, offset: 0x18

◆  [4/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Numerator Control Register, offset: 0x28

◆  [5/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Denominator Control Register, offset: 0x38

◆ CLR [6/69]

__IO uint32_t CCM_Type::CLR

General Purpose Register, array offset: 0x4808, array step: 0x20

◆  [7/69]

__IO uint32_t { ... } ::CLR

General Purpose Register, array offset: 0x4808, array step: 0x20

◆ CLR [8/69]

__IO uint32_t ETHERNET_PLL_Type::CLR

Fractional PLL Control Register, offset: 0x8

Fractional PLL Spread Spectrum Control Register, offset: 0x18

Fractional PLL Numerator Control Register, offset: 0x28

Fractional PLL Denominator Control Register, offset: 0x38

◆  [9/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Control Register, offset: 0x8

◆  [10/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Spread Spectrum Control Register, offset: 0x18

◆  [11/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Numerator Control Register, offset: 0x28

◆  [12/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Denominator Control Register, offset: 0x38

◆ CLR [13/69]

__IO uint32_t OSC_RC_400M_Type::CLR

Control Register 0, offset: 0x8

Control Register 1, offset: 0x18

Control Register 2, offset: 0x28

Control Register 3, offset: 0x38

◆  [14/69]

__IO uint32_t { ... } ::CLR

Control Register 0, offset: 0x8

◆  [15/69]

__IO uint32_t { ... } ::CLR

Control Register 1, offset: 0x18

◆  [16/69]

__IO uint32_t { ... } ::CLR

Control Register 2, offset: 0x28

◆  [17/69]

__IO uint32_t { ... } ::CLR

Control Register 3, offset: 0x38

◆  [18/69]

__I uint32_t { ... } ::CLR

Status Register 0, offset: 0x58

◆ CLR [19/69]

__I uint32_t OSC_RC_400M_Type::CLR

Status Register 0, offset: 0x58

Status Register 1, offset: 0x68

Status Register 2, offset: 0x78

◆  [20/69]

__I uint32_t { ... } ::CLR

Status Register 1, offset: 0x68

◆  [21/69]

__I uint32_t { ... } ::CLR

Status Register 2, offset: 0x78

◆  [22/69]

__IO uint32_t { ... } ::CLR

Analog Control Register CTRL0, offset: 0x8

◆ CLR [23/69]

__IO uint32_t PHY_LDO_Type::CLR

Analog Control Register CTRL0, offset: 0x8

◆  [24/69]

__I uint32_t { ... } ::CLR

Analog Status Register STAT0, offset: 0x58

◆ CLR [25/69]

__I uint32_t PHY_LDO_Type::CLR

Analog Status Register STAT0, offset: 0x58

◆ CLR [26/69]

__IO uint32_t VIDEO_MUX_Type::CLR

Video mux Control Register, offset: 0x8

Pixel Link Master(PLM) Control Register, offset: 0x28

YUV420 Control Register, offset: 0x38

Data Disable Register, offset: 0x58

MIPI DSI Control Register, offset: 0x78

◆  [27/69]

__IO uint32_t { ... } ::CLR

Video mux Control Register, offset: 0x8

◆  [28/69]

__IO uint32_t { ... } ::CLR

Pixel Link Master(PLM) Control Register, offset: 0x28

◆  [29/69]

__IO uint32_t { ... } ::CLR

YUV420 Control Register, offset: 0x38

◆  [30/69]

__IO uint32_t { ... } ::CLR

Data Disable Register, offset: 0x58

◆  [31/69]

__IO uint32_t { ... } ::CLR

MIPI DSI Control Register, offset: 0x78

◆ CLR [32/69]

__IO uint32_t VIDEO_PLL_Type::CLR

Fractional PLL Control Register, offset: 0x8

Fractional PLL Spread Spectrum Control Register, offset: 0x18

Fractional PLL Numerator Control Register, offset: 0x28

Fractional PLL Denominator Control Register, offset: 0x38

◆  [33/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Control Register, offset: 0x8

◆  [34/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Spread Spectrum Control Register, offset: 0x18

◆  [35/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Numerator Control Register, offset: 0x28

◆  [36/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Denominator Control Register, offset: 0x38

◆ CLR [37/69]

__IO uint32_t VMBANDGAP_Type::CLR

Analog Control Register CTRL0, offset: 0x8

◆  [38/69]

__IO uint32_t { ... } ::CLR

Analog Control Register CTRL0, offset: 0x8

◆ CLR [39/69]

__I uint32_t VMBANDGAP_Type::CLR

Analog Status Register STAT0, offset: 0x58

◆  [40/69]

__I uint32_t { ... } ::CLR

Analog Status Register STAT0, offset: 0x58

◆  [41/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Control Register, offset: 0x8

◆  [42/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Spread Spectrum Control Register, offset: 0x18

◆  [43/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Numerator Control Register, offset: 0x28

◆  [44/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Denominator Control Register, offset: 0x38

◆  [45/69]

__IO uint32_t { ... } ::CLR

General Purpose Register, array offset: 0x4808, array step: 0x20

◆  [46/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Control Register, offset: 0x8

◆  [47/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Spread Spectrum Control Register, offset: 0x18

◆  [48/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Numerator Control Register, offset: 0x28

◆  [49/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Denominator Control Register, offset: 0x38

◆  [50/69]

__IO uint32_t { ... } ::CLR

Control Register 0, offset: 0x8

◆  [51/69]

__IO uint32_t { ... } ::CLR

Control Register 1, offset: 0x18

◆  [52/69]

__IO uint32_t { ... } ::CLR

Control Register 2, offset: 0x28

◆  [53/69]

__IO uint32_t { ... } ::CLR

Control Register 3, offset: 0x38

◆  [54/69]

__I uint32_t { ... } ::CLR

Status Register 0, offset: 0x58

◆  [55/69]

__I uint32_t { ... } ::CLR

Status Register 1, offset: 0x68

◆  [56/69]

__I uint32_t { ... } ::CLR

Status Register 2, offset: 0x78

◆  [57/69]

__IO uint32_t { ... } ::CLR

Analog Control Register CTRL0, offset: 0x8

◆  [58/69]

__I uint32_t { ... } ::CLR

Analog Status Register STAT0, offset: 0x58

◆  [59/69]

__IO uint32_t { ... } ::CLR

Video mux Control Register, offset: 0x8

◆  [60/69]

__IO uint32_t { ... } ::CLR

Pixel Link Master(PLM) Control Register, offset: 0x28

◆  [61/69]

__IO uint32_t { ... } ::CLR

YUV420 Control Register, offset: 0x38

◆  [62/69]

__IO uint32_t { ... } ::CLR

Data Disable Register, offset: 0x58

◆  [63/69]

__IO uint32_t { ... } ::CLR

MIPI DSI Control Register, offset: 0x78

◆  [64/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Control Register, offset: 0x8

◆  [65/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Spread Spectrum Control Register, offset: 0x18

◆  [66/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Numerator Control Register, offset: 0x28

◆  [67/69]

__IO uint32_t { ... } ::CLR

Fractional PLL Denominator Control Register, offset: 0x38

◆  [68/69]

__IO uint32_t { ... } ::CLR

Analog Control Register CTRL0, offset: 0x8

◆  [69/69]

__I uint32_t { ... } ::CLR

Analog Status Register STAT0, offset: 0x58

◆ CLUT_LOAD

__IO uint32_t LCDIFV2_Type::CLUT_LOAD

LCDIFv2 CLUT load Register, offset: 0x400

◆ CM

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::CM

CM, offset: 0x28

◆ CM_AUTHEN_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_AUTHEN_CTRL

CM Authentication Control, offset: 0x4

◆ CM_INT_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_INT_CTRL

CM Interrupt Control, offset: 0x8

◆ CM_IRQ_WAKEUP_MASK

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_IRQ_WAKEUP_MASK

CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask, array offset: 0x100, array step: 0x4

◆ CM_IRQ_WAKEUP_STAT

__I uint32_t GPC_CPU_MODE_CTRL_Type::CM_IRQ_WAKEUP_STAT

CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status, array offset: 0x150, array step: 0x4

◆ CM_MISC

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_MISC

Miscellaneous, offset: 0xC

◆ CM_MODE_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_MODE_CTRL

CPU mode control, offset: 0x10

◆ CM_MODE_STAT

__I uint32_t GPC_CPU_MODE_CTRL_Type::CM_MODE_STAT

CM CPU mode Status, offset: 0x14

◆ CM_NON_IRQ_WAKEUP_MASK

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_NON_IRQ_WAKEUP_MASK

CM non-irq wakeup mask, offset: 0x140

◆ CM_NON_IRQ_WAKEUP_STAT

__I uint32_t GPC_CPU_MODE_CTRL_Type::CM_NON_IRQ_WAKEUP_STAT

CM non-irq wakeup status, offset: 0x190

◆ CM_RUN_MODE_MAPPING

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_RUN_MODE_MAPPING

CM Run Mode Setpoint Allowed, offset: 0x310

◆ CM_SLEEP_ISO_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_ISO_CTRL

CM sleep isolation control, offset: 0x218

◆ CM_SLEEP_LPCG_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_LPCG_CTRL

CM sleep LPCG control, offset: 0x208

◆ CM_SLEEP_PLL_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_PLL_CTRL

CM sleep PLL control, offset: 0x210

◆ CM_SLEEP_POWER_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_POWER_CTRL

CM sleep power control, offset: 0x228

◆ CM_SLEEP_RESET_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_RESET_CTRL

CM sleep reset control, offset: 0x220

◆ CM_SLEEP_SSAR_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SLEEP_SSAR_CTRL

CM sleep SSAR control, offset: 0x200

◆ CM_SP_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SP_CTRL

CM Setpoint Control, offset: 0x300

◆ CM_SP_MAPPING

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SP_MAPPING

CM Setpoint 0 Mapping..CM Setpoint 15 Mapping, array offset: 0x320, array step: 0x4

◆ CM_SP_STAT

__I uint32_t GPC_CPU_MODE_CTRL_Type::CM_SP_STAT

CM Setpoint Status, offset: 0x304

◆ CM_STBY_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_STBY_CTRL

CM standby control, offset: 0x380

◆ CM_STOP_MODE_MAPPING

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_STOP_MODE_MAPPING

CM Stop Mode Setpoint Allowed, offset: 0x318

◆ CM_SUSPEND_MODE_MAPPING

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_SUSPEND_MODE_MAPPING

CM Suspend Mode Setpoint Allowed, offset: 0x31C

◆ CM_WAIT_MODE_MAPPING

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAIT_MODE_MAPPING

CM Wait Mode Setpoint Allowed, offset: 0x314

◆ CM_WAKEUP_ISO_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_ISO_CTRL

CM wakeup isolation control, offset: 0x2A0

◆ CM_WAKEUP_LPCG_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_LPCG_CTRL

CM wakeup LPCG control, offset: 0x2B0

◆ CM_WAKEUP_PLL_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_PLL_CTRL

CM wakeup PLL control, offset: 0x2A8

◆ CM_WAKEUP_POWER_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_POWER_CTRL

CM wakeup power control, offset: 0x290

◆ CM_WAKEUP_RESET_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_RESET_CTRL

CM wakeup reset control, offset: 0x298

◆ CM_WAKEUP_SSAR_CTRL

__IO uint32_t GPC_CPU_MODE_CTRL_Type::CM_WAKEUP_SSAR_CTRL

CM wakeup SSAR control, offset: 0x2B8

◆ CMD_ARG

__IO uint32_t USDHC_Type::CMD_ARG

Command Argument, offset: 0x8

◆ CMD_RSP0

__I uint32_t USDHC_Type::CMD_RSP0

Command Response0, offset: 0x10

◆ CMD_RSP1

__I uint32_t USDHC_Type::CMD_RSP1

Command Response1, offset: 0x14

◆ CMD_RSP2

__I uint32_t USDHC_Type::CMD_RSP2

Command Response2, offset: 0x18

◆ CMD_RSP3

__I uint32_t USDHC_Type::CMD_RSP3

Command Response3, offset: 0x1C

◆ CMD_XFR_TYP

__IO uint32_t USDHC_Type::CMD_XFR_TYP

Command Transfer Type, offset: 0xC

◆  [1/3]

__IO uint32_t { ... } ::CMDH

LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8

◆ CMDH [2/3]

__IO uint32_t ADC_Type::CMDH

LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8

◆  [3/3]

__IO uint32_t { ... } ::CMDH

LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8

◆ CMDL [1/3]

__IO uint32_t ADC_Type::CMDL

LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8

◆  [2/3]

__IO uint32_t { ... } ::CMDL

LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8

◆  [3/3]

__IO uint32_t { ... } ::CMDL

LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8

◆ CMEOR

__IO uint32_t CCM_Type::CMEOR

CCM Module Enable Overide Register, offset: 0x88

◆ CMPH

__IO uint8_t EWM_Type::CMPH

Compare High Register, offset: 0x3

◆ CMPL

__IO uint8_t EWM_Type::CMPL

Compare Low Register, offset: 0x2

◆  [1/4]

__IO uint16_t { ... } ::CMPLD1

Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20

◆ CMPLD1 [2/4]

__IO uint16_t TMR_Type::CMPLD1

Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::CMPLD1

Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::CMPLD1

Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20

◆  [1/4]

__IO uint16_t { ... } ::CMPLD2

Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20

◆ CMPLD2 [2/4]

__IO uint16_t TMR_Type::CMPLD2

Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::CMPLD2

Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::CMPLD2

Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20

◆ CN

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::CN

CN, offset: 0x24

◆ CNFIFO [1/3]

__O uint32_t CAAM_Type::CNFIFO

CCB 0 iNformation FIFO When STYPE != 10b, array offset: 0x807D0, array step: 0xE3C

◆  [2/3]

__O uint32_t { ... } ::CNFIFO

CCB 0 iNformation FIFO When STYPE != 10b, array offset: 0x807D0, array step: 0xE3C

◆  [3/3]

__O uint32_t { ... } ::CNFIFO

CCB 0 iNformation FIFO When STYPE != 10b, array offset: 0x807D0, array step: 0xE3C

◆  [1/3]

__O uint32_t { ... } ::CNFIFO_2

CCB 0 iNformation FIFO When STYPE == 10b, array offset: 0x807D0, array step: 0xE3C

◆ CNFIFO_2 [2/3]

__O uint32_t CAAM_Type::CNFIFO_2

CCB 0 iNformation FIFO When STYPE == 10b, array offset: 0x807D0, array step: 0xE3C

◆  [3/3]

__O uint32_t { ... } ::CNFIFO_2

CCB 0 iNformation FIFO When STYPE == 10b, array offset: 0x807D0, array step: 0xE3C

◆ CNT [1/6]

__I uint32_t GPT_Type::CNT

GPT Counter Register, offset: 0x24

◆ CNT [2/6]

__I uint16_t PWM_Type::CNT

Counter Register, array offset: 0x0, array step: 0x60

◆  [3/6]

__I uint16_t { ... } ::CNT

Counter Register, array offset: 0x0, array step: 0x60

◆ CNT [4/6]

__IO uint32_t RTWDOG_Type::CNT

Watchdog Counter Register, offset: 0x4

◆  [5/6]

__I uint16_t { ... } ::CNT

Counter Register, array offset: 0x0, array step: 0x60

◆  [6/6]

__I uint16_t { ... } ::CNT

Counter Register, array offset: 0x0, array step: 0x60

◆ CNTR [1/5]

__IO uint32_t GPC_Type::CNTR

GPC Interface control register, offset: 0x0

◆ CNTR [2/5]

__IO uint16_t TMR_Type::CNTR

Timer Channel Counter Register, array offset: 0xA, array step: 0x20

◆  [3/5]

__IO uint16_t { ... } ::CNTR

Timer Channel Counter Register, array offset: 0xA, array step: 0x20

◆  [4/5]

__IO uint16_t { ... } ::CNTR

Timer Channel Counter Register, array offset: 0xA, array step: 0x20

◆  [5/5]

__IO uint16_t { ... } ::CNTR

Timer Channel Counter Register, array offset: 0xA, array step: 0x20

◆ CO

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::CO

CO, offset: 0x2C

◆ CODEINPUT

__O uint32_t PUF_Type::CODEINPUT

PUF Code Input Register, offset: 0x44

◆ CODEOUTPUT

__I uint32_t PUF_Type::CODEOUTPUT

PUF Code Output Register, offset: 0x48

◆  [1/3]

__I uint64_t { ... } ::COFIFO

CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C

◆ COFIFO [2/3]

__I uint64_t CAAM_Type::COFIFO

CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C

◆  [3/3]

__I uint64_t { ... } ::COFIFO

CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C

◆  [1/4]

__IO uint16_t { ... } ::COMP1

Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20

◆ COMP1 [2/4]

__IO uint16_t TMR_Type::COMP1

Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::COMP1

Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::COMP1

Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20

◆ COMP2 [1/4]

__IO uint16_t TMR_Type::COMP2

Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20

◆  [2/4]

__IO uint16_t { ... } ::COMP2

Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::COMP2

Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::COMP2

Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20

◆ CONFIG [1/9]

__I uint32_t CCM_Type::CONFIG

Clock root configuration, array offset: 0x2C, array step: 0x80

Clock group configuration, array offset: 0x402C, array step: 0x80

Clock source configuration, array offset: 0x5018, array step: 0x20

LPCG configuration, array offset: 0x6018, array step: 0x20

◆  [2/9]

__I uint32_t { ... } ::CONFIG

Clock root configuration, array offset: 0x2C, array step: 0x80

◆  [3/9]

__I uint32_t { ... } ::CONFIG

Clock group configuration, array offset: 0x402C, array step: 0x80

◆  [4/9]

__I uint32_t { ... } ::CONFIG

Clock source configuration, array offset: 0x5018, array step: 0x20

◆  [5/9]

__I uint32_t { ... } ::CONFIG

LPCG configuration, array offset: 0x6018, array step: 0x20

◆  [6/9]

__I uint32_t { ... } ::CONFIG

Clock root configuration, array offset: 0x2C, array step: 0x80

◆  [7/9]

__I uint32_t { ... } ::CONFIG

Clock group configuration, array offset: 0x402C, array step: 0x80

◆  [8/9]

__I uint32_t { ... } ::CONFIG

Clock source configuration, array offset: 0x5018, array step: 0x20

◆  [9/9]

__I uint32_t { ... } ::CONFIG

LPCG configuration, array offset: 0x6018, array step: 0x20

◆ CONFIGFLAG

__I uint32_t USB_Type::CONFIGFLAG

Configure Flag Register, offset: 0x180

◆ CONTEXT

__IO uint32_t DCP_Type::CONTEXT

DCP context buffer pointer, offset: 0x50

◆  [1/10]

__IO uint32_t { ... } ::CONTROL

Clock root control, array offset: 0x0, array step: 0x80

◆ CONTROL [2/10]

__IO uint32_t CCM_Type::CONTROL

Clock root control, array offset: 0x0, array step: 0x80

Clock group control, array offset: 0x4000, array step: 0x80

◆  [3/10]

__IO uint32_t { ... } ::CONTROL

Clock group control, array offset: 0x4000, array step: 0x80

◆  [4/10]

__IO uint32_t { ... } ::CONTROL

Observe control, array offset: 0x0, array step: 0x80

◆ CONTROL [5/10]

__IO uint32_t CCM_OBS_Type::CONTROL

Observe control, array offset: 0x0, array step: 0x80

◆ CONTROL [6/10]

__IO uint32_t CDOG_Type::CONTROL

Control, offset: 0x0

◆ CONTROL [7/10]

__IO uint32_t USBHSDCD_Type::CONTROL

Control register, offset: 0x0

◆  [8/10]

__IO uint32_t { ... } ::CONTROL

Clock root control, array offset: 0x0, array step: 0x80

◆  [9/10]

__IO uint32_t { ... } ::CONTROL

Clock group control, array offset: 0x4000, array step: 0x80

◆  [10/10]

__IO uint32_t { ... } ::CONTROL

Observe control, array offset: 0x0, array step: 0x80

◆ CONTROL_CLR [1/8]

__IO uint32_t CCM_Type::CONTROL_CLR

Clock root control, array offset: 0x8, array step: 0x80

Clock group control, array offset: 0x4008, array step: 0x80

◆  [2/8]

__IO uint32_t { ... } ::CONTROL_CLR

Clock root control, array offset: 0x8, array step: 0x80

◆  [3/8]

__IO uint32_t { ... } ::CONTROL_CLR

Clock group control, array offset: 0x4008, array step: 0x80

◆ CONTROL_CLR [4/8]

__IO uint32_t CCM_OBS_Type::CONTROL_CLR

Observe control, array offset: 0x8, array step: 0x80

◆  [5/8]

__IO uint32_t { ... } ::CONTROL_CLR

Observe control, array offset: 0x8, array step: 0x80

◆  [6/8]

__IO uint32_t { ... } ::CONTROL_CLR

Clock root control, array offset: 0x8, array step: 0x80

◆  [7/8]

__IO uint32_t { ... } ::CONTROL_CLR

Clock group control, array offset: 0x4008, array step: 0x80

◆  [8/8]

__IO uint32_t { ... } ::CONTROL_CLR

Observe control, array offset: 0x8, array step: 0x80

◆ CONTROL_SET [1/8]

__IO uint32_t CCM_Type::CONTROL_SET

Clock root control, array offset: 0x4, array step: 0x80

Clock group control, array offset: 0x4004, array step: 0x80

◆  [2/8]

__IO uint32_t { ... } ::CONTROL_SET

Clock root control, array offset: 0x4, array step: 0x80

◆  [3/8]

__IO uint32_t { ... } ::CONTROL_SET

Clock group control, array offset: 0x4004, array step: 0x80

◆ CONTROL_SET [4/8]

__IO uint32_t CCM_OBS_Type::CONTROL_SET

Observe control, array offset: 0x4, array step: 0x80

◆  [5/8]

__IO uint32_t { ... } ::CONTROL_SET

Observe control, array offset: 0x4, array step: 0x80

◆  [6/8]

__IO uint32_t { ... } ::CONTROL_SET

Clock root control, array offset: 0x4, array step: 0x80

◆  [7/8]

__IO uint32_t { ... } ::CONTROL_SET

Clock group control, array offset: 0x4004, array step: 0x80

◆  [8/8]

__IO uint32_t { ... } ::CONTROL_SET

Observe control, array offset: 0x4, array step: 0x80

◆ CONTROL_TOG [1/8]

__IO uint32_t CCM_Type::CONTROL_TOG

Clock root control, array offset: 0xC, array step: 0x80

Clock group control, array offset: 0x400C, array step: 0x80

◆  [2/8]

__IO uint32_t { ... } ::CONTROL_TOG

Clock root control, array offset: 0xC, array step: 0x80

◆  [3/8]

__IO uint32_t { ... } ::CONTROL_TOG

Clock group control, array offset: 0x400C, array step: 0x80

◆ CONTROL_TOG [4/8]

__IO uint32_t CCM_OBS_Type::CONTROL_TOG

Observe control, array offset: 0xC, array step: 0x80

◆  [5/8]

__IO uint32_t { ... } ::CONTROL_TOG

Observe control, array offset: 0xC, array step: 0x80

◆  [6/8]

__IO uint32_t { ... } ::CONTROL_TOG

Clock root control, array offset: 0xC, array step: 0x80

◆  [7/8]

__IO uint32_t { ... } ::CONTROL_TOG

Clock group control, array offset: 0x400C, array step: 0x80

◆  [8/8]

__IO uint32_t { ... } ::CONTROL_TOG

Observe control, array offset: 0xC, array step: 0x80

◆ CPC_AUTHEN_CTRL

__IO uint32_t PGMC_CPC_Type::CPC_AUTHEN_CTRL

CPC Authentication Control, offset: 0x4

◆ CPC_CACHE_CM_CTRL

__IO uint32_t PGMC_CPC_Type::CPC_CACHE_CM_CTRL

CPC cache CPU mode control, offset: 0x44

◆ CPC_CACHE_MODE

__IO uint32_t PGMC_CPC_Type::CPC_CACHE_MODE

CPC Cache Mode, offset: 0x40

◆ CPC_CACHE_SP_CTRL_0

__IO uint32_t PGMC_CPC_Type::CPC_CACHE_SP_CTRL_0

CPC cache Setpoint control 0, offset: 0x48

◆ CPC_CACHE_SP_CTRL_1

__IO uint32_t PGMC_CPC_Type::CPC_CACHE_SP_CTRL_1

CPC cache Setpoint control 1, offset: 0x4C

◆ CPC_CORE_MODE

__IO uint32_t PGMC_CPC_Type::CPC_CORE_MODE

CPC Core Mode, offset: 0x10

◆ CPC_CORE_POWER_CTRL

__IO uint32_t PGMC_CPC_Type::CPC_CORE_POWER_CTRL

CPC core power control, offset: 0x14

◆ CPC_FLAG

__IO uint32_t PGMC_CPC_Type::CPC_FLAG

CPC flag, offset: 0x2C

◆ CPC_LMEM_CM_CTRL

__IO uint32_t PGMC_CPC_Type::CPC_LMEM_CM_CTRL

CPC local memory CPU mode control, offset: 0xC4

◆ CPC_LMEM_MODE

__IO uint32_t PGMC_CPC_Type::CPC_LMEM_MODE

CPC local memory Mode, offset: 0xC0

◆ CPC_LMEM_SP_CTRL_0

__IO uint32_t PGMC_CPC_Type::CPC_LMEM_SP_CTRL_0

CPC local memory Setpoint control 0, offset: 0xC8

◆ CPC_LMEM_SP_CTRL_1

__IO uint32_t PGMC_CPC_Type::CPC_LMEM_SP_CTRL_1

CPC local memory Setpoint control 1, offset: 0xCC

◆ CPINE [1/3]

__IO uint16_t SEMA4_Type::CPINE

Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8

◆  [2/3]

__IO uint16_t { ... } ::CPINE

Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8

◆  [3/3]

__IO uint16_t { ... } ::CPINE

Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8

◆  [1/3]

__IO uint32_t { ... } ::CPKASZR

PKHA A Size Register, array offset: 0x80084, array step: 0xE3C

◆ CPKASZR [2/3]

__IO uint32_t CAAM_Type::CPKASZR

PKHA A Size Register, array offset: 0x80084, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CPKASZR

PKHA A Size Register, array offset: 0x80084, array step: 0xE3C

◆  [1/3]

__IO uint32_t { ... } ::CPKBSZR

PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C

◆ CPKBSZR [2/3]

__IO uint32_t CAAM_Type::CPKBSZR

PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CPKBSZR

PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C

◆ CPKESZR [1/3]

__IO uint32_t CAAM_Type::CPKESZR

PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C

◆  [2/3]

__IO uint32_t { ... } ::CPKESZR

PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CPKESZR

PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C

◆  [1/3]

__IO uint32_t { ... } ::CPKNSZR

PKHA N Size Register, array offset: 0x80094, array step: 0xE3C

◆ CPKNSZR [2/3]

__IO uint32_t CAAM_Type::CPKNSZR

PKHA N Size Register, array offset: 0x80094, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::CPKNSZR

PKHA N Size Register, array offset: 0x80094, array step: 0xE3C

◆  [1/3]

__I uint16_t { ... } ::CPNTF

Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8

◆ CPNTF [2/3]

__I uint16_t SEMA4_Type::CPNTF

Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8

◆  [3/3]

__I uint16_t { ... } ::CPNTF

Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8

◆ CPU_CTRL

__IO uint32_t PGC_Type::CPU_CTRL

PGC CPU Control Register, offset: 0x2A0

◆ CPU_PDNSCR

__IO uint32_t PGC_Type::CPU_PDNSCR

PGC CPU Pull Down Sequence Control Register, offset: 0x2A8

◆ CPU_PUPSCR

__IO uint32_t PGC_Type::CPU_PUPSCR

PGC CPU Power Up Sequence Control Register, offset: 0x2A4

◆ CPU_SR

__IO uint32_t PGC_Type::CPU_SR

PGC CPU Power Gating Controller Status Register, offset: 0x2AC

◆ CR [1/8]

__IO uint32_t DMA_Type::CR

Control, offset: 0x0

◆ CR [2/8]

__IO uint32_t GPT_Type::CR

GPT Control Register, offset: 0x0

◆ CR [3/8]

__IO uint32_t LPSPI_Type::CR

Control Register, offset: 0x10

Control, offset: 0x10

◆ CR [4/8]

__IO uint32_t CSI_Type::CR

CSI Control Register, array offset: 0x54, array step: 0x4

◆ CR [5/8]

__IO uint32_t DAC_Type::CR

DAC Status and Control Register, offset: 0xC

◆ CR [6/8]

__IO uint32_t MCM_Type::CR

Control Register, offset: 0xC

◆ CR [7/8]

__IO uint32_t MU_Type::CR

Processor B Control Register, offset: 0x24

Processor A Control Register, offset: 0x24

◆ CR [8/8]

__IO uint32_t OTFAD_Type::CR

Control Register, offset: 0xC00

◆ CR0

__IO uint8_t CMP_Type::CR0

CMP Control Register 0, offset: 0x0

◆ CR1 [1/2]

__IO uint8_t CMP_Type::CR1

CMP Control Register 1, offset: 0x1

◆ CR1 [2/2]

__IO uint32_t CSI_Type::CR1

CSI Control Register 1, offset: 0x0

◆ CR18

__IO uint32_t CSI_Type::CR18

CSI Control Register 18, offset: 0x48

◆ CR19

__IO uint32_t CSI_Type::CR19

CSI Control Register 19, offset: 0x4C

◆ CR2 [1/2]

__IO uint32_t CSI_Type::CR2

CSI Control Register 2, offset: 0x4

◆ CR2 [2/2]

__IO uint32_t DAC_Type::CR2

DAC Status and Control Register 2, offset: 0x14

◆ CR20

__IO uint32_t CSI_Type::CR20

CSI Control Register 20, offset: 0x50

◆ CR3

__IO uint32_t CSI_Type::CR3

CSI Control Register 3, offset: 0x8

◆ CRC_STAT

__IO uint32_t LCDIF_Type::CRC_STAT

CRC Status Register, offset: 0x1A0

◆ CRCR

__I uint32_t CAN_Type::CRCR

CRC Register, offset: 0x44

CRC register, offset: 0x44

◆ CRNR_LS

__I uint32_t CAAM_Type::CRNR_LS

CHA Revision Number Register, least-significant half, offset: 0xFA4

◆ CRNR_LS_DC01

__I uint32_t CAAM_Type::CRNR_LS_DC01

CHA Revision Number Register, least-significant half, offset: 0x80FA4

◆ CRNR_LS_JR [1/3]

__I uint32_t CAAM_Type::CRNR_LS_JR

CHA Revision Number Register, least-significant half, array offset: 0x10FA4, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::CRNR_LS_JR

CHA Revision Number Register, least-significant half, array offset: 0x10FA4, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CRNR_LS_JR

CHA Revision Number Register, least-significant half, array offset: 0x10FA4, array step: 0x10000

◆ CRNR_LS_RTIC

__I uint32_t CAAM_Type::CRNR_LS_RTIC

CHA Revision Number Register, least-significant half, offset: 0x60FA4

◆ CRNR_MS

__I uint32_t CAAM_Type::CRNR_MS

CHA Revision Number Register, most-significant half, offset: 0xFA0

◆ CRNR_MS_DC01

__I uint32_t CAAM_Type::CRNR_MS_DC01

CHA Revision Number Register, most-significant half, offset: 0x80FA0

◆  [1/3]

__I uint32_t { ... } ::CRNR_MS_JR

CHA Revision Number Register, most-significant half, array offset: 0x10FA0, array step: 0x10000

◆ CRNR_MS_JR [2/3]

__I uint32_t CAAM_Type::CRNR_MS_JR

CHA Revision Number Register, most-significant half, array offset: 0x10FA0, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CRNR_MS_JR

CHA Revision Number Register, most-significant half, array offset: 0x10FA0, array step: 0x10000

◆ CRNR_MS_RTIC

__I uint32_t CAAM_Type::CRNR_MS_RTIC

CHA Revision Number Register, most-significant half, offset: 0x60FA0

◆ CS [1/19]

__IO uint32_t CAN_Type::CS

Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10

Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18

Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x280, array step: 0x18

Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28

Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x280, array step: 0x28

Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48

Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x280, array step: 0x48

◆  [2/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10

◆ CS [3/19]

__IO uint32_t RTWDOG_Type::CS

Watchdog Control and Status Register, offset: 0x0

◆  [4/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10

◆  [5/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18

◆  [6/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x280, array step: 0x18

◆  [7/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28

◆  [8/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x280, array step: 0x28

◆  [9/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48

◆  [10/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x280, array step: 0x48

◆  [11/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10

◆  [12/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10

◆  [13/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18

◆  [14/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x280, array step: 0x18

◆  [15/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28

◆  [16/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x280, array step: 0x28

◆  [17/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48

◆  [18/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x280, array step: 0x48

◆  [19/19]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10

◆ CS1CDR

__IO uint32_t CCM_Type::CS1CDR

CCM Clock Divider Register, offset: 0x28

◆ CS2CDR

__IO uint32_t CCM_Type::CS2CDR

CCM Clock Divider Register, offset: 0x2C

◆ CSC1_COEF0

__IO uint32_t PXP_Type::CSC1_COEF0

Color Space Conversion Coefficient Register 0, offset: 0x1A0

◆ CSC1_COEF1

__IO uint32_t PXP_Type::CSC1_COEF1

Color Space Conversion Coefficient Register 1, offset: 0x1B0

◆ CSC1_COEF2

__IO uint32_t PXP_Type::CSC1_COEF2

Color Space Conversion Coefficient Register 2, offset: 0x1C0

◆  [1/3]

__IO uint32_t { ... } ::CSC_COEF0

Color Space Conversion Coefficient Register 0, array offset: 0x218, array step: 0x40, this item is not available for all array instances

◆ CSC_COEF0 [2/3]

__IO uint32_t LCDIFV2_Type::CSC_COEF0

Color Space Conversion Coefficient Register 0, array offset: 0x218, array step: 0x40, this item is not available for all array instances

◆  [3/3]

__IO uint32_t { ... } ::CSC_COEF0

Color Space Conversion Coefficient Register 0, array offset: 0x218, array step: 0x40, this item is not available for all array instances

◆ CSC_COEF1 [1/3]

__IO uint32_t LCDIFV2_Type::CSC_COEF1

Color Space Conversion Coefficient Register 1, array offset: 0x21C, array step: 0x40, this item is not available for all array instances

◆  [2/3]

__IO uint32_t { ... } ::CSC_COEF1

Color Space Conversion Coefficient Register 1, array offset: 0x21C, array step: 0x40, this item is not available for all array instances

◆  [3/3]

__IO uint32_t { ... } ::CSC_COEF1

Color Space Conversion Coefficient Register 1, array offset: 0x21C, array step: 0x40, this item is not available for all array instances

◆  [1/3]

__IO uint32_t { ... } ::CSC_COEF2

Color Space Conversion Coefficient Register 2, array offset: 0x220, array step: 0x40, this item is not available for all array instances

◆ CSC_COEF2 [2/3]

__IO uint32_t LCDIFV2_Type::CSC_COEF2

Color Space Conversion Coefficient Register 2, array offset: 0x220, array step: 0x40, this item is not available for all array instances

◆  [3/3]

__IO uint32_t { ... } ::CSC_COEF2

Color Space Conversion Coefficient Register 2, array offset: 0x220, array step: 0x40, this item is not available for all array instances

◆ CSCDR1

__IO uint32_t CCM_Type::CSCDR1

CCM Serial Clock Divider Register 1, offset: 0x24

◆ CSCDR2

__IO uint32_t CCM_Type::CSCDR2

CCM Serial Clock Divider Register 2, offset: 0x38

◆ CSCDR3

__IO uint32_t CCM_Type::CSCDR3

CCM Serial Clock Divider Register 3, offset: 0x3C

◆ CSCMR1

__IO uint32_t CCM_Type::CSCMR1

CCM Serial Clock Multiplexer Register 1, offset: 0x1C

◆ CSCMR2

__IO uint32_t CCM_Type::CSCMR2

CCM Serial Clock Multiplexer Register 2, offset: 0x20

◆ CSCTRL [1/4]

__IO uint16_t TMR_Type::CSCTRL

Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20

◆  [2/4]

__IO uint16_t { ... } ::CSCTRL

Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::CSCTRL

Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::CSCTRL

Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20

◆ CSL

__IO uint32_t CSU_Type::CSL[32]

Config security level register, array offset: 0x0, array step: 0x4

◆ CSR [1/5]

__I uint32_t CCM_Type::CSR

CCM Status Register, offset: 0x8

◆  [2/5]

__IO uint16_t { ... } ::CSR

TCD Control and Status, array offset: 0x101C, array step: 0x20

◆ CSR [3/5]

__IO uint16_t DMA_Type::CSR

TCD Control and Status, array offset: 0x101C, array step: 0x20

◆  [4/5]

__IO uint16_t { ... } ::CSR

TCD Control and Status, array offset: 0x101C, array step: 0x20

◆  [5/5]

__IO uint16_t { ... } ::CSR

TCD Control and Status, array offset: 0x101C, array step: 0x20

◆ CSTA

__I uint32_t CAAM_Type::CSTA

CAAM Status Register, offset: 0xFD4

◆ CSTA_DC01

__I uint32_t CAAM_Type::CSTA_DC01

CAAM Status Register, offset: 0x80FD4

◆  [1/3]

__I uint32_t { ... } ::CSTA_JR

CAAM Status Register, array offset: 0x10FD4, array step: 0x10000

◆ CSTA_JR [2/3]

__I uint32_t CAAM_Type::CSTA_JR

CAAM Status Register, array offset: 0x10FD4, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CSTA_JR

CAAM Status Register, array offset: 0x10FD4, array step: 0x10000

◆ CSTA_RTIC

__I uint32_t CAAM_Type::CSTA_RTIC

CAAM Status Register, offset: 0x60FD4

◆ CTPR_LS

__I uint32_t CAAM_Type::CTPR_LS

Compile Time Parameters Register, least-significant half, offset: 0xFAC

◆ CTPR_LS_DC01

__I uint32_t CAAM_Type::CTPR_LS_DC01

Compile Time Parameters Register, least-significant half, offset: 0x80FAC

◆  [1/3]

__I uint32_t { ... } ::CTPR_LS_JR

Compile Time Parameters Register, least-significant half, array offset: 0x10FAC, array step: 0x10000

◆ CTPR_LS_JR [2/3]

__I uint32_t CAAM_Type::CTPR_LS_JR

Compile Time Parameters Register, least-significant half, array offset: 0x10FAC, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CTPR_LS_JR

Compile Time Parameters Register, least-significant half, array offset: 0x10FAC, array step: 0x10000

◆ CTPR_LS_RTIC

__I uint32_t CAAM_Type::CTPR_LS_RTIC

Compile Time Parameters Register, least-significant half, offset: 0x60FAC

◆ CTPR_MS

__I uint32_t CAAM_Type::CTPR_MS

Compile Time Parameters Register, most-significant half, offset: 0xFA8

◆ CTPR_MS_DC01

__I uint32_t CAAM_Type::CTPR_MS_DC01

Compile Time Parameters Register, most-significant half, offset: 0x80FA8

◆  [1/3]

__I uint32_t { ... } ::CTPR_MS_JR

Compile Time Parameters Register, most-significant half, array offset: 0x10FA8, array step: 0x10000

◆ CTPR_MS_JR [2/3]

__I uint32_t CAAM_Type::CTPR_MS_JR

Compile Time Parameters Register, most-significant half, array offset: 0x10FA8, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::CTPR_MS_JR

Compile Time Parameters Register, most-significant half, array offset: 0x10FA8, array step: 0x10000

◆ CTPR_MS_RTIC

__I uint32_t CAAM_Type::CTPR_MS_RTIC

Compile Time Parameters Register, most-significant half, offset: 0x60FA8

◆ CTR [1/3]

__IO uint32_t OTFAD_Type::CTR[2]

AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4

◆  [2/3]

__IO uint32_t { ... } ::CTR[2]

AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4

◆  [3/3]

__IO uint32_t { ... } ::CTR[2]

AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4

◆ CTR_NONCE0_W0

__O uint32_t BEE_Type::CTR_NONCE0_W0

NONCE00 Register, offset: 0x20

◆ CTR_NONCE0_W1

__O uint32_t BEE_Type::CTR_NONCE0_W1

NONCE01 Register, offset: 0x24

◆ CTR_NONCE0_W2

__O uint32_t BEE_Type::CTR_NONCE0_W2

NONCE02 Register, offset: 0x28

◆ CTR_NONCE0_W3

__O uint32_t BEE_Type::CTR_NONCE0_W3

NONCE03 Register, offset: 0x2C

◆ CTR_NONCE1_W0

__O uint32_t BEE_Type::CTR_NONCE1_W0

NONCE10 Register, offset: 0x30

◆ CTR_NONCE1_W1

__O uint32_t BEE_Type::CTR_NONCE1_W1

NONCE11 Register, offset: 0x34

◆ CTR_NONCE1_W2

__O uint32_t BEE_Type::CTR_NONCE1_W2

NONCE12 Register, offset: 0x38

◆ CTR_NONCE1_W3

__O uint32_t BEE_Type::CTR_NONCE1_W3

NONCE13 Register, offset: 0x3C

◆ CTRL [1/25]

__IO uint32_t ADC_ETC_Type::CTRL

ADC_ETC Global Control Register, offset: 0x0

◆ CTRL [2/25]

__IO uint32_t BEE_Type::CTRL

Control Register, offset: 0x0

◆ CTRL [3/25]

__IO uint32_t DCP_Type::CTRL

DCP control register 0, offset: 0x0

◆ CTRL [4/25]

__IO uint16_t ENC_Type::CTRL

Control Register, offset: 0x0

◆ CTRL [5/25]

__IO uint8_t EWM_Type::CTRL

Control Register, offset: 0x0

◆ CTRL [6/25]

__IO uint32_t FLEXIO_Type::CTRL

FlexIO Control Register, offset: 0x8

◆ CTRL [7/25]

__IO uint32_t LCDIF_Type::CTRL

LCDIF General Control Register, offset: 0x0

◆ CTRL [8/25]

__IO uint32_t LPUART_Type::CTRL

LPUART Control Register, offset: 0x18

◆ CTRL [9/25]

__IO uint32_t OCOTP_Type::CTRL

OTP Controller Control and Status Register, offset: 0x0

◆ CTRL [10/25]

__IO uint16_t PWM_Type::CTRL

Control Register, array offset: 0x6, array step: 0x60

◆  [11/25]

__IO uint16_t { ... } ::CTRL

Control Register, array offset: 0x6, array step: 0x60

◆ CTRL [12/25]

__IO uint32_t PXP_Type::CTRL

Control Register 0, offset: 0x0

◆  [13/25]

__IO uint16_t { ... } ::CTRL

Timer Channel Control Register, array offset: 0xC, array step: 0x20

◆ CTRL [14/25]

__IO uint16_t TMR_Type::CTRL

Timer Channel Control Register, array offset: 0xC, array step: 0x20

◆ CTRL [15/25]

__IO uint32_t USBPHY_Type::CTRL

USB PHY General Control Register, offset: 0x30

◆ CTRL [16/25]

__IO uint32_t ADC_Type::CTRL

LPADC Control Register, offset: 0x10

◆ CTRL [17/25]

__IO uint32_t EMVSIM_Type::CTRL

Control Register, offset: 0x10

◆ CTRL [18/25]

__IO uint32_t LCDIFV2_Type::CTRL

LCDIFv2 display control Register, offset: 0x0

◆ CTRL [19/25]

__IO uint32_t PUF_Type::CTRL

PUF Control Register, offset: 0x0

◆  [20/25]

__IO uint16_t { ... } ::CTRL

Control Register, array offset: 0x6, array step: 0x60

◆ CTRL [21/25]

__IO uint32_t SRAM_Type::CTRL

Control Register, offset: 0x3000

◆ CTRL [22/25]

__IO uint32_t SSARC_LP_Type::CTRL

Control Register, offset: 0x200

◆  [23/25]

__IO uint16_t { ... } ::CTRL

Timer Channel Control Register, array offset: 0xC, array step: 0x20

◆  [24/25]

__IO uint16_t { ... } ::CTRL

Control Register, array offset: 0x6, array step: 0x60

◆  [25/25]

__IO uint16_t { ... } ::CTRL

Timer Channel Control Register, array offset: 0xC, array step: 0x20

◆ CTRL0 [1/3]

__IO uint16_t XBARA_Type::CTRL0

Crossbar A Control Register 0, offset: 0x84

Crossbar A Control Register 0, offset: 0xB0

◆ CTRL0 [2/3]

__IO uint32_t DCDC_Type::CTRL0

DCDC Control Register 0, offset: 0x0

◆ CTRL0 [3/3]

__IO uint32_t TMPSNS_Type::CTRL0

Temperature Sensor Control Register 0, offset: 0x0

◆ CTRL0_CLR

__IO uint32_t TMPSNS_Type::CTRL0_CLR

Temperature Sensor Control Register 0, offset: 0x8

◆ CTRL0_SET

__IO uint32_t TMPSNS_Type::CTRL0_SET

Temperature Sensor Control Register 0, offset: 0x4

◆ CTRL0_TOG

__IO uint32_t TMPSNS_Type::CTRL0_TOG

Temperature Sensor Control Register 0, offset: 0xC

◆ CTRL1 [1/6]

__IO uint32_t CAN_Type::CTRL1

Control 1 Register, offset: 0x4

Control 1 register, offset: 0x4

◆ CTRL1 [2/6]

__IO uint32_t LCDIF_Type::CTRL1

LCDIF General Control1 Register, offset: 0x10

◆ CTRL1 [3/6]

__IO uint16_t XBARA_Type::CTRL1

Crossbar A Control Register 1, offset: 0x86

Crossbar A Control Register 1, offset: 0xB2

◆ CTRL1 [4/6]

__IO uint32_t DCDC_Type::CTRL1

DCDC Control Register 1, offset: 0x4

◆ CTRL1 [5/6]

__IO uint32_t TMPSNS_Type::CTRL1

Temperature Sensor Control Register 1, offset: 0x10

◆ CTRL1 [6/6]

__IO uint32_t USBNC_Type::CTRL1

USB OTG Control 1 Register, offset: 0x0

◆ CTRL1_CLR [1/2]

__IO uint32_t LCDIF_Type::CTRL1_CLR

LCDIF General Control1 Register, offset: 0x18

◆ CTRL1_CLR [2/2]

__IO uint32_t TMPSNS_Type::CTRL1_CLR

Temperature Sensor Control Register 1, offset: 0x18

◆ CTRL1_SET [1/2]

__IO uint32_t LCDIF_Type::CTRL1_SET

LCDIF General Control1 Register, offset: 0x14

◆ CTRL1_SET [2/2]

__IO uint32_t TMPSNS_Type::CTRL1_SET

Temperature Sensor Control Register 1, offset: 0x14

◆ CTRL1_TOG [1/2]

__IO uint32_t LCDIF_Type::CTRL1_TOG

LCDIF General Control1 Register, offset: 0x1C

◆ CTRL1_TOG [2/2]

__IO uint32_t TMPSNS_Type::CTRL1_TOG

Temperature Sensor Control Register 1, offset: 0x1C

◆ CTRL2 [1/8]

__IO uint32_t CAN_Type::CTRL2

Control 2 Register, offset: 0x34

Control 2 register, offset: 0x34

◆ CTRL2 [2/8]

__IO uint16_t ENC_Type::CTRL2

Control 2 Register, offset: 0x1E

◆ CTRL2 [3/8]

__IO uint32_t LCDIF_Type::CTRL2

LCDIF General Control2 Register, offset: 0x20

◆ CTRL2 [4/8]

__IO uint16_t PWM_Type::CTRL2

Control 2 Register, array offset: 0x4, array step: 0x60

◆  [5/8]

__IO uint16_t { ... } ::CTRL2

Control 2 Register, array offset: 0x4, array step: 0x60

◆  [6/8]

__IO uint16_t { ... } ::CTRL2

Control 2 Register, array offset: 0x4, array step: 0x60

◆ CTRL2 [7/8]

__IO uint32_t USBNC_Type::CTRL2

USB OTG Control 2 Register, offset: 0x4

◆  [8/8]

__IO uint16_t { ... } ::CTRL2

Control 2 Register, array offset: 0x4, array step: 0x60

◆ CTRL2_CLR

__IO uint32_t LCDIF_Type::CTRL2_CLR

LCDIF General Control2 Register, offset: 0x28

◆ CTRL2_SET

__IO uint32_t LCDIF_Type::CTRL2_SET

LCDIF General Control2 Register, offset: 0x24

◆ CTRL2_TOG

__IO uint32_t LCDIF_Type::CTRL2_TOG

LCDIF General Control2 Register, offset: 0x2C

◆ CTRL3

__IO uint16_t ENC_Type::CTRL3

Control 3 Register, offset: 0x32

◆ CTRL_1

__IO uint32_t PDM_Type::CTRL_1

PDM Control register 1, offset: 0x0

◆ CTRL_2

__IO uint32_t PDM_Type::CTRL_2

PDM Control register 2, offset: 0x4

◆ CTRL_CLR [1/6]

__IO uint32_t DCP_Type::CTRL_CLR

DCP control register 0, offset: 0x8

◆ CTRL_CLR [2/6]

__IO uint32_t LCDIF_Type::CTRL_CLR

LCDIF General Control Register, offset: 0x8

◆ CTRL_CLR [3/6]

__IO uint32_t OCOTP_Type::CTRL_CLR

OTP Controller Control and Status Register, offset: 0x8

◆ CTRL_CLR [4/6]

__IO uint32_t PXP_Type::CTRL_CLR

Control Register 0, offset: 0x8

◆ CTRL_CLR [5/6]

__IO uint32_t USBPHY_Type::CTRL_CLR

USB PHY General Control Register, offset: 0x38

◆ CTRL_CLR [6/6]

__IO uint32_t LCDIFV2_Type::CTRL_CLR

LCDIFv2 display control Register, offset: 0x8

◆ CTRL_DISPLAY

__IO uint32_t SRC_Type::CTRL_DISPLAY

Slice Control Register, offset: 0x224

◆ CTRL_M4CORE

__IO uint32_t SRC_Type::CTRL_M4CORE

Slice Control Register, offset: 0x284

◆ CTRL_M4DEBUG

__IO uint32_t SRC_Type::CTRL_M4DEBUG

Slice Control Register, offset: 0x2C4

◆ CTRL_M7CORE

__IO uint32_t SRC_Type::CTRL_M7CORE

Slice Control Register, offset: 0x2A4

◆ CTRL_M7DEBUG

__IO uint32_t SRC_Type::CTRL_M7DEBUG

Slice Control Register, offset: 0x2E4

◆ CTRL_MEGA

__IO uint32_t SRC_Type::CTRL_MEGA

Slice Control Register, offset: 0x204

◆ CTRL_SET [1/6]

__IO uint32_t DCP_Type::CTRL_SET

DCP control register 0, offset: 0x4

◆ CTRL_SET [2/6]

__IO uint32_t LCDIF_Type::CTRL_SET

LCDIF General Control Register, offset: 0x4

◆ CTRL_SET [3/6]

__IO uint32_t OCOTP_Type::CTRL_SET

OTP Controller Control and Status Register, offset: 0x4

◆ CTRL_SET [4/6]

__IO uint32_t PXP_Type::CTRL_SET

Control Register 0, offset: 0x4

◆ CTRL_SET [5/6]

__IO uint32_t USBPHY_Type::CTRL_SET

USB PHY General Control Register, offset: 0x34

◆ CTRL_SET [6/6]

__IO uint32_t LCDIFV2_Type::CTRL_SET

LCDIFv2 display control Register, offset: 0x4

◆ CTRL_TOG [1/6]

__IO uint32_t DCP_Type::CTRL_TOG

DCP control register 0, offset: 0xC

◆ CTRL_TOG [2/6]

__IO uint32_t LCDIF_Type::CTRL_TOG

LCDIF General Control Register, offset: 0xC

◆ CTRL_TOG [3/6]

__IO uint32_t OCOTP_Type::CTRL_TOG

OTP Controller Control and Status Register, offset: 0xC

◆ CTRL_TOG [4/6]

__IO uint32_t PXP_Type::CTRL_TOG

Control Register 0, offset: 0xC

◆ CTRL_TOG [5/6]

__IO uint32_t USBPHY_Type::CTRL_TOG

USB PHY General Control Register, offset: 0x3C

◆ CTRL_TOG [6/6]

__IO uint32_t LCDIFV2_Type::CTRL_TOG

LCDIFv2 display control Register, offset: 0xC

◆ CTRL_USBPHY1

__IO uint32_t SRC_Type::CTRL_USBPHY1

Slice Control Register, offset: 0x304

◆ CTRL_USBPHY2

__IO uint32_t SRC_Type::CTRL_USBPHY2

Slice Control Register, offset: 0x324

◆ CTRL_WAKEUP

__IO uint32_t SRC_Type::CTRL_WAKEUP

Slice Control Register, offset: 0x244

◆ CTRLDESCL1 [1/3]

__IO uint32_t LCDIFV2_Type::CTRLDESCL1

Control Descriptor Layer 1 Register, array offset: 0x200, array step: 0x40

◆  [2/3]

__IO uint32_t { ... } ::CTRLDESCL1

Control Descriptor Layer 1 Register, array offset: 0x200, array step: 0x40

◆  [3/3]

__IO uint32_t { ... } ::CTRLDESCL1

Control Descriptor Layer 1 Register, array offset: 0x200, array step: 0x40

◆ CTRLDESCL2 [1/3]

__IO uint32_t LCDIFV2_Type::CTRLDESCL2

Control Descriptor Layer 2 Register, array offset: 0x204, array step: 0x40

◆  [2/3]

__IO uint32_t { ... } ::CTRLDESCL2

Control Descriptor Layer 2 Register, array offset: 0x204, array step: 0x40

◆  [3/3]

__IO uint32_t { ... } ::CTRLDESCL2

Control Descriptor Layer 2 Register, array offset: 0x204, array step: 0x40

◆ CTRLDESCL3 [1/3]

__IO uint32_t LCDIFV2_Type::CTRLDESCL3

Control Descriptor Layer 3 Register, array offset: 0x208, array step: 0x40

◆  [2/3]

__IO uint32_t { ... } ::CTRLDESCL3

Control Descriptor Layer 3 Register, array offset: 0x208, array step: 0x40

◆  [3/3]

__IO uint32_t { ... } ::CTRLDESCL3

Control Descriptor Layer 3 Register, array offset: 0x208, array step: 0x40

◆  [1/3]

__IO uint32_t { ... } ::CTRLDESCL4

Control Descriptor Layer 4 Register, array offset: 0x20C, array step: 0x40

◆ CTRLDESCL4 [2/3]

__IO uint32_t LCDIFV2_Type::CTRLDESCL4

Control Descriptor Layer 4 Register, array offset: 0x20C, array step: 0x40

◆  [3/3]

__IO uint32_t { ... } ::CTRLDESCL4

Control Descriptor Layer 4 Register, array offset: 0x20C, array step: 0x40

◆  [1/3]

__IO uint32_t { ... } ::CTRLDESCL5

Control Descriptor Layer 5 Register, array offset: 0x210, array step: 0x40

◆ CTRLDESCL5 [2/3]

__IO uint32_t LCDIFV2_Type::CTRLDESCL5

Control Descriptor Layer 5 Register, array offset: 0x210, array step: 0x40

◆  [3/3]

__IO uint32_t { ... } ::CTRLDESCL5

Control Descriptor Layer 5 Register, array offset: 0x210, array step: 0x40

◆  [1/3]

__IO uint32_t { ... } ::CTRLDESCL6

Control Descriptor Layer 6 Register, array offset: 0x214, array step: 0x40

◆ CTRLDESCL6 [2/3]

__IO uint32_t LCDIFV2_Type::CTRLDESCL6

Control Descriptor Layer 6 Register, array offset: 0x214, array step: 0x40

◆  [3/3]

__IO uint32_t { ... } ::CTRLDESCL6

Control Descriptor Layer 6 Register, array offset: 0x214, array step: 0x40

◆ CUR_BUF

__IO uint32_t LCDIF_Type::CUR_BUF

LCD Interface Current Buffer Address Register, offset: 0x40

◆ CV

__IO uint32_t ADC_Type::CV

Compare value register, offset: 0x50

Compare Value Register, array offset: 0x200, array step: 0x4

◆ CVAL [1/4]

__I uint32_t PIT_Type::CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10

◆  [2/4]

__I uint32_t { ... } ::CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10

◆  [3/4]

__I uint32_t { ... } ::CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10

◆  [4/4]

__I uint32_t { ... } ::CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10

◆ CVAL0 [1/4]

__I uint16_t PWM_Type::CVAL0

Capture Value 0 Register, array offset: 0x40, array step: 0x60

◆  [2/4]

__I uint16_t { ... } ::CVAL0

Capture Value 0 Register, array offset: 0x40, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL0

Capture Value 0 Register, array offset: 0x40, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL0

Capture Value 0 Register, array offset: 0x40, array step: 0x60

◆  [1/4]

__I uint16_t { ... } ::CVAL0CYC

Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60

◆ CVAL0CYC [2/4]

__I uint16_t PWM_Type::CVAL0CYC

Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL0CYC

Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL0CYC

Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60

◆  [1/4]

__I uint16_t { ... } ::CVAL1

Capture Value 1 Register, array offset: 0x44, array step: 0x60

◆ CVAL1 [2/4]

__I uint16_t PWM_Type::CVAL1

Capture Value 1 Register, array offset: 0x44, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL1

Capture Value 1 Register, array offset: 0x44, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL1

Capture Value 1 Register, array offset: 0x44, array step: 0x60

◆ CVAL1CYC [1/4]

__I uint16_t PWM_Type::CVAL1CYC

Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60

◆  [2/4]

__I uint16_t { ... } ::CVAL1CYC

Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL1CYC

Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL1CYC

Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60

◆ CVAL2 [1/4]

__I uint16_t PWM_Type::CVAL2

Capture Value 2 Register, array offset: 0x48, array step: 0x60

◆  [2/4]

__I uint16_t { ... } ::CVAL2

Capture Value 2 Register, array offset: 0x48, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL2

Capture Value 2 Register, array offset: 0x48, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL2

Capture Value 2 Register, array offset: 0x48, array step: 0x60

◆ CVAL2CYC [1/4]

__I uint16_t PWM_Type::CVAL2CYC

Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60

◆  [2/4]

__I uint16_t { ... } ::CVAL2CYC

Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL2CYC

Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL2CYC

Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60

◆ CVAL3 [1/4]

__I uint16_t PWM_Type::CVAL3

Capture Value 3 Register, array offset: 0x4C, array step: 0x60

◆  [2/4]

__I uint16_t { ... } ::CVAL3

Capture Value 3 Register, array offset: 0x4C, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL3

Capture Value 3 Register, array offset: 0x4C, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL3

Capture Value 3 Register, array offset: 0x4C, array step: 0x60

◆ CVAL3CYC [1/4]

__I uint16_t PWM_Type::CVAL3CYC

Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60

◆  [2/4]

__I uint16_t { ... } ::CVAL3CYC

Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL3CYC

Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL3CYC

Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60

◆ CVAL4 [1/4]

__I uint16_t PWM_Type::CVAL4

Capture Value 4 Register, array offset: 0x50, array step: 0x60

◆  [2/4]

__I uint16_t { ... } ::CVAL4

Capture Value 4 Register, array offset: 0x50, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL4

Capture Value 4 Register, array offset: 0x50, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL4

Capture Value 4 Register, array offset: 0x50, array step: 0x60

◆  [1/4]

__I uint16_t { ... } ::CVAL4CYC

Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60

◆ CVAL4CYC [2/4]

__I uint16_t PWM_Type::CVAL4CYC

Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL4CYC

Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL4CYC

Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60

◆ CVAL5 [1/4]

__I uint16_t PWM_Type::CVAL5

Capture Value 5 Register, array offset: 0x54, array step: 0x60

◆  [2/4]

__I uint16_t { ... } ::CVAL5

Capture Value 5 Register, array offset: 0x54, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL5

Capture Value 5 Register, array offset: 0x54, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL5

Capture Value 5 Register, array offset: 0x54, array step: 0x60

◆ CVAL5CYC [1/4]

__I uint16_t PWM_Type::CVAL5CYC

Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60

◆  [2/4]

__I uint16_t { ... } ::CVAL5CYC

Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60

◆  [3/4]

__I uint16_t { ... } ::CVAL5CYC

Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60

◆  [4/4]

__I uint16_t { ... } ::CVAL5CYC

Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60

◆ CWT_VAL

__IO uint32_t EMVSIM_Type::CWT_VAL

Character Wait Time Value Register, offset: 0x38

◆ D0TCM_ECC_MULTI_ERROR_ADDR

__I uint32_t FLEXRAM_Type::D0TCM_ECC_MULTI_ERROR_ADDR

D0TCM multi-bit ECC Error Address Register, offset: 0x6C

◆ D0TCM_ECC_MULTI_ERROR_DATA

__I uint32_t FLEXRAM_Type::D0TCM_ECC_MULTI_ERROR_DATA

D0TCM multi-bit ECC Error Data Register, offset: 0x70

◆ D0TCM_ECC_MULTI_ERROR_INFO

__I uint32_t FLEXRAM_Type::D0TCM_ECC_MULTI_ERROR_INFO

D0TCM multi-bit ECC Error Information Register, offset: 0x68

◆ D0TCM_ECC_SINGLE_ERROR_ADDR

__I uint32_t FLEXRAM_Type::D0TCM_ECC_SINGLE_ERROR_ADDR

D0TCM single-bit ECC Error Address Register, offset: 0x60

◆ D0TCM_ECC_SINGLE_ERROR_DATA

__I uint32_t FLEXRAM_Type::D0TCM_ECC_SINGLE_ERROR_DATA

D0TCM single-bit ECC Error Data Register, offset: 0x64

◆ D0TCM_ECC_SINGLE_ERROR_INFO

__I uint32_t FLEXRAM_Type::D0TCM_ECC_SINGLE_ERROR_INFO

D0TCM single-bit ECC Error Information Register, offset: 0x5C

◆ D1TCM_ECC_MULTI_ERROR_ADDR

__I uint32_t FLEXRAM_Type::D1TCM_ECC_MULTI_ERROR_ADDR

D1TCM multi-bit ECC Error Address Register, offset: 0x84

◆ D1TCM_ECC_MULTI_ERROR_DATA

__I uint32_t FLEXRAM_Type::D1TCM_ECC_MULTI_ERROR_DATA

D1TCM multi-bit ECC Error Data Register, offset: 0x88

◆ D1TCM_ECC_MULTI_ERROR_INFO

__I uint32_t FLEXRAM_Type::D1TCM_ECC_MULTI_ERROR_INFO

D1TCM multi-bit ECC Error Information Register, offset: 0x80

◆ D1TCM_ECC_SINGLE_ERROR_ADDR

__I uint32_t FLEXRAM_Type::D1TCM_ECC_SINGLE_ERROR_ADDR

D1TCM single-bit ECC Error Address Register, offset: 0x78

◆ D1TCM_ECC_SINGLE_ERROR_DATA

__I uint32_t FLEXRAM_Type::D1TCM_ECC_SINGLE_ERROR_DATA

D1TCM single-bit ECC Error Data Register, offset: 0x7C

◆ D1TCM_ECC_SINGLE_ERROR_INFO

__I uint32_t FLEXRAM_Type::D1TCM_ECC_SINGLE_ERROR_INFO

D1TCM single-bit ECC Error Information Register, offset: 0x74

◆ DACCR

__IO uint8_t CMP_Type::DACCR

DAC Control Register, offset: 0x4

◆ DADDR [1/4]

__IO uint32_t DMA_Type::DADDR

TCD Destination Address, array offset: 0x1010, array step: 0x20

◆  [2/4]

__IO uint32_t { ... } ::DADDR

TCD Destination Address, array offset: 0x1010, array step: 0x20

◆  [3/4]

__IO uint32_t { ... } ::DADDR

TCD Destination Address, array offset: 0x1010, array step: 0x20

◆  [4/4]

__IO uint32_t { ... } ::DADDR

TCD Destination Address, array offset: 0x1010, array step: 0x20

◆ DAR

__IO uint32_t CAAM_Type::DAR

DECO Availability Register, offset: 0x120

◆ DATA [1/3]

__IO uint32_t LPUART_Type::DATA

LPUART Data Register, offset: 0x1C

◆ DATA [2/3]

__IO uint32_t OCOTP_Type::DATA

OTP Controller Write Data Register, offset: 0x20

◆ DATA [3/3]

__O uint32_t DAC_Type::DATA

DAC Data Register, offset: 0x8

◆ DATA_BUFF_ACC_PORT

__IO uint32_t USDHC_Type::DATA_BUFF_ACC_PORT

Data Buffer Access Port, offset: 0x20

◆ DATACH

__I uint32_t PDM_Type::DATACH

PDM Output Result Register, array offset: 0x24, array step: 0x4

◆ DBG1

__I uint32_t CAN_Type::DBG1

Debug 1 register, offset: 0x58

◆ DBG2

__I uint32_t CAN_Type::DBG2

Debug 2 register, offset: 0x5C

◆ DBGDATA

__I uint32_t DCP_Type::DBGDATA

DCP debug data register, offset: 0x410

◆ DBGSELECT

__IO uint32_t DCP_Type::DBGSELECT

DCP debug select register, offset: 0x400

◆ DBICR0

__IO uint32_t SEMC_Type::DBICR0

DBI-B control register 0, offset: 0x80

DBI-B Control Register 0, offset: 0x80

◆ DBICR1

__IO uint32_t SEMC_Type::DBICR1

DBI-B control register 1, offset: 0x84

DBI-B Control Register 1, offset: 0x84

◆ DBICR2

__IO uint32_t SEMC_Type::DBICR2

DBI-B Control Register 2, offset: 0x88

◆ DC_CTRL

__IO uint32_t PDM_Type::DC_CTRL

PDM DC Remover Control register, offset: 0x64

◆ DCCPARAMS

__I uint32_t USB_Type::DCCPARAMS

Device Controller Capability Parameters, offset: 0x124

◆ DCCR

__IO uint32_t SEMC_Type::DCCR

Delay Chain Control Register, offset: 0x150

◆ DCHPRI0

__IO uint8_t DMA_Type::DCHPRI0

Channel Priority, offset: 0x103

◆ DCHPRI1

__IO uint8_t DMA_Type::DCHPRI1

Channel Priority, offset: 0x102

◆ DCHPRI10

__IO uint8_t DMA_Type::DCHPRI10

Channel Priority, offset: 0x109

◆ DCHPRI11

__IO uint8_t DMA_Type::DCHPRI11

Channel Priority, offset: 0x108

◆ DCHPRI12

__IO uint8_t DMA_Type::DCHPRI12

Channel Priority, offset: 0x10F

◆ DCHPRI13

__IO uint8_t DMA_Type::DCHPRI13

Channel Priority, offset: 0x10E

◆ DCHPRI14

__IO uint8_t DMA_Type::DCHPRI14

Channel Priority, offset: 0x10D

◆ DCHPRI15

__IO uint8_t DMA_Type::DCHPRI15

Channel Priority, offset: 0x10C

◆ DCHPRI16

__IO uint8_t DMA_Type::DCHPRI16

Channel Priority, offset: 0x113

◆ DCHPRI17

__IO uint8_t DMA_Type::DCHPRI17

Channel Priority, offset: 0x112

◆ DCHPRI18

__IO uint8_t DMA_Type::DCHPRI18

Channel Priority, offset: 0x111

◆ DCHPRI19

__IO uint8_t DMA_Type::DCHPRI19

Channel Priority, offset: 0x110

◆ DCHPRI2

__IO uint8_t DMA_Type::DCHPRI2

Channel Priority, offset: 0x101

◆ DCHPRI20

__IO uint8_t DMA_Type::DCHPRI20

Channel Priority, offset: 0x117

◆ DCHPRI21

__IO uint8_t DMA_Type::DCHPRI21

Channel Priority, offset: 0x116

◆ DCHPRI22

__IO uint8_t DMA_Type::DCHPRI22

Channel Priority, offset: 0x115

◆ DCHPRI23

__IO uint8_t DMA_Type::DCHPRI23

Channel Priority, offset: 0x114

◆ DCHPRI24

__IO uint8_t DMA_Type::DCHPRI24

Channel Priority, offset: 0x11B

◆ DCHPRI25

__IO uint8_t DMA_Type::DCHPRI25

Channel Priority, offset: 0x11A

◆ DCHPRI26

__IO uint8_t DMA_Type::DCHPRI26

Channel Priority, offset: 0x119

◆ DCHPRI27

__IO uint8_t DMA_Type::DCHPRI27

Channel Priority, offset: 0x118

◆ DCHPRI28

__IO uint8_t DMA_Type::DCHPRI28

Channel Priority, offset: 0x11F

◆ DCHPRI29

__IO uint8_t DMA_Type::DCHPRI29

Channel Priority, offset: 0x11E

◆ DCHPRI3

__IO uint8_t DMA_Type::DCHPRI3

Channel Priority, offset: 0x100

◆ DCHPRI30

__IO uint8_t DMA_Type::DCHPRI30

Channel Priority, offset: 0x11D

◆ DCHPRI31

__IO uint8_t DMA_Type::DCHPRI31

Channel Priority, offset: 0x11C

◆ DCHPRI4

__IO uint8_t DMA_Type::DCHPRI4

Channel Priority, offset: 0x107

◆ DCHPRI5

__IO uint8_t DMA_Type::DCHPRI5

Channel Priority, offset: 0x106

◆ DCHPRI6

__IO uint8_t DMA_Type::DCHPRI6

Channel Priority, offset: 0x105

◆ DCHPRI7

__IO uint8_t DMA_Type::DCHPRI7

Channel Priority, offset: 0x104

◆ DCHPRI8

__IO uint8_t DMA_Type::DCHPRI8

Channel Priority, offset: 0x10B

◆ DCHPRI9

__IO uint8_t DMA_Type::DCHPRI9

Channel Priority, offset: 0x10A

◆ DCICC

__IO uint32_t DCIC_Type::DCICC

DCIC Control Register, offset: 0x0

◆ DCICIC

__IO uint32_t DCIC_Type::DCICIC

DCIC Interrupt Control Register, offset: 0x4

◆ DCICRC [1/3]

__IO uint32_t DCIC_Type::DCICRC

DCIC ROI Config Register, array offset: 0x10, array step: 0x10

◆  [2/3]

__IO uint32_t { ... } ::DCICRC

DCIC ROI Config Register, array offset: 0x10, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::DCICRC

DCIC ROI Config Register, array offset: 0x10, array step: 0x10

◆  [1/3]

__I uint32_t { ... } ::DCICRCS

DCIC ROI Calculated Signature Register, array offset: 0x1C, array step: 0x10

◆ DCICRCS [2/3]

__I uint32_t DCIC_Type::DCICRCS

DCIC ROI Calculated Signature Register, array offset: 0x1C, array step: 0x10

◆  [3/3]

__I uint32_t { ... } ::DCICRCS

DCIC ROI Calculated Signature Register, array offset: 0x1C, array step: 0x10

◆ DCICRRS [1/3]

__IO uint32_t DCIC_Type::DCICRRS

DCIC ROI Reference Signature Register, array offset: 0x18, array step: 0x10

◆  [2/3]

__IO uint32_t { ... } ::DCICRRS

DCIC ROI Reference Signature Register, array offset: 0x18, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::DCICRRS

DCIC ROI Reference Signature Register, array offset: 0x18, array step: 0x10

◆ DCICRS [1/3]

__IO uint32_t DCIC_Type::DCICRS

DCIC ROI Size Register, array offset: 0x14, array step: 0x10

◆  [2/3]

__IO uint32_t { ... } ::DCICRS

DCIC ROI Size Register, array offset: 0x14, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::DCICRS

DCIC ROI Size Register, array offset: 0x14, array step: 0x10

◆ DCICS

__IO uint32_t DCIC_Type::DCICS

DCIC Status Register, offset: 0x8

◆ DCIVERSION

__I uint16_t USB_Type::DCIVERSION

Device Controller Interface Version, offset: 0x120

◆ DDAR [1/3]

__I uint64_t CAAM_Type::DDAR

DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C

◆  [2/3]

__I uint64_t { ... } ::DDAR

DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C

◆  [3/3]

__I uint64_t { ... } ::DDAR

DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C

◆  [1/3]

__I uint32_t { ... } ::DDDR

DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C

◆ DDDR [2/3]

__I uint32_t CAAM_Type::DDDR

DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::DDDR

DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C

◆ DDDR_LS [1/3]

__I uint32_t CAAM_Type::DDDR_LS

DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C

◆  [2/3]

__I uint32_t { ... } ::DDDR_LS

DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::DDDR_LS

DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C

◆ DDDR_MS [1/3]

__I uint32_t CAAM_Type::DDDR_MS

DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C

◆  [2/3]

__I uint32_t { ... } ::DDDR_MS

DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::DDDR_MS

DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C

◆  [1/3]

__IO uint32_t { ... } ::DDESB[64]

DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4

◆ DDESB [2/3]

__IO uint32_t CAAM_Type::DDESB[64]

DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4

◆  [3/3]

__IO uint32_t { ... } ::DDESB[64]

DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4

◆  [1/3]

__I uint64_t { ... } ::DDJP

DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C

◆ DDJP [2/3]

__I uint64_t CAAM_Type::DDJP

DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C

◆  [3/3]

__I uint64_t { ... } ::DDJP

DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C

◆  [1/3]

__I uint32_t { ... } ::DDJR

DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C

◆ DDJR [2/3]

__I uint32_t CAAM_Type::DDJR

DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::DDJR

DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C

◆ DE

__IO uint32_t ADC_Type::DE

DMA Enable Register, offset: 0x1C

◆ DEBUG0_STATUS

__I uint32_t USBPHY_Type::DEBUG0_STATUS

UTMI Debug Status Register 0, offset: 0x60

◆ DEBUG1

__IO uint32_t USBPHY_Type::DEBUG1

UTMI Debug Status Register 1, offset: 0x70

◆ DEBUG1_CLR

__IO uint32_t USBPHY_Type::DEBUG1_CLR

UTMI Debug Status Register 1, offset: 0x78

◆ DEBUG1_SET

__IO uint32_t USBPHY_Type::DEBUG1_SET

UTMI Debug Status Register 1, offset: 0x74

◆ DEBUG1_TOG

__IO uint32_t USBPHY_Type::DEBUG1_TOG

UTMI Debug Status Register 1, offset: 0x7C

◆ DEBUG_CLR

__IO uint32_t USBPHY_Type::DEBUG_CLR

USB PHY Debug Register, offset: 0x58

◆ DEBUG_MODE

__IO uint32_t TSC_Type::DEBUG_MODE

Debug Mode Register, offset: 0x70

◆ DEBUG_MODE2

__IO uint32_t TSC_Type::DEBUG_MODE2

Debug Mode Register 2, offset: 0x80

◆ DEBUG_SET

__IO uint32_t USBPHY_Type::DEBUG_SET

USB PHY Debug Register, offset: 0x54

◆ DEBUG_TOG

__IO uint32_t USBPHY_Type::DEBUG_TOG

USB PHY Debug Register, offset: 0x5C

◆ DEBUGCTL

__IO uint32_t CAAM_Type::DEBUGCTL

Debug Control Register, offset: 0x58

◆ DEBUGr

__IO uint32_t USBPHY_Type::DEBUGr

USB PHY Debug Register, offset: 0x50, 'r' suffix has been added to avoid clash with DEBUG symbolic constant

◆ DECODID_LS [1/3]

__IO uint32_t CAAM_Type::DECODID_LS

DECO0 DID Register - least significant half, array offset: 0xA4, array step: 0x8

◆  [2/3]

__IO uint32_t { ... } ::DECODID_LS

DECO0 DID Register - least significant half, array offset: 0xA4, array step: 0x8

◆  [3/3]

__IO uint32_t { ... } ::DECODID_LS

DECO0 DID Register - least significant half, array offset: 0xA4, array step: 0x8

◆  [1/3]

__IO uint32_t { ... } ::DECODID_MS

DECO0 DID Register - most significant half, array offset: 0xA0, array step: 0x8

◆ DECODID_MS [2/3]

__IO uint32_t CAAM_Type::DECODID_MS

DECO0 DID Register - most significant half, array offset: 0xA0, array step: 0x8

◆  [3/3]

__IO uint32_t { ... } ::DECODID_MS

DECO0 DID Register - most significant half, array offset: 0xA0, array step: 0x8

◆ DECORR

__IO uint32_t CAAM_Type::DECORR

DECO Request Register, offset: 0x9C

◆ DECORSR

__IO uint32_t CAAM_Type::DECORSR

DECO Request Source Register, offset: 0x94

◆ DER

__IO uint32_t LPSPI_Type::DER

DMA Enable Register, offset: 0x1C

DMA Enable, offset: 0x1C

◆  [1/3]

__IO uint32_t { ... } ::DESC_ADDR_DOWN

Descriptor Address Down 0 Register..Descriptor Address Down 15 Register, array offset: 0xC, array step: 0x20

◆ DESC_ADDR_DOWN [2/3]

__IO uint32_t SSARC_LP_Type::DESC_ADDR_DOWN

Descriptor Address Down 0 Register..Descriptor Address Down 15 Register, array offset: 0xC, array step: 0x20

◆  [3/3]

__IO uint32_t { ... } ::DESC_ADDR_DOWN

Descriptor Address Down 0 Register..Descriptor Address Down 15 Register, array offset: 0xC, array step: 0x20

◆  [1/3]

__IO uint32_t { ... } ::DESC_ADDR_UP

Descriptor Address Up 0 Register..Descriptor Address Up 15 Register, array offset: 0x8, array step: 0x20

◆ DESC_ADDR_UP [2/3]

__IO uint32_t SSARC_LP_Type::DESC_ADDR_UP

Descriptor Address Up 0 Register..Descriptor Address Up 15 Register, array offset: 0x8, array step: 0x20

◆  [3/3]

__IO uint32_t { ... } ::DESC_ADDR_UP

Descriptor Address Up 0 Register..Descriptor Address Up 15 Register, array offset: 0x8, array step: 0x20

◆  [1/3]

__IO uint32_t { ... } ::DESC_CTRL0

Descriptor Control0 0 Register..Descriptor Control0 15 Register, array offset: 0x0, array step: 0x20

◆ DESC_CTRL0 [2/3]

__IO uint32_t SSARC_LP_Type::DESC_CTRL0

Descriptor Control0 0 Register..Descriptor Control0 15 Register, array offset: 0x0, array step: 0x20

◆  [3/3]

__IO uint32_t { ... } ::DESC_CTRL0

Descriptor Control0 0 Register..Descriptor Control0 15 Register, array offset: 0x0, array step: 0x20

◆  [1/3]

__IO uint32_t { ... } ::DESC_CTRL1

Descriptor Control1 0 Register..Descriptor Control1 15 Register, array offset: 0x4, array step: 0x20

◆ DESC_CTRL1 [2/3]

__IO uint32_t SSARC_LP_Type::DESC_CTRL1

Descriptor Control1 0 Register..Descriptor Control1 15 Register, array offset: 0x4, array step: 0x20

◆  [3/3]

__IO uint32_t { ... } ::DESC_CTRL1

Descriptor Control1 0 Register..Descriptor Control1 15 Register, array offset: 0x4, array step: 0x20

◆  [1/4]

__IO uint32_t { ... } ::DEVICEADDR

Device Address, offset: 0x154

◆ DEVICEADDR [2/4]

__IO uint32_t USB_Type::DEVICEADDR

Device Address, offset: 0x154

◆  [3/4]

__IO uint32_t { ... } ::DEVICEADDR

Device Address, offset: 0x154

◆  [4/4]

__IO uint32_t { ... } ::DEVICEADDR

Device Address, offset: 0x154

◆  [1/3]

__IO uint32_t { ... } ::DGTR_0

DECO0 Gather Table Register 0 Word 0, array offset: 0x80880, array step: index*0xE3C, index2*0x10

◆ DGTR_0 [2/3]

__IO uint32_t CAAM_Type::DGTR_0

DECO0 Gather Table Register 0 Word 0, array offset: 0x80880, array step: index*0xE3C, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::DGTR_0

DECO0 Gather Table Register 0 Word 0, array offset: 0x80880, array step: index*0xE3C, index2*0x10

◆ DGTR_1 [1/3]

__IO uint32_t CAAM_Type::DGTR_1

DECO0 Gather Table Register 0 Word 1, array offset: 0x80884, array step: index*0xE3C, index2*0x10

◆  [2/3]

__IO uint32_t { ... } ::DGTR_1

DECO0 Gather Table Register 0 Word 1, array offset: 0x80884, array step: index*0xE3C, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::DGTR_1

DECO0 Gather Table Register 0 Word 1, array offset: 0x80884, array step: index*0xE3C, index2*0x10

◆ DGTR_2 [1/3]

__IO uint32_t CAAM_Type::DGTR_2

DECO0 Gather Table Register 0 Word 2, array offset: 0x80888, array step: index*0xE3C, index2*0x10

◆  [2/3]

__IO uint32_t { ... } ::DGTR_2

DECO0 Gather Table Register 0 Word 2, array offset: 0x80888, array step: index*0xE3C, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::DGTR_2

DECO0 Gather Table Register 0 Word 2, array offset: 0x80888, array step: index*0xE3C, index2*0x10

◆  [1/3]

__IO uint32_t { ... } ::DGTR_3

DECO0 Gather Table Register 0 Word 3, array offset: 0x8088C, array step: index*0xE3C, index2*0x10

◆ DGTR_3 [2/3]

__IO uint32_t CAAM_Type::DGTR_3

DECO0 Gather Table Register 0 Word 3, array offset: 0x8088C, array step: index*0xE3C, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::DGTR_3

DECO0 Gather Table Register 0 Word 3, array offset: 0x8088C, array step: index*0xE3C, index2*0x10

◆ DIGPROG

__I uint32_t USB_ANALOG_Type::DIGPROG

Chip Silicon Version, offset: 0x260

◆ DIRECT [1/5]

__IO uint32_t CCM_Type::DIRECT

Clock source direct control, array offset: 0x5000, array step: 0x20

LPCG direct control, array offset: 0x6000, array step: 0x20

◆  [2/5]

__IO uint32_t { ... } ::DIRECT

Clock source direct control, array offset: 0x5000, array step: 0x20

◆  [3/5]

__IO uint32_t { ... } ::DIRECT

LPCG direct control, array offset: 0x6000, array step: 0x20

◆  [4/5]

__IO uint32_t { ... } ::DIRECT

Clock source direct control, array offset: 0x5000, array step: 0x20

◆  [5/5]

__IO uint32_t { ... } ::DIRECT

LPCG direct control, array offset: 0x6000, array step: 0x20

◆  [1/4]

__IO uint16_t { ... } ::DISMAP[1]

Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2

◆  [2/4]

__IO uint16_t { ... } ::DISMAP[1]

Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2

◆  [3/4]

__IO uint16_t { ... } ::DISMAP[2]

Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2

◆ DISMAP [4/4]

__IO uint16_t PWM_Type::DISMAP[1]

Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2

Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2

◆ DISP_PARA

__IO uint32_t LCDIFV2_Type::DISP_PARA

Display Parameter Register, offset: 0x10

◆ DISP_SIZE

__IO uint32_t LCDIFV2_Type::DISP_SIZE

Display Size Register, offset: 0x14

◆ DIVISOR

__IO uint32_t EMVSIM_Type::DIVISOR

Baud Rate Divisor Register, offset: 0xC

◆ DJQCR_LS [1/3]

__I uint32_t CAAM_Type::DJQCR_LS

DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C

◆  [2/3]

__I uint32_t { ... } ::DJQCR_LS

DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::DJQCR_LS

DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C

◆  [1/3]

__IO uint32_t { ... } ::DJQCR_MS

DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C

◆ DJQCR_MS [2/3]

__IO uint32_t CAAM_Type::DJQCR_MS

DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::DJQCR_MS

DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C

◆  [1/4]

__IO int32_t { ... } ::DLAST_SGA

TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20

◆ DLAST_SGA [2/4]

__IO int32_t DMA_Type::DLAST_SGA

TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20

◆  [3/4]

__IO int32_t { ... } ::DLAST_SGA

TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20

◆  [4/4]

__IO int32_t { ... } ::DLAST_SGA

TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20

◆ DLL_CTRL

__IO uint32_t USDHC_Type::DLL_CTRL

DLL (Delay Line) Control, offset: 0x60

◆ DLL_STATUS

__I uint32_t USDHC_Type::DLL_STATUS

DLL Status, offset: 0x64

◆ DLLCR [1/2]

__IO uint32_t FLEXSPI_Type::DLLCR

DLL Control Register 0, array offset: 0xC0, array step: 0x4

◆ DLLCR [2/2]

__IO uint32_t SEMC_Type::DLLCR

DLL Control Register, offset: 0x34

◆  [1/4]

__IO uint16_t { ... } ::DMA

Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20

◆ DMA [2/4]

__IO uint16_t TMR_Type::DMA

Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::DMA

Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::DMA

Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20

◆ DMA0_AID_ENB

__I uint32_t CAAM_Type::DMA0_AID_ENB

DMA0 AXI ID Enable Register, offset: 0x250

◆ DMA0_ARD_LAT

__IO uint32_t CAAM_Type::DMA0_ARD_LAT

DMA0 Read Timing Check Latency Register, offset: 0x26C

◆ DMA0_ARD_TC

__IO uint64_t CAAM_Type::DMA0_ARD_TC

DMA0 AXI Read Timing Check Register, offset: 0x260

◆ DMA0_AWR_LAT

__IO uint32_t CAAM_Type::DMA0_AWR_LAT

DMA0 Write Timing Check Latency Register, offset: 0x27C

◆ DMA0_AWR_TC

__IO uint64_t CAAM_Type::DMA0_AWR_TC

DMA0 AXI Write Timing Check Register, offset: 0x270

◆  [1/3]

__I uint32_t { ... } ::DMA_AIDL_MAP_LS

DMA0_AIDL_MAP_LS, array offset: 0x244, array step: 0x10

◆ DMA_AIDL_MAP_LS [2/3]

__I uint32_t CAAM_Type::DMA_AIDL_MAP_LS

DMA0_AIDL_MAP_LS, array offset: 0x244, array step: 0x10

◆  [3/3]

__I uint32_t { ... } ::DMA_AIDL_MAP_LS

DMA0_AIDL_MAP_LS, array offset: 0x244, array step: 0x10

◆  [1/3]

__I uint32_t { ... } ::DMA_AIDL_MAP_MS

DMA0_AIDL_MAP_MS, array offset: 0x240, array step: 0x10

◆ DMA_AIDL_MAP_MS [2/3]

__I uint32_t CAAM_Type::DMA_AIDL_MAP_MS

DMA0_AIDL_MAP_MS, array offset: 0x240, array step: 0x10

◆  [3/3]

__I uint32_t { ... } ::DMA_AIDL_MAP_MS

DMA0_AIDL_MAP_MS, array offset: 0x240, array step: 0x10

◆  [1/3]

__I uint32_t { ... } ::DMA_AIDM_MAP_LS

DMA0_AIDM_MAP_LS, array offset: 0x24C, array step: 0x10

◆ DMA_AIDM_MAP_LS [2/3]

__I uint32_t CAAM_Type::DMA_AIDM_MAP_LS

DMA0_AIDM_MAP_LS, array offset: 0x24C, array step: 0x10

◆  [3/3]

__I uint32_t { ... } ::DMA_AIDM_MAP_LS

DMA0_AIDM_MAP_LS, array offset: 0x24C, array step: 0x10

◆  [1/3]

__I uint32_t { ... } ::DMA_AIDM_MAP_MS

DMA0_AIDM_MAP_MS, array offset: 0x248, array step: 0x10

◆ DMA_AIDM_MAP_MS [2/3]

__I uint32_t CAAM_Type::DMA_AIDM_MAP_MS

DMA0_AIDM_MAP_MS, array offset: 0x248, array step: 0x10

◆  [3/3]

__I uint32_t { ... } ::DMA_AIDM_MAP_MS

DMA0_AIDM_MAP_MS, array offset: 0x248, array step: 0x10

◆ DMA_CTRL

__IO uint32_t ADC_ETC_Type::DMA_CTRL

ETC DMA control Register, offset: 0xC

◆ DMA_STA

__I uint32_t CAAM_Type::DMA_STA

DMA Status Register, offset: 0x50C

◆ DMA_X_AID_11_8_MAP

__I uint32_t CAAM_Type::DMA_X_AID_11_8_MAP

DMA_X_AID_11_8_MAP, offset: 0x51C

◆ DMA_X_AID_15_0_EN

__I uint32_t CAAM_Type::DMA_X_AID_15_0_EN

DMA_X AXI ID Map Enable Register, offset: 0x524

◆ DMA_X_AID_15_12_MAP

__I uint32_t CAAM_Type::DMA_X_AID_15_12_MAP

DMA_X_AID_15_12_MAP, offset: 0x518

◆ DMA_X_AID_3_0_MAP

__I uint32_t CAAM_Type::DMA_X_AID_3_0_MAP

DMA_X_AID_3_0_MAP, offset: 0x514

◆ DMA_X_AID_7_4_MAP

__I uint32_t CAAM_Type::DMA_X_AID_7_4_MAP

DMA_X_AID_7_4_MAP, offset: 0x510

◆ DMA_X_ARTC_CTL

__IO uint32_t CAAM_Type::DMA_X_ARTC_CTL

DMA_X AXI Read Timing Check Control Register, offset: 0x530

◆ DMA_X_ARTC_LAT

__IO uint32_t CAAM_Type::DMA_X_ARTC_LAT

DMA_X Read Timing Check Latency Register, offset: 0x53C

◆ DMA_X_ARTC_LC

__IO uint32_t CAAM_Type::DMA_X_ARTC_LC

DMA_X AXI Read Timing Check Late Count Register, offset: 0x534

◆ DMA_X_ARTC_SC

__IO uint32_t CAAM_Type::DMA_X_ARTC_SC

DMA_X AXI Read Timing Check Sample Count Register, offset: 0x538

◆ DMA_X_AWTC_CTL

__IO uint32_t CAAM_Type::DMA_X_AWTC_CTL

DMA_X AXI Write Timing Check Control Register, offset: 0x540

◆ DMA_X_AWTC_LAT

__IO uint32_t CAAM_Type::DMA_X_AWTC_LAT

DMA_X Write Timing Check Latency Register, offset: 0x54C

◆ DMA_X_AWTC_LC

__IO uint32_t CAAM_Type::DMA_X_AWTC_LC

DMA_X AXI Write Timing Check Late Count Register, offset: 0x544

◆ DMA_X_AWTC_SC

__IO uint32_t CAAM_Type::DMA_X_AWTC_SC

DMA_X AXI Write Timing Check Sample Count Register, offset: 0x548

◆ DMACFG

__IO uint32_t ENET_Type::DMACFG

DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4

◆ DMAEN [1/4]

__IO uint16_t PWM_Type::DMAEN

DMA Enable Register, array offset: 0x28, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::DMAEN

DMA Enable Register, array offset: 0x28, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::DMAEN

DMA Enable Register, array offset: 0x28, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::DMAEN

DMA Enable Register, array offset: 0x28, array step: 0x60

◆ DMASA_FB1

__IO uint32_t CSI_Type::DMASA_FB1

CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28

◆ DMASA_FB2

__IO uint32_t CSI_Type::DMASA_FB2

CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C

◆ DMASA_STATFIFO

__IO uint32_t CSI_Type::DMASA_STATFIFO

CSI DMA Start Address Register - for STATFIFO, offset: 0x20

◆ DMATS_STATFIFO

__IO uint32_t CSI_Type::DMATS_STATFIFO

CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24

◆ DMR0

__IO uint32_t LPSPI_Type::DMR0

Data Match Register 0, offset: 0x30

Data Match 0, offset: 0x30

◆ DMR1

__IO uint32_t LPSPI_Type::DMR1

Data Match Register 1, offset: 0x34

Data Match 1, offset: 0x34

◆  [1/3]

__IO uint32_t { ... } ::DMTH_LS

DECO0 Math Register 0_LS..DECO0 Math Register 3_LS, array offset: 0x80844, array step: index*0xE3C, index2*0x8

◆ DMTH_LS [2/3]

__IO uint32_t CAAM_Type::DMTH_LS

DECO0 Math Register 0_LS..DECO0 Math Register 3_LS, array offset: 0x80844, array step: index*0xE3C, index2*0x8

◆  [3/3]

__IO uint32_t { ... } ::DMTH_LS

DECO0 Math Register 0_LS..DECO0 Math Register 3_LS, array offset: 0x80844, array step: index*0xE3C, index2*0x8

◆  [1/3]

__IO uint32_t { ... } ::DMTH_MS

DECO0 Math Register 0_MS..DECO0 Math Register 3_MS, array offset: 0x80840, array step: index*0xE3C, index2*0x8

◆ DMTH_MS [2/3]

__IO uint32_t CAAM_Type::DMTH_MS

DECO0 Math Register 0_MS..DECO0 Math Register 3_MS, array offset: 0x80840, array step: index*0xE3C, index2*0x8

◆  [3/3]

__IO uint32_t { ... } ::DMTH_MS

DECO0 Math Register 0_MS..DECO0 Math Register 3_MS, array offset: 0x80840, array step: index*0xE3C, index2*0x8

◆ DODIDSR [1/3]

__I uint32_t CAAM_Type::DODIDSR

DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C

◆  [2/3]

__I uint32_t { ... } ::DODIDSR

DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::DODIDSR

DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C

◆  [1/4]

__IO uint16_t { ... } ::DOFF

TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20

◆ DOFF [2/4]

__IO uint16_t DMA_Type::DOFF

TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::DOFF

TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::DOFF

TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20

◆ DOMAIN_DISPLAY

__IO uint32_t SRC_Type::DOMAIN_DISPLAY

Slice Domain Config Register, offset: 0x22C

◆ DOMAIN_M4CORE

__IO uint32_t SRC_Type::DOMAIN_M4CORE

Slice Domain Config Register, offset: 0x28C

◆ DOMAIN_M4DEBUG

__IO uint32_t SRC_Type::DOMAIN_M4DEBUG

Slice Domain Config Register, offset: 0x2CC

◆ DOMAIN_M7CORE

__IO uint32_t SRC_Type::DOMAIN_M7CORE

Slice Domain Config Register, offset: 0x2AC

◆ DOMAIN_M7DEBUG

__IO uint32_t SRC_Type::DOMAIN_M7DEBUG

Slice Domain Config Register, offset: 0x2EC

◆ DOMAIN_MEGA

__IO uint32_t SRC_Type::DOMAIN_MEGA

Slice Domain Config Register, offset: 0x20C

◆ DOMAIN_USBPHY1

__IO uint32_t SRC_Type::DOMAIN_USBPHY1

Slice Domain Config Register, offset: 0x30C

◆ DOMAIN_USBPHY2

__IO uint32_t SRC_Type::DOMAIN_USBPHY2

Slice Domain Config Register, offset: 0x32C

◆ DOMAIN_WAKEUP

__IO uint32_t SRC_Type::DOMAIN_WAKEUP

Slice Domain Config Register, offset: 0x24C

◆ DOMAINr [1/5]

__IO uint32_t CCM_Type::DOMAINr

Clock source domain control, array offset: 0x5004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h

LPCG domain control, array offset: 0x6004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h

◆  [2/5]

__IO uint32_t { ... } ::DOMAINr

Clock source domain control, array offset: 0x5004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h

◆  [3/5]

__IO uint32_t { ... } ::DOMAINr

LPCG domain control, array offset: 0x6004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h

◆  [4/5]

__IO uint32_t { ... } ::DOMAINr

Clock source domain control, array offset: 0x5004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h

◆  [5/5]

__IO uint32_t { ... } ::DOMAINr

LPCG domain control, array offset: 0x6004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h

◆ DONE0_1_IRQ

__IO uint32_t ADC_ETC_Type::DONE0_1_IRQ

ETC DONE0 and DONE1 IRQ State Register, offset: 0x4

◆ DONE2_3_ERR_IRQ

__IO uint32_t ADC_ETC_Type::DONE2_3_ERR_IRQ

ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8

ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register, offset: 0x8

◆ DOPSTA_LS [1/3]

__I uint32_t CAAM_Type::DOPSTA_LS

DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C

◆  [2/3]

__I uint32_t { ... } ::DOPSTA_LS

DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::DOPSTA_LS

DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C

◆  [1/3]

__I uint32_t { ... } ::DOPSTA_MS

DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C

◆ DOPSTA_MS [2/3]

__I uint32_t CAAM_Type::DOPSTA_MS

DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::DOPSTA_MS

DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C

◆ DPAMS

__O uint32_t IEE_Type::DPAMS

AES Mask Generation Seed, offset: 0xC

◆ DPDIDSR [1/3]

__I uint32_t CAAM_Type::DPDIDSR

DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C

◆  [2/3]

__I uint32_t { ... } ::DPDIDSR

DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C

◆  [3/3]

__I uint32_t { ... } ::DPDIDSR

DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C

◆ DPOVRD [1/3]

__IO uint32_t CAAM_Type::DPOVRD

Protocol Override Register, array offset: 0x80E30, array step: 0xE3C

◆  [2/3]

__IO uint32_t { ... } ::DPOVRD

Protocol Override Register, array offset: 0x80E30, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::DPOVRD

Protocol Override Register, array offset: 0x80E30, array step: 0xE3C

◆ DR

__IO uint32_t GPIO_Type::DR

GPIO data register, offset: 0x0

◆ DR_CLEAR

__O uint32_t GPIO_Type::DR_CLEAR

GPIO data register CLEAR, offset: 0x88

◆ DR_SET

__O uint32_t GPIO_Type::DR_SET

GPIO data register SET, offset: 0x84

◆ DR_TOGGLE

__O uint32_t GPIO_Type::DR_TOGGLE

GPIO data register TOGGLE, offset: 0x8C

◆ DRR

__O uint32_t CAAM_Type::DRR

DECO Reset Register, offset: 0x124

◆ DS_ADDR

__IO uint32_t USDHC_Type::DS_ADDR

DMA System Address, offset: 0x0

◆  [1/3]

__I uint64_t { ... } ::DSDP

DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C

◆ DSDP [2/3]

__I uint64_t CAAM_Type::DSDP

DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C

◆  [3/3]

__I uint64_t { ... } ::DSDP

DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C

◆ DSTR_0 [1/3]

__IO uint32_t CAAM_Type::DSTR_0

DECO0 Scatter Table Register 0 Word 0, array offset: 0x80900, array step: index*0xE3C, index2*0x10

◆  [2/3]

__IO uint32_t { ... } ::DSTR_0

DECO0 Scatter Table Register 0 Word 0, array offset: 0x80900, array step: index*0xE3C, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::DSTR_0

DECO0 Scatter Table Register 0 Word 0, array offset: 0x80900, array step: index*0xE3C, index2*0x10

◆  [1/3]

__IO uint32_t { ... } ::DSTR_1

DECO0 Scatter Table Register 0 Word 1, array offset: 0x80904, array step: index*0xE3C, index2*0x10

◆ DSTR_1 [2/3]

__IO uint32_t CAAM_Type::DSTR_1

DECO0 Scatter Table Register 0 Word 1, array offset: 0x80904, array step: index*0xE3C, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::DSTR_1

DECO0 Scatter Table Register 0 Word 1, array offset: 0x80904, array step: index*0xE3C, index2*0x10

◆ DSTR_2 [1/3]

__IO uint32_t CAAM_Type::DSTR_2

DECO0 Scatter Table Register 0 Word 2, array offset: 0x80908, array step: index*0xE3C, index2*0x10

◆  [2/3]

__IO uint32_t { ... } ::DSTR_2

DECO0 Scatter Table Register 0 Word 2, array offset: 0x80908, array step: index*0xE3C, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::DSTR_2

DECO0 Scatter Table Register 0 Word 2, array offset: 0x80908, array step: index*0xE3C, index2*0x10

◆ DSTR_3 [1/3]

__IO uint32_t CAAM_Type::DSTR_3

DECO0 Scatter Table Register 0 Word 3, array offset: 0x8090C, array step: index*0xE3C, index2*0x10

◆  [2/3]

__IO uint32_t { ... } ::DSTR_3

DECO0 Scatter Table Register 0 Word 3, array offset: 0x8090C, array step: index*0xE3C, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::DSTR_3

DECO0 Scatter Table Register 0 Word 3, array offset: 0x8090C, array step: index*0xE3C, index2*0x10

◆ DTCM_MAGIC_ADDR

__IO uint32_t FLEXRAM_Type::DTCM_MAGIC_ADDR

DTCM Magic Address Register, offset: 0x8

◆  [1/4]

__IO uint16_t { ... } ::DTCNT0

Deadtime Count Register 0, array offset: 0x30, array step: 0x60

◆ DTCNT0 [2/4]

__IO uint16_t PWM_Type::DTCNT0

Deadtime Count Register 0, array offset: 0x30, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::DTCNT0

Deadtime Count Register 0, array offset: 0x30, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::DTCNT0

Deadtime Count Register 0, array offset: 0x30, array step: 0x60

◆  [1/4]

__IO uint16_t { ... } ::DTCNT1

Deadtime Count Register 1, array offset: 0x32, array step: 0x60

◆ DTCNT1 [2/4]

__IO uint16_t PWM_Type::DTCNT1

Deadtime Count Register 1, array offset: 0x32, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::DTCNT1

Deadtime Count Register 1, array offset: 0x32, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::DTCNT1

Deadtime Count Register 1, array offset: 0x32, array step: 0x60

◆ DTSRCSEL

__IO uint16_t PWM_Type::DTSRCSEL

PWM Source Select Register, offset: 0x186

◆ EARS

__IO uint32_t DMA_Type::EARS

Enable Asynchronous Request in Stop, offset: 0x44

◆ ECC_BASE_ADDR0

__IO uint32_t XECC_Type::ECC_BASE_ADDR0

ECC Region 0 Base Address, offset: 0x3C

◆ ECC_BASE_ADDR1

__IO uint32_t XECC_Type::ECC_BASE_ADDR1

ECC Region 1 Base Address, offset: 0x44

◆ ECC_BASE_ADDR2

__IO uint32_t XECC_Type::ECC_BASE_ADDR2

ECC Region 2 Base Address, offset: 0x4C

◆ ECC_BASE_ADDR3

__IO uint32_t XECC_Type::ECC_BASE_ADDR3

ECC Region 3 Base Address, offset: 0x54

◆ ECC_CTRL

__IO uint32_t XECC_Type::ECC_CTRL

ECC Control Register, offset: 0x0

◆ ECC_END_ADDR0

__IO uint32_t XECC_Type::ECC_END_ADDR0

ECC Region 0 End Address, offset: 0x40

◆ ECC_END_ADDR1

__IO uint32_t XECC_Type::ECC_END_ADDR1

ECC Region 1 End Address, offset: 0x48

◆ ECC_END_ADDR2

__IO uint32_t XECC_Type::ECC_END_ADDR2

ECC Region 2 End Address, offset: 0x50

◆ ECC_END_ADDR3

__IO uint32_t XECC_Type::ECC_END_ADDR3

ECC Region 3 End Address, offset: 0x58

◆ ECR [1/2]

__IO uint32_t CAN_Type::ECR

Error Counter Register, offset: 0x1C

Error Counter, offset: 0x1C

◆ ECR [2/2]

__IO uint32_t ENET_Type::ECR

Ethernet Control Register, offset: 0x24

◆ EDGE_SEL

__IO uint32_t GPIO_Type::EDGE_SEL

GPIO edge select register, offset: 0x1C

◆ EEI

__IO uint32_t DMA_Type::EEI

Enable Error Interrupt, offset: 0x14

◆ EIMR

__IO uint32_t ENET_Type::EIMR

Interrupt Mask Register, offset: 0x8

◆ EIR

__IO uint32_t ENET_Type::EIR

Interrupt Event Register, offset: 0x4

◆ ENABLE_MULT_PKTS

__IO uint32_t DSI_HOST_DPI_INTFC_Type::ENABLE_MULT_PKTS

ENABLE_MULT_PKTS, offset: 0x28

◆  [1/4]

__IO uint16_t { ... } ::ENBL

Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances

◆ ENBL [2/4]

__IO uint16_t TMR_Type::ENBL

Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances

◆  [3/4]

__IO uint16_t { ... } ::ENBL

Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances

◆  [4/4]

__IO uint16_t { ... } ::ENBL

Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances

◆ ENDPTCOMPLETE

__IO uint32_t USB_Type::ENDPTCOMPLETE

Endpoint Complete, offset: 0x1BC

◆ ENDPTCTRL

__IO uint32_t USB_Type::ENDPTCTRL

Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4

◆ ENDPTCTRL0

__IO uint32_t USB_Type::ENDPTCTRL0

Endpoint Control0, offset: 0x1C0

◆ ENDPTFLUSH

__IO uint32_t USB_Type::ENDPTFLUSH

Endpoint Flush, offset: 0x1B4

◆ ENDPTLISTADDR [1/4]

__IO uint32_t USB_Type::ENDPTLISTADDR

Endpoint List Address, offset: 0x158

◆  [2/4]

__IO uint32_t { ... } ::ENDPTLISTADDR

Endpoint List Address, offset: 0x158

◆  [3/4]

__IO uint32_t { ... } ::ENDPTLISTADDR

Endpoint List Address, offset: 0x158

◆  [4/4]

__IO uint32_t { ... } ::ENDPTLISTADDR

Endpoint List Address, offset: 0x158

◆ ENDPTNAK

__IO uint32_t USB_Type::ENDPTNAK

Endpoint NAK, offset: 0x178

◆ ENDPTNAKEN

__IO uint32_t USB_Type::ENDPTNAKEN

Endpoint NAK Enable, offset: 0x17C

◆ ENDPTPRIME

__IO uint32_t USB_Type::ENDPTPRIME

Endpoint Prime, offset: 0x1B0

◆ ENDPTSETUPSTAT

__IO uint32_t USB_Type::ENDPTSETUPSTAT

Endpoint Setup Status, offset: 0x1AC

◆ ENDPTSTAT

__I uint32_t USB_Type::ENDPTSTAT

Endpoint Status, offset: 0x1B8

◆ ENT

__I uint32_t TRNG_Type::ENT[16]

Entropy Read Register, array offset: 0x40, array step: 0x4

◆ ERQ

__IO uint32_t DMA_Type::ERQ

Enable Request, offset: 0xC

◆ ERR

__IO uint32_t DMA_Type::ERR

Error, offset: 0x2C

◆ ERR_DATA_INJ

__IO uint32_t XECC_Type::ERR_DATA_INJ

Error Injection On Write Data, offset: 0x10

◆ ERR_DATA_INJ_HIGH0

__IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH0

Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data, offset: 0x10

◆ ERR_DATA_INJ_HIGH1

__IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH1

Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data, offset: 0x1C

◆ ERR_DATA_INJ_HIGH2

__IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH2

Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data, offset: 0x28

◆ ERR_DATA_INJ_HIGH3

__IO uint32_t MECC_Type::ERR_DATA_INJ_HIGH3

Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data, offset: 0x34

◆ ERR_DATA_INJ_LOW0

__IO uint32_t MECC_Type::ERR_DATA_INJ_LOW0

Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data, offset: 0xC

◆ ERR_DATA_INJ_LOW1

__IO uint32_t MECC_Type::ERR_DATA_INJ_LOW1

Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data, offset: 0x18

◆ ERR_DATA_INJ_LOW2

__IO uint32_t MECC_Type::ERR_DATA_INJ_LOW2

Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data, offset: 0x24

◆ ERR_DATA_INJ_LOW3

__IO uint32_t MECC_Type::ERR_DATA_INJ_LOW3

Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data, offset: 0x30

◆ ERR_ECC_INJ

__IO uint32_t XECC_Type::ERR_ECC_INJ

Error Injection On ECC Code of Write Data, offset: 0x14

◆ ERR_ECC_INJ0

__IO uint32_t MECC_Type::ERR_ECC_INJ0

Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data, offset: 0x14

◆ ERR_ECC_INJ1

__IO uint32_t MECC_Type::ERR_ECC_INJ1

Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data, offset: 0x20

◆ ERR_ECC_INJ2

__IO uint32_t MECC_Type::ERR_ECC_INJ2

Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data, offset: 0x2C

◆ ERR_ECC_INJ3

__IO uint32_t MECC_Type::ERR_ECC_INJ3

Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data, offset: 0x38

◆ ERR_SIG_EN [1/2]

__IO uint32_t MECC_Type::ERR_SIG_EN

Error Interrupt Enable Register, offset: 0x8

◆ ERR_SIG_EN [2/2]

__IO uint32_t XECC_Type::ERR_SIG_EN

Error Interrupt Enable Register, offset: 0xC

◆ ERR_STAT_EN [1/2]

__IO uint32_t MECC_Type::ERR_STAT_EN

Error Interrupt Status Enable Register, offset: 0x4

◆ ERR_STAT_EN [2/2]

__IO uint32_t XECC_Type::ERR_STAT_EN

Error Interrupt Status Enable Register, offset: 0x8

◆ ERR_STATUS [1/2]

__IO uint32_t MECC_Type::ERR_STATUS

Error Interrupt Status Register, offset: 0x0

◆ ERR_STATUS [2/2]

__IO uint32_t XECC_Type::ERR_STATUS

Error Interrupt Status Register, offset: 0x4

◆ ERRIAR

__IO uint32_t CAN_Type::ERRIAR

Error Injection Address register, offset: 0xAE4

◆ ERRIDPR

__IO uint32_t CAN_Type::ERRIDPR

Error Injection Data Pattern register, offset: 0xAE8

◆ ERRIPPR

__IO uint32_t CAN_Type::ERRIPPR

Error Injection Parity Pattern register, offset: 0xAEC

◆ ERRSR

__IO uint32_t CAN_Type::ERRSR

Error Status register, offset: 0xAFC

◆ ES

__I uint32_t DMA_Type::ES

Error Status, offset: 0x4

◆ ESR1

__IO uint32_t CAN_Type::ESR1

Error and Status 1 Register, offset: 0x20

Error and Status 1 register, offset: 0x20

◆ ESR2

__I uint32_t CAN_Type::ESR2

Error and Status 2 Register, offset: 0x38

Error and Status 2 register, offset: 0x38

◆ FADID

__I uint32_t CAAM_Type::FADID

Fault Address DID Register, offset: 0xFC8

◆ FADID_DC01

__I uint32_t CAAM_Type::FADID_DC01

Fault Address DID Register, offset: 0x80FC8

◆  [1/3]

__I uint32_t { ... } ::FADID_JR

Fault Address DID Register, array offset: 0x10FC8, array step: 0x10000

◆ FADID_JR [2/3]

__I uint32_t CAAM_Type::FADID_JR

Fault Address DID Register, array offset: 0x10FC8, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::FADID_JR

Fault Address DID Register, array offset: 0x10FC8, array step: 0x10000

◆ FADID_RTIC

__I uint32_t CAAM_Type::FADID_RTIC

Fault Address DID Register, offset: 0x60FC8

◆ FADR [1/2]

__I uint32_t CAAM_Type::FADR

Fault Address Detail Register, offset: 0xFCC

◆ FADR [2/2]

__I uint32_t MCM_Type::FADR

Fault address register, offset: 0x20

◆ FADR_DC01

__I uint32_t CAAM_Type::FADR_DC01

Fault Address Detail Register, offset: 0x80FCC

◆  [1/3]

__I uint32_t { ... } ::FADR_JR

Fault Address Detail Register, array offset: 0x10FCC, array step: 0x10000

◆ FADR_JR [2/3]

__I uint32_t CAAM_Type::FADR_JR

Fault Address Detail Register, array offset: 0x10FCC, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::FADR_JR

Fault Address Detail Register, array offset: 0x10FCC, array step: 0x10000

◆ FADR_RTIC

__I uint32_t CAAM_Type::FADR_RTIC

Fault Address Detail Register, offset: 0x60FCC

◆ FAR

__I uint64_t CAAM_Type::FAR

Fault Address Register, offset: 0xFC0

◆ FAR_DC01

__I uint64_t CAAM_Type::FAR_DC01

Fault Address Register, offset: 0x80FC0

◆  [1/3]

__I uint64_t { ... } ::FAR_JR

Fault Address Register, array offset: 0x10FC0, array step: 0x10000

◆ FAR_JR [2/3]

__I uint64_t CAAM_Type::FAR_JR

Fault Address Register, array offset: 0x10FC0, array step: 0x10000

◆  [3/3]

__I uint64_t { ... } ::FAR_JR

Fault Address Register, array offset: 0x10FC0, array step: 0x10000

◆ FAR_RTIC

__I uint64_t CAAM_Type::FAR_RTIC

Fault Address Register, offset: 0x60FC0

◆ FATR

__I uint32_t MCM_Type::FATR

Fault attributes register, offset: 0x24

◆ FBUF_PARA

__IO uint32_t CSI_Type::FBUF_PARA

CSI Frame Buffer Parameter Register, offset: 0x30

◆ FCR

__IO uint32_t LPSPI_Type::FCR

The FIFO Control register contains the RXWATER and TXWATER control fields., offset: 0x58

FIFO Control, offset: 0x58

◆ FCTRL [1/2]

__IO uint16_t PWM_Type::FCTRL

Fault Control Register, offset: 0x18C

◆ FCTRL [2/2]

__IO uint32_t ADC_Type::FCTRL

LPADC FIFO Control Register, offset: 0x30

◆ FCTRL2

__IO uint16_t PWM_Type::FCTRL2

Fault Control 2 Register, offset: 0x194

◆ FDCBT

__IO uint32_t CAN_Type::FDCBT

CAN FD Bit Timing register, offset: 0xC04

◆ FDCRC

__I uint32_t CAN_Type::FDCRC

CAN FD CRC register, offset: 0xC08

◆ FDCTRL

__IO uint32_t CAN_Type::FDCTRL

CAN FD Control register, offset: 0xC00

◆ FDR

__I uint32_t MCM_Type::FDR

Fault data register, offset: 0x28

◆ FFILT

__IO uint16_t PWM_Type::FFILT

Fault Filter Register, offset: 0x190

◆ FIFO

__IO uint32_t LPUART_Type::FIFO

LPUART FIFO Register, offset: 0x28

◆ FIFO_CTRL

__IO uint32_t PDM_Type::FIFO_CTRL

PDM FIFO Control register, offset: 0x10

◆ FIFO_STAT

__IO uint32_t PDM_Type::FIFO_STAT

PDM FIFO Status register, offset: 0x14

◆ FILT [1/5]

__IO uint16_t ENC_Type::FILT

Input Filter Register, offset: 0x2

◆  [2/5]

__IO uint16_t { ... } ::FILT

Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20

◆ FILT [3/5]

__IO uint16_t TMR_Type::FILT

Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20

◆  [4/5]

__IO uint16_t { ... } ::FILT

Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20

◆  [5/5]

__IO uint16_t { ... } ::FILT

Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20

◆ FLAGS

__IO uint32_t CDOG_Type::FLAGS

Flags, offset: 0x18

◆ FLEXRAM_CTRL

__IO uint32_t FLEXRAM_Type::FLEXRAM_CTRL

FlexRAM feature Control register, offset: 0x108

◆ FLOW_CONTROL

__IO uint32_t TSC_Type::FLOW_CONTROL

Flow Control, offset: 0x20

◆ FLSHCR0

__IO uint32_t FLEXSPI_Type::FLSHCR0

Flash Control Register 0, array offset: 0x60, array step: 0x4

◆ FLSHCR1

__IO uint32_t FLEXSPI_Type::FLSHCR1

Flash Control Register 1, array offset: 0x70, array step: 0x4

◆ FLSHCR2

__IO uint32_t FLEXSPI_Type::FLSHCR2

Flash Control Register 2, array offset: 0x80, array step: 0x4

◆ FLSHCR4

__IO uint32_t FLEXSPI_Type::FLSHCR4

Flash Control Register 4, offset: 0x94

◆ FORCE_EVENT

__O uint32_t USDHC_Type::FORCE_EVENT

Force Event, offset: 0x50

◆ FPR

__IO uint8_t CMP_Type::FPR

CMP Filter Period Register, offset: 0x2

◆  [1/4]

__IO uint16_t { ... } ::FRACVAL1

Fractional Value Register 1, array offset: 0xC, array step: 0x60

◆ FRACVAL1 [2/4]

__IO uint16_t PWM_Type::FRACVAL1

Fractional Value Register 1, array offset: 0xC, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::FRACVAL1

Fractional Value Register 1, array offset: 0xC, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::FRACVAL1

Fractional Value Register 1, array offset: 0xC, array step: 0x60

◆ FRACVAL2 [1/4]

__IO uint16_t PWM_Type::FRACVAL2

Fractional Value Register 2, array offset: 0x10, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::FRACVAL2

Fractional Value Register 2, array offset: 0x10, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::FRACVAL2

Fractional Value Register 2, array offset: 0x10, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::FRACVAL2

Fractional Value Register 2, array offset: 0x10, array step: 0x60

◆ FRACVAL3 [1/4]

__IO uint16_t PWM_Type::FRACVAL3

Fractional Value Register 3, array offset: 0x14, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::FRACVAL3

Fractional Value Register 3, array offset: 0x14, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::FRACVAL3

Fractional Value Register 3, array offset: 0x14, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::FRACVAL3

Fractional Value Register 3, array offset: 0x14, array step: 0x60

◆ FRACVAL4 [1/4]

__IO uint16_t PWM_Type::FRACVAL4

Fractional Value Register 4, array offset: 0x18, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::FRACVAL4

Fractional Value Register 4, array offset: 0x18, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::FRACVAL4

Fractional Value Register 4, array offset: 0x18, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::FRACVAL4

Fractional Value Register 4, array offset: 0x18, array step: 0x60

◆  [1/4]

__IO uint16_t { ... } ::FRACVAL5

Fractional Value Register 5, array offset: 0x1C, array step: 0x60

◆ FRACVAL5 [2/4]

__IO uint16_t PWM_Type::FRACVAL5

Fractional Value Register 5, array offset: 0x1C, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::FRACVAL5

Fractional Value Register 5, array offset: 0x1C, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::FRACVAL5

Fractional Value Register 5, array offset: 0x1C, array step: 0x60

◆  [1/4]

__IO uint16_t { ... } ::FRCTRL

Fractional Control Register, array offset: 0x20, array step: 0x60

◆ FRCTRL [2/4]

__IO uint16_t PWM_Type::FRCTRL

Fractional Control Register, array offset: 0x20, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::FRCTRL

Fractional Control Register, array offset: 0x20, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::FRCTRL

Fractional Control Register, array offset: 0x20, array step: 0x60

◆ FREQUENCY_CURRENT [1/3]

__I uint32_t CCM_OBS_Type::FREQUENCY_CURRENT

Current frequency detected, array offset: 0x40, array step: 0x80

◆  [2/3]

__I uint32_t { ... } ::FREQUENCY_CURRENT

Current frequency detected, array offset: 0x40, array step: 0x80

◆  [3/3]

__I uint32_t { ... } ::FREQUENCY_CURRENT

Current frequency detected, array offset: 0x40, array step: 0x80

◆  [1/3]

__I uint32_t { ... } ::FREQUENCY_MAX

Maximum frequency detected, array offset: 0x48, array step: 0x80

◆ FREQUENCY_MAX [2/3]

__I uint32_t CCM_OBS_Type::FREQUENCY_MAX

Maximum frequency detected, array offset: 0x48, array step: 0x80

◆  [3/3]

__I uint32_t { ... } ::FREQUENCY_MAX

Maximum frequency detected, array offset: 0x48, array step: 0x80

◆  [1/3]

__I uint32_t { ... } ::FREQUENCY_MIN

Minimum frequency detected, array offset: 0x44, array step: 0x80

◆ FREQUENCY_MIN [2/3]

__I uint32_t CCM_OBS_Type::FREQUENCY_MIN

Minimum frequency detected, array offset: 0x44, array step: 0x80

◆  [3/3]

__I uint32_t { ... } ::FREQUENCY_MIN

Minimum frequency detected, array offset: 0x44, array step: 0x80

◆ FRINDEX

__IO uint32_t USB_Type::FRINDEX

USB Frame Index, offset: 0x14C

◆ FRQCNT [1/2]

__I uint32_t TRNG_Type::FRQCNT

Frequency Count Register, offset: 0x1C

◆  [2/2]

__I uint32_t { ... } ::FRQCNT

Frequency Count Register, offset: 0x1C

◆ FRQMAX [1/2]

__IO uint32_t TRNG_Type::FRQMAX

Frequency Count Maximum Limit Register, offset: 0x1C

◆  [2/2]

__IO uint32_t { ... } ::FRQMAX

Frequency Count Maximum Limit Register, offset: 0x1C

◆ FRQMIN

__IO uint32_t TRNG_Type::FRQMIN

Frequency Count Minimum Limit Register, offset: 0x18

◆ FSR

__I uint32_t LPSPI_Type::FSR

FIFO Status Register, offset: 0x5C

FIFO Status, offset: 0x5C

◆ FSTS

__IO uint16_t PWM_Type::FSTS

Fault Status Register, offset: 0x18E

◆ FTRL

__IO uint32_t ENET_Type::FTRL

Frame Truncation Length, offset: 0x1B0

◆ FTST

__IO uint16_t PWM_Type::FTST

Fault Test Register, offset: 0x192

◆  [1/3]

__I uint32_t { ... } ::FUSE

Value of fuse word 0..Value of fuse word 143, array offset: 0x800, array step: 0x10

◆ FUSE [2/3]

__I uint32_t OCOTP_Type::FUSE

Value of fuse word 0..Value of fuse word 143, array offset: 0x800, array step: 0x10

◆  [3/3]

__I uint32_t { ... } ::FUSE

Value of fuse word 0..Value of fuse word 143, array offset: 0x800, array step: 0x10

◆ GALR

__IO uint32_t ENET_Type::GALR

Descriptor Group Lower Address Register, offset: 0x124

◆ GATE [1/2]

__IO uint8_t SEMA4_Type::GATE

Semaphores Gate n Register, array offset: 0x0, array step: 0x1

◆ GATE [2/2]

__IO uint8_t RDC_SEMAPHORE_Type::GATE

Gate Register, array offset: 0x0, array step: 0x1

◆ GAUR

__IO uint32_t ENET_Type::GAUR

Descriptor Group Upper Address Register, offset: 0x120

◆ GC

__IO uint32_t ADC_Type::GC

General control register, offset: 0x48

◆ GCFG

__IO uint32_t IEE_Type::GCFG

IEE Global Configuration, offset: 0x0

◆ GDIR

__IO uint32_t GPIO_Type::GDIR

GPIO direction register, offset: 0x4

◆ GFWR [1/2]

__IO uint32_t CAN_Type::GFWR

Glitch Filter Width Registers, offset: 0x9E0

◆ GFWR [2/2]

__IO uint32_t CAN_WRAPPER_Type::GFWR

Glitch Filter Width Register, offset: 0x9E0

◆ GLOBAL

__IO uint32_t LPUART_Type::GLOBAL

LPUART Global Register, offset: 0x8

◆ GP1

__IO uint32_t OCOTP_Type::GP1

Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660

◆ GP2

__IO uint32_t OCOTP_Type::GP2

Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670

◆ GP3

__IO uint32_t OCOTP_Type::GP3

Value of OTP Bank4 Word4 (MAC Address), offset: 0x640

◆ GPCNT0_VAL

__IO uint32_t EMVSIM_Type::GPCNT0_VAL

General Purpose Counter 0 Timeout Value Register, offset: 0x44

◆ GPCNT1_VAL

__IO uint32_t EMVSIM_Type::GPCNT1_VAL

General Purpose Counter 1 Timeout Value, offset: 0x48

◆ GPR [1/2]

__IO uint32_t SRC_Type::GPR

SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4

SRC General Purpose Register, array offset: 0x14, array step: 0x4

◆ GPR [2/2]

__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR

GPR0 General Purpose Register, array offset: 0x0, array step: 0x4

◆ GPR0 [1/4]

__IO uint32_t IOMUXC_GPR_Type::GPR0

GPR0 General Purpose Register, offset: 0x0

◆ GPR0 [2/4]

uint32_t IOMUXC_SNVS_GPR_Type::GPR0

GPR0 General Purpose Register, offset: 0x0

◆ GPR0 [3/4]

__IO uint32_t IOMUXC_GPR_Type::GPR0

GPR0 General Purpose Register, offset: 0x0

◆ GPR0 [4/4]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR0

GPR0 General Purpose Register, offset: 0x0

◆ GPR1 [1/3]

__IO uint32_t IOMUXC_GPR_Type::GPR1

GPR1 General Purpose Register, offset: 0x4

◆ GPR1 [2/3]

uint32_t IOMUXC_SNVS_GPR_Type::GPR1

GPR1 General Purpose Register, offset: 0x4

◆ GPR1 [3/3]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR1

GPR1 General Purpose Register, offset: 0x4

◆ GPR10 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR10

GPR10 General Purpose Register, offset: 0x28

◆ GPR10 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR10

GPR10 General Purpose Register, offset: 0x28

◆ GPR11 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR11

GPR11 General Purpose Register, offset: 0x2C

◆ GPR11 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR11

GPR11 General Purpose Register, offset: 0x2C

◆ GPR12 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR12

GPR12 General Purpose Register, offset: 0x30

◆ GPR12 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR12

GPR12 General Purpose Register, offset: 0x30

◆ GPR13 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR13

GPR13 General Purpose Register, offset: 0x34

◆ GPR13 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR13

GPR13 General Purpose Register, offset: 0x34

◆ GPR14 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR14

GPR14 General Purpose Register, offset: 0x38

◆ GPR14 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR14

GPR14 General Purpose Register, offset: 0x38

◆ GPR15 [1/3]

__IO uint32_t IOMUXC_GPR_Type::GPR15

GPR15 General Purpose Register, offset: 0x3C

◆ GPR15 [2/3]

__IO uint32_t IOMUXC_GPR_Type::GPR15

GPR15 General Purpose Register, offset: 0x3C

◆ GPR15 [3/3]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR15

GPR15 General Purpose Register, offset: 0x3C

◆ GPR16 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR16

GPR16 General Purpose Register, offset: 0x40

◆ GPR16 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR16

GPR16 General Purpose Register, offset: 0x40

◆ GPR17 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR17

GPR17 General Purpose Register, offset: 0x44

◆ GPR17 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR17

GPR17 General Purpose Register, offset: 0x44

◆ GPR18 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR18

GPR18 General Purpose Register, offset: 0x48

◆ GPR18 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR18

GPR18 General Purpose Register, offset: 0x48

◆ GPR19 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR19

GPR19 General Purpose Register, offset: 0x4C

◆ GPR19 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR19

GPR19 General Purpose Register, offset: 0x4C

◆ GPR2 [1/3]

__IO uint32_t IOMUXC_GPR_Type::GPR2

GPR2 General Purpose Register, offset: 0x8

◆ GPR2 [2/3]

uint32_t IOMUXC_SNVS_GPR_Type::GPR2

GPR2 General Purpose Register, offset: 0x8

◆ GPR2 [3/3]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR2

GPR2 General Purpose Register, offset: 0x8

◆ GPR20 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR20

GPR20 General Purpose Register, offset: 0x50

◆ GPR20 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR20

GPR20 General Purpose Register, offset: 0x50

◆ GPR21 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR21

GPR21 General Purpose Register, offset: 0x54

◆ GPR21 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR21

GPR21 General Purpose Register, offset: 0x54

◆ GPR22 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR22

GPR22 General Purpose Register, offset: 0x58

◆ GPR22 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR22

GPR22 General Purpose Register, offset: 0x58

◆ GPR23 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR23

GPR23 General Purpose Register, offset: 0x5C

◆ GPR23 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR23

GPR23 General Purpose Register, offset: 0x5C

◆ GPR24 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR24

GPR24 General Purpose Register, offset: 0x60

◆ GPR24 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR24

GPR24 General Purpose Register, offset: 0x60

◆ GPR25 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR25

GPR25 General Purpose Register, offset: 0x64

◆ GPR25 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR25

GPR25 General Purpose Register, offset: 0x64

◆ GPR26 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR26

GPR26 General Purpose Register, offset: 0x68

◆ GPR26 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR26

GPR26 General Purpose Register, offset: 0x68

◆ GPR27

__IO uint32_t IOMUXC_GPR_Type::GPR27

GPR27 General Purpose Register, offset: 0x6C

◆ GPR28

__IO uint32_t IOMUXC_GPR_Type::GPR28

GPR28 General Purpose Register, offset: 0x70

◆ GPR29

__IO uint32_t IOMUXC_GPR_Type::GPR29

GPR29 General Purpose Register, offset: 0x74

◆ GPR3 [1/3]

__IO uint32_t IOMUXC_GPR_Type::GPR3

GPR3 General Purpose Register, offset: 0xC

◆ GPR3 [2/3]

__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR3

GPR3 General Purpose Register, offset: 0xC

◆ GPR3 [3/3]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR3

GPR3 General Purpose Register, offset: 0xC

◆ GPR30

__IO uint32_t IOMUXC_GPR_Type::GPR30

GPR30 General Purpose Register, offset: 0x78

◆ GPR31

__IO uint32_t IOMUXC_GPR_Type::GPR31

GPR31 General Purpose Register, offset: 0x7C

◆ GPR32 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR32

GPR32 General Purpose Register, offset: 0x80

◆ GPR32 [2/2]

__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR32

GPR32 General Purpose Register, offset: 0x80

◆ GPR33 [1/3]

__IO uint32_t IOMUXC_GPR_Type::GPR33

GPR33 General Purpose Register, offset: 0x84

◆ GPR33 [2/3]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR33

GPR33 General Purpose Register, offset: 0x84

◆ GPR33 [3/3]

__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR33

GPR33 General Purpose Register, offset: 0x84

◆ GPR34 [1/3]

__IO uint32_t IOMUXC_GPR_Type::GPR34

GPR34 General Purpose Register, offset: 0x88

◆ GPR34 [2/3]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR34

GPR34 General Purpose Register, offset: 0x88

◆ GPR34 [3/3]

__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR34

GPR34 General Purpose Register, offset: 0x88

◆ GPR35 [1/3]

__IO uint32_t IOMUXC_GPR_Type::GPR35

GPR35 General Purpose Register, offset: 0x8C

◆ GPR35 [2/3]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR35

GPR35 General Purpose Register, offset: 0x8C

◆ GPR35 [3/3]

__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR35

GPR35 General Purpose Register, offset: 0x8C

◆ GPR36 [1/3]

__IO uint32_t IOMUXC_GPR_Type::GPR36

GPR36 General Purpose Register, offset: 0x90

◆ GPR36 [2/3]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR36

GPR36 General Purpose Register, offset: 0x90

◆ GPR36 [3/3]

__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR36

GPR36 General Purpose Register, offset: 0x90

◆ GPR37 [1/3]

__IO uint32_t IOMUXC_GPR_Type::GPR37

GPR37 General Purpose Register, offset: 0x94

◆ GPR37 [2/3]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR37

GPR37 General Purpose Register, offset: 0x94

◆ GPR37 [3/3]

__IO uint32_t IOMUXC_SNVS_GPR_Type::GPR37

GPR37 General Purpose Register, offset: 0x94

◆ GPR38 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR38

GPR38 General Purpose Register, offset: 0x98

◆ GPR38 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR38

GPR38 General Purpose Register, offset: 0x98

◆ GPR39 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR39

GPR39 General Purpose Register, offset: 0x9C

◆ GPR39 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR39

GPR39 General Purpose Register, offset: 0x9C

◆ GPR4 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR4

GPR4 General Purpose Register, offset: 0x10

◆ GPR4 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR4

GPR4 General Purpose Register, offset: 0x10

◆ GPR40 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR40

GPR40 General Purpose Register, offset: 0xA0

◆ GPR40 [2/2]

__I uint32_t IOMUXC_LPSR_GPR_Type::GPR40

GPR40 General Purpose Register, offset: 0xA0

◆ GPR41 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR41

GPR41 General Purpose Register, offset: 0xA4

◆ GPR41 [2/2]

__I uint32_t IOMUXC_LPSR_GPR_Type::GPR41

GPR41 General Purpose Register, offset: 0xA4

◆ GPR42

__IO uint32_t IOMUXC_GPR_Type::GPR42

GPR42 General Purpose Register, offset: 0xA8

◆ GPR43

__IO uint32_t IOMUXC_GPR_Type::GPR43

GPR43 General Purpose Register, offset: 0xAC

◆ GPR44

__IO uint32_t IOMUXC_GPR_Type::GPR44

GPR44 General Purpose Register, offset: 0xB0

◆ GPR45

__IO uint32_t IOMUXC_GPR_Type::GPR45

GPR45 General Purpose Register, offset: 0xB4

◆ GPR46

__IO uint32_t IOMUXC_GPR_Type::GPR46

GPR46 General Purpose Register, offset: 0xB8

◆ GPR47

__IO uint32_t IOMUXC_GPR_Type::GPR47

GPR47 General Purpose Register, offset: 0xBC

◆ GPR48

__IO uint32_t IOMUXC_GPR_Type::GPR48

GPR48 General Purpose Register, offset: 0xC0

◆ GPR49

__IO uint32_t IOMUXC_GPR_Type::GPR49

GPR49 General Purpose Register, offset: 0xC4

◆ GPR5 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR5

GPR5 General Purpose Register, offset: 0x14

◆ GPR5 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR5

GPR5 General Purpose Register, offset: 0x14

◆ GPR50

__IO uint32_t IOMUXC_GPR_Type::GPR50

GPR50 General Purpose Register, offset: 0xC8

◆ GPR51

__IO uint32_t IOMUXC_GPR_Type::GPR51

GPR51 General Purpose Register, offset: 0xCC

◆ GPR52

__IO uint32_t IOMUXC_GPR_Type::GPR52

GPR52 General Purpose Register, offset: 0xD0

◆ GPR53

__IO uint32_t IOMUXC_GPR_Type::GPR53

GPR53 General Purpose Register, offset: 0xD4

◆ GPR54

__IO uint32_t IOMUXC_GPR_Type::GPR54

GPR54 General Purpose Register, offset: 0xD8

◆ GPR55

__IO uint32_t IOMUXC_GPR_Type::GPR55

GPR55 General Purpose Register, offset: 0xDC

◆ GPR59

__IO uint32_t IOMUXC_GPR_Type::GPR59

GPR59 General Purpose Register, offset: 0xEC

◆ GPR6 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR6

GPR6 General Purpose Register, offset: 0x18

◆ GPR6 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR6

GPR6 General Purpose Register, offset: 0x18

◆ GPR62

__IO uint32_t IOMUXC_GPR_Type::GPR62

GPR62 General Purpose Register, offset: 0xF8

◆ GPR63

__I uint32_t IOMUXC_GPR_Type::GPR63

GPR63 General Purpose Register, offset: 0xFC

◆ GPR64

__IO uint32_t IOMUXC_GPR_Type::GPR64

GPR64 General Purpose Register, offset: 0x100

◆ GPR65

__IO uint32_t IOMUXC_GPR_Type::GPR65

GPR65 General Purpose Register, offset: 0x104

◆ GPR66

__IO uint32_t IOMUXC_GPR_Type::GPR66

GPR66 General Purpose Register, offset: 0x108

◆ GPR67

__IO uint32_t IOMUXC_GPR_Type::GPR67

GPR67 General Purpose Register, offset: 0x10C

◆ GPR68

__IO uint32_t IOMUXC_GPR_Type::GPR68

GPR68 General Purpose Register, offset: 0x110

◆ GPR69

__IO uint32_t IOMUXC_GPR_Type::GPR69

GPR69 General Purpose Register, offset: 0x114

◆ GPR7 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR7

GPR7 General Purpose Register, offset: 0x1C

◆ GPR7 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR7

GPR7 General Purpose Register, offset: 0x1C

◆ GPR70

__IO uint32_t IOMUXC_GPR_Type::GPR70

GPR70 General Purpose Register, offset: 0x118

◆ GPR71

__IO uint32_t IOMUXC_GPR_Type::GPR71

GPR71 General Purpose Register, offset: 0x11C

◆ GPR72

__IO uint32_t IOMUXC_GPR_Type::GPR72

GPR72 General Purpose Register, offset: 0x120

◆ GPR73

__IO uint32_t IOMUXC_GPR_Type::GPR73

GPR73 General Purpose Register, offset: 0x124

◆ GPR74

__IO uint32_t IOMUXC_GPR_Type::GPR74

GPR74 General Purpose Register, offset: 0x128

◆ GPR75

__I uint32_t IOMUXC_GPR_Type::GPR75

GPR75 General Purpose Register, offset: 0x12C

◆ GPR76

__I uint32_t IOMUXC_GPR_Type::GPR76

GPR76 General Purpose Register, offset: 0x130

◆ GPR8 [1/2]

__IO uint32_t IOMUXC_GPR_Type::GPR8

GPR8 General Purpose Register, offset: 0x20

◆ GPR8 [2/2]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR8

GPR8 General Purpose Register, offset: 0x20

◆ GPR9 [1/3]

__IO uint32_t IOMUXC_GPR_Type::GPR9

GPR9 General Purpose Register, offset: 0x24

◆ GPR9 [2/3]

__IO uint32_t IOMUXC_GPR_Type::GPR9

GPR9 General Purpose Register, offset: 0x24

◆ GPR9 [3/3]

__IO uint32_t IOMUXC_LPSR_GPR_Type::GPR9

GPR9 General Purpose Register, offset: 0x24

◆ GPR_PRIVATE1

__IO uint32_t CCM_Type::GPR_PRIVATE1

General Purpose Register, offset: 0x4C20

◆ GPR_PRIVATE1_AUTHEN

__IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN

GPR access control, offset: 0x4C30

◆ GPR_PRIVATE1_AUTHEN_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN_CLR

GPR access control, offset: 0x4C38

◆ GPR_PRIVATE1_AUTHEN_SET

__IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN_SET

GPR access control, offset: 0x4C34

◆ GPR_PRIVATE1_AUTHEN_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE1_AUTHEN_TOG

GPR access control, offset: 0x4C3C

◆ GPR_PRIVATE1_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE1_CLR

General Purpose Register, offset: 0x4C28

◆ GPR_PRIVATE1_SET

__IO uint32_t CCM_Type::GPR_PRIVATE1_SET

General Purpose Register, offset: 0x4C24

◆ GPR_PRIVATE1_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE1_TOG

General Purpose Register, offset: 0x4C2C

◆ GPR_PRIVATE2

__IO uint32_t CCM_Type::GPR_PRIVATE2

General Purpose Register, offset: 0x4C40

◆ GPR_PRIVATE2_AUTHEN

__IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN

GPR access control, offset: 0x4C50

◆ GPR_PRIVATE2_AUTHEN_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN_CLR

GPR access control, offset: 0x4C58

◆ GPR_PRIVATE2_AUTHEN_SET

__IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN_SET

GPR access control, offset: 0x4C54

◆ GPR_PRIVATE2_AUTHEN_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE2_AUTHEN_TOG

GPR access control, offset: 0x4C5C

◆ GPR_PRIVATE2_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE2_CLR

General Purpose Register, offset: 0x4C48

◆ GPR_PRIVATE2_SET

__IO uint32_t CCM_Type::GPR_PRIVATE2_SET

General Purpose Register, offset: 0x4C44

◆ GPR_PRIVATE2_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE2_TOG

General Purpose Register, offset: 0x4C4C

◆ GPR_PRIVATE3

__IO uint32_t CCM_Type::GPR_PRIVATE3

General Purpose Register, offset: 0x4C60

◆ GPR_PRIVATE3_AUTHEN

__IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN

GPR access control, offset: 0x4C70

◆ GPR_PRIVATE3_AUTHEN_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN_CLR

GPR access control, offset: 0x4C78

◆ GPR_PRIVATE3_AUTHEN_SET

__IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN_SET

GPR access control, offset: 0x4C74

◆ GPR_PRIVATE3_AUTHEN_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE3_AUTHEN_TOG

GPR access control, offset: 0x4C7C

◆ GPR_PRIVATE3_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE3_CLR

General Purpose Register, offset: 0x4C68

◆ GPR_PRIVATE3_SET

__IO uint32_t CCM_Type::GPR_PRIVATE3_SET

General Purpose Register, offset: 0x4C64

◆ GPR_PRIVATE3_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE3_TOG

General Purpose Register, offset: 0x4C6C

◆ GPR_PRIVATE4

__IO uint32_t CCM_Type::GPR_PRIVATE4

General Purpose Register, offset: 0x4C80

◆ GPR_PRIVATE4_AUTHEN

__IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN

GPR access control, offset: 0x4C90

◆ GPR_PRIVATE4_AUTHEN_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN_CLR

GPR access control, offset: 0x4C98

◆ GPR_PRIVATE4_AUTHEN_SET

__IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN_SET

GPR access control, offset: 0x4C94

◆ GPR_PRIVATE4_AUTHEN_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE4_AUTHEN_TOG

GPR access control, offset: 0x4C9C

◆ GPR_PRIVATE4_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE4_CLR

General Purpose Register, offset: 0x4C88

◆ GPR_PRIVATE4_SET

__IO uint32_t CCM_Type::GPR_PRIVATE4_SET

General Purpose Register, offset: 0x4C84

◆ GPR_PRIVATE4_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE4_TOG

General Purpose Register, offset: 0x4C8C

◆ GPR_PRIVATE5

__IO uint32_t CCM_Type::GPR_PRIVATE5

General Purpose Register, offset: 0x4CA0

◆ GPR_PRIVATE5_AUTHEN

__IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN

GPR access control, offset: 0x4CB0

◆ GPR_PRIVATE5_AUTHEN_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN_CLR

GPR access control, offset: 0x4CB8

◆ GPR_PRIVATE5_AUTHEN_SET

__IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN_SET

GPR access control, offset: 0x4CB4

◆ GPR_PRIVATE5_AUTHEN_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE5_AUTHEN_TOG

GPR access control, offset: 0x4CBC

◆ GPR_PRIVATE5_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE5_CLR

General Purpose Register, offset: 0x4CA8

◆ GPR_PRIVATE5_SET

__IO uint32_t CCM_Type::GPR_PRIVATE5_SET

General Purpose Register, offset: 0x4CA4

◆ GPR_PRIVATE5_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE5_TOG

General Purpose Register, offset: 0x4CAC

◆ GPR_PRIVATE6

__IO uint32_t CCM_Type::GPR_PRIVATE6

General Purpose Register, offset: 0x4CC0

◆ GPR_PRIVATE6_AUTHEN

__IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN

GPR access control, offset: 0x4CD0

◆ GPR_PRIVATE6_AUTHEN_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN_CLR

GPR access control, offset: 0x4CD8

◆ GPR_PRIVATE6_AUTHEN_SET

__IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN_SET

GPR access control, offset: 0x4CD4

◆ GPR_PRIVATE6_AUTHEN_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE6_AUTHEN_TOG

GPR access control, offset: 0x4CDC

◆ GPR_PRIVATE6_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE6_CLR

General Purpose Register, offset: 0x4CC8

◆ GPR_PRIVATE6_SET

__IO uint32_t CCM_Type::GPR_PRIVATE6_SET

General Purpose Register, offset: 0x4CC4

◆ GPR_PRIVATE6_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE6_TOG

General Purpose Register, offset: 0x4CCC

◆ GPR_PRIVATE7

__IO uint32_t CCM_Type::GPR_PRIVATE7

General Purpose Register, offset: 0x4CE0

◆ GPR_PRIVATE7_AUTHEN

__IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN

GPR access control, offset: 0x4CF0

◆ GPR_PRIVATE7_AUTHEN_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN_CLR

GPR access control, offset: 0x4CF8

◆ GPR_PRIVATE7_AUTHEN_SET

__IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN_SET

GPR access control, offset: 0x4CF4

◆ GPR_PRIVATE7_AUTHEN_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE7_AUTHEN_TOG

GPR access control, offset: 0x4CFC

◆ GPR_PRIVATE7_CLR

__IO uint32_t CCM_Type::GPR_PRIVATE7_CLR

General Purpose Register, offset: 0x4CE8

◆ GPR_PRIVATE7_SET

__IO uint32_t CCM_Type::GPR_PRIVATE7_SET

General Purpose Register, offset: 0x4CE4

◆ GPR_PRIVATE7_TOG

__IO uint32_t CCM_Type::GPR_PRIVATE7_TOG

General Purpose Register, offset: 0x4CEC

◆ GPR_SHARED [1/3]

__IO uint32_t CCM_Type::GPR_SHARED

General Purpose Register, array offset: 0x4800, array step: 0x20

◆  [2/3]

__IO uint32_t { ... } ::GPR_SHARED

General Purpose Register, array offset: 0x4800, array step: 0x20

◆  [3/3]

__IO uint32_t { ... } ::GPR_SHARED

General Purpose Register, array offset: 0x4800, array step: 0x20

◆ GPTIMER0CTRL

__IO uint32_t USB_Type::GPTIMER0CTRL

General Purpose Timer #0 Controller, offset: 0x84

◆ GPTIMER0LD

__IO uint32_t USB_Type::GPTIMER0LD

General Purpose Timer #0 Load, offset: 0x80

◆ GPTIMER1CTRL

__IO uint32_t USB_Type::GPTIMER1CTRL

General Purpose Timer #1 Controller, offset: 0x8C

◆ GPTIMER1LD

__IO uint32_t USB_Type::GPTIMER1LD

General Purpose Timer #1 Load, offset: 0x88

◆ GS

__IO uint32_t ADC_Type::GS

General status register, offset: 0x4C

◆ HADDREND

__IO uint32_t FLEXSPI_Type::HADDREND

HADDR REMAP END ADDR, offset: 0x424

◆ HADDROFFSET

__IO uint32_t FLEXSPI_Type::HADDROFFSET

HADDR REMAP OFFSET, offset: 0x428

◆ HADDRSTART

__IO uint32_t FLEXSPI_Type::HADDRSTART

HADDR REMAP START ADDR, offset: 0x420

◆ HBP

__IO uint32_t DSI_HOST_DPI_INTFC_Type::HBP

HBP, offset: 0x20

◆ HC

__IO uint32_t ADC_Type::HC[8]

Control register for hardware triggers, array offset: 0x0, array step: 0x4

◆ HCCPARAMS

__I uint32_t USB_Type::HCCPARAMS

Host Controller Capability Parameters, offset: 0x108

◆ HCIVERSION

__I uint16_t USB_Type::HCIVERSION

Host Controller Interface Version, offset: 0x102

◆ HCSPARAMS

__I uint32_t USB_Type::HCSPARAMS

Host Controller Structural Parameters, offset: 0x104

◆ HFP

__IO uint32_t DSI_HOST_DPI_INTFC_Type::HFP

HFP, offset: 0x1C

◆ HMSTRCR

__IO uint32_t FLEXSPI_Type::HMSTRCR

AHB Master ID 0 Control Register..AHB Master ID 7 Control Register, array offset: 0x400, array step: 0x4

◆  [1/4]

__IO uint16_t { ... } ::HOLD

Timer Channel Hold Register, array offset: 0x8, array step: 0x20

◆ HOLD [2/4]

__IO uint16_t TMR_Type::HOLD

Timer Channel Hold Register, array offset: 0x8, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::HOLD

Timer Channel Hold Register, array offset: 0x8, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::HOLD

Timer Channel Hold Register, array offset: 0x8, array step: 0x20

◆ HOST_CTRL_CAP

__IO uint32_t USDHC_Type::HOST_CTRL_CAP

Host Controller Capabilities, offset: 0x40

◆ HP0

__IO uint32_t CSU_Type::HP0

HP0 register, offset: 0x200

◆ HP_TIMEOUT

__IO uint32_t SSARC_LP_Type::HP_TIMEOUT

HP Timeout Register, offset: 0x20C

◆ HPCOMR

__IO uint32_t SNVS_Type::HPCOMR

SNVS_HP Command Register, offset: 0x4

◆ HPCONTROL0

__IO uint32_t CSU_Type::HPCONTROL0

HPCONTROL0 register, offset: 0x358

◆ HPCR

__IO uint32_t SNVS_Type::HPCR

SNVS_HP Control Register, offset: 0x8

◆ HPHACIVR

__IO uint32_t SNVS_Type::HPHACIVR

SNVS_HP High Assurance Counter IV Register, offset: 0x1C

◆ HPHACR

__I uint32_t SNVS_Type::HPHACR

SNVS_HP High Assurance Counter Register, offset: 0x20

◆ HPLR

__IO uint32_t SNVS_Type::HPLR

SNVS_HP Lock Register, offset: 0x0

◆ HPRTCLR

__IO uint32_t SNVS_Type::HPRTCLR

SNVS_HP Real Time Counter LSB Register, offset: 0x28

◆ HPRTCMR

__IO uint32_t SNVS_Type::HPRTCMR

SNVS_HP Real Time Counter MSB Register, offset: 0x24

◆ HPSICR

__IO uint32_t SNVS_Type::HPSICR

SNVS_HP Security Interrupt Control Register, offset: 0xC

◆ HPSR

__IO uint32_t SNVS_Type::HPSR

SNVS_HP Status Register, offset: 0x14

◆ HPSVCR

__IO uint32_t SNVS_Type::HPSVCR

SNVS_HP Security Violation Control Register, offset: 0x10

◆ HPSVSR

__IO uint32_t SNVS_Type::HPSVSR

SNVS_HP Security Violation Status Register, offset: 0x18

◆ HPTALR

__IO uint32_t SNVS_Type::HPTALR

SNVS_HP Time Alarm LSB Register, offset: 0x30

◆ HPTAMR

__IO uint32_t SNVS_Type::HPTAMR

SNVS_HP Time Alarm MSB Register, offset: 0x2C

◆ HPVIDR1

__I uint32_t SNVS_Type::HPVIDR1

SNVS_HP Version ID Register 1, offset: 0xBF8

◆ HPVIDR2

__I uint32_t SNVS_Type::HPVIDR2

SNVS_HP Version ID Register 2, offset: 0xBFC

◆ HRS

__I uint32_t DMA_Type::HRS

Hardware Request Status, offset: 0x34

◆ HS

__I uint32_t ADC_Type::HS

Status register for HW triggers, offset: 0x20

◆ HSA

__IO uint32_t DSI_HOST_DPI_INTFC_Type::HSA

HSA, offset: 0x24

◆ HSIC_CTRL

__IO uint32_t USBNC_Type::HSIC_CTRL

USB Host HSIC Control Register, offset: 0x10

◆ HSYN_PARA

__IO uint32_t LCDIFV2_Type::HSYN_PARA

Horizontal Sync Parameter Register, offset: 0x18

◆ HSYNC_POLARITY

__IO uint32_t DSI_HOST_DPI_INTFC_Type::HSYNC_POLARITY

HSYNC_POLARITY, offset: 0x14

◆ HT_JD_ADDR [1/3]

__I uint64_t CAAM_Type::HT_JD_ADDR

Holding Tank 0 Job Descriptor Address, array offset: 0xC00, array step: 0x20

◆  [2/3]

__I uint64_t { ... } ::HT_JD_ADDR

Holding Tank 0 Job Descriptor Address, array offset: 0xC00, array step: 0x20

◆  [3/3]

__I uint64_t { ... } ::HT_JD_ADDR

Holding Tank 0 Job Descriptor Address, array offset: 0xC00, array step: 0x20

◆ HT_JQ_CTRL_LS [1/3]

__I uint32_t CAAM_Type::HT_JQ_CTRL_LS

Holding Tank 0 Job Queue Control, least-significant half, array offset: 0xC14, array step: 0x20

◆  [2/3]

__I uint32_t { ... } ::HT_JQ_CTRL_LS

Holding Tank 0 Job Queue Control, least-significant half, array offset: 0xC14, array step: 0x20

◆  [3/3]

__I uint32_t { ... } ::HT_JQ_CTRL_LS

Holding Tank 0 Job Queue Control, least-significant half, array offset: 0xC14, array step: 0x20

◆ HT_JQ_CTRL_MS [1/3]

__I uint32_t CAAM_Type::HT_JQ_CTRL_MS

Holding Tank 0 Job Queue Control, most-significant half, array offset: 0xC10, array step: 0x20

◆  [2/3]

__I uint32_t { ... } ::HT_JQ_CTRL_MS

Holding Tank 0 Job Queue Control, most-significant half, array offset: 0xC10, array step: 0x20

◆  [3/3]

__I uint32_t { ... } ::HT_JQ_CTRL_MS

Holding Tank 0 Job Queue Control, most-significant half, array offset: 0xC10, array step: 0x20

◆ HT_SD_ADDR [1/3]

__I uint64_t CAAM_Type::HT_SD_ADDR

Holding Tank 0 Shared Descriptor Address, array offset: 0xC08, array step: 0x20

◆  [2/3]

__I uint64_t { ... } ::HT_SD_ADDR

Holding Tank 0 Shared Descriptor Address, array offset: 0xC08, array step: 0x20

◆  [3/3]

__I uint64_t { ... } ::HT_SD_ADDR

Holding Tank 0 Shared Descriptor Address, array offset: 0xC08, array step: 0x20

◆ HT_STATUS [1/3]

__I uint32_t CAAM_Type::HT_STATUS

Holding Tank Status, array offset: 0xC1C, array step: 0x20

◆  [2/3]

__I uint32_t { ... } ::HT_STATUS

Holding Tank Status, array offset: 0xC1C, array step: 0x20

◆  [3/3]

__I uint32_t { ... } ::HT_STATUS

Holding Tank Status, array offset: 0xC1C, array step: 0x20

◆ HW_GROUP_PENDING

__I uint32_t SSARC_LP_Type::HW_GROUP_PENDING

Hardware Request Pending Register, offset: 0x21C

◆ HWDEVICE

__I uint32_t USB_Type::HWDEVICE

Device Hardware Parameters, offset: 0xC

◆ HWGENERAL

__I uint32_t USB_Type::HWGENERAL

Hardware General, offset: 0x4

◆ HWHOST

__I uint32_t USB_Type::HWHOST

Host Hardware Parameters, offset: 0x8

◆ HWRXBUF

__I uint32_t USB_Type::HWRXBUF

RX Buffer Hardware Parameters, offset: 0x14

◆ HWTXBUF

__I uint32_t USB_Type::HWTXBUF

TX Buffer Hardware Parameters, offset: 0x10

◆ IALR

__IO uint32_t ENET_Type::IALR

Descriptor Individual Lower Address Register, offset: 0x11C

◆ IAUR

__IO uint32_t ENET_Type::IAUR

Descriptor Individual Upper Address Register, offset: 0x118

◆ ICR

__I uint32_t GPT_Type::ICR

GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4

GPT Input Capture Register, array offset: 0x1C, array step: 0x4

◆ ICR1

__IO uint32_t GPIO_Type::ICR1

GPIO interrupt configuration register1, offset: 0xC

◆ ICR2

__IO uint32_t GPIO_Type::ICR2

GPIO interrupt configuration register2, offset: 0x10

◆  [1/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10

◆ ID [2/19]

__IO uint32_t CAN_Type::ID

Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10

Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18

Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x284, array step: 0x18

Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28

Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x284, array step: 0x28

Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48

Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x284, array step: 0x48

◆ ID [3/19]

__I uint32_t USB_Type::ID

Identification register, offset: 0x0

◆  [4/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10

◆  [5/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18

◆  [6/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x284, array step: 0x18

◆  [7/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28

◆  [8/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x284, array step: 0x28

◆  [9/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48

◆  [10/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x284, array step: 0x48

◆  [11/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10

◆  [12/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10

◆  [13/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18

◆  [14/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x284, array step: 0x18

◆  [15/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28

◆  [16/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x284, array step: 0x28

◆  [17/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48

◆  [18/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x284, array step: 0x48

◆  [19/19]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10

◆ IDXBLK

__IO uint32_t PUF_Type::IDXBLK

PUF Index Block Key Output, offset: 0x20C

◆ IDXBLK_DP

__IO uint32_t PUF_Type::IDXBLK_DP

PUF Index Block Key Output, offset: 0x210

◆ IDXBLK_SHIFT

__I uint32_t PUF_Type::IDXBLK_SHIFT

PUF Key Manager Shift Status, offset: 0x258

◆ IDXBLK_STATUS

__I uint32_t PUF_Type::IDXBLK_STATUS

PUF Index Block Setting Status Register, offset: 0x254

◆ IE

__IO uint32_t ADC_Type::IE

Interrupt Enable Register, offset: 0x18

◆ IEE_KEY_CTRL

__IO uint32_t KEY_MANAGER_Type::IEE_KEY_CTRL

CSR IEE Key Control, offset: 0x20

◆ IEEE_R_ALIGN

__I uint32_t ENET_Type::IEEE_R_ALIGN

Frames Received with Alignment Error Statistic Register, offset: 0x2D4

◆ IEEE_R_CRC

__I uint32_t ENET_Type::IEEE_R_CRC

Frames Received with CRC Error Statistic Register, offset: 0x2D0

◆ IEEE_R_DROP

__I uint32_t ENET_Type::IEEE_R_DROP

Frames not Counted Correctly Statistic Register, offset: 0x2C8

◆ IEEE_R_FDXFC

__I uint32_t ENET_Type::IEEE_R_FDXFC

Flow Control Pause Frames Received Statistic Register, offset: 0x2DC

◆ IEEE_R_FRAME_OK

__I uint32_t ENET_Type::IEEE_R_FRAME_OK

Frames Received OK Statistic Register, offset: 0x2CC

◆ IEEE_R_MACERR

__I uint32_t ENET_Type::IEEE_R_MACERR

Receive FIFO Overflow Count Statistic Register, offset: 0x2D8

◆ IEEE_R_OCTETS_OK

__I uint32_t ENET_Type::IEEE_R_OCTETS_OK

Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0

◆ IEEE_T_1COL

__I uint32_t ENET_Type::IEEE_T_1COL

Frames Transmitted with Single Collision Statistic Register, offset: 0x250

◆ IEEE_T_CSERR

__I uint32_t ENET_Type::IEEE_T_CSERR

Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268

◆ IEEE_T_DEF

__I uint32_t ENET_Type::IEEE_T_DEF

Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258

◆ IEEE_T_DROP

uint32_t ENET_Type::IEEE_T_DROP

Reserved Statistic Register, offset: 0x248

◆ IEEE_T_EXCOL

__I uint32_t ENET_Type::IEEE_T_EXCOL

Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260

◆ IEEE_T_FDXFC

__I uint32_t ENET_Type::IEEE_T_FDXFC

Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270

◆ IEEE_T_FRAME_OK

__I uint32_t ENET_Type::IEEE_T_FRAME_OK

Frames Transmitted OK Statistic Register, offset: 0x24C

◆ IEEE_T_LCOL

__I uint32_t ENET_Type::IEEE_T_LCOL

Frames Transmitted with Late Collision Statistic Register, offset: 0x25C

◆ IEEE_T_MACERR

__I uint32_t ENET_Type::IEEE_T_MACERR

Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264

◆ IEEE_T_MCOL

__I uint32_t ENET_Type::IEEE_T_MCOL

Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254

◆ IEEE_T_OCTETS_OK

__I uint32_t ENET_Type::IEEE_T_OCTETS_OK

Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274

◆ IEEE_T_SQE

__I uint32_t ENET_Type::IEEE_T_SQE

Reserved Statistic Register, offset: 0x26C

◆ IER

__IO uint32_t LPSPI_Type::IER

Interrupt Enable Register, offset: 0x18

Interrupt Enable, offset: 0x18

◆ IFLAG1

__IO uint32_t CAN_Type::IFLAG1

Interrupt Flags 1 Register, offset: 0x30

Interrupt Flags 1 register, offset: 0x30

◆ IFLAG2

__IO uint32_t CAN_Type::IFLAG2

Interrupt Flags 2 Register, offset: 0x2C

Interrupt Flags 2 register, offset: 0x2C

◆ IFSTAT

__IO uint32_t PUF_Type::IFSTAT

PUF Interface Status Register, offset: 0xDC

◆ IMAG_PARA

__IO uint32_t CSI_Type::IMAG_PARA

CSI Image Parameter Register, offset: 0x34

◆ IMASK1

__IO uint32_t CAN_Type::IMASK1

Interrupt Masks 1 Register, offset: 0x28

Interrupt Masks 1 register, offset: 0x28

◆ IMASK2

__IO uint32_t CAN_Type::IMASK2

Interrupt Masks 2 Register, offset: 0x24

Interrupt Masks 2 register, offset: 0x24

◆ IMR [1/3]

__I uint16_t ENC_Type::IMR

Input Monitor Register, offset: 0x1A

◆ IMR [2/3]

__IO uint32_t GPC_Type::IMR[4]

IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4

◆ IMR [3/3]

__IO uint32_t GPIO_Type::IMR

GPIO interrupt mask register, offset: 0x14

◆ IMR5

__IO uint32_t GPC_Type::IMR5

IRQ masking register 5, offset: 0x34

◆  [1/4]

__IO uint16_t { ... } ::INIT

Initial Count Register, array offset: 0x2, array step: 0x60

◆ INIT [2/4]

__IO uint16_t PWM_Type::INIT

Initial Count Register, array offset: 0x2, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::INIT

Initial Count Register, array offset: 0x2, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::INIT

Initial Count Register, array offset: 0x2, array step: 0x60

◆ INSTRUCTION_TIMER

__IO uint32_t CDOG_Type::INSTRUCTION_TIMER

Instruction Timer, offset: 0x8

◆ INT

__IO uint32_t DMA_Type::INT

Interrupt Request, offset: 0x24

◆ INT_CTRL

__IO uint32_t TRNG_Type::INT_CTRL

Interrupt Control Register, offset: 0xA4

◆ INT_EN

__IO uint32_t TSC_Type::INT_EN

Interrupt Enable, offset: 0x40

◆  [1/3]

__IO uint32_t { ... } ::INT_ENABLE

Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1, array offset: 0x24, array step: 0x10

◆ INT_ENABLE [2/3]

__IO uint32_t LCDIFV2_Type::INT_ENABLE

Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1, array offset: 0x24, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::INT_ENABLE

Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1, array offset: 0x24, array step: 0x10

◆ INT_MASK [1/2]

__IO uint32_t TRNG_Type::INT_MASK

Mask Register, offset: 0xA8

◆ INT_MASK [2/2]

__IO uint32_t EMVSIM_Type::INT_MASK

Interrupt Mask Register, offset: 0x14

◆ INT_SIG_EN [1/2]

__IO uint32_t FLEXRAM_Type::INT_SIG_EN

Interrupt Enable Register, offset: 0x18

◆ INT_SIG_EN [2/2]

__IO uint32_t TSC_Type::INT_SIG_EN

Interrupt Signal Enable, offset: 0x50

◆ INT_SIGNAL_EN

__IO uint32_t USDHC_Type::INT_SIGNAL_EN

Interrupt Signal Enable, offset: 0x38

◆ INT_STAT_EN

__IO uint32_t FLEXRAM_Type::INT_STAT_EN

Interrupt Status Enable Register, offset: 0x14

◆ INT_STATUS [1/8]

__IO uint32_t FLEXRAM_Type::INT_STATUS

Interrupt Status Register, offset: 0x10

◆ INT_STATUS [2/8]

__I uint32_t TRNG_Type::INT_STATUS

Interrupt Status Register, offset: 0xAC

◆ INT_STATUS [3/8]

__IO uint32_t TSC_Type::INT_STATUS

Intterrupt Status, offset: 0x60

◆ INT_STATUS [4/8]

__IO uint32_t USDHC_Type::INT_STATUS

Interrupt Status, offset: 0x30

◆  [5/8]

__IO uint32_t { ... } ::INT_STATUS

Interrupt Status Register for domain 0..Interrupt Status Register for domain 1, array offset: 0x20, array step: 0x10

◆ INT_STATUS [6/8]

__IO uint32_t LCDIFV2_Type::INT_STATUS

Interrupt Status Register for domain 0..Interrupt Status Register for domain 1, array offset: 0x20, array step: 0x10

◆ INT_STATUS [7/8]

__IO uint32_t SSARC_LP_Type::INT_STATUS

Interrupt Status Register, offset: 0x204

◆  [8/8]

__IO uint32_t { ... } ::INT_STATUS

Interrupt Status Register for domain 0..Interrupt Status Register for domain 1, array offset: 0x20, array step: 0x10

◆ INT_STATUS_EN

__IO uint32_t USDHC_Type::INT_STATUS_EN

Interrupt Status Enable, offset: 0x34

◆ INTCTRL

__IO uint32_t RDC_Type::INTCTRL

Interrupt and Control, offset: 0x28

◆ INTEN [1/7]

__IO uint32_t FLEXSPI_Type::INTEN

Interrupt Enable Register, offset: 0x10

◆ INTEN [2/7]

__IO uint16_t PWM_Type::INTEN

Interrupt Enable Register, array offset: 0x26, array step: 0x60

◆  [3/7]

__IO uint16_t { ... } ::INTEN

Interrupt Enable Register, array offset: 0x26, array step: 0x60

◆ INTEN [4/7]

__IO uint32_t SEMC_Type::INTEN

Interrupt Enable Register, offset: 0x38

◆ INTEN [5/7]

__IO uint32_t PUF_Type::INTEN

PUF Interrupt Enable, offset: 0x100

◆  [6/7]

__IO uint16_t { ... } ::INTEN

Interrupt Enable Register, array offset: 0x26, array step: 0x60

◆  [7/7]

__IO uint16_t { ... } ::INTEN

Interrupt Enable Register, array offset: 0x26, array step: 0x60

◆ INTERFACE_COLOR_CODING

__IO uint32_t DSI_HOST_DPI_INTFC_Type::INTERFACE_COLOR_CODING

INTERFACE_COLOR_CODING, offset: 0x8

◆ INTR [1/2]

__IO uint32_t FLEXSPI_Type::INTR

Interrupt Register, offset: 0x14

◆ INTR [2/2]

__IO uint32_t SEMC_Type::INTR

Interrupt Enable Register, offset: 0x3C

Interrupt Register, offset: 0x3C

◆ INTSTAT [1/2]

__IO uint32_t PUF_Type::INTSTAT

PUF Interrupt Status, offset: 0x104

◆ INTSTAT [2/2]

__IO uint32_t RDC_Type::INTSTAT

Interrupt Status, offset: 0x2C

◆ IOCR

__IO uint32_t SEMC_Type::IOCR

IO Mux Control Register, offset: 0x4

IO MUX Control Register, offset: 0x4

◆ IPCMD [1/2]

__IO uint32_t FLEXSPI_Type::IPCMD

IP Command Register, offset: 0xB0

◆ IPCMD [2/2]

__IO uint32_t SEMC_Type::IPCMD

IP Command register, offset: 0x9C

IP Command Register, offset: 0x9C

◆ IPCR0 [1/2]

__IO uint32_t FLEXSPI_Type::IPCR0

IP Control Register 0, offset: 0xA0

◆ IPCR0 [2/2]

__IO uint32_t SEMC_Type::IPCR0

IP Command control register 0, offset: 0x90

IP Command Control Register 0, offset: 0x90

◆ IPCR1 [1/2]

__IO uint32_t FLEXSPI_Type::IPCR1

IP Control Register 1, offset: 0xA4

◆ IPCR1 [2/2]

__IO uint32_t SEMC_Type::IPCR1

IP Command control register 1, offset: 0x94

IP Command Control Register 1, offset: 0x94

◆ IPCR2

__IO uint32_t SEMC_Type::IPCR2

IP Command control register 2, offset: 0x98

IP Command Control Register 2, offset: 0x98

◆ IPRXDAT

__I uint32_t SEMC_Type::IPRXDAT

RX DATA register (for IP Command), offset: 0xB0

RX DATA Register, offset: 0xB0

◆ IPRXFCR

__IO uint32_t FLEXSPI_Type::IPRXFCR

IP RX FIFO Control Register, offset: 0xB8

◆ IPRXFSTS

__I uint32_t FLEXSPI_Type::IPRXFSTS

IP RX FIFO Status Register, offset: 0xF0

◆ IPSNSZEND0

__IO uint32_t FLEXSPI_Type::IPSNSZEND0

IPS nonsecure region End address of region 0, offset: 0x434

◆ IPSNSZEND1

__IO uint32_t FLEXSPI_Type::IPSNSZEND1

IPS nonsecure region End address of region 1, offset: 0x43C

◆ IPSNSZSTART0

__IO uint32_t FLEXSPI_Type::IPSNSZSTART0

IPS nonsecure region Start address of region 0, offset: 0x430

◆ IPSNSZSTART1

__IO uint32_t FLEXSPI_Type::IPSNSZSTART1

IPS nonsecure region Start address of region 1, offset: 0x438

◆ IPTXDAT

__IO uint32_t SEMC_Type::IPTXDAT

TX DATA register (for IP Command), offset: 0xA0

TX DATA Register, offset: 0xA0

◆ IPTXFCR

__IO uint32_t FLEXSPI_Type::IPTXFCR

IP TX FIFO Control Register, offset: 0xBC

◆ IPTXFSTS

__I uint32_t FLEXSPI_Type::IPTXFSTS

IP TX FIFO Status Register, offset: 0xF4

◆ IR

__IO uint32_t GPT_Type::IR

GPT Interrupt Register, offset: 0xC

◆  [1/3]

__IO uint64_t { ... } ::IRBAR_JR

Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3, array offset: 0x10000, array step: 0x10000

◆ IRBAR_JR [2/3]

__IO uint64_t CAAM_Type::IRBAR_JR

Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3, array offset: 0x10000, array step: 0x10000

◆  [3/3]

__IO uint64_t { ... } ::IRBAR_JR

Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3, array offset: 0x10000, array step: 0x10000

◆  [1/3]

__IO uint32_t { ... } ::IRJAR_JR

Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3, array offset: 0x1001C, array step: 0x10000

◆ IRJAR_JR [2/3]

__IO uint32_t CAAM_Type::IRJAR_JR

Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3, array offset: 0x1001C, array step: 0x10000

◆  [3/3]

__IO uint32_t { ... } ::IRJAR_JR

Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3, array offset: 0x1001C, array step: 0x10000

◆ IRQ_MASK [1/2]

__IO uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_MASK

IRQ_MASK, offset: 0x28

◆ IRQ_MASK [2/2]

__IO uint32_t MIPI_CSI2RX_Type::IRQ_MASK

IRQ Mask Setting Register, offset: 0x110

◆ IRQ_MASK2

__IO uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_MASK2

IRQ_MASK2, offset: 0x2C

◆ IRQ_STATUS [1/2]

__I uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_STATUS

IRQ_STATUS, offset: 0x20

◆ IRQ_STATUS [2/2]

__I uint32_t MIPI_CSI2RX_Type::IRQ_STATUS

IRQ Status Register, offset: 0x10C

◆ IRQ_STATUS2

__I uint32_t DSI_HOST_APB_PKT_IF_Type::IRQ_STATUS2

IRQ_STATUS2, offset: 0x24

◆ IRRIR_JR [1/3]

__IO uint32_t CAAM_Type::IRRIR_JR

Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3, array offset: 0x1005C, array step: 0x10000

◆  [2/3]

__IO uint32_t { ... } ::IRRIR_JR

Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3, array offset: 0x1005C, array step: 0x10000

◆  [3/3]

__IO uint32_t { ... } ::IRRIR_JR

Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3, array offset: 0x1005C, array step: 0x10000

◆ IRSAR_JR [1/3]

__IO uint32_t CAAM_Type::IRSAR_JR

Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3, array offset: 0x10014, array step: 0x10000

◆  [2/3]

__IO uint32_t { ... } ::IRSAR_JR

Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3, array offset: 0x10014, array step: 0x10000

◆  [3/3]

__IO uint32_t { ... } ::IRSAR_JR

Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3, array offset: 0x10014, array step: 0x10000

◆  [1/3]

__IO uint32_t { ... } ::IRSR_JR

Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3, array offset: 0x1000C, array step: 0x10000

◆ IRSR_JR [2/3]

__IO uint32_t CAAM_Type::IRSR_JR

Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3, array offset: 0x1000C, array step: 0x10000

◆  [3/3]

__IO uint32_t { ... } ::IRSR_JR

Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3, array offset: 0x1000C, array step: 0x10000

◆ ISCR [1/2]

__IO uint32_t CM7_MCM_Type::ISCR

Interrupt Status and Control Register, offset: 0x10

◆ ISCR [2/2]

__IO uint32_t MCM_Type::ISCR

Interrupt Status and Control Register, offset: 0x10

◆ ISR [1/2]

__I uint32_t GPC_Type::ISR[4]

IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4

◆ ISR [2/2]

__IO uint32_t GPIO_Type::ISR

GPIO interrupt status register, offset: 0x18

◆ ISR5

__I uint32_t GPC_Type::ISR5

IRQ status resister 5, offset: 0x38

◆ ITCM_ECC_MULTI_ERROR_ADDR

__I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_ADDR

ITCM multi-bit ECC Error Address Register, offset: 0x50

◆ ITCM_ECC_MULTI_ERROR_DATA_LSB

__I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_DATA_LSB

ITCM multi-bit ECC Error Data Register, offset: 0x54

◆ ITCM_ECC_MULTI_ERROR_DATA_MSB

__I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_DATA_MSB

ITCM multi-bit ECC Error Data Register, offset: 0x58

◆ ITCM_ECC_MULTI_ERROR_INFO

__I uint32_t FLEXRAM_Type::ITCM_ECC_MULTI_ERROR_INFO

ITCM multi-bit ECC Error Information Register, offset: 0x4C

◆ ITCM_ECC_SINGLE_ERROR_ADDR

__I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_ADDR

ITCM single-bit ECC Error Address Register, offset: 0x40

◆ ITCM_ECC_SINGLE_ERROR_DATA_LSB

__I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_DATA_LSB

ITCM single-bit ECC Error Data Register, offset: 0x44

◆ ITCM_ECC_SINGLE_ERROR_DATA_MSB

__I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_DATA_MSB

ITCM single-bit ECC Error Data Register, offset: 0x48

◆ ITCM_ECC_SINGLE_ERROR_INFO

__I uint32_t FLEXRAM_Type::ITCM_ECC_SINGLE_ERROR_INFO

ITCM single-bit ECC Error Information Register, offset: 0x3C

◆ ITCM_MAGIC_ADDR

__IO uint32_t FLEXRAM_Type::ITCM_MAGIC_ADDR

ITCM Magic Address Register, offset: 0xC

◆ JDKEKR

__IO uint32_t CAAM_Type::JDKEKR

Job Descriptor Key Encryption Key Register, array offset: 0x400, array step: 0x4

◆ JQ_DEBUG_SEL

__IO uint32_t CAAM_Type::JQ_DEBUG_SEL

Job Queue Debug Select Register, offset: 0xC24

◆  [1/3]

__I uint64_t { ... } ::JRAAA[4]

Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register, array offset: 0x10800, array step: index*0x10000, index2*0x8

◆ JRAAA [2/3]

__I uint64_t CAAM_Type::JRAAA[4]

Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register, array offset: 0x10800, array step: index*0x10000, index2*0x8

◆  [3/3]

__I uint64_t { ... } ::JRAAA[4]

Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register, array offset: 0x10800, array step: index*0x10000, index2*0x8

◆ JRAAV [1/3]

__I uint32_t CAAM_Type::JRAAV

Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register, array offset: 0x10704, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::JRAAV

Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register, array offset: 0x10704, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::JRAAV

Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register, array offset: 0x10704, array step: 0x10000

◆  [1/3]

__IO uint32_t { ... } ::JRCFGR_JR_LS

Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half, array offset: 0x10054, array step: 0x10000

◆ JRCFGR_JR_LS [2/3]

__IO uint32_t CAAM_Type::JRCFGR_JR_LS

Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half, array offset: 0x10054, array step: 0x10000

◆  [3/3]

__IO uint32_t { ... } ::JRCFGR_JR_LS

Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half, array offset: 0x10054, array step: 0x10000

◆  [1/3]

__IO uint32_t { ... } ::JRCFGR_JR_MS

Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half, array offset: 0x10050, array step: 0x10000

◆ JRCFGR_JR_MS [2/3]

__IO uint32_t CAAM_Type::JRCFGR_JR_MS

Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half, array offset: 0x10050, array step: 0x10000

◆  [3/3]

__IO uint32_t { ... } ::JRCFGR_JR_MS

Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half, array offset: 0x10050, array step: 0x10000

◆  [1/3]

__O uint32_t { ... } ::JRCR_JR

Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3, array offset: 0x1006C, array step: 0x10000

◆ JRCR_JR [2/3]

__O uint32_t CAAM_Type::JRCR_JR

Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3, array offset: 0x1006C, array step: 0x10000

◆  [3/3]

__O uint32_t { ... } ::JRCR_JR

Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3, array offset: 0x1006C, array step: 0x10000

◆  [1/3]

__IO uint32_t { ... } ::JRDID_LS

Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half, array offset: 0x14, array step: 0x8

◆ JRDID_LS [2/3]

__IO uint32_t CAAM_Type::JRDID_LS

Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half, array offset: 0x14, array step: 0x8

◆  [3/3]

__IO uint32_t { ... } ::JRDID_LS

Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half, array offset: 0x14, array step: 0x8

◆ JRDID_MS [1/3]

__IO uint32_t CAAM_Type::JRDID_MS

Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half, array offset: 0x10, array step: 0x8

◆  [2/3]

__IO uint32_t { ... } ::JRDID_MS

Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half, array offset: 0x10, array step: 0x8

◆  [3/3]

__IO uint32_t { ... } ::JRDID_MS

Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half, array offset: 0x10, array step: 0x8

◆  [1/3]

__IO uint32_t { ... } ::JRINTR_JR

Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3, array offset: 0x1004C, array step: 0x10000

◆ JRINTR_JR [2/3]

__IO uint32_t CAAM_Type::JRINTR_JR

Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3, array offset: 0x1004C, array step: 0x10000

◆  [3/3]

__IO uint32_t { ... } ::JRINTR_JR

Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3, array offset: 0x1004C, array step: 0x10000

◆ JRJDDA

__I uint64_t CAAM_Type::JRJDDA

Job Ring Job-Done Descriptor Address 0 Register, array offset: 0xE00, array step: 0x8

◆ JRJDJIF

__I uint32_t CAAM_Type::JRJDJIF

Job Ring Job-Done Job ID FIFO, offset: 0xDC4

◆ JRJDJIFBC

__I uint32_t CAAM_Type::JRJDJIFBC

Job Ring Job-Done Job ID FIFO BC, offset: 0xDC0

◆ JRJDS1

__I uint32_t CAAM_Type::JRJDS1

Job Ring Job-Done Source 1, offset: 0xDE4

◆ JRJIDU_LS

__I uint32_t CAAM_Type::JRJIDU_LS

Job Ring Job IDs in Use Register, least-significant half, offset: 0xDBC

◆  [1/3]

__IO uint32_t { ... } ::JRSMVBAR

Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register, array offset: 0x184, array step: 0x8

◆ JRSMVBAR [2/3]

__IO uint32_t CAAM_Type::JRSMVBAR

Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register, array offset: 0x184, array step: 0x8

◆  [3/3]

__IO uint32_t { ... } ::JRSMVBAR

Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register, array offset: 0x184, array step: 0x8

◆  [1/3]

__I uint32_t { ... } ::JRSTAR_JR

Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3, array offset: 0x10044, array step: 0x10000

◆ JRSTAR_JR [2/3]

__I uint32_t CAAM_Type::JRSTAR_JR

Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3, array offset: 0x10044, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::JRSTAR_JR

Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3, array offset: 0x10044, array step: 0x10000

◆ JRSTARTR

__IO uint32_t CAAM_Type::JRSTARTR

Job Ring Start Register, offset: 0x5C

◆ KDDR

__IO uint16_t KPP_Type::KDDR

Keypad Data Direction Register, offset: 0x4

◆ KEY [1/4]

__IO uint32_t DCP_Type::KEY

DCP key index, offset: 0x60

◆ KEY [2/4]

__IO uint32_t OTFAD_Type::KEY[4]

AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4

◆  [3/4]

__IO uint32_t { ... } ::KEY[4]

AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4

◆  [4/4]

__IO uint32_t { ... } ::KEY[4]

AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4

◆ KEYDATA

__IO uint32_t DCP_Type::KEYDATA

DCP key data, offset: 0x70

◆ KEYENABLE

__IO uint32_t PUF_Type::KEYENABLE

PUF Key Manager Enable, offset: 0x204

◆ KEYINDEX

__IO uint32_t PUF_Type::KEYINDEX

PUF Key Index Register, offset: 0x4

◆ KEYINPUT

__O uint32_t PUF_Type::KEYINPUT

PUF Key Input Register, offset: 0x40

◆ KEYLOCK

__IO uint32_t PUF_Type::KEYLOCK

PUF Key Manager Lock, offset: 0x200

◆ KEYMASK

__IO uint32_t PUF_Type::KEYMASK

PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable, array offset: 0x214, array step: 0x4

◆ KEYOUTINDEX

__I uint32_t PUF_Type::KEYOUTINDEX

PUF Key Output Index Register, offset: 0x60

◆ KEYOUTPUT

__I uint32_t PUF_Type::KEYOUTPUT

PUF Key Output Register, offset: 0x64

◆ KEYRESET

__IO uint32_t PUF_Type::KEYRESET

PUF Key Manager Reset, offset: 0x208

◆ KEYSIZE

__IO uint32_t PUF_Type::KEYSIZE

PUF Key Size Register, offset: 0x8

◆ KPCR

__IO uint16_t KPP_Type::KPCR

Keypad Control Register, offset: 0x0

◆ KPDR

__IO uint16_t KPP_Type::KPDR

Keypad Data Register, offset: 0x6

◆ KPSR

__IO uint16_t KPP_Type::KPSR

Keypad Status Register, offset: 0x2

◆ LASTEDGE

__I uint16_t ENC_Type::LASTEDGE

Last Edge Time Register, offset: 0x28

◆ LASTEDGEH

__I uint16_t ENC_Type::LASTEDGEH

Last Edge Time Hold Register, offset: 0x2A

◆ LCOMP

__IO uint16_t ENC_Type::LCOMP

Lower Position Compare Register, offset: 0x26

◆ LDO_LPSR_ANA_BYPASS_EN_SP

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_BYPASS_EN_SP

LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER, offset: 0x640

◆ LDO_LPSR_ANA_ENABLE_SP

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_ENABLE_SP

LDO_LPSR_ANA_ENABLE_SP_REGISTER, offset: 0x610

◆ LDO_LPSR_ANA_LP_MODE_SP

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_LP_MODE_SP

LDO_LPSR_ANA_LP_MODE_SP_REGISTER, offset: 0x620

◆ LDO_LPSR_ANA_STBY_EN_SP

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_STBY_EN_SP

LDO_LPSR_ANA_STBY_EN_SP_REGISTER, offset: 0x650

◆ LDO_LPSR_ANA_TRACKING_EN_SP

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_ANA_TRACKING_EN_SP

LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER, offset: 0x630

◆ LDO_LPSR_DIG_BYPASS_EN_SP

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_BYPASS_EN_SP

LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER, offset: 0x6D0

◆ LDO_LPSR_DIG_ENABLE_SP

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_ENABLE_SP

LDO_LPSR_DIG_ENABLE_SP_REGISTER, offset: 0x660

◆ LDO_LPSR_DIG_LP_MODE_SP

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_LP_MODE_SP

LDO_LPSR_DIG_LP_MODE_SP_REGISTER, offset: 0x6B0

◆ LDO_LPSR_DIG_STBY_EN_SP

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_STBY_EN_SP

LDO_LPSR_DIG_STBY_EN_SP_REGISTER, offset: 0x6E0

◆ LDO_LPSR_DIG_TRACKING_EN_SP

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRACKING_EN_SP

LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER, offset: 0x6C0

◆ LDO_LPSR_DIG_TRG_SP0

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP0

LDO_LPSR_DIG_TRG_SP0_REGISTER, offset: 0x670

◆ LDO_LPSR_DIG_TRG_SP1

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP1

LDO_LPSR_DIG_TRG_SP1_REGISTER, offset: 0x680

◆ LDO_LPSR_DIG_TRG_SP2

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP2

LDO_LPSR_DIG_TRG_SP2_REGISTER, offset: 0x690

◆ LDO_LPSR_DIG_TRG_SP3

__IO uint32_t ANADIG_PMU_Type::LDO_LPSR_DIG_TRG_SP3

LDO_LPSR_DIG_TRG_SP3_REGISTER, offset: 0x6A0

◆ LDO_PLL_ENABLE_SP

__IO uint32_t ANADIG_PMU_Type::LDO_PLL_ENABLE_SP

LDO_PLL_ENABLE_SP_REGISTER, offset: 0x600

◆ LDVAL [1/4]

__IO uint32_t PIT_Type::LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10

◆  [2/4]

__IO uint32_t { ... } ::LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10

◆  [3/4]

__IO uint32_t { ... } ::LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10

◆  [4/4]

__IO uint32_t { ... } ::LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10

◆ LINIT

__IO uint16_t ENC_Type::LINIT

Lower Initialization Register, offset: 0x18

◆ LMDR

__IO uint32_t MCM_Type::LMDR[4]

Local Memory Descriptor Register, array offset: 0x400, array step: 0x4

◆ LMFAR

__I uint32_t MCM_Type::LMFAR

LMEM Fault Address Register, offset: 0x490

◆ LMFATR

__IO uint32_t MCM_Type::LMFATR

LMEM Fault Attribute Register, offset: 0x494

◆ LMFDHR

__I uint32_t MCM_Type::LMFDHR

LMEM Fault Data High Register, offset: 0x4A0

◆ LMFDLR

__I uint32_t MCM_Type::LMFDLR

LMEM Fault Data Low Register, offset: 0x4A4

◆ LMOD

__IO uint16_t ENC_Type::LMOD

Lower Modulus Register, offset: 0x22

◆ LMPECR

__IO uint32_t MCM_Type::LMPECR

LMEM Parity & ECC Control Register, offset: 0x480

◆ LMPEIR

__IO uint32_t MCM_Type::LMPEIR

LMEM Parity & ECC Interrupt Register, offset: 0x488

◆  [1/4]

__IO uint16_t { ... } ::LOAD

Timer Channel Load Register, array offset: 0x6, array step: 0x20

◆ LOAD [2/4]

__IO uint16_t TMR_Type::LOAD

Timer Channel Load Register, array offset: 0x6, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::LOAD

Timer Channel Load Register, array offset: 0x6, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::LOAD

Timer Channel Load Register, array offset: 0x6, array step: 0x20

◆ LOCK [1/2]

__IO uint32_t OCOTP_Type::LOCK

Value of OTP Bank0 Word0 (Lock controls), offset: 0x400

◆ LOCK [2/2]

__I uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::LOCK

LOCK, offset: 0x30

◆ LOCK_BYP

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::LOCK_BYP

LOCK_BYP, offset: 0x34

◆ LOCKED0

__I uint32_t OCOTP_Type::LOCKED0

OTP Controller Program Locked Status 0 Register, offset: 0x600

◆ LOCKED1

__I uint32_t OCOTP_Type::LOCKED1

OTP Controller Program Locked Status 1 Register, offset: 0x610

◆ LOCKED2

__I uint32_t OCOTP_Type::LOCKED2

OTP Controller Program Locked Status 2 Register, offset: 0x620

◆ LOCKED3

__I uint32_t OCOTP_Type::LOCKED3

OTP Controller Program Locked Status 3 Register, offset: 0x630

◆ LOCKED4

__I uint32_t OCOTP_Type::LOCKED4

OTP Controller Program Locked Status 4 Register, offset: 0x640

◆  [1/2]

__IO uint32_t { ... } ::LOOPBACK

USB Loopback Test Register, array offset: 0x1E0, array step: 0x60

◆ LOOPBACK [2/2]

__IO uint32_t USB_ANALOG_Type::LOOPBACK

USB Loopback Test Register, array offset: 0x1E0, array step: 0x60

◆  [1/2]

__IO uint32_t { ... } ::LOOPBACK_CLR

USB Loopback Test Register, array offset: 0x1E8, array step: 0x60

◆ LOOPBACK_CLR [2/2]

__IO uint32_t USB_ANALOG_Type::LOOPBACK_CLR

USB Loopback Test Register, array offset: 0x1E8, array step: 0x60

◆  [1/2]

__IO uint32_t { ... } ::LOOPBACK_SET

USB Loopback Test Register, array offset: 0x1E4, array step: 0x60

◆ LOOPBACK_SET [2/2]

__IO uint32_t USB_ANALOG_Type::LOOPBACK_SET

USB Loopback Test Register, array offset: 0x1E4, array step: 0x60

◆  [1/2]

__IO uint32_t { ... } ::LOOPBACK_TOG

USB Loopback Test Register, array offset: 0x1EC, array step: 0x60

◆ LOOPBACK_TOG [2/2]

__IO uint32_t USB_ANALOG_Type::LOOPBACK_TOG

USB Loopback Test Register, array offset: 0x1EC, array step: 0x60

◆ LOWPWR_CTRL

__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL

XTAL OSC (LP) Control Register, offset: 0x270

◆ LOWPWR_CTRL_CLR

__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_CLR

XTAL OSC (LP) Control Register, offset: 0x278

◆ LOWPWR_CTRL_SET

__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_SET

XTAL OSC (LP) Control Register, offset: 0x274

◆ LOWPWR_CTRL_TOG

__IO uint32_t XTALOSC24M_Type::LOWPWR_CTRL_TOG

XTAL OSC (LP) Control Register, offset: 0x27C

◆ LPATCLKR

__IO uint32_t SNVS_Type::LPATCLKR

SNVS_LP Active Tamper Clock Control Register, offset: 0xE4

◆ LPATCR

__O uint32_t SNVS_Type::LPATCR

SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register, array offset: 0xC0, array step: 0x4

◆ LPATCTLR

__IO uint32_t SNVS_Type::LPATCTLR

SNVS_LP Active Tamper Control Register, offset: 0xE0

◆ LPATRC1R

__IO uint32_t SNVS_Type::LPATRC1R

SNVS_LP Active Tamper Routing Control 1 Register, offset: 0xE8

◆ LPATRC2R

__IO uint32_t SNVS_Type::LPATRC2R

SNVS_LP Active Tamper Routing Control 2 Register, offset: 0xEC

◆ LPCR

__IO uint32_t SNVS_Type::LPCR

SNVS_LP Control Register, offset: 0x38

◆ LPGPR

__IO uint32_t SNVS_Type::LPGPR

SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4

SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4

◆ LPGPR0_LEGACY_ALIAS

__IO uint32_t SNVS_Type::LPGPR0_LEGACY_ALIAS

SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68

◆ LPGPR_ALIAS

__IO uint32_t SNVS_Type::LPGPR_ALIAS

SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4

◆ LPLR

__IO uint32_t SNVS_Type::LPLR

SNVS_LP Lock Register, offset: 0x34

◆ LPLVDR

__IO uint32_t SNVS_Type::LPLVDR

SNVS_LP Digital Low-Voltage Detector Register, offset: 0x64

◆ LPMKCR

__IO uint32_t SNVS_Type::LPMKCR

SNVS_LP Master Key Control Register, offset: 0x3C

◆ LPOS

__IO uint16_t ENC_Type::LPOS

Lower Position Counter Register, offset: 0x10

◆ LPOSH

__I uint16_t ENC_Type::LPOSH

Lower Position Hold Register, offset: 0x14

◆ LPSECR

__IO uint32_t SNVS_Type::LPSECR

SNVS_LP Security Events Configuration Register, offset: 0x48

◆ LPSMCLR

__IO uint32_t SNVS_Type::LPSMCLR

SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60

◆ LPSMCMR

__IO uint32_t SNVS_Type::LPSMCMR

SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C

◆ LPSR

__IO uint32_t SNVS_Type::LPSR

SNVS_LP Status Register, offset: 0x4C

◆ LPSR_1P8_LDO_OTP_TRIM_VALUE

__I uint32_t ANADIG_PMU_Type::LPSR_1P8_LDO_OTP_TRIM_VALUE

LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER, offset: 0x7D0

◆ LPSRTCLR

__IO uint32_t SNVS_Type::LPSRTCLR

SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54

◆ LPSRTCMR

__IO uint32_t SNVS_Type::LPSRTCMR

SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50

◆ LPSVCR

__IO uint32_t SNVS_Type::LPSVCR

SNVS_LP Security Violation Control Register, offset: 0x40

◆ LPTAR

__IO uint32_t SNVS_Type::LPTAR

SNVS_LP Time Alarm Register, offset: 0x58

◆ LPTDC2R

__IO uint32_t SNVS_Type::LPTDC2R

SNVS_LP Tamper Detectors Config 2 Register, offset: 0xA0

◆ LPTDCR

__IO uint32_t SNVS_Type::LPTDCR

SNVS_LP Tamper Detect Configuration Register, offset: 0x48

◆ LPTDSR

__IO uint32_t SNVS_Type::LPTDSR

SNVS_LP Tamper Detectors Status Register, offset: 0xA4

◆ LPTGF1CR

__IO uint32_t SNVS_Type::LPTGF1CR

SNVS_LP Tamper Glitch Filter 1 Configuration Register, offset: 0xA8

◆ LPTGF2CR

__IO uint32_t SNVS_Type::LPTGF2CR

SNVS_LP Tamper Glitch Filter 2 Configuration Register, offset: 0xAC

◆ LPTGFCR

__IO uint32_t SNVS_Type::LPTGFCR

SNVS_LP Tamper Glitch Filters Configuration Register, offset: 0x44

◆ LPZMKR

__IO uint32_t SNVS_Type::LPZMKR

SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4

◆ LTMR64H

__I uint32_t PIT_Type::LTMR64H

PIT Upper Lifetime Timer Register, offset: 0xE0

◆ LTMR64L

__I uint32_t PIT_Type::LTMR64L

PIT Lower Lifetime Timer Register, offset: 0xE4

◆ LUT

__IO uint32_t FLEXSPI_Type::LUT

LUT 0..LUT 63, array offset: 0x200, array step: 0x4

◆ LUT0_ADDR

__IO uint32_t LCDIF_Type::LUT0_ADDR

Lookup Table 0 Index Register, offset: 0xB10

◆ LUT0_DATA

__IO uint32_t LCDIF_Type::LUT0_DATA

Lookup Table 0 Data Register, offset: 0xB20

◆ LUT1_ADDR

__IO uint32_t LCDIF_Type::LUT1_ADDR

Lookup Table 1 Index Register, offset: 0xB30

◆ LUT1_DATA

__IO uint32_t LCDIF_Type::LUT1_DATA

Lookup Table 1 Data Register, offset: 0xB40

◆ LUT_CTRL

__IO uint32_t LCDIF_Type::LUT_CTRL

Look Up Table Control Register, offset: 0xB00

◆ LUTCR

__IO uint32_t FLEXSPI_Type::LUTCR

LUT Control Register, offset: 0x1C

◆ LUTKEY

__IO uint32_t FLEXSPI_Type::LUTKEY

LUT Key Register, offset: 0x18

◆ M_PRG_HS_PREPARE

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::M_PRG_HS_PREPARE

M_PRG_HS_PREPARE, offset: 0x4

◆ M_PRG_HS_TRAIL

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::M_PRG_HS_TRAIL

M_PRG_HS_TRAIL, offset: 0x14

◆ M_PRG_HS_ZERO

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::M_PRG_HS_ZERO

M_PRG_HS_ZERO, offset: 0xC

◆ MAC0

__IO uint32_t OCOTP_Type::MAC0

Value of OTP Bank4 Word2 (MAC Address), offset: 0x620

◆ MAC1

__IO uint32_t OCOTP_Type::MAC1

Value of OTP Bank4 Word3 (MAC Address), offset: 0x630

◆ MASK

__IO uint16_t PWM_Type::MASK

Mask Register, offset: 0x182

◆ MASTER_KEY_CTRL

__IO uint32_t KEY_MANAGER_Type::MASTER_KEY_CTRL

CSR Master Key Control Register, offset: 0x0

◆ MATCH

__IO uint32_t LPUART_Type::MATCH

LPUART Match Address Register, offset: 0x20

◆ MC_PRG_HS_PREPARE

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::MC_PRG_HS_PREPARE

MC_PRG_HS_PREPARE, offset: 0x8

◆ MC_PRG_HS_TRAIL

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::MC_PRG_HS_TRAIL

MC_PRG_HS_TRAIL, offset: 0x18

◆ MC_PRG_HS_ZERO

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::MC_PRG_HS_ZERO

MC_PRG_HS_ZERO, offset: 0x10

◆ MCCR0

__IO uint32_t LPI2C_Type::MCCR0

Master Clock Configuration Register 0, offset: 0x48

Master Clock Configuration 0, offset: 0x48

◆ MCCR1

__IO uint32_t LPI2C_Type::MCCR1

Master Clock Configuration Register 1, offset: 0x50

Master Clock Configuration 1, offset: 0x50

◆ MCFGR

__IO uint32_t CAAM_Type::MCFGR

Master Configuration Register, offset: 0x4

◆ MCFGR0

__IO uint32_t LPI2C_Type::MCFGR0

Master Configuration Register 0, offset: 0x20

Master Configuration 0, offset: 0x20

◆ MCFGR1

__IO uint32_t LPI2C_Type::MCFGR1

Master Configuration Register 1, offset: 0x24

Master Configuration 1, offset: 0x24

◆ MCFGR2

__IO uint32_t LPI2C_Type::MCFGR2

Master Configuration Register 2, offset: 0x28

Master Configuration 2, offset: 0x28

◆ MCFGR3

__IO uint32_t LPI2C_Type::MCFGR3

Master Configuration Register 3, offset: 0x2C

Master Configuration 3, offset: 0x2C

◆ MCR [1/5]

__IO uint32_t CAN_Type::MCR

Module Configuration Register, offset: 0x0

Module Configuration register, offset: 0x0

◆ MCR [2/5]

__IO uint32_t LPI2C_Type::MCR

Master Control Register, offset: 0x10

Master Control, offset: 0x10

◆ MCR [3/5]

__IO uint32_t PIT_Type::MCR

PIT Module Control Register, offset: 0x0

◆ MCR [4/5]

__IO uint32_t SEMC_Type::MCR

Module Control Register, offset: 0x0

◆ MCR [5/5]

__IO uint32_t XRDC2_Type::MCR

Module Control Register, offset: 0x0

◆ MCR0

__IO uint32_t FLEXSPI_Type::MCR0

Module Control Register 0, offset: 0x0

◆ MCR1

__IO uint32_t FLEXSPI_Type::MCR1

Module Control Register 1, offset: 0x4

◆ MCR2

__IO uint32_t FLEXSPI_Type::MCR2

Module Control Register 2, offset: 0x8

◆ MCTL

__IO uint32_t TRNG_Type::MCTL

Miscellaneous Control Register, offset: 0x0

◆ MCTRL

__IO uint16_t PWM_Type::MCTRL

Master Control Register, offset: 0x188

◆ MCTRL2

__IO uint16_t PWM_Type::MCTRL2

Master Control 2 Register, offset: 0x18A

◆ MDA

__IO uint32_t RDC_Type::MDA

Master Domain Assignment, array offset: 0x200, array step: 0x4

◆  [1/3]

__IO uint32_t { ... } ::MDAC_MDA_W0

Master Domain Assignment, array offset: 0x2000, array step: index*0x100, index2*0x8

◆ MDAC_MDA_W0 [2/3]

__IO uint32_t XRDC2_Type::MDAC_MDA_W0

Master Domain Assignment, array offset: 0x2000, array step: index*0x100, index2*0x8

◆  [3/3]

__IO uint32_t { ... } ::MDAC_MDA_W0

Master Domain Assignment, array offset: 0x2000, array step: index*0x100, index2*0x8

◆  [1/3]

__IO uint32_t { ... } ::MDAC_MDA_W1

Master Domain Assignment, array offset: 0x2004, array step: index*0x100, index2*0x8

◆ MDAC_MDA_W1 [2/3]

__IO uint32_t XRDC2_Type::MDAC_MDA_W1

Master Domain Assignment, array offset: 0x2004, array step: index*0x100, index2*0x8

◆  [3/3]

__IO uint32_t { ... } ::MDAC_MDA_W1

Master Domain Assignment, array offset: 0x2004, array step: index*0x100, index2*0x8

◆ MDER

__IO uint32_t LPI2C_Type::MDER

Master DMA Enable Register, offset: 0x1C

Master DMA Enable, offset: 0x1C

◆ MDMR

__IO uint32_t LPI2C_Type::MDMR

Master Data Match Register, offset: 0x40

Master Data Match, offset: 0x40

◆ MEASEURE_VALUE

__I uint32_t TSC_Type::MEASEURE_VALUE

Measure Value, offset: 0x30

◆ MECR

__IO uint32_t CAN_Type::MECR

Memory Error Control register, offset: 0xAE0

◆ MEGA_CTRL

__IO uint32_t PGC_Type::MEGA_CTRL

PGC Mega Control Register, offset: 0x220

◆ MEGA_PDNSCR

__IO uint32_t PGC_Type::MEGA_PDNSCR

PGC Mega Pull Down Sequence Control Register, offset: 0x228

◆ MEGA_PUPSCR

__IO uint32_t PGC_Type::MEGA_PUPSCR

PGC Mega Power Up Sequence Control Register, offset: 0x224

◆ MEGA_SR

__IO uint32_t PGC_Type::MEGA_SR

PGC Mega Power Gating Controller Status Register, offset: 0x22C

◆ MEM0

__IO uint32_t OCOTP_Type::MEM0

Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480

◆ MEM1

__IO uint32_t OCOTP_Type::MEM1

Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490

◆ MEM2

__IO uint32_t OCOTP_Type::MEM2

Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0

◆ MEM3

__IO uint32_t OCOTP_Type::MEM3

Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0

◆ MEM4

__IO uint32_t OCOTP_Type::MEM4

Value of OTP Bank 1 Word 4 (Memory Related Info.), offset: 0x4C0

◆ MEMCFG

__I uint32_t MCM_Type::MEMCFG

Memory configuration, offset: 0x4

◆ MFCR

__IO uint32_t LPI2C_Type::MFCR

Master FIFO Control Register, offset: 0x58

Master FIFO Control, offset: 0x58

◆ MFSR

__I uint32_t LPI2C_Type::MFSR

Master FIFO Status Register, offset: 0x5C

Master FIFO Status, offset: 0x5C

◆ MIBC

__IO uint32_t ENET_Type::MIBC

MIB Control Register, offset: 0x64

◆ MIER

__IO uint32_t LPI2C_Type::MIER

Master Interrupt Enable Register, offset: 0x18

Master Interrupt Enable, offset: 0x18

◆ MIF_AUTHEN_CTRL

__IO uint32_t PGMC_MIF_Type::MIF_AUTHEN_CTRL

MIF Authentication Control, offset: 0x4

◆ MIF_MLPL_ARR_PDN

__IO uint32_t PGMC_MIF_Type::MIF_MLPL_ARR_PDN

MIF MLPL control of array power down, offset: 0x60

◆ MIF_MLPL_HS

__IO uint32_t PGMC_MIF_Type::MIF_MLPL_HS

MIF MLPL control of HS, offset: 0x40

◆ MIF_MLPL_IG

__IO uint32_t PGMC_MIF_Type::MIF_MLPL_IG

MIF MLPL control of IG, offset: 0x20

◆ MIF_MLPL_INITN

__IO uint32_t PGMC_MIF_Type::MIF_MLPL_INITN

MIF MLPL control of INITN, offset: 0x80

◆ MIF_MLPL_ISO

__IO uint32_t PGMC_MIF_Type::MIF_MLPL_ISO

MIF MLPL control of isolation enable, offset: 0xB0

◆ MIF_MLPL_LS

__IO uint32_t PGMC_MIF_Type::MIF_MLPL_LS

MIF MLPL control of LS, offset: 0x30

◆ MIF_MLPL_PER_PDN

__IO uint32_t PGMC_MIF_Type::MIF_MLPL_PER_PDN

MIF MLPL control of peripheral power down, offset: 0x70

◆ MIF_MLPL_SLEEP

__IO uint32_t PGMC_MIF_Type::MIF_MLPL_SLEEP

MIF MLPL control of SLEEP, offset: 0x10

◆ MIF_MLPL_STDBY

__IO uint32_t PGMC_MIF_Type::MIF_MLPL_STDBY

MIF MLPL control of STDBY, offset: 0x50

◆ MISC [1/2]

__IO uint32_t USB_ANALOG_Type::MISC

USB Misc Register, array offset: 0x1F0, array step: 0x60

◆  [2/2]

__IO uint32_t { ... } ::MISC

USB Misc Register, array offset: 0x1F0, array step: 0x60

◆ MISC0 [1/3]

__IO uint32_t CCM_ANALOG_Type::MISC0

Miscellaneous Register 0, offset: 0x150

◆ MISC0 [2/3]

__IO uint32_t PMU_Type::MISC0

Miscellaneous Register 0, offset: 0x150

◆ MISC0 [3/3]

__IO uint32_t XTALOSC24M_Type::MISC0

Miscellaneous Register 0, offset: 0x150

◆ MISC0_CLR [1/3]

__IO uint32_t CCM_ANALOG_Type::MISC0_CLR

Miscellaneous Register 0, offset: 0x158

◆ MISC0_CLR [2/3]

__IO uint32_t PMU_Type::MISC0_CLR

Miscellaneous Register 0, offset: 0x158

◆ MISC0_CLR [3/3]

__IO uint32_t XTALOSC24M_Type::MISC0_CLR

Miscellaneous Register 0, offset: 0x158

◆ MISC0_SET [1/3]

__IO uint32_t CCM_ANALOG_Type::MISC0_SET

Miscellaneous Register 0, offset: 0x154

◆ MISC0_SET [2/3]

__IO uint32_t PMU_Type::MISC0_SET

Miscellaneous Register 0, offset: 0x154

◆ MISC0_SET [3/3]

__IO uint32_t XTALOSC24M_Type::MISC0_SET

Miscellaneous Register 0, offset: 0x154

◆ MISC0_TOG [1/3]

__IO uint32_t CCM_ANALOG_Type::MISC0_TOG

Miscellaneous Register 0, offset: 0x15C

◆ MISC0_TOG [2/3]

__IO uint32_t PMU_Type::MISC0_TOG

Miscellaneous Register 0, offset: 0x15C

◆ MISC0_TOG [3/3]

__IO uint32_t XTALOSC24M_Type::MISC0_TOG

Miscellaneous Register 0, offset: 0x15C

◆ MISC1 [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC1

Miscellaneous Register 1, offset: 0x160

◆ MISC1 [2/2]

__IO uint32_t PMU_Type::MISC1

Miscellaneous Register 1, offset: 0x160

◆ MISC1_CLR [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC1_CLR

Miscellaneous Register 1, offset: 0x168

◆ MISC1_CLR [2/2]

__IO uint32_t PMU_Type::MISC1_CLR

Miscellaneous Register 1, offset: 0x168

◆ MISC1_SET [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC1_SET

Miscellaneous Register 1, offset: 0x164

◆ MISC1_SET [2/2]

__IO uint32_t PMU_Type::MISC1_SET

Miscellaneous Register 1, offset: 0x164

◆ MISC1_TOG [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC1_TOG

Miscellaneous Register 1, offset: 0x16C

◆ MISC1_TOG [2/2]

__IO uint32_t PMU_Type::MISC1_TOG

Miscellaneous Register 1, offset: 0x16C

◆ MISC2 [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC2

Miscellaneous Register 2, offset: 0x170

◆ MISC2 [2/2]

__IO uint32_t PMU_Type::MISC2

Miscellaneous Control Register, offset: 0x170

◆ MISC2_CLR [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC2_CLR

Miscellaneous Register 2, offset: 0x178

◆ MISC2_CLR [2/2]

__IO uint32_t PMU_Type::MISC2_CLR

Miscellaneous Control Register, offset: 0x178

◆ MISC2_SET [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC2_SET

Miscellaneous Register 2, offset: 0x174

◆ MISC2_SET [2/2]

__IO uint32_t PMU_Type::MISC2_SET

Miscellaneous Control Register, offset: 0x174

◆ MISC2_TOG [1/2]

__IO uint32_t CCM_ANALOG_Type::MISC2_TOG

Miscellaneous Register 2, offset: 0x17C

◆ MISC2_TOG [2/2]

__IO uint32_t PMU_Type::MISC2_TOG

Miscellaneous Control Register, offset: 0x17C

◆ MISC_CLR [1/2]

__IO uint32_t USB_ANALOG_Type::MISC_CLR

USB Misc Register, array offset: 0x1F8, array step: 0x60

◆  [2/2]

__IO uint32_t { ... } ::MISC_CLR

USB Misc Register, array offset: 0x1F8, array step: 0x60

◆ MISC_CONF0

__IO uint32_t OCOTP_Type::MISC_CONF0

Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0

◆ MISC_CONF1

__IO uint32_t OCOTP_Type::MISC_CONF1

Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0

◆ MISC_DIFPROG

__I uint32_t ANADIG_MISC_Type::MISC_DIFPROG

Chip Silicon Version Register, offset: 0x800

◆ MISC_SET [1/2]

__IO uint32_t USB_ANALOG_Type::MISC_SET

USB Misc Register, array offset: 0x1F4, array step: 0x60

◆  [2/2]

__IO uint32_t { ... } ::MISC_SET

USB Misc Register, array offset: 0x1F4, array step: 0x60

◆  [1/2]

__IO uint32_t { ... } ::MISC_TOG

USB Misc Register, array offset: 0x1FC, array step: 0x60

◆ MISC_TOG [2/2]

__IO uint32_t USB_ANALOG_Type::MISC_TOG

USB Misc Register, array offset: 0x1FC, array step: 0x60

◆ MISCCR4

__I uint32_t FLEXSPI_Type::MISCCR4

Misc Control Register 4, offset: 0xD0

◆ MISCCR5

__I uint32_t FLEXSPI_Type::MISCCR5

Misc Control Register 5, offset: 0xD4

◆ MISCCR6

__I uint32_t FLEXSPI_Type::MISCCR6

Misc Control Register 6, offset: 0xD8

◆ MISCCR7

__I uint32_t FLEXSPI_Type::MISCCR7

Misc Control Register 7, offset: 0xDC

◆ MIX_CTRL

__IO uint32_t USDHC_Type::MIX_CTRL

Mixer Control, offset: 0x48

◆ MMC_BOOT

__IO uint32_t USDHC_Type::MMC_BOOT

MMC Boot, offset: 0xC4

◆ MMFR

__IO uint32_t ENET_Type::MMFR

MII Management Frame Register, offset: 0x40

◆ MODIR

__IO uint32_t LPUART_Type::MODIR

LPUART Modem IrDA Register, offset: 0x24

◆ MPECC

__I uint32_t CAAM_Type::MPECC

Manufacturing Protection ECC Register, offset: 0x3F8

◆ MPMR

__IO uint8_t CAAM_Type::MPMR

Manufacturing Protection Message Register, array offset: 0x380, array step: 0x1

◆ MPPKR

__IO uint8_t CAAM_Type::MPPKR

Manufacturing Protection Private Key Register, array offset: 0x300, array step: 0x1

◆ MPR

__IO uint32_t AIPSTZ_Type::MPR

Master Priviledge Registers, offset: 0x0

◆ MPTESTR

__I uint8_t CAAM_Type::MPTESTR

Manufacturing Protection Test Register, array offset: 0x3C0, array step: 0x1

◆ MRBR

__IO uint32_t ENET_Type::MRBR

Maximum Receive Buffer Size Register - Ring 0, offset: 0x188

◆ MRBR1

__IO uint32_t ENET_Type::MRBR1

Maximum Receive Buffer Size Register - Ring 1, offset: 0x168

◆ MRBR2

__IO uint32_t ENET_Type::MRBR2

Maximum Receive Buffer Size Register - Ring 2, offset: 0x174

◆ MRC [1/3]

__IO uint32_t RDC_Type::MRC

Memory Region Control, array offset: 0x808, array step: 0x10

◆  [2/3]

__IO uint32_t { ... } ::MRC

Memory Region Control, array offset: 0x808, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::MRC

Memory Region Control, array offset: 0x808, array step: 0x10

◆  [1/3]

__IO uint32_t { ... } ::MRC_MRGD_W0

Memory Region Descriptor, array offset: 0x8000, array step: index*0x400, index2*0x20

◆ MRC_MRGD_W0 [2/3]

__IO uint32_t XRDC2_Type::MRC_MRGD_W0

Memory Region Descriptor, array offset: 0x8000, array step: index*0x400, index2*0x20

◆  [3/3]

__IO uint32_t { ... } ::MRC_MRGD_W0

Memory Region Descriptor, array offset: 0x8000, array step: index*0x400, index2*0x20

◆ MRC_MRGD_W1 [1/3]

__IO uint32_t XRDC2_Type::MRC_MRGD_W1

Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20

◆  [2/3]

__IO uint32_t { ... } ::MRC_MRGD_W1

Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20

◆  [3/3]

__IO uint32_t { ... } ::MRC_MRGD_W1

Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20

◆  [1/3]

__IO uint32_t { ... } ::MRC_MRGD_W2

Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20

◆ MRC_MRGD_W2 [2/3]

__IO uint32_t XRDC2_Type::MRC_MRGD_W2

Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20

◆  [3/3]

__IO uint32_t { ... } ::MRC_MRGD_W2

Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20

◆  [1/3]

__IO uint32_t { ... } ::MRC_MRGD_W3

Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20

◆ MRC_MRGD_W3 [2/3]

__IO uint32_t XRDC2_Type::MRC_MRGD_W3

Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20

◆  [3/3]

__IO uint32_t { ... } ::MRC_MRGD_W3

Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20

◆  [1/3]

__IO uint32_t { ... } ::MRC_MRGD_W5

Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20

◆ MRC_MRGD_W5 [2/3]

__IO uint32_t XRDC2_Type::MRC_MRGD_W5

Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20

◆  [3/3]

__IO uint32_t { ... } ::MRC_MRGD_W5

Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20

◆ MRC_MRGD_W6 [1/3]

__IO uint32_t XRDC2_Type::MRC_MRGD_W6

Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20

◆  [2/3]

__IO uint32_t { ... } ::MRC_MRGD_W6

Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20

◆  [3/3]

__IO uint32_t { ... } ::MRC_MRGD_W6

Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20

◆ MRDR

__I uint32_t LPI2C_Type::MRDR

Master Receive Data Register, offset: 0x70

Master Receive Data, offset: 0x70

◆ MREA [1/3]

__IO uint32_t RDC_Type::MREA

Memory Region End Address, array offset: 0x804, array step: 0x10

◆  [2/3]

__IO uint32_t { ... } ::MREA

Memory Region End Address, array offset: 0x804, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::MREA

Memory Region End Address, array offset: 0x804, array step: 0x10

◆ MRSA [1/3]

__IO uint32_t RDC_Type::MRSA

Memory Region Start Address, array offset: 0x800, array step: 0x10

◆  [2/3]

__IO uint32_t { ... } ::MRSA

Memory Region Start Address, array offset: 0x800, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::MRSA

Memory Region Start Address, array offset: 0x800, array step: 0x10

◆ MRVS [1/3]

__IO uint32_t RDC_Type::MRVS

Memory Region Violation Status, array offset: 0x80C, array step: 0x10

◆  [2/3]

__IO uint32_t { ... } ::MRVS

Memory Region Violation Status, array offset: 0x80C, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::MRVS

Memory Region Violation Status, array offset: 0x80C, array step: 0x10

◆ MSC_MSAC_W0 [1/3]

__IO uint32_t XRDC2_Type::MSC_MSAC_W0

Memory Slot Access Control, array offset: 0x1000, array step: 0x8

◆  [2/3]

__IO uint32_t { ... } ::MSC_MSAC_W0

Memory Slot Access Control, array offset: 0x1000, array step: 0x8

◆  [3/3]

__IO uint32_t { ... } ::MSC_MSAC_W0

Memory Slot Access Control, array offset: 0x1000, array step: 0x8

◆  [1/3]

__IO uint32_t { ... } ::MSC_MSAC_W1

Memory Slot Access Control, array offset: 0x1004, array step: 0x8

◆ MSC_MSAC_W1 [2/3]

__IO uint32_t XRDC2_Type::MSC_MSAC_W1

Memory Slot Access Control, array offset: 0x1004, array step: 0x8

◆  [3/3]

__IO uint32_t { ... } ::MSC_MSAC_W1

Memory Slot Access Control, array offset: 0x1004, array step: 0x8

◆ MSCR

__IO uint32_t ENET_Type::MSCR

MII Speed Control Register, offset: 0x44

◆ MSR

__IO uint32_t LPI2C_Type::MSR

Master Status Register, offset: 0x14

Master Status, offset: 0x14

◆ MTDR

__O uint32_t LPI2C_Type::MTDR

Master Transmit Data Register, offset: 0x60

Master Transmit Data, offset: 0x60

◆ MULTI_ERR_ADDR

__I uint32_t XECC_Type::MULTI_ERR_ADDR

Multiple Error Address, offset: 0x2C

◆ MULTI_ERR_ADDR_ECC0

__I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC0

Multiple Error Address And ECC code On OCRAM Bank0, offset: 0x8C

◆ MULTI_ERR_ADDR_ECC1

__I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC1

Multiple Error Address And ECC code On OCRAM Bank1, offset: 0x98

◆ MULTI_ERR_ADDR_ECC2

__I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC2

Multiple Error Address And ECC code On OCRAM Bank2, offset: 0xA4

◆ MULTI_ERR_ADDR_ECC3

__I uint32_t MECC_Type::MULTI_ERR_ADDR_ECC3

Multiple Error Address And ECC code On OCRAM Bank3, offset: 0xB0

◆ MULTI_ERR_BIT_FIELD

__I uint32_t XECC_Type::MULTI_ERR_BIT_FIELD

Multiple Error Bit Field, offset: 0x38

◆ MULTI_ERR_DATA

__I uint32_t XECC_Type::MULTI_ERR_DATA

Multiple Error Read Data, offset: 0x30

◆ MULTI_ERR_DATA_HIGH0

__I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH0

HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x94

◆ MULTI_ERR_DATA_HIGH1

__I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH1

HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0xA0

◆ MULTI_ERR_DATA_HIGH2

__I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH2

HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xAC

◆ MULTI_ERR_DATA_HIGH3

__I uint32_t MECC_Type::MULTI_ERR_DATA_HIGH3

HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB8

◆ MULTI_ERR_DATA_LOW0

__I uint32_t MECC_Type::MULTI_ERR_DATA_LOW0

LOW 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x90

◆ MULTI_ERR_DATA_LOW1

__I uint32_t MECC_Type::MULTI_ERR_DATA_LOW1

LOW 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0x9C

◆ MULTI_ERR_DATA_LOW2

__I uint32_t MECC_Type::MULTI_ERR_DATA_LOW2

LOW 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xA8

◆ MULTI_ERR_DATA_LOW3

__I uint32_t MECC_Type::MULTI_ERR_DATA_LOW3

LOW 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB4

◆ MULTI_ERR_ECC

__I uint32_t XECC_Type::MULTI_ERR_ECC

Multiple Error ECC code, offset: 0x34

◆ MUXCR

__IO uint8_t CMP_Type::MUXCR

MUX Control Register, offset: 0x5

◆ NANDCR0

__IO uint32_t SEMC_Type::NANDCR0

NAND control register 0, offset: 0x50

NAND Control Register 0, offset: 0x50

◆ NANDCR1

__IO uint32_t SEMC_Type::NANDCR1

NAND control register 1, offset: 0x54

NAND Control Register 1, offset: 0x54

◆ NANDCR2

__IO uint32_t SEMC_Type::NANDCR2

NAND control register 2, offset: 0x58

NAND Control Register 2, offset: 0x58

◆ NANDCR3

__IO uint32_t SEMC_Type::NANDCR3

NAND control register 3, offset: 0x5C

NAND Control Register 3, offset: 0x5C

◆ NBYTES_MLNO [1/4]

__IO uint32_t DMA_Type::NBYTES_MLNO

TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20

◆  [2/4]

__IO uint32_t { ... } ::NBYTES_MLNO

TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20

◆  [3/4]

__IO uint32_t { ... } ::NBYTES_MLNO

TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20

◆  [4/4]

__IO uint32_t { ... } ::NBYTES_MLNO

TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20

◆ NBYTES_MLOFFNO [1/4]

__IO uint32_t DMA_Type::NBYTES_MLOFFNO

TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20

◆  [2/4]

__IO uint32_t { ... } ::NBYTES_MLOFFNO

TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20

◆  [3/4]

__IO uint32_t { ... } ::NBYTES_MLOFFNO

TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20

◆  [4/4]

__IO uint32_t { ... } ::NBYTES_MLOFFNO

TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20

◆ NBYTES_MLOFFYES [1/4]

__IO uint32_t DMA_Type::NBYTES_MLOFFYES

TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20

◆  [2/4]

__IO uint32_t { ... } ::NBYTES_MLOFFYES

TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20

◆  [3/4]

__IO uint32_t { ... } ::NBYTES_MLOFFYES

TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20

◆  [4/4]

__IO uint32_t { ... } ::NBYTES_MLOFFYES

TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20

◆ NEXT

__IO uint32_t PXP_Type::NEXT

Next Frame Pointer, offset: 0x400

◆ NEXT_BUF

__IO uint32_t LCDIF_Type::NEXT_BUF

LCD Interface Next Buffer Address Register, offset: 0x50

◆ NORCR0

__IO uint32_t SEMC_Type::NORCR0

NOR control register 0, offset: 0x60

NOR Control Register 0, offset: 0x60

◆ NORCR1

__IO uint32_t SEMC_Type::NORCR1

NOR control register 1, offset: 0x64

NOR Control Register 1, offset: 0x64

◆ NORCR2

__IO uint32_t SEMC_Type::NORCR2

NOR control register 2, offset: 0x68

NOR Control Register 2, offset: 0x68

◆ NORCR3 [1/2]

__IO uint32_t SEMC_Type::NORCR3

NOR control register 3, offset: 0x6C

NOR Control Register 3, offset: 0x6C

◆ NORCR3 [2/2]

__IO uint32_t SEMC_Type::NORCR3

NOR Control Register 3, offset: 0x6C

◆ OCR

__IO uint32_t GPT_Type::OCR

GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4

GPT Output Compare Register, array offset: 0x10, array step: 0x4

◆ OCRAM_ECC_MULTI_ERROR_ADDR

__I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_ADDR

OCRAM multi-bit ECC Error Address Register, offset: 0x30

◆ OCRAM_ECC_MULTI_ERROR_DATA_LSB

__I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_DATA_LSB

OCRAM multi-bit ECC Error Data Register, offset: 0x34

◆ OCRAM_ECC_MULTI_ERROR_DATA_MSB

__I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_DATA_MSB

OCRAM multi-bit ECC Error Data Register, offset: 0x38

◆ OCRAM_ECC_MULTI_ERROR_INFO

__I uint32_t FLEXRAM_Type::OCRAM_ECC_MULTI_ERROR_INFO

OCRAM multi-bit ECC Error Information Register, offset: 0x2C

◆ OCRAM_ECC_SINGLE_ERROR_ADDR

__I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_ADDR

OCRAM single-bit ECC Error Address Register, offset: 0x20

◆ OCRAM_ECC_SINGLE_ERROR_DATA_LSB

__I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_DATA_LSB

OCRAM single-bit ECC Error Data Register, offset: 0x24

◆ OCRAM_ECC_SINGLE_ERROR_DATA_MSB

__I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_DATA_MSB

OCRAM single-bit ECC Error Data Register, offset: 0x28

◆ OCRAM_ECC_SINGLE_ERROR_INFO

__I uint32_t FLEXRAM_Type::OCRAM_ECC_SINGLE_ERROR_INFO

OCRAM single-bit ECC Error Information Register, offset: 0x1C

◆ OCRAM_MAGIC_ADDR

__IO uint32_t FLEXRAM_Type::OCRAM_MAGIC_ADDR

OCRAM Magic Address Register, offset: 0x4

◆ OCRAM_PIPELINE_STATUS

__I uint32_t FLEXRAM_Type::OCRAM_PIPELINE_STATUS

OCRAM Pipeline Status register, offset: 0x10C

◆  [1/4]

__IO uint16_t { ... } ::OCTRL

Output Control Register, array offset: 0x22, array step: 0x60

◆ OCTRL [2/4]

__IO uint16_t PWM_Type::OCTRL

Output Control Register, array offset: 0x22, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::OCTRL

Output Control Register, array offset: 0x22, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::OCTRL

Output Control Register, array offset: 0x22, array step: 0x60

◆ OFS

__IO uint32_t ADC_Type::OFS

Offset correction value register, offset: 0x54

◆ OPACR

__IO uint32_t AIPSTZ_Type::OPACR

Off-Platform Peripheral Access Control Registers, offset: 0x40

◆ OPACR1

__IO uint32_t AIPSTZ_Type::OPACR1

Off-Platform Peripheral Access Control Registers, offset: 0x44

◆ OPACR2

__IO uint32_t AIPSTZ_Type::OPACR2

Off-Platform Peripheral Access Control Registers, offset: 0x48

◆ OPACR3

__IO uint32_t AIPSTZ_Type::OPACR3

Off-Platform Peripheral Access Control Registers, offset: 0x4C

◆ OPACR4

__IO uint32_t AIPSTZ_Type::OPACR4

Off-Platform Peripheral Access Control Registers, offset: 0x50

◆ OPD

__IO uint32_t ENET_Type::OPD

Opcode/Pause Duration Register, offset: 0xEC

◆  [1/3]

__IO uint64_t { ... } ::ORBAR_JR

Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3, array offset: 0x10020, array step: 0x10000

◆ ORBAR_JR [2/3]

__IO uint64_t CAAM_Type::ORBAR_JR

Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3, array offset: 0x10020, array step: 0x10000

◆  [3/3]

__IO uint64_t { ... } ::ORBAR_JR

Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3, array offset: 0x10020, array step: 0x10000

◆  [1/3]

__IO uint32_t { ... } ::ORJRR_JR

Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3, array offset: 0x10034, array step: 0x10000

◆ ORJRR_JR [2/3]

__IO uint32_t CAAM_Type::ORJRR_JR

Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3, array offset: 0x10034, array step: 0x10000

◆  [3/3]

__IO uint32_t { ... } ::ORJRR_JR

Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3, array offset: 0x10034, array step: 0x10000

◆  [1/3]

__IO uint32_t { ... } ::ORSFR_JR

Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3, array offset: 0x1003C, array step: 0x10000

◆ ORSFR_JR [2/3]

__IO uint32_t CAAM_Type::ORSFR_JR

Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3, array offset: 0x1003C, array step: 0x10000

◆  [3/3]

__IO uint32_t { ... } ::ORSFR_JR

Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3, array offset: 0x1003C, array step: 0x10000

◆  [1/3]

__IO uint32_t { ... } ::ORSR_JR

Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3, array offset: 0x1002C, array step: 0x10000

◆ ORSR_JR [2/3]

__IO uint32_t CAAM_Type::ORSR_JR

Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3, array offset: 0x1002C, array step: 0x10000

◆  [3/3]

__IO uint32_t { ... } ::ORSR_JR

Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3, array offset: 0x1002C, array step: 0x10000

◆  [1/3]

__IO uint32_t { ... } ::ORWIR_JR

Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3, array offset: 0x10064, array step: 0x10000

◆ ORWIR_JR [2/3]

__IO uint32_t CAAM_Type::ORWIR_JR

Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3, array offset: 0x10064, array step: 0x10000

◆  [3/3]

__IO uint32_t { ... } ::ORWIR_JR

Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3, array offset: 0x10064, array step: 0x10000

◆ OSC_16M_CTRL

__IO uint32_t ANADIG_OSC_Type::OSC_16M_CTRL

16MHz RCOSC Control Register, offset: 0xC0

◆ OSC_24M_CTRL

__IO uint32_t ANADIG_OSC_Type::OSC_24M_CTRL

24MHz OSC Control Register, offset: 0x20

◆ OSC_400M_CTRL0

__I uint32_t ANADIG_OSC_Type::OSC_400M_CTRL0

400MHz RCOSC Control0 Register, offset: 0x40

◆ OSC_400M_CTRL1

__IO uint32_t ANADIG_OSC_Type::OSC_400M_CTRL1

400MHz RCOSC Control1 Register, offset: 0x50

◆ OSC_400M_CTRL2

__IO uint32_t ANADIG_OSC_Type::OSC_400M_CTRL2

400MHz RCOSC Control2 Register, offset: 0x60

◆ OSC_48M_CTRL

__IO uint32_t ANADIG_OSC_Type::OSC_48M_CTRL

48MHz RCOSC Control Register, offset: 0x10

◆ OSC_CONFIG0

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0

XTAL OSC Configuration 0 Register, offset: 0x2A0

◆ OSC_CONFIG0_CLR

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_CLR

XTAL OSC Configuration 0 Register, offset: 0x2A8

◆ OSC_CONFIG0_SET

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_SET

XTAL OSC Configuration 0 Register, offset: 0x2A4

◆ OSC_CONFIG0_TOG

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG0_TOG

XTAL OSC Configuration 0 Register, offset: 0x2AC

◆ OSC_CONFIG1

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1

XTAL OSC Configuration 1 Register, offset: 0x2B0

◆ OSC_CONFIG1_CLR

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_CLR

XTAL OSC Configuration 1 Register, offset: 0x2B8

◆ OSC_CONFIG1_SET

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_SET

XTAL OSC Configuration 1 Register, offset: 0x2B4

◆ OSC_CONFIG1_TOG

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG1_TOG

XTAL OSC Configuration 1 Register, offset: 0x2BC

◆ OSC_CONFIG2

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2

XTAL OSC Configuration 2 Register, offset: 0x2C0

◆ OSC_CONFIG2_CLR

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_CLR

XTAL OSC Configuration 2 Register, offset: 0x2C8

◆ OSC_CONFIG2_SET

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_SET

XTAL OSC Configuration 2 Register, offset: 0x2C4

◆ OSC_CONFIG2_TOG

__IO uint32_t XTALOSC24M_Type::OSC_CONFIG2_TOG

XTAL OSC Configuration 2 Register, offset: 0x2CC

◆ OTFAD1_KEY_CTRL

__IO uint32_t KEY_MANAGER_Type::OTFAD1_KEY_CTRL

CSR OTFAD-1 Key Control, offset: 0x10

◆ OTFAD2_KEY_CTRL

__IO uint32_t KEY_MANAGER_Type::OTFAD2_KEY_CTRL

CSR OTFAD-2 Key Control, offset: 0x18

◆ OTGSC

__IO uint32_t USB_Type::OTGSC

On-The-Go Status & control, offset: 0x1A4

◆ OUT_AS_LRC

__IO uint32_t PXP_Type::OUT_AS_LRC

Alpha Surface Lower Right Coordinate, offset: 0xA0

◆ OUT_AS_ULC

__IO uint32_t PXP_Type::OUT_AS_ULC

Alpha Surface Upper Left Coordinate, offset: 0x90

◆ OUT_BUF

__IO uint32_t PXP_Type::OUT_BUF

Output Frame Buffer Pointer, offset: 0x30

◆ OUT_BUF2

__IO uint32_t PXP_Type::OUT_BUF2

Output Frame Buffer Pointer #2, offset: 0x40

◆ OUT_CTRL

__IO uint32_t PXP_Type::OUT_CTRL

Output Buffer Control Register, offset: 0x20

◆ OUT_CTRL_CLR

__IO uint32_t PXP_Type::OUT_CTRL_CLR

Output Buffer Control Register, offset: 0x28

◆ OUT_CTRL_SET

__IO uint32_t PXP_Type::OUT_CTRL_SET

Output Buffer Control Register, offset: 0x24

◆ OUT_CTRL_TOG

__IO uint32_t PXP_Type::OUT_CTRL_TOG

Output Buffer Control Register, offset: 0x2C

◆ OUT_LRC

__IO uint32_t PXP_Type::OUT_LRC

Output Surface Lower Right Coordinate, offset: 0x60

◆ OUT_PITCH

__IO uint32_t PXP_Type::OUT_PITCH

Output Buffer Pitch, offset: 0x50

◆ OUT_PS_LRC

__IO uint32_t PXP_Type::OUT_PS_LRC

Processed Surface Lower Right Coordinate, offset: 0x80

◆ OUT_PS_ULC

__IO uint32_t PXP_Type::OUT_PS_ULC

Processed Surface Upper Left Coordinate, offset: 0x70

◆ OUT_STATUS

__IO uint32_t OCOTP_Type::OUT_STATUS

8K OTP Memory STATUS Register, offset: 0x90

◆ OUT_STATUS_CLR

__IO uint32_t OCOTP_Type::OUT_STATUS_CLR

8K OTP Memory STATUS Register, offset: 0x98

◆ OUT_STATUS_SET

__IO uint32_t OCOTP_Type::OUT_STATUS_SET

8K OTP Memory STATUS Register, offset: 0x94

◆ OUT_STATUS_TOG

__IO uint32_t OCOTP_Type::OUT_STATUS_TOG

8K OTP Memory STATUS Register, offset: 0x9C

◆ OUTEN

__IO uint16_t PWM_Type::OUTEN

Output Enable Register, offset: 0x180

◆ PAC_PDAC_W0 [1/3]

__IO uint32_t XRDC2_Type::PAC_PDAC_W0

Peripheral Domain Access Control, array offset: 0x4000, array step: index*0x800, index2*0x8

◆  [2/3]

__IO uint32_t { ... } ::PAC_PDAC_W0

Peripheral Domain Access Control, array offset: 0x4000, array step: index*0x800, index2*0x8

◆  [3/3]

__IO uint32_t { ... } ::PAC_PDAC_W0

Peripheral Domain Access Control, array offset: 0x4000, array step: index*0x800, index2*0x8

◆  [1/3]

__IO uint32_t { ... } ::PAC_PDAC_W1

Peripheral Domain Access Control, array offset: 0x4004, array step: index*0x800, index2*0x8

◆ PAC_PDAC_W1 [2/3]

__IO uint32_t XRDC2_Type::PAC_PDAC_W1

Peripheral Domain Access Control, array offset: 0x4004, array step: index*0x800, index2*0x8

◆  [3/3]

__IO uint32_t { ... } ::PAC_PDAC_W1

Peripheral Domain Access Control, array offset: 0x4004, array step: index*0x800, index2*0x8

◆ PACKET0

__I uint32_t DCP_Type::PACKET0

DCP work packet 0 status register, offset: 0x80

◆ PACKET1

__I uint32_t DCP_Type::PACKET1

DCP work packet 1 status register, offset: 0x90

◆ PACKET2

__I uint32_t DCP_Type::PACKET2

DCP work packet 2 status register, offset: 0xA0

◆ PACKET3

__I uint32_t DCP_Type::PACKET3

DCP work packet 3 status register, offset: 0xB0

◆ PACKET4

__I uint32_t DCP_Type::PACKET4

DCP work packet 4 status register, offset: 0xC0

◆ PACKET5

__I uint32_t DCP_Type::PACKET5

DCP work packet 5 status register, offset: 0xD0

◆ PACKET6

__I uint32_t DCP_Type::PACKET6

DCP work packet 6 status register, offset: 0xE0

◆ PAGE0_SDID

__IO uint32_t CAAM_Type::PAGE0_SDID

Page 0 SDID Register, offset: 0x8

◆ PAGETABLE

__IO uint32_t DCP_Type::PAGETABLE

DCP page table register, offset: 0x420

◆ PALR

__IO uint32_t ENET_Type::PALR

Physical Address Lower Register, offset: 0xE4

◆ PARAM [1/9]

__I uint32_t FLEXIO_Type::PARAM

Parameter Register, offset: 0x4

◆ PARAM [2/9]

__I uint32_t I2S_Type::PARAM

Parameter Register, offset: 0x4

Parameter, offset: 0x4

◆ PARAM [3/9]

__I uint32_t LPI2C_Type::PARAM

Parameter Register, offset: 0x4

Parameter, offset: 0x4

◆ PARAM [4/9]

__I uint32_t LPSPI_Type::PARAM

Parameter Register, offset: 0x4

Parameter, offset: 0x4

◆ PARAM [5/9]

__I uint32_t LPUART_Type::PARAM

Parameter Register, offset: 0x4

◆ PARAM [6/9]

__I uint32_t ADC_Type::PARAM

Parameter Register, offset: 0x4

◆ PARAM [7/9]

__I uint32_t CMP_Type::PARAM

Parameter Register, offset: 0x4

◆ PARAM [8/9]

__I uint32_t DAC_Type::PARAM

Parameter Register, offset: 0x4

◆ PARAM [9/9]

__I uint32_t EMVSIM_Type::PARAM

Parameter Register, offset: 0x4

◆ PAUR

__IO uint32_t ENET_Type::PAUR

Physical Address Upper Register, offset: 0xE8

◆ PAUSE

__IO uint32_t ADC_Type::PAUSE

LPADC Pause Register, offset: 0x24

◆ PBSL

__IO uint32_t CAAM_Type::PBSL

Peak Bandwidth Smoothing Limit Register, offset: 0x220

◆ PC_BLK_DEC

__IO uint32_t IEE_Type::PC_BLK_DEC

Performance Counter, Number of AES Block Decryptions, offset: 0x44

◆ PC_BLK_ENC

__IO uint32_t IEE_Type::PC_BLK_ENC

Performance Counter, Number of AES Block Encryptions, offset: 0x40

◆ PC_M_LT

__IO uint32_t IEE_Type::PC_M_LT

Performance Counter, AES Master Latency Threshold, offset: 0x24

◆ PC_M_MBR

__IO uint32_t IEE_Type::PC_M_MBR

Performance Counter, Number of AXI Master Merge Buffer Read Transactions, offset: 0x64

◆ PC_MR_TBC_L

__IO uint32_t IEE_Type::PC_MR_TBC_L

Performance Counter, Lower Master Read Transactions Byte Count, offset: 0x84

◆ PC_MR_TBC_U

__IO uint32_t IEE_Type::PC_MR_TBC_U

Performance Counter, Upper Master Read Transactions Byte Count, offset: 0x80

◆ PC_MR_TLAT_L

__IO uint32_t IEE_Type::PC_MR_TLAT_L

Performance Counter, Lower Master Read Latency Count, offset: 0xB4

◆ PC_MR_TLAT_U

__IO uint32_t IEE_Type::PC_MR_TLAT_U

Performance Counter, Upper Master Read Latency Count, offset: 0xB0

◆ PC_MR_TLGTT

__IO uint32_t IEE_Type::PC_MR_TLGTT

Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold, offset: 0x98

◆ PC_MR_TRANS

__IO uint32_t IEE_Type::PC_MR_TRANS

Performance Counter, Number of AXI Master Read Transactions, offset: 0x58

◆ PC_MW_TBC_L

__IO uint32_t IEE_Type::PC_MW_TBC_L

Performance Counter, Lower Master Write Transactions Byte Count, offset: 0x8C

◆ PC_MW_TBC_U

__IO uint32_t IEE_Type::PC_MW_TBC_U

Performance Counter, Upper Master Write Transactions Byte Count, offset: 0x88

◆ PC_MW_TLAT_L

__IO uint32_t IEE_Type::PC_MW_TLAT_L

Performance Counter, Lower Master Write Latency Count, offset: 0xBC

◆ PC_MW_TLAT_U

__IO uint32_t IEE_Type::PC_MW_TLAT_U

Performance Counter, Upper Master Write Latency Count, offset: 0xB8

◆ PC_MW_TLGTT

__IO uint32_t IEE_Type::PC_MW_TLGTT

Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold, offset: 0x9C

◆ PC_MW_TRANS

__IO uint32_t IEE_Type::PC_MW_TRANS

Performance Counter, Number of AXI Master Write Transactions, offset: 0x5C

◆ PC_S_LT

__IO uint32_t IEE_Type::PC_S_LT

Performance Counter, AES Slave Latency Threshold Value, offset: 0x20

◆ PC_SR_TBC_L

__IO uint32_t IEE_Type::PC_SR_TBC_L

Performance Counter, Lower Slave Read Transactions Byte Count, offset: 0x74

◆ PC_SR_TBC_U

__IO uint32_t IEE_Type::PC_SR_TBC_U

Performance Counter, Upper Slave Read Transactions Byte Count, offset: 0x70

◆ PC_SR_TLAT_L

__IO uint32_t IEE_Type::PC_SR_TLAT_L

Performance Counter, Lower Slave Read Latency Count, offset: 0xA4

◆ PC_SR_TLAT_U

__IO uint32_t IEE_Type::PC_SR_TLAT_U

Performance Counter, Upper Slave Read Latency Count, offset: 0xA0

◆ PC_SR_TLGTT

__IO uint32_t IEE_Type::PC_SR_TLGTT

Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold, offset: 0x90

◆ PC_SR_TNRT_L

__IO uint32_t IEE_Type::PC_SR_TNRT_L

Performance Counter, Lower Slave Read Total Non-Responding Time, offset: 0xC4

◆ PC_SR_TNRT_U

__IO uint32_t IEE_Type::PC_SR_TNRT_U

Performance Counter, Upper Slave Read Total Non-Responding Time, offset: 0xC0

◆ PC_SR_TRANS

__IO uint32_t IEE_Type::PC_SR_TRANS

Performance Counter, Number of AXI Slave Read Transactions, offset: 0x50

◆ PC_SW_TBC_L

__IO uint32_t IEE_Type::PC_SW_TBC_L

Performance Counter, Lower Slave Write Transactions Byte Count, offset: 0x7C

◆ PC_SW_TBC_U

__IO uint32_t IEE_Type::PC_SW_TBC_U

Performance Counter, Upper Slave Write Transactions Byte Count, offset: 0x78

◆ PC_SW_TLAT_L

__IO uint32_t IEE_Type::PC_SW_TLAT_L

Performance Counter, Lower Slave Write Latency Count, offset: 0xAC

◆ PC_SW_TLAT_U

__IO uint32_t IEE_Type::PC_SW_TLAT_U

Performance Counter, Upper Slave Write Latency Count, offset: 0xA8

◆ PC_SW_TLGTT

__IO uint32_t IEE_Type::PC_SW_TLGTT

Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold, offset: 0x94

◆ PC_SW_TNRT_L

__IO uint32_t IEE_Type::PC_SW_TNRT_L

Performance Counter, Lower Slave Write Total Non-Responding Time, offset: 0xCC

◆ PC_SW_TNRT_U

__IO uint32_t IEE_Type::PC_SW_TNRT_U

Performance Counter, Upper Slave Write Total Non-Responding Time, offset: 0xC8

◆ PC_SW_TRANS

__IO uint32_t IEE_Type::PC_SW_TRANS

Performance Counter, Number of AXI Slave Write Transactions, offset: 0x54

◆ PCCCR

__IO uint32_t LMEM_Type::PCCCR

PC bus Cache control register, offset: 0x0

◆ PCCCVR

__IO uint32_t LMEM_Type::PCCCVR

PC bus Cache read/write value register, offset: 0xC

◆ PCCLCR

__IO uint32_t LMEM_Type::PCCLCR

PC bus Cache line control register, offset: 0x4

◆ PCCSAR

__IO uint32_t LMEM_Type::PCCSAR

PC bus Cache search address register, offset: 0x8

◆ PCSR

__IO uint32_t EMVSIM_Type::PCSR

Port Control and Status Register, offset: 0x28

◆ PCT

__I uint16_t MCM_Type::PCT

Processor core type, offset: 0x2

◆ PD_PLL

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::PD_PLL

PD_PLL, offset: 0x1C

◆ PD_TX

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::PD_TX

PD_TX, offset: 0x0

◆ PDAP

__IO uint32_t RDC_Type::PDAP

Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4

◆ PDI_PARA

__IO uint32_t LCDIFV2_Type::PDI_PARA

Parallel Data Interface Parameter Register, offset: 0x40

◆ PDN

__IO uint32_t OCOTP_Type::PDN

OTP Controller PDN Register, offset: 0x10

◆ PENDING_STAT

__I uint32_t MECC_Type::PENDING_STAT

Pending Status, offset: 0x104

◆ PERIODICLISTBASE [1/4]

__IO uint32_t USB_Type::PERIODICLISTBASE

Frame List Base Address, offset: 0x154

◆  [2/4]

__IO uint32_t { ... } ::PERIODICLISTBASE

Frame List Base Address, offset: 0x154

◆  [3/4]

__IO uint32_t { ... } ::PERIODICLISTBASE

Frame List Base Address, offset: 0x154

◆  [4/4]

__IO uint32_t { ... } ::PERIODICLISTBASE

Frame List Base Address, offset: 0x154

◆ PERSISTENT

__IO uint32_t CDOG_Type::PERSISTENT

Persistent Data Storage, offset: 0x1C

◆ PFD_480

__IO uint32_t CCM_ANALOG_Type::PFD_480

480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0

◆ PFD_480_CLR

__IO uint32_t CCM_ANALOG_Type::PFD_480_CLR

480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8

◆ PFD_480_SET

__IO uint32_t CCM_ANALOG_Type::PFD_480_SET

480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4

◆ PFD_480_TOG

__IO uint32_t CCM_ANALOG_Type::PFD_480_TOG

480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC

◆ PFD_528

__IO uint32_t CCM_ANALOG_Type::PFD_528

528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100

◆ PFD_528_CLR

__IO uint32_t CCM_ANALOG_Type::PFD_528_CLR

528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108

◆ PFD_528_SET

__IO uint32_t CCM_ANALOG_Type::PFD_528_SET

528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104

◆ PFD_528_TOG

__IO uint32_t CCM_ANALOG_Type::PFD_528_TOG

528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C

◆  [1/4]

__IO uint32_t { ... } ::PIGEON_0

Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40

◆ PIGEON_0 [2/4]

__IO uint32_t LCDIF_Type::PIGEON_0

Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40

◆  [3/4]

__IO uint32_t { ... } ::PIGEON_0

Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40

◆  [4/4]

__IO uint32_t { ... } ::PIGEON_0

Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40

◆ PIGEON_1 [1/4]

__IO uint32_t LCDIF_Type::PIGEON_1

Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40

◆  [2/4]

__IO uint32_t { ... } ::PIGEON_1

Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40

◆  [3/4]

__IO uint32_t { ... } ::PIGEON_1

Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40

◆  [4/4]

__IO uint32_t { ... } ::PIGEON_1

Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40

◆ PIGEON_2 [1/4]

__IO uint32_t LCDIF_Type::PIGEON_2

Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40

◆  [2/4]

__IO uint32_t { ... } ::PIGEON_2

Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40

◆  [3/4]

__IO uint32_t { ... } ::PIGEON_2

Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40

◆  [4/4]

__IO uint32_t { ... } ::PIGEON_2

Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40

◆ PIGEONCTRL0

__IO uint32_t LCDIF_Type::PIGEONCTRL0

LCDIF Pigeon Mode Control0 Register, offset: 0x380

◆ PIGEONCTRL0_CLR

__IO uint32_t LCDIF_Type::PIGEONCTRL0_CLR

LCDIF Pigeon Mode Control0 Register, offset: 0x388

◆ PIGEONCTRL0_SET

__IO uint32_t LCDIF_Type::PIGEONCTRL0_SET

LCDIF Pigeon Mode Control0 Register, offset: 0x384

◆ PIGEONCTRL0_TOG

__IO uint32_t LCDIF_Type::PIGEONCTRL0_TOG

LCDIF Pigeon Mode Control0 Register, offset: 0x38C

◆ PIGEONCTRL1

__IO uint32_t LCDIF_Type::PIGEONCTRL1

LCDIF Pigeon Mode Control1 Register, offset: 0x390

◆ PIGEONCTRL1_CLR

__IO uint32_t LCDIF_Type::PIGEONCTRL1_CLR

LCDIF Pigeon Mode Control1 Register, offset: 0x398

◆ PIGEONCTRL1_SET

__IO uint32_t LCDIF_Type::PIGEONCTRL1_SET

LCDIF Pigeon Mode Control1 Register, offset: 0x394

◆ PIGEONCTRL1_TOG

__IO uint32_t LCDIF_Type::PIGEONCTRL1_TOG

LCDIF Pigeon Mode Control1 Register, offset: 0x39C

◆ PIGEONCTRL2

__IO uint32_t LCDIF_Type::PIGEONCTRL2

LCDIF Pigeon Mode Control2 Register, offset: 0x3A0

◆ PIGEONCTRL2_CLR

__IO uint32_t LCDIF_Type::PIGEONCTRL2_CLR

LCDIF Pigeon Mode Control2 Register, offset: 0x3A8

◆ PIGEONCTRL2_SET

__IO uint32_t LCDIF_Type::PIGEONCTRL2_SET

LCDIF Pigeon Mode Control2 Register, offset: 0x3A4

◆ PIGEONCTRL2_TOG

__IO uint32_t LCDIF_Type::PIGEONCTRL2_TOG

LCDIF Pigeon Mode Control2 Register, offset: 0x3AC

◆ PIN

__I uint32_t FLEXIO_Type::PIN

Pin State Register, offset: 0xC

◆ PINCFG

__IO uint32_t LPUART_Type::PINCFG

LPUART Pin Configuration Register, offset: 0xC

◆ PIPE_ECC_EN

__IO uint32_t MECC_Type::PIPE_ECC_EN

OCRAM Pipeline And ECC Enable, offset: 0x100

◆ PIXEL_FIFO_SEND_LEVEL

__IO uint32_t DSI_HOST_DPI_INTFC_Type::PIXEL_FIFO_SEND_LEVEL

PIXEL_FIFO_SEND_LEVEL, offset: 0x4

◆ PIXEL_FORMAT

__IO uint32_t DSI_HOST_DPI_INTFC_Type::PIXEL_FORMAT

PIXEL_FORMAT, offset: 0xC

◆ PIXEL_PAYLOAD_SIZE

__IO uint32_t DSI_HOST_DPI_INTFC_Type::PIXEL_PAYLOAD_SIZE

PEXEL_PAYLOAD_SIZE, offset: 0x0

◆ PKRCNT10

__I uint32_t TRNG_Type::PKRCNT10

Statistical Check Poker Count 1 and 0 Register, offset: 0x80

◆ PKRCNT32

__I uint32_t TRNG_Type::PKRCNT32

Statistical Check Poker Count 3 and 2 Register, offset: 0x84

◆ PKRCNT54

__I uint32_t TRNG_Type::PKRCNT54

Statistical Check Poker Count 5 and 4 Register, offset: 0x88

◆ PKRCNT76

__I uint32_t TRNG_Type::PKRCNT76

Statistical Check Poker Count 7 and 6 Register, offset: 0x8C

◆ PKRCNT98

__I uint32_t TRNG_Type::PKRCNT98

Statistical Check Poker Count 9 and 8 Register, offset: 0x90

◆ PKRCNTBA

__I uint32_t TRNG_Type::PKRCNTBA

Statistical Check Poker Count B and A Register, offset: 0x94

◆ PKRCNTDC

__I uint32_t TRNG_Type::PKRCNTDC

Statistical Check Poker Count D and C Register, offset: 0x98

◆ PKRCNTFE

__I uint32_t TRNG_Type::PKRCNTFE

Statistical Check Poker Count F and E Register, offset: 0x9C

◆  [1/2]

__IO uint32_t { ... } ::PKRMAX

Poker Maximum Limit Register, offset: 0xC

◆ PKRMAX [2/2]

__IO uint32_t TRNG_Type::PKRMAX

Poker Maximum Limit Register, offset: 0xC

◆ PKRRNG

__IO uint32_t TRNG_Type::PKRRNG

Poker Range Register, offset: 0x8

◆  [1/2]

__I uint32_t { ... } ::PKRSQ

Poker Square Calculation Result Register, offset: 0xC

◆ PKRSQ [2/2]

__I uint32_t TRNG_Type::PKRSQ

Poker Square Calculation Result Register, offset: 0xC

◆ PKT_CONTROL

__IO uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_CONTROL

PKT_CONTROL, offset: 0x4

◆ PKT_FIFO_RD_LEVEL

__I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_FIFO_RD_LEVEL

PKT_FIFO_RD_LEVEL, offset: 0x14

◆ PKT_FIFO_WR_LEVEL

__I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_FIFO_WR_LEVEL

PKT_FIFO_WR_LEVEL, offset: 0x10

◆ PKT_RX_PAYLOAD

__I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_RX_PAYLOAD

PKT_RX_PAYLOAD, offset: 0x18

◆ PKT_RX_PKT_HEADER

__I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_RX_PKT_HEADER

PKT_RX_PKT_HEADER, offset: 0x1C

◆ PKT_STATUS

__I uint32_t DSI_HOST_APB_PKT_IF_Type::PKT_STATUS

PKT_STATUS, offset: 0xC

◆ PLAMC

__I uint16_t MCM_Type::PLAMC

Crossbar Switch (AXBS) Master Configuration, offset: 0xA

◆ PLASC

__I uint16_t MCM_Type::PLASC

Crossbar Switch (AXBS) Slave Configuration, offset: 0x8

◆ PLL_ARM

__IO uint32_t CCM_ANALOG_Type::PLL_ARM

Analog ARM PLL control Register, offset: 0x0

◆ PLL_ARM_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_ARM_CLR

Analog ARM PLL control Register, offset: 0x8

◆ PLL_ARM_SET

__IO uint32_t CCM_ANALOG_Type::PLL_ARM_SET

Analog ARM PLL control Register, offset: 0x4

◆ PLL_ARM_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_ARM_TOG

Analog ARM PLL control Register, offset: 0xC

◆ PLL_AUDIO

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO

Analog Audio PLL control Register, offset: 0x70

◆ PLL_AUDIO_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_CLR

Analog Audio PLL control Register, offset: 0x78

◆ PLL_AUDIO_CTRL

__IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_CTRL

PLL_AUDIO_CTRL_REGISTER, offset: 0x300

◆ PLL_AUDIO_DENOM

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_DENOM

Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90

◆ PLL_AUDIO_DENOMINATOR

__IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_DENOMINATOR

PLL_AUDIO_DENOMINATOR_REGISTER, offset: 0x320

◆ PLL_AUDIO_DIV_SELECT

__IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_DIV_SELECT

PLL_AUDIO_DIV_SELECT_REGISTER, offset: 0x340

◆ PLL_AUDIO_NUM

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_NUM

Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80

◆ PLL_AUDIO_NUMERATOR

__IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_NUMERATOR

PLL_AUDIO_NUMERATOR_REGISTER, offset: 0x330

◆ PLL_AUDIO_SET

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_SET

Analog Audio PLL control Register, offset: 0x74

◆ PLL_AUDIO_SS

__IO uint32_t ANADIG_PLL_Type::PLL_AUDIO_SS

PLL_AUDIO_SS_REGISTER, offset: 0x310

◆ PLL_AUDIO_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_AUDIO_TOG

Analog Audio PLL control Register, offset: 0x7C

◆ PLL_ENET

__IO uint32_t CCM_ANALOG_Type::PLL_ENET

Analog ENET PLL Control Register, offset: 0xE0

◆ PLL_ENET_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_ENET_CLR

Analog ENET PLL Control Register, offset: 0xE8

◆ PLL_ENET_SET

__IO uint32_t CCM_ANALOG_Type::PLL_ENET_SET

Analog ENET PLL Control Register, offset: 0xE4

◆ PLL_ENET_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_ENET_TOG

Analog ENET PLL Control Register, offset: 0xEC

◆ PLL_LDO_STBY_EN_SP

__IO uint32_t ANADIG_PMU_Type::PLL_LDO_STBY_EN_SP

PLL_LDO_STBY_EN_SP_REGISTER, offset: 0x740

◆ PLL_SIC

__IO uint32_t USBPHY_Type::PLL_SIC

USB PHY PLL Control/Status Register, offset: 0xA0

◆ PLL_SIC_CLR

__IO uint32_t USBPHY_Type::PLL_SIC_CLR

USB PHY PLL Control/Status Register, offset: 0xA8

◆ PLL_SIC_SET

__IO uint32_t USBPHY_Type::PLL_SIC_SET

USB PHY PLL Control/Status Register, offset: 0xA4

◆ PLL_SIC_TOG

__IO uint32_t USBPHY_Type::PLL_SIC_TOG

USB PHY PLL Control/Status Register, offset: 0xAC

◆ PLL_SYS

__IO uint32_t CCM_ANALOG_Type::PLL_SYS

Analog System PLL Control Register, offset: 0x30

◆ PLL_SYS_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_CLR

Analog System PLL Control Register, offset: 0x38

◆ PLL_SYS_DENOM

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_DENOM

Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60

◆ PLL_SYS_NUM

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_NUM

Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50

◆ PLL_SYS_SET

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_SET

Analog System PLL Control Register, offset: 0x34

◆ PLL_SYS_SS

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_SS

528MHz System PLL Spread Spectrum Register, offset: 0x40

◆ PLL_SYS_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_SYS_TOG

Analog System PLL Control Register, offset: 0x3C

◆ PLL_USB1

__IO uint32_t CCM_ANALOG_Type::PLL_USB1

Analog USB1 480MHz PLL Control Register, offset: 0x10

◆ PLL_USB1_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_USB1_CLR

Analog USB1 480MHz PLL Control Register, offset: 0x18

◆ PLL_USB1_SET

__IO uint32_t CCM_ANALOG_Type::PLL_USB1_SET

Analog USB1 480MHz PLL Control Register, offset: 0x14

◆ PLL_USB1_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_USB1_TOG

Analog USB1 480MHz PLL Control Register, offset: 0x1C

◆ PLL_USB2

__IO uint32_t CCM_ANALOG_Type::PLL_USB2

Analog USB2 480MHz PLL Control Register, offset: 0x20

◆ PLL_USB2_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_USB2_CLR

Analog USB2 480MHz PLL Control Register, offset: 0x28

◆ PLL_USB2_SET

__IO uint32_t CCM_ANALOG_Type::PLL_USB2_SET

Analog USB2 480MHz PLL Control Register, offset: 0x24

◆ PLL_USB2_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_USB2_TOG

Analog USB2 480MHz PLL Control Register, offset: 0x2C

◆ PLL_VIDEO

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO

Analog Video PLL control Register, offset: 0xA0

◆ PLL_VIDEO_CLR

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_CLR

Analog Video PLL control Register, offset: 0xA8

◆ PLL_VIDEO_CTRL

__IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_CTRL

PLL_VIDEO_CTRL_REGISTER, offset: 0x350

◆ PLL_VIDEO_DENOM

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_DENOM

Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0

◆ PLL_VIDEO_DENOMINATOR

__IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_DENOMINATOR

PLL_VIDEO_DENOMINATOR_REGISTER, offset: 0x370

◆ PLL_VIDEO_DIV_SELECT

__IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_DIV_SELECT

PLL_VIDEO_DIV_SELECT_REGISTER, offset: 0x390

◆ PLL_VIDEO_NUM

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_NUM

Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0

◆ PLL_VIDEO_NUMERATOR

__IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_NUMERATOR

PLL_VIDEO_NUMERATOR_REGISTER, offset: 0x380

◆ PLL_VIDEO_SET

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_SET

Analog Video PLL control Register, offset: 0xA4

◆ PLL_VIDEO_SS

__IO uint32_t ANADIG_PLL_Type::PLL_VIDEO_SS

PLL_VIDEO_SS_REGISTER, offset: 0x360

◆ PLL_VIDEO_TOG

__IO uint32_t CCM_ANALOG_Type::PLL_VIDEO_TOG

Analog Video PLL control Register, offset: 0xAC

◆ PLREV

__I uint16_t MCM_Type::PLREV

SoC-defined platform revision, offset: 0x0

◆ PMU_BIAS_CTRL

__IO uint32_t ANADIG_PMU_Type::PMU_BIAS_CTRL

PMU_BIAS_CTRL_REGISTER, offset: 0x550

◆ PMU_BIAS_CTRL2

__IO uint32_t ANADIG_PMU_Type::PMU_BIAS_CTRL2

PMU_BIAS_CTRL2_REGISTER, offset: 0x560

◆ PMU_LDO_LPSR_ANA

__IO uint32_t ANADIG_LDO_SNVS_Type::PMU_LDO_LPSR_ANA

PMU_LDO_LPSR_ANA_REGISTER, offset: 0x510

◆ PMU_LDO_LPSR_DIG

__IO uint32_t ANADIG_LDO_SNVS_Type::PMU_LDO_LPSR_DIG

PMU_LDO_LPSR_DIG_REGISTER, offset: 0x530

◆ PMU_LDO_LPSR_DIG_2

__IO uint32_t ANADIG_LDO_SNVS_Type::PMU_LDO_LPSR_DIG_2

PMU_LDO_LPSR_DIG_2_REGISTER, offset: 0x520

◆ PMU_LDO_PLL

__IO uint32_t ANADIG_PMU_Type::PMU_LDO_PLL

PMU_LDO_PLL_REGISTER, offset: 0x500

◆ PMU_LDO_SNVS_DIG

__IO uint32_t ANADIG_LDO_SNVS_DIG_Type::PMU_LDO_SNVS_DIG

PMU_LDO_SNVS_DIG_REGISTER, offset: 0x540

◆ PMU_POWER_DETECT_CTRL

__IO uint32_t ANADIG_PMU_Type::PMU_POWER_DETECT_CTRL

PMU_POWER_DETECT_CTRL_REGISTER, offset: 0x580

◆ PMU_REF_CTRL

__IO uint32_t ANADIG_PMU_Type::PMU_REF_CTRL

PMU_REF_CTRL_REGISTER, offset: 0x570

◆ PORTER_DUFF_CTRL

__IO uint32_t PXP_Type::PORTER_DUFF_CTRL

PXP Alpha Engine A Control Register., offset: 0x440

◆ PORTSC1

__IO uint32_t USB_Type::PORTSC1

Port Status & Control, offset: 0x184

◆ POSD

__IO uint16_t ENC_Type::POSD

Position Difference Counter Register, offset: 0x6

◆ POSDH

__I uint16_t ENC_Type::POSDH

Position Difference Hold Register, offset: 0x8

◆ POSDPER

__I uint16_t ENC_Type::POSDPER

Position Difference Period Counter Register, offset: 0x2C

◆ POSDPERBFR

__I uint16_t ENC_Type::POSDPERBFR

Position Difference Period Buffer Register, offset: 0x2E

◆ POSDPERH

__I uint16_t ENC_Type::POSDPERH

Position Difference Period Hold Register, offset: 0x30

◆ POWER

__IO uint32_t PXP_Type::POWER

PXP Power Control Register, offset: 0x320

◆ PPC_AUTHEN_CTRL

__IO uint32_t PGMC_PPC_Type::PPC_AUTHEN_CTRL

PPC Authentication Control, offset: 0x4

◆ PPC_MODE

__IO uint32_t PGMC_PPC_Type::PPC_MODE

PPC Mode, offset: 0x10

◆ PPC_STBY_CM_CTRL

__IO uint32_t PGMC_PPC_Type::PPC_STBY_CM_CTRL

PPC standby CPU mode control, offset: 0x14

◆ PPC_STBY_SP_CTRL

__IO uint32_t PGMC_PPC_Type::PPC_STBY_SP_CTRL

PPC standby Setpoint control, offset: 0x18

◆ PPI_ERRCONTROL

__I uint32_t MIPI_CSI2RX_Type::PPI_ERRCONTROL

ErrControl Status Register, offset: 0x128

◆ PPI_ERRESC

__I uint32_t MIPI_CSI2RX_Type::PPI_ERRESC

ErrEsc Status Register, offset: 0x120

◆ PPI_ERRSOT_HS

__I uint32_t MIPI_CSI2RX_Type::PPI_ERRSOT_HS

ERRSot HS Status Register, offset: 0x118

◆ PPI_ERRSOTSYNC_HS

__I uint32_t MIPI_CSI2RX_Type::PPI_ERRSOTSYNC_HS

ErrSotSync HS Status Register, offset: 0x11C

◆ PPI_ERRSYNCESC

__I uint32_t MIPI_CSI2RX_Type::PPI_ERRSYNCESC

ErrSyncEsc Status Register, offset: 0x124

◆ PR

__IO uint32_t GPT_Type::PR

GPT Prescaler Register, offset: 0x4

◆ PRE_CHARGE_TIME

__IO uint32_t TSC_Type::PRE_CHARGE_TIME

Pre-charge Time, offset: 0x10

◆ PRES_STATE

__I uint32_t USDHC_Type::PRES_STATE

Present State, offset: 0x24

◆ PROT_CTRL

__IO uint32_t USDHC_Type::PROT_CTRL

Protocol Control, offset: 0x28

◆ PS_BACKGROUND

__IO uint32_t PXP_Type::PS_BACKGROUND

PS Background Color, offset: 0x100

◆ PS_BUF

__IO uint32_t PXP_Type::PS_BUF

PS Input Buffer Address, offset: 0xC0

◆ PS_CLRKEYHIGH

__IO uint32_t PXP_Type::PS_CLRKEYHIGH

PS Color Key High, offset: 0x140

◆ PS_CLRKEYLOW

__IO uint32_t PXP_Type::PS_CLRKEYLOW

PS Color Key Low, offset: 0x130

◆ PS_CTRL

__IO uint32_t PXP_Type::PS_CTRL

Processed Surface (PS) Control Register, offset: 0xB0

◆ PS_CTRL_CLR

__IO uint32_t PXP_Type::PS_CTRL_CLR

Processed Surface (PS) Control Register, offset: 0xB8

◆ PS_CTRL_SET

__IO uint32_t PXP_Type::PS_CTRL_SET

Processed Surface (PS) Control Register, offset: 0xB4

◆ PS_CTRL_TOG

__IO uint32_t PXP_Type::PS_CTRL_TOG

Processed Surface (PS) Control Register, offset: 0xBC

◆ PS_OFFSET

__IO uint32_t PXP_Type::PS_OFFSET

PS Scale Offset Register, offset: 0x120

◆ PS_PITCH

__IO uint32_t PXP_Type::PS_PITCH

Processed Surface Pitch, offset: 0xF0

◆ PS_SCALE

__IO uint32_t PXP_Type::PS_SCALE

PS Scale Factor Register, offset: 0x110

◆ PS_UBUF

__IO uint32_t PXP_Type::PS_UBUF

PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0

◆ PS_VBUF

__IO uint32_t PXP_Type::PS_VBUF

PS V/Cr Input Buffer Address, offset: 0xE0

◆ PSCCR

__IO uint32_t LMEM_Type::PSCCR

PS bus Cache control register, offset: 0x800

◆ PSCCVR

__IO uint32_t LMEM_Type::PSCCVR

PS bus Cache read/write value register, offset: 0x80C

◆ PSCLCR

__IO uint32_t LMEM_Type::PSCLCR

PS bus Cache line control register, offset: 0x804

◆ PSCSAR

__IO uint32_t LMEM_Type::PSCSAR

PS bus Cache search address register, offset: 0x808

◆ PSR

__I uint32_t GPIO_Type::PSR

GPIO pad status register, offset: 0x8

◆ PTR

__I uint32_t DAC_Type::PTR

DAC FIFO Pointer Register, offset: 0x10

◆ PUF_KEY_CTRL

__IO uint32_t KEY_MANAGER_Type::PUF_KEY_CTRL

CSR PUF Key Control, offset: 0x30

◆ PWD

__IO uint32_t USBPHY_Type::PWD

USB PHY Power-Down Register, offset: 0x0

◆ PWD_CLR

__IO uint32_t USBPHY_Type::PWD_CLR

USB PHY Power-Down Register, offset: 0x8

◆ PWD_SET

__IO uint32_t USBPHY_Type::PWD_SET

USB PHY Power-Down Register, offset: 0x4

◆ PWD_TOG

__IO uint32_t USBPHY_Type::PWD_TOG

USB PHY Power-Down Register, offset: 0xC

◆ PWRCTRL

__IO uint32_t PUF_Type::PWRCTRL

PUF Power Control Of RAM, offset: 0x108

◆ PX_SDID_JR [1/3]

__I uint32_t CAAM_Type::PX_SDID_JR

Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10

◆  [2/3]

__I uint32_t { ... } ::PX_SDID_JR

Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10

◆  [3/3]

__I uint32_t { ... } ::PX_SDID_JR

Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10

◆ PX_SDID_PG0 [1/3]

__I uint32_t CAAM_Type::PX_SDID_PG0

Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10

◆  [2/3]

__I uint32_t { ... } ::PX_SDID_PG0

Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10

◆  [3/3]

__I uint32_t { ... } ::PX_SDID_PG0

Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10

◆ PX_SMAG1_JR [1/3]

__IO uint32_t CAAM_Type::PX_SMAG1_JR

Secure Memory Access Group Registers, array offset: 0x10A0C, array step: index*0x10000, index2*0x10

◆  [2/3]

__IO uint32_t { ... } ::PX_SMAG1_JR

Secure Memory Access Group Registers, array offset: 0x10A0C, array step: index*0x10000, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::PX_SMAG1_JR

Secure Memory Access Group Registers, array offset: 0x10A0C, array step: index*0x10000, index2*0x10

◆ PX_SMAG1_PG0 [1/3]

__IO uint32_t CAAM_Type::PX_SMAG1_PG0

Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10

◆  [2/3]

__IO uint32_t { ... } ::PX_SMAG1_PG0

Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::PX_SMAG1_PG0

Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10

◆ PX_SMAG2_JR [1/3]

__IO uint32_t CAAM_Type::PX_SMAG2_JR

Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10

◆  [2/3]

__IO uint32_t { ... } ::PX_SMAG2_JR

Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::PX_SMAG2_JR

Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10

◆  [1/3]

__IO uint32_t { ... } ::PX_SMAG2_PG0

Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10

◆ PX_SMAG2_PG0 [2/3]

__IO uint32_t CAAM_Type::PX_SMAG2_PG0

Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::PX_SMAG2_PG0

Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10

◆  [1/3]

__IO uint32_t { ... } ::PX_SMAPR_JR

Secure Memory Access Permissions register, array offset: 0x10A04, array step: index*0x10000, index2*0x10

◆ PX_SMAPR_JR [2/3]

__IO uint32_t CAAM_Type::PX_SMAPR_JR

Secure Memory Access Permissions register, array offset: 0x10A04, array step: index*0x10000, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::PX_SMAPR_JR

Secure Memory Access Permissions register, array offset: 0x10A04, array step: index*0x10000, index2*0x10

◆  [1/3]

__IO uint32_t { ... } ::PX_SMAPR_PG0

Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10

◆ PX_SMAPR_PG0 [2/3]

__IO uint32_t CAAM_Type::PX_SMAPR_PG0

Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::PX_SMAPR_PG0

Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10

◆ QOS

__IO uint32_t ENET_Type::QOS

QOS Scheme, offset: 0x1F0

◆ R

__I uint32_t ADC_Type::R[8]

Data result register for HW triggers, array offset: 0x24, array step: 0x4

◆ RACC

__IO uint32_t ENET_Type::RACC

Receive Accelerator Function Configuration, offset: 0x1C4

◆ RAEM

__IO uint32_t ENET_Type::RAEM

Receive FIFO Almost Empty Threshold, offset: 0x198

◆ RAFL

__IO uint32_t ENET_Type::RAFL

Receive FIFO Almost Full Threshold, offset: 0x19C

◆ RANGE0

__IO uint32_t TMPSNS_Type::RANGE0

Temperature Sensor Range Register 0, offset: 0x20

◆ RANGE0_CLR

__IO uint32_t TMPSNS_Type::RANGE0_CLR

Temperature Sensor Range Register 0, offset: 0x28

◆ RANGE0_SET

__IO uint32_t TMPSNS_Type::RANGE0_SET

Temperature Sensor Range Register 0, offset: 0x24

◆ RANGE0_TOG

__IO uint32_t TMPSNS_Type::RANGE0_TOG

Temperature Sensor Range Register 0, offset: 0x2C

◆ RANGE1

__IO uint32_t TMPSNS_Type::RANGE1

Temperature Sensor Range Register 1, offset: 0x30

◆ RANGE1_CLR

__IO uint32_t TMPSNS_Type::RANGE1_CLR

Temperature Sensor Range Register 1, offset: 0x38

◆ RANGE1_SET

__IO uint32_t TMPSNS_Type::RANGE1_SET

Temperature Sensor Range Register 1, offset: 0x34

◆ RANGE1_TOG

__IO uint32_t TMPSNS_Type::RANGE1_TOG

Temperature Sensor Range Register 1, offset: 0x3C

◆ RANGE_CTRL

__IO uint32_t PDM_Type::RANGE_CTRL

PDM Range Control register, offset: 0x74

◆ RANGE_STAT

__IO uint32_t PDM_Type::RANGE_STAT

PDM Range Status register, offset: 0x7C

◆ RBB_LPSR_CONFIGURE

__IO uint32_t ANADIG_PMU_Type::RBB_LPSR_CONFIGURE

RBB_LPSR_CONFIGURE_REGISTER, offset: 0x790

◆ RBB_LPSR_ENABLE_SP

__IO uint32_t ANADIG_PMU_Type::RBB_LPSR_ENABLE_SP

RBB_LPSR_ENABLE_SP_REGISTER, offset: 0x720

◆ RBB_LPSR_STBY_EN_SP

__IO uint32_t ANADIG_PMU_Type::RBB_LPSR_STBY_EN_SP

RBB_LPSR_STBY_EN_SP_REGISTER, offset: 0x770

◆ RBB_SOC_CONFIGURE

__IO uint32_t ANADIG_PMU_Type::RBB_SOC_CONFIGURE

RBB_SOC_CONFIGURE_REGISTER, offset: 0x7A0

◆ RBB_SOC_ENABLE_SP

__IO uint32_t ANADIG_PMU_Type::RBB_SOC_ENABLE_SP

RBB_SOC_ENABLE_SP_REGISTER, offset: 0x710

◆ RBB_SOC_STBY_EN_SP

__IO uint32_t ANADIG_PMU_Type::RBB_SOC_STBY_EN_SP

RBB_SOC_STBY_EN_SP_REGISTER, offset: 0x760

◆ RCMD

__IO uint32_t CAAM_Type::RCMD

RTIC Command Register, offset: 0x6000C

◆ RCMR

__IO uint32_t ENET_Type::RCMR

Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4

◆ RCR

__IO uint32_t ENET_Type::RCR

Receive Control Register, offset: 0x84

◆ RCR1

__IO uint32_t I2S_Type::RCR1

SAI Receive Configuration 1 Register, offset: 0x8C

Receive Configuration 1, offset: 0x8C

◆ RCR2

__IO uint32_t I2S_Type::RCR2

SAI Receive Configuration 2 Register, offset: 0x90

Receive Configuration 2, offset: 0x90

◆ RCR3

__IO uint32_t I2S_Type::RCR3

SAI Receive Configuration 3 Register, offset: 0x94

Receive Configuration 3, offset: 0x94

◆ RCR4

__IO uint32_t I2S_Type::RCR4

SAI Receive Configuration 4 Register, offset: 0x98

Receive Configuration 4, offset: 0x98

◆ RCR5

__IO uint32_t I2S_Type::RCR5

SAI Receive Configuration 5 Register, offset: 0x9C

Receive Configuration 5, offset: 0x9C

◆ RCSR

__IO uint32_t I2S_Type::RCSR

SAI Receive Control Register, offset: 0x88

Receive Control, offset: 0x88

◆ RCTL

__IO uint32_t CAAM_Type::RCTL

RTIC Control Register, offset: 0x60014

◆ RDAR

__IO uint32_t ENET_Type::RDAR

Receive Descriptor Active Register - Ring 0, offset: 0x10

◆ RDAR1

__IO uint32_t ENET_Type::RDAR1

Receive Descriptor Active Register - Ring 1, offset: 0x1E0

◆ RDAR2

__IO uint32_t ENET_Type::RDAR2

Receive Descriptor Active Register - Ring 2, offset: 0x1E8

◆ RDHBUF

__O uint32_t CAAM_Type::RDHBUF

RNG DRNG Hash Buffer Register, offset: 0x6E8

◆ RDHCNTL

__IO uint32_t CAAM_Type::RDHCNTL

RNG DRNG Hash Control Register, offset: 0x6E0

◆ RDHDIG

__I uint32_t CAAM_Type::RDHDIG

RNG DRNG Hash Digest Register, offset: 0x6E4

◆ RDINT0

__I uint32_t CAAM_Type::RDINT0

RNG DRNG State Handle 0 Reseed Interval Register, offset: 0x6D0

◆ RDINT1

__I uint32_t CAAM_Type::RDINT1

RNG DRNG State Handle 1 Reseed Interval Register, offset: 0x6D4

◆ RDR [1/2]

__I uint32_t I2S_Type::RDR

SAI Receive Data Register, array offset: 0xA0, array step: 0x4

Receive Data, array offset: 0xA0, array step: 0x4

◆ RDR [2/2]

__I uint32_t LPSPI_Type::RDR

Receive Data Register, offset: 0x74

Receive Data, offset: 0x74

◆ RDSR

__IO uint32_t ENET_Type::RDSR

Receive Descriptor Ring 0 Start Register, offset: 0x180

◆ RDSR1

__IO uint32_t ENET_Type::RDSR1

Receive Descriptor Ring 1 Start Register, offset: 0x160

◆ RDSR2

__IO uint32_t ENET_Type::RDSR2

Receive Descriptor Ring 2 Start Register, offset: 0x16C

◆ RDSTA

__I uint32_t CAAM_Type::RDSTA

RNG DRNG Status Register, offset: 0x6C0

◆ READ_CTRL

__IO uint32_t OCOTP_Type::READ_CTRL

OTP Controller Write Data Register, offset: 0x30

OTP Controller Read Control Register, offset: 0x30

◆ READ_FUSE_DATA [1/3]

__IO uint32_t OCOTP_Type::READ_FUSE_DATA

OTP Controller Read Data Register, offset: 0x40

OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register, array offset: 0x100, array step: 0x10

◆  [2/3]

__IO uint32_t { ... } ::READ_FUSE_DATA

OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register, array offset: 0x100, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::READ_FUSE_DATA

OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register, array offset: 0x100, array step: 0x10

◆ REFTOP_OTP_TRIM_VALUE

__I uint32_t ANADIG_PMU_Type::REFTOP_OTP_TRIM_VALUE

REFTOP_OTP_TRIM_VALUE_REGISTER, offset: 0x7B0

◆ REG0

__IO uint32_t DCDC_Type::REG0

DCDC Register 0, offset: 0x0

DCDC Register 0, offset: 0x8

◆ REG1

__IO uint32_t DCDC_Type::REG1

DCDC Register 1, offset: 0x4

DCDC Register 1, offset: 0xC

◆ REG10

__IO uint32_t DCDC_Type::REG10

DCDC Register 10, offset: 0x34

◆ REG11

__IO uint32_t DCDC_Type::REG11

DCDC Register 11, offset: 0x38

◆ REG12

__IO uint32_t DCDC_Type::REG12

DCDC Register 12, offset: 0x3C

◆ REG13

__IO uint32_t DCDC_Type::REG13

DCDC Register 13, offset: 0x40

◆ REG14

__IO uint32_t DCDC_Type::REG14

DCDC Register 14, offset: 0x44

◆ REG15

__IO uint32_t DCDC_Type::REG15

DCDC Register 15, offset: 0x48

◆ REG16

__IO uint32_t DCDC_Type::REG16

DCDC Register 16, offset: 0x4C

◆ REG17

__IO uint32_t DCDC_Type::REG17

DCDC Register 17, offset: 0x50

◆ REG18

__IO uint32_t DCDC_Type::REG18

DCDC Register 18, offset: 0x54

◆ REG19

__IO uint32_t DCDC_Type::REG19

DCDC Register 19, offset: 0x58

◆ REG2

__IO uint32_t DCDC_Type::REG2

DCDC Register 2, offset: 0x8

DCDC Register 2, offset: 0x10

◆ REG20

__IO uint32_t DCDC_Type::REG20

DCDC Register 20, offset: 0x5C

◆ REG21

__IO uint32_t DCDC_Type::REG21

DCDC Register 21, offset: 0x60

◆ REG22

__IO uint32_t DCDC_Type::REG22

DCDC Register 22, offset: 0x64

◆ REG23

__IO uint32_t DCDC_Type::REG23

DCDC Register 23, offset: 0x68

◆ REG24

__IO uint32_t DCDC_Type::REG24

DCDC Register 24, offset: 0x6C

◆ REG3

__IO uint32_t DCDC_Type::REG3

DCDC Register 3, offset: 0xC

DCDC Register 3, offset: 0x14

◆ REG4

__IO uint32_t DCDC_Type::REG4

DCDC Register 4, offset: 0x18

◆ REG5

__IO uint32_t DCDC_Type::REG5

DCDC Register 5, offset: 0x1C

◆ REG6

__IO uint32_t DCDC_Type::REG6

DCDC Register 6, offset: 0x20

◆ REG7

__IO uint32_t DCDC_Type::REG7

DCDC Register 7, offset: 0x24

◆ REG7P

__IO uint32_t DCDC_Type::REG7P

DCDC Register 7 plus, offset: 0x28

◆ REG8

__IO uint32_t DCDC_Type::REG8

DCDC Register 8, offset: 0x2C

◆ REG9

__IO uint32_t DCDC_Type::REG9

DCDC Register 9, offset: 0x30

◆ REG_1P1

__IO uint32_t PMU_Type::REG_1P1

Regulator 1P1 Register, offset: 0x110

◆ REG_1P1_CLR

__IO uint32_t PMU_Type::REG_1P1_CLR

Regulator 1P1 Register, offset: 0x118

◆ REG_1P1_SET

__IO uint32_t PMU_Type::REG_1P1_SET

Regulator 1P1 Register, offset: 0x114

◆ REG_1P1_TOG

__IO uint32_t PMU_Type::REG_1P1_TOG

Regulator 1P1 Register, offset: 0x11C

◆ REG_2P5

__IO uint32_t PMU_Type::REG_2P5

Regulator 2P5 Register, offset: 0x130

◆ REG_2P5_CLR

__IO uint32_t PMU_Type::REG_2P5_CLR

Regulator 2P5 Register, offset: 0x138

◆ REG_2P5_SET

__IO uint32_t PMU_Type::REG_2P5_SET

Regulator 2P5 Register, offset: 0x134

◆ REG_2P5_TOG

__IO uint32_t PMU_Type::REG_2P5_TOG

Regulator 2P5 Register, offset: 0x13C

◆ REG_3P0

__IO uint32_t PMU_Type::REG_3P0

Regulator 3P0 Register, offset: 0x120

◆ REG_3P0_CLR

__IO uint32_t PMU_Type::REG_3P0_CLR

Regulator 3P0 Register, offset: 0x128

◆ REG_3P0_SET

__IO uint32_t PMU_Type::REG_3P0_SET

Regulator 3P0 Register, offset: 0x124

◆ REG_3P0_TOG

__IO uint32_t PMU_Type::REG_3P0_TOG

Regulator 3P0 Register, offset: 0x12C

◆ REG_CORE

__IO uint32_t PMU_Type::REG_CORE

Digital Regulator Core Register, offset: 0x140

◆ REG_CORE_CLR

__IO uint32_t PMU_Type::REG_CORE_CLR

Digital Regulator Core Register, offset: 0x148

◆ REG_CORE_SET

__IO uint32_t PMU_Type::REG_CORE_SET

Digital Regulator Core Register, offset: 0x144

◆ REG_CORE_TOG

__IO uint32_t PMU_Type::REG_CORE_TOG

Digital Regulator Core Register, offset: 0x14C

◆ REGATTR [1/3]

__IO uint32_t IEE_Type::REGATTR

IEE Region 0 Attribute Register...IEE Region 7 Attribute Register., array offset: 0x100, array step: 0x100

◆  [2/3]

__IO uint32_t { ... } ::REGATTR

IEE Region 0 Attribute Register...IEE Region 7 Attribute Register., array offset: 0x100, array step: 0x100

◆  [3/3]

__IO uint32_t { ... } ::REGATTR

IEE Region 0 Attribute Register...IEE Region 7 Attribute Register., array offset: 0x100, array step: 0x100

◆ REGION0_BOT_ADDR

__IO uint32_t IEE_APC_Type::REGION0_BOT_ADDR

Start address of IEE region (n), offset: 0x4

◆ REGION0_RDC_D0

__IO uint32_t IEE_APC_Type::REGION0_RDC_D0

Region control of core domain 0 for region (n), offset: 0x8

◆ REGION0_RDC_D1

__IO uint32_t IEE_APC_Type::REGION0_RDC_D1

Region control of core domain 1 for region (n), offset: 0xC

◆ REGION0_TOP_ADDR

__IO uint32_t IEE_APC_Type::REGION0_TOP_ADDR

End address of IEE region (n), offset: 0x0

◆ REGION1_BOT

__IO uint32_t BEE_Type::REGION1_BOT

Region1 Bottom Address Register, offset: 0x44

◆ REGION1_BOT_ADDR

__IO uint32_t IEE_APC_Type::REGION1_BOT_ADDR

Start address of IEE region (n), offset: 0x14

◆ REGION1_RDC_D0

__IO uint32_t IEE_APC_Type::REGION1_RDC_D0

Region control of core domain 0 for region (n), offset: 0x18

◆ REGION1_RDC_D1

__IO uint32_t IEE_APC_Type::REGION1_RDC_D1

Region control of core domain 1 for region (n), offset: 0x1C

◆ REGION1_TOP

__IO uint32_t BEE_Type::REGION1_TOP

Region1 Top Address Register, offset: 0x40

◆ REGION1_TOP_ADDR

__IO uint32_t IEE_APC_Type::REGION1_TOP_ADDR

End address of IEE region (n), offset: 0x10

◆ REGION2_BOT_ADDR

__IO uint32_t IEE_APC_Type::REGION2_BOT_ADDR

Start address of IEE region (n), offset: 0x24

◆ REGION2_RDC_D0

__IO uint32_t IEE_APC_Type::REGION2_RDC_D0

Region control of core domain 0 for region (n), offset: 0x28

◆ REGION2_RDC_D1

__IO uint32_t IEE_APC_Type::REGION2_RDC_D1

Region control of core domain 1 for region (n), offset: 0x2C

◆ REGION2_TOP_ADDR

__IO uint32_t IEE_APC_Type::REGION2_TOP_ADDR

End address of IEE region (n), offset: 0x20

◆ REGION3_BOT_ADDR

__IO uint32_t IEE_APC_Type::REGION3_BOT_ADDR

Start address of IEE region (n), offset: 0x34

◆ REGION3_RDC_D0

__IO uint32_t IEE_APC_Type::REGION3_RDC_D0

Region control of core domain 0 for region (n), offset: 0x38

◆ REGION3_RDC_D1

__IO uint32_t IEE_APC_Type::REGION3_RDC_D1

Region control of core domain 1 for region (n), offset: 0x3C

◆ REGION3_TOP_ADDR

__IO uint32_t IEE_APC_Type::REGION3_TOP_ADDR

End address of IEE region (n), offset: 0x30

◆ REGION4_BOT_ADDR

__IO uint32_t IEE_APC_Type::REGION4_BOT_ADDR

Start address of IEE region (n), offset: 0x44

◆ REGION4_RDC_D0

__IO uint32_t IEE_APC_Type::REGION4_RDC_D0

Region control of core domain 0 for region (n), offset: 0x48

◆ REGION4_RDC_D1

__IO uint32_t IEE_APC_Type::REGION4_RDC_D1

Region control of core domain 1 for region (n), offset: 0x4C

◆ REGION4_TOP_ADDR

__IO uint32_t IEE_APC_Type::REGION4_TOP_ADDR

End address of IEE region (n), offset: 0x40

◆ REGION5_BOT_ADDR

__IO uint32_t IEE_APC_Type::REGION5_BOT_ADDR

Start address of IEE region (n), offset: 0x54

◆ REGION5_RDC_D0

__IO uint32_t IEE_APC_Type::REGION5_RDC_D0

Region control of core domain 0 for region (n), offset: 0x58

◆ REGION5_RDC_D1

__IO uint32_t IEE_APC_Type::REGION5_RDC_D1

Region control of core domain 1 for region (n), offset: 0x5C

◆ REGION5_TOP_ADDR

__IO uint32_t IEE_APC_Type::REGION5_TOP_ADDR

End address of IEE region (n), offset: 0x50

◆ REGION6_BOT_ADDR

__IO uint32_t IEE_APC_Type::REGION6_BOT_ADDR

Start address of IEE region (n), offset: 0x64

◆ REGION6_RDC_D0

__IO uint32_t IEE_APC_Type::REGION6_RDC_D0

Region control of core domain 0 for region (n), offset: 0x68

◆ REGION6_RDC_D1

__IO uint32_t IEE_APC_Type::REGION6_RDC_D1

Region control of core domain 1 for region (n), offset: 0x6C

◆ REGION6_TOP_ADDR

__IO uint32_t IEE_APC_Type::REGION6_TOP_ADDR

End address of IEE region (n), offset: 0x60

◆ REGION7_BOT_ADDR

__IO uint32_t IEE_APC_Type::REGION7_BOT_ADDR

Start address of IEE region (n), offset: 0x74

◆ REGION7_RDC_D0

__IO uint32_t IEE_APC_Type::REGION7_RDC_D0

Region control of core domain 0 for region (n), offset: 0x78

◆ REGION7_RDC_D1

__IO uint32_t IEE_APC_Type::REGION7_RDC_D1

Region control of core domain 1 for region (n), offset: 0x7C

◆ REGION7_TOP_ADDR

__IO uint32_t IEE_APC_Type::REGION7_TOP_ADDR

End address of IEE region (n), offset: 0x70

◆  [1/3]

__O uint32_t { ... } ::REGKEY1[8]

IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register, array offset: 0x140, array step: index*0x100, index2*0x4

◆ REGKEY1 [2/3]

__O uint32_t IEE_Type::REGKEY1[8]

IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register, array offset: 0x140, array step: index*0x100, index2*0x4

◆  [3/3]

__O uint32_t { ... } ::REGKEY1[8]

IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register, array offset: 0x140, array step: index*0x100, index2*0x4

◆  [1/3]

__O uint32_t { ... } ::REGKEY2[8]

IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register, array offset: 0x180, array step: index*0x100, index2*0x4

◆ REGKEY2 [2/3]

__O uint32_t IEE_Type::REGKEY2[8]

IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register, array offset: 0x180, array step: index*0x100, index2*0x4

◆  [3/3]

__O uint32_t { ... } ::REGKEY2[8]

IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register, array offset: 0x180, array step: index*0x100, index2*0x4

◆  [1/3]

__IO uint32_t { ... } ::REGPO

IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register, array offset: 0x108, array step: 0x100

◆ REGPO [2/3]

__IO uint32_t IEE_Type::REGPO

IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register, array offset: 0x108, array step: 0x100

◆  [3/3]

__IO uint32_t { ... } ::REGPO

IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register, array offset: 0x108, array step: 0x100

◆ REIE

__IO uint32_t CAAM_Type::REIE

Recoverable Error Interrupt Enable, offset: 0xB04

◆ REIF

__I uint32_t CAAM_Type::REIF

Recoverable Error Interrupt Force, offset: 0xB08

◆ REIH

__IO uint32_t CAAM_Type::REIH

Recoverable Error Interrupt Halt, offset: 0xB0C

◆ REIR0JR [1/3]

__I uint32_t CAAM_Type::REIR0JR

Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3, array offset: 0x10E00, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::REIR0JR

Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3, array offset: 0x10E00, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::REIR0JR

Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3, array offset: 0x10E00, array step: 0x10000

◆ REIR0RTIC

__I uint32_t CAAM_Type::REIR0RTIC

Recoverable Error Interrupt Record 0 for RTIC, offset: 0x60E00

◆ REIR2JR [1/3]

__I uint64_t CAAM_Type::REIR2JR

Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3, array offset: 0x10E08, array step: 0x10000

◆  [2/3]

__I uint64_t { ... } ::REIR2JR

Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3, array offset: 0x10E08, array step: 0x10000

◆  [3/3]

__I uint64_t { ... } ::REIR2JR

Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3, array offset: 0x10E08, array step: 0x10000

◆ REIR2RTIC

__I uint64_t CAAM_Type::REIR2RTIC

Recoverable Error Interrupt Record 2 for RTIC, offset: 0x60E08

◆  [1/3]

__I uint32_t { ... } ::REIR4JR

Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3, array offset: 0x10E10, array step: 0x10000

◆ REIR4JR [2/3]

__I uint32_t CAAM_Type::REIR4JR

Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3, array offset: 0x10E10, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::REIR4JR

Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3, array offset: 0x10E10, array step: 0x10000

◆ REIR4RTIC

__I uint32_t CAAM_Type::REIR4RTIC

Recoverable Error Interrupt Record 4 for RTIC, offset: 0x60E10

◆ REIR5JR [1/3]

__I uint32_t CAAM_Type::REIR5JR

Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3, array offset: 0x10E14, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::REIR5JR

Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3, array offset: 0x10E14, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::REIR5JR

Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3, array offset: 0x10E14, array step: 0x10000

◆ REIR5RTIC

__I uint32_t CAAM_Type::REIR5RTIC

Recoverable Error Interrupt Record 5 for RTIC, offset: 0x60E14

◆ REIS

__IO uint32_t CAAM_Type::REIS

Recoverable Error Interrupt Status, offset: 0xB00

◆ RELOAD

__IO uint32_t CDOG_Type::RELOAD

Instruction Timer reload, offset: 0x4

◆ REND

__IO uint32_t CAAM_Type::REND

RTIC Endian Register, offset: 0x60034

◆ RERRAR

__I uint32_t CAN_Type::RERRAR

Error Report Address register, offset: 0xAF0

◆ RERRDR

__I uint32_t CAN_Type::RERRDR

Error Report Data register, offset: 0xAF4

◆ RERRSYNR

__I uint32_t CAN_Type::RERRSYNR

Error Report Syndrome register, offset: 0xAF8

◆ RESFIFO

__I uint32_t ADC_Type::RESFIFO

LPADC Data Result FIFO Register, offset: 0x300

◆ RESTART

__O uint32_t CDOG_Type::RESTART

RESTART Command, offset: 0x28

◆ REV

__IO uint16_t ENC_Type::REV

Revolution Counter Register, offset: 0xA

◆ REVH

__I uint16_t ENC_Type::REVH

Revolution Hold Register, offset: 0xC

◆ RFDR

__I uint32_t FLEXSPI_Type::RFDR

IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4

◆ RFIFO

__I uint32_t CSI_Type::RFIFO

CSI RX FIFO Register, offset: 0x10

◆ RFR

__I uint32_t I2S_Type::RFR

SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4

Receive FIFO, array offset: 0xC0, array step: 0x4

◆ RGB_ADJUST

__IO uint32_t LCDIF_Type::RGB_ADJUST

RGB Color Range Adjust, offset: 0x2A0

◆ RGB_ADJUST_CLR

__IO uint32_t LCDIF_Type::RGB_ADJUST_CLR

RGB Color Range Adjust, offset: 0x2A8

◆ RGB_ADJUST_SET

__IO uint32_t LCDIF_Type::RGB_ADJUST_SET

RGB Color Range Adjust, offset: 0x2A4

◆ RGB_ADJUST_TOG

__IO uint32_t LCDIF_Type::RGB_ADJUST_TOG

RGB Color Range Adjust, offset: 0x2AC

◆  [1/3]

__IO uint32_t { ... } ::RGD_W0

AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40

◆ RGD_W0 [2/3]

__IO uint32_t OTFAD_Type::RGD_W0

AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40

◆  [3/3]

__IO uint32_t { ... } ::RGD_W0

AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40

◆  [1/3]

__IO uint32_t { ... } ::RGD_W1

AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40

◆ RGD_W1 [2/3]

__IO uint32_t OTFAD_Type::RGD_W1

AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40

◆  [3/3]

__IO uint32_t { ... } ::RGD_W1

AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40

◆  [1/3]

__IO uint64_t { ... } ::RMA

RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register, array offset: 0x60100, array step: index*0x20, index2*0x10

◆ RMA [2/3]

__IO uint64_t CAAM_Type::RMA

RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register, array offset: 0x60100, array step: index*0x20, index2*0x10

◆  [3/3]

__IO uint64_t { ... } ::RMA

RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register, array offset: 0x60100, array step: index*0x20, index2*0x10

◆ RMD

__IO uint32_t CAAM_Type::RMD

RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31, array offset: 0x60200, array step: index*0x100, index2*0x80, index3*0x4

◆  [1/3]

__IO uint32_t { ... } ::RML

RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register, array offset: 0x6010C, array step: index*0x20, index2*0x10

◆ RML [2/3]

__IO uint32_t CAAM_Type::RML

RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register, array offset: 0x6010C, array step: index*0x20, index2*0x10

◆  [3/3]

__IO uint32_t { ... } ::RML

RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register, array offset: 0x6010C, array step: index*0x20, index2*0x10

◆ RMON_R_BC_PKT

__I uint32_t ENET_Type::RMON_R_BC_PKT

Rx Broadcast Packets Statistic Register, offset: 0x288

◆ RMON_R_CRC_ALIGN

__I uint32_t ENET_Type::RMON_R_CRC_ALIGN

Rx Packets with CRC/Align Error Statistic Register, offset: 0x290

◆ RMON_R_FRAG

__I uint32_t ENET_Type::RMON_R_FRAG

Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C

◆ RMON_R_JAB

__I uint32_t ENET_Type::RMON_R_JAB

Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0

◆ RMON_R_MC_PKT

__I uint32_t ENET_Type::RMON_R_MC_PKT

Rx Multicast Packets Statistic Register, offset: 0x28C

◆ RMON_R_OCTETS

__I uint32_t ENET_Type::RMON_R_OCTETS

Rx Octets Statistic Register, offset: 0x2C4

◆ RMON_R_OVERSIZE

__I uint32_t ENET_Type::RMON_R_OVERSIZE

Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298

◆ RMON_R_P1024TO2047

__I uint32_t ENET_Type::RMON_R_P1024TO2047

Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC

◆ RMON_R_P128TO255

__I uint32_t ENET_Type::RMON_R_P128TO255

Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0

◆ RMON_R_P256TO511

__I uint32_t ENET_Type::RMON_R_P256TO511

Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4

◆ RMON_R_P512TO1023

__I uint32_t ENET_Type::RMON_R_P512TO1023

Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8

◆ RMON_R_P64

__I uint32_t ENET_Type::RMON_R_P64

Rx 64-Byte Packets Statistic Register, offset: 0x2A8

◆ RMON_R_P65TO127

__I uint32_t ENET_Type::RMON_R_P65TO127

Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC

◆ RMON_R_P_GTE2048

__I uint32_t ENET_Type::RMON_R_P_GTE2048

Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0

◆ RMON_R_PACKETS

__I uint32_t ENET_Type::RMON_R_PACKETS

Rx Packet Count Statistic Register, offset: 0x284

◆ RMON_R_UNDERSIZE

__I uint32_t ENET_Type::RMON_R_UNDERSIZE

Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294

◆ RMON_T_BC_PKT

__I uint32_t ENET_Type::RMON_T_BC_PKT

Tx Broadcast Packets Statistic Register, offset: 0x208

◆ RMON_T_COL

__I uint32_t ENET_Type::RMON_T_COL

Tx Collision Count Statistic Register, offset: 0x224

◆ RMON_T_CRC_ALIGN

__I uint32_t ENET_Type::RMON_T_CRC_ALIGN

Tx Packets with CRC/Align Error Statistic Register, offset: 0x210

◆ RMON_T_FRAG

__I uint32_t ENET_Type::RMON_T_FRAG

Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C

◆ RMON_T_JAB

__I uint32_t ENET_Type::RMON_T_JAB

Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220

◆ RMON_T_MC_PKT

__I uint32_t ENET_Type::RMON_T_MC_PKT

Tx Multicast Packets Statistic Register, offset: 0x20C

◆ RMON_T_OCTETS

__I uint32_t ENET_Type::RMON_T_OCTETS

Tx Octets Statistic Register, offset: 0x244

◆ RMON_T_OVERSIZE

__I uint32_t ENET_Type::RMON_T_OVERSIZE

Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218

◆ RMON_T_P1024TO2047

__I uint32_t ENET_Type::RMON_T_P1024TO2047

Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C

◆ RMON_T_P128TO255

__I uint32_t ENET_Type::RMON_T_P128TO255

Tx 128- to 255-byte Packets Statistic Register, offset: 0x230

◆ RMON_T_P256TO511

__I uint32_t ENET_Type::RMON_T_P256TO511

Tx 256- to 511-byte Packets Statistic Register, offset: 0x234

◆ RMON_T_P512TO1023

__I uint32_t ENET_Type::RMON_T_P512TO1023

Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238

◆ RMON_T_P64

__I uint32_t ENET_Type::RMON_T_P64

Tx 64-Byte Packets Statistic Register, offset: 0x228

◆ RMON_T_P65TO127

__I uint32_t ENET_Type::RMON_T_P65TO127

Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C

◆ RMON_T_P_GTE2048

__I uint32_t ENET_Type::RMON_T_P_GTE2048

Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240

◆ RMON_T_PACKETS

__I uint32_t ENET_Type::RMON_T_PACKETS

Tx Packet Count Statistic Register, offset: 0x204

◆ RMON_T_UNDERSIZE

__I uint32_t ENET_Type::RMON_T_UNDERSIZE

Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214

◆ RMR

__IO uint32_t I2S_Type::RMR

SAI Receive Mask Register, offset: 0xE0

Receive Mask, offset: 0xE0

◆ ROMPATCHA

__IO uint32_t ROMC_Type::ROMPATCHA[16]

ROMC Address Registers, array offset: 0x100, array step: 0x4

◆ ROMPATCHCNTL

__IO uint32_t ROMC_Type::ROMPATCHCNTL

ROMC Control Register, offset: 0xF4

◆ ROMPATCHD

__IO uint32_t ROMC_Type::ROMPATCHD[8]

ROMC Data Registers, array offset: 0xD4, array step: 0x4

◆ ROMPATCHENH

uint32_t ROMC_Type::ROMPATCHENH

ROMC Enable Register High, offset: 0xF8

◆ ROMPATCHENL

__IO uint32_t ROMC_Type::ROMPATCHENL

ROMC Enable Register Low, offset: 0xFC

◆ ROMPATCHSR

__IO uint32_t ROMC_Type::ROMPATCHSR

ROMC Status Register, offset: 0x208

◆ RR

__I uint32_t MU_Type::RR

Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array step: 0x4

Processor A Receive Register 0..Processor A Receive Register 3, array offset: 0x10, array step: 0x4

◆ RSEM

__IO uint32_t ENET_Type::RSEM

Receive FIFO Section Empty Threshold, offset: 0x194

◆ RSFL

__IO uint32_t ENET_Type::RSFL

Receive FIFO Section Full Threshold, offset: 0x190

◆ RSR

__I uint32_t LPSPI_Type::RSR

Receive Status Register, offset: 0x70

Receive Status, offset: 0x70

◆ RSTA

__I uint32_t CAAM_Type::RSTA

RTIC Status Register, offset: 0x60004

◆ RSTGT

__IO uint16_t SEMA4_Type::RSTGT

Semaphores (Secure) Reset Gate n, offset: 0x100

◆  [1/3]

__IO uint16_t { ... } ::RSTGT_R

Reset Gate Read, offset: 0x42

◆ RSTGT_R [2/3]

__IO uint16_t RDC_SEMAPHORE_Type::RSTGT_R

Reset Gate Read, offset: 0x42

◆  [3/3]

__IO uint16_t { ... } ::RSTGT_R

Reset Gate Read, offset: 0x42

◆  [1/3]

__IO uint16_t { ... } ::RSTGT_W

Reset Gate Write, offset: 0x42

◆ RSTGT_W [2/3]

__IO uint16_t RDC_SEMAPHORE_Type::RSTGT_W

Reset Gate Write, offset: 0x42

◆  [3/3]

__IO uint16_t { ... } ::RSTGT_W

Reset Gate Write, offset: 0x42

◆ RSTNTF

__IO uint16_t SEMA4_Type::RSTNTF

Semaphores (Secure) Reset IRQ Notification, offset: 0x104

◆ RTENT

__I uint32_t CAAM_Type::RTENT

RNG TRNG Entropy Read Register, array offset: 0x640, array step: 0x4

◆ RTFRQCNT [1/3]

__I uint32_t CAAM_Type::RTFRQCNT

RNG TRNG Frequency Count Register, offset: 0x61C

◆  [2/3]

__I uint32_t { ... } ::RTFRQCNT

RNG TRNG Frequency Count Register, offset: 0x61C

◆  [3/3]

__I uint32_t { ... } ::RTFRQCNT

RNG TRNG Frequency Count Register, offset: 0x61C

◆ RTFRQMAX [1/3]

__IO uint32_t CAAM_Type::RTFRQMAX

RNG TRNG Frequency Count Maximum Limit Register, offset: 0x61C

◆  [2/3]

__IO uint32_t { ... } ::RTFRQMAX

RNG TRNG Frequency Count Maximum Limit Register, offset: 0x61C

◆  [3/3]

__IO uint32_t { ... } ::RTFRQMAX

RNG TRNG Frequency Count Maximum Limit Register, offset: 0x61C

◆ RTFRQMIN

__IO uint32_t CAAM_Type::RTFRQMIN

RNG TRNG Frequency Count Minimum Limit Register, offset: 0x618

◆ RTHR

__IO uint32_t CAAM_Type::RTHR

RTIC Throttle Register, offset: 0x6001C

◆ RTIC_DID [1/3]

__IO uint32_t CAAM_Type::RTIC_DID

RTIC DID Register for Block A..RTIC DID Register for Block D, array offset: 0x64, array step: 0x8

◆  [2/3]

__IO uint32_t { ... } ::RTIC_DID

RTIC DID Register for Block A..RTIC DID Register for Block D, array offset: 0x64, array step: 0x8

◆  [3/3]

__IO uint32_t { ... } ::RTIC_DID

RTIC DID Register for Block A..RTIC DID Register for Block D, array offset: 0x64, array step: 0x8

◆ RTIC_OWN

__IO uint32_t CAAM_Type::RTIC_OWN

RTIC OWN Register, offset: 0x60

◆ RTMCTL

__IO uint32_t CAAM_Type::RTMCTL

RNG TRNG Miscellaneous Control Register, offset: 0x600

◆ RTPKRCNT10

__I uint32_t CAAM_Type::RTPKRCNT10

RNG TRNG Statistical Check Poker Count 1 and 0 Register, offset: 0x680

◆ RTPKRCNT32

__I uint32_t CAAM_Type::RTPKRCNT32

RNG TRNG Statistical Check Poker Count 3 and 2 Register, offset: 0x684

◆ RTPKRCNT54

__I uint32_t CAAM_Type::RTPKRCNT54

RNG TRNG Statistical Check Poker Count 5 and 4 Register, offset: 0x688

◆ RTPKRCNT76

__I uint32_t CAAM_Type::RTPKRCNT76

RNG TRNG Statistical Check Poker Count 7 and 6 Register, offset: 0x68C

◆ RTPKRCNT98

__I uint32_t CAAM_Type::RTPKRCNT98

RNG TRNG Statistical Check Poker Count 9 and 8 Register, offset: 0x690

◆ RTPKRCNTBA

__I uint32_t CAAM_Type::RTPKRCNTBA

RNG TRNG Statistical Check Poker Count B and A Register, offset: 0x694

◆ RTPKRCNTDC

__I uint32_t CAAM_Type::RTPKRCNTDC

RNG TRNG Statistical Check Poker Count D and C Register, offset: 0x698

◆ RTPKRCNTFE

__I uint32_t CAAM_Type::RTPKRCNTFE

RNG TRNG Statistical Check Poker Count F and E Register, offset: 0x69C

◆ RTPKRMAX [1/3]

__IO uint32_t CAAM_Type::RTPKRMAX

RNG TRNG Poker Maximum Limit Register, offset: 0x60C

◆  [2/3]

__IO uint32_t { ... } ::RTPKRMAX

RNG TRNG Poker Maximum Limit Register, offset: 0x60C

◆  [3/3]

__IO uint32_t { ... } ::RTPKRMAX

RNG TRNG Poker Maximum Limit Register, offset: 0x60C

◆ RTPKRRNG

__IO uint32_t CAAM_Type::RTPKRRNG

RNG TRNG Poker Range Register, offset: 0x608

◆ RTPKRSQ [1/3]

__I uint32_t CAAM_Type::RTPKRSQ

RNG TRNG Poker Square Calculation Result Register, offset: 0x60C

◆  [2/3]

__I uint32_t { ... } ::RTPKRSQ

RNG TRNG Poker Square Calculation Result Register, offset: 0x60C

◆  [3/3]

__I uint32_t { ... } ::RTPKRSQ

RNG TRNG Poker Square Calculation Result Register, offset: 0x60C

◆ RTSBLIM [1/3]

__IO uint32_t CAAM_Type::RTSBLIM

RNG TRNG Sparse Bit Limit Register, offset: 0x614

◆  [2/3]

__IO uint32_t { ... } ::RTSBLIM

RNG TRNG Sparse Bit Limit Register, offset: 0x614

◆  [3/3]

__IO uint32_t { ... } ::RTSBLIM

RNG TRNG Sparse Bit Limit Register, offset: 0x614

◆  [1/3]

__I uint32_t { ... } ::RTSCMC

RNG TRNG Statistical Check Monobit Count Register, offset: 0x620

◆ RTSCMC [2/3]

__I uint32_t CAAM_Type::RTSCMC

RNG TRNG Statistical Check Monobit Count Register, offset: 0x620

◆  [3/3]

__I uint32_t { ... } ::RTSCMC

RNG TRNG Statistical Check Monobit Count Register, offset: 0x620

◆ RTSCMISC

__IO uint32_t CAAM_Type::RTSCMISC

RNG TRNG Statistical Check Miscellaneous Register, offset: 0x604

◆  [1/3]

__IO uint32_t { ... } ::RTSCML

RNG TRNG Statistical Check Monobit Limit Register, offset: 0x620

◆ RTSCML [2/3]

__IO uint32_t CAAM_Type::RTSCML

RNG TRNG Statistical Check Monobit Limit Register, offset: 0x620

◆  [3/3]

__IO uint32_t { ... } ::RTSCML

RNG TRNG Statistical Check Monobit Limit Register, offset: 0x620

◆  [1/3]

__I uint32_t { ... } ::RTSCR1C

RNG TRNG Statistical Check Run Length 1 Count Register, offset: 0x624

◆ RTSCR1C [2/3]

__I uint32_t CAAM_Type::RTSCR1C

RNG TRNG Statistical Check Run Length 1 Count Register, offset: 0x624

◆  [3/3]

__I uint32_t { ... } ::RTSCR1C

RNG TRNG Statistical Check Run Length 1 Count Register, offset: 0x624

◆ RTSCR1L [1/3]

__IO uint32_t CAAM_Type::RTSCR1L

RNG TRNG Statistical Check Run Length 1 Limit Register, offset: 0x624

◆  [2/3]

__IO uint32_t { ... } ::RTSCR1L

RNG TRNG Statistical Check Run Length 1 Limit Register, offset: 0x624

◆  [3/3]

__IO uint32_t { ... } ::RTSCR1L

RNG TRNG Statistical Check Run Length 1 Limit Register, offset: 0x624

◆ RTSCR2C [1/3]

__I uint32_t CAAM_Type::RTSCR2C

RNG TRNG Statistical Check Run Length 2 Count Register, offset: 0x628

◆  [2/3]

__I uint32_t { ... } ::RTSCR2C

RNG TRNG Statistical Check Run Length 2 Count Register, offset: 0x628

◆  [3/3]

__I uint32_t { ... } ::RTSCR2C

RNG TRNG Statistical Check Run Length 2 Count Register, offset: 0x628

◆ RTSCR2L [1/3]

__IO uint32_t CAAM_Type::RTSCR2L

RNG TRNG Statistical Check Run Length 2 Limit Register, offset: 0x628

◆  [2/3]

__IO uint32_t { ... } ::RTSCR2L

RNG TRNG Statistical Check Run Length 2 Limit Register, offset: 0x628

◆  [3/3]

__IO uint32_t { ... } ::RTSCR2L

RNG TRNG Statistical Check Run Length 2 Limit Register, offset: 0x628

◆ RTSCR3C [1/3]

__I uint32_t CAAM_Type::RTSCR3C

RNG TRNG Statistical Check Run Length 3 Count Register, offset: 0x62C

◆  [2/3]

__I uint32_t { ... } ::RTSCR3C

RNG TRNG Statistical Check Run Length 3 Count Register, offset: 0x62C

◆  [3/3]

__I uint32_t { ... } ::RTSCR3C

RNG TRNG Statistical Check Run Length 3 Count Register, offset: 0x62C

◆  [1/3]

__IO uint32_t { ... } ::RTSCR3L

RNG TRNG Statistical Check Run Length 3 Limit Register, offset: 0x62C

◆ RTSCR3L [2/3]

__IO uint32_t CAAM_Type::RTSCR3L

RNG TRNG Statistical Check Run Length 3 Limit Register, offset: 0x62C

◆  [3/3]

__IO uint32_t { ... } ::RTSCR3L

RNG TRNG Statistical Check Run Length 3 Limit Register, offset: 0x62C

◆ RTSCR4C [1/3]

__I uint32_t CAAM_Type::RTSCR4C

RNG TRNG Statistical Check Run Length 4 Count Register, offset: 0x630

◆  [2/3]

__I uint32_t { ... } ::RTSCR4C

RNG TRNG Statistical Check Run Length 4 Count Register, offset: 0x630

◆  [3/3]

__I uint32_t { ... } ::RTSCR4C

RNG TRNG Statistical Check Run Length 4 Count Register, offset: 0x630

◆ RTSCR4L [1/3]

__IO uint32_t CAAM_Type::RTSCR4L

RNG TRNG Statistical Check Run Length 4 Limit Register, offset: 0x630

◆  [2/3]

__IO uint32_t { ... } ::RTSCR4L

RNG TRNG Statistical Check Run Length 4 Limit Register, offset: 0x630

◆  [3/3]

__IO uint32_t { ... } ::RTSCR4L

RNG TRNG Statistical Check Run Length 4 Limit Register, offset: 0x630

◆ RTSCR5C [1/3]

__I uint32_t CAAM_Type::RTSCR5C

RNG TRNG Statistical Check Run Length 5 Count Register, offset: 0x634

◆  [2/3]

__I uint32_t { ... } ::RTSCR5C

RNG TRNG Statistical Check Run Length 5 Count Register, offset: 0x634

◆  [3/3]

__I uint32_t { ... } ::RTSCR5C

RNG TRNG Statistical Check Run Length 5 Count Register, offset: 0x634

◆  [1/3]

__IO uint32_t { ... } ::RTSCR5L

RNG TRNG Statistical Check Run Length 5 Limit Register, offset: 0x634

◆ RTSCR5L [2/3]

__IO uint32_t CAAM_Type::RTSCR5L

RNG TRNG Statistical Check Run Length 5 Limit Register, offset: 0x634

◆  [3/3]

__IO uint32_t { ... } ::RTSCR5L

RNG TRNG Statistical Check Run Length 5 Limit Register, offset: 0x634

◆ RTSCR6PC [1/3]

__I uint32_t CAAM_Type::RTSCR6PC

RNG TRNG Statistical Check Run Length 6+ Count Register, offset: 0x638

◆  [2/3]

__I uint32_t { ... } ::RTSCR6PC

RNG TRNG Statistical Check Run Length 6+ Count Register, offset: 0x638

◆  [3/3]

__I uint32_t { ... } ::RTSCR6PC

RNG TRNG Statistical Check Run Length 6+ Count Register, offset: 0x638

◆ RTSCR6PL [1/3]

__IO uint32_t CAAM_Type::RTSCR6PL

RNG TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x638

◆  [2/3]

__IO uint32_t { ... } ::RTSCR6PL

RNG TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x638

◆  [3/3]

__IO uint32_t { ... } ::RTSCR6PL

RNG TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x638

◆ RTSDCTL

__IO uint32_t CAAM_Type::RTSDCTL

RNG TRNG Seed Control Register, offset: 0x610

◆ RTSTATUS

__I uint32_t CAAM_Type::RTSTATUS

RNG TRNG Status Register, offset: 0x63C

◆ RTTOTSAM [1/3]

__I uint32_t CAAM_Type::RTTOTSAM

RNG TRNG Total Samples Register, offset: 0x614

◆  [2/3]

__I uint32_t { ... } ::RTTOTSAM

RNG TRNG Total Samples Register, offset: 0x614

◆  [3/3]

__I uint32_t { ... } ::RTTOTSAM

RNG TRNG Total Samples Register, offset: 0x614

◆ RVID

__I uint32_t CAAM_Type::RVID

RTIC Version ID Register, offset: 0xFE0

◆ RVID_DC01

__I uint32_t CAAM_Type::RVID_DC01

RTIC Version ID Register, offset: 0x80FE0

◆  [1/3]

__I uint32_t { ... } ::RVID_JR

RTIC Version ID Register, array offset: 0x10FE0, array step: 0x10000

◆ RVID_JR [2/3]

__I uint32_t CAAM_Type::RVID_JR

RTIC Version ID Register, array offset: 0x10FE0, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::RVID_JR

RTIC Version ID Register, array offset: 0x10FE0, array step: 0x10000

◆ RVID_RTIC

__I uint32_t CAAM_Type::RVID_RTIC

RTIC Version ID Register, offset: 0x60FE0

◆ RW [1/66]

__IO uint32_t AUDIO_PLL_Type::RW

Fractional PLL Control Register, offset: 0x0

Fractional PLL Spread Spectrum Control Register, offset: 0x10

Fractional PLL Numerator Control Register, offset: 0x20

Fractional PLL Denominator Control Register, offset: 0x30

◆  [2/66]

__IO uint32_t { ... } ::RW

Fractional PLL Control Register, offset: 0x0

◆  [3/66]

__IO uint32_t { ... } ::RW

Fractional PLL Spread Spectrum Control Register, offset: 0x10

◆  [4/66]

__IO uint32_t { ... } ::RW

Fractional PLL Numerator Control Register, offset: 0x20

◆  [5/66]

__IO uint32_t { ... } ::RW

Fractional PLL Denominator Control Register, offset: 0x30

◆  [6/66]

__IO uint32_t { ... } ::RW

Fractional PLL Control Register, offset: 0x0

◆ RW [7/66]

__IO uint32_t ETHERNET_PLL_Type::RW

Fractional PLL Control Register, offset: 0x0

Fractional PLL Spread Spectrum Control Register, offset: 0x10

Fractional PLL Numerator Control Register, offset: 0x20

Fractional PLL Denominator Control Register, offset: 0x30

◆  [8/66]

__IO uint32_t { ... } ::RW

Fractional PLL Spread Spectrum Control Register, offset: 0x10

◆  [9/66]

__IO uint32_t { ... } ::RW

Fractional PLL Numerator Control Register, offset: 0x20

◆  [10/66]

__IO uint32_t { ... } ::RW

Fractional PLL Denominator Control Register, offset: 0x30

◆ RW [11/66]

__IO uint32_t OSC_RC_400M_Type::RW

Control Register 0, offset: 0x0

Control Register 1, offset: 0x10

Control Register 2, offset: 0x20

Control Register 3, offset: 0x30

◆  [12/66]

__IO uint32_t { ... } ::RW

Control Register 0, offset: 0x0

◆  [13/66]

__IO uint32_t { ... } ::RW

Control Register 1, offset: 0x10

◆  [14/66]

__IO uint32_t { ... } ::RW

Control Register 2, offset: 0x20

◆  [15/66]

__IO uint32_t { ... } ::RW

Control Register 3, offset: 0x30

◆  [16/66]

__I uint32_t { ... } ::RW

Status Register 0, offset: 0x50

◆ RW [17/66]

__I uint32_t OSC_RC_400M_Type::RW

Status Register 0, offset: 0x50

Status Register 1, offset: 0x60

Status Register 2, offset: 0x70

◆  [18/66]

__I uint32_t { ... } ::RW

Status Register 1, offset: 0x60

◆  [19/66]

__I uint32_t { ... } ::RW

Status Register 2, offset: 0x70

◆  [20/66]

__IO uint32_t { ... } ::RW

Analog Control Register CTRL0, offset: 0x0

◆ RW [21/66]

__IO uint32_t PHY_LDO_Type::RW

Analog Control Register CTRL0, offset: 0x0

◆ RW [22/66]

__I uint32_t PHY_LDO_Type::RW

Analog Status Register STAT0, offset: 0x50

◆  [23/66]

__I uint32_t { ... } ::RW

Analog Status Register STAT0, offset: 0x50

◆ RW [24/66]

__IO uint32_t VIDEO_MUX_Type::RW

Video mux Control Register, offset: 0x0

Pixel Link Master(PLM) Control Register, offset: 0x20

YUV420 Control Register, offset: 0x30

Data Disable Register, offset: 0x50

MIPI DSI Control Register, offset: 0x70

◆  [25/66]

__IO uint32_t { ... } ::RW

Video mux Control Register, offset: 0x0

◆  [26/66]

__IO uint32_t { ... } ::RW

Pixel Link Master(PLM) Control Register, offset: 0x20

◆  [27/66]

__IO uint32_t { ... } ::RW

YUV420 Control Register, offset: 0x30

◆  [28/66]

__IO uint32_t { ... } ::RW

Data Disable Register, offset: 0x50

◆  [29/66]

__IO uint32_t { ... } ::RW

MIPI DSI Control Register, offset: 0x70

◆ RW [30/66]

__IO uint32_t VIDEO_PLL_Type::RW

Fractional PLL Control Register, offset: 0x0

Fractional PLL Spread Spectrum Control Register, offset: 0x10

Fractional PLL Numerator Control Register, offset: 0x20

Fractional PLL Denominator Control Register, offset: 0x30

◆  [31/66]

__IO uint32_t { ... } ::RW

Fractional PLL Control Register, offset: 0x0

◆  [32/66]

__IO uint32_t { ... } ::RW

Fractional PLL Spread Spectrum Control Register, offset: 0x10

◆  [33/66]

__IO uint32_t { ... } ::RW

Fractional PLL Numerator Control Register, offset: 0x20

◆  [34/66]

__IO uint32_t { ... } ::RW

Fractional PLL Denominator Control Register, offset: 0x30

◆  [35/66]

__IO uint32_t { ... } ::RW

Analog Control Register CTRL0, offset: 0x0

◆ RW [36/66]

__IO uint32_t VMBANDGAP_Type::RW

Analog Control Register CTRL0, offset: 0x0

◆  [37/66]

__I uint32_t { ... } ::RW

Analog Status Register STAT0, offset: 0x50

◆ RW [38/66]

__I uint32_t VMBANDGAP_Type::RW

Analog Status Register STAT0, offset: 0x50

◆  [39/66]

__IO uint32_t { ... } ::RW

Fractional PLL Control Register, offset: 0x0

◆  [40/66]

__IO uint32_t { ... } ::RW

Fractional PLL Spread Spectrum Control Register, offset: 0x10

◆  [41/66]

__IO uint32_t { ... } ::RW

Fractional PLL Numerator Control Register, offset: 0x20

◆  [42/66]

__IO uint32_t { ... } ::RW

Fractional PLL Denominator Control Register, offset: 0x30

◆  [43/66]

__IO uint32_t { ... } ::RW

Fractional PLL Control Register, offset: 0x0

◆  [44/66]

__IO uint32_t { ... } ::RW

Fractional PLL Spread Spectrum Control Register, offset: 0x10

◆  [45/66]

__IO uint32_t { ... } ::RW

Fractional PLL Numerator Control Register, offset: 0x20

◆  [46/66]

__IO uint32_t { ... } ::RW

Fractional PLL Denominator Control Register, offset: 0x30

◆  [47/66]

__IO uint32_t { ... } ::RW

Control Register 0, offset: 0x0

◆  [48/66]

__IO uint32_t { ... } ::RW

Control Register 1, offset: 0x10

◆  [49/66]

__IO uint32_t { ... } ::RW

Control Register 2, offset: 0x20

◆  [50/66]

__IO uint32_t { ... } ::RW

Control Register 3, offset: 0x30

◆  [51/66]

__I uint32_t { ... } ::RW

Status Register 0, offset: 0x50

◆  [52/66]

__I uint32_t { ... } ::RW

Status Register 1, offset: 0x60

◆  [53/66]

__I uint32_t { ... } ::RW

Status Register 2, offset: 0x70

◆  [54/66]

__IO uint32_t { ... } ::RW

Analog Control Register CTRL0, offset: 0x0

◆  [55/66]

__I uint32_t { ... } ::RW

Analog Status Register STAT0, offset: 0x50

◆  [56/66]

__IO uint32_t { ... } ::RW

Video mux Control Register, offset: 0x0

◆  [57/66]

__IO uint32_t { ... } ::RW

Pixel Link Master(PLM) Control Register, offset: 0x20

◆  [58/66]

__IO uint32_t { ... } ::RW

YUV420 Control Register, offset: 0x30

◆  [59/66]

__IO uint32_t { ... } ::RW

Data Disable Register, offset: 0x50

◆  [60/66]

__IO uint32_t { ... } ::RW

MIPI DSI Control Register, offset: 0x70

◆  [61/66]

__IO uint32_t { ... } ::RW

Fractional PLL Control Register, offset: 0x0

◆  [62/66]

__IO uint32_t { ... } ::RW

Fractional PLL Spread Spectrum Control Register, offset: 0x10

◆  [63/66]

__IO uint32_t { ... } ::RW

Fractional PLL Numerator Control Register, offset: 0x20

◆  [64/66]

__IO uint32_t { ... } ::RW

Fractional PLL Denominator Control Register, offset: 0x30

◆  [65/66]

__IO uint32_t { ... } ::RW

Analog Control Register CTRL0, offset: 0x0

◆  [66/66]

__I uint32_t { ... } ::RW

Analog Status Register STAT0, offset: 0x50

◆ RWDOG

__IO uint64_t CAAM_Type::RWDOG

RTIC Watchdog Timer, offset: 0x60028

◆ RX

__IO uint32_t USBPHY_Type::RX

USB PHY Receiver Control Register, offset: 0x20

◆ RX14MASK

__IO uint32_t CAN_Type::RX14MASK

Rx Buffer 14 Mask Register, offset: 0x14

Rx 14 Mask register, offset: 0x14

◆ RX15MASK

__IO uint32_t CAN_Type::RX15MASK

Rx Buffer 15 Mask Register, offset: 0x18

Rx 15 Mask register, offset: 0x18

◆ RX_BUF

__I uint32_t EMVSIM_Type::RX_BUF

Receive Data Read Buffer, offset: 0x2C

◆ RX_CLR

__IO uint32_t USBPHY_Type::RX_CLR

USB PHY Receiver Control Register, offset: 0x28

◆ RX_ERROR_STATUS

__I uint32_t DSI_HOST_Type::RX_ERROR_STATUS

RX_ERROR_STATUS, offset: 0x30

◆ RX_SET

__IO uint32_t USBPHY_Type::RX_SET

USB PHY Receiver Control Register, offset: 0x24

◆ RX_STATUS

__IO uint32_t EMVSIM_Type::RX_STATUS

Receive Status Register, offset: 0x20

◆ RX_THD

__IO uint32_t EMVSIM_Type::RX_THD

Receiver Threshold Register, offset: 0x18

◆ RX_TOG

__IO uint32_t USBPHY_Type::RX_TOG

USB PHY Receiver Control Register, offset: 0x2C

◆ RXCDRP

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::RXCDRP

RXCDRP, offset: 0x44

◆ RXCNT

__IO uint32_t CSI_Type::RXCNT

CSI RX Count Register, offset: 0x14

◆ RXFGMASK

__IO uint32_t CAN_Type::RXFGMASK

Rx FIFO Global Mask Register, offset: 0x48

Rx FIFO Global Mask register, offset: 0x48

◆ RXFIR

__I uint32_t CAN_Type::RXFIR

Rx FIFO Information Register, offset: 0x4C

Rx FIFO Information register, offset: 0x4C

◆ RXIC

__IO uint32_t ENET_Type::RXIC

Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4

◆ RXIMR

__IO uint32_t CAN_Type::RXIMR

Rx Individual Mask Registers, array offset: 0x880, array step: 0x4

Rx Individual Mask registers, array offset: 0x880, array step: 0x4

◆ RXLPRP

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::RXLPRP

RXLPRP, offset: 0x40

◆ RXMGMASK

__IO uint32_t CAN_Type::RXMGMASK

Rx Mailboxes Global Mask Register, offset: 0x10

Rx Mailboxes Global Mask register, offset: 0x10

◆ SA

__IO uint32_t CSU_Type::SA

Secure access register, offset: 0x218

◆ SADDR [1/4]

__IO uint32_t DMA_Type::SADDR

TCD Source Address, array offset: 0x1000, array step: 0x20

◆  [2/4]

__IO uint32_t { ... } ::SADDR

TCD Source Address, array offset: 0x1000, array step: 0x20

◆  [3/4]

__IO uint32_t { ... } ::SADDR

TCD Source Address, array offset: 0x1000, array step: 0x20

◆  [4/4]

__IO uint32_t { ... } ::SADDR

TCD Source Address, array offset: 0x1000, array step: 0x20

◆ SAMR

__IO uint32_t LPI2C_Type::SAMR

Slave Address Match Register, offset: 0x140

Slave Address Match, offset: 0x140

◆ SASR

__I uint32_t LPI2C_Type::SASR

Slave Address Status Register, offset: 0x150

Slave Address Status, offset: 0x150

◆  [1/2]

__IO uint32_t { ... } ::SBLIM

Sparse Bit Limit Register, offset: 0x14

◆ SBLIM [2/2]

__IO uint32_t TRNG_Type::SBLIM

Sparse Bit Limit Register, offset: 0x14

◆ SBMR1

__I uint32_t SRC_Type::SBMR1

SRC Boot Mode Register 1, offset: 0x4

SRC Boot Mode Register 1, offset: 0x8

◆ SBMR2

__I uint32_t SRC_Type::SBMR2

SRC Boot Mode Register 2, offset: 0x1C

SRC Boot Mode Register 2, offset: 0xC

◆ SBUSCFG

__IO uint32_t USB_Type::SBUSCFG

System Bus Config, offset: 0x90

◆ SCFGR

__IO uint32_t CAAM_Type::SCFGR

Security Configuration Register, offset: 0xC

◆ SCFGR1

__IO uint32_t LPI2C_Type::SCFGR1

Slave Configuration Register 1, offset: 0x124

Slave Configuration 1, offset: 0x124

◆ SCFGR2

__IO uint32_t LPI2C_Type::SCFGR2

Slave Configuration Register 2, offset: 0x128

Slave Configuration 2, offset: 0x128

◆ SCMC [1/2]

__I uint32_t TRNG_Type::SCMC

Statistical Check Monobit Count Register, offset: 0x20

◆  [2/2]

__I uint32_t { ... } ::SCMC

Statistical Check Monobit Count Register, offset: 0x20

◆ SCMISC

__IO uint32_t TRNG_Type::SCMISC

Statistical Check Miscellaneous Register, offset: 0x4

◆ SCML [1/2]

__IO uint32_t TRNG_Type::SCML

Statistical Check Monobit Limit Register, offset: 0x20

◆  [2/2]

__IO uint32_t { ... } ::SCML

Statistical Check Monobit Limit Register, offset: 0x20

◆ SCR [1/4]

__IO uint8_t CMP_Type::SCR

CMP Status and Control Register, offset: 0x3

◆ SCR [2/4]

__IO uint32_t LPI2C_Type::SCR

Slave Control Register, offset: 0x110

Slave Control, offset: 0x110

◆ SCR [3/4]

__IO uint32_t SPDIF_Type::SCR

SPDIF Configuration Register, offset: 0x0

◆ SCR [4/4]

__IO uint32_t SRC_Type::SCR

SRC Control Register, offset: 0x0

◆ SCR1C [1/2]

__I uint32_t TRNG_Type::SCR1C

Statistical Check Run Length 1 Count Register, offset: 0x24

◆  [2/2]

__I uint32_t { ... } ::SCR1C

Statistical Check Run Length 1 Count Register, offset: 0x24

◆ SCR1L [1/2]

__IO uint32_t TRNG_Type::SCR1L

Statistical Check Run Length 1 Limit Register, offset: 0x24

◆  [2/2]

__IO uint32_t { ... } ::SCR1L

Statistical Check Run Length 1 Limit Register, offset: 0x24

◆ SCR2C [1/2]

__I uint32_t TRNG_Type::SCR2C

Statistical Check Run Length 2 Count Register, offset: 0x28

◆  [2/2]

__I uint32_t { ... } ::SCR2C

Statistical Check Run Length 2 Count Register, offset: 0x28

◆ SCR2L [1/2]

__IO uint32_t TRNG_Type::SCR2L

Statistical Check Run Length 2 Limit Register, offset: 0x28

◆  [2/2]

__IO uint32_t { ... } ::SCR2L

Statistical Check Run Length 2 Limit Register, offset: 0x28

◆  [1/2]

__I uint32_t { ... } ::SCR3C

Statistical Check Run Length 3 Count Register, offset: 0x2C

◆ SCR3C [2/2]

__I uint32_t TRNG_Type::SCR3C

Statistical Check Run Length 3 Count Register, offset: 0x2C

◆  [1/2]

__IO uint32_t { ... } ::SCR3L

Statistical Check Run Length 3 Limit Register, offset: 0x2C

◆ SCR3L [2/2]

__IO uint32_t TRNG_Type::SCR3L

Statistical Check Run Length 3 Limit Register, offset: 0x2C

◆ SCR4C [1/2]

__I uint32_t TRNG_Type::SCR4C

Statistical Check Run Length 4 Count Register, offset: 0x30

◆  [2/2]

__I uint32_t { ... } ::SCR4C

Statistical Check Run Length 4 Count Register, offset: 0x30

◆ SCR4L [1/2]

__IO uint32_t TRNG_Type::SCR4L

Statistical Check Run Length 4 Limit Register, offset: 0x30

◆  [2/2]

__IO uint32_t { ... } ::SCR4L

Statistical Check Run Length 4 Limit Register, offset: 0x30

◆  [1/2]

__I uint32_t { ... } ::SCR5C

Statistical Check Run Length 5 Count Register, offset: 0x34

◆ SCR5C [2/2]

__I uint32_t TRNG_Type::SCR5C

Statistical Check Run Length 5 Count Register, offset: 0x34

◆  [1/2]

__IO uint32_t { ... } ::SCR5L

Statistical Check Run Length 5 Limit Register, offset: 0x34

◆ SCR5L [2/2]

__IO uint32_t TRNG_Type::SCR5L

Statistical Check Run Length 5 Limit Register, offset: 0x34

◆ SCR6PC [1/2]

__I uint32_t TRNG_Type::SCR6PC

Statistical Check Run Length 6+ Count Register, offset: 0x38

◆  [2/2]

__I uint32_t { ... } ::SCR6PC

Statistical Check Run Length 6+ Count Register, offset: 0x38

◆ SCR6PL [1/2]

__IO uint32_t TRNG_Type::SCR6PL

Statistical Check Run Length 6+ Limit Register, offset: 0x38

◆  [2/2]

__IO uint32_t { ... } ::SCR6PL

Statistical Check Run Length 6+ Limit Register, offset: 0x38

◆ SCS

__IO uint32_t OCOTP_Type::SCS

Software Controllable Signals Register, offset: 0x60

◆ SCS_CLR

__IO uint32_t OCOTP_Type::SCS_CLR

Software Controllable Signals Register, offset: 0x68

◆ SCS_SET

__IO uint32_t OCOTP_Type::SCS_SET

Software Controllable Signals Register, offset: 0x64

◆ SCS_TOG

__IO uint32_t OCOTP_Type::SCS_TOG

Software Controllable Signals Register, offset: 0x6C

◆  [1/4]

__IO uint16_t { ... } ::SCTRL

Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20

◆ SCTRL [2/4]

__IO uint16_t TMR_Type::SCTRL

Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::SCTRL

Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::SCTRL

Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20

◆ SDCTL

__IO uint32_t TRNG_Type::SDCTL

Seed Control Register, offset: 0x10

◆ SDER

__IO uint32_t LPI2C_Type::SDER

Slave DMA Enable Register, offset: 0x11C

Slave DMA Enable, offset: 0x11C

◆ SDRAMCR0

__IO uint32_t SEMC_Type::SDRAMCR0

SDRAM control register 0, offset: 0x40

SDRAM Control Register 0, offset: 0x40

◆ SDRAMCR1

__IO uint32_t SEMC_Type::SDRAMCR1

SDRAM control register 1, offset: 0x44

SDRAM Control Register 1, offset: 0x44

◆ SDRAMCR2

__IO uint32_t SEMC_Type::SDRAMCR2

SDRAM control register 2, offset: 0x48

SDRAM Control Register 2, offset: 0x48

◆ SDRAMCR3

__IO uint32_t SEMC_Type::SDRAMCR3

SDRAM control register 3, offset: 0x4C

SDRAM Control Register 3, offset: 0x4C

◆ SEC_CFG

__IO uint32_t TRNG_Type::SEC_CFG

Security Configuration Register, offset: 0xA0

◆ SECURE_COUNTER

__O uint32_t CDOG_Type::SECURE_COUNTER

Secure Counter, offset: 0xC

◆ SEEI

__O uint8_t DMA_Type::SEEI

Set Enable Error Interrupt, offset: 0x19

◆ SEL0 [1/2]

__IO uint16_t XBARA_Type::SEL0

Crossbar A Select Register 0, offset: 0x0

◆ SEL0 [2/2]

__IO uint16_t XBARB_Type::SEL0

Crossbar B Select Register 0, offset: 0x0

◆ SEL1 [1/2]

__IO uint16_t XBARA_Type::SEL1

Crossbar A Select Register 1, offset: 0x2

◆ SEL1 [2/2]

__IO uint16_t XBARB_Type::SEL1

Crossbar B Select Register 1, offset: 0x2

◆ SEL10

__IO uint16_t XBARA_Type::SEL10

Crossbar A Select Register 10, offset: 0x14

◆ SEL11

__IO uint16_t XBARA_Type::SEL11

Crossbar A Select Register 11, offset: 0x16

◆ SEL12

__IO uint16_t XBARA_Type::SEL12

Crossbar A Select Register 12, offset: 0x18

◆ SEL13

__IO uint16_t XBARA_Type::SEL13

Crossbar A Select Register 13, offset: 0x1A

◆ SEL14

__IO uint16_t XBARA_Type::SEL14

Crossbar A Select Register 14, offset: 0x1C

◆ SEL15

__IO uint16_t XBARA_Type::SEL15

Crossbar A Select Register 15, offset: 0x1E

◆ SEL16

__IO uint16_t XBARA_Type::SEL16

Crossbar A Select Register 16, offset: 0x20

◆ SEL17

__IO uint16_t XBARA_Type::SEL17

Crossbar A Select Register 17, offset: 0x22

◆ SEL18

__IO uint16_t XBARA_Type::SEL18

Crossbar A Select Register 18, offset: 0x24

◆ SEL19

__IO uint16_t XBARA_Type::SEL19

Crossbar A Select Register 19, offset: 0x26

◆ SEL2 [1/2]

__IO uint16_t XBARA_Type::SEL2

Crossbar A Select Register 2, offset: 0x4

◆ SEL2 [2/2]

__IO uint16_t XBARB_Type::SEL2

Crossbar B Select Register 2, offset: 0x4

◆ SEL20

__IO uint16_t XBARA_Type::SEL20

Crossbar A Select Register 20, offset: 0x28

◆ SEL21

__IO uint16_t XBARA_Type::SEL21

Crossbar A Select Register 21, offset: 0x2A

◆ SEL22

__IO uint16_t XBARA_Type::SEL22

Crossbar A Select Register 22, offset: 0x2C

◆ SEL23

__IO uint16_t XBARA_Type::SEL23

Crossbar A Select Register 23, offset: 0x2E

◆ SEL24

__IO uint16_t XBARA_Type::SEL24

Crossbar A Select Register 24, offset: 0x30

◆ SEL25

__IO uint16_t XBARA_Type::SEL25

Crossbar A Select Register 25, offset: 0x32

◆ SEL26

__IO uint16_t XBARA_Type::SEL26

Crossbar A Select Register 26, offset: 0x34

◆ SEL27

__IO uint16_t XBARA_Type::SEL27

Crossbar A Select Register 27, offset: 0x36

◆ SEL28

__IO uint16_t XBARA_Type::SEL28

Crossbar A Select Register 28, offset: 0x38

◆ SEL29

__IO uint16_t XBARA_Type::SEL29

Crossbar A Select Register 29, offset: 0x3A

◆ SEL3 [1/2]

__IO uint16_t XBARA_Type::SEL3

Crossbar A Select Register 3, offset: 0x6

◆ SEL3 [2/2]

__IO uint16_t XBARB_Type::SEL3

Crossbar B Select Register 3, offset: 0x6

◆ SEL30

__IO uint16_t XBARA_Type::SEL30

Crossbar A Select Register 30, offset: 0x3C

◆ SEL31

__IO uint16_t XBARA_Type::SEL31

Crossbar A Select Register 31, offset: 0x3E

◆ SEL32

__IO uint16_t XBARA_Type::SEL32

Crossbar A Select Register 32, offset: 0x40

◆ SEL33

__IO uint16_t XBARA_Type::SEL33

Crossbar A Select Register 33, offset: 0x42

◆ SEL34

__IO uint16_t XBARA_Type::SEL34

Crossbar A Select Register 34, offset: 0x44

◆ SEL35

__IO uint16_t XBARA_Type::SEL35

Crossbar A Select Register 35, offset: 0x46

◆ SEL36

__IO uint16_t XBARA_Type::SEL36

Crossbar A Select Register 36, offset: 0x48

◆ SEL37

__IO uint16_t XBARA_Type::SEL37

Crossbar A Select Register 37, offset: 0x4A

◆ SEL38

__IO uint16_t XBARA_Type::SEL38

Crossbar A Select Register 38, offset: 0x4C

◆ SEL39

__IO uint16_t XBARA_Type::SEL39

Crossbar A Select Register 39, offset: 0x4E

◆ SEL4 [1/2]

__IO uint16_t XBARA_Type::SEL4

Crossbar A Select Register 4, offset: 0x8

◆ SEL4 [2/2]

__IO uint16_t XBARB_Type::SEL4

Crossbar B Select Register 4, offset: 0x8

◆ SEL40

__IO uint16_t XBARA_Type::SEL40

Crossbar A Select Register 40, offset: 0x50

◆ SEL41

__IO uint16_t XBARA_Type::SEL41

Crossbar A Select Register 41, offset: 0x52

◆ SEL42

__IO uint16_t XBARA_Type::SEL42

Crossbar A Select Register 42, offset: 0x54

◆ SEL43

__IO uint16_t XBARA_Type::SEL43

Crossbar A Select Register 43, offset: 0x56

◆ SEL44

__IO uint16_t XBARA_Type::SEL44

Crossbar A Select Register 44, offset: 0x58

◆ SEL45

__IO uint16_t XBARA_Type::SEL45

Crossbar A Select Register 45, offset: 0x5A

◆ SEL46

__IO uint16_t XBARA_Type::SEL46

Crossbar A Select Register 46, offset: 0x5C

◆ SEL47

__IO uint16_t XBARA_Type::SEL47

Crossbar A Select Register 47, offset: 0x5E

◆ SEL48

__IO uint16_t XBARA_Type::SEL48

Crossbar A Select Register 48, offset: 0x60

◆ SEL49

__IO uint16_t XBARA_Type::SEL49

Crossbar A Select Register 49, offset: 0x62

◆ SEL5 [1/2]

__IO uint16_t XBARA_Type::SEL5

Crossbar A Select Register 5, offset: 0xA

◆ SEL5 [2/2]

__IO uint16_t XBARB_Type::SEL5

Crossbar B Select Register 5, offset: 0xA

◆ SEL50

__IO uint16_t XBARA_Type::SEL50

Crossbar A Select Register 50, offset: 0x64

◆ SEL51

__IO uint16_t XBARA_Type::SEL51

Crossbar A Select Register 51, offset: 0x66

◆ SEL52

__IO uint16_t XBARA_Type::SEL52

Crossbar A Select Register 52, offset: 0x68

◆ SEL53

__IO uint16_t XBARA_Type::SEL53

Crossbar A Select Register 53, offset: 0x6A

◆ SEL54

__IO uint16_t XBARA_Type::SEL54

Crossbar A Select Register 54, offset: 0x6C

◆ SEL55

__IO uint16_t XBARA_Type::SEL55

Crossbar A Select Register 55, offset: 0x6E

◆ SEL56

__IO uint16_t XBARA_Type::SEL56

Crossbar A Select Register 56, offset: 0x70

◆ SEL57

__IO uint16_t XBARA_Type::SEL57

Crossbar A Select Register 57, offset: 0x72

◆ SEL58

__IO uint16_t XBARA_Type::SEL58

Crossbar A Select Register 58, offset: 0x74

◆ SEL59

__IO uint16_t XBARA_Type::SEL59

Crossbar A Select Register 59, offset: 0x76

◆ SEL6 [1/2]

__IO uint16_t XBARA_Type::SEL6

Crossbar A Select Register 6, offset: 0xC

◆ SEL6 [2/2]

__IO uint16_t XBARB_Type::SEL6

Crossbar B Select Register 6, offset: 0xC

◆ SEL60

__IO uint16_t XBARA_Type::SEL60

Crossbar A Select Register 60, offset: 0x78

◆ SEL61

__IO uint16_t XBARA_Type::SEL61

Crossbar A Select Register 61, offset: 0x7A

◆ SEL62

__IO uint16_t XBARA_Type::SEL62

Crossbar A Select Register 62, offset: 0x7C

◆ SEL63

__IO uint16_t XBARA_Type::SEL63

Crossbar A Select Register 63, offset: 0x7E

◆ SEL64

__IO uint16_t XBARA_Type::SEL64

Crossbar A Select Register 64, offset: 0x80

◆ SEL65

__IO uint16_t XBARA_Type::SEL65

Crossbar A Select Register 65, offset: 0x82

◆ SEL66

__IO uint16_t XBARA_Type::SEL66

Crossbar A Select Register 66, offset: 0x84

◆ SEL67

__IO uint16_t XBARA_Type::SEL67

Crossbar A Select Register 67, offset: 0x86

◆ SEL68

__IO uint16_t XBARA_Type::SEL68

Crossbar A Select Register 68, offset: 0x88

◆ SEL69

__IO uint16_t XBARA_Type::SEL69

Crossbar A Select Register 69, offset: 0x8A

◆ SEL7 [1/2]

__IO uint16_t XBARA_Type::SEL7

Crossbar A Select Register 7, offset: 0xE

◆ SEL7 [2/2]

__IO uint16_t XBARB_Type::SEL7

Crossbar B Select Register 7, offset: 0xE

◆ SEL70

__IO uint16_t XBARA_Type::SEL70

Crossbar A Select Register 70, offset: 0x8C

◆ SEL71

__IO uint16_t XBARA_Type::SEL71

Crossbar A Select Register 71, offset: 0x8E

◆ SEL72

__IO uint16_t XBARA_Type::SEL72

Crossbar A Select Register 72, offset: 0x90

◆ SEL73

__IO uint16_t XBARA_Type::SEL73

Crossbar A Select Register 73, offset: 0x92

◆ SEL74

__IO uint16_t XBARA_Type::SEL74

Crossbar A Select Register 74, offset: 0x94

◆ SEL75

__IO uint16_t XBARA_Type::SEL75

Crossbar A Select Register 75, offset: 0x96

◆ SEL76

__IO uint16_t XBARA_Type::SEL76

Crossbar A Select Register 76, offset: 0x98

◆ SEL77

__IO uint16_t XBARA_Type::SEL77

Crossbar A Select Register 77, offset: 0x9A

◆ SEL78

__IO uint16_t XBARA_Type::SEL78

Crossbar A Select Register 78, offset: 0x9C

◆ SEL79

__IO uint16_t XBARA_Type::SEL79

Crossbar A Select Register 79, offset: 0x9E

◆ SEL8

__IO uint16_t XBARA_Type::SEL8

Crossbar A Select Register 8, offset: 0x10

◆ SEL80

__IO uint16_t XBARA_Type::SEL80

Crossbar A Select Register 80, offset: 0xA0

◆ SEL81

__IO uint16_t XBARA_Type::SEL81

Crossbar A Select Register 81, offset: 0xA2

◆ SEL82

__IO uint16_t XBARA_Type::SEL82

Crossbar A Select Register 82, offset: 0xA4

◆ SEL83

__IO uint16_t XBARA_Type::SEL83

Crossbar A Select Register 83, offset: 0xA6

◆ SEL84

__IO uint16_t XBARA_Type::SEL84

Crossbar A Select Register 84, offset: 0xA8

◆ SEL85

__IO uint16_t XBARA_Type::SEL85

Crossbar A Select Register 85, offset: 0xAA

◆ SEL86

__IO uint16_t XBARA_Type::SEL86

Crossbar A Select Register 86, offset: 0xAC

◆ SEL87

__IO uint16_t XBARA_Type::SEL87

Crossbar A Select Register 87, offset: 0xAE

◆ SEL9

__IO uint16_t XBARA_Type::SEL9

Crossbar A Select Register 9, offset: 0x12

◆ SELECT_INPUT [1/2]

__IO uint32_t IOMUXC_Type::SELECT_INPUT

ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR_INOUT23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4

FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register, array offset: 0x498, array step: 0x4

◆ SELECT_INPUT [2/2]

__IO uint32_t IOMUXC_LPSR_Type::SELECT_INPUT

CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register, array offset: 0x80, array step: 0x4

◆ SEND_PACKET

__IO uint32_t DSI_HOST_APB_PKT_IF_Type::SEND_PACKET

SEND_PACKET, offset: 0x8

◆ SERQ

__O uint8_t DMA_Type::SERQ

Set Enable Request, offset: 0x1B

◆ SERV

__O uint8_t EWM_Type::SERV

Service Register, offset: 0x1

◆  [1/69]

__IO uint32_t { ... } ::SET

Fractional PLL Control Register, offset: 0x4

◆ SET [2/69]

__IO uint32_t AUDIO_PLL_Type::SET

Fractional PLL Control Register, offset: 0x4

Fractional PLL Spread Spectrum Control Register, offset: 0x14

Fractional PLL Numerator Control Register, offset: 0x24

Fractional PLL Denominator Control Register, offset: 0x34

◆  [3/69]

__IO uint32_t { ... } ::SET

Fractional PLL Spread Spectrum Control Register, offset: 0x14

◆  [4/69]

__IO uint32_t { ... } ::SET

Fractional PLL Numerator Control Register, offset: 0x24

◆  [5/69]

__IO uint32_t { ... } ::SET

Fractional PLL Denominator Control Register, offset: 0x34

◆ SET [6/69]

__IO uint32_t CCM_Type::SET

General Purpose Register, array offset: 0x4804, array step: 0x20

◆  [7/69]

__IO uint32_t { ... } ::SET

General Purpose Register, array offset: 0x4804, array step: 0x20

◆ SET [8/69]

__IO uint32_t ETHERNET_PLL_Type::SET

Fractional PLL Control Register, offset: 0x4

Fractional PLL Spread Spectrum Control Register, offset: 0x14

Fractional PLL Numerator Control Register, offset: 0x24

Fractional PLL Denominator Control Register, offset: 0x34

◆  [9/69]

__IO uint32_t { ... } ::SET

Fractional PLL Control Register, offset: 0x4

◆  [10/69]

__IO uint32_t { ... } ::SET

Fractional PLL Spread Spectrum Control Register, offset: 0x14

◆  [11/69]

__IO uint32_t { ... } ::SET

Fractional PLL Numerator Control Register, offset: 0x24

◆  [12/69]

__IO uint32_t { ... } ::SET

Fractional PLL Denominator Control Register, offset: 0x34

◆  [13/69]

__IO uint32_t { ... } ::SET

Control Register 0, offset: 0x4

◆ SET [14/69]

__IO uint32_t OSC_RC_400M_Type::SET

Control Register 0, offset: 0x4

Control Register 1, offset: 0x14

Control Register 2, offset: 0x24

Control Register 3, offset: 0x34

◆  [15/69]

__IO uint32_t { ... } ::SET

Control Register 1, offset: 0x14

◆  [16/69]

__IO uint32_t { ... } ::SET

Control Register 2, offset: 0x24

◆  [17/69]

__IO uint32_t { ... } ::SET

Control Register 3, offset: 0x34

◆  [18/69]

__I uint32_t { ... } ::SET

Status Register 0, offset: 0x54

◆ SET [19/69]

__I uint32_t OSC_RC_400M_Type::SET

Status Register 0, offset: 0x54

Status Register 1, offset: 0x64

Status Register 2, offset: 0x74

◆  [20/69]

__I uint32_t { ... } ::SET

Status Register 1, offset: 0x64

◆  [21/69]

__I uint32_t { ... } ::SET

Status Register 2, offset: 0x74

◆  [22/69]

__IO uint32_t { ... } ::SET

Analog Control Register CTRL0, offset: 0x4

◆ SET [23/69]

__IO uint32_t PHY_LDO_Type::SET

Analog Control Register CTRL0, offset: 0x4

◆  [24/69]

__I uint32_t { ... } ::SET

Analog Status Register STAT0, offset: 0x54

◆ SET [25/69]

__I uint32_t PHY_LDO_Type::SET

Analog Status Register STAT0, offset: 0x54

◆  [26/69]

__IO uint32_t { ... } ::SET

Video mux Control Register, offset: 0x4

◆ SET [27/69]

__IO uint32_t VIDEO_MUX_Type::SET

Video mux Control Register, offset: 0x4

Pixel Link Master(PLM) Control Register, offset: 0x24

YUV420 Control Register, offset: 0x34

Data Disable Register, offset: 0x54

MIPI DSI Control Register, offset: 0x74

◆  [28/69]

__IO uint32_t { ... } ::SET

Pixel Link Master(PLM) Control Register, offset: 0x24

◆  [29/69]

__IO uint32_t { ... } ::SET

YUV420 Control Register, offset: 0x34

◆  [30/69]

__IO uint32_t { ... } ::SET

Data Disable Register, offset: 0x54

◆  [31/69]

__IO uint32_t { ... } ::SET

MIPI DSI Control Register, offset: 0x74

◆ SET [32/69]

__IO uint32_t VIDEO_PLL_Type::SET

Fractional PLL Control Register, offset: 0x4

Fractional PLL Spread Spectrum Control Register, offset: 0x14

Fractional PLL Numerator Control Register, offset: 0x24

Fractional PLL Denominator Control Register, offset: 0x34

◆  [33/69]

__IO uint32_t { ... } ::SET

Fractional PLL Control Register, offset: 0x4

◆  [34/69]

__IO uint32_t { ... } ::SET

Fractional PLL Spread Spectrum Control Register, offset: 0x14

◆  [35/69]

__IO uint32_t { ... } ::SET

Fractional PLL Numerator Control Register, offset: 0x24

◆  [36/69]

__IO uint32_t { ... } ::SET

Fractional PLL Denominator Control Register, offset: 0x34

◆  [37/69]

__IO uint32_t { ... } ::SET

Analog Control Register CTRL0, offset: 0x4

◆ SET [38/69]

__IO uint32_t VMBANDGAP_Type::SET

Analog Control Register CTRL0, offset: 0x4

◆  [39/69]

__I uint32_t { ... } ::SET

Analog Status Register STAT0, offset: 0x54

◆ SET [40/69]

__I uint32_t VMBANDGAP_Type::SET

Analog Status Register STAT0, offset: 0x54

◆  [41/69]

__IO uint32_t { ... } ::SET

Fractional PLL Control Register, offset: 0x4

◆  [42/69]

__IO uint32_t { ... } ::SET

Fractional PLL Spread Spectrum Control Register, offset: 0x14

◆  [43/69]

__IO uint32_t { ... } ::SET

Fractional PLL Numerator Control Register, offset: 0x24

◆  [44/69]

__IO uint32_t { ... } ::SET

Fractional PLL Denominator Control Register, offset: 0x34

◆  [45/69]

__IO uint32_t { ... } ::SET

General Purpose Register, array offset: 0x4804, array step: 0x20

◆  [46/69]

__IO uint32_t { ... } ::SET

Fractional PLL Control Register, offset: 0x4

◆  [47/69]

__IO uint32_t { ... } ::SET

Fractional PLL Spread Spectrum Control Register, offset: 0x14

◆  [48/69]

__IO uint32_t { ... } ::SET

Fractional PLL Numerator Control Register, offset: 0x24

◆  [49/69]

__IO uint32_t { ... } ::SET

Fractional PLL Denominator Control Register, offset: 0x34

◆  [50/69]

__IO uint32_t { ... } ::SET

Control Register 0, offset: 0x4

◆  [51/69]

__IO uint32_t { ... } ::SET

Control Register 1, offset: 0x14

◆  [52/69]

__IO uint32_t { ... } ::SET

Control Register 2, offset: 0x24

◆  [53/69]

__IO uint32_t { ... } ::SET

Control Register 3, offset: 0x34

◆  [54/69]

__I uint32_t { ... } ::SET

Status Register 0, offset: 0x54

◆  [55/69]

__I uint32_t { ... } ::SET

Status Register 1, offset: 0x64

◆  [56/69]

__I uint32_t { ... } ::SET

Status Register 2, offset: 0x74

◆  [57/69]

__IO uint32_t { ... } ::SET

Analog Control Register CTRL0, offset: 0x4

◆  [58/69]

__I uint32_t { ... } ::SET

Analog Status Register STAT0, offset: 0x54

◆  [59/69]

__IO uint32_t { ... } ::SET

Video mux Control Register, offset: 0x4

◆  [60/69]

__IO uint32_t { ... } ::SET

Pixel Link Master(PLM) Control Register, offset: 0x24

◆  [61/69]

__IO uint32_t { ... } ::SET

YUV420 Control Register, offset: 0x34

◆  [62/69]

__IO uint32_t { ... } ::SET

Data Disable Register, offset: 0x54

◆  [63/69]

__IO uint32_t { ... } ::SET

MIPI DSI Control Register, offset: 0x74

◆  [64/69]

__IO uint32_t { ... } ::SET

Fractional PLL Control Register, offset: 0x4

◆  [65/69]

__IO uint32_t { ... } ::SET

Fractional PLL Spread Spectrum Control Register, offset: 0x14

◆  [66/69]

__IO uint32_t { ... } ::SET

Fractional PLL Numerator Control Register, offset: 0x24

◆  [67/69]

__IO uint32_t { ... } ::SET

Fractional PLL Denominator Control Register, offset: 0x34

◆  [68/69]

__IO uint32_t { ... } ::SET

Analog Control Register CTRL0, offset: 0x4

◆  [69/69]

__I uint32_t { ... } ::SET

Analog Status Register STAT0, offset: 0x54

◆ SETPOINT [1/9]

__IO uint32_t CCM_Type::SETPOINT

Setpoint setting, array offset: 0x40, array step: index*0x80, index2*0x4

Setpoint setting, array offset: 0x4040, array step: index*0x80, index2*0x4

Clock source Setpoint setting, array offset: 0x5008, array step: 0x20

LPCG Setpoint setting, array offset: 0x6008, array step: 0x20

◆  [2/9]

__IO uint32_t { ... } ::SETPOINT[16]

Setpoint setting, array offset: 0x40, array step: index*0x80, index2*0x4

◆  [3/9]

__IO uint32_t { ... } ::SETPOINT[16]

Setpoint setting, array offset: 0x4040, array step: index*0x80, index2*0x4

◆  [4/9]

__IO uint32_t { ... } ::SETPOINT

Clock source Setpoint setting, array offset: 0x5008, array step: 0x20

◆  [5/9]

__IO uint32_t { ... } ::SETPOINT

LPCG Setpoint setting, array offset: 0x6008, array step: 0x20

◆  [6/9]

__IO uint32_t { ... } ::SETPOINT[16]

Setpoint setting, array offset: 0x40, array step: index*0x80, index2*0x4

◆  [7/9]

__IO uint32_t { ... } ::SETPOINT[16]

Setpoint setting, array offset: 0x4040, array step: index*0x80, index2*0x4

◆  [8/9]

__IO uint32_t { ... } ::SETPOINT

Clock source Setpoint setting, array offset: 0x5008, array step: 0x20

◆  [9/9]

__IO uint32_t { ... } ::SETPOINT

LPCG Setpoint setting, array offset: 0x6008, array step: 0x20

◆ SETPOINT_DISPLAY

__IO uint32_t SRC_Type::SETPOINT_DISPLAY

Slice Setpoint Config Register, offset: 0x228

◆ SETPOINT_M4CORE

__IO uint32_t SRC_Type::SETPOINT_M4CORE

Slice Setpoint Config Register, offset: 0x288

◆ SETPOINT_M4DEBUG

__IO uint32_t SRC_Type::SETPOINT_M4DEBUG

Slice Setpoint Config Register, offset: 0x2C8

◆ SETPOINT_M7CORE

__IO uint32_t SRC_Type::SETPOINT_M7CORE

Slice Setpoint Config Register, offset: 0x2A8

◆ SETPOINT_M7DEBUG

__IO uint32_t SRC_Type::SETPOINT_M7DEBUG

Slice Setpoint Config Register, offset: 0x2E8

◆ SETPOINT_MEGA

__IO uint32_t SRC_Type::SETPOINT_MEGA

Slice Setpoint Config Register, offset: 0x208

◆ SETPOINT_USBPHY1

__IO uint32_t SRC_Type::SETPOINT_USBPHY1

Slice Setpoint Config Register, offset: 0x308

◆ SETPOINT_USBPHY2

__IO uint32_t SRC_Type::SETPOINT_USBPHY2

Slice Setpoint Config Register, offset: 0x328

◆ SETPOINT_WAKEUP

__IO uint32_t SRC_Type::SETPOINT_WAKEUP

Slice Setpoint Config Register, offset: 0x248

◆ SHIFTBUF

__IO uint32_t FLEXIO_Type::SHIFTBUF

Shifter Buffer N Register, array offset: 0x200, array step: 0x4

◆ SHIFTBUFBBS

__IO uint32_t FLEXIO_Type::SHIFTBUFBBS

Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4

◆ SHIFTBUFBIS

__IO uint32_t FLEXIO_Type::SHIFTBUFBIS

Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4

◆ SHIFTBUFBYS

__IO uint32_t FLEXIO_Type::SHIFTBUFBYS

Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4

◆ SHIFTBUFEOS

__IO uint32_t FLEXIO_Type::SHIFTBUFEOS

Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4

◆ SHIFTBUFHWS

__IO uint32_t FLEXIO_Type::SHIFTBUFHWS

Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4

◆ SHIFTBUFNBS

__IO uint32_t FLEXIO_Type::SHIFTBUFNBS

Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4

◆ SHIFTBUFNIS

__IO uint32_t FLEXIO_Type::SHIFTBUFNIS

Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4

◆ SHIFTBUFOES

__IO uint32_t FLEXIO_Type::SHIFTBUFOES

Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4

◆ SHIFTCFG

__IO uint32_t FLEXIO_Type::SHIFTCFG

Shifter Configuration N Register, array offset: 0x100, array step: 0x4

◆ SHIFTCTL

__IO uint32_t FLEXIO_Type::SHIFTCTL

Shifter Control N Register, array offset: 0x80, array step: 0x4

◆ SHIFTEIEN

__IO uint32_t FLEXIO_Type::SHIFTEIEN

Shifter Error Interrupt Enable, offset: 0x24

◆ SHIFTERR

__IO uint32_t FLEXIO_Type::SHIFTERR

Shifter Error Register, offset: 0x14

◆ SHIFTSDEN

__IO uint32_t FLEXIO_Type::SHIFTSDEN

Shifter Status DMA Enable, offset: 0x30

◆ SHIFTSIEN

__IO uint32_t FLEXIO_Type::SHIFTSIEN

Shifter Status Interrupt Enable, offset: 0x20

◆ SHIFTSTAT

__IO uint32_t FLEXIO_Type::SHIFTSTAT

Shifter Status Register, offset: 0x10

◆ SHIFTSTATE

__IO uint32_t FLEXIO_Type::SHIFTSTATE

Shifter State Register, offset: 0x40

◆ SIC [1/4]

__O uint32_t SPDIF_Type::SIC

InterruptClear Register, offset: 0x10

◆  [2/4]

__O uint32_t { ... } ::SIC

InterruptClear Register, offset: 0x10

◆  [3/4]

__O uint32_t { ... } ::SIC

InterruptClear Register, offset: 0x10

◆  [4/4]

__O uint32_t { ... } ::SIC

InterruptClear Register, offset: 0x10

◆ SIE

__IO uint32_t SPDIF_Type::SIE

InterruptEn Register, offset: 0xC

◆ SIER

__IO uint32_t LPI2C_Type::SIER

Slave Interrupt Enable Register, offset: 0x118

Slave Interrupt Enable, offset: 0x118

◆ SIGNAL_OVERRIDE

__IO uint32_t USBHSDCD_Type::SIGNAL_OVERRIDE

Signal Override Register, offset: 0xC

◆ SIL [1/3]

__IO uint32_t CAAM_Type::SIL

Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C

◆  [2/3]

__IO uint32_t { ... } ::SIL

Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::SIL

Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C

◆ SINGLE_ERR_ADDR

__I uint32_t XECC_Type::SINGLE_ERR_ADDR

Single Error Address, offset: 0x18

◆ SINGLE_ERR_ADDR_ECC0

__I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC0

Single Error Address And ECC code On OCRAM Bank0, offset: 0x3C

◆ SINGLE_ERR_ADDR_ECC1

__I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC1

Single Error Address And ECC code On OCRAM Bank1, offset: 0x50

◆ SINGLE_ERR_ADDR_ECC2

__I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC2

Single Error Address And ECC code On OCRAM Bank2, offset: 0x64

◆ SINGLE_ERR_ADDR_ECC3

__I uint32_t MECC_Type::SINGLE_ERR_ADDR_ECC3

Single Error Address And ECC code On OCRAM Bank3, offset: 0x78

◆ SINGLE_ERR_BIT_FIELD

__I uint32_t XECC_Type::SINGLE_ERR_BIT_FIELD

Single Error Bit Field, offset: 0x28

◆ SINGLE_ERR_DATA

__I uint32_t XECC_Type::SINGLE_ERR_DATA

Single Error Read Data, offset: 0x1C

◆ SINGLE_ERR_DATA_HIGH0

__I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH0

HIGH 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x44

◆ SINGLE_ERR_DATA_HIGH1

__I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH1

HIGH 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x58

◆ SINGLE_ERR_DATA_HIGH2

__I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH2

HIGH 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x6C

◆ SINGLE_ERR_DATA_HIGH3

__I uint32_t MECC_Type::SINGLE_ERR_DATA_HIGH3

HIGH 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x80

◆ SINGLE_ERR_DATA_LOW0

__I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW0

LOW 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x40

◆ SINGLE_ERR_DATA_LOW1

__I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW1

LOW 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x54

◆ SINGLE_ERR_DATA_LOW2

__I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW2

LOW 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x68

◆ SINGLE_ERR_DATA_LOW3

__I uint32_t MECC_Type::SINGLE_ERR_DATA_LOW3

LOW 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x7C

◆ SINGLE_ERR_ECC

__I uint32_t XECC_Type::SINGLE_ERR_ECC

Single Error ECC Code, offset: 0x20

◆ SINGLE_ERR_POS

__I uint32_t XECC_Type::SINGLE_ERR_POS

Single Error Bit Position, offset: 0x24

◆ SINGLE_ERR_POS_HIGH0

__I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH0

HIGH Single Error Bit Position On OCRAM Bank0, offset: 0x4C

◆ SINGLE_ERR_POS_HIGH1

__I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH1

HIGH Single Error Bit Position On OCRAM Bank1, offset: 0x60

◆ SINGLE_ERR_POS_HIGH2

__I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH2

HIGH Single Error Bit Position On OCRAM Bank2, offset: 0x74

◆ SINGLE_ERR_POS_HIGH3

__I uint32_t MECC_Type::SINGLE_ERR_POS_HIGH3

HIGH Single Error Bit Position On OCRAM Bank3, offset: 0x88

◆ SINGLE_ERR_POS_LOW0

__I uint32_t MECC_Type::SINGLE_ERR_POS_LOW0

LOW Single Error Bit Position On OCRAM Bank0, offset: 0x48

◆ SINGLE_ERR_POS_LOW1

__I uint32_t MECC_Type::SINGLE_ERR_POS_LOW1

LOW Single Error Bit Position On OCRAM Bank1, offset: 0x5C

◆ SINGLE_ERR_POS_LOW2

__I uint32_t MECC_Type::SINGLE_ERR_POS_LOW2

LOW Single Error Bit Position On OCRAM Bank2, offset: 0x70

◆ SINGLE_ERR_POS_LOW3

__I uint32_t MECC_Type::SINGLE_ERR_POS_LOW3

LOW Single Error Bit Position On OCRAM Bank3, offset: 0x84

◆  [1/4]

__I uint32_t { ... } ::SIS

InterruptStat Register, offset: 0x10

◆ SIS [2/4]

__I uint32_t SPDIF_Type::SIS

InterruptStat Register, offset: 0x10

◆  [3/4]

__I uint32_t { ... } ::SIS

InterruptStat Register, offset: 0x10

◆  [4/4]

__I uint32_t { ... } ::SIS

InterruptStat Register, offset: 0x10

◆ SJC_RESP0

__IO uint32_t OCOTP_Type::SJC_RESP0

Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600

◆ SJC_RESP1

__IO uint32_t OCOTP_Type::SJC_RESP1

Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610

◆ SKNR

__IO uint64_t CAAM_Type::SKNR

Secure Key Nonce Register, offset: 0x4E0

◆ SLAST [1/4]

__IO int32_t DMA_Type::SLAST

TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20

◆  [2/4]

__IO int32_t { ... } ::SLAST

TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20

◆  [3/4]

__IO int32_t { ... } ::SLAST

TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20

◆  [4/4]

__IO int32_t { ... } ::SLAST

TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20

◆ SLOT0_CTRL

__IO uint32_t KEY_MANAGER_Type::SLOT0_CTRL

Slot 0 Control, offset: 0x400

◆ SLOT1_CTRL

__IO uint32_t KEY_MANAGER_Type::SLOT1_CTRL

Slot1 Control, offset: 0x404

◆ SLOT2_CTRL

__IO uint32_t KEY_MANAGER_Type::SLOT2_CTRL

Slot2 Control, offset: 0x408

◆ SLOT3_CTRL

__IO uint32_t KEY_MANAGER_Type::SLOT3_CTRL

Slot3 Control, offset: 0x40C

◆ SLOT4_CTRL

__IO uint32_t KEY_MANAGER_Type::SLOT4_CTRL

Slot 4 Control, offset: 0x410

◆  [1/3]

__IO uint32_t { ... } ::SLOT_CTRL

Slot Control Register, array offset: 0x0, array step: 0x10

◆ SLOT_CTRL [2/3]

__IO uint32_t IPS_DOMAIN_Type::SLOT_CTRL

Slot Control Register, array offset: 0x0, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::SLOT_CTRL

Slot Control Register, array offset: 0x0, array step: 0x10

◆  [1/3]

__O uint32_t { ... } ::SMCR_JR

Secure Memory Command Register, array offset: 0x10BE4, array step: 0x10000

◆ SMCR_JR [2/3]

__O uint32_t CAAM_Type::SMCR_JR

Secure Memory Command Register, array offset: 0x10BE4, array step: 0x10000

◆  [3/3]

__O uint32_t { ... } ::SMCR_JR

Secure Memory Command Register, array offset: 0x10BE4, array step: 0x10000

◆ SMCR_PG0

__O uint32_t CAAM_Type::SMCR_PG0

Secure Memory Command Register, offset: 0xBE4

◆  [1/3]

__I uint32_t { ... } ::SMCSR_JR

Secure Memory Command Status Register, array offset: 0x10BEC, array step: 0x10000

◆ SMCSR_JR [2/3]

__I uint32_t CAAM_Type::SMCSR_JR

Secure Memory Command Status Register, array offset: 0x10BEC, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::SMCSR_JR

Secure Memory Command Status Register, array offset: 0x10BEC, array step: 0x10000

◆ SMCSR_PG0

__I uint32_t CAAM_Type::SMCSR_PG0

Secure Memory Command Status Register, offset: 0xBEC

◆ SMPO

__I uint32_t CAAM_Type::SMPO

Secure Memory Partition Owners Register, offset: 0xFBC

◆  [1/3]

__I uint32_t { ... } ::SMPO_JR

Secure Memory Partition Owners Register, array offset: 0x10FBC, array step: 0x10000

◆ SMPO_JR [2/3]

__I uint32_t CAAM_Type::SMPO_JR

Secure Memory Partition Owners Register, array offset: 0x10FBC, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::SMPO_JR

Secure Memory Partition Owners Register, array offset: 0x10FBC, array step: 0x10000

◆ SMSTA

__I uint32_t CAAM_Type::SMSTA

Secure Memory Status Register, offset: 0xFB4

◆ SMSTA_DC01

__I uint32_t CAAM_Type::SMSTA_DC01

Secure Memory Status Register, offset: 0x80FB4

◆ SMSTA_JR [1/3]

__I uint32_t CAAM_Type::SMSTA_JR

Secure Memory Status Register, array offset: 0x10FB4, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::SMSTA_JR

Secure Memory Status Register, array offset: 0x10FB4, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::SMSTA_JR

Secure Memory Status Register, array offset: 0x10FB4, array step: 0x10000

◆ SMSTA_RTIC

__I uint32_t CAAM_Type::SMSTA_RTIC

Secure Memory Status Register, offset: 0x60FB4

◆ SMVID_LS

__I uint32_t CAAM_Type::SMVID_LS

Secure Memory Version ID Register, least-significant half, offset: 0xFDC

◆ SMVID_LS_DC01

__I uint32_t CAAM_Type::SMVID_LS_DC01

Secure Memory Version ID Register, least-significant half, offset: 0x80FDC

◆ SMVID_LS_JR [1/3]

__I uint32_t CAAM_Type::SMVID_LS_JR

Secure Memory Version ID Register, least-significant half, array offset: 0x10FDC, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::SMVID_LS_JR

Secure Memory Version ID Register, least-significant half, array offset: 0x10FDC, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::SMVID_LS_JR

Secure Memory Version ID Register, least-significant half, array offset: 0x10FDC, array step: 0x10000

◆ SMVID_LS_RTIC

__I uint32_t CAAM_Type::SMVID_LS_RTIC

Secure Memory Version ID Register, least-significant half, offset: 0x60FDC

◆ SMVID_MS

__I uint32_t CAAM_Type::SMVID_MS

Secure Memory Version ID Register, most-significant half, offset: 0xFD8

◆ SMVID_MS_DC01

__I uint32_t CAAM_Type::SMVID_MS_DC01

Secure Memory Version ID Register, most-significant half, offset: 0x80FD8

◆ SMVID_MS_JR [1/3]

__I uint32_t CAAM_Type::SMVID_MS_JR

Secure Memory Version ID Register, most-significant half, array offset: 0x10FD8, array step: 0x10000

◆  [2/3]

__I uint32_t { ... } ::SMVID_MS_JR

Secure Memory Version ID Register, most-significant half, array offset: 0x10FD8, array step: 0x10000

◆  [3/3]

__I uint32_t { ... } ::SMVID_MS_JR

Secure Memory Version ID Register, most-significant half, array offset: 0x10FD8, array step: 0x10000

◆ SMVID_MS_RTIC

__I uint32_t CAAM_Type::SMVID_MS_RTIC

Secure Memory Version ID Register, most-significant half, offset: 0x60FD8

◆ SMWPJRR

__IO uint32_t CAAM_Type::SMWPJRR

Secure Memory Write Protect Job Ring Register, array offset: 0xBD0, array step: 0x4

◆  [1/4]

__IO uint16_t { ... } ::SOFF

TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20

◆ SOFF [2/4]

__IO uint16_t DMA_Type::SOFF

TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20

◆  [3/4]

__IO uint16_t { ... } ::SOFF

TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20

◆  [4/4]

__IO uint16_t { ... } ::SOFF

TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20

◆  [1/3]

__IO uint32_t { ... } ::SOL

Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C

◆ SOL [2/3]

__IO uint32_t CAAM_Type::SOL

Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::SOL

Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C

◆ SP_AUTHEN_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_AUTHEN_CTRL

SP Authentication Control, offset: 0x4

◆ SP_BG_PLDO_OFF_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BG_PLDO_OFF_CTRL

SP bandgap and PLL_LDO off control, offset: 0x190

◆ SP_BG_PLDO_ON_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BG_PLDO_ON_CTRL

SP bandgap and PLL_LDO on control, offset: 0x220

◆ SP_BIAS_OFF_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BIAS_OFF_CTRL

SP bias off control, offset: 0x180

◆ SP_BIAS_ON_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_BIAS_ON_CTRL

SP bias on control, offset: 0x230

◆ SP_CPU_REQ

__I uint32_t GPC_SET_POINT_CTRL_Type::SP_CPU_REQ

CPU SP Request, offset: 0x10

◆ SP_DCDC_DOWN_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_DCDC_DOWN_CTRL

SP DCDC down control, offset: 0x1B0

◆ SP_DCDC_UP_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_DCDC_UP_CTRL

SP DCDC up control, offset: 0x200

◆ SP_GROUP_DOWN_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_GROUP_DOWN_CTRL

SP group down control, offset: 0x120

◆ SP_GROUP_UP_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_GROUP_UP_CTRL

SP group up control, offset: 0x290

◆ SP_INT_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_INT_CTRL

SP Interrupt Control, offset: 0x8

◆ SP_ISO_OFF_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ISO_OFF_CTRL

SP ISO off control, offset: 0x260

◆ SP_ISO_ON_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ISO_ON_CTRL

SP ISO on control, offset: 0x150

◆ SP_LDO_POST_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LDO_POST_CTRL

SP LDO post control, offset: 0x210

◆ SP_LDO_PRE_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LDO_PRE_CTRL

SP LDO pre control, offset: 0x1A0

◆ SP_LPCG_OFF_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LPCG_OFF_CTRL

SP LPCG off control, offset: 0x110

◆ SP_LPCG_ON_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_LPCG_ON_CTRL

SP LPCG on control, offset: 0x2A0

◆ SP_PLL_OFF_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PLL_OFF_CTRL

SP PLL off control, offset: 0x140

◆ SP_PLL_ON_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PLL_ON_CTRL

SP PLL on control, offset: 0x270

◆ SP_POWER_OFF_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_POWER_OFF_CTRL

SP power off control, offset: 0x170

◆ SP_POWER_ON_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_POWER_ON_CTRL

SP power on control, offset: 0x240

◆ SP_PRIORITY_0_7

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PRIORITY_0_7

SP0~7 Priority, offset: 0x40

◆ SP_PRIORITY_8_15

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_PRIORITY_8_15

SP8~15 Priority, offset: 0x44

◆ SP_RESET_EARLY_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_RESET_EARLY_CTRL

SP reset early control, offset: 0x160

◆ SP_RESET_LATE_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_RESET_LATE_CTRL

SP reset late control, offset: 0x250

◆ SP_ROOT_DOWN_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ROOT_DOWN_CTRL

SP root down control, offset: 0x130

◆ SP_ROOT_UP_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ROOT_UP_CTRL

SP root up control, offset: 0x280

◆ SP_ROSC_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_ROSC_CTRL

SP ROSC Control, offset: 0x1C

◆ SP_SSAR_RESTORE_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_SSAR_RESTORE_CTRL

SP SSAR restore control, offset: 0x2B0

◆ SP_SSAR_SAVE_CTRL

__IO uint32_t GPC_SET_POINT_CTRL_Type::SP_SSAR_SAVE_CTRL

SP SSAR save control, offset: 0x100

◆ SP_SYS_STAT

__I uint32_t GPC_SET_POINT_CTRL_Type::SP_SYS_STAT

SP System Status, offset: 0x14

◆ SR [1/6]

__IO uint32_t CSI_Type::SR

CSI Status Register, offset: 0x18

◆ SR [2/6]

__IO uint32_t GPT_Type::SR

GPT Status Register, offset: 0x8

◆ SR [3/6]

__IO uint32_t LPSPI_Type::SR

Status Register, offset: 0x14

Status, offset: 0x14

◆ SR [4/6]

__IO uint32_t MU_Type::SR

Processor B Status Register, offset: 0x20

Processor A Status Register, offset: 0x20

◆ SR [5/6]

__IO uint32_t OTFAD_Type::SR

Status Register, offset: 0xC04

◆ SR [6/6]

__I uint32_t XRDC2_Type::SR

Status Register, offset: 0x4

◆  [1/3]

__IO uint32_t { ... } ::SRAM0

Description Address Register, array offset: 0x0, array step: 0x10

◆ SRAM0 [2/3]

__IO uint32_t SSARC_HP_Type::SRAM0

Description Address Register, array offset: 0x0, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::SRAM0

Description Address Register, array offset: 0x0, array step: 0x10

◆  [1/3]

__IO uint32_t { ... } ::SRAM1

Description Data Register, array offset: 0x4, array step: 0x10

◆ SRAM1 [2/3]

__IO uint32_t SSARC_HP_Type::SRAM1

Description Data Register, array offset: 0x4, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::SRAM1

Description Data Register, array offset: 0x4, array step: 0x10

◆  [1/3]

__IO uint32_t { ... } ::SRAM2

Description Control Register, array offset: 0x8, array step: 0x10

◆ SRAM2 [2/3]

__IO uint32_t SSARC_HP_Type::SRAM2

Description Control Register, array offset: 0x8, array step: 0x10

◆  [3/3]

__IO uint32_t { ... } ::SRAM2

Description Control Register, array offset: 0x8, array step: 0x10

◆ SRAMCR0

__IO uint32_t SEMC_Type::SRAMCR0

SRAM control register 0, offset: 0x70

SRAM Control Register 0, offset: 0x70

◆ SRAMCR1

__IO uint32_t SEMC_Type::SRAMCR1

SRAM control register 1, offset: 0x74

SRAM Control Register 1, offset: 0x74

◆ SRAMCR2

__IO uint32_t SEMC_Type::SRAMCR2

SRAM control register 2, offset: 0x78

SRAM Control Register 2, offset: 0x78

◆ SRAMCR3

uint32_t SEMC_Type::SRAMCR3

SRAM control register 3, offset: 0x7C

SRAM Control Register 3, offset: 0x7C

◆ SRAMCR4

__IO uint32_t SEMC_Type::SRAMCR4

SRAM Control Register 4, offset: 0x120

◆ SRAMCR5

__IO uint32_t SEMC_Type::SRAMCR5

SRAM Control Register 5, offset: 0x124

◆ SRAMCR6

__IO uint32_t SEMC_Type::SRAMCR6

SRAM Control Register 6, offset: 0x128

◆ SRCD

__IO uint32_t SPDIF_Type::SRCD

CDText Control Register, offset: 0x4

◆ SRCSH

__I uint32_t SPDIF_Type::SRCSH

SPDIFRxCChannel_h Register, offset: 0x1C

◆ SRCSL

__I uint32_t SPDIF_Type::SRCSL

SPDIFRxCChannel_l Register, offset: 0x20

◆ SRDR

__I uint32_t LPI2C_Type::SRDR

Slave Receive Data Register, offset: 0x170

Slave Receive Data, offset: 0x170

◆ SRFM

__I uint32_t SPDIF_Type::SRFM

FreqMeas Register, offset: 0x44

◆ SRK0

__IO uint32_t OCOTP_Type::SRK0

Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580

◆ SRK1

__IO uint32_t OCOTP_Type::SRK1

Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590

◆ SRK2

__IO uint32_t OCOTP_Type::SRK2

Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0

◆ SRK3

__IO uint32_t OCOTP_Type::SRK3

Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0

◆ SRK4

__IO uint32_t OCOTP_Type::SRK4

Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0

◆ SRK5

__IO uint32_t OCOTP_Type::SRK5

Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0

◆ SRK6

__IO uint32_t OCOTP_Type::SRK6

Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0

◆ SRK7

__IO uint32_t OCOTP_Type::SRK7

Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0

◆ SRK_REVOKE

__IO uint32_t OCOTP_Type::SRK_REVOKE

Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0

◆ SRL

__I uint32_t SPDIF_Type::SRL

SPDIFRxLeft Register, offset: 0x14

◆ SRMR

__IO uint32_t SRC_Type::SRMR

SRC Reset Mode Register, offset: 0x4

◆ SRPC

__IO uint32_t SPDIF_Type::SRPC

PhaseConfig Register, offset: 0x8

◆ SRQ

__I uint32_t SPDIF_Type::SRQ

QchannelRx Register, offset: 0x28

◆ SRR

__I uint32_t SPDIF_Type::SRR

SPDIFRxRight Register, offset: 0x18

◆ SRSR

__IO uint32_t SRC_Type::SRSR

SRC Reset Status Register, offset: 0x8

SRC Reset Status Register, offset: 0x10

◆ SRU

__I uint32_t SPDIF_Type::SRU

UchannelRx Register, offset: 0x24

◆ SSR

__IO uint32_t LPI2C_Type::SSR

Slave Status Register, offset: 0x114

Slave Status, offset: 0x114

◆ SSRT

__O uint8_t DMA_Type::SSRT

Set START Bit, offset: 0x1D

◆ STA

__I uint32_t IEE_Type::STA

IEE Status, offset: 0x4

◆ STAR

__IO uint32_t LPI2C_Type::STAR

Slave Transmit ACK Register, offset: 0x154

Slave Transmit ACK, offset: 0x154

◆ START

__O uint32_t CDOG_Type::START

START Command, offset: 0x20

◆ STAT [1/8]

__IO uint32_t DCP_Type::STAT

DCP status register, offset: 0x10

◆ STAT [2/8]

__I uint32_t LCDIF_Type::STAT

LCD Interface Status Register, offset: 0x1B0

◆ STAT [3/8]

__IO uint32_t LPUART_Type::STAT

LPUART Status Register, offset: 0x14

◆ STAT [4/8]

__IO uint32_t PXP_Type::STAT

Status Register, offset: 0x10

◆ STAT [5/8]

__IO uint32_t ADC_Type::STAT

LPADC Status Register, offset: 0x14

◆ STAT [6/8]

__IO uint32_t PDM_Type::STAT

PDM Status register, offset: 0x8

◆ STAT [7/8]

__I uint32_t PUF_Type::STAT

PUF Status Register, offset: 0x20

◆ STAT [8/8]

__IO uint32_t RDC_Type::STAT

Status, offset: 0x24

◆ STAT_CLR [1/2]

__IO uint32_t DCP_Type::STAT_CLR

DCP status register, offset: 0x18

◆ STAT_CLR [2/2]

__IO uint32_t PXP_Type::STAT_CLR

Status Register, offset: 0x18

◆ STAT_DISPLAY

__IO uint32_t SRC_Type::STAT_DISPLAY

Slice Status Register, offset: 0x230

◆ STAT_M4CORE

__IO uint32_t SRC_Type::STAT_M4CORE

Slice Status Register, offset: 0x290

◆ STAT_M4DEBUG

__IO uint32_t SRC_Type::STAT_M4DEBUG

Slice Status Register, offset: 0x2D0

◆ STAT_M7CORE

__IO uint32_t SRC_Type::STAT_M7CORE

Slice Status Register, offset: 0x2B0

◆ STAT_M7DEBUG

__IO uint32_t SRC_Type::STAT_M7DEBUG

Slice Status Register, offset: 0x2F0

◆ STAT_MEGA

__IO uint32_t SRC_Type::STAT_MEGA

Slice Status Register, offset: 0x210

◆ STAT_SET [1/2]

__IO uint32_t DCP_Type::STAT_SET

DCP status register, offset: 0x14

◆ STAT_SET [2/2]

__IO uint32_t PXP_Type::STAT_SET

Status Register, offset: 0x14

◆ STAT_TOG [1/2]

__IO uint32_t DCP_Type::STAT_TOG

DCP status register, offset: 0x1C

◆ STAT_TOG [2/2]

__IO uint32_t PXP_Type::STAT_TOG

Status Register, offset: 0x1C

◆ STAT_USBPHY1

__IO uint32_t SRC_Type::STAT_USBPHY1

Slice Status Register, offset: 0x310

◆ STAT_USBPHY2

__IO uint32_t SRC_Type::STAT_USBPHY2

Slice Status Register, offset: 0x330

◆ STAT_WAKEUP

__IO uint32_t SRC_Type::STAT_WAKEUP

Slice Status Register, offset: 0x250

◆ STATFIFO

__I uint32_t CSI_Type::STATFIFO

CSI Statistic FIFO Register, offset: 0xC

◆ STATUS [1/5]

__IO uint32_t BEE_Type::STATUS

Status Register, offset: 0x1C

◆ STATUS [2/5]

__I uint32_t TRNG_Type::STATUS

Status Register, offset: 0x3C

◆ STATUS [3/5]

__IO uint32_t USBPHY_Type::STATUS

USB PHY Status Register, offset: 0x40

◆ STATUS [4/5]

__I uint32_t CDOG_Type::STATUS

Status 1, offset: 0x10

◆ STATUS [5/5]

__I uint32_t USBHSDCD_Type::STATUS

Status register, offset: 0x8

◆ STATUS0 [1/14]

__I uint32_t CCM_Type::STATUS0

Clock root working status, array offset: 0x20, array step: 0x80

Clock source working status, array offset: 0x5010, array step: 0x20

LPCG working status, array offset: 0x6010, array step: 0x20

◆  [2/14]

__I uint32_t { ... } ::STATUS0

Clock root working status, array offset: 0x20, array step: 0x80

◆  [3/14]

__IO uint32_t { ... } ::STATUS0

Clock group working status, array offset: 0x4020, array step: 0x80

◆ STATUS0 [4/14]

__IO uint32_t CCM_Type::STATUS0

Clock group working status, array offset: 0x4020, array step: 0x80

◆  [5/14]

__I uint32_t { ... } ::STATUS0

Clock source working status, array offset: 0x5010, array step: 0x20

◆  [6/14]

__I uint32_t { ... } ::STATUS0

LPCG working status, array offset: 0x6010, array step: 0x20

◆  [7/14]

__I uint32_t { ... } ::STATUS0

Observe status, array offset: 0x20, array step: 0x80

◆ STATUS0 [8/14]

__I uint32_t CCM_OBS_Type::STATUS0

Observe status, array offset: 0x20, array step: 0x80

◆ STATUS0 [9/14]

__IO uint32_t TMPSNS_Type::STATUS0

Temperature Sensor Status Register 0, offset: 0x50

◆  [10/14]

__I uint32_t { ... } ::STATUS0

Clock root working status, array offset: 0x20, array step: 0x80

◆  [11/14]

__IO uint32_t { ... } ::STATUS0

Clock group working status, array offset: 0x4020, array step: 0x80

◆  [12/14]

__I uint32_t { ... } ::STATUS0

Clock source working status, array offset: 0x5010, array step: 0x20

◆  [13/14]

__I uint32_t { ... } ::STATUS0

LPCG working status, array offset: 0x6010, array step: 0x20

◆  [14/14]

__I uint32_t { ... } ::STATUS0

Observe status, array offset: 0x20, array step: 0x80

◆  [1/9]

__I uint32_t { ... } ::STATUS1

Clock root low power status, array offset: 0x24, array step: 0x80

◆ STATUS1 [2/9]

__I uint32_t CCM_Type::STATUS1

Clock root low power status, array offset: 0x24, array step: 0x80

Clock group low power/extend status, array offset: 0x4024, array step: 0x80

Clock source low power status, array offset: 0x5014, array step: 0x20

LPCG low power status, array offset: 0x6014, array step: 0x20

◆  [3/9]

__I uint32_t { ... } ::STATUS1

Clock group low power/extend status, array offset: 0x4024, array step: 0x80

◆  [4/9]

__I uint32_t { ... } ::STATUS1

Clock source low power status, array offset: 0x5014, array step: 0x20

◆  [5/9]

__I uint32_t { ... } ::STATUS1

LPCG low power status, array offset: 0x6014, array step: 0x20

◆  [6/9]

__I uint32_t { ... } ::STATUS1

Clock root low power status, array offset: 0x24, array step: 0x80

◆  [7/9]

__I uint32_t { ... } ::STATUS1

Clock group low power/extend status, array offset: 0x4024, array step: 0x80

◆  [8/9]

__I uint32_t { ... } ::STATUS1

Clock source low power status, array offset: 0x5014, array step: 0x20

◆  [9/9]

__I uint32_t { ... } ::STATUS1

LPCG low power status, array offset: 0x6014, array step: 0x20

◆ STATUS2

__I uint32_t CDOG_Type::STATUS2

Status 2, offset: 0x14

◆ STBY_AUTHEN_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_AUTHEN_CTRL

Standby Authentication Control, offset: 0x4

◆ STBY_BANDGAP_IN_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_BANDGAP_IN_CTRL

STBY bandgap_in control, offset: 0x128

◆ STBY_BANDGAP_OUT_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_BANDGAP_OUT_CTRL

STBY bandgap out control, offset: 0x230

◆ STBY_BIAS_IN_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_BIAS_IN_CTRL

STBY bias_in control, offset: 0x110

◆ STBY_BIAS_OUT_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_BIAS_OUT_CTRL

STBY bias out control, offset: 0x240

◆ STBY_DCDC_IN_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_DCDC_IN_CTRL

STBY dcdc_in control, offset: 0x140

◆ STBY_DCDC_OUT_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_DCDC_OUT_CTRL

STBY DCDC out control, offset: 0x210

◆ STBY_LDO_IN_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_LDO_IN_CTRL

STBY ldo_in control, offset: 0x130

◆ STBY_LDO_OUT_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_LDO_OUT_CTRL

STBY LDO out control, offset: 0x220

◆ STBY_LPCG_IN_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_LPCG_IN_CTRL

STBY lpcg_in control, offset: 0xF0

◆ STBY_LPCG_OUT_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_LPCG_OUT_CTRL

STBY LPCG out control, offset: 0x260

◆ STBY_MISC

__IO uint32_t GPC_STBY_CTRL_Type::STBY_MISC

STBY Misc, offset: 0xC

◆ STBY_PLDO_IN_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_PLDO_IN_CTRL

STBY pldo_in control, offset: 0x120

◆ STBY_PLDO_OUT_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_PLDO_OUT_CTRL

STBY pldo out control, offset: 0x238

◆ STBY_PLL_IN_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_PLL_IN_CTRL

STBY pll_in control, offset: 0x100

◆ STBY_PLL_OUT_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_PLL_OUT_CTRL

STBY PLL out control, offset: 0x250

◆ STBY_PMIC_IN_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_PMIC_IN_CTRL

STBY PMIC in control, offset: 0x150

◆ STBY_PMIC_OUT_CTRL

__IO uint32_t GPC_STBY_CTRL_Type::STBY_PMIC_OUT_CTRL

STBY PMIC out control, offset: 0x200

◆ STC

__IO uint32_t SPDIF_Type::STC

SPDIFTxClk Register, offset: 0x50

◆ STCSCH

__IO uint32_t SPDIF_Type::STCSCH

SPDIFTxCChannelCons_h Register, offset: 0x34

◆ STCSCL

__IO uint32_t SPDIF_Type::STCSCL

SPDIFTxCChannelCons_l Register, offset: 0x38

◆ STDR

__O uint32_t LPI2C_Type::STDR

Slave Transmit Data Register, offset: 0x160

Slave Transmit Data, offset: 0x160

◆ STL

__O uint32_t SPDIF_Type::STL

SPDIFTxLeft Register, offset: 0x2C

◆ STOP

__O uint32_t CDOG_Type::STOP

STOP Command, offset: 0x24

◆ STR

__O uint32_t SPDIF_Type::STR

SPDIFTxRight Register, offset: 0x30

◆ STROBE_DLL_CTRL

__IO uint32_t USDHC_Type::STROBE_DLL_CTRL

Strobe DLL control, offset: 0x70

◆ STROBE_DLL_STATUS

__I uint32_t USDHC_Type::STROBE_DLL_STATUS

Strobe DLL status, offset: 0x74

◆ STS [1/4]

__IO uint16_t PWM_Type::STS

Status Register, array offset: 0x24, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::STS

Status Register, array offset: 0x24, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::STS

Status Register, array offset: 0x24, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::STS

Status Register, array offset: 0x24, array step: 0x60

◆ STS0 [1/2]

__I uint32_t FLEXSPI_Type::STS0

Status Register 0, offset: 0xE0

◆ STS0 [2/2]

__I uint32_t SEMC_Type::STS0

Status register 0, offset: 0xC0

Status Register 0, offset: 0xC0

◆ STS1 [1/2]

__I uint32_t FLEXSPI_Type::STS1

Status Register 1, offset: 0xE4

◆ STS1 [2/2]

uint32_t SEMC_Type::STS1

Status register 1, offset: 0xC4

Status Register 1, offset: 0xC4

◆ STS10

uint32_t SEMC_Type::STS10

Status register 10, offset: 0xE8

Status Register 10, offset: 0xE8

◆ STS11

uint32_t SEMC_Type::STS11

Status register 11, offset: 0xEC

Status Register 11, offset: 0xEC

◆ STS12

__I uint32_t SEMC_Type::STS12

Status register 12, offset: 0xF0

Status Register 12, offset: 0xF0

◆ STS13 [1/2]

__I uint32_t SEMC_Type::STS13

Status register 13, offset: 0xF4

Status Register 13, offset: 0xF4

◆ STS13 [2/2]

__I uint32_t SEMC_Type::STS13

Status Register 13, offset: 0xF4

◆ STS14

uint32_t SEMC_Type::STS14

Status register 14, offset: 0xF8

Status Register 14, offset: 0xF8

◆ STS15

uint32_t SEMC_Type::STS15

Status register 15, offset: 0xFC

Status Register 15, offset: 0xFC

◆ STS2 [1/2]

__I uint32_t FLEXSPI_Type::STS2

Status Register 2, offset: 0xE8

◆ STS2 [2/2]

__I uint32_t SEMC_Type::STS2

Status register 2, offset: 0xC8

Status Register 2, offset: 0xC8

◆ STS3

uint32_t SEMC_Type::STS3

Status register 3, offset: 0xCC

Status Register 3, offset: 0xCC

◆ STS4

uint32_t SEMC_Type::STS4

Status register 4, offset: 0xD0

Status Register 4, offset: 0xD0

◆ STS5

uint32_t SEMC_Type::STS5

Status register 5, offset: 0xD4

Status Register 5, offset: 0xD4

◆ STS6

uint32_t SEMC_Type::STS6

Status register 6, offset: 0xD8

Status Register 6, offset: 0xD8

◆ STS7

uint32_t SEMC_Type::STS7

Status register 7, offset: 0xDC

Status Register 7, offset: 0xDC

◆ STS8

uint32_t SEMC_Type::STS8

Status register 8, offset: 0xE0

Status Register 8, offset: 0xE0

◆ STS9

uint32_t SEMC_Type::STS9

Status register 9, offset: 0xE4

Status Register 9, offset: 0xE4

◆ SUB

__O uint32_t CDOG_Type::SUB

SUB Command, offset: 0x3C

◆ SUB1

__O uint32_t CDOG_Type::SUB1

SUB1 Command, offset: 0x40

◆ SUB16

__O uint32_t CDOG_Type::SUB16

SUB16 Command, offset: 0x44

◆ SUB256

__O uint32_t CDOG_Type::SUB256

SUB256 Command, offset: 0x48

◆ SW_GP1

__IO uint32_t OCOTP_Type::SW_GP1

Value of OTP Bank5 Word0 (SW GP1), offset: 0x680

◆ SW_GP20

__IO uint32_t OCOTP_Type::SW_GP20

Value of OTP Bank5 Word1 (SW GP2), offset: 0x690

◆ SW_GP21

__IO uint32_t OCOTP_Type::SW_GP21

Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0

◆ SW_GP22

__IO uint32_t OCOTP_Type::SW_GP22

Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0

◆ SW_GP23

__IO uint32_t OCOTP_Type::SW_GP23

Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0

◆ SW_GROUP_PENDING

__I uint32_t SSARC_LP_Type::SW_GROUP_PENDING

Software Request Pending Register, offset: 0x220

◆ SW_LOCK

__IO uint32_t OCOTP_Type::SW_LOCK

SW_LOCK Register, offset: 0x140

◆ SW_MUX_CTL_PAD [1/2]

__IO uint32_t IOMUXC_Type::SW_MUX_CTL_PAD

SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4

SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register, array offset: 0x10, array step: 0x4

◆ SW_MUX_CTL_PAD [2/2]

__IO uint32_t IOMUXC_LPSR_Type::SW_MUX_CTL_PAD

SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register, array offset: 0x0, array step: 0x4

◆ SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG

SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register, offset: 0xC

◆ SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG

SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register, offset: 0x10

◆ SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG

SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register, offset: 0x14

◆ SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG

SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register, offset: 0x18

◆ SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG

SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register, offset: 0x1C

◆ SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG

SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register, offset: 0x20

◆ SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG

SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register, offset: 0x24

◆ SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG

SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register, offset: 0x28

◆ SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG

SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register, offset: 0x2C

◆ SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG

SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register, offset: 0x30

◆ SW_MUX_CTL_PAD_PMIC_ON_REQ

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_ON_REQ

SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4

◆ SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG

SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register, offset: 0x4

◆ SW_MUX_CTL_PAD_PMIC_STBY_REQ

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_STBY_REQ

SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x8

◆ SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG

SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register, offset: 0x8

◆ SW_MUX_CTL_PAD_WAKEUP

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_WAKEUP

SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register, offset: 0x0

◆ SW_MUX_CTL_PAD_WAKEUP_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_MUX_CTL_PAD_WAKEUP_DIG

SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register, offset: 0x0

◆ SW_PAD_CTL_PAD [1/2]

__IO uint32_t IOMUXC_Type::SW_PAD_CTL_PAD

SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4

SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register, array offset: 0x254, array step: 0x4

◆ SW_PAD_CTL_PAD [2/2]

__IO uint32_t IOMUXC_LPSR_Type::SW_PAD_CTL_PAD

SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register, array offset: 0x40, array step: 0x4

◆ SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG

SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register, offset: 0x4C

◆ SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG

SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register, offset: 0x50

◆ SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG

SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register, offset: 0x54

◆ SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG

SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register, offset: 0x58

◆ SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG

SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register, offset: 0x5C

◆ SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG

SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register, offset: 0x60

◆ SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG

SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register, offset: 0x64

◆ SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG

SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register, offset: 0x68

◆ SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG

SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register, offset: 0x6C

◆ SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG

SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register, offset: 0x70

◆ SW_PAD_CTL_PAD_ONOFF

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_ONOFF

SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14

◆ SW_PAD_CTL_PAD_ONOFF_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_ONOFF_DIG

SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register, offset: 0x3C

◆ SW_PAD_CTL_PAD_PMIC_ON_REQ

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_ON_REQ

SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C

◆ SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG

SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register, offset: 0x44

◆ SW_PAD_CTL_PAD_PMIC_STBY_REQ

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_STBY_REQ

SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register, offset: 0x20

◆ SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG

SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register, offset: 0x48

◆ SW_PAD_CTL_PAD_POR_B

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_POR_B

SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10

◆ SW_PAD_CTL_PAD_POR_B_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_POR_B_DIG

SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register, offset: 0x38

◆ SW_PAD_CTL_PAD_TEST_MODE

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_TEST_MODE

SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC

◆ SW_PAD_CTL_PAD_TEST_MODE_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_TEST_MODE_DIG

SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register, offset: 0x34

◆ SW_PAD_CTL_PAD_WAKEUP

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_WAKEUP

SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register, offset: 0x18

◆ SW_PAD_CTL_PAD_WAKEUP_DIG

__IO uint32_t IOMUXC_SNVS_Type::SW_PAD_CTL_PAD_WAKEUP_DIG

SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register, offset: 0x40

◆ SW_STICKY

__IO uint32_t OCOTP_Type::SW_STICKY

Sticky bit Register, offset: 0x50

◆ SWCOUT

__IO uint16_t PWM_Type::SWCOUT

Software Controlled Output Register, offset: 0x184

◆ SWTRIG

__O uint32_t ADC_Type::SWTRIG

Software Trigger Register, offset: 0x34

◆ SYS_CTRL

__IO uint32_t USDHC_Type::SYS_CTRL

System Control, offset: 0x2C

◆ SYS_PLL1_CTRL

__IO uint32_t ANADIG_PLL_Type::SYS_PLL1_CTRL

SYS_PLL1_CTRL_REGISTER, offset: 0x2C0

◆ SYS_PLL1_DENOMINATOR

__IO uint32_t ANADIG_PLL_Type::SYS_PLL1_DENOMINATOR

SYS_PLL1_DENOMINATOR_REGISTER, offset: 0x2D0

◆ SYS_PLL1_DIV_SELECT

__IO uint32_t ANADIG_PLL_Type::SYS_PLL1_DIV_SELECT

SYS_PLL1_DIV_SELECT_REGISTER, offset: 0x2F0

◆ SYS_PLL1_NUMERATOR

__IO uint32_t ANADIG_PLL_Type::SYS_PLL1_NUMERATOR

SYS_PLL1_NUMERATOR_REGISTER, offset: 0x2E0

◆ SYS_PLL1_SS

__IO uint32_t ANADIG_PLL_Type::SYS_PLL1_SS

SYS_PLL1_SS_REGISTER, offset: 0x2B0

◆ SYS_PLL2_CTRL

__IO uint32_t ANADIG_PLL_Type::SYS_PLL2_CTRL

SYS_PLL2_CTRL_REGISTER, offset: 0x240

◆ SYS_PLL2_MFD

__IO uint32_t ANADIG_PLL_Type::SYS_PLL2_MFD

SYS_PLL2_MFD_REGISTER, offset: 0x2A0

◆ SYS_PLL2_PFD

__IO uint32_t ANADIG_PLL_Type::SYS_PLL2_PFD

SYS_PLL2_PFD_REGISTER, offset: 0x270

◆ SYS_PLL2_SS

__IO uint32_t ANADIG_PLL_Type::SYS_PLL2_SS

SYS_PLL2_SS_REGISTER, offset: 0x260

◆ SYS_PLL2_UPDATE

__IO uint32_t ANADIG_PLL_Type::SYS_PLL2_UPDATE

SYS_PLL2_UPDATE_REGISTER, offset: 0x250

◆ SYS_PLL3_CTRL

__IO uint32_t ANADIG_PLL_Type::SYS_PLL3_CTRL

SYS_PLL3_CTRL_REGISTER, offset: 0x210

◆ SYS_PLL3_PFD

__IO uint32_t ANADIG_PLL_Type::SYS_PLL3_PFD

SYS_PLL3_PFD_REGISTER, offset: 0x230

◆ SYS_PLL3_UPDATE

__IO uint32_t ANADIG_PLL_Type::SYS_PLL3_UPDATE

SYS_PLL3_UPDATE_REGISTER, offset: 0x220

◆ TACC

__IO uint32_t ENET_Type::TACC

Transmit Accelerator Function Configuration, offset: 0x1C0

◆ TAEM

__IO uint32_t ENET_Type::TAEM

Transmit FIFO Almost Empty Threshold, offset: 0x1A4

◆ TAFL

__IO uint32_t ENET_Type::TAFL

Transmit FIFO Almost Full Threshold, offset: 0x1A8

◆  [1/4]

__IO uint32_t { ... } ::TCCR

Timer Compare Capture Register, array offset: 0x60C, array step: 0x8

◆ TCCR [2/4]

__IO uint32_t ENET_Type::TCCR

Timer Compare Capture Register, array offset: 0x60C, array step: 0x8

◆  [3/4]

__IO uint32_t { ... } ::TCCR

Timer Compare Capture Register, array offset: 0x60C, array step: 0x8

◆  [4/4]

__IO uint32_t { ... } ::TCCR

Timer Compare Capture Register, array offset: 0x60C, array step: 0x8

◆ TCM_CTRL

__IO uint32_t FLEXRAM_Type::TCM_CTRL

TCM CRTL Register, offset: 0x0

◆ TCR [1/2]

__IO uint32_t ENET_Type::TCR

Transmit Control Register, offset: 0xC4

◆ TCR [2/2]

__IO uint32_t LPSPI_Type::TCR

Transmit Command Register, offset: 0x60

Transmit Command, offset: 0x60

◆ TCR1

__IO uint32_t I2S_Type::TCR1

SAI Transmit Configuration 1 Register, offset: 0xC

Transmit Configuration 1, offset: 0xC

◆ TCR2

__IO uint32_t I2S_Type::TCR2

SAI Transmit Configuration 2 Register, offset: 0x10

Transmit Configuration 2, offset: 0x10

◆ TCR3

__IO uint32_t I2S_Type::TCR3

SAI Transmit Configuration 3 Register, offset: 0x14

Transmit Configuration 3, offset: 0x14

◆ TCR4

__IO uint32_t I2S_Type::TCR4

SAI Transmit Configuration 4 Register, offset: 0x18

Transmit Configuration 4, offset: 0x18

◆ TCR5

__IO uint32_t I2S_Type::TCR5

SAI Transmit Configuration 5 Register, offset: 0x1C

Transmit Configuration 5, offset: 0x1C

◆ TCSR [1/5]

__IO uint32_t ENET_Type::TCSR

Timer Control Status Register, array offset: 0x608, array step: 0x8

◆  [2/5]

__IO uint32_t { ... } ::TCSR

Timer Control Status Register, array offset: 0x608, array step: 0x8

◆ TCSR [3/5]

__IO uint32_t I2S_Type::TCSR

SAI Transmit Control Register, offset: 0x8

Transmit Control, offset: 0x8

◆  [4/5]

__IO uint32_t { ... } ::TCSR

Timer Control Status Register, array offset: 0x608, array step: 0x8

◆  [5/5]

__IO uint32_t { ... } ::TCSR

Timer Control Status Register, array offset: 0x608, array step: 0x8

◆  [1/9]

__IO uint32_t { ... } ::TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10

◆ TCTRL [2/9]

__IO uint32_t PIT_Type::TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10

◆ TCTRL [3/9]

__IO uint16_t PWM_Type::TCTRL

Output Trigger Control Register, array offset: 0x2A, array step: 0x60

◆  [4/9]

__IO uint16_t { ... } ::TCTRL

Output Trigger Control Register, array offset: 0x2A, array step: 0x60

◆ TCTRL [5/9]

__IO uint32_t ADC_Type::TCTRL

Trigger Control Register, array offset: 0xC0, array step: 0x4

◆  [6/9]

__IO uint32_t { ... } ::TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10

◆  [7/9]

__IO uint16_t { ... } ::TCTRL

Output Trigger Control Register, array offset: 0x2A, array step: 0x60

◆  [8/9]

__IO uint32_t { ... } ::TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10

◆  [9/9]

__IO uint16_t { ... } ::TCTRL

Output Trigger Control Register, array offset: 0x2A, array step: 0x60

◆ TDAR

__IO uint32_t ENET_Type::TDAR

Transmit Descriptor Active Register - Ring 0, offset: 0x14

◆ TDAR1

__IO uint32_t ENET_Type::TDAR1

Transmit Descriptor Active Register - Ring 1, offset: 0x1E4

◆ TDAR2

__IO uint32_t ENET_Type::TDAR2

Transmit Descriptor Active Register - Ring 2, offset: 0x1EC

◆ TDKEKR

__IO uint32_t CAAM_Type::TDKEKR

Trusted Descriptor Key Encryption Key Register, array offset: 0x420, array step: 0x4

◆ TDR [1/2]

__O uint32_t I2S_Type::TDR

SAI Transmit Data Register, array offset: 0x20, array step: 0x4

Transmit Data, array offset: 0x20, array step: 0x4

◆ TDR [2/2]

__O uint32_t LPSPI_Type::TDR

Transmit Data Register, offset: 0x64

Transmit Data, offset: 0x64

◆ TDSKR

__IO uint32_t CAAM_Type::TDSKR

Trusted Descriptor Signing Key Register, array offset: 0x440, array step: 0x4

◆ TDSR

__IO uint32_t ENET_Type::TDSR

Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184

◆ TDSR1

__IO uint32_t ENET_Type::TDSR1

Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164

◆ TDSR2

__IO uint32_t ENET_Type::TDSR2

Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170

◆ TEMPSENSE0

__IO uint32_t TEMPMON_Type::TEMPSENSE0

Tempsensor Control Register 0, offset: 0x180

◆ TEMPSENSE0_CLR

__IO uint32_t TEMPMON_Type::TEMPSENSE0_CLR

Tempsensor Control Register 0, offset: 0x188

◆ TEMPSENSE0_SET

__IO uint32_t TEMPMON_Type::TEMPSENSE0_SET

Tempsensor Control Register 0, offset: 0x184

◆ TEMPSENSE0_TOG

__IO uint32_t TEMPMON_Type::TEMPSENSE0_TOG

Tempsensor Control Register 0, offset: 0x18C

◆ TEMPSENSE1

__IO uint32_t TEMPMON_Type::TEMPSENSE1

Tempsensor Control Register 1, offset: 0x190

◆ TEMPSENSE1_CLR

__IO uint32_t TEMPMON_Type::TEMPSENSE1_CLR

Tempsensor Control Register 1, offset: 0x198

◆ TEMPSENSE1_SET

__IO uint32_t TEMPMON_Type::TEMPSENSE1_SET

Tempsensor Control Register 1, offset: 0x194

◆ TEMPSENSE1_TOG

__IO uint32_t TEMPMON_Type::TEMPSENSE1_TOG

Tempsensor Control Register 1, offset: 0x19C

◆ TEMPSENSE2

__IO uint32_t TEMPMON_Type::TEMPSENSE2

Tempsensor Control Register 2, offset: 0x290

◆ TEMPSENSE2_CLR

__IO uint32_t TEMPMON_Type::TEMPSENSE2_CLR

Tempsensor Control Register 2, offset: 0x298

◆ TEMPSENSE2_SET

__IO uint32_t TEMPMON_Type::TEMPSENSE2_SET

Tempsensor Control Register 2, offset: 0x294

◆ TEMPSENSE2_TOG

__IO uint32_t TEMPMON_Type::TEMPSENSE2_TOG

Tempsensor Control Register 2, offset: 0x29C

◆ TEMPSENSOR

__IO uint32_t ANADIG_TEMPSENSOR_Type::TEMPSENSOR

Tempsensor Register, offset: 0x400

◆ TEMPSNS_OTP_TRIM_VALUE

__I uint32_t ANADIG_TEMPSENSOR_Type::TEMPSNS_OTP_TRIM_VALUE

TEMPSNS_OTP_TRIM_VALUE_REGISTER, offset: 0x430

◆ TFDR

__O uint32_t FLEXSPI_Type::TFDR

IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4

◆ TFLG [1/4]

__IO uint32_t PIT_Type::TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10

◆  [2/4]

__IO uint32_t { ... } ::TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10

◆  [3/4]

__IO uint32_t { ... } ::TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10

◆  [4/4]

__IO uint32_t { ... } ::TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10

◆ TFR

__I uint32_t I2S_Type::TFR

SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4

Transmit FIFO, array offset: 0x40, array step: 0x4

◆ TFWR

__IO uint32_t ENET_Type::TFWR

Transmit FIFO Watermark Register, offset: 0x144

◆ TGSR

__IO uint32_t ENET_Type::TGSR

Timer Global Status Register, offset: 0x604

◆ THRES

__IO uint32_t LCDIF_Type::THRES

LCDIF Threshold Register, offset: 0x200

◆ TIMCFG

__IO uint32_t FLEXIO_Type::TIMCFG

Timer Configuration N Register, array offset: 0x480, array step: 0x4

◆ TIMCMP

__IO uint32_t FLEXIO_Type::TIMCMP

Timer Compare N Register, array offset: 0x500, array step: 0x4

◆ TIMCTL

__IO uint32_t FLEXIO_Type::TIMCTL

Timer Control N Register, array offset: 0x400, array step: 0x4

◆ TIMER

__IO uint32_t CAN_Type::TIMER

Free Running Timer Register, offset: 0x8

Free Running Timer, offset: 0x8

◆ TIMER0

__IO uint32_t USBHSDCD_Type::TIMER0

TIMER0 register, offset: 0x10

◆ TIMER1

__IO uint32_t USBHSDCD_Type::TIMER1

TIMER1 register, offset: 0x14

◆ TIMER2_BC11 [1/3]

__IO uint32_t USBHSDCD_Type::TIMER2_BC11

TIMER2_BC11 register, offset: 0x18

◆  [2/3]

__IO uint32_t { ... } ::TIMER2_BC11

TIMER2_BC11 register, offset: 0x18

◆  [3/3]

__IO uint32_t { ... } ::TIMER2_BC11

TIMER2_BC11 register, offset: 0x18

◆ TIMER2_BC12 [1/3]

__IO uint32_t USBHSDCD_Type::TIMER2_BC12

TIMER2_BC12 register, offset: 0x18

◆  [2/3]

__IO uint32_t { ... } ::TIMER2_BC12

TIMER2_BC12 register, offset: 0x18

◆  [3/3]

__IO uint32_t { ... } ::TIMER2_BC12

TIMER2_BC12 register, offset: 0x18

◆ TIMERSDEN

__IO uint32_t FLEXIO_Type::TIMERSDEN

Timer Status DMA Enable, offset: 0x38

◆ TIMIEN

__IO uint32_t FLEXIO_Type::TIMIEN

Timer Interrupt Enable Register, offset: 0x28

◆ TIMING

__IO uint32_t OCOTP_Type::TIMING

OTP Controller Timing Register, offset: 0x10

◆ TIMING2

__IO uint32_t OCOTP_Type::TIMING2

OTP Controller Timing Register 2, offset: 0x100

◆ TIMSTAT

__IO uint32_t FLEXIO_Type::TIMSTAT

Timer Status Register, offset: 0x18

◆ TIPG

__IO uint32_t ENET_Type::TIPG

Transmit Inter-Packet Gap, offset: 0x1AC

◆ TMR

__IO uint32_t I2S_Type::TMR

SAI Transmit Mask Register, offset: 0x60

Transmit Mask, offset: 0x60

◆ TOG [1/69]

__IO uint32_t AUDIO_PLL_Type::TOG

Fractional PLL Control Register, offset: 0xC

Fractional PLL Spread Spectrum Control Register, offset: 0x1C

Fractional PLL Numerator Control Register, offset: 0x2C

Fractional PLL Denominator Control Register, offset: 0x3C

◆  [2/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Control Register, offset: 0xC

◆  [3/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Spread Spectrum Control Register, offset: 0x1C

◆  [4/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Numerator Control Register, offset: 0x2C

◆  [5/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Denominator Control Register, offset: 0x3C

◆  [6/69]

__IO uint32_t { ... } ::TOG

General Purpose Register, array offset: 0x480C, array step: 0x20

◆ TOG [7/69]

__IO uint32_t CCM_Type::TOG

General Purpose Register, array offset: 0x480C, array step: 0x20

◆  [8/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Control Register, offset: 0xC

◆ TOG [9/69]

__IO uint32_t ETHERNET_PLL_Type::TOG

Fractional PLL Control Register, offset: 0xC

Fractional PLL Spread Spectrum Control Register, offset: 0x1C

Fractional PLL Numerator Control Register, offset: 0x2C

Fractional PLL Denominator Control Register, offset: 0x3C

◆  [10/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Spread Spectrum Control Register, offset: 0x1C

◆  [11/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Numerator Control Register, offset: 0x2C

◆  [12/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Denominator Control Register, offset: 0x3C

◆ TOG [13/69]

__IO uint32_t OSC_RC_400M_Type::TOG

Control Register 0, offset: 0xC

Control Register 1, offset: 0x1C

Control Register 2, offset: 0x2C

Control Register 3, offset: 0x3C

◆  [14/69]

__IO uint32_t { ... } ::TOG

Control Register 0, offset: 0xC

◆  [15/69]

__IO uint32_t { ... } ::TOG

Control Register 1, offset: 0x1C

◆  [16/69]

__IO uint32_t { ... } ::TOG

Control Register 2, offset: 0x2C

◆  [17/69]

__IO uint32_t { ... } ::TOG

Control Register 3, offset: 0x3C

◆ TOG [18/69]

__I uint32_t OSC_RC_400M_Type::TOG

Status Register 0, offset: 0x5C

Status Register 1, offset: 0x6C

Status Register 2, offset: 0x7C

◆  [19/69]

__I uint32_t { ... } ::TOG

Status Register 0, offset: 0x5C

◆  [20/69]

__I uint32_t { ... } ::TOG

Status Register 1, offset: 0x6C

◆  [21/69]

__I uint32_t { ... } ::TOG

Status Register 2, offset: 0x7C

◆  [22/69]

__IO uint32_t { ... } ::TOG

Analog Control Register CTRL0, offset: 0xC

◆ TOG [23/69]

__IO uint32_t PHY_LDO_Type::TOG

Analog Control Register CTRL0, offset: 0xC

◆ TOG [24/69]

__I uint32_t PHY_LDO_Type::TOG

Analog Status Register STAT0, offset: 0x5C

◆  [25/69]

__I uint32_t { ... } ::TOG

Analog Status Register STAT0, offset: 0x5C

◆ TOG [26/69]

__IO uint32_t VIDEO_MUX_Type::TOG

Video mux Control Register, offset: 0xC

Pixel Link Master(PLM) Control Register, offset: 0x2C

YUV420 Control Register, offset: 0x3C

Data Disable Register, offset: 0x5C

MIPI DSI Control Register, offset: 0x7C

◆  [27/69]

__IO uint32_t { ... } ::TOG

Video mux Control Register, offset: 0xC

◆  [28/69]

__IO uint32_t { ... } ::TOG

Pixel Link Master(PLM) Control Register, offset: 0x2C

◆  [29/69]

__IO uint32_t { ... } ::TOG

YUV420 Control Register, offset: 0x3C

◆  [30/69]

__IO uint32_t { ... } ::TOG

Data Disable Register, offset: 0x5C

◆  [31/69]

__IO uint32_t { ... } ::TOG

MIPI DSI Control Register, offset: 0x7C

◆ TOG [32/69]

__IO uint32_t VIDEO_PLL_Type::TOG

Fractional PLL Control Register, offset: 0xC

Fractional PLL Spread Spectrum Control Register, offset: 0x1C

Fractional PLL Numerator Control Register, offset: 0x2C

Fractional PLL Denominator Control Register, offset: 0x3C

◆  [33/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Control Register, offset: 0xC

◆  [34/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Spread Spectrum Control Register, offset: 0x1C

◆  [35/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Numerator Control Register, offset: 0x2C

◆  [36/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Denominator Control Register, offset: 0x3C

◆  [37/69]

__IO uint32_t { ... } ::TOG

Analog Control Register CTRL0, offset: 0xC

◆ TOG [38/69]

__IO uint32_t VMBANDGAP_Type::TOG

Analog Control Register CTRL0, offset: 0xC

◆ TOG [39/69]

__I uint32_t VMBANDGAP_Type::TOG

Analog Status Register STAT0, offset: 0x5C

◆  [40/69]

__I uint32_t { ... } ::TOG

Analog Status Register STAT0, offset: 0x5C

◆  [41/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Control Register, offset: 0xC

◆  [42/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Spread Spectrum Control Register, offset: 0x1C

◆  [43/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Numerator Control Register, offset: 0x2C

◆  [44/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Denominator Control Register, offset: 0x3C

◆  [45/69]

__IO uint32_t { ... } ::TOG

General Purpose Register, array offset: 0x480C, array step: 0x20

◆  [46/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Control Register, offset: 0xC

◆  [47/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Spread Spectrum Control Register, offset: 0x1C

◆  [48/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Numerator Control Register, offset: 0x2C

◆  [49/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Denominator Control Register, offset: 0x3C

◆  [50/69]

__IO uint32_t { ... } ::TOG

Control Register 0, offset: 0xC

◆  [51/69]

__IO uint32_t { ... } ::TOG

Control Register 1, offset: 0x1C

◆  [52/69]

__IO uint32_t { ... } ::TOG

Control Register 2, offset: 0x2C

◆  [53/69]

__IO uint32_t { ... } ::TOG

Control Register 3, offset: 0x3C

◆  [54/69]

__I uint32_t { ... } ::TOG

Status Register 0, offset: 0x5C

◆  [55/69]

__I uint32_t { ... } ::TOG

Status Register 1, offset: 0x6C

◆  [56/69]

__I uint32_t { ... } ::TOG

Status Register 2, offset: 0x7C

◆  [57/69]

__IO uint32_t { ... } ::TOG

Analog Control Register CTRL0, offset: 0xC

◆  [58/69]

__I uint32_t { ... } ::TOG

Analog Status Register STAT0, offset: 0x5C

◆  [59/69]

__IO uint32_t { ... } ::TOG

Video mux Control Register, offset: 0xC

◆  [60/69]

__IO uint32_t { ... } ::TOG

Pixel Link Master(PLM) Control Register, offset: 0x2C

◆  [61/69]

__IO uint32_t { ... } ::TOG

YUV420 Control Register, offset: 0x3C

◆  [62/69]

__IO uint32_t { ... } ::TOG

Data Disable Register, offset: 0x5C

◆  [63/69]

__IO uint32_t { ... } ::TOG

MIPI DSI Control Register, offset: 0x7C

◆  [64/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Control Register, offset: 0xC

◆  [65/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Spread Spectrum Control Register, offset: 0x1C

◆  [66/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Numerator Control Register, offset: 0x2C

◆  [67/69]

__IO uint32_t { ... } ::TOG

Fractional PLL Denominator Control Register, offset: 0x3C

◆  [68/69]

__IO uint32_t { ... } ::TOG

Analog Control Register CTRL0, offset: 0xC

◆  [69/69]

__I uint32_t { ... } ::TOG

Analog Status Register STAT0, offset: 0x5C

◆ TOTSAM [1/2]

__I uint32_t TRNG_Type::TOTSAM

Total Samples Register, offset: 0x14

◆  [2/2]

__I uint32_t { ... } ::TOTSAM

Total Samples Register, offset: 0x14

◆ TOVAL

__IO uint32_t RTWDOG_Type::TOVAL

Watchdog Timeout Value Register, offset: 0x8

◆ TR

__IO uint32_t MU_Type::TR

Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array step: 0x4

Processor A Transmit Register 0..Processor A Transmit Register 3, array offset: 0x0, array step: 0x4

◆ TRANSFER_COUNT

__IO uint32_t LCDIF_Type::TRANSFER_COUNT

LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30

◆  [1/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_1_0

ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28

◆ TRIGn_CHAIN_1_0 [2/4]

__IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_1_0

ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28

◆  [3/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_1_0

ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28

◆  [4/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_1_0

ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28

◆  [1/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_3_2

ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28

◆ TRIGn_CHAIN_3_2 [2/4]

__IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_3_2

ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28

◆  [3/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_3_2

ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28

◆  [4/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_3_2

ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28

◆ TRIGn_CHAIN_5_4 [1/4]

__IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_5_4

ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28

◆  [2/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_5_4

ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28

◆  [3/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_5_4

ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28

◆  [4/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_5_4

ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28

◆ TRIGn_CHAIN_7_6 [1/4]

__IO uint32_t ADC_ETC_Type::TRIGn_CHAIN_7_6

ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28

◆  [2/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_7_6

ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28

◆  [3/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_7_6

ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28

◆  [4/4]

__IO uint32_t { ... } ::TRIGn_CHAIN_7_6

ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28

◆  [1/4]

__IO uint32_t { ... } ::TRIGn_COUNTER

ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28

◆ TRIGn_COUNTER [2/4]

__IO uint32_t ADC_ETC_Type::TRIGn_COUNTER

ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28

◆  [3/4]

__IO uint32_t { ... } ::TRIGn_COUNTER

ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28

◆  [4/4]

__IO uint32_t { ... } ::TRIGn_COUNTER

ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28

◆ TRIGn_CTRL [1/4]

__IO uint32_t ADC_ETC_Type::TRIGn_CTRL

ETC_TRIG Control Register, array offset: 0x10, array step: 0x28

◆  [2/4]

__IO uint32_t { ... } ::TRIGn_CTRL

ETC_TRIG Control Register, array offset: 0x10, array step: 0x28

◆  [3/4]

__IO uint32_t { ... } ::TRIGn_CTRL

ETC_TRIG Control Register, array offset: 0x10, array step: 0x28

◆  [4/4]

__IO uint32_t { ... } ::TRIGn_CTRL

ETC_TRIG Control Register, array offset: 0x10, array step: 0x28

◆ TRIGn_RESULT_1_0 [1/4]

__I uint32_t ADC_ETC_Type::TRIGn_RESULT_1_0

ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28

◆  [2/4]

__I uint32_t { ... } ::TRIGn_RESULT_1_0

ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28

◆  [3/4]

__I uint32_t { ... } ::TRIGn_RESULT_1_0

ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28

◆  [4/4]

__I uint32_t { ... } ::TRIGn_RESULT_1_0

ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28

◆ TRIGn_RESULT_3_2 [1/4]

__I uint32_t ADC_ETC_Type::TRIGn_RESULT_3_2

ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28

◆  [2/4]

__I uint32_t { ... } ::TRIGn_RESULT_3_2

ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28

◆  [3/4]

__I uint32_t { ... } ::TRIGn_RESULT_3_2

ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28

◆  [4/4]

__I uint32_t { ... } ::TRIGn_RESULT_3_2

ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28

◆ TRIGn_RESULT_5_4 [1/4]

__I uint32_t ADC_ETC_Type::TRIGn_RESULT_5_4

ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28

◆  [2/4]

__I uint32_t { ... } ::TRIGn_RESULT_5_4

ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28

◆  [3/4]

__I uint32_t { ... } ::TRIGn_RESULT_5_4

ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28

◆  [4/4]

__I uint32_t { ... } ::TRIGn_RESULT_5_4

ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28

◆ TRIGn_RESULT_7_6 [1/4]

__I uint32_t ADC_ETC_Type::TRIGn_RESULT_7_6

ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28

◆  [2/4]

__I uint32_t { ... } ::TRIGn_RESULT_7_6

ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28

◆  [3/4]

__I uint32_t { ... } ::TRIGn_RESULT_7_6

ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28

◆  [4/4]

__I uint32_t { ... } ::TRIGn_RESULT_7_6

ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28

◆ TRIM_OVERRIDE_EN

__IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN

USB PHY Trim Override Enable Register, offset: 0x130

◆ TRIM_OVERRIDE_EN_CLR

__IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_CLR

USB PHY Trim Override Enable Register, offset: 0x138

◆ TRIM_OVERRIDE_EN_SET

__IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_SET

USB PHY Trim Override Enable Register, offset: 0x134

◆ TRIM_OVERRIDE_EN_TOG

__IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_TOG

USB PHY Trim Override Enable Register, offset: 0x13C

◆ TSEM

__IO uint32_t ENET_Type::TSEM

Transmit FIFO Section Empty Threshold, offset: 0x1A0

◆ TST [1/2]

__IO uint16_t ENC_Type::TST

Test Register, offset: 0x1C

◆ TST [2/2]

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::TST

TST, offset: 0x20

◆ TSTMD

__IO uint32_t IEE_Type::TSTMD

IEE Test Mode Register, offset: 0x8

◆ TUNING_CTRL

__IO uint32_t USDHC_Type::TUNING_CTRL

Tuning Control, offset: 0xCC

◆ TX

__IO uint32_t USBPHY_Type::TX

USB PHY Transmitter Control Register, offset: 0x10

◆ TX_BUF

__O uint32_t EMVSIM_Type::TX_BUF

Transmit Data Buffer, offset: 0x30

◆ TX_CLR

__IO uint32_t USBPHY_Type::TX_CLR

USB PHY Transmitter Control Register, offset: 0x18

◆ TX_GETU

__IO uint32_t EMVSIM_Type::TX_GETU

Transmitter Guard ETU Value Register, offset: 0x34

◆ TX_PAYLOAD

__IO uint32_t DSI_HOST_APB_PKT_IF_Type::TX_PAYLOAD

TX_PAYLOAD, offset: 0x0

◆ TX_RCAL

__IO uint32_t DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type::TX_RCAL

TX_RCAL, offset: 0x38

◆ TX_SET

__IO uint32_t USBPHY_Type::TX_SET

USB PHY Transmitter Control Register, offset: 0x14

◆ TX_STATUS

__IO uint32_t EMVSIM_Type::TX_STATUS

Transmitter Status Register, offset: 0x24

◆ TX_THD

__IO uint32_t EMVSIM_Type::TX_THD

Transmitter Threshold Register, offset: 0x1C

◆ TX_TOG

__IO uint32_t USBPHY_Type::TX_TOG

USB PHY Transmitter Control Register, offset: 0x1C

◆ TXFILLTUNING

__IO uint32_t USB_Type::TXFILLTUNING

TX FIFO Fill Tuning, offset: 0x164

◆ TXIC

__IO uint32_t ENET_Type::TXIC

Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4

◆ UCOMP

__IO uint16_t ENC_Type::UCOMP

Upper Position Compare Register, offset: 0x24

◆ UINIT

__IO uint16_t ENC_Type::UINIT

Upper Initialization Register, offset: 0x16

◆ ULPS_STATUS

__I uint32_t MIPI_CSI2RX_Type::ULPS_STATUS

Ultra Low Power State (ULPS) Status Register, offset: 0x114

◆ UMOD

__IO uint16_t ENC_Type::UMOD

Upper Modulus Register, offset: 0x20

◆ UPOS

__IO uint16_t ENC_Type::UPOS

Upper Position Counter Register, offset: 0xE

◆ UPOSH

__I uint16_t ENC_Type::UPOSH

Upper Position Hold Register, offset: 0x12

◆ USB1_CHRG_DET_STAT

__I uint32_t USBPHY_Type::USB1_CHRG_DET_STAT

USB PHY Charger Detect Status Register, offset: 0xF0

◆ USB1_CHRG_DETECT

__IO uint32_t USBPHY_Type::USB1_CHRG_DETECT

USB PHY Charger Detect Control Register, offset: 0xE0

◆ USB1_CHRG_DETECT_CLR

__IO uint32_t USBPHY_Type::USB1_CHRG_DETECT_CLR

USB PHY Charger Detect Control Register, offset: 0xE8

◆ USB1_CHRG_DETECT_SET

__IO uint32_t USBPHY_Type::USB1_CHRG_DETECT_SET

USB PHY Charger Detect Control Register, offset: 0xE4

◆ USB1_CHRG_DETECT_TOG

__IO uint32_t USBPHY_Type::USB1_CHRG_DETECT_TOG

USB PHY Charger Detect Control Register, offset: 0xEC

◆ USB1_LOOPBACK

__IO uint32_t USBPHY_Type::USB1_LOOPBACK

USB PHY Loopback Control/Status Register, offset: 0x110

◆ USB1_LOOPBACK_CLR

__IO uint32_t USBPHY_Type::USB1_LOOPBACK_CLR

USB PHY Loopback Control/Status Register, offset: 0x118

◆ USB1_LOOPBACK_HSFSCNT

__IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT

USB PHY Loopback Packet Number Select Register, offset: 0x120

◆ USB1_LOOPBACK_HSFSCNT_CLR

__IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_CLR

USB PHY Loopback Packet Number Select Register, offset: 0x128

◆ USB1_LOOPBACK_HSFSCNT_SET

__IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_SET

USB PHY Loopback Packet Number Select Register, offset: 0x124

◆ USB1_LOOPBACK_HSFSCNT_TOG

__IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_TOG

USB PHY Loopback Packet Number Select Register, offset: 0x12C

◆ USB1_LOOPBACK_SET

__IO uint32_t USBPHY_Type::USB1_LOOPBACK_SET

USB PHY Loopback Control/Status Register, offset: 0x114

◆ USB1_LOOPBACK_TOG

__IO uint32_t USBPHY_Type::USB1_LOOPBACK_TOG

USB PHY Loopback Control/Status Register, offset: 0x11C

◆ USB1_VBUS_DET_STAT

__I uint32_t USBPHY_Type::USB1_VBUS_DET_STAT

USB PHY VBUS Detector Status Register, offset: 0xD0

◆ USB1_VBUS_DETECT

__IO uint32_t USBPHY_Type::USB1_VBUS_DETECT

USB PHY VBUS Detect Control Register, offset: 0xC0

◆ USB1_VBUS_DETECT_CLR

__IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_CLR

USB PHY VBUS Detect Control Register, offset: 0xC8

◆ USB1_VBUS_DETECT_SET

__IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_SET

USB PHY VBUS Detect Control Register, offset: 0xC4

◆ USB1_VBUS_DETECT_TOG

__IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_TOG

USB PHY VBUS Detect Control Register, offset: 0xCC

◆ USB_OTGn_CTRL

__IO uint32_t USBNC_Type::USB_OTGn_CTRL

USB OTG1 Control Register..USB OTG2 Control Register, offset: 0x800

◆ USB_OTGn_PHY_CTRL_0

__IO uint32_t USBNC_Type::USB_OTGn_PHY_CTRL_0

OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register, offset: 0x818

◆ USBCMD

__IO uint32_t USB_Type::USBCMD

USB Command Register, offset: 0x140

◆ USBINTR

__IO uint32_t USB_Type::USBINTR

Interrupt Enable Register, offset: 0x148

◆ USBMODE

__IO uint32_t USB_Type::USBMODE

USB Device Mode, offset: 0x1A8

◆ USBSTS

__IO uint32_t USB_Type::USBSTS

USB Status Register, offset: 0x144

◆ USE_NULL_PKT_BLLP

__IO uint32_t DSI_HOST_DPI_INTFC_Type::USE_NULL_PKT_BLLP

USE_NULL_PKT_BLLP, offset: 0x38

◆ UVSIL [1/3]

__IO uint32_t CAAM_Type::UVSIL

Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C

◆  [2/3]

__IO uint32_t { ... } ::UVSIL

Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::UVSIL

Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C

◆ UVSOL [1/3]

__IO uint32_t CAAM_Type::UVSOL

Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C

◆  [2/3]

__IO uint32_t { ... } ::UVSOL

Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::UVSOL

Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C

◆ VACTIVE

__IO uint32_t DSI_HOST_DPI_INTFC_Type::VACTIVE

VACTIVE, offset: 0x3C

◆ VAD0_CTRL_1

__IO uint32_t PDM_Type::VAD0_CTRL_1

Voice Activity Detector 0 Control register, offset: 0x90

◆ VAD0_CTRL_2

__IO uint32_t PDM_Type::VAD0_CTRL_2

Voice Activity Detector 0 Control register, offset: 0x94

◆ VAD0_NCONFIG

__IO uint32_t PDM_Type::VAD0_NCONFIG

Voice Activity Detector 0 Noise Configuration, offset: 0xA0

◆ VAD0_NDATA

__I uint32_t PDM_Type::VAD0_NDATA

Voice Activity Detector 0 Noise Data, offset: 0xA4

◆ VAD0_SCONFIG

__IO uint32_t PDM_Type::VAD0_SCONFIG

Voice Activity Detector 0 Signal Configuration, offset: 0x9C

◆ VAD0_STAT

__IO uint32_t PDM_Type::VAD0_STAT

Voice Activity Detector 0 Status register, offset: 0x98

◆ VAD0_ZCD

__IO uint32_t PDM_Type::VAD0_ZCD

Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8

◆ VAL0 [1/4]

__IO uint16_t PWM_Type::VAL0

Value Register 0, array offset: 0xA, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::VAL0

Value Register 0, array offset: 0xA, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::VAL0

Value Register 0, array offset: 0xA, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::VAL0

Value Register 0, array offset: 0xA, array step: 0x60

◆ VAL1 [1/4]

__IO uint16_t PWM_Type::VAL1

Value Register 1, array offset: 0xE, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::VAL1

Value Register 1, array offset: 0xE, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::VAL1

Value Register 1, array offset: 0xE, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::VAL1

Value Register 1, array offset: 0xE, array step: 0x60

◆ VAL2 [1/4]

__IO uint16_t PWM_Type::VAL2

Value Register 2, array offset: 0x12, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::VAL2

Value Register 2, array offset: 0x12, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::VAL2

Value Register 2, array offset: 0x12, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::VAL2

Value Register 2, array offset: 0x12, array step: 0x60

◆ VAL3 [1/4]

__IO uint16_t PWM_Type::VAL3

Value Register 3, array offset: 0x16, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::VAL3

Value Register 3, array offset: 0x16, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::VAL3

Value Register 3, array offset: 0x16, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::VAL3

Value Register 3, array offset: 0x16, array step: 0x60

◆ VAL4 [1/4]

__IO uint16_t PWM_Type::VAL4

Value Register 4, array offset: 0x1A, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::VAL4

Value Register 4, array offset: 0x1A, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::VAL4

Value Register 4, array offset: 0x1A, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::VAL4

Value Register 4, array offset: 0x1A, array step: 0x60

◆ VAL5 [1/4]

__IO uint16_t PWM_Type::VAL5

Value Register 5, array offset: 0x1E, array step: 0x60

◆  [2/4]

__IO uint16_t { ... } ::VAL5

Value Register 5, array offset: 0x1E, array step: 0x60

◆  [3/4]

__IO uint16_t { ... } ::VAL5

Value Register 5, array offset: 0x1E, array step: 0x60

◆  [4/4]

__IO uint16_t { ... } ::VAL5

Value Register 5, array offset: 0x1E, array step: 0x60

◆ VBP

__IO uint32_t DSI_HOST_DPI_INTFC_Type::VBP

VBP, offset: 0x2C

◆  [1/2]

__IO uint32_t { ... } ::VBUS_DETECT

USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60

◆ VBUS_DETECT [2/2]

__IO uint32_t USB_ANALOG_Type::VBUS_DETECT

USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60

◆  [1/2]

__IO uint32_t { ... } ::VBUS_DETECT_CLR

USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60

◆ VBUS_DETECT_CLR [2/2]

__IO uint32_t USB_ANALOG_Type::VBUS_DETECT_CLR

USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60

◆  [1/2]

__IO uint32_t { ... } ::VBUS_DETECT_SET

USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60

◆ VBUS_DETECT_SET [2/2]

__IO uint32_t USB_ANALOG_Type::VBUS_DETECT_SET

USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60

◆  [1/2]

__I uint32_t { ... } ::VBUS_DETECT_STAT

USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60

◆ VBUS_DETECT_STAT [2/2]

__I uint32_t USB_ANALOG_Type::VBUS_DETECT_STAT

USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60

◆  [1/2]

__IO uint32_t { ... } ::VBUS_DETECT_TOG

USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60

◆ VBUS_DETECT_TOG [2/2]

__IO uint32_t USB_ANALOG_Type::VBUS_DETECT_TOG

USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60

◆ VDCTRL0

__IO uint32_t LCDIF_Type::VDCTRL0

LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70

◆ VDCTRL0_CLR

__IO uint32_t LCDIF_Type::VDCTRL0_CLR

LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78

◆ VDCTRL0_SET

__IO uint32_t LCDIF_Type::VDCTRL0_SET

LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74

◆ VDCTRL0_TOG

__IO uint32_t LCDIF_Type::VDCTRL0_TOG

LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C

◆ VDCTRL1

__IO uint32_t LCDIF_Type::VDCTRL1

LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80

◆ VDCTRL2

__IO uint32_t LCDIF_Type::VDCTRL2

LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90

◆ VDCTRL3

__IO uint32_t LCDIF_Type::VDCTRL3

LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0

◆ VDCTRL4

__IO uint32_t LCDIF_Type::VDCTRL4

LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0

◆ VDDLPSR_AI400M_CTRL

__IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI400M_CTRL

VDDLPSR_AI400M_CTRL_REGISTER, offset: 0x920

◆ VDDLPSR_AI400M_RDATA

__I uint32_t ANADIG_MISC_Type::VDDLPSR_AI400M_RDATA

VDDLPSR_AI400M_RDATA_REGISTER, offset: 0x940

◆ VDDLPSR_AI400M_WDATA

__IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI400M_WDATA

VDDLPSR_AI400M_WDATA_REGISTER, offset: 0x930

◆ VDDLPSR_AI_CTRL

__IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI_CTRL

VDDSOC_AI_CTRL_REGISTER, offset: 0x8E0

◆ VDDLPSR_AI_RDATA_REFTOP

__I uint32_t ANADIG_MISC_Type::VDDLPSR_AI_RDATA_REFTOP

VDDLPSR_AI_RDATA_REFTOP_REGISTER, offset: 0x900

◆ VDDLPSR_AI_RDATA_TMPSNS

__I uint32_t ANADIG_MISC_Type::VDDLPSR_AI_RDATA_TMPSNS

VDDLPSR_AI_RDATA_TMPSNS_REGISTER, offset: 0x910

◆ VDDLPSR_AI_WDATA

__IO uint32_t ANADIG_MISC_Type::VDDLPSR_AI_WDATA

VDDLPSR_AI_WDATA_REGISTER, offset: 0x8F0

◆ VDDSOC2PLL_AI_CTRL_1G

__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_CTRL_1G

VDDSOC2PLL_AI_CTRL_1G_REGISTER, offset: 0x850

◆ VDDSOC2PLL_AI_CTRL_AUDIO

__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_CTRL_AUDIO

VDDSOC_AI_CTRL_AUDIO_REGISTER, offset: 0x880

◆ VDDSOC2PLL_AI_CTRL_VIDEO

__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_CTRL_VIDEO

VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER, offset: 0x8B0

◆ VDDSOC2PLL_AI_RDATA_1G

__I uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_RDATA_1G

VDDSOC2PLL_AI_RDATA_1G_REGISTER, offset: 0x870

◆ VDDSOC2PLL_AI_RDATA_AUDIO

__I uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_RDATA_AUDIO

VDDSOC2PLL_AI_RDATA_REGISTER, offset: 0x8A0

◆ VDDSOC2PLL_AI_RDATA_VIDEO

__I uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_RDATA_VIDEO

VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER, offset: 0x8D0

◆ VDDSOC2PLL_AI_WDATA_1G

__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_WDATA_1G

VDDSOC2PLL_AI_WDATA_1G_REGISTER, offset: 0x860

◆ VDDSOC2PLL_AI_WDATA_AUDIO

__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_WDATA_AUDIO

VDDSOC_AI_WDATA_AUDIO_REGISTER, offset: 0x890

◆ VDDSOC2PLL_AI_WDATA_VIDEO

__IO uint32_t ANADIG_MISC_Type::VDDSOC2PLL_AI_WDATA_VIDEO

VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER, offset: 0x8C0

◆ VDDSOC_AI_CTRL

__IO uint32_t ANADIG_MISC_Type::VDDSOC_AI_CTRL

VDDSOC_AI_CTRL_REGISTER, offset: 0x820

◆ VDDSOC_AI_RDATA

__I uint32_t ANADIG_MISC_Type::VDDSOC_AI_RDATA

VDDSOC_AI_RDATA_REGISTER, offset: 0x840

◆ VDDSOC_AI_WDATA

__IO uint32_t ANADIG_MISC_Type::VDDSOC_AI_WDATA

VDDSOC_AI_WDATA_REGISTER, offset: 0x830

◆ VEND_SPEC

__IO uint32_t USDHC_Type::VEND_SPEC

Vendor Specific Register, offset: 0xC0

◆ VEND_SPEC2

__IO uint32_t USDHC_Type::VEND_SPEC2

Vendor Specific 2 Register, offset: 0xC8

◆ VER_ID

__I uint32_t EMVSIM_Type::VER_ID

Version ID Register, offset: 0x0

◆ VERID [1/8]

__I uint32_t FLEXIO_Type::VERID

Version ID Register, offset: 0x0

◆ VERID [2/8]

__I uint32_t I2S_Type::VERID

Version ID Register, offset: 0x0

Version ID, offset: 0x0

◆ VERID [3/8]

__I uint32_t LPI2C_Type::VERID

Version ID Register, offset: 0x0

Version ID, offset: 0x0

◆ VERID [4/8]

__I uint32_t LPSPI_Type::VERID

Version ID Register, offset: 0x0

Version ID, offset: 0x0

◆ VERID [5/8]

__I uint32_t LPUART_Type::VERID

Version ID Register, offset: 0x0

◆ VERID [6/8]

__I uint32_t ADC_Type::VERID

Version ID Register, offset: 0x0

◆ VERID [7/8]

__I uint32_t CMP_Type::VERID

Version ID Register, offset: 0x0

◆ VERID [8/8]

__I uint32_t DAC_Type::VERID

Version Identifier Register, offset: 0x0

◆ VERSION [1/4]

__I uint32_t DCP_Type::VERSION

DCP version register, offset: 0x430

◆ VERSION [2/4]

__I uint32_t OCOTP_Type::VERSION

OTP Controller Version Register, offset: 0x90

OTP Controller Version Register, offset: 0xB0

◆ VERSION [3/4]

__I uint32_t USBPHY_Type::VERSION

UTMI RTL Version, offset: 0x80

◆ VERSION [4/4]

__I uint32_t PUF_Type::VERSION

PUF Version Register, offset: 0xFC

◆ VFP

__IO uint32_t DSI_HOST_DPI_INTFC_Type::VFP

VFP, offset: 0x30

◆ VID1

__I uint32_t TRNG_Type::VID1

Version ID Register (MS), offset: 0xF0

◆ VID2

__I uint32_t TRNG_Type::VID2

Version ID Register (LS), offset: 0xF4

◆ VIDEO_MODE

__IO uint32_t DSI_HOST_DPI_INTFC_Type::VIDEO_MODE

VIDEO_MODE, offset: 0x18

◆ VIDR1

__I uint32_t IEE_Type::VIDR1

IEE Version ID Register 1, offset: 0xF0

◆ VIR

__I uint32_t RDC_Type::VIR

Version Information, offset: 0x0

◆ VSIL [1/3]

__IO uint32_t CAAM_Type::VSIL

Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C

◆  [2/3]

__IO uint32_t { ... } ::VSIL

Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::VSIL

Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C

◆ VSOL [1/3]

__IO uint32_t CAAM_Type::VSOL

Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C

◆  [2/3]

__IO uint32_t { ... } ::VSOL

Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C

◆  [3/3]

__IO uint32_t { ... } ::VSOL

Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C

◆ VSYN_PARA

__IO uint32_t LCDIFV2_Type::VSYN_PARA

Vertical Sync Parameter Register, offset: 0x1C

◆ VSYNC_POLARITY

__IO uint32_t DSI_HOST_DPI_INTFC_Type::VSYNC_POLARITY

VSYNC_POLARITY, offset: 0x10

◆ WATER

__IO uint32_t LPUART_Type::WATER

LPUART Watermark Register, offset: 0x2C

◆ WCR

__IO uint16_t WDOG_Type::WCR

Watchdog Control Register, offset: 0x0

◆ WICR

__IO uint16_t WDOG_Type::WICR

Watchdog Interrupt Control Register, offset: 0x6

◆ WIN

__IO uint32_t RTWDOG_Type::WIN

Watchdog Window Register, offset: 0xC

◆ WMCR

__IO uint16_t WDOG_Type::WMCR

Watchdog Miscellaneous Control Register, offset: 0x8

◆  [1/15]

__IO uint32_t { ... } ::WORD[16]

Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4

◆  [2/15]

__IO uint32_t { ... } ::WORD[16]

Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x288, array step: index*0x48, index2*0x4

◆  [3/15]

__IO uint32_t { ... } ::WORD[16]

Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4

◆  [4/15]

__IO uint32_t { ... } ::WORD[16]

Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x288, array step: index*0x48, index2*0x4

◆  [5/15]

__IO uint32_t { ... } ::WORD[2]

Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4

◆ WORD [6/15]

__IO uint32_t CAN_Type::WORD[16]

Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4

Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4

Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x288, array step: index*0x18, index2*0x4

Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4

Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x288, array step: index*0x28, index2*0x4

Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4

Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x288, array step: index*0x48, index2*0x4

◆  [7/15]

__IO uint32_t { ... } ::WORD[2]

Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4

◆  [8/15]

__IO uint32_t { ... } ::WORD[4]

Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4

◆  [9/15]

__IO uint32_t { ... } ::WORD[4]

Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x288, array step: index*0x18, index2*0x4

◆  [10/15]

__IO uint32_t { ... } ::WORD[4]

Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4

◆  [11/15]

__IO uint32_t { ... } ::WORD[4]

Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x288, array step: index*0x18, index2*0x4

◆  [12/15]

__IO uint32_t { ... } ::WORD[8]

Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4

◆  [13/15]

__IO uint32_t { ... } ::WORD[8]

Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x288, array step: index*0x28, index2*0x4

◆  [14/15]

__IO uint32_t { ... } ::WORD[8]

Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4

◆  [15/15]

__IO uint32_t { ... } ::WORD[8]

Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x288, array step: index*0x28, index2*0x4

◆  [1/4]

__IO uint32_t { ... } ::WORD0

Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10

◆ WORD0 [2/4]

__IO uint32_t CAN_Type::WORD0

Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10

◆  [3/4]

__IO uint32_t { ... } ::WORD0

Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10

◆  [4/4]

__IO uint32_t { ... } ::WORD0

Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10

◆  [1/4]

__IO uint32_t { ... } ::WORD1

Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10

◆ WORD1 [2/4]

__IO uint32_t CAN_Type::WORD1

Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10

◆  [3/4]

__IO uint32_t { ... } ::WORD1

Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10

◆  [4/4]

__IO uint32_t { ... } ::WORD1

Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10

◆ WRSR

__I uint16_t WDOG_Type::WRSR

Watchdog Reset Status Register, offset: 0x4

◆ WSR

__IO uint16_t WDOG_Type::WSR

Watchdog Service Register, offset: 0x2

◆ WTMK_LVL

__IO uint32_t USDHC_Type::WTMK_LVL

Watermark Level, offset: 0x44

◆ WTR

__IO uint16_t ENC_Type::WTR

Watchdog Timeout Register, offset: 0x4

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