RTEMS 6.1-rc4
Loading...
Searching...
No Matches
Modules | Data Structures | Macros

Modules

 DMA Register Masks
 

Data Structures

struct  DMA_Type
 

Macros

#define DMA0_BASE   (0x400E8000u)
 
#define DMA0   ((DMA_Type *)DMA0_BASE)
 
#define DMA_BASE_ADDRS   { DMA0_BASE }
 
#define DMA_BASE_PTRS   { DMA0 }
 
#define DMA_CHN_IRQS   { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
 
#define DMA_ERROR_IRQS   { DMA_ERROR_IRQn }
 
#define DMA1_BASE   (0x40C14000u)
 
#define DMA1   ((DMA_Type *)DMA1_BASE)
 
#define DMA_BASE_ADDRS   { 0u, DMA1_BASE }
 
#define DMA_BASE_PTRS   { (DMA_Type *)0u, DMA1 }
 
#define DMA_CHN_IRQS
 
#define DMA_ERROR_IRQS   { NotAvail_IRQn, DMA_ERROR_IRQn }
 
#define DMA0_BASE   (0x40070000u)
 
#define DMA0   ((DMA_Type *)DMA0_BASE)
 
#define DMA_BASE_ADDRS   { DMA0_BASE }
 
#define DMA_BASE_PTRS   { DMA0 }
 
#define DMA_CHN_IRQS   { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
 
#define DMA_ERROR_IRQS   { DMA_ERROR_IRQn }
 

Detailed Description

Macro Definition Documentation

◆ DMA0 [1/2]

#define DMA0   ((DMA_Type *)DMA0_BASE)

Peripheral DMA0 base pointer

◆ DMA0 [2/2]

#define DMA0   ((DMA_Type *)DMA0_BASE)

Peripheral DMA0 base pointer

◆ DMA0_BASE [1/2]

#define DMA0_BASE   (0x400E8000u)

Peripheral DMA0 base address

◆ DMA0_BASE [2/2]

#define DMA0_BASE   (0x40070000u)

Peripheral DMA0 base address

◆ DMA1

#define DMA1   ((DMA_Type *)DMA1_BASE)

Peripheral DMA1 base pointer

◆ DMA1_BASE

#define DMA1_BASE   (0x40C14000u)

Peripheral DMA1 base address

◆ DMA_BASE_ADDRS [1/3]

#define DMA_BASE_ADDRS   { DMA0_BASE }

Array initializer of DMA peripheral base addresses

◆ DMA_BASE_ADDRS [2/3]

#define DMA_BASE_ADDRS   { 0u, DMA1_BASE }

Array initializer of DMA peripheral base addresses

◆ DMA_BASE_ADDRS [3/3]

#define DMA_BASE_ADDRS   { DMA0_BASE }

Array initializer of DMA peripheral base addresses

◆ DMA_BASE_PTRS [1/3]

#define DMA_BASE_PTRS   { DMA0 }

Array initializer of DMA peripheral base pointers

◆ DMA_BASE_PTRS [2/3]

#define DMA_BASE_PTRS   { (DMA_Type *)0u, DMA1 }

Array initializer of DMA peripheral base pointers

◆ DMA_BASE_PTRS [3/3]

#define DMA_BASE_PTRS   { DMA0 }

Array initializer of DMA peripheral base pointers

◆ DMA_CHN_IRQS [1/3]

Interrupt vectors for the DMA peripheral type

◆ DMA_CHN_IRQS [2/3]

#define DMA_CHN_IRQS
Value:
@ DMA0_DMA16_IRQn
Definition: MIMXRT1166_cm4.h:96
@ DMA14_DMA30_IRQn
Definition: MIMXRT1166_cm4.h:110
@ NotAvail_IRQn
Definition: MIMXRT1166_cm4.h:82
@ DMA13_DMA29_IRQn
Definition: MIMXRT1166_cm4.h:109
@ DMA15_DMA31_IRQn
Definition: MIMXRT1166_cm4.h:111
@ DMA10_DMA26_IRQn
Definition: MIMXRT1166_cm4.h:106
@ DMA5_DMA21_IRQn
Definition: MIMXRT1166_cm4.h:101
@ DMA3_DMA19_IRQn
Definition: MIMXRT1166_cm4.h:99
@ DMA4_DMA20_IRQn
Definition: MIMXRT1166_cm4.h:100
@ DMA7_DMA23_IRQn
Definition: MIMXRT1166_cm4.h:103
@ DMA8_DMA24_IRQn
Definition: MIMXRT1166_cm4.h:104
@ DMA6_DMA22_IRQn
Definition: MIMXRT1166_cm4.h:102
@ DMA11_DMA27_IRQn
Definition: MIMXRT1166_cm4.h:107
@ DMA2_DMA18_IRQn
Definition: MIMXRT1166_cm4.h:98
@ DMA9_DMA25_IRQn
Definition: MIMXRT1166_cm4.h:105
@ DMA12_DMA28_IRQn
Definition: MIMXRT1166_cm4.h:108
@ DMA1_DMA17_IRQn
Definition: MIMXRT1166_cm4.h:97

Interrupt vectors for the DMA peripheral type

◆ DMA_CHN_IRQS [3/3]

Interrupt vectors for the DMA peripheral type